1
Arm patches for rc3 : just a handful of bug fixes.
1
A last lot of bug fixes before rc0...
2
2
3
thanks
3
thanks
4
-- PMM
4
-- PMM
5
5
6
The following changes since commit 0d0275c31f00b71b49eb80bbdca2cfe244cf80fb:
6
7
7
The following changes since commit 4ecc984210ca1bf508a96a550ec8a93a5f833f6c:
8
Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2022-07-26 10:31:02 +0100)
8
9
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc3' into staging (2019-11-26 12:36:40 +0000)
10
9
11
are available in the Git repository at:
10
are available in the Git repository at:
12
11
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191126
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220726
14
13
15
for you to fetch changes up to 6a4ef4e5d1084ce41fafa7d470a644b0fd3d9317:
14
for you to fetch changes up to 5865d99fe88d8c8fa437c18c6b63fb2a8165634f:
16
15
17
target/arm: Honor HCR_EL2.TID3 trapping requirements (2019-11-26 13:55:37 +0000)
16
hw/display/bcm2835_fb: Fix framebuffer allocation address (2022-07-26 14:09:44 +0100)
18
17
19
----------------------------------------------------------------
18
----------------------------------------------------------------
20
target-arm queue:
19
target-arm queue:
21
* handle FTYPE flag correctly in v7M exception return
20
* Update Coverity component definitions
22
for v7M CPUs with an FPU (v8M CPUs were already correct)
21
* target/arm: Add MO_128 entry to pred_esz_masks[]
23
* versal: Add the CRP as unimplemented
22
* configure: Fix portability issues
24
* Fix ISR_EL1 tracking when executing at EL2
23
* hw/display/bcm2835_fb: Fix framebuffer allocation address
25
* Honor HCR_EL2.TID3 trapping requirements
26
24
27
----------------------------------------------------------------
25
----------------------------------------------------------------
28
Edgar E. Iglesias (1):
26
Alan Jian (1):
29
hw/arm: versal: Add the CRP as unimplemented
27
hw/display/bcm2835_fb: Fix framebuffer allocation address
30
28
31
Jean-Hugues Deschênes (1):
29
Peter Maydell (8):
32
target/arm: Fix handling of cortex-m FTYPE flag in EXCRET
30
scripts/coverity-scan/COMPONENTS.md: Add loongarch component
31
scripts/coverity-scan/COMPONENTS.md: Update slirp component info
32
target/arm: Add MO_128 entry to pred_esz_masks[]
33
configure: Add missing POSIX-required space
34
configure: Add braces to clarify intent of $emu[[:space:]]
35
configure: Don't use bash-specific string-replacement syntax
36
configure: Drop dead code attempting to use -msmall-data on alpha hosts
37
configure: Avoid '==' bashism
33
38
34
Marc Zyngier (2):
39
configure | 20 +++++++-------------
35
target/arm: Fix ISR_EL1 tracking when executing at EL2
40
target/arm/cpu.h | 2 +-
36
target/arm: Honor HCR_EL2.TID3 trapping requirements
41
hw/display/bcm2835_fb.c | 3 +--
37
42
target/arm/translate-sve.c | 5 +++--
38
include/hw/arm/xlnx-versal.h | 3 ++
43
scripts/coverity-scan/COMPONENTS.md | 7 +++++--
39
hw/arm/xlnx-versal.c | 2 ++
44
5 files changed, 17 insertions(+), 20 deletions(-)
40
target/arm/helper.c | 83 ++++++++++++++++++++++++++++++++++++++++++--
41
target/arm/m_helper.c | 7 ++--
42
4 files changed, 89 insertions(+), 6 deletions(-)
43
diff view generated by jsdifflib
New patch
1
Add the component regex for the new loongarch target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
5
Message-id: 20220718142310.16013-2-peter.maydell@linaro.org
6
---
7
scripts/coverity-scan/COMPONENTS.md | 3 +++
8
1 file changed, 3 insertions(+)
9
10
diff --git a/scripts/coverity-scan/COMPONENTS.md b/scripts/coverity-scan/COMPONENTS.md
11
index XXXXXXX..XXXXXXX 100644
12
--- a/scripts/coverity-scan/COMPONENTS.md
13
+++ b/scripts/coverity-scan/COMPONENTS.md
14
@@ -XXX,XX +XXX,XX @@ testlibs
15
16
tests
17
~ (/qemu)?(/tests/.*)
18
+
19
+loongarch
20
+ ~ (/qemu)?((/include)?/hw/(loongarch/.*|.*/loongarch.*)|/target/loongarch/.*)
21
--
22
2.25.1
diff view generated by jsdifflib
New patch
1
Update the regex for the slirp component now that it lives
2
solely inside /slirp/, and note that it should be ignored in
3
Coverity analysis (because it's a separate upstream project
4
now, and they run Coverity on it themselves).
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
8
Message-id: 20220718142310.16013-3-peter.maydell@linaro.org
9
---
10
scripts/coverity-scan/COMPONENTS.md | 4 ++--
11
1 file changed, 2 insertions(+), 2 deletions(-)
12
13
diff --git a/scripts/coverity-scan/COMPONENTS.md b/scripts/coverity-scan/COMPONENTS.md
14
index XXXXXXX..XXXXXXX 100644
15
--- a/scripts/coverity-scan/COMPONENTS.md
16
+++ b/scripts/coverity-scan/COMPONENTS.md
17
@@ -XXX,XX +XXX,XX @@ qemu-ga
18
scsi
19
~ (/qemu)?(/scsi/.*|/hw/scsi/.*|/include/hw/scsi/.*)
20
21
-slirp
22
- ~ (/qemu)?(/.*slirp.*)
23
+slirp (component should be ignored in analysis)
24
+ ~ (/qemu)?(/slirp/.*)
25
26
tcg
27
~ (/qemu)?(/accel/tcg/.*|/replay/.*|/(.*/)?softmmu.*)
28
--
29
2.25.1
diff view generated by jsdifflib
1
From: Marc Zyngier <maz@kernel.org>
1
In commit 7390e0e9ab8475, we added support for SME loads and stores.
2
Unlike SVE loads and stores, these include handling of 128-bit
3
elements. The SME load/store functions call down into the existing
4
sve_cont_ldst_elements() function, which uses the element size MO_*
5
value as an index into the pred_esz_masks[] array. Because this code
6
path now has to handle MO_128, we need to add an extra element to the
7
array.
2
8
3
HCR_EL2.TID3 mandates that access from EL1 to a long list of id
9
This bug was spotted by Coverity because it meant we were reading off
4
registers traps to EL2, and QEMU has so far ignored this requirement.
10
the end of the array.
5
11
6
This breaks (among other things) KVM guests that have PtrAuth enabled,
12
Resolves: Coverity CID 1490539, 1490541, 1490543, 1490544, 1490545,
7
while the hypervisor doesn't want to expose the feature to its guest.
13
1490546, 1490548, 1490549, 1490550, 1490551, 1490555, 1490557,
8
To achieve this, KVM traps the ID registers (ID_AA64ISAR1_EL1 in this
14
1490558, 1490560, 1490561, 1490563
9
case), and masks out the unsupported feature.
15
Fixes: 7390e0e9ab8475 ("target/arm: Implement SME LD1, ST1")
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Message-id: 20220718100144.3248052-1-peter.maydell@linaro.org
19
---
20
target/arm/cpu.h | 2 +-
21
target/arm/translate-sve.c | 5 +++--
22
2 files changed, 4 insertions(+), 3 deletions(-)
10
23
11
QEMU not honoring the trap request means that the guest observes
24
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
12
that the feature is present in the HW, starts using it, and dies
13
a horrible death when KVM injects an UNDEF, because the feature
14
*really* isn't supported.
15
16
Do the right thing by trapping to EL2 if HCR_EL2.TID3 is set.
17
18
Note that this change does not include trapping of the MVFR
19
registers from AArch32 (they are accessed via the VMRS
20
instruction and need to be handled in a different way).
21
22
Reported-by: Will Deacon <will@kernel.org>
23
Signed-off-by: Marc Zyngier <maz@kernel.org>
24
Tested-by: Will Deacon <will@kernel.org>
25
Message-id: 20191123115618.29230-1-maz@kernel.org
26
[PMM: added missing accessfn line for ID_AA4PFR2_EL1_RESERVED;
27
changed names of access functions to include _tid3]
28
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
---
31
target/arm/helper.c | 76 +++++++++++++++++++++++++++++++++++++++++++++
32
1 file changed, 76 insertions(+)
33
34
diff --git a/target/arm/helper.c b/target/arm/helper.c
35
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/helper.c
26
--- a/target/arm/cpu.h
37
+++ b/target/arm/helper.c
27
+++ b/target/arm/cpu.h
38
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = {
28
@@ -XXX,XX +XXX,XX @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
39
REGINFO_SENTINEL
29
}
30
31
/* Shared between translate-sve.c and sve_helper.c. */
32
-extern const uint64_t pred_esz_masks[4];
33
+extern const uint64_t pred_esz_masks[5];
34
35
/* Helper for the macros below, validating the argument type. */
36
static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
37
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/translate-sve.c
40
+++ b/target/arm/translate-sve.c
41
@@ -XXX,XX +XXX,XX @@ static void do_predtest(DisasContext *s, int dofs, int gofs, int words)
42
}
43
44
/* For each element size, the bits within a predicate word that are active. */
45
-const uint64_t pred_esz_masks[4] = {
46
+const uint64_t pred_esz_masks[5] = {
47
0xffffffffffffffffull, 0x5555555555555555ull,
48
- 0x1111111111111111ull, 0x0101010101010101ull
49
+ 0x1111111111111111ull, 0x0101010101010101ull,
50
+ 0x0001000100010001ull,
40
};
51
};
41
52
42
+static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
53
static bool trans_INVALID(DisasContext *s, arg_INVALID *a)
43
+ bool isread)
44
+{
45
+ if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) {
46
+ return CP_ACCESS_TRAP_EL2;
47
+ }
48
+
49
+ return CP_ACCESS_OK;
50
+}
51
+
52
+static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
53
+ bool isread)
54
+{
55
+ if (arm_feature(env, ARM_FEATURE_V8)) {
56
+ return access_aa64_tid3(env, ri, isread);
57
+ }
58
+
59
+ return CP_ACCESS_OK;
60
+}
61
+
62
void register_cp_regs_for_features(ARMCPU *cpu)
63
{
64
/* Register all the coprocessor registers based on feature bits */
65
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
66
{ .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
67
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
68
.access = PL1_R, .type = ARM_CP_CONST,
69
+ .accessfn = access_aa32_tid3,
70
.resetvalue = cpu->id_pfr0 },
71
/* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
72
* the value of the GIC field until after we define these regs.
73
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
74
{ .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
75
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
76
.access = PL1_R, .type = ARM_CP_NO_RAW,
77
+ .accessfn = access_aa32_tid3,
78
.readfn = id_pfr1_read,
79
.writefn = arm_cp_write_ignore },
80
{ .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
81
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
82
.access = PL1_R, .type = ARM_CP_CONST,
83
+ .accessfn = access_aa32_tid3,
84
.resetvalue = cpu->id_dfr0 },
85
{ .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
86
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
87
.access = PL1_R, .type = ARM_CP_CONST,
88
+ .accessfn = access_aa32_tid3,
89
.resetvalue = cpu->id_afr0 },
90
{ .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
91
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
92
.access = PL1_R, .type = ARM_CP_CONST,
93
+ .accessfn = access_aa32_tid3,
94
.resetvalue = cpu->id_mmfr0 },
95
{ .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
96
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
97
.access = PL1_R, .type = ARM_CP_CONST,
98
+ .accessfn = access_aa32_tid3,
99
.resetvalue = cpu->id_mmfr1 },
100
{ .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
101
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
102
.access = PL1_R, .type = ARM_CP_CONST,
103
+ .accessfn = access_aa32_tid3,
104
.resetvalue = cpu->id_mmfr2 },
105
{ .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
106
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
107
.access = PL1_R, .type = ARM_CP_CONST,
108
+ .accessfn = access_aa32_tid3,
109
.resetvalue = cpu->id_mmfr3 },
110
{ .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
111
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
112
.access = PL1_R, .type = ARM_CP_CONST,
113
+ .accessfn = access_aa32_tid3,
114
.resetvalue = cpu->isar.id_isar0 },
115
{ .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
116
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
117
.access = PL1_R, .type = ARM_CP_CONST,
118
+ .accessfn = access_aa32_tid3,
119
.resetvalue = cpu->isar.id_isar1 },
120
{ .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
121
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
122
.access = PL1_R, .type = ARM_CP_CONST,
123
+ .accessfn = access_aa32_tid3,
124
.resetvalue = cpu->isar.id_isar2 },
125
{ .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
126
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
127
.access = PL1_R, .type = ARM_CP_CONST,
128
+ .accessfn = access_aa32_tid3,
129
.resetvalue = cpu->isar.id_isar3 },
130
{ .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
131
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
132
.access = PL1_R, .type = ARM_CP_CONST,
133
+ .accessfn = access_aa32_tid3,
134
.resetvalue = cpu->isar.id_isar4 },
135
{ .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
136
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
137
.access = PL1_R, .type = ARM_CP_CONST,
138
+ .accessfn = access_aa32_tid3,
139
.resetvalue = cpu->isar.id_isar5 },
140
{ .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
141
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
142
.access = PL1_R, .type = ARM_CP_CONST,
143
+ .accessfn = access_aa32_tid3,
144
.resetvalue = cpu->id_mmfr4 },
145
{ .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
146
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
147
.access = PL1_R, .type = ARM_CP_CONST,
148
+ .accessfn = access_aa32_tid3,
149
.resetvalue = cpu->isar.id_isar6 },
150
REGINFO_SENTINEL
151
};
152
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
153
{ .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
154
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
155
.access = PL1_R, .type = ARM_CP_NO_RAW,
156
+ .accessfn = access_aa64_tid3,
157
.readfn = id_aa64pfr0_read,
158
.writefn = arm_cp_write_ignore },
159
{ .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
160
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
161
.access = PL1_R, .type = ARM_CP_CONST,
162
+ .accessfn = access_aa64_tid3,
163
.resetvalue = cpu->isar.id_aa64pfr1},
164
{ .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
165
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
166
.access = PL1_R, .type = ARM_CP_CONST,
167
+ .accessfn = access_aa64_tid3,
168
.resetvalue = 0 },
169
{ .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
170
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
171
.access = PL1_R, .type = ARM_CP_CONST,
172
+ .accessfn = access_aa64_tid3,
173
.resetvalue = 0 },
174
{ .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64,
175
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
176
.access = PL1_R, .type = ARM_CP_CONST,
177
+ .accessfn = access_aa64_tid3,
178
/* At present, only SVEver == 0 is defined anyway. */
179
.resetvalue = 0 },
180
{ .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
181
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
182
.access = PL1_R, .type = ARM_CP_CONST,
183
+ .accessfn = access_aa64_tid3,
184
.resetvalue = 0 },
185
{ .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
186
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
187
.access = PL1_R, .type = ARM_CP_CONST,
188
+ .accessfn = access_aa64_tid3,
189
.resetvalue = 0 },
190
{ .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
191
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
192
.access = PL1_R, .type = ARM_CP_CONST,
193
+ .accessfn = access_aa64_tid3,
194
.resetvalue = 0 },
195
{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
196
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
197
.access = PL1_R, .type = ARM_CP_CONST,
198
+ .accessfn = access_aa64_tid3,
199
.resetvalue = cpu->id_aa64dfr0 },
200
{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
201
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
202
.access = PL1_R, .type = ARM_CP_CONST,
203
+ .accessfn = access_aa64_tid3,
204
.resetvalue = cpu->id_aa64dfr1 },
205
{ .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
206
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
207
.access = PL1_R, .type = ARM_CP_CONST,
208
+ .accessfn = access_aa64_tid3,
209
.resetvalue = 0 },
210
{ .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
211
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
212
.access = PL1_R, .type = ARM_CP_CONST,
213
+ .accessfn = access_aa64_tid3,
214
.resetvalue = 0 },
215
{ .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
216
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
217
.access = PL1_R, .type = ARM_CP_CONST,
218
+ .accessfn = access_aa64_tid3,
219
.resetvalue = cpu->id_aa64afr0 },
220
{ .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
221
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
222
.access = PL1_R, .type = ARM_CP_CONST,
223
+ .accessfn = access_aa64_tid3,
224
.resetvalue = cpu->id_aa64afr1 },
225
{ .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
226
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
227
.access = PL1_R, .type = ARM_CP_CONST,
228
+ .accessfn = access_aa64_tid3,
229
.resetvalue = 0 },
230
{ .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
231
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
232
.access = PL1_R, .type = ARM_CP_CONST,
233
+ .accessfn = access_aa64_tid3,
234
.resetvalue = 0 },
235
{ .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
236
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
237
.access = PL1_R, .type = ARM_CP_CONST,
238
+ .accessfn = access_aa64_tid3,
239
.resetvalue = cpu->isar.id_aa64isar0 },
240
{ .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
241
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
242
.access = PL1_R, .type = ARM_CP_CONST,
243
+ .accessfn = access_aa64_tid3,
244
.resetvalue = cpu->isar.id_aa64isar1 },
245
{ .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
246
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
247
.access = PL1_R, .type = ARM_CP_CONST,
248
+ .accessfn = access_aa64_tid3,
249
.resetvalue = 0 },
250
{ .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
251
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
252
.access = PL1_R, .type = ARM_CP_CONST,
253
+ .accessfn = access_aa64_tid3,
254
.resetvalue = 0 },
255
{ .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
256
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
257
.access = PL1_R, .type = ARM_CP_CONST,
258
+ .accessfn = access_aa64_tid3,
259
.resetvalue = 0 },
260
{ .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
261
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
262
.access = PL1_R, .type = ARM_CP_CONST,
263
+ .accessfn = access_aa64_tid3,
264
.resetvalue = 0 },
265
{ .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
266
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
267
.access = PL1_R, .type = ARM_CP_CONST,
268
+ .accessfn = access_aa64_tid3,
269
.resetvalue = 0 },
270
{ .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
271
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
272
.access = PL1_R, .type = ARM_CP_CONST,
273
+ .accessfn = access_aa64_tid3,
274
.resetvalue = 0 },
275
{ .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
276
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
277
.access = PL1_R, .type = ARM_CP_CONST,
278
+ .accessfn = access_aa64_tid3,
279
.resetvalue = cpu->isar.id_aa64mmfr0 },
280
{ .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
281
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
282
.access = PL1_R, .type = ARM_CP_CONST,
283
+ .accessfn = access_aa64_tid3,
284
.resetvalue = cpu->isar.id_aa64mmfr1 },
285
{ .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
286
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
287
.access = PL1_R, .type = ARM_CP_CONST,
288
+ .accessfn = access_aa64_tid3,
289
.resetvalue = 0 },
290
{ .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
291
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
292
.access = PL1_R, .type = ARM_CP_CONST,
293
+ .accessfn = access_aa64_tid3,
294
.resetvalue = 0 },
295
{ .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
296
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
297
.access = PL1_R, .type = ARM_CP_CONST,
298
+ .accessfn = access_aa64_tid3,
299
.resetvalue = 0 },
300
{ .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
301
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
302
.access = PL1_R, .type = ARM_CP_CONST,
303
+ .accessfn = access_aa64_tid3,
304
.resetvalue = 0 },
305
{ .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
306
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
307
.access = PL1_R, .type = ARM_CP_CONST,
308
+ .accessfn = access_aa64_tid3,
309
.resetvalue = 0 },
310
{ .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
311
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
312
.access = PL1_R, .type = ARM_CP_CONST,
313
+ .accessfn = access_aa64_tid3,
314
.resetvalue = 0 },
315
{ .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
316
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
317
.access = PL1_R, .type = ARM_CP_CONST,
318
+ .accessfn = access_aa64_tid3,
319
.resetvalue = cpu->isar.mvfr0 },
320
{ .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
321
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
322
.access = PL1_R, .type = ARM_CP_CONST,
323
+ .accessfn = access_aa64_tid3,
324
.resetvalue = cpu->isar.mvfr1 },
325
{ .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
326
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
327
.access = PL1_R, .type = ARM_CP_CONST,
328
+ .accessfn = access_aa64_tid3,
329
.resetvalue = cpu->isar.mvfr2 },
330
{ .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
331
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
332
.access = PL1_R, .type = ARM_CP_CONST,
333
+ .accessfn = access_aa64_tid3,
334
.resetvalue = 0 },
335
{ .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
336
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
337
.access = PL1_R, .type = ARM_CP_CONST,
338
+ .accessfn = access_aa64_tid3,
339
.resetvalue = 0 },
340
{ .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
341
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
342
.access = PL1_R, .type = ARM_CP_CONST,
343
+ .accessfn = access_aa64_tid3,
344
.resetvalue = 0 },
345
{ .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
346
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
347
.access = PL1_R, .type = ARM_CP_CONST,
348
+ .accessfn = access_aa64_tid3,
349
.resetvalue = 0 },
350
{ .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
351
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
352
.access = PL1_R, .type = ARM_CP_CONST,
353
+ .accessfn = access_aa64_tid3,
354
.resetvalue = 0 },
355
{ .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
356
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
357
--
54
--
358
2.20.1
55
2.25.1
359
360
diff view generated by jsdifflib
New patch
1
In commit 7d7dbf9dc15be6e1 we added a line to the configure script
2
which is not valid POSIX shell syntax, because it is missing a space
3
after a '!' character. shellcheck diagnoses this:
1
4
5
if !(GIT="$git" "$source_path/scripts/git-submodule.sh" "$git_submodules_action" "$git_submodules"); then
6
^-- SC1035: You are missing a required space after the !.
7
8
and the OpenBSD shell will not correctly handle this without the space.
9
10
Fixes: 7d7dbf9dc15be6e1 ("configure: replace --enable/disable-git-update with --with-git-submodules")
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Thomas Huth <thuth@redhat.com>
13
Tested-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
14
Message-id: 20220720152631.450903-2-peter.maydell@linaro.org
15
---
16
configure | 2 +-
17
1 file changed, 1 insertion(+), 1 deletion(-)
18
19
diff --git a/configure b/configure
20
index XXXXXXX..XXXXXXX 100755
21
--- a/configure
22
+++ b/configure
23
@@ -XXX,XX +XXX,XX @@ else
24
cxx=
25
fi
26
27
-if !(GIT="$git" "$source_path/scripts/git-submodule.sh" "$git_submodules_action" "$git_submodules"); then
28
+if ! (GIT="$git" "$source_path/scripts/git-submodule.sh" "$git_submodules_action" "$git_submodules"); then
29
exit 1
30
fi
31
32
--
33
2.25.1
diff view generated by jsdifflib
New patch
1
In shell script syntax, $var[something] is not special for variable
2
expansion: $var is expanded. However, as it can look as if it were
3
intended to be an array element access (the correct syntax for which
4
is ${var[something]}), shellcheck recommends using explicit braces
5
around ${var} to clarify the intended expansion.
1
6
7
This fixes the warning:
8
9
In ./configure line 2346:
10
if "$target_ld" -verbose 2>&1 | grep -q "^[[:space:]]*$emu[[:space:]]*$"; then
11
^-- SC1087: Use braces when expanding arrays, e.g. ${array[idx]} (or ${var}[.. to quiet).
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Thomas Huth <thuth@redhat.com>
15
Message-id: 20220720152631.450903-3-peter.maydell@linaro.org
16
---
17
configure | 2 +-
18
1 file changed, 1 insertion(+), 1 deletion(-)
19
20
diff --git a/configure b/configure
21
index XXXXXXX..XXXXXXX 100755
22
--- a/configure
23
+++ b/configure
24
@@ -XXX,XX +XXX,XX @@ if test -n "$target_cc" &&
25
# emulation. Linux and OpenBSD/amd64 use 'elf_i386'; FreeBSD uses the _fbsd
26
# variant; OpenBSD/i386 uses the _obsd variant; and Windows uses i386pe.
27
for emu in elf_i386 elf_i386_fbsd elf_i386_obsd i386pe; do
28
- if "$target_ld" -verbose 2>&1 | grep -q "^[[:space:]]*$emu[[:space:]]*$"; then
29
+ if "$target_ld" -verbose 2>&1 | grep -q "^[[:space:]]*${emu}[[:space:]]*$"; then
30
ld_i386_emulation="$emu"
31
break
32
fi
33
--
34
2.25.1
diff view generated by jsdifflib
New patch
1
The variable string-replacement syntax ${var/old/new} is a bashism
2
(though it is also supported by some other shells), and for instance
3
does not work with the NetBSD /bin/sh, which complains:
4
../src/configure: 687: Syntax error: Bad substitution
1
5
6
Replace it with a more portable sed-based approach, similar to
7
what we already do in quote_sh().
8
9
Note that shellcheck also diagnoses this:
10
11
In ./configure line 687:
12
e=${e/'\'/'\\'}
13
^-----------^ SC2039: In POSIX sh, string replacement is undefined.
14
^-- SC1003: Want to escape a single quote? echo 'This is how it'\''s done'.
15
^-- SC1003: Want to escape a single quote? echo 'This is how it'\''s done'.
16
17
In ./configure line 688:
18
e=${e/\"/'\"'}
19
^----------^ SC2039: In POSIX sh, string replacement is undefined.
20
21
Fixes: 8154f5e64b0cf ("meson: Prefix each element of firmware path")
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Tested-by: Thomas Huth <thuth@redhat.com>
24
Message-id: 20220720152631.450903-4-peter.maydell@linaro.org
25
---
26
configure | 7 ++++---
27
1 file changed, 4 insertions(+), 3 deletions(-)
28
29
diff --git a/configure b/configure
30
index XXXXXXX..XXXXXXX 100755
31
--- a/configure
32
+++ b/configure
33
@@ -XXX,XX +XXX,XX @@ meson_option_build_array() {
34
IFS=:
35
fi
36
for e in $1; do
37
- e=${e/'\'/'\\'}
38
- e=${e/\"/'\"'}
39
- printf '"""%s""",' "$e"
40
+ printf '"""'
41
+ # backslash escape any '\' and '"' characters
42
+ printf "%s" "$e" | sed -e 's/\([\"]\)/\\\1/g'
43
+ printf '""",'
44
done)
45
printf ']\n'
46
}
47
--
48
2.25.1
diff view generated by jsdifflib
1
From: Marc Zyngier <maz@kernel.org>
1
In commit 823eb013452e93d we moved the setting of ARCH from configure
2
to meson.build, but we accidentally left behind one attempt to use
3
$ARCH in configure, which was trying to add -msmall-data to the
4
compiler flags on Alpha hosts. Since ARCH is now never set, the test
5
always fails and we never add the flag.
2
6
3
The ARMv8 ARM states when executing at EL2, EL3 or Secure EL1,
7
There isn't actually any need to use this compiler flag on Alpha:
4
ISR_EL1 shows the pending status of the physical IRQ, FIQ, or
8
the original intent was that it would allow us to simplify our TCG
5
SError interrupts.
9
codegen on that platform, but we never actually made the TCG changes
10
that would rely on -msmall-data.
6
11
7
Unfortunately, QEMU's implementation only considers the HCR_EL2
12
Drop the effectively-dead code from configure, as we don't need it.
8
bits, and ignores the current exception level. This means a hypervisor
9
trying to look at its own interrupt state actually sees the guest
10
state, which is unexpected and breaks KVM as of Linux 5.3.
11
13
12
Instead, check for the running EL and return the physical bits
14
This was spotted by shellcheck:
13
if not running in a virtualized context.
14
15
15
Fixes: 636540e9c40b
16
In ./configure line 2254:
16
Cc: qemu-stable@nongnu.org
17
case "$ARCH" in
17
Reported-by: Quentin Perret <qperret@google.com>
18
^---^ SC2153: Possible misspelling: ARCH may not be assigned, but arch is.
18
Signed-off-by: Marc Zyngier <maz@kernel.org>
19
19
Message-id: 20191122135833.28953-1-maz@kernel.org
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
21
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Reviewed-by: Thomas Huth <thuth@redhat.com>
22
Message-id: 20220720152631.450903-5-peter.maydell@linaro.org
23
---
23
---
24
target/arm/helper.c | 7 +++++--
24
configure | 7 -------
25
1 file changed, 5 insertions(+), 2 deletions(-)
25
1 file changed, 7 deletions(-)
26
26
27
diff --git a/target/arm/helper.c b/target/arm/helper.c
27
diff --git a/configure b/configure
28
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100755
29
--- a/target/arm/helper.c
29
--- a/configure
30
+++ b/target/arm/helper.c
30
+++ b/configure
31
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
31
@@ -XXX,XX +XXX,XX @@ if test "$fortify_source" = "yes" ; then
32
CPUState *cs = env_cpu(env);
32
QEMU_CFLAGS="-U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 $QEMU_CFLAGS"
33
uint64_t hcr_el2 = arm_hcr_el2_eff(env);
33
fi
34
uint64_t ret = 0;
34
35
+ bool allow_virt = (arm_current_el(env) == 1 &&
35
-case "$ARCH" in
36
+ (!arm_is_secure_below_el3(env) ||
36
-alpha)
37
+ (env->cp15.scr_el3 & SCR_EEL2)));
37
- # Ensure there's only a single GP
38
38
- QEMU_CFLAGS="-msmall-data $QEMU_CFLAGS"
39
- if (hcr_el2 & HCR_IMO) {
39
-;;
40
+ if (allow_virt && (hcr_el2 & HCR_IMO)) {
40
-esac
41
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
41
-
42
ret |= CPSR_I;
42
if test "$have_asan" = "yes"; then
43
}
43
QEMU_CFLAGS="-fsanitize=address $QEMU_CFLAGS"
44
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
44
QEMU_LDFLAGS="-fsanitize=address $QEMU_LDFLAGS"
45
}
46
}
47
48
- if (hcr_el2 & HCR_FMO) {
49
+ if (allow_virt && (hcr_el2 & HCR_FMO)) {
50
if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
51
ret |= CPSR_F;
52
}
53
--
45
--
54
2.20.1
46
2.25.1
55
56
diff view generated by jsdifflib
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
The '==' operator to test is a bashism; the standard way to copmare
2
strings is '='. This causes dash to complain:
2
3
3
Add the CRP as unimplemented thus avoiding bus errors when
4
../../configure: 681: test: linux: unexpected operator
4
guests access these registers.
5
5
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
Message-id: 20191115154734.26449-2-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Thomas Huth <thuth@redhat.com>
8
Message-id: 20220720152631.450903-6-peter.maydell@linaro.org
11
---
9
---
12
include/hw/arm/xlnx-versal.h | 3 +++
10
configure | 2 +-
13
hw/arm/xlnx-versal.c | 2 ++
11
1 file changed, 1 insertion(+), 1 deletion(-)
14
2 files changed, 5 insertions(+)
15
12
16
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
13
diff --git a/configure b/configure
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100755
18
--- a/include/hw/arm/xlnx-versal.h
15
--- a/configure
19
+++ b/include/hw/arm/xlnx-versal.h
16
+++ b/configure
20
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
17
@@ -XXX,XX +XXX,XX @@ werror=""
21
#define MM_IOU_SCNTRS_SIZE 0x10000
18
22
#define MM_FPD_CRF 0xfd1a0000U
19
meson_option_build_array() {
23
#define MM_FPD_CRF_SIZE 0x140000
20
printf '['
24
+
21
- (if test "$targetos" == windows; then
25
+#define MM_PMC_CRP 0xf1260000U
22
+ (if test "$targetos" = windows; then
26
+#define MM_PMC_CRP_SIZE 0x10000
23
IFS=\;
27
#endif
24
else
28
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
25
IFS=:
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/arm/xlnx-versal.c
31
+++ b/hw/arm/xlnx-versal.c
32
@@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s)
33
MM_CRL, MM_CRL_SIZE);
34
versal_unimp_area(s, "crf", &s->mr_ps,
35
MM_FPD_CRF, MM_FPD_CRF_SIZE);
36
+ versal_unimp_area(s, "crp", &s->mr_ps,
37
+ MM_PMC_CRP, MM_PMC_CRP_SIZE);
38
versal_unimp_area(s, "iou-scntr", &s->mr_ps,
39
MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
40
versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,
41
--
26
--
42
2.20.1
27
2.25.1
43
44
diff view generated by jsdifflib
1
From: Jean-Hugues Deschênes <Jean-Hugues.Deschenes@ossiaco.com>
1
From: Alan Jian <alanjian85@gmail.com>
2
2
3
According to the PushStack() pseudocode in the armv7m RM,
3
This patch fixes the dedicated framebuffer mailbox interface by
4
bit 4 of the LR should be set to NOT(CONTROL.PFCA) when
4
removing an unneeded offset. This means that we pick the framebuffer
5
an FPU is present. Current implementation is doing it for
5
address in the same way that we do if the guest code uses the buffer
6
armv8, but not for armv7. This patch makes the existing
6
allocate mechanism of the bcm2835_property interface (case
7
logic applicable to both code paths.
7
0x00040001: /* Allocate buffer */ in bcm2835_property.c).
8
8
9
Signed-off-by: Jean-Hugues Deschenes <jean-hugues.deschenes@ossiaco.com>
9
The documentation of this mailbox interface doesn't say anything
10
about using parts of the request buffer address to affect the
11
chosen framebuffer address:
12
https://github.com/raspberrypi/firmware/wiki/Mailbox-framebuffer-interface
13
14
Some baremetal applications like the Screen01/Screen02 examples from
15
Baking Pi tutorial[1] didn't work before this patch.
16
17
[1] https://www.cl.cam.ac.uk/projects/raspberrypi/tutorials/os/screen01.html
18
19
Signed-off-by: Alan Jian <alanjian85@outlook.com>
20
Message-id: 20220725145838.8412-1-alanjian85@outlook.com
21
[PMM: tweaked commit message]
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
22
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
24
---
13
target/arm/m_helper.c | 7 +++----
25
hw/display/bcm2835_fb.c | 3 +--
14
1 file changed, 3 insertions(+), 4 deletions(-)
26
1 file changed, 1 insertion(+), 2 deletions(-)
15
27
16
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
28
diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c
17
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/m_helper.c
30
--- a/hw/display/bcm2835_fb.c
19
+++ b/target/arm/m_helper.c
31
+++ b/hw/display/bcm2835_fb.c
20
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
32
@@ -XXX,XX +XXX,XX @@ static void bcm2835_fb_mbox_push(BCM2835FBState *s, uint32_t value)
21
if (env->v7m.secure) {
33
newconf.xoffset = ldl_le_phys(&s->dma_as, value + 24);
22
lr |= R_V7M_EXCRET_S_MASK;
34
newconf.yoffset = ldl_le_phys(&s->dma_as, value + 28);
23
}
35
24
- if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
36
- newconf.base = s->vcram_base | (value & 0xc0000000);
25
- lr |= R_V7M_EXCRET_FTYPE_MASK;
37
- newconf.base += BCM2835_FB_OFFSET;
26
- }
38
+ newconf.base = s->vcram_base + BCM2835_FB_OFFSET;
27
} else {
39
28
lr = R_V7M_EXCRET_RES1_MASK |
40
/* Copy fields which we don't want to change from the existing config */
29
R_V7M_EXCRET_S_MASK |
41
newconf.pixo = s->config.pixo;
30
R_V7M_EXCRET_DCRS_MASK |
31
- R_V7M_EXCRET_FTYPE_MASK |
32
R_V7M_EXCRET_ES_MASK;
33
if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) {
34
lr |= R_V7M_EXCRET_SPSEL_MASK;
35
}
36
}
37
+ if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
38
+ lr |= R_V7M_EXCRET_FTYPE_MASK;
39
+ }
40
if (!arm_v7m_is_handler_mode(env)) {
41
lr |= R_V7M_EXCRET_MODE_MASK;
42
}
43
--
42
--
44
2.20.1
43
2.25.1
45
46
diff view generated by jsdifflib