arm queue: big stuff here is my MVE codegen optimisation,

and Alex's Apple Silicon hvf support.

Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20210916' into staging (2021-09-19 18:53:29 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210920

for you to fetch changes up to 1dc5a60bfe406bc1122d68cbdefda38d23134b27:

target/arm: Optimize MVE 1op-immediate insns (2021-09-20 14:18:01 +0100)

* Optimize codegen for MVE when predication not active

* hvf: Add Apple Silicon support

* hw/intc: Set GIC maintenance interrupt level to only 0 or 1

* Fix mishandling of MVE FPSCR.LTPSIZE reset for usermode emulator

* elf2dmp: Fix coverity nits

Alexander Graf (7):

arm: Move PMC register definitions to internals.h

hvf: Add execute to dirty log permission bitmap

hvf: Introduce hvf_arch_init() callback

hvf: Add Apple Silicon support

hvf: arm: Implement PSCI handling

arm: Add Hypervisor.framework build target

hvf: arm: Add rudimentary PMC support

Peter Collingbourne (1):

arm/hvf: Add a WFI handler

Peter Maydell (18):

elf2dmp: Check curl_easy_setopt() return value

elf2dmp: Fail cleanly if PDB file specifies zero block_size

target/arm: Don't skip M-profile reset entirely in user mode

target/arm: Always clear exclusive monitor on reset

target/arm: Consolidate ifdef blocks in reset

hvf: arm: Implement -cpu host

target/arm: Avoid goto_tb if we're trying to exit to the main loop

target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration

target/arm: Add TB flag for "MVE insns not predicated"

target/arm: Optimize MVE logic ops

target/arm: Optimize MVE arithmetic ops

target/arm: Optimize MVE VNEG, VABS

target/arm: Optimize MVE VDUP

target/arm: Optimize MVE VMVN

target/arm: Optimize MVE VSHL, VSHR immediate forms

target/arm: Optimize MVE VSHLL and VMOVL

target/arm: Optimize MVE VSLI and VSRI

target/arm: Optimize MVE 1op-immediate insns

Shashi Mallela (1):

hw/intc: Set GIC maintenance interrupt level to only 0 or 1

From: Shashi Mallela <shashi.mallela@linaro.org>

During sbsa acs level 3 testing, it is seen that the GIC maintenance

interrupts are not triggered and the related test cases fail. This

is because we were incorrectly passing the value of the MISR register

(from maintenance_interrupt_state()) to qemu_set_irq() as the level

argument, whereas the device on the other end of this irq line

expects a 0/1 value.

Fix the logic to pass a 0/1 level indication, rather than a

0/not-0 value.

Fixes: c5fc89b36c0 ("hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()")

Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20210915205809.59068-1-shashi.mallela@linaro.org

[PMM: tweaked commit message; collapsed nested if()s into one]

hw/intc/arm_gicv3_cpuif.c | 5 +++--

1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c

--- a/hw/intc/arm_gicv3_cpuif.c

+++ b/hw/intc/arm_gicv3_cpuif.c

@@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs)

- if (cs->ich_hcr_el2 & ICH_HCR_EL2_EN) {

- maintlevel = maintenance_interrupt_state(cs);

+ if ((cs->ich_hcr_el2 & ICH_HCR_EL2_EN) &&

+ maintenance_interrupt_state(cs) != 0) {

+ maintlevel = 1;

From: Alexander Graf <agraf@csgraf.de>

We will need PMC register definitions in accel specific code later.

Move all constant definitions to common arm headers so we can reuse

them.

Signed-off-by: Alexander Graf <agraf@csgraf.de>

Message-id: 20210916155404.86958-2-agraf@csgraf.de

target/arm/internals.h | 44 ++++++++++++++++++++++++++++++++++++++++++

target/arm/helper.c | 44 ------------------------------------------

2 files changed, 44 insertions(+), 44 deletions(-)

@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {

REGINFO_SENTINEL

};

-/* Definitions for the PMU registers */

-#define PMCRN_MASK 0xf800

-#define PMCRN_SHIFT 11

-#define PMCRLC 0x40

-#define PMCRDP 0x20

-#define PMCRX 0x10

-#define PMCRD 0x8

-#define PMCRC 0x4

-#define PMCRP 0x2

-#define PMCRE 0x1

-/*

- * Mask of PMCR bits writeable by guest (not including WO bits like C, P,

- * which can be written as 1 to trigger behaviour but which stay RAZ).

- */

-#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)

-

-#define PMXEVTYPER_P 0x80000000

-#define PMXEVTYPER_U 0x40000000

-#define PMXEVTYPER_NSK 0x20000000

-#define PMXEVTYPER_NSU 0x10000000

-#define PMXEVTYPER_NSH 0x08000000

-#define PMXEVTYPER_M 0x04000000

-#define PMXEVTYPER_MT 0x02000000

-#define PMXEVTYPER_EVTCOUNT 0x0000ffff

-#define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \

- PMXEVTYPER_NSU | PMXEVTYPER_NSH | \

- PMXEVTYPER_M | PMXEVTYPER_MT | \

- PMXEVTYPER_EVTCOUNT)

-

-#define PMCCFILTR 0xf8000000

-#define PMCCFILTR_M PMXEVTYPER_M

-#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)

-

-static inline uint32_t pmu_num_counters(CPUARMState *env)

-{

- return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;

-}

-

-/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */

-static inline uint64_t pmu_counter_mask(CPUARMState *env)

-{

- return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);

-}

-

typedef struct pm_event {

uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */

/* If the event is supported on this CPU (used to generate PMCEID[01]) */