[PULL 0/4] target-arm queue
[PULL 00/12] target-arm queue
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Arm patches for rc3 : just a handful of bug fixes.
1
Last few changes before rc0: a few bug fixes, but mostly
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docs stuff.
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3
3
thanks
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-- PMM
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-- PMM
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5
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The following changes since commit a97fca4ceb9d9b10aa8b582e817a5ee6c42ffbaf:
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The following changes since commit 4ecc984210ca1bf508a96a550ec8a93a5f833f6c:
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Merge remote-tracking branch 'remotes/mst/tags/for_upstream3' into staging (2021-07-16 16:34:42 +0100)
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Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc3' into staging (2019-11-26 12:36:40 +0000)
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9
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191126
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210718
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13
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for you to fetch changes up to 6a4ef4e5d1084ce41fafa7d470a644b0fd3d9317:
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for you to fetch changes up to 8fe612a183dec4c63afdc57537079bc742d024ca:
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target/arm: Honor HCR_EL2.TID3 trapping requirements (2019-11-26 13:55:37 +0000)
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target/arm: Remove duplicate 'plus1' function from Neon and SVE decode (2021-07-18 10:59:47 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
19
target-arm queue:
21
* handle FTYPE flag correctly in v7M exception return
20
* Remove duplicate 'plus1' function from Neon and SVE decode
22
for v7M CPUs with an FPU (v8M CPUs were already correct)
21
* Fix offsets for TTBCR for big-endian hosts
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* versal: Add the CRP as unimplemented
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* docs: fix copyright date
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* Fix ISR_EL1 tracking when executing at EL2
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* docs: add license/version info to HTML footers
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* Honor HCR_EL2.TID3 trapping requirements
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* docs: add an About section
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* docs: document some more arm boards
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26
27
----------------------------------------------------------------
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----------------------------------------------------------------
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Edgar E. Iglesias (1):
28
Peter Maydell (11):
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hw/arm: versal: Add the CRP as unimplemented
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docs: Fix documentation Copyright date
30
docs: Stop calling the top level subsections of our manual 'manuals'
31
docs: Remove "Contents:" lines from top-level subsections
32
docs: Move deprecation, build and license info out of system/
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docs: Add some actual About text to about/index.rst
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docs: Add license note to the HTML page footer
35
docs: Add QEMU version information to HTML footer
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docs: Add skeletal documentation of cubieboard
37
docs: Add skeletal documentation of the emcraft-sf2
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docs: Add skeletal documentation of highbank and midway
39
target/arm: Remove duplicate 'plus1' function from Neon and SVE decode
30
40
31
Jean-Hugues Deschênes (1):
41
Richard Henderson (1):
32
target/arm: Fix handling of cortex-m FTYPE flag in EXCRET
42
target/arm: Fix offsets for TTBCR
33
43
34
Marc Zyngier (2):
44
docs/_templates/footer.html | 14 ++++++++++++++
35
target/arm: Fix ISR_EL1 tracking when executing at EL2
45
docs/{system => about}/build-platforms.rst | 0
36
target/arm: Honor HCR_EL2.TID3 trapping requirements
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docs/{system => about}/deprecated.rst | 0
47
docs/about/index.rst | 27 +++++++++++++++++++++++++++
48
docs/{system => about}/license.rst | 0
49
docs/{system => about}/removed-features.rst | 0
50
docs/conf.py | 2 +-
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docs/devel/index.rst | 7 +------
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docs/index.rst | 1 +
53
docs/interop/index.rst | 9 ++-------
54
docs/meson.build | 3 ++-
55
docs/specs/index.rst | 7 ++-----
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docs/system/arm/cubieboard.rst | 16 ++++++++++++++++
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docs/system/arm/emcraft-sf2.rst | 15 +++++++++++++++
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docs/system/arm/highbank.rst | 19 +++++++++++++++++++
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docs/system/index.rst | 11 +----------
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docs/system/target-arm.rst | 3 +++
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docs/tools/index.rst | 7 ++-----
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docs/user/index.rst | 7 +------
63
target/arm/neon-ls.decode | 4 ++--
64
target/arm/neon-shared.decode | 2 +-
65
target/arm/sve.decode | 2 +-
66
target/arm/helper.c | 11 +++++++----
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target/arm/translate-neon.c | 5 -----
68
target/arm/translate-sve.c | 5 -----
69
MAINTAINERS | 4 ++++
70
26 files changed, 122 insertions(+), 59 deletions(-)
71
create mode 100644 docs/_templates/footer.html
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rename docs/{system => about}/build-platforms.rst (100%)
73
rename docs/{system => about}/deprecated.rst (100%)
74
create mode 100644 docs/about/index.rst
75
rename docs/{system => about}/license.rst (100%)
76
rename docs/{system => about}/removed-features.rst (100%)
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create mode 100644 docs/system/arm/cubieboard.rst
78
create mode 100644 docs/system/arm/emcraft-sf2.rst
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create mode 100644 docs/system/arm/highbank.rst
37
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include/hw/arm/xlnx-versal.h | 3 ++
39
hw/arm/xlnx-versal.c | 2 ++
40
target/arm/helper.c | 83 ++++++++++++++++++++++++++++++++++++++++++--
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target/arm/m_helper.c | 7 ++--
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4 files changed, 89 insertions(+), 6 deletions(-)
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diff view generated by jsdifflib
[PULL 4/4] target/arm: Honor HCR_EL2.TID3 trapping requirements
[PULL 01/12] target/arm: Fix offsets for TTBCR
1
From: Marc Zyngier <maz@kernel.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
HCR_EL2.TID3 mandates that access from EL1 to a long list of id
3
The functions vmsa_ttbcr_write and vmsa_ttbcr_raw_write expect
4
registers traps to EL2, and QEMU has so far ignored this requirement.
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the offset to be for the complete TCR structure, not the offset
5
to the low 32-bits of a uint64_t. Using offsetoflow32 in this
6
case breaks big-endian hosts.
5
7
6
This breaks (among other things) KVM guests that have PtrAuth enabled,
8
For TTBCR2, we do want the high 32-bits of a uint64_t.
7
while the hypervisor doesn't want to expose the feature to its guest.
9
Use cp15.tcr_el[*].raw_tcr as the offsetofhigh32 argument to
8
To achieve this, KVM traps the ID registers (ID_AA64ISAR1_EL1 in this
10
clarify this.
9
case), and masks out the unsupported feature.
10
11
11
QEMU not honoring the trap request means that the guest observes
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Buglink: https://gitlab.com/qemu-project/qemu/-/issues/187
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that the feature is present in the HW, starts using it, and dies
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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a horrible death when KVM injects an UNDEF, because the feature
14
Message-id: 20210709230621.938821-2-richard.henderson@linaro.org
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*really* isn't supported.
15
16
Do the right thing by trapping to EL2 if HCR_EL2.TID3 is set.
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18
Note that this change does not include trapping of the MVFR
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registers from AArch32 (they are accessed via the VMRS
20
instruction and need to be handled in a different way).
21
22
Reported-by: Will Deacon <will@kernel.org>
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Signed-off-by: Marc Zyngier <maz@kernel.org>
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Tested-by: Will Deacon <will@kernel.org>
25
Message-id: 20191123115618.29230-1-maz@kernel.org
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[PMM: added missing accessfn line for ID_AA4PFR2_EL1_RESERVED;
27
changed names of access functions to include _tid3]
28
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
---
17
---
31
target/arm/helper.c | 76 +++++++++++++++++++++++++++++++++++++++++++++
18
target/arm/helper.c | 11 +++++++----
32
1 file changed, 76 insertions(+)
19
1 file changed, 7 insertions(+), 4 deletions(-)
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20
34
diff --git a/target/arm/helper.c b/target/arm/helper.c
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diff --git a/target/arm/helper.c b/target/arm/helper.c
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index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/helper.c
23
--- a/target/arm/helper.c
37
+++ b/target/arm/helper.c
24
+++ b/target/arm/helper.c
38
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = {
25
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
26
.access = PL1_RW, .accessfn = access_tvm_trvm,
27
.type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
28
.raw_writefn = vmsa_ttbcr_raw_write,
29
- .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
30
- offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
31
+ /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */
32
+ .bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]),
33
+ offsetof(CPUARMState, cp15.tcr_el[1])} },
39
REGINFO_SENTINEL
34
REGINFO_SENTINEL
40
};
35
};
41
36
42
+static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
37
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ttbcr2_reginfo = {
43
+ bool isread)
38
.name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3,
44
+{
39
.access = PL1_RW, .accessfn = access_tvm_trvm,
45
+ if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) {
40
.type = ARM_CP_ALIAS,
46
+ return CP_ACCESS_TRAP_EL2;
41
- .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]),
47
+ }
42
- offsetofhigh32(CPUARMState, cp15.tcr_el[1]) },
48
+
43
+ .bank_fieldoffsets = {
49
+ return CP_ACCESS_OK;
44
+ offsetofhigh32(CPUARMState, cp15.tcr_el[3].raw_tcr),
50
+}
45
+ offsetofhigh32(CPUARMState, cp15.tcr_el[1].raw_tcr),
51
+
46
+ },
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+static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
47
};
53
+ bool isread)
48
54
+{
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static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
55
+ if (arm_feature(env, ARM_FEATURE_V8)) {
56
+ return access_aa64_tid3(env, ri, isread);
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+ }
58
+
59
+ return CP_ACCESS_OK;
60
+}
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+
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void register_cp_regs_for_features(ARMCPU *cpu)
63
{
64
/* Register all the coprocessor registers based on feature bits */
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@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
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{ .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
67
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
68
.access = PL1_R, .type = ARM_CP_CONST,
69
+ .accessfn = access_aa32_tid3,
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.resetvalue = cpu->id_pfr0 },
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/* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
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* the value of the GIC field until after we define these regs.
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@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
74
{ .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
75
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
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.access = PL1_R, .type = ARM_CP_NO_RAW,
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+ .accessfn = access_aa32_tid3,
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.readfn = id_pfr1_read,
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.writefn = arm_cp_write_ignore },
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{ .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
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.access = PL1_R, .type = ARM_CP_CONST,
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+ .accessfn = access_aa32_tid3,
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.resetvalue = cpu->id_dfr0 },
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{ .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
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.access = PL1_R, .type = ARM_CP_CONST,
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+ .accessfn = access_aa32_tid3,
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.resetvalue = cpu->id_afr0 },
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{ .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
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.access = PL1_R, .type = ARM_CP_CONST,
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+ .accessfn = access_aa32_tid3,
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.resetvalue = cpu->id_mmfr0 },
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{ .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
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.access = PL1_R, .type = ARM_CP_CONST,
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+ .accessfn = access_aa32_tid3,
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.resetvalue = cpu->id_mmfr1 },
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{ .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
101
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
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.access = PL1_R, .type = ARM_CP_CONST,
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+ .accessfn = access_aa32_tid3,
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.resetvalue = cpu->id_mmfr2 },
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{ .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
106
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
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.access = PL1_R, .type = ARM_CP_CONST,
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+ .accessfn = access_aa32_tid3,
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.resetvalue = cpu->id_mmfr3 },
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{ .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
111
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
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.access = PL1_R, .type = ARM_CP_CONST,
113
+ .accessfn = access_aa32_tid3,
114
.resetvalue = cpu->isar.id_isar0 },
115
{ .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
116
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
117
.access = PL1_R, .type = ARM_CP_CONST,
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+ .accessfn = access_aa32_tid3,
119
.resetvalue = cpu->isar.id_isar1 },
120
{ .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
121
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
122
.access = PL1_R, .type = ARM_CP_CONST,
123
+ .accessfn = access_aa32_tid3,
124
.resetvalue = cpu->isar.id_isar2 },
125
{ .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
126
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
127
.access = PL1_R, .type = ARM_CP_CONST,
128
+ .accessfn = access_aa32_tid3,
129
.resetvalue = cpu->isar.id_isar3 },
130
{ .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
131
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
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.access = PL1_R, .type = ARM_CP_CONST,
133
+ .accessfn = access_aa32_tid3,
134
.resetvalue = cpu->isar.id_isar4 },
135
{ .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
136
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
137
.access = PL1_R, .type = ARM_CP_CONST,
138
+ .accessfn = access_aa32_tid3,
139
.resetvalue = cpu->isar.id_isar5 },
140
{ .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
141
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
142
.access = PL1_R, .type = ARM_CP_CONST,
143
+ .accessfn = access_aa32_tid3,
144
.resetvalue = cpu->id_mmfr4 },
145
{ .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
146
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
147
.access = PL1_R, .type = ARM_CP_CONST,
148
+ .accessfn = access_aa32_tid3,
149
.resetvalue = cpu->isar.id_isar6 },
150
REGINFO_SENTINEL
151
};
152
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
153
{ .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
154
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
155
.access = PL1_R, .type = ARM_CP_NO_RAW,
156
+ .accessfn = access_aa64_tid3,
157
.readfn = id_aa64pfr0_read,
158
.writefn = arm_cp_write_ignore },
159
{ .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
160
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
161
.access = PL1_R, .type = ARM_CP_CONST,
162
+ .accessfn = access_aa64_tid3,
163
.resetvalue = cpu->isar.id_aa64pfr1},
164
{ .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
165
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
166
.access = PL1_R, .type = ARM_CP_CONST,
167
+ .accessfn = access_aa64_tid3,
168
.resetvalue = 0 },
169
{ .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
170
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
171
.access = PL1_R, .type = ARM_CP_CONST,
172
+ .accessfn = access_aa64_tid3,
173
.resetvalue = 0 },
174
{ .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64,
175
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
176
.access = PL1_R, .type = ARM_CP_CONST,
177
+ .accessfn = access_aa64_tid3,
178
/* At present, only SVEver == 0 is defined anyway. */
179
.resetvalue = 0 },
180
{ .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
181
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
182
.access = PL1_R, .type = ARM_CP_CONST,
183
+ .accessfn = access_aa64_tid3,
184
.resetvalue = 0 },
185
{ .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
186
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
187
.access = PL1_R, .type = ARM_CP_CONST,
188
+ .accessfn = access_aa64_tid3,
189
.resetvalue = 0 },
190
{ .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
191
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
192
.access = PL1_R, .type = ARM_CP_CONST,
193
+ .accessfn = access_aa64_tid3,
194
.resetvalue = 0 },
195
{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
196
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
197
.access = PL1_R, .type = ARM_CP_CONST,
198
+ .accessfn = access_aa64_tid3,
199
.resetvalue = cpu->id_aa64dfr0 },
200
{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
201
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
202
.access = PL1_R, .type = ARM_CP_CONST,
203
+ .accessfn = access_aa64_tid3,
204
.resetvalue = cpu->id_aa64dfr1 },
205
{ .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
206
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
207
.access = PL1_R, .type = ARM_CP_CONST,
208
+ .accessfn = access_aa64_tid3,
209
.resetvalue = 0 },
210
{ .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
211
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
212
.access = PL1_R, .type = ARM_CP_CONST,
213
+ .accessfn = access_aa64_tid3,
214
.resetvalue = 0 },
215
{ .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
216
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
217
.access = PL1_R, .type = ARM_CP_CONST,
218
+ .accessfn = access_aa64_tid3,
219
.resetvalue = cpu->id_aa64afr0 },
220
{ .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
221
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
222
.access = PL1_R, .type = ARM_CP_CONST,
223
+ .accessfn = access_aa64_tid3,
224
.resetvalue = cpu->id_aa64afr1 },
225
{ .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
226
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
227
.access = PL1_R, .type = ARM_CP_CONST,
228
+ .accessfn = access_aa64_tid3,
229
.resetvalue = 0 },
230
{ .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
231
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
232
.access = PL1_R, .type = ARM_CP_CONST,
233
+ .accessfn = access_aa64_tid3,
234
.resetvalue = 0 },
235
{ .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
236
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
237
.access = PL1_R, .type = ARM_CP_CONST,
238
+ .accessfn = access_aa64_tid3,
239
.resetvalue = cpu->isar.id_aa64isar0 },
240
{ .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
241
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
242
.access = PL1_R, .type = ARM_CP_CONST,
243
+ .accessfn = access_aa64_tid3,
244
.resetvalue = cpu->isar.id_aa64isar1 },
245
{ .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
246
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
247
.access = PL1_R, .type = ARM_CP_CONST,
248
+ .accessfn = access_aa64_tid3,
249
.resetvalue = 0 },
250
{ .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
251
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
252
.access = PL1_R, .type = ARM_CP_CONST,
253
+ .accessfn = access_aa64_tid3,
254
.resetvalue = 0 },
255
{ .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
256
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
257
.access = PL1_R, .type = ARM_CP_CONST,
258
+ .accessfn = access_aa64_tid3,
259
.resetvalue = 0 },
260
{ .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
261
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
262
.access = PL1_R, .type = ARM_CP_CONST,
263
+ .accessfn = access_aa64_tid3,
264
.resetvalue = 0 },
265
{ .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
266
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
267
.access = PL1_R, .type = ARM_CP_CONST,
268
+ .accessfn = access_aa64_tid3,
269
.resetvalue = 0 },
270
{ .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
271
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
272
.access = PL1_R, .type = ARM_CP_CONST,
273
+ .accessfn = access_aa64_tid3,
274
.resetvalue = 0 },
275
{ .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
276
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
277
.access = PL1_R, .type = ARM_CP_CONST,
278
+ .accessfn = access_aa64_tid3,
279
.resetvalue = cpu->isar.id_aa64mmfr0 },
280
{ .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
281
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
282
.access = PL1_R, .type = ARM_CP_CONST,
283
+ .accessfn = access_aa64_tid3,
284
.resetvalue = cpu->isar.id_aa64mmfr1 },
285
{ .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
286
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
287
.access = PL1_R, .type = ARM_CP_CONST,
288
+ .accessfn = access_aa64_tid3,
289
.resetvalue = 0 },
290
{ .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
291
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
292
.access = PL1_R, .type = ARM_CP_CONST,
293
+ .accessfn = access_aa64_tid3,
294
.resetvalue = 0 },
295
{ .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
296
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
297
.access = PL1_R, .type = ARM_CP_CONST,
298
+ .accessfn = access_aa64_tid3,
299
.resetvalue = 0 },
300
{ .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
301
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
302
.access = PL1_R, .type = ARM_CP_CONST,
303
+ .accessfn = access_aa64_tid3,
304
.resetvalue = 0 },
305
{ .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
306
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
307
.access = PL1_R, .type = ARM_CP_CONST,
308
+ .accessfn = access_aa64_tid3,
309
.resetvalue = 0 },
310
{ .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
311
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
312
.access = PL1_R, .type = ARM_CP_CONST,
313
+ .accessfn = access_aa64_tid3,
314
.resetvalue = 0 },
315
{ .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
316
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
317
.access = PL1_R, .type = ARM_CP_CONST,
318
+ .accessfn = access_aa64_tid3,
319
.resetvalue = cpu->isar.mvfr0 },
320
{ .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
321
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
322
.access = PL1_R, .type = ARM_CP_CONST,
323
+ .accessfn = access_aa64_tid3,
324
.resetvalue = cpu->isar.mvfr1 },
325
{ .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
326
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
327
.access = PL1_R, .type = ARM_CP_CONST,
328
+ .accessfn = access_aa64_tid3,
329
.resetvalue = cpu->isar.mvfr2 },
330
{ .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
331
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
332
.access = PL1_R, .type = ARM_CP_CONST,
333
+ .accessfn = access_aa64_tid3,
334
.resetvalue = 0 },
335
{ .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
336
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
337
.access = PL1_R, .type = ARM_CP_CONST,
338
+ .accessfn = access_aa64_tid3,
339
.resetvalue = 0 },
340
{ .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
341
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
342
.access = PL1_R, .type = ARM_CP_CONST,
343
+ .accessfn = access_aa64_tid3,
344
.resetvalue = 0 },
345
{ .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
346
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
347
.access = PL1_R, .type = ARM_CP_CONST,
348
+ .accessfn = access_aa64_tid3,
349
.resetvalue = 0 },
350
{ .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
351
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
352
.access = PL1_R, .type = ARM_CP_CONST,
353
+ .accessfn = access_aa64_tid3,
354
.resetvalue = 0 },
355
{ .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
356
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
357
--
50
--
358
2.20.1
51
2.20.1
359
52
360
53
diff view generated by jsdifflib
New patch
[PULL 02/12] docs: Fix documentation Copyright date
1
In commit 6d8980a38fa we updated the copyright string we present to
2
the user in -version output, About dialogs, etc, but we forgot that
3
the Sphinx manuals have a separate copyright string setting. Update
4
that one too.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Acked-by: Markus Armbruster <armbru@redhat.com>
8
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
9
Message-id: 20210705095547.15790-2-peter.maydell@linaro.org
10
---
11
docs/conf.py | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/docs/conf.py b/docs/conf.py
15
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/conf.py
17
+++ b/docs/conf.py
18
@@ -XXX,XX +XXX,XX @@
19
20
# General information about the project.
21
project = u'QEMU'
22
-copyright = u'2020, The QEMU Project Developers'
23
+copyright = u'2021, The QEMU Project Developers'
24
author = u'The QEMU Project Developers'
25
26
# The version info for the project you're documenting, acts as replacement for
27
--
28
2.20.1
29
30
diff view generated by jsdifflib
New patch
[PULL 03/12] docs: Stop calling the top level subsections of our manual 'manuals'
1
We merged our previous multiple-manual setup into a single Sphinx
2
manual, but we left some text in the various index.rst lines that
3
still calls the top level subsections separate 'manuals'. Update
4
them to talk about "this section of the manual" instead, and remove
5
now-obsolete comments about how the index.rst files are the "top
6
level page for the 'foo' manual".
1
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Acked-by: Markus Armbruster <armbru@redhat.com>
10
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
11
Message-id: 20210705095547.15790-3-peter.maydell@linaro.org
12
---
13
docs/devel/index.rst | 5 +----
14
docs/interop/index.rst | 7 ++-----
15
docs/specs/index.rst | 5 ++---
16
docs/system/index.rst | 5 +----
17
docs/tools/index.rst | 5 ++---
18
docs/user/index.rst | 5 +----
19
6 files changed, 9 insertions(+), 23 deletions(-)
20
21
diff --git a/docs/devel/index.rst b/docs/devel/index.rst
22
index XXXXXXX..XXXXXXX 100644
23
--- a/docs/devel/index.rst
24
+++ b/docs/devel/index.rst
25
@@ -XXX,XX +XXX,XX @@
26
-.. This is the top level page for the 'devel' manual.
27
-
28
-
29
Developer Information
30
=====================
31
32
-This manual documents various parts of the internals of QEMU.
33
+This section of the manual documents various parts of the internals of QEMU.
34
You only need to read it if you are interested in reading or
35
modifying QEMU's source code.
36
37
diff --git a/docs/interop/index.rst b/docs/interop/index.rst
38
index XXXXXXX..XXXXXXX 100644
39
--- a/docs/interop/index.rst
40
+++ b/docs/interop/index.rst
41
@@ -XXX,XX +XXX,XX @@
42
-.. This is the top level page for the 'interop' manual.
43
-
44
-
45
System Emulation Management and Interoperability
46
================================================
47
48
-This manual contains documents and specifications that are useful
49
-for making QEMU interoperate with other software.
50
+This section of the manual contains documents and specifications that
51
+are useful for making QEMU interoperate with other software.
52
53
Contents:
54
55
diff --git a/docs/specs/index.rst b/docs/specs/index.rst
56
index XXXXXXX..XXXXXXX 100644
57
--- a/docs/specs/index.rst
58
+++ b/docs/specs/index.rst
59
@@ -XXX,XX +XXX,XX @@
60
-.. This is the top level page for the 'specs' manual
61
-
62
-
63
System Emulation Guest Hardware Specifications
64
==============================================
65
66
+This section of the manual contains specifications of
67
+guest hardware that is specific to QEMU.
68
69
Contents:
70
71
diff --git a/docs/system/index.rst b/docs/system/index.rst
72
index XXXXXXX..XXXXXXX 100644
73
--- a/docs/system/index.rst
74
+++ b/docs/system/index.rst
75
@@ -XXX,XX +XXX,XX @@
76
-.. This is the top level page for the 'system' manual.
77
-
78
-
79
System Emulation
80
================
81
82
-This manual is the overall guide for users using QEMU
83
+This section of the manual is the overall guide for users using QEMU
84
for full system emulation (as opposed to user-mode emulation).
85
This includes working with hypervisors such as KVM, Xen, Hax
86
or Hypervisor.Framework.
87
diff --git a/docs/tools/index.rst b/docs/tools/index.rst
88
index XXXXXXX..XXXXXXX 100644
89
--- a/docs/tools/index.rst
90
+++ b/docs/tools/index.rst
91
@@ -XXX,XX +XXX,XX @@
92
-.. This is the top level page for the 'tools' manual
93
-
94
-
95
Tools
96
=====
97
98
+This section of the manual documents QEMU's "tools": its
99
+command line utilities and other standalone programs.
100
101
Contents:
102
103
diff --git a/docs/user/index.rst b/docs/user/index.rst
104
index XXXXXXX..XXXXXXX 100644
105
--- a/docs/user/index.rst
106
+++ b/docs/user/index.rst
107
@@ -XXX,XX +XXX,XX @@
108
-.. This is the top level page for the 'user' manual.
109
-
110
-
111
User Mode Emulation
112
===================
113
114
-This manual is the overall guide for users using QEMU
115
+This section of the manual is the overall guide for users using QEMU
116
for user-mode emulation. In this mode, QEMU can launch
117
processes compiled for one CPU on another CPU.
118
119
--
120
2.20.1
121
122
diff view generated by jsdifflib
New patch
[PULL 04/12] docs: Remove "Contents:" lines from top-level subsections
1
Since the top-level subsections aren't self-contained manuals
2
any more, the "Contents:" lines at the top of each of their
3
index pages look a bit odd; remove them.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Acked-by: Markus Armbruster <armbru@redhat.com>
7
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
8
Message-id: 20210705095547.15790-4-peter.maydell@linaro.org
9
---
10
docs/devel/index.rst | 2 --
11
docs/interop/index.rst | 2 --
12
docs/specs/index.rst | 2 --
13
docs/system/index.rst | 2 --
14
docs/tools/index.rst | 2 --
15
docs/user/index.rst | 2 --
16
6 files changed, 12 deletions(-)
17
18
diff --git a/docs/devel/index.rst b/docs/devel/index.rst
19
index XXXXXXX..XXXXXXX 100644
20
--- a/docs/devel/index.rst
21
+++ b/docs/devel/index.rst
22
@@ -XXX,XX +XXX,XX @@ This section of the manual documents various parts of the internals of QEMU.
23
You only need to read it if you are interested in reading or
24
modifying QEMU's source code.
25
26
-Contents:
27
-
28
.. toctree::
29
:maxdepth: 2
30
:includehidden:
31
diff --git a/docs/interop/index.rst b/docs/interop/index.rst
32
index XXXXXXX..XXXXXXX 100644
33
--- a/docs/interop/index.rst
34
+++ b/docs/interop/index.rst
35
@@ -XXX,XX +XXX,XX @@ System Emulation Management and Interoperability
36
This section of the manual contains documents and specifications that
37
are useful for making QEMU interoperate with other software.
38
39
-Contents:
40
-
41
.. toctree::
42
:maxdepth: 2
43
44
diff --git a/docs/specs/index.rst b/docs/specs/index.rst
45
index XXXXXXX..XXXXXXX 100644
46
--- a/docs/specs/index.rst
47
+++ b/docs/specs/index.rst
48
@@ -XXX,XX +XXX,XX @@ System Emulation Guest Hardware Specifications
49
This section of the manual contains specifications of
50
guest hardware that is specific to QEMU.
51
52
-Contents:
53
-
54
.. toctree::
55
:maxdepth: 2
56
57
diff --git a/docs/system/index.rst b/docs/system/index.rst
58
index XXXXXXX..XXXXXXX 100644
59
--- a/docs/system/index.rst
60
+++ b/docs/system/index.rst
61
@@ -XXX,XX +XXX,XX @@ for full system emulation (as opposed to user-mode emulation).
62
This includes working with hypervisors such as KVM, Xen, Hax
63
or Hypervisor.Framework.
64
65
-Contents:
66
-
67
.. toctree::
68
:maxdepth: 3
69
70
diff --git a/docs/tools/index.rst b/docs/tools/index.rst
71
index XXXXXXX..XXXXXXX 100644
72
--- a/docs/tools/index.rst
73
+++ b/docs/tools/index.rst
74
@@ -XXX,XX +XXX,XX @@ Tools
75
This section of the manual documents QEMU's "tools": its
76
command line utilities and other standalone programs.
77
78
-Contents:
79
-
80
.. toctree::
81
:maxdepth: 2
82
83
diff --git a/docs/user/index.rst b/docs/user/index.rst
84
index XXXXXXX..XXXXXXX 100644
85
--- a/docs/user/index.rst
86
+++ b/docs/user/index.rst
87
@@ -XXX,XX +XXX,XX @@ This section of the manual is the overall guide for users using QEMU
88
for user-mode emulation. In this mode, QEMU can launch
89
processes compiled for one CPU on another CPU.
90
91
-Contents:
92
-
93
.. toctree::
94
:maxdepth: 2
95
96
--
97
2.20.1
98
99
diff view generated by jsdifflib
New patch
[PULL 05/12] docs: Move deprecation, build and license info out of system/
1
Now that we have a single Sphinx manual rather than multiple manuals,
2
we can provide a better place for "common to all of QEMU" information
3
like the deprecation notices, build platforms, license information,
4
which we currently have in the system/ manual even though it applies
5
to all of QEMU.
1
6
7
Create a new directory about/ on the same level as system/, user/,
8
etc, and move these documents there.
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Acked-by: Markus Armbruster <armbru@redhat.com>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
14
Message-id: 20210705095547.15790-5-peter.maydell@linaro.org
15
---
16
docs/{system => about}/build-platforms.rst | 0
17
docs/{system => about}/deprecated.rst | 0
18
docs/about/index.rst | 10 ++++++++++
19
docs/{system => about}/license.rst | 0
20
docs/{system => about}/removed-features.rst | 0
21
docs/index.rst | 1 +
22
docs/system/index.rst | 4 ----
23
7 files changed, 11 insertions(+), 4 deletions(-)
24
rename docs/{system => about}/build-platforms.rst (100%)
25
rename docs/{system => about}/deprecated.rst (100%)
26
create mode 100644 docs/about/index.rst
27
rename docs/{system => about}/license.rst (100%)
28
rename docs/{system => about}/removed-features.rst (100%)
29
30
diff --git a/docs/system/build-platforms.rst b/docs/about/build-platforms.rst
31
similarity index 100%
32
rename from docs/system/build-platforms.rst
33
rename to docs/about/build-platforms.rst
34
diff --git a/docs/system/deprecated.rst b/docs/about/deprecated.rst
35
similarity index 100%
36
rename from docs/system/deprecated.rst
37
rename to docs/about/deprecated.rst
38
diff --git a/docs/about/index.rst b/docs/about/index.rst
39
new file mode 100644
40
index XXXXXXX..XXXXXXX
41
--- /dev/null
42
+++ b/docs/about/index.rst
43
@@ -XXX,XX +XXX,XX @@
44
+About QEMU
45
+==========
46
+
47
+.. toctree::
48
+ :maxdepth: 2
49
+
50
+ build-platforms
51
+ deprecated
52
+ removed-features
53
+ license
54
diff --git a/docs/system/license.rst b/docs/about/license.rst
55
similarity index 100%
56
rename from docs/system/license.rst
57
rename to docs/about/license.rst
58
diff --git a/docs/system/removed-features.rst b/docs/about/removed-features.rst
59
similarity index 100%
60
rename from docs/system/removed-features.rst
61
rename to docs/about/removed-features.rst
62
diff --git a/docs/index.rst b/docs/index.rst
63
index XXXXXXX..XXXXXXX 100644
64
--- a/docs/index.rst
65
+++ b/docs/index.rst
66
@@ -XXX,XX +XXX,XX @@ Welcome to QEMU's documentation!
67
:maxdepth: 2
68
:caption: Contents:
69
70
+ about/index
71
system/index
72
user/index
73
tools/index
74
diff --git a/docs/system/index.rst b/docs/system/index.rst
75
index XXXXXXX..XXXXXXX 100644
76
--- a/docs/system/index.rst
77
+++ b/docs/system/index.rst
78
@@ -XXX,XX +XXX,XX @@ or Hypervisor.Framework.
79
targets
80
security
81
multi-process
82
- deprecated
83
- removed-features
84
- build-platforms
85
- license
86
--
87
2.20.1
88
89
diff view generated by jsdifflib
New patch
[PULL 06/12] docs: Add some actual About text to about/index.rst
1
Add some text to About to act as a brief introduction to the QEMU
2
manual and to make the about page a bit less of an abrupt start to
3
it.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Acked-by: Markus Armbruster <armbru@redhat.com>
7
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
8
Message-id: 20210705095547.15790-6-peter.maydell@linaro.org
9
---
10
docs/about/index.rst | 17 +++++++++++++++++
11
1 file changed, 17 insertions(+)
12
13
diff --git a/docs/about/index.rst b/docs/about/index.rst
14
index XXXXXXX..XXXXXXX 100644
15
--- a/docs/about/index.rst
16
+++ b/docs/about/index.rst
17
@@ -XXX,XX +XXX,XX @@
18
About QEMU
19
==========
20
21
+QEMU is a generic and open source machine emulator and virtualizer.
22
+
23
+QEMU can be used in several different ways. The most common is for
24
+"system emulation", where it provides a virtual model of an
25
+entire machine (CPU, memory and emulated devices) to run a guest OS.
26
+In this mode the CPU may be fully emulated, or it may work with
27
+a hypervisor such as KVM, Xen, Hax or Hypervisor.Framework to
28
+allow the guest to run directly on the host CPU.
29
+
30
+The second supported way to use QEMU is "user mode emulation",
31
+where QEMU can launch processes compiled for one CPU on another CPU.
32
+In this mode the CPU is always emulated.
33
+
34
+QEMU also provides a number of standalone commandline utilities,
35
+such as the `qemu-img` disk image utility that allows you to create,
36
+convert and modify disk images.
37
+
38
.. toctree::
39
:maxdepth: 2
40
41
--
42
2.20.1
43
44
diff view generated by jsdifflib
New patch
[PULL 07/12] docs: Add license note to the HTML page footer
1
The standard Sphinx/RTD HTML page footer gives a copyright line
2
(based on the 'copyright' variable set in conf.py) and a line "Built
3
with Sphinx using a theme provided by Read the Docs" (which can be
4
disabled via the html_show_sphinx variable, but we leave it enabled).
5
As a free software project, we'd like to also mention the license
6
QEMU and its manual are released under.
1
7
8
Add a template footer.html which defines the 'extrafooter' block that
9
the RtD theme provides for this purpose. The new line of text will
10
go below the existing copyright and sphinx-acknowledgement lines.
11
(Unfortunately the RTD footer template does not permit putting it
12
after the copyright but before the sphinx-acknowledgement.)
13
14
We use the templating functionality to make the new text also be a
15
hyperlink to the about/license.html page of the manual.
16
17
Unlike rst files, HTML template files are not reported to our depfile
18
plugin, so we maintain a manual list in meson.build. New template
19
files should be rare, so not being able to auto-generate the
20
dependency info is not too awkward.
21
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Acked-by: Markus Armbruster <armbru@redhat.com>
24
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
25
Message-id: 20210705095547.15790-7-peter.maydell@linaro.org
26
---
27
docs/_templates/footer.html | 12 ++++++++++++
28
docs/meson.build | 3 ++-
29
MAINTAINERS | 1 +
30
3 files changed, 15 insertions(+), 1 deletion(-)
31
create mode 100644 docs/_templates/footer.html
32
33
diff --git a/docs/_templates/footer.html b/docs/_templates/footer.html
34
new file mode 100644
35
index XXXXXXX..XXXXXXX
36
--- /dev/null
37
+++ b/docs/_templates/footer.html
38
@@ -XXX,XX +XXX,XX @@
39
+{% extends "!footer.html" %}
40
+{% block extrafooter %}
41
+
42
+<!-- Empty para to force a blank line after "Built with Sphinx ..." -->
43
+<p></p>
44
+
45
+{% trans path=pathto('about/license') %}
46
+<p><a href="{{ path }}">QEMU and this manual are released under the
47
+GNU General Public License, version 2.</a></p>
48
+{% endtrans %}
49
+{{ super() }}
50
+{% endblock %}
51
diff --git a/docs/meson.build b/docs/meson.build
52
index XXXXXXX..XXXXXXX 100644
53
--- a/docs/meson.build
54
+++ b/docs/meson.build
55
@@ -XXX,XX +XXX,XX @@ if build_docs
56
meson.source_root() / 'docs/sphinx/qapidoc.py',
57
meson.source_root() / 'docs/sphinx/qmp_lexer.py',
58
qapi_gen_depends ]
59
+ sphinx_template_files = [ meson.source_root() / 'docs/_templates/footer.html' ]
60
61
have_ga = have_tools and config_host.has_key('CONFIG_GUEST_AGENT')
62
63
@@ -XXX,XX +XXX,XX @@ if build_docs
64
output: 'docs.stamp',
65
input: files('conf.py'),
66
depfile: 'docs.d',
67
- depend_files: sphinx_extn_depends,
68
+ depend_files: [ sphinx_extn_depends, sphinx_template_files ],
69
command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@',
70
'-Ddepfile_stamp=@OUTPUT0@',
71
'-b', 'html', '-d', private_dir,
72
diff --git a/MAINTAINERS b/MAINTAINERS
73
index XXXXXXX..XXXXXXX 100644
74
--- a/MAINTAINERS
75
+++ b/MAINTAINERS
76
@@ -XXX,XX +XXX,XX @@ S: Maintained
77
F: docs/conf.py
78
F: docs/*/conf.py
79
F: docs/sphinx/
80
+F: docs/_templates/
81
82
Miscellaneous
83
-------------
84
--
85
2.20.1
86
87
diff view generated by jsdifflib
New patch
[PULL 08/12] docs: Add QEMU version information to HTML footer
1
Add a line to the HTML document footer mentioning the QEMU version.
2
The version information is already provided in very faint text below
3
the QEMU logo in the sidebar, but that is rather inconspicious, so
4
repeating it in the footer seems useful.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Acked-by: Markus Armbruster <armbru@redhat.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
10
Message-id: 20210705095547.15790-8-peter.maydell@linaro.org
11
---
12
docs/_templates/footer.html | 2 ++
13
1 file changed, 2 insertions(+)
14
15
diff --git a/docs/_templates/footer.html b/docs/_templates/footer.html
16
index XXXXXXX..XXXXXXX 100644
17
--- a/docs/_templates/footer.html
18
+++ b/docs/_templates/footer.html
19
@@ -XXX,XX +XXX,XX @@
20
<!-- Empty para to force a blank line after "Built with Sphinx ..." -->
21
<p></p>
22
23
+<p>This documentation is for QEMU version {{ version }}.</p>
24
+
25
{% trans path=pathto('about/license') %}
26
<p><a href="{{ path }}">QEMU and this manual are released under the
27
GNU General Public License, version 2.</a></p>
28
--
29
2.20.1
30
31
diff view generated by jsdifflib
New patch
[PULL 09/12] docs: Add skeletal documentation of cubieboard
1
Add skeletal documentation of the cubieboard machine.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-id: 20210713142226.19155-2-peter.maydell@linaro.org
7
---
8
docs/system/arm/cubieboard.rst | 16 ++++++++++++++++
9
docs/system/target-arm.rst | 1 +
10
MAINTAINERS | 1 +
11
3 files changed, 18 insertions(+)
12
create mode 100644 docs/system/arm/cubieboard.rst
13
14
diff --git a/docs/system/arm/cubieboard.rst b/docs/system/arm/cubieboard.rst
15
new file mode 100644
16
index XXXXXXX..XXXXXXX
17
--- /dev/null
18
+++ b/docs/system/arm/cubieboard.rst
19
@@ -XXX,XX +XXX,XX @@
20
+Cubietech Cubieboard (``cubieboard``)
21
+=====================================
22
+
23
+The ``cubieboard`` model emulates the Cubietech Cubieboard,
24
+which is a Cortex-A8 based single-board computer using
25
+the AllWinner A10 SoC.
26
+
27
+Emulated devices:
28
+
29
+- Timer
30
+- UART
31
+- RTC
32
+- EMAC
33
+- SDHCI
34
+- USB controller
35
+- SATA controller
36
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
37
index XXXXXXX..XXXXXXX 100644
38
--- a/docs/system/target-arm.rst
39
+++ b/docs/system/target-arm.rst
40
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
41
arm/aspeed
42
arm/sabrelite
43
arm/digic
44
+ arm/cubieboard
45
arm/musicpal
46
arm/gumstix
47
arm/nrf
48
diff --git a/MAINTAINERS b/MAINTAINERS
49
index XXXXXXX..XXXXXXX 100644
50
--- a/MAINTAINERS
51
+++ b/MAINTAINERS
52
@@ -XXX,XX +XXX,XX @@ S: Odd Fixes
53
F: hw/*/allwinner*
54
F: include/hw/*/allwinner*
55
F: hw/arm/cubieboard.c
56
+F: docs/system/arm/cubieboard.rst
57
58
Allwinner-h3
59
M: Niek Linnenbank <nieklinnenbank@gmail.com>
60
--
61
2.20.1
62
63
diff view generated by jsdifflib
[PULL 3/4] target/arm: Fix ISR_EL1 tracking when executing at EL2
[PULL 10/12] docs: Add skeletal documentation of the emcraft-sf2
1
From: Marc Zyngier <maz@kernel.org>
1
Add skeletal documentation of the emcraft-sf2 machine.
2
2
3
The ARMv8 ARM states when executing at EL2, EL3 or Secure EL1,
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
ISR_EL1 shows the pending status of the physical IRQ, FIQ, or
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
SError interrupts.
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-id: 20210713142226.19155-3-peter.maydell@linaro.org
7
---
8
docs/system/arm/emcraft-sf2.rst | 15 +++++++++++++++
9
docs/system/target-arm.rst | 1 +
10
MAINTAINERS | 1 +
11
3 files changed, 17 insertions(+)
12
create mode 100644 docs/system/arm/emcraft-sf2.rst
6
13
7
Unfortunately, QEMU's implementation only considers the HCR_EL2
14
diff --git a/docs/system/arm/emcraft-sf2.rst b/docs/system/arm/emcraft-sf2.rst
8
bits, and ignores the current exception level. This means a hypervisor
15
new file mode 100644
9
trying to look at its own interrupt state actually sees the guest
16
index XXXXXXX..XXXXXXX
10
state, which is unexpected and breaks KVM as of Linux 5.3.
17
--- /dev/null
11
18
+++ b/docs/system/arm/emcraft-sf2.rst
12
Instead, check for the running EL and return the physical bits
19
@@ -XXX,XX +XXX,XX @@
13
if not running in a virtualized context.
20
+Emcraft SmartFusion2 SOM kit (``emcraft-sf2``)
14
21
+==============================================
15
Fixes: 636540e9c40b
22
+
16
Cc: qemu-stable@nongnu.org
23
+The ``emcraft-sf2`` board emulates the SmartFusion2 SOM kit from
17
Reported-by: Quentin Perret <qperret@google.com>
24
+Emcraft (M2S010). This is a System-on-Module from EmCraft systems,
18
Signed-off-by: Marc Zyngier <maz@kernel.org>
25
+based on the SmartFusion2 SoC FPGA from Microsemi Corporation.
19
Message-id: 20191122135833.28953-1-maz@kernel.org
26
+The SoC is based on a Cortex-M4 processor.
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
27
+
21
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
28
+Emulated devices:
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
+
23
---
30
+- System timer
24
target/arm/helper.c | 7 +++++--
31
+- System registers
25
1 file changed, 5 insertions(+), 2 deletions(-)
32
+- SPI controller
26
33
+- UART
27
diff --git a/target/arm/helper.c b/target/arm/helper.c
34
+- EMAC
35
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
28
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/helper.c
37
--- a/docs/system/target-arm.rst
30
+++ b/target/arm/helper.c
38
+++ b/docs/system/target-arm.rst
31
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
39
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
32
CPUState *cs = env_cpu(env);
40
arm/sabrelite
33
uint64_t hcr_el2 = arm_hcr_el2_eff(env);
41
arm/digic
34
uint64_t ret = 0;
42
arm/cubieboard
35
+ bool allow_virt = (arm_current_el(env) == 1 &&
43
+ arm/emcraft-sf2
36
+ (!arm_is_secure_below_el3(env) ||
44
arm/musicpal
37
+ (env->cp15.scr_el3 & SCR_EEL2)));
45
arm/gumstix
38
46
arm/nrf
39
- if (hcr_el2 & HCR_IMO) {
47
diff --git a/MAINTAINERS b/MAINTAINERS
40
+ if (allow_virt && (hcr_el2 & HCR_IMO)) {
48
index XXXXXXX..XXXXXXX 100644
41
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
49
--- a/MAINTAINERS
42
ret |= CPSR_I;
50
+++ b/MAINTAINERS
43
}
51
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
44
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
52
L: qemu-arm@nongnu.org
45
}
53
S: Maintained
46
}
54
F: hw/arm/msf2-som.c
47
55
+F: docs/system/arm/emcraft-sf2.rst
48
- if (hcr_el2 & HCR_FMO) {
56
49
+ if (allow_virt && (hcr_el2 & HCR_FMO)) {
57
ASPEED BMCs
50
if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
58
M: Cédric Le Goater <clg@kaod.org>
51
ret |= CPSR_F;
52
}
53
--
59
--
54
2.20.1
60
2.20.1
55
61
56
62
diff view generated by jsdifflib
[PULL 2/4] hw/arm: versal: Add the CRP as unimplemented
[PULL 11/12] docs: Add skeletal documentation of highbank and midway
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
Add skeletal documentation for the highbank and midway machines.
2
2
3
Add the CRP as unimplemented thus avoiding bus errors when
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
guests access these registers.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-id: 20210713142226.19155-4-peter.maydell@linaro.org
7
---
8
docs/system/arm/highbank.rst | 19 +++++++++++++++++++
9
docs/system/target-arm.rst | 1 +
10
MAINTAINERS | 1 +
11
3 files changed, 21 insertions(+)
12
create mode 100644 docs/system/arm/highbank.rst
5
13
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
14
diff --git a/docs/system/arm/highbank.rst b/docs/system/arm/highbank.rst
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
new file mode 100644
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
16
index XXXXXXX..XXXXXXX
9
Message-id: 20191115154734.26449-2-edgar.iglesias@gmail.com
17
--- /dev/null
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
+++ b/docs/system/arm/highbank.rst
11
---
19
@@ -XXX,XX +XXX,XX @@
12
include/hw/arm/xlnx-versal.h | 3 +++
20
+Calxeda Highbank and Midway (``highbank``, ``midway``)
13
hw/arm/xlnx-versal.c | 2 ++
21
+======================================================
14
2 files changed, 5 insertions(+)
22
+
15
23
+``highbank`` is a model of the Calxeda Highbank (ECX-1000) system,
16
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
24
+which has four Cortex-A9 cores.
25
+
26
+``midway`` is a model of the Calxeda Midway (ECX-2000) system,
27
+which has four Cortex-A15 cores.
28
+
29
+Emulated devices:
30
+
31
+- L2x0 cache controller
32
+- SP804 dual timer
33
+- PL011 UART
34
+- PL061 GPIOs
35
+- PL031 RTC
36
+- PL022 synchronous serial port controller
37
+- AHCI
38
+- XGMAC ethernet controllers
39
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
17
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/xlnx-versal.h
41
--- a/docs/system/target-arm.rst
19
+++ b/include/hw/arm/xlnx-versal.h
42
+++ b/docs/system/target-arm.rst
20
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
43
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
21
#define MM_IOU_SCNTRS_SIZE 0x10000
44
arm/digic
22
#define MM_FPD_CRF 0xfd1a0000U
45
arm/cubieboard
23
#define MM_FPD_CRF_SIZE 0x140000
46
arm/emcraft-sf2
24
+
47
+ arm/highbank
25
+#define MM_PMC_CRP 0xf1260000U
48
arm/musicpal
26
+#define MM_PMC_CRP_SIZE 0x10000
49
arm/gumstix
27
#endif
50
arm/nrf
28
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
51
diff --git a/MAINTAINERS b/MAINTAINERS
29
index XXXXXXX..XXXXXXX 100644
52
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/arm/xlnx-versal.c
53
--- a/MAINTAINERS
31
+++ b/hw/arm/xlnx-versal.c
54
+++ b/MAINTAINERS
32
@@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s)
55
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
33
MM_CRL, MM_CRL_SIZE);
56
S: Odd Fixes
34
versal_unimp_area(s, "crf", &s->mr_ps,
57
F: hw/arm/highbank.c
35
MM_FPD_CRF, MM_FPD_CRF_SIZE);
58
F: hw/net/xgmac.c
36
+ versal_unimp_area(s, "crp", &s->mr_ps,
59
+F: docs/system/arm/highbank.rst
37
+ MM_PMC_CRP, MM_PMC_CRP_SIZE);
60
38
versal_unimp_area(s, "iou-scntr", &s->mr_ps,
61
Canon DIGIC
39
MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
62
M: Antony Pavlov <antonynpavlov@gmail.com>
40
versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,
41
--
63
--
42
2.20.1
64
2.20.1
43
65
44
66
diff view generated by jsdifflib
[PULL 1/4] target/arm: Fix handling of cortex-m FTYPE flag in EXCRET
[PULL 12/12] target/arm: Remove duplicate 'plus1' function from Neon and SVE decode
1
From: Jean-Hugues Deschênes <Jean-Hugues.Deschenes@ossiaco.com>
1
The Neon and SVE decoders use private 'plus1' functions to implement
2
"add one" for the !function decoder syntax. We have a generic
3
"plus_1" function in translate.h, so use that instead.
2
4
3
According to the PushStack() pseudocode in the armv7m RM,
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
bit 4 of the LR should be set to NOT(CONTROL.PFCA) when
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
an FPU is present. Current implementation is doing it for
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
armv8, but not for armv7. This patch makes the existing
8
Message-id: 20210715095341.701-1-peter.maydell@linaro.org
7
logic applicable to both code paths.
9
---
10
target/arm/neon-ls.decode | 4 ++--
11
target/arm/neon-shared.decode | 2 +-
12
target/arm/sve.decode | 2 +-
13
target/arm/translate-neon.c | 5 -----
14
target/arm/translate-sve.c | 5 -----
15
5 files changed, 4 insertions(+), 14 deletions(-)
8
16
9
Signed-off-by: Jean-Hugues Deschenes <jean-hugues.deschenes@ossiaco.com>
17
diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/m_helper.c | 7 +++----
14
1 file changed, 3 insertions(+), 4 deletions(-)
15
16
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/m_helper.c
19
--- a/target/arm/neon-ls.decode
19
+++ b/target/arm/m_helper.c
20
+++ b/target/arm/neon-ls.decode
20
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
21
@@ -XXX,XX +XXX,XX @@ VLD_all_lanes 1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \
21
if (env->v7m.secure) {
22
vd=%vd_dp
22
lr |= R_V7M_EXCRET_S_MASK;
23
23
}
24
# Neon load/store single structure to one lane
24
- if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
25
-%imm1_5_p1 5:1 !function=plus1
25
- lr |= R_V7M_EXCRET_FTYPE_MASK;
26
-%imm1_6_p1 6:1 !function=plus1
26
- }
27
+%imm1_5_p1 5:1 !function=plus_1
27
} else {
28
+%imm1_6_p1 6:1 !function=plus_1
28
lr = R_V7M_EXCRET_RES1_MASK |
29
29
R_V7M_EXCRET_S_MASK |
30
VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \
30
R_V7M_EXCRET_DCRS_MASK |
31
vd=%vd_dp size=0 stride=1
31
- R_V7M_EXCRET_FTYPE_MASK |
32
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
32
R_V7M_EXCRET_ES_MASK;
33
index XXXXXXX..XXXXXXX 100644
33
if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) {
34
--- a/target/arm/neon-shared.decode
34
lr |= R_V7M_EXCRET_SPSEL_MASK;
35
+++ b/target/arm/neon-shared.decode
35
}
36
@@ -XXX,XX +XXX,XX @@
36
}
37
# which is 0 for fp16 and 1 for fp32 into a MO_* constant.
37
+ if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
38
# (Note that this is the reverse of the sense of the 1-bit size
38
+ lr |= R_V7M_EXCRET_FTYPE_MASK;
39
# field in the 3same_fp Neon insns.)
39
+ }
40
-%vcadd_size 20:1 !function=plus1
40
if (!arm_v7m_is_handler_mode(env)) {
41
+%vcadd_size 20:1 !function=plus_1
41
lr |= R_V7M_EXCRET_MODE_MASK;
42
42
}
43
VCMLA 1111 110 rot:2 . 1 . .... .... 1000 . q:1 . 0 .... \
44
vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%vcadd_size
45
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/sve.decode
48
+++ b/target/arm/sve.decode
49
@@ -XXX,XX +XXX,XX @@
50
###########################################################################
51
# Named fields. These are primarily for disjoint fields.
52
53
-%imm4_16_p1 16:4 !function=plus1
54
+%imm4_16_p1 16:4 !function=plus_1
55
%imm6_22_5 22:1 5:5
56
%imm7_22_16 22:2 16:5
57
%imm8_16_10 16:5 10:3
58
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/translate-neon.c
61
+++ b/target/arm/translate-neon.c
62
@@ -XXX,XX +XXX,XX @@
63
#include "translate.h"
64
#include "translate-a32.h"
65
66
-static inline int plus1(DisasContext *s, int x)
67
-{
68
- return x + 1;
69
-}
70
-
71
static inline int neon_3same_fp_size(DisasContext *s, int x)
72
{
73
/* Convert 0==fp32, 1==fp16 into a MO_* value */
74
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/target/arm/translate-sve.c
77
+++ b/target/arm/translate-sve.c
78
@@ -XXX,XX +XXX,XX @@ static int tszimm_shl(DisasContext *s, int x)
79
return x - (8 << tszimm_esz(s, x));
80
}
81
82
-static inline int plus1(DisasContext *s, int x)
83
-{
84
- return x + 1;
85
-}
86
-
87
/* The SH bit is in bit 8. Extract the low 8 and shift. */
88
static inline int expand_imm_sh8s(DisasContext *s, int x)
89
{
43
--
90
--
44
2.20.1
91
2.20.1
45
92
46
93
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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