[PULL 0/4] target-arm queue
[PULL 00/12] target-arm queue
1
Arm patches for rc3 : just a handful of bug fixes.
1
The following changes since commit 6eeea6725a70e6fcb5abba0764496bdab07ddfb3:
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3
thanks
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Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-10-06' into staging (2020-10-06 21:13:34 +0100)
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-- PMM
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7
The following changes since commit 4ecc984210ca1bf508a96a550ec8a93a5f833f6c:
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Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc3' into staging (2019-11-26 12:36:40 +0000)
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4
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are available in the Git repository at:
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are available in the Git repository at:
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6
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191126
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201008
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8
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for you to fetch changes up to 6a4ef4e5d1084ce41fafa7d470a644b0fd3d9317:
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for you to fetch changes up to ba118c26e16a97e6ff6de8184057d3420ce16a23:
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10
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target/arm: Honor HCR_EL2.TID3 trapping requirements (2019-11-26 13:55:37 +0000)
11
target/arm: Make '-cpu max' have a 48-bit PA (2020-10-08 15:24:32 +0100)
18
12
19
----------------------------------------------------------------
13
----------------------------------------------------------------
20
target-arm queue:
14
target-arm queue:
21
* handle FTYPE flag correctly in v7M exception return
15
* hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer
22
for v7M CPUs with an FPU (v8M CPUs were already correct)
16
* hw/arm/fsl-imx25: Fix a typo
23
* versal: Add the CRP as unimplemented
17
* hw/arm/sbsa-ref : Fix SMMUv3 Initialisation
24
* Fix ISR_EL1 tracking when executing at EL2
18
* hw/arm/sbsa-ref : allocate IRQs for SMMUv3
25
* Honor HCR_EL2.TID3 trapping requirements
19
* hw/char/bcm2835_aux: Allow less than 32-bit accesses
20
* hw/arm/virt: Implement kvm-steal-time
21
* target/arm: Make '-cpu max' have a 48-bit PA
26
22
27
----------------------------------------------------------------
23
----------------------------------------------------------------
28
Edgar E. Iglesias (1):
24
Andrew Jones (6):
29
hw/arm: versal: Add the CRP as unimplemented
25
linux headers: sync to 5.9-rc7
26
target/arm/kvm: Make uncalled stubs explicitly unreachable
27
hw/arm/virt: Move post cpu realize check into its own function
28
hw/arm/virt: Move kvm pmu setup to virt_cpu_post_init
29
tests/qtest: Restore aarch64 arm-cpu-features test
30
hw/arm/virt: Implement kvm-steal-time
30
31
31
Jean-Hugues Deschênes (1):
32
Graeme Gregory (2):
32
target/arm: Fix handling of cortex-m FTYPE flag in EXCRET
33
hw/arm/sbsa-ref : Fix SMMUv3 Initialisation
34
hw/arm/sbsa-ref : allocate IRQs for SMMUv3
33
35
34
Marc Zyngier (2):
36
Peter Maydell (1):
35
target/arm: Fix ISR_EL1 tracking when executing at EL2
37
target/arm: Make '-cpu max' have a 48-bit PA
36
target/arm: Honor HCR_EL2.TID3 trapping requirements
37
38
38
include/hw/arm/xlnx-versal.h | 3 ++
39
Philippe Mathieu-Daudé (3):
39
hw/arm/xlnx-versal.c | 2 ++
40
hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer
40
target/arm/helper.c | 83 ++++++++++++++++++++++++++++++++++++++++++--
41
hw/arm/fsl-imx25: Fix a typo
41
target/arm/m_helper.c | 7 ++--
42
hw/char/bcm2835_aux: Allow less than 32-bit accesses
42
4 files changed, 89 insertions(+), 6 deletions(-)
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43
44
docs/system/arm/cpu-features.rst | 11 ++++
45
include/hw/arm/fsl-imx25.h | 2 +-
46
include/hw/arm/virt.h | 5 ++
47
linux-headers/linux/kvm.h | 6 ++-
48
target/arm/cpu.h | 4 ++
49
target/arm/kvm_arm.h | 94 ++++++++++++++++++++++++++-------
50
hw/arm/sbsa-ref.c | 3 +-
51
hw/arm/virt.c | 110 ++++++++++++++++++++++++++++-----------
52
hw/char/bcm2835_aux.c | 4 +-
53
hw/ssi/npcm7xx_fiu.c | 12 ++---
54
target/arm/cpu.c | 8 +++
55
target/arm/cpu64.c | 4 ++
56
target/arm/kvm.c | 16 ++++++
57
target/arm/kvm64.c | 64 +++++++++++++++++++++--
58
target/arm/monitor.c | 2 +-
59
tests/qtest/arm-cpu-features.c | 25 +++++++--
60
hw/ssi/trace-events | 2 +-
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tests/qtest/meson.build | 3 +-
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18 files changed, 303 insertions(+), 72 deletions(-)
63
diff view generated by jsdifflib
New patch
[PULL 01/12] hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Fix integer handling issues handling issue reported by Coverity:
4
5
hw/ssi/npcm7xx_fiu.c: 162 in npcm7xx_fiu_flash_read()
6
>>> CID 1432730: Integer handling issues (NEGATIVE_RETURNS)
7
>>> "npcm7xx_fiu_cs_index(fiu, f)" is passed to a parameter that cannot be negative.
8
162 npcm7xx_fiu_select(fiu, npcm7xx_fiu_cs_index(fiu, f));
9
10
hw/ssi/npcm7xx_fiu.c: 221 in npcm7xx_fiu_flash_write()
11
218 cs_id = npcm7xx_fiu_cs_index(fiu, f);
12
219 trace_npcm7xx_fiu_flash_write(DEVICE(fiu)->canonical_path, cs_id, addr,
13
220 size, v);
14
>>> CID 1432729: Integer handling issues (NEGATIVE_RETURNS)
15
>>> "cs_id" is passed to a parameter that cannot be negative.
16
221 npcm7xx_fiu_select(fiu, cs_id);
17
18
Since the index of the flash can not be negative, return an
19
unsigned type.
20
21
Reported-by: Coverity (CID 1432729 & 1432730: NEGATIVE_RETURNS)
22
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
23
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
24
Message-id: 20200919132435.310527-1-f4bug@amsat.org
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
---
27
hw/ssi/npcm7xx_fiu.c | 12 ++++++------
28
hw/ssi/trace-events | 2 +-
29
2 files changed, 7 insertions(+), 7 deletions(-)
30
31
diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/ssi/npcm7xx_fiu.c
34
+++ b/hw/ssi/npcm7xx_fiu.c
35
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxFIURegister {
36
* Returns the index of flash in the fiu->flash array. This corresponds to the
37
* chip select ID of the flash.
38
*/
39
-static int npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu, NPCM7xxFIUFlash *flash)
40
+static unsigned npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu,
41
+ NPCM7xxFIUFlash *flash)
42
{
43
int index = flash - fiu->flash;
44
45
@@ -XXX,XX +XXX,XX @@ static int npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu, NPCM7xxFIUFlash *flash)
46
}
47
48
/* Assert the chip select specified in the UMA Control/Status Register. */
49
-static void npcm7xx_fiu_select(NPCM7xxFIUState *s, int cs_id)
50
+static void npcm7xx_fiu_select(NPCM7xxFIUState *s, unsigned cs_id)
51
{
52
trace_npcm7xx_fiu_select(DEVICE(s)->canonical_path, cs_id);
53
54
if (cs_id < s->cs_count) {
55
qemu_irq_lower(s->cs_lines[cs_id]);
56
+ s->active_cs = cs_id;
57
} else {
58
qemu_log_mask(LOG_GUEST_ERROR,
59
"%s: UMA to CS%d; this module has only %d chip selects",
60
DEVICE(s)->canonical_path, cs_id, s->cs_count);
61
- cs_id = -1;
62
+ s->active_cs = -1;
63
}
64
-
65
- s->active_cs = cs_id;
66
}
67
68
/* Deassert the currently active chip select. */
69
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_flash_write(void *opaque, hwaddr addr, uint64_t v,
70
NPCM7xxFIUFlash *f = opaque;
71
NPCM7xxFIUState *fiu = f->fiu;
72
uint32_t dwr_cfg;
73
- int cs_id;
74
+ unsigned cs_id;
75
int i;
76
77
if (fiu->active_cs != -1) {
78
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
79
index XXXXXXX..XXXXXXX 100644
80
--- a/hw/ssi/trace-events
81
+++ b/hw/ssi/trace-events
82
@@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_deselect(const char *id, int cs) "%s deselect CS%d"
83
npcm7xx_fiu_ctrl_read(const char *id, uint64_t addr, uint32_t data) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
84
npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
85
npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
86
-npcm7xx_fiu_flash_write(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
87
+npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
88
--
89
2.20.1
90
91
diff view generated by jsdifflib
New patch
[PULL 02/12] hw/arm/fsl-imx25: Fix a typo
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Message-id: 20201002080935.1660005-1-f4bug@amsat.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
include/hw/arm/fsl-imx25.h | 2 +-
9
1 file changed, 1 insertion(+), 1 deletion(-)
10
11
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/arm/fsl-imx25.h
14
+++ b/include/hw/arm/fsl-imx25.h
15
@@ -XXX,XX +XXX,XX @@ struct FslIMX25State {
16
* 0xBB00_0000 0xBB00_0FFF 4 Kbytes NAND flash main area buffer
17
* 0xBB00_1000 0xBB00_11FF 512 B NAND flash spare area buffer
18
* 0xBB00_1200 0xBB00_1DFF 3 Kbytes Reserved
19
- * 0xBB00_1E00 0xBB00_1FFF 512 B NAND flash control regisers
20
+ * 0xBB00_1E00 0xBB00_1FFF 512 B NAND flash control registers
21
* 0xBB01_2000 0xBFFF_FFFF 96 Mbytes (minus 8 Kbytes) Reserved
22
* 0xC000_0000 0xFFFF_FFFF 1024 Mbytes Reserved
23
*/
24
--
25
2.20.1
26
27
diff view generated by jsdifflib
New patch
[PULL 03/12] hw/arm/sbsa-ref : Fix SMMUv3 Initialisation
1
From: Graeme Gregory <graeme@nuviainc.com>
1
2
3
SMMUv3 has an error in a previous patch where an i was transposed to a 1
4
meaning interrupts would not have been correctly assigned to the SMMUv3
5
instance.
6
7
Fixes: 48ba18e6d3f3 ("hw/arm/sbsa-ref: Simplify by moving the gic in the machine state")
8
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
Message-id: 20201007100732.4103790-2-graeme@nuviainc.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/sbsa-ref.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/sbsa-ref.c
20
+++ b/hw/arm/sbsa-ref.c
21
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
22
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
23
for (i = 0; i < NUM_SMMU_IRQS; i++) {
24
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
25
- qdev_get_gpio_in(sms->gic, irq + 1));
26
+ qdev_get_gpio_in(sms->gic, irq + i));
27
}
28
}
29
30
--
31
2.20.1
32
33
diff view generated by jsdifflib
New patch
[PULL 04/12] hw/arm/sbsa-ref : allocate IRQs for SMMUv3
1
From: Graeme Gregory <graeme@nuviainc.com>
1
2
3
Original commit did not allocate IRQs for the SMMUv3 in the irqmap
4
effectively using irq 0->3 (shared with other devices). Assuming
5
original intent was to allocate unique IRQs then add an allocation
6
to the irqmap.
7
8
Fixes: e9fdf453240 ("hw/arm: Add arm SBSA reference machine, devices part")
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
12
Message-id: 20201007100732.4103790-3-graeme@nuviainc.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/arm/sbsa-ref.c | 1 +
16
1 file changed, 1 insertion(+)
17
18
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/sbsa-ref.c
21
+++ b/hw/arm/sbsa-ref.c
22
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
23
[SBSA_SECURE_UART_MM] = 9,
24
[SBSA_AHCI] = 10,
25
[SBSA_EHCI] = 11,
26
+ [SBSA_SMMU] = 12, /* ... to 15 */
27
};
28
29
static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
30
--
31
2.20.1
32
33
diff view generated by jsdifflib
New patch
[PULL 05/12] hw/char/bcm2835_aux: Allow less than 32-bit accesses
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
The "BCM2835 ARM Peripherals" datasheet [*] chapter 2
4
("Auxiliaries: UART1 & SPI1, SPI2"), list the register
5
sizes as 3/8/16/32 bits. We assume this means this
6
peripheral allows 8-bit accesses.
7
8
This was not an issue until commit 5d971f9e67 which reverted
9
("memory: accept mismatching sizes in memory_region_access_valid").
10
11
The model is implemented as 32-bit accesses (see commit 97398d900c,
12
all registers are 32-bit) so replace MemoryRegionOps.valid as
13
MemoryRegionOps.impl, and re-introduce MemoryRegionOps.valid
14
with a 8/32-bit range.
15
16
[*] https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
17
18
Fixes: 97398d900c ("bcm2835_aux: add emulation of BCM2835 AUX (aka UART1) block")
19
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
Message-id: 20201002181032.1899463-1-f4bug@amsat.org
21
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
---
24
hw/char/bcm2835_aux.c | 4 +++-
25
1 file changed, 3 insertions(+), 1 deletion(-)
26
27
diff --git a/hw/char/bcm2835_aux.c b/hw/char/bcm2835_aux.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/char/bcm2835_aux.c
30
+++ b/hw/char/bcm2835_aux.c
31
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps bcm2835_aux_ops = {
32
.read = bcm2835_aux_read,
33
.write = bcm2835_aux_write,
34
.endianness = DEVICE_NATIVE_ENDIAN,
35
- .valid.min_access_size = 4,
36
+ .impl.min_access_size = 4,
37
+ .impl.max_access_size = 4,
38
+ .valid.min_access_size = 1,
39
.valid.max_access_size = 4,
40
};
41
42
--
43
2.20.1
44
45
diff view generated by jsdifflib
New patch
[PULL 06/12] linux headers: sync to 5.9-rc7
1
From: Andrew Jones <drjones@redhat.com>
1
2
3
Update against Linux 5.9-rc7.
4
5
Cc: Paolo Bonzini <pbonzini@redhat.com>
6
Signed-off-by: Andrew Jones <drjones@redhat.com>
7
Message-id: 20201001061718.101915-2-drjones@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
linux-headers/linux/kvm.h | 6 ++++--
11
1 file changed, 4 insertions(+), 2 deletions(-)
12
13
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/linux-headers/linux/kvm.h
16
+++ b/linux-headers/linux/kvm.h
17
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_resize_hpt {
18
#define KVM_VM_PPC_HV 1
19
#define KVM_VM_PPC_PR 2
20
21
-/* on MIPS, 0 forces trap & emulate, 1 forces VZ ASE */
22
-#define KVM_VM_MIPS_TE        0
23
+/* on MIPS, 0 indicates auto, 1 forces VZ ASE, 2 forces trap & emulate */
24
+#define KVM_VM_MIPS_AUTO    0
25
#define KVM_VM_MIPS_VZ        1
26
+#define KVM_VM_MIPS_TE        2
27
28
#define KVM_S390_SIE_PAGE_OFFSET 1
29
30
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_resize_hpt {
31
#define KVM_CAP_LAST_CPU 184
32
#define KVM_CAP_SMALLER_MAXPHYADDR 185
33
#define KVM_CAP_S390_DIAG318 186
34
+#define KVM_CAP_STEAL_TIME 187
35
36
#ifdef KVM_CAP_IRQ_ROUTING
37
38
--
39
2.20.1
40
41
diff view generated by jsdifflib
[PULL 4/4] target/arm: Honor HCR_EL2.TID3 trapping requirements
[PULL 07/12] target/arm/kvm: Make uncalled stubs explicitly unreachable
1
From: Marc Zyngier <maz@kernel.org>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
HCR_EL2.TID3 mandates that access from EL1 to a long list of id
3
When we compile without KVM support !defined(CONFIG_KVM) we generate
4
registers traps to EL2, and QEMU has so far ignored this requirement.
4
stubs for functions that the linker will still encounter. Sometimes
5
these stubs can be executed safely and are placed in paths where they
6
get executed with or without KVM. Other functions should never be
7
called without KVM. Those functions should be guarded by kvm_enabled(),
8
but should also be robust to refactoring mistakes. Putting a
9
g_assert_not_reached() in the function should help. Additionally,
10
the g_assert_not_reached() calls may actually help the linker remove
11
some code.
5
12
6
This breaks (among other things) KVM guests that have PtrAuth enabled,
13
We remove the stubs for kvm_arm_get/put_virtual_time(), as they aren't
7
while the hypervisor doesn't want to expose the feature to its guest.
14
necessary at all - the only caller is in kvm.c
8
To achieve this, KVM traps the ID registers (ID_AA64ISAR1_EL1 in this
9
case), and masks out the unsupported feature.
10
15
11
QEMU not honoring the trap request means that the guest observes
16
Reviewed-by: Eric Auger <eric.auger@redhat.com>
12
that the feature is present in the HW, starts using it, and dies
17
Signed-off-by: Andrew Jones <drjones@redhat.com>
13
a horrible death when KVM injects an UNDEF, because the feature
18
Message-id: 20201001061718.101915-3-drjones@redhat.com
14
*really* isn't supported.
15
16
Do the right thing by trapping to EL2 if HCR_EL2.TID3 is set.
17
18
Note that this change does not include trapping of the MVFR
19
registers from AArch32 (they are accessed via the VMRS
20
instruction and need to be handled in a different way).
21
22
Reported-by: Will Deacon <will@kernel.org>
23
Signed-off-by: Marc Zyngier <maz@kernel.org>
24
Tested-by: Will Deacon <will@kernel.org>
25
Message-id: 20191123115618.29230-1-maz@kernel.org
26
[PMM: added missing accessfn line for ID_AA4PFR2_EL1_RESERVED;
27
changed names of access functions to include _tid3]
28
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
---
20
---
31
target/arm/helper.c | 76 +++++++++++++++++++++++++++++++++++++++++++++
21
target/arm/kvm_arm.h | 51 +++++++++++++++++++++++++++-----------------
32
1 file changed, 76 insertions(+)
22
1 file changed, 32 insertions(+), 19 deletions(-)
33
23
34
diff --git a/target/arm/helper.c b/target/arm/helper.c
24
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
35
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/helper.c
26
--- a/target/arm/kvm_arm.h
37
+++ b/target/arm/helper.c
27
+++ b/target/arm/kvm_arm.h
38
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = {
28
@@ -XXX,XX +XXX,XX @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level);
39
REGINFO_SENTINEL
29
40
};
30
#else
41
31
42
+static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
32
-static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
43
+ bool isread)
33
-{
34
- /*
35
- * This should never actually be called in the "not KVM" case,
36
- * but set up the fields to indicate an error anyway.
37
- */
38
- cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
39
- cpu->host_cpu_probe_failed = true;
40
-}
41
-
42
-static inline void kvm_arm_add_vcpu_properties(Object *obj) {}
43
-
44
+/*
45
+ * It's safe to call these functions without KVM support.
46
+ * They should either do nothing or return "not supported".
47
+ */
48
static inline bool kvm_arm_aarch32_supported(void)
49
{
50
return false;
51
@@ -XXX,XX +XXX,XX @@ static inline bool kvm_arm_sve_supported(void)
52
return false;
53
}
54
55
+/*
56
+ * These functions should never actually be called without KVM support.
57
+ */
58
+static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
44
+{
59
+{
45
+ if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) {
60
+ g_assert_not_reached();
46
+ return CP_ACCESS_TRAP_EL2;
47
+ }
48
+
49
+ return CP_ACCESS_OK;
50
+}
61
+}
51
+
62
+
52
+static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
63
+static inline void kvm_arm_add_vcpu_properties(Object *obj)
53
+ bool isread)
54
+{
64
+{
55
+ if (arm_feature(env, ARM_FEATURE_V8)) {
65
+ g_assert_not_reached();
56
+ return access_aa64_tid3(env, ri, isread);
57
+ }
58
+
59
+ return CP_ACCESS_OK;
60
+}
66
+}
61
+
67
+
62
void register_cp_regs_for_features(ARMCPU *cpu)
68
static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
63
{
69
{
64
/* Register all the coprocessor registers based on feature bits */
70
- return -ENOENT;
65
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
71
+ g_assert_not_reached();
66
{ .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
72
}
67
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
73
68
.access = PL1_R, .type = ARM_CP_CONST,
74
static inline int kvm_arm_vgic_probe(void)
69
+ .accessfn = access_aa32_tid3,
75
{
70
.resetvalue = cpu->id_pfr0 },
76
- return 0;
71
/* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
77
+ g_assert_not_reached();
72
* the value of the GIC field until after we define these regs.
78
}
73
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
79
74
{ .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
80
-static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {}
75
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
81
-static inline void kvm_arm_pmu_init(CPUState *cs) {}
76
.access = PL1_R, .type = ARM_CP_NO_RAW,
82
+static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
77
+ .accessfn = access_aa32_tid3,
83
+{
78
.readfn = id_pfr1_read,
84
+ g_assert_not_reached();
79
.writefn = arm_cp_write_ignore },
85
+}
80
{ .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
86
81
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
87
-static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) {}
82
.access = PL1_R, .type = ARM_CP_CONST,
88
+static inline void kvm_arm_pmu_init(CPUState *cs)
83
+ .accessfn = access_aa32_tid3,
89
+{
84
.resetvalue = cpu->id_dfr0 },
90
+ g_assert_not_reached();
85
{ .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
91
+}
86
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
92
+
87
.access = PL1_R, .type = ARM_CP_CONST,
93
+static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map)
88
+ .accessfn = access_aa32_tid3,
94
+{
89
.resetvalue = cpu->id_afr0 },
95
+ g_assert_not_reached();
90
{ .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
96
+}
91
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
97
92
.access = PL1_R, .type = ARM_CP_CONST,
98
-static inline void kvm_arm_get_virtual_time(CPUState *cs) {}
93
+ .accessfn = access_aa32_tid3,
99
-static inline void kvm_arm_put_virtual_time(CPUState *cs) {}
94
.resetvalue = cpu->id_mmfr0 },
100
#endif
95
{ .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
101
96
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
102
static inline const char *gic_class_name(void)
97
.access = PL1_R, .type = ARM_CP_CONST,
98
+ .accessfn = access_aa32_tid3,
99
.resetvalue = cpu->id_mmfr1 },
100
{ .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
101
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
102
.access = PL1_R, .type = ARM_CP_CONST,
103
+ .accessfn = access_aa32_tid3,
104
.resetvalue = cpu->id_mmfr2 },
105
{ .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
106
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
107
.access = PL1_R, .type = ARM_CP_CONST,
108
+ .accessfn = access_aa32_tid3,
109
.resetvalue = cpu->id_mmfr3 },
110
{ .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
111
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
112
.access = PL1_R, .type = ARM_CP_CONST,
113
+ .accessfn = access_aa32_tid3,
114
.resetvalue = cpu->isar.id_isar0 },
115
{ .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
116
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
117
.access = PL1_R, .type = ARM_CP_CONST,
118
+ .accessfn = access_aa32_tid3,
119
.resetvalue = cpu->isar.id_isar1 },
120
{ .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
121
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
122
.access = PL1_R, .type = ARM_CP_CONST,
123
+ .accessfn = access_aa32_tid3,
124
.resetvalue = cpu->isar.id_isar2 },
125
{ .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
126
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
127
.access = PL1_R, .type = ARM_CP_CONST,
128
+ .accessfn = access_aa32_tid3,
129
.resetvalue = cpu->isar.id_isar3 },
130
{ .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
131
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
132
.access = PL1_R, .type = ARM_CP_CONST,
133
+ .accessfn = access_aa32_tid3,
134
.resetvalue = cpu->isar.id_isar4 },
135
{ .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
136
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
137
.access = PL1_R, .type = ARM_CP_CONST,
138
+ .accessfn = access_aa32_tid3,
139
.resetvalue = cpu->isar.id_isar5 },
140
{ .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
141
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
142
.access = PL1_R, .type = ARM_CP_CONST,
143
+ .accessfn = access_aa32_tid3,
144
.resetvalue = cpu->id_mmfr4 },
145
{ .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
146
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
147
.access = PL1_R, .type = ARM_CP_CONST,
148
+ .accessfn = access_aa32_tid3,
149
.resetvalue = cpu->isar.id_isar6 },
150
REGINFO_SENTINEL
151
};
152
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
153
{ .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
154
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
155
.access = PL1_R, .type = ARM_CP_NO_RAW,
156
+ .accessfn = access_aa64_tid3,
157
.readfn = id_aa64pfr0_read,
158
.writefn = arm_cp_write_ignore },
159
{ .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
160
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
161
.access = PL1_R, .type = ARM_CP_CONST,
162
+ .accessfn = access_aa64_tid3,
163
.resetvalue = cpu->isar.id_aa64pfr1},
164
{ .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
165
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
166
.access = PL1_R, .type = ARM_CP_CONST,
167
+ .accessfn = access_aa64_tid3,
168
.resetvalue = 0 },
169
{ .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
170
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
171
.access = PL1_R, .type = ARM_CP_CONST,
172
+ .accessfn = access_aa64_tid3,
173
.resetvalue = 0 },
174
{ .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64,
175
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
176
.access = PL1_R, .type = ARM_CP_CONST,
177
+ .accessfn = access_aa64_tid3,
178
/* At present, only SVEver == 0 is defined anyway. */
179
.resetvalue = 0 },
180
{ .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
181
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
182
.access = PL1_R, .type = ARM_CP_CONST,
183
+ .accessfn = access_aa64_tid3,
184
.resetvalue = 0 },
185
{ .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
186
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
187
.access = PL1_R, .type = ARM_CP_CONST,
188
+ .accessfn = access_aa64_tid3,
189
.resetvalue = 0 },
190
{ .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
191
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
192
.access = PL1_R, .type = ARM_CP_CONST,
193
+ .accessfn = access_aa64_tid3,
194
.resetvalue = 0 },
195
{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
196
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
197
.access = PL1_R, .type = ARM_CP_CONST,
198
+ .accessfn = access_aa64_tid3,
199
.resetvalue = cpu->id_aa64dfr0 },
200
{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
201
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
202
.access = PL1_R, .type = ARM_CP_CONST,
203
+ .accessfn = access_aa64_tid3,
204
.resetvalue = cpu->id_aa64dfr1 },
205
{ .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
206
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
207
.access = PL1_R, .type = ARM_CP_CONST,
208
+ .accessfn = access_aa64_tid3,
209
.resetvalue = 0 },
210
{ .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
211
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
212
.access = PL1_R, .type = ARM_CP_CONST,
213
+ .accessfn = access_aa64_tid3,
214
.resetvalue = 0 },
215
{ .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
216
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
217
.access = PL1_R, .type = ARM_CP_CONST,
218
+ .accessfn = access_aa64_tid3,
219
.resetvalue = cpu->id_aa64afr0 },
220
{ .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
221
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
222
.access = PL1_R, .type = ARM_CP_CONST,
223
+ .accessfn = access_aa64_tid3,
224
.resetvalue = cpu->id_aa64afr1 },
225
{ .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
226
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
227
.access = PL1_R, .type = ARM_CP_CONST,
228
+ .accessfn = access_aa64_tid3,
229
.resetvalue = 0 },
230
{ .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
231
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
232
.access = PL1_R, .type = ARM_CP_CONST,
233
+ .accessfn = access_aa64_tid3,
234
.resetvalue = 0 },
235
{ .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
236
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
237
.access = PL1_R, .type = ARM_CP_CONST,
238
+ .accessfn = access_aa64_tid3,
239
.resetvalue = cpu->isar.id_aa64isar0 },
240
{ .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
241
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
242
.access = PL1_R, .type = ARM_CP_CONST,
243
+ .accessfn = access_aa64_tid3,
244
.resetvalue = cpu->isar.id_aa64isar1 },
245
{ .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
246
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
247
.access = PL1_R, .type = ARM_CP_CONST,
248
+ .accessfn = access_aa64_tid3,
249
.resetvalue = 0 },
250
{ .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
251
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
252
.access = PL1_R, .type = ARM_CP_CONST,
253
+ .accessfn = access_aa64_tid3,
254
.resetvalue = 0 },
255
{ .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
256
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
257
.access = PL1_R, .type = ARM_CP_CONST,
258
+ .accessfn = access_aa64_tid3,
259
.resetvalue = 0 },
260
{ .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
261
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
262
.access = PL1_R, .type = ARM_CP_CONST,
263
+ .accessfn = access_aa64_tid3,
264
.resetvalue = 0 },
265
{ .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
266
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
267
.access = PL1_R, .type = ARM_CP_CONST,
268
+ .accessfn = access_aa64_tid3,
269
.resetvalue = 0 },
270
{ .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
271
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
272
.access = PL1_R, .type = ARM_CP_CONST,
273
+ .accessfn = access_aa64_tid3,
274
.resetvalue = 0 },
275
{ .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
276
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
277
.access = PL1_R, .type = ARM_CP_CONST,
278
+ .accessfn = access_aa64_tid3,
279
.resetvalue = cpu->isar.id_aa64mmfr0 },
280
{ .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
281
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
282
.access = PL1_R, .type = ARM_CP_CONST,
283
+ .accessfn = access_aa64_tid3,
284
.resetvalue = cpu->isar.id_aa64mmfr1 },
285
{ .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
286
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
287
.access = PL1_R, .type = ARM_CP_CONST,
288
+ .accessfn = access_aa64_tid3,
289
.resetvalue = 0 },
290
{ .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
291
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
292
.access = PL1_R, .type = ARM_CP_CONST,
293
+ .accessfn = access_aa64_tid3,
294
.resetvalue = 0 },
295
{ .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
296
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
297
.access = PL1_R, .type = ARM_CP_CONST,
298
+ .accessfn = access_aa64_tid3,
299
.resetvalue = 0 },
300
{ .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
301
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
302
.access = PL1_R, .type = ARM_CP_CONST,
303
+ .accessfn = access_aa64_tid3,
304
.resetvalue = 0 },
305
{ .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
306
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
307
.access = PL1_R, .type = ARM_CP_CONST,
308
+ .accessfn = access_aa64_tid3,
309
.resetvalue = 0 },
310
{ .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
311
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
312
.access = PL1_R, .type = ARM_CP_CONST,
313
+ .accessfn = access_aa64_tid3,
314
.resetvalue = 0 },
315
{ .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
316
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
317
.access = PL1_R, .type = ARM_CP_CONST,
318
+ .accessfn = access_aa64_tid3,
319
.resetvalue = cpu->isar.mvfr0 },
320
{ .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
321
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
322
.access = PL1_R, .type = ARM_CP_CONST,
323
+ .accessfn = access_aa64_tid3,
324
.resetvalue = cpu->isar.mvfr1 },
325
{ .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
326
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
327
.access = PL1_R, .type = ARM_CP_CONST,
328
+ .accessfn = access_aa64_tid3,
329
.resetvalue = cpu->isar.mvfr2 },
330
{ .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
331
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
332
.access = PL1_R, .type = ARM_CP_CONST,
333
+ .accessfn = access_aa64_tid3,
334
.resetvalue = 0 },
335
{ .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
336
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
337
.access = PL1_R, .type = ARM_CP_CONST,
338
+ .accessfn = access_aa64_tid3,
339
.resetvalue = 0 },
340
{ .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
341
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
342
.access = PL1_R, .type = ARM_CP_CONST,
343
+ .accessfn = access_aa64_tid3,
344
.resetvalue = 0 },
345
{ .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
346
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
347
.access = PL1_R, .type = ARM_CP_CONST,
348
+ .accessfn = access_aa64_tid3,
349
.resetvalue = 0 },
350
{ .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
351
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
352
.access = PL1_R, .type = ARM_CP_CONST,
353
+ .accessfn = access_aa64_tid3,
354
.resetvalue = 0 },
355
{ .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
356
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
357
--
103
--
358
2.20.1
104
2.20.1
359
105
360
106
diff view generated by jsdifflib
New patch
[PULL 08/12] hw/arm/virt: Move post cpu realize check into its own function
1
From: Andrew Jones <drjones@redhat.com>
1
2
3
We'll add more to this new function in coming patches so we also
4
state the gic must be created and call it below create_gic().
5
6
No functional change intended.
7
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Andrew Jones <drjones@redhat.com>
11
Message-id: 20201001061718.101915-4-drjones@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/virt.c | 43 +++++++++++++++++++++++++++----------------
15
1 file changed, 27 insertions(+), 16 deletions(-)
16
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/virt.c
20
+++ b/hw/arm/virt.c
21
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
22
}
23
}
24
25
+/*
26
+ * virt_cpu_post_init() must be called after the CPUs have
27
+ * been realized and the GIC has been created.
28
+ */
29
+static void virt_cpu_post_init(VirtMachineState *vms)
30
+{
31
+ bool aarch64;
32
+
33
+ aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
34
+
35
+ if (!kvm_enabled()) {
36
+ if (aarch64 && vms->highmem) {
37
+ int requested_pa_size = 64 - clz64(vms->highest_gpa);
38
+ int pamax = arm_pamax(ARM_CPU(first_cpu));
39
+
40
+ if (pamax < requested_pa_size) {
41
+ error_report("VCPU supports less PA bits (%d) than "
42
+ "requested by the memory map (%d)",
43
+ pamax, requested_pa_size);
44
+ exit(1);
45
+ }
46
+ }
47
+ }
48
+}
49
+
50
static void machvirt_init(MachineState *machine)
51
{
52
VirtMachineState *vms = VIRT_MACHINE(machine);
53
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
54
fdt_add_timer_nodes(vms);
55
fdt_add_cpu_nodes(vms);
56
57
- if (!kvm_enabled()) {
58
- ARMCPU *cpu = ARM_CPU(first_cpu);
59
- bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL);
60
-
61
- if (aarch64 && vms->highmem) {
62
- int requested_pa_size, pamax = arm_pamax(cpu);
63
-
64
- requested_pa_size = 64 - clz64(vms->highest_gpa);
65
- if (pamax < requested_pa_size) {
66
- error_report("VCPU supports less PA bits (%d) than requested "
67
- "by the memory map (%d)", pamax, requested_pa_size);
68
- exit(1);
69
- }
70
- }
71
- }
72
-
73
memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
74
machine->ram);
75
if (machine->device_memory) {
76
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
77
78
create_gic(vms);
79
80
+ virt_cpu_post_init(vms);
81
+
82
fdt_add_pmu_nodes(vms);
83
84
create_uart(vms, VIRT_UART, sysmem, serial_hd(0));
85
--
86
2.20.1
87
88
diff view generated by jsdifflib
[PULL 3/4] target/arm: Fix ISR_EL1 tracking when executing at EL2
[PULL 09/12] hw/arm/virt: Move kvm pmu setup to virt_cpu_post_init
1
From: Marc Zyngier <maz@kernel.org>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
The ARMv8 ARM states when executing at EL2, EL3 or Secure EL1,
3
Move the KVM PMU setup part of fdt_add_pmu_nodes() to
4
ISR_EL1 shows the pending status of the physical IRQ, FIQ, or
4
virt_cpu_post_init(), which is a more appropriate location. Now
5
SError interrupts.
5
fdt_add_pmu_nodes() is also named more appropriately, because it
6
no longer does anything but fdt node creation.
6
7
7
Unfortunately, QEMU's implementation only considers the HCR_EL2
8
No functional change intended.
8
bits, and ignores the current exception level. This means a hypervisor
9
trying to look at its own interrupt state actually sees the guest
10
state, which is unexpected and breaks KVM as of Linux 5.3.
11
9
12
Instead, check for the running EL and return the physical bits
13
if not running in a virtualized context.
14
15
Fixes: 636540e9c40b
16
Cc: qemu-stable@nongnu.org
17
Reported-by: Quentin Perret <qperret@google.com>
18
Signed-off-by: Marc Zyngier <maz@kernel.org>
19
Message-id: 20191122135833.28953-1-maz@kernel.org
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
21
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
12
Signed-off-by: Andrew Jones <drjones@redhat.com>
13
Message-id: 20201001061718.101915-5-drjones@redhat.com
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
---
15
---
24
target/arm/helper.c | 7 +++++--
16
hw/arm/virt.c | 34 ++++++++++++++++++----------------
25
1 file changed, 5 insertions(+), 2 deletions(-)
17
1 file changed, 18 insertions(+), 16 deletions(-)
26
18
27
diff --git a/target/arm/helper.c b/target/arm/helper.c
19
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
28
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/helper.c
21
--- a/hw/arm/virt.c
30
+++ b/target/arm/helper.c
22
+++ b/hw/arm/virt.c
31
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
23
@@ -XXX,XX +XXX,XX @@ static void fdt_add_gic_node(VirtMachineState *vms)
32
CPUState *cs = env_cpu(env);
24
33
uint64_t hcr_el2 = arm_hcr_el2_eff(env);
25
static void fdt_add_pmu_nodes(const VirtMachineState *vms)
34
uint64_t ret = 0;
26
{
35
+ bool allow_virt = (arm_current_el(env) == 1 &&
27
- CPUState *cpu;
36
+ (!arm_is_secure_below_el3(env) ||
28
- ARMCPU *armcpu;
37
+ (env->cp15.scr_el3 & SCR_EEL2)));
29
+ ARMCPU *armcpu = ARM_CPU(first_cpu);
38
30
uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
39
- if (hcr_el2 & HCR_IMO) {
31
40
+ if (allow_virt && (hcr_el2 & HCR_IMO)) {
32
- CPU_FOREACH(cpu) {
41
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
33
- armcpu = ARM_CPU(cpu);
42
ret |= CPSR_I;
34
- if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
43
}
35
- return;
44
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
36
- }
45
}
37
- if (kvm_enabled()) {
38
- if (kvm_irqchip_in_kernel()) {
39
- kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
40
- }
41
- kvm_arm_pmu_init(cpu);
42
- }
43
+ if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
44
+ assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
45
+ return;
46
}
46
}
47
47
48
- if (hcr_el2 & HCR_FMO) {
48
if (vms->gic_version == VIRT_GIC_VERSION_2) {
49
+ if (allow_virt && (hcr_el2 & HCR_FMO)) {
49
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)
50
if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
50
(1 << vms->smp_cpus) - 1);
51
ret |= CPSR_F;
51
}
52
}
52
53
- armcpu = ARM_CPU(qemu_get_cpu(0));
54
qemu_fdt_add_subnode(vms->fdt, "/pmu");
55
if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
56
const char compat[] = "arm,armv8-pmuv3";
57
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
58
*/
59
static void virt_cpu_post_init(VirtMachineState *vms)
60
{
61
- bool aarch64;
62
+ bool aarch64, pmu;
63
+ CPUState *cpu;
64
65
aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
66
+ pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
67
68
- if (!kvm_enabled()) {
69
+ if (kvm_enabled()) {
70
+ CPU_FOREACH(cpu) {
71
+ if (pmu) {
72
+ assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
73
+ if (kvm_irqchip_in_kernel()) {
74
+ kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
75
+ }
76
+ kvm_arm_pmu_init(cpu);
77
+ }
78
+ }
79
+ } else {
80
if (aarch64 && vms->highmem) {
81
int requested_pa_size = 64 - clz64(vms->highest_gpa);
82
int pamax = arm_pamax(ARM_CPU(first_cpu));
53
--
83
--
54
2.20.1
84
2.20.1
55
85
56
86
diff view generated by jsdifflib
[PULL 1/4] target/arm: Fix handling of cortex-m FTYPE flag in EXCRET
[PULL 10/12] tests/qtest: Restore aarch64 arm-cpu-features test
1
From: Jean-Hugues Deschênes <Jean-Hugues.Deschenes@ossiaco.com>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
According to the PushStack() pseudocode in the armv7m RM,
3
arm-cpu-features got dropped from the AArch64 tests during the meson
4
bit 4 of the LR should be set to NOT(CONTROL.PFCA) when
4
conversion shuffle.
5
an FPU is present. Current implementation is doing it for
6
armv8, but not for armv7. This patch makes the existing
7
logic applicable to both code paths.
8
5
9
Signed-off-by: Jean-Hugues Deschenes <jean-hugues.deschenes@ossiaco.com>
6
Signed-off-by: Andrew Jones <drjones@redhat.com>
7
Message-id: 20201001061718.101915-6-drjones@redhat.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
target/arm/m_helper.c | 7 +++----
11
tests/qtest/meson.build | 3 ++-
14
1 file changed, 3 insertions(+), 4 deletions(-)
12
1 file changed, 2 insertions(+), 1 deletion(-)
15
13
16
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
14
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/m_helper.c
16
--- a/tests/qtest/meson.build
19
+++ b/target/arm/m_helper.c
17
+++ b/tests/qtest/meson.build
20
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
18
@@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \
21
if (env->v7m.secure) {
19
(cpu != 'arm' ? ['bios-tables-test'] : []) + \
22
lr |= R_V7M_EXCRET_S_MASK;
20
(config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \
23
}
21
(config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \
24
- if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
22
- ['numa-test',
25
- lr |= R_V7M_EXCRET_FTYPE_MASK;
23
+ ['arm-cpu-features',
26
- }
24
+ 'numa-test',
27
} else {
25
'boot-serial-test',
28
lr = R_V7M_EXCRET_RES1_MASK |
26
'migration-test']
29
R_V7M_EXCRET_S_MASK |
27
30
R_V7M_EXCRET_DCRS_MASK |
31
- R_V7M_EXCRET_FTYPE_MASK |
32
R_V7M_EXCRET_ES_MASK;
33
if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) {
34
lr |= R_V7M_EXCRET_SPSEL_MASK;
35
}
36
}
37
+ if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
38
+ lr |= R_V7M_EXCRET_FTYPE_MASK;
39
+ }
40
if (!arm_v7m_is_handler_mode(env)) {
41
lr |= R_V7M_EXCRET_MODE_MASK;
42
}
43
--
28
--
44
2.20.1
29
2.20.1
45
30
46
31
diff view generated by jsdifflib
[PULL 2/4] hw/arm: versal: Add the CRP as unimplemented
[PULL 11/12] hw/arm/virt: Implement kvm-steal-time
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
Add the CRP as unimplemented thus avoiding bus errors when
3
We add the kvm-steal-time CPU property and implement it for machvirt.
4
guests access these registers.
4
A tiny bit of refactoring was also done to allow pmu and pvtime to
5
use the same vcpu device helper functions.
5
6
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Reviewed-by: Eric Auger <eric.auger@redhat.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Signed-off-by: Andrew Jones <drjones@redhat.com>
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
Message-id: 20201001061718.101915-7-drjones@redhat.com
9
Message-id: 20191115154734.26449-2-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
include/hw/arm/xlnx-versal.h | 3 +++
12
docs/system/arm/cpu-features.rst | 11 ++++++
13
hw/arm/xlnx-versal.c | 2 ++
13
include/hw/arm/virt.h | 5 +++
14
2 files changed, 5 insertions(+)
14
target/arm/cpu.h | 4 ++
15
target/arm/kvm_arm.h | 43 +++++++++++++++++++++
16
hw/arm/virt.c | 43 +++++++++++++++++++--
17
target/arm/cpu.c | 8 ++++
18
target/arm/kvm.c | 16 ++++++++
19
target/arm/kvm64.c | 64 +++++++++++++++++++++++++++++---
20
target/arm/monitor.c | 2 +-
21
tests/qtest/arm-cpu-features.c | 25 +++++++++++--
22
10 files changed, 208 insertions(+), 13 deletions(-)
15
23
16
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
24
diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst
17
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/xlnx-versal.h
26
--- a/docs/system/arm/cpu-features.rst
19
+++ b/include/hw/arm/xlnx-versal.h
27
+++ b/docs/system/arm/cpu-features.rst
20
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
28
@@ -XXX,XX +XXX,XX @@ the list of KVM VCPU features and their descriptions.
21
#define MM_IOU_SCNTRS_SIZE 0x10000
29
adjustment, also restoring the legacy (pre-5.0)
22
#define MM_FPD_CRF 0xfd1a0000U
30
behavior.
23
#define MM_FPD_CRF_SIZE 0x140000
31
24
+
32
+ kvm-steal-time Since v5.2, kvm-steal-time is enabled by
25
+#define MM_PMC_CRP 0xf1260000U
33
+ default when KVM is enabled, the feature is
26
+#define MM_PMC_CRP_SIZE 0x10000
34
+ supported, and the guest is 64-bit.
27
#endif
35
+
28
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
36
+ When kvm-steal-time is enabled a 64-bit guest
29
index XXXXXXX..XXXXXXX 100644
37
+ can account for time its CPUs were not running
30
--- a/hw/arm/xlnx-versal.c
38
+ due to the host not scheduling the corresponding
31
+++ b/hw/arm/xlnx-versal.c
39
+ VCPU threads. The accounting statistics may
32
@@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s)
40
+ influence the guest scheduler behavior and/or be
33
MM_CRL, MM_CRL_SIZE);
41
+ exposed to the guest userspace.
34
versal_unimp_area(s, "crf", &s->mr_ps,
42
+
35
MM_FPD_CRF, MM_FPD_CRF_SIZE);
43
SVE CPU Properties
36
+ versal_unimp_area(s, "crp", &s->mr_ps,
44
==================
37
+ MM_PMC_CRP, MM_PMC_CRP_SIZE);
45
38
versal_unimp_area(s, "iou-scntr", &s->mr_ps,
46
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
39
MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
47
index XXXXXXX..XXXXXXX 100644
40
versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,
48
--- a/include/hw/arm/virt.h
49
+++ b/include/hw/arm/virt.h
50
@@ -XXX,XX +XXX,XX @@
51
52
#define PPI(irq) ((irq) + 16)
53
54
+/* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */
55
+#define PVTIME_SIZE_PER_CPU 64
56
+
57
enum {
58
VIRT_FLASH,
59
VIRT_MEM,
60
@@ -XXX,XX +XXX,XX @@ enum {
61
VIRT_PCDIMM_ACPI,
62
VIRT_ACPI_GED,
63
VIRT_NVDIMM_ACPI,
64
+ VIRT_PVTIME,
65
VIRT_LOWMEMMAP_LAST,
66
};
67
68
@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
69
bool no_highmem_ecam;
70
bool no_ged; /* Machines < 4.2 has no support for ACPI GED device */
71
bool kvm_no_adjvtime;
72
+ bool no_kvm_steal_time;
73
bool acpi_expose_flash;
74
};
75
76
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/cpu.h
79
+++ b/target/arm/cpu.h
80
@@ -XXX,XX +XXX,XX @@
81
#include "hw/registerfields.h"
82
#include "cpu-qom.h"
83
#include "exec/cpu-defs.h"
84
+#include "qapi/qapi-types-common.h"
85
86
/* ARM processors have a weak memory model */
87
#define TCG_GUEST_DEFAULT_MO (0)
88
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
89
bool kvm_vtime_dirty;
90
uint64_t kvm_vtime;
91
92
+ /* KVM steal time */
93
+ OnOffAuto kvm_steal_time;
94
+
95
/* Uniprocessor system with MP extensions */
96
bool mp_is_up;
97
98
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/kvm_arm.h
101
+++ b/target/arm/kvm_arm.h
102
@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu);
103
*/
104
void kvm_arm_add_vcpu_properties(Object *obj);
105
106
+/**
107
+ * kvm_arm_steal_time_finalize:
108
+ * @cpu: ARMCPU for which to finalize kvm-steal-time
109
+ * @errp: Pointer to Error* for error propagation
110
+ *
111
+ * Validate the kvm-steal-time property selection and set its default
112
+ * based on KVM support and guest configuration.
113
+ */
114
+void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp);
115
+
116
+/**
117
+ * kvm_arm_steal_time_supported:
118
+ *
119
+ * Returns: true if KVM can enable steal time reporting
120
+ * and false otherwise.
121
+ */
122
+bool kvm_arm_steal_time_supported(void);
123
+
124
/**
125
* kvm_arm_aarch32_supported:
126
*
127
@@ -XXX,XX +XXX,XX @@ int kvm_arm_vgic_probe(void);
128
129
void kvm_arm_pmu_set_irq(CPUState *cs, int irq);
130
void kvm_arm_pmu_init(CPUState *cs);
131
+
132
+/**
133
+ * kvm_arm_pvtime_init:
134
+ * @cs: CPUState
135
+ * @ipa: Per-vcpu guest physical base address of the pvtime structures
136
+ *
137
+ * Initializes PVTIME for the VCPU, setting the PVTIME IPA to @ipa.
138
+ */
139
+void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa);
140
+
141
int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level);
142
143
#else
144
@@ -XXX,XX +XXX,XX @@ static inline bool kvm_arm_sve_supported(void)
145
return false;
146
}
147
148
+static inline bool kvm_arm_steal_time_supported(void)
149
+{
150
+ return false;
151
+}
152
+
153
/*
154
* These functions should never actually be called without KVM support.
155
*/
156
@@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_pmu_init(CPUState *cs)
157
g_assert_not_reached();
158
}
159
160
+static inline void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa)
161
+{
162
+ g_assert_not_reached();
163
+}
164
+
165
+static inline void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp)
166
+{
167
+ g_assert_not_reached();
168
+}
169
+
170
static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map)
171
{
172
g_assert_not_reached();
173
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
174
index XXXXXXX..XXXXXXX 100644
175
--- a/hw/arm/virt.c
176
+++ b/hw/arm/virt.c
177
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry base_memmap[] = {
178
[VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
179
[VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
180
[VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
181
+ [VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
182
[VIRT_MMIO] = { 0x0a000000, 0x00000200 },
183
/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
184
[VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
185
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
186
* virt_cpu_post_init() must be called after the CPUs have
187
* been realized and the GIC has been created.
188
*/
189
-static void virt_cpu_post_init(VirtMachineState *vms)
190
+static void virt_cpu_post_init(VirtMachineState *vms, int max_cpus,
191
+ MemoryRegion *sysmem)
192
{
193
- bool aarch64, pmu;
194
+ bool aarch64, pmu, steal_time;
195
CPUState *cpu;
196
197
aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
198
pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
199
+ steal_time = object_property_get_bool(OBJECT(first_cpu),
200
+ "kvm-steal-time", NULL);
201
202
if (kvm_enabled()) {
203
+ hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
204
+ hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
205
+
206
+ if (steal_time) {
207
+ MemoryRegion *pvtime = g_new(MemoryRegion, 1);
208
+ hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
209
+
210
+ /* The memory region size must be a multiple of host page size. */
211
+ pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
212
+
213
+ if (pvtime_size > pvtime_reg_size) {
214
+ error_report("pvtime requires a %ld byte memory region for "
215
+ "%d CPUs, but only %ld has been reserved",
216
+ pvtime_size, max_cpus, pvtime_reg_size);
217
+ exit(1);
218
+ }
219
+
220
+ memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
221
+ memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
222
+ }
223
+
224
CPU_FOREACH(cpu) {
225
if (pmu) {
226
assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
227
@@ -XXX,XX +XXX,XX @@ static void virt_cpu_post_init(VirtMachineState *vms)
228
}
229
kvm_arm_pmu_init(cpu);
230
}
231
+ if (steal_time) {
232
+ kvm_arm_pvtime_init(cpu, pvtime_reg_base +
233
+ cpu->cpu_index * PVTIME_SIZE_PER_CPU);
234
+ }
235
}
236
} else {
237
if (aarch64 && vms->highmem) {
238
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
239
object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
240
}
241
242
+ if (vmc->no_kvm_steal_time &&
243
+ object_property_find(cpuobj, "kvm-steal-time")) {
244
+ object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
245
+ }
246
+
247
if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
248
object_property_set_bool(cpuobj, "pmu", false, NULL);
249
}
250
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
251
252
create_gic(vms);
253
254
- virt_cpu_post_init(vms);
255
+ virt_cpu_post_init(vms, possible_cpus->len, sysmem);
256
257
fdt_add_pmu_nodes(vms);
258
259
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 2)
260
261
static void virt_machine_5_1_options(MachineClass *mc)
262
{
263
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
264
+
265
virt_machine_5_2_options(mc);
266
compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
267
+ vmc->no_kvm_steal_time = true;
268
}
269
DEFINE_VIRT_MACHINE(5, 1)
270
271
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
272
index XXXXXXX..XXXXXXX 100644
273
--- a/target/arm/cpu.c
274
+++ b/target/arm/cpu.c
275
@@ -XXX,XX +XXX,XX @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
276
return;
277
}
278
}
279
+
280
+ if (kvm_enabled()) {
281
+ kvm_arm_steal_time_finalize(cpu, &local_err);
282
+ if (local_err != NULL) {
283
+ error_propagate(errp, local_err);
284
+ return;
285
+ }
286
+ }
287
}
288
289
static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
290
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
291
index XXXXXXX..XXXXXXX 100644
292
--- a/target/arm/kvm.c
293
+++ b/target/arm/kvm.c
294
@@ -XXX,XX +XXX,XX @@ static void kvm_no_adjvtime_set(Object *obj, bool value, Error **errp)
295
ARM_CPU(obj)->kvm_adjvtime = !value;
296
}
297
298
+static bool kvm_steal_time_get(Object *obj, Error **errp)
299
+{
300
+ return ARM_CPU(obj)->kvm_steal_time != ON_OFF_AUTO_OFF;
301
+}
302
+
303
+static void kvm_steal_time_set(Object *obj, bool value, Error **errp)
304
+{
305
+ ARM_CPU(obj)->kvm_steal_time = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
306
+}
307
+
308
/* KVM VCPU properties should be prefixed with "kvm-". */
309
void kvm_arm_add_vcpu_properties(Object *obj)
310
{
311
@@ -XXX,XX +XXX,XX @@ void kvm_arm_add_vcpu_properties(Object *obj)
312
"the virtual counter. VM stopped time "
313
"will be counted.");
314
}
315
+
316
+ cpu->kvm_steal_time = ON_OFF_AUTO_AUTO;
317
+ object_property_add_bool(obj, "kvm-steal-time", kvm_steal_time_get,
318
+ kvm_steal_time_set);
319
+ object_property_set_description(obj, "kvm-steal-time",
320
+ "Set off to disable KVM steal time.");
321
}
322
323
bool kvm_arm_pmu_supported(void)
324
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
325
index XXXXXXX..XXXXXXX 100644
326
--- a/target/arm/kvm64.c
327
+++ b/target/arm/kvm64.c
328
@@ -XXX,XX +XXX,XX @@
329
#include <linux/kvm.h>
330
331
#include "qemu-common.h"
332
+#include "qapi/error.h"
333
#include "cpu.h"
334
#include "qemu/timer.h"
335
#include "qemu/error-report.h"
336
@@ -XXX,XX +XXX,XX @@ static CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr)
337
return NULL;
338
}
339
340
-static bool kvm_arm_pmu_set_attr(CPUState *cs, struct kvm_device_attr *attr)
341
+static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *attr,
342
+ const char *name)
343
{
344
int err;
345
346
err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr);
347
if (err != 0) {
348
- error_report("PMU: KVM_HAS_DEVICE_ATTR: %s", strerror(-err));
349
+ error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err));
350
return false;
351
}
352
353
err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr);
354
if (err != 0) {
355
- error_report("PMU: KVM_SET_DEVICE_ATTR: %s", strerror(-err));
356
+ error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err));
357
return false;
358
}
359
360
@@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_init(CPUState *cs)
361
if (!ARM_CPU(cs)->has_pmu) {
362
return;
363
}
364
- if (!kvm_arm_pmu_set_attr(cs, &attr)) {
365
+ if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) {
366
error_report("failed to init PMU");
367
abort();
368
}
369
@@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
370
if (!ARM_CPU(cs)->has_pmu) {
371
return;
372
}
373
- if (!kvm_arm_pmu_set_attr(cs, &attr)) {
374
+ if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) {
375
error_report("failed to set irq for PMU");
376
abort();
377
}
378
}
379
380
+void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa)
381
+{
382
+ struct kvm_device_attr attr = {
383
+ .group = KVM_ARM_VCPU_PVTIME_CTRL,
384
+ .attr = KVM_ARM_VCPU_PVTIME_IPA,
385
+ .addr = (uint64_t)&ipa,
386
+ };
387
+
388
+ if (ARM_CPU(cs)->kvm_steal_time == ON_OFF_AUTO_OFF) {
389
+ return;
390
+ }
391
+ if (!kvm_arm_set_device_attr(cs, &attr, "PVTIME IPA")) {
392
+ error_report("failed to init PVTIME IPA");
393
+ abort();
394
+ }
395
+}
396
+
397
static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
398
{
399
uint64_t ret;
400
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
401
return true;
402
}
403
404
+void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp)
405
+{
406
+ bool has_steal_time = kvm_arm_steal_time_supported();
407
+
408
+ if (cpu->kvm_steal_time == ON_OFF_AUTO_AUTO) {
409
+ if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
410
+ cpu->kvm_steal_time = ON_OFF_AUTO_OFF;
411
+ } else {
412
+ cpu->kvm_steal_time = ON_OFF_AUTO_ON;
413
+ }
414
+ } else if (cpu->kvm_steal_time == ON_OFF_AUTO_ON) {
415
+ if (!has_steal_time) {
416
+ error_setg(errp, "'kvm-steal-time' cannot be enabled "
417
+ "on this host");
418
+ return;
419
+ } else if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
420
+ /*
421
+ * DEN0057A chapter 2 says "This specification only covers
422
+ * systems in which the Execution state of the hypervisor
423
+ * as well as EL1 of virtual machines is AArch64.". And,
424
+ * to ensure that, the smc/hvc calls are only specified as
425
+ * smc64/hvc64.
426
+ */
427
+ error_setg(errp, "'kvm-steal-time' cannot be enabled "
428
+ "for AArch32 guests");
429
+ return;
430
+ }
431
+ }
432
+}
433
+
434
bool kvm_arm_aarch32_supported(void)
435
{
436
return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT);
437
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_sve_supported(void)
438
return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE);
439
}
440
441
+bool kvm_arm_steal_time_supported(void)
442
+{
443
+ return kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME);
444
+}
445
+
446
QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1);
447
448
void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map)
449
diff --git a/target/arm/monitor.c b/target/arm/monitor.c
450
index XXXXXXX..XXXXXXX 100644
451
--- a/target/arm/monitor.c
452
+++ b/target/arm/monitor.c
453
@@ -XXX,XX +XXX,XX @@ static const char *cpu_model_advertised_features[] = {
454
"sve128", "sve256", "sve384", "sve512",
455
"sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280",
456
"sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048",
457
- "kvm-no-adjvtime",
458
+ "kvm-no-adjvtime", "kvm-steal-time",
459
NULL
460
};
461
462
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
463
index XXXXXXX..XXXXXXX 100644
464
--- a/tests/qtest/arm-cpu-features.c
465
+++ b/tests/qtest/arm-cpu-features.c
466
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
467
assert_set_feature(qts, "max", "pmu", true);
468
469
assert_has_not_feature(qts, "max", "kvm-no-adjvtime");
470
+ assert_has_not_feature(qts, "max", "kvm-steal-time");
471
472
if (g_str_equal(qtest_get_arch(), "aarch64")) {
473
assert_has_feature_enabled(qts, "max", "aarch64");
474
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
475
assert_set_feature(qts, "host", "kvm-no-adjvtime", false);
476
477
if (g_str_equal(qtest_get_arch(), "aarch64")) {
478
+ bool kvm_supports_steal_time;
479
bool kvm_supports_sve;
480
char max_name[8], name[8];
481
uint32_t max_vq, vq;
482
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
483
QDict *resp;
484
char *error;
485
486
+ assert_error(qts, "cortex-a15",
487
+ "We cannot guarantee the CPU type 'cortex-a15' works "
488
+ "with KVM on this host", NULL);
489
+
490
assert_has_feature_enabled(qts, "host", "aarch64");
491
492
/* Enabling and disabling pmu should always work. */
493
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
494
assert_set_feature(qts, "host", "pmu", false);
495
assert_set_feature(qts, "host", "pmu", true);
496
497
- assert_error(qts, "cortex-a15",
498
- "We cannot guarantee the CPU type 'cortex-a15' works "
499
- "with KVM on this host", NULL);
500
-
501
+ /*
502
+ * Some features would be enabled by default, but they're disabled
503
+ * because this instance of KVM doesn't support them. Test that the
504
+ * features are present, and, when enabled, issue further tests.
505
+ */
506
+ assert_has_feature(qts, "host", "kvm-steal-time");
507
assert_has_feature(qts, "host", "sve");
508
+
509
resp = do_query_no_props(qts, "host");
510
+ kvm_supports_steal_time = resp_get_feature(resp, "kvm-steal-time");
511
kvm_supports_sve = resp_get_feature(resp, "sve");
512
vls = resp_get_sve_vls(resp);
513
qobject_unref(resp);
514
515
+ if (kvm_supports_steal_time) {
516
+ /* If we have steal-time then we should be able to toggle it. */
517
+ assert_set_feature(qts, "host", "kvm-steal-time", false);
518
+ assert_set_feature(qts, "host", "kvm-steal-time", true);
519
+ }
520
+
521
if (kvm_supports_sve) {
522
g_assert(vls != 0);
523
max_vq = 64 - __builtin_clzll(vls);
524
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
525
assert_has_not_feature(qts, "host", "aarch64");
526
assert_has_not_feature(qts, "host", "pmu");
527
assert_has_not_feature(qts, "host", "sve");
528
+ assert_has_not_feature(qts, "host", "kvm-steal-time");
529
}
530
531
qtest_quit(qts);
41
--
532
--
42
2.20.1
533
2.20.1
43
534
44
535
diff view generated by jsdifflib
New patch
[PULL 12/12] target/arm: Make '-cpu max' have a 48-bit PA
1
QEMU supports a 48-bit physical address range, but we don't currently
2
expose it in the '-cpu max' ID registers (you get the same range as
3
Cortex-A57, which is 44 bits).
1
4
5
Set the ID_AA64MMFR0.PARange field to indicate 48 bits.
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20201001160116.18095-1-peter.maydell@linaro.org
10
---
11
target/arm/cpu64.c | 4 ++++
12
1 file changed, 4 insertions(+)
13
14
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu64.c
17
+++ b/target/arm/cpu64.c
18
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
19
t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);
20
cpu->isar.id_aa64pfr1 = t;
21
22
+ t = cpu->isar.id_aa64mmfr0;
23
+ t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */
24
+ cpu->isar.id_aa64mmfr0 = t;
25
+
26
t = cpu->isar.id_aa64mmfr1;
27
t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
28
t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
29
--
30
2.20.1
31
32
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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