[PULL 0/4] target-arm queue
[PULL 00/18] target-arm queue
1
Arm patches for rc3 : just a handful of bug fixes.
1
Nothing very exciting this time around...
2
2
3
thanks
4
-- PMM
3
-- PMM
5
4
5
The following changes since commit 37a712a0f969ca2df7f01182409a6c4825cebfb5:
6
6
7
The following changes since commit 4ecc984210ca1bf508a96a550ec8a93a5f833f6c:
7
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2020-10-01 12:23:19 +0100)
8
9
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc3' into staging (2019-11-26 12:36:40 +0000)
10
8
11
are available in the Git repository at:
9
are available in the Git repository at:
12
10
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191126
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201001
14
12
15
for you to fetch changes up to 6a4ef4e5d1084ce41fafa7d470a644b0fd3d9317:
13
for you to fetch changes up to cdfaa57dcb53ba012439765a1462247dfda8595d:
16
14
17
target/arm: Honor HCR_EL2.TID3 trapping requirements (2019-11-26 13:55:37 +0000)
15
hw/arm/raspi: Remove use of the 'version' value in the board code (2020-10-01 15:31:01 +0100)
18
16
19
----------------------------------------------------------------
17
----------------------------------------------------------------
20
target-arm queue:
18
target-arm queue:
21
* handle FTYPE flag correctly in v7M exception return
19
* Make isar_feature_aa32_fp16_arith() handle M-profile
22
for v7M CPUs with an FPU (v8M CPUs were already correct)
20
* Fix SVE splice
23
* versal: Add the CRP as unimplemented
21
* Fix SVE LDR/STR
24
* Fix ISR_EL1 tracking when executing at EL2
22
* Remove ignore_memory_transaction_failures on the raspi2
25
* Honor HCR_EL2.TID3 trapping requirements
23
* raspi: Various cleanup/refactoring
26
24
27
----------------------------------------------------------------
25
----------------------------------------------------------------
28
Edgar E. Iglesias (1):
26
Peter Maydell (5):
29
hw/arm: versal: Add the CRP as unimplemented
27
target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check
28
target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters
29
hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs
30
target/arm: Add ID register values for Cortex-M0
31
target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile
30
32
31
Jean-Hugues Deschênes (1):
33
Philippe Mathieu-Daudé (11):
32
target/arm: Fix handling of cortex-m FTYPE flag in EXCRET
34
hw/arm/raspi: Define various blocks base addresses
35
hw/arm/bcm2835: Add more unimplemented peripherals
36
hw/arm/raspi: Remove ignore_memory_transaction_failures on the raspi2
37
hw/arm/raspi: Display the board revision in the machine description
38
hw/arm/raspi: Load the firmware on the first core
39
hw/arm/raspi: Move arm_boot_info structure to RaspiMachineState
40
hw/arm/raspi: Avoid using TypeInfo::class_data pointer
41
hw/arm/raspi: Use more specific machine names
42
hw/arm/raspi: Introduce RaspiProcessorId enum
43
hw/arm/raspi: Use RaspiProcessorId to set the firmware load address
44
hw/arm/raspi: Remove use of the 'version' value in the board code
33
45
34
Marc Zyngier (2):
46
Richard Henderson (2):
35
target/arm: Fix ISR_EL1 tracking when executing at EL2
47
target/arm: Fix sve ldr/str
36
target/arm: Honor HCR_EL2.TID3 trapping requirements
48
target/arm: Fix SVE splice
37
49
38
include/hw/arm/xlnx-versal.h | 3 ++
50
include/hw/arm/bcm2835_peripherals.h | 2 +
39
hw/arm/xlnx-versal.c | 2 ++
51
include/hw/arm/raspi_platform.h | 51 ++++++++++--
40
target/arm/helper.c | 83 ++++++++++++++++++++++++++++++++++++++++++--
52
target/arm/cpu.h | 50 +++++++++--
41
target/arm/m_helper.c | 7 ++--
53
hw/arm/bcm2835_peripherals.c | 2 +
42
4 files changed, 89 insertions(+), 6 deletions(-)
54
hw/arm/raspi.c | 155 +++++++++++++++++++----------------
55
hw/intc/armv7m_nvic.c | 46 ++++++++++-
56
target/arm/cpu.c | 21 +++--
57
target/arm/cpu64.c | 12 +--
58
target/arm/cpu_tcg.c | 60 ++++++++++----
59
target/arm/helper.c | 9 +-
60
target/arm/kvm64.c | 4 +
61
target/arm/translate-sve.c | 6 +-
62
12 files changed, 286 insertions(+), 132 deletions(-)
43
63
diff view generated by jsdifflib
[PULL 3/4] target/arm: Fix ISR_EL1 tracking when executing at EL2
[PULL 01/18] target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check
1
From: Marc Zyngier <maz@kernel.org>
1
The ARM_FEATURE_PXN bit indicates whether the CPU supports the PXN
2
bit in short-descriptor translation table format descriptors. This
3
is indicated by ID_MMFR0.VMSA being at least 0b0100. Replace the
4
feature bit with an ID register check, in line with our preference
5
for ID register checks over feature bits.
2
6
3
The ARMv8 ARM states when executing at EL2, EL3 or Secure EL1,
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
ISR_EL1 shows the pending status of the physical IRQ, FIQ, or
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
SError interrupts.
9
Message-id: 20200910173855.4068-2-peter.maydell@linaro.org
10
---
11
target/arm/cpu.h | 15 ++++++++++++++-
12
target/arm/cpu.c | 1 -
13
target/arm/helper.c | 5 +++--
14
3 files changed, 17 insertions(+), 4 deletions(-)
6
15
7
Unfortunately, QEMU's implementation only considers the HCR_EL2
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
8
bits, and ignores the current exception level. This means a hypervisor
17
index XXXXXXX..XXXXXXX 100644
9
trying to look at its own interrupt state actually sees the guest
18
--- a/target/arm/cpu.h
10
state, which is unexpected and breaks KVM as of Linux 5.3.
19
+++ b/target/arm/cpu.h
11
20
@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, FHM, 8, 4)
12
Instead, check for the running EL and return the physical bits
21
FIELD(ID_ISAR6, SB, 12, 4)
13
if not running in a virtualized context.
22
FIELD(ID_ISAR6, SPECRES, 16, 4)
14
23
15
Fixes: 636540e9c40b
24
+FIELD(ID_MMFR0, VMSA, 0, 4)
16
Cc: qemu-stable@nongnu.org
25
+FIELD(ID_MMFR0, PMSA, 4, 4)
17
Reported-by: Quentin Perret <qperret@google.com>
26
+FIELD(ID_MMFR0, OUTERSHR, 8, 4)
18
Signed-off-by: Marc Zyngier <maz@kernel.org>
27
+FIELD(ID_MMFR0, SHARELVL, 12, 4)
19
Message-id: 20191122135833.28953-1-maz@kernel.org
28
+FIELD(ID_MMFR0, TCM, 16, 4)
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
29
+FIELD(ID_MMFR0, AUXREG, 20, 4)
21
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
30
+FIELD(ID_MMFR0, FCSE, 24, 4)
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
+FIELD(ID_MMFR0, INNERSHR, 28, 4)
23
---
32
+
24
target/arm/helper.c | 7 +++++--
33
FIELD(ID_MMFR3, CMAINTVA, 0, 4)
25
1 file changed, 5 insertions(+), 2 deletions(-)
34
FIELD(ID_MMFR3, CMAINTSW, 4, 4)
26
35
FIELD(ID_MMFR3, BPMAINT, 8, 4)
36
@@ -XXX,XX +XXX,XX @@ enum arm_features {
37
ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
38
ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
39
ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
40
- ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
41
ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
42
ARM_FEATURE_V8,
43
ARM_FEATURE_AARCH64, /* supports 64 bit mode */
44
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
45
return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
46
}
47
48
+static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
49
+{
50
+ return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
51
+}
52
+
53
static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
54
{
55
return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
56
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/target/arm/cpu.c
59
+++ b/target/arm/cpu.c
60
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
61
}
62
if (arm_feature(env, ARM_FEATURE_LPAE)) {
63
set_feature(env, ARM_FEATURE_V7MP);
64
- set_feature(env, ARM_FEATURE_PXN);
65
}
66
if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
67
set_feature(env, ARM_FEATURE_CBAR);
27
diff --git a/target/arm/helper.c b/target/arm/helper.c
68
diff --git a/target/arm/helper.c b/target/arm/helper.c
28
index XXXXXXX..XXXXXXX 100644
69
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/helper.c
70
--- a/target/arm/helper.c
30
+++ b/target/arm/helper.c
71
+++ b/target/arm/helper.c
31
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
72
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
73
target_ulong *page_size, ARMMMUFaultInfo *fi)
74
{
32
CPUState *cs = env_cpu(env);
75
CPUState *cs = env_cpu(env);
33
uint64_t hcr_el2 = arm_hcr_el2_eff(env);
76
+ ARMCPU *cpu = env_archcpu(env);
34
uint64_t ret = 0;
77
int level = 1;
35
+ bool allow_virt = (arm_current_el(env) == 1 &&
78
uint32_t table;
36
+ (!arm_is_secure_below_el3(env) ||
79
uint32_t desc;
37
+ (env->cp15.scr_el3 & SCR_EEL2)));
80
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
38
81
goto do_fault;
39
- if (hcr_el2 & HCR_IMO) {
82
}
40
+ if (allow_virt && (hcr_el2 & HCR_IMO)) {
83
type = (desc & 3);
41
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
84
- if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
42
ret |= CPSR_I;
85
+ if (type == 0 || (type == 3 && !cpu_isar_feature(aa32_pxn, cpu))) {
86
/* Section translation fault, or attempt to use the encoding
87
* which is Reserved on implementations without PXN.
88
*/
89
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
90
pxn = desc & 1;
91
ns = extract32(desc, 19, 1);
92
} else {
93
- if (arm_feature(env, ARM_FEATURE_PXN)) {
94
+ if (cpu_isar_feature(aa32_pxn, cpu)) {
95
pxn = (desc >> 2) & 1;
43
}
96
}
44
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
97
ns = extract32(desc, 3, 1);
45
}
46
}
47
48
- if (hcr_el2 & HCR_FMO) {
49
+ if (allow_virt && (hcr_el2 & HCR_FMO)) {
50
if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
51
ret |= CPSR_F;
52
}
53
--
98
--
54
2.20.1
99
2.20.1
55
100
56
101
diff view generated by jsdifflib
[PULL 4/4] target/arm: Honor HCR_EL2.TID3 trapping requirements
[PULL 02/18] target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters
1
From: Marc Zyngier <maz@kernel.org>
1
Move the id_pfr0 and id_pfr1 fields into the ARMISARegisters
2
2
sub-struct. We're going to want id_pfr1 for an isar_features
3
HCR_EL2.TID3 mandates that access from EL1 to a long list of id
3
check, and moving both at the same time avoids an odd
4
registers traps to EL2, and QEMU has so far ignored this requirement.
4
inconsistency.
5
5
6
This breaks (among other things) KVM guests that have PtrAuth enabled,
6
Changes other than the ones to cpu.h and kvm64.c made
7
while the hypervisor doesn't want to expose the feature to its guest.
7
automatically with:
8
To achieve this, KVM traps the ID registers (ID_AA64ISAR1_EL1 in this
8
perl -p -i -e 's/cpu->id_pfr/cpu->isar.id_pfr/' target/arm/*.c hw/intc/armv7m_nvic.c
9
case), and masks out the unsupported feature.
9
10
11
QEMU not honoring the trap request means that the guest observes
12
that the feature is present in the HW, starts using it, and dies
13
a horrible death when KVM injects an UNDEF, because the feature
14
*really* isn't supported.
15
16
Do the right thing by trapping to EL2 if HCR_EL2.TID3 is set.
17
18
Note that this change does not include trapping of the MVFR
19
registers from AArch32 (they are accessed via the VMRS
20
instruction and need to be handled in a different way).
21
22
Reported-by: Will Deacon <will@kernel.org>
23
Signed-off-by: Marc Zyngier <maz@kernel.org>
24
Tested-by: Will Deacon <will@kernel.org>
25
Message-id: 20191123115618.29230-1-maz@kernel.org
26
[PMM: added missing accessfn line for ID_AA4PFR2_EL1_RESERVED;
27
changed names of access functions to include _tid3]
28
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20200910173855.4068-3-peter.maydell@linaro.org
30
---
13
---
31
target/arm/helper.c | 76 +++++++++++++++++++++++++++++++++++++++++++++
14
target/arm/cpu.h | 4 ++--
32
1 file changed, 76 insertions(+)
15
hw/intc/armv7m_nvic.c | 4 ++--
33
16
target/arm/cpu.c | 20 ++++++++++----------
17
target/arm/cpu64.c | 12 ++++++------
18
target/arm/cpu_tcg.c | 36 ++++++++++++++++++------------------
19
target/arm/helper.c | 4 ++--
20
target/arm/kvm64.c | 4 ++++
21
7 files changed, 44 insertions(+), 40 deletions(-)
22
23
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/cpu.h
26
+++ b/target/arm/cpu.h
27
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
28
uint32_t id_mmfr2;
29
uint32_t id_mmfr3;
30
uint32_t id_mmfr4;
31
+ uint32_t id_pfr0;
32
+ uint32_t id_pfr1;
33
uint32_t mvfr0;
34
uint32_t mvfr1;
35
uint32_t mvfr2;
36
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
37
uint32_t reset_fpsid;
38
uint32_t ctr;
39
uint32_t reset_sctlr;
40
- uint32_t id_pfr0;
41
- uint32_t id_pfr1;
42
uint64_t pmceid0;
43
uint64_t pmceid1;
44
uint32_t id_afr0;
45
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/intc/armv7m_nvic.c
48
+++ b/hw/intc/armv7m_nvic.c
49
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
50
"Aux Fault status registers unimplemented\n");
51
return 0;
52
case 0xd40: /* PFR0. */
53
- return cpu->id_pfr0;
54
+ return cpu->isar.id_pfr0;
55
case 0xd44: /* PFR1. */
56
- return cpu->id_pfr1;
57
+ return cpu->isar.id_pfr1;
58
case 0xd48: /* DFR0. */
59
return cpu->isar.id_dfr0;
60
case 0xd4c: /* AFR0. */
61
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/target/arm/cpu.c
64
+++ b/target/arm/cpu.c
65
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
66
/* Disable the security extension feature bits in the processor feature
67
* registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
68
*/
69
- cpu->id_pfr1 &= ~0xf0;
70
+ cpu->isar.id_pfr1 &= ~0xf0;
71
cpu->isar.id_aa64pfr0 &= ~0xf000;
72
}
73
74
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
75
* id_aa64pfr0_el1[11:8].
76
*/
77
cpu->isar.id_aa64pfr0 &= ~0xf00;
78
- cpu->id_pfr1 &= ~0xf000;
79
+ cpu->isar.id_pfr1 &= ~0xf000;
80
}
81
82
#ifndef CONFIG_USER_ONLY
83
@@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj)
84
cpu->isar.mvfr1 = 0x00011111;
85
cpu->ctr = 0x82048004;
86
cpu->reset_sctlr = 0x00c50078;
87
- cpu->id_pfr0 = 0x1031;
88
- cpu->id_pfr1 = 0x11;
89
+ cpu->isar.id_pfr0 = 0x1031;
90
+ cpu->isar.id_pfr1 = 0x11;
91
cpu->isar.id_dfr0 = 0x400;
92
cpu->id_afr0 = 0;
93
cpu->isar.id_mmfr0 = 0x31100003;
94
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
95
cpu->isar.mvfr1 = 0x01111111;
96
cpu->ctr = 0x80038003;
97
cpu->reset_sctlr = 0x00c50078;
98
- cpu->id_pfr0 = 0x1031;
99
- cpu->id_pfr1 = 0x11;
100
+ cpu->isar.id_pfr0 = 0x1031;
101
+ cpu->isar.id_pfr1 = 0x11;
102
cpu->isar.id_dfr0 = 0x000;
103
cpu->id_afr0 = 0;
104
cpu->isar.id_mmfr0 = 0x00100103;
105
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
106
cpu->isar.mvfr1 = 0x11111111;
107
cpu->ctr = 0x84448003;
108
cpu->reset_sctlr = 0x00c50078;
109
- cpu->id_pfr0 = 0x00001131;
110
- cpu->id_pfr1 = 0x00011011;
111
+ cpu->isar.id_pfr0 = 0x00001131;
112
+ cpu->isar.id_pfr1 = 0x00011011;
113
cpu->isar.id_dfr0 = 0x02010555;
114
cpu->id_afr0 = 0x00000000;
115
cpu->isar.id_mmfr0 = 0x10101105;
116
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
117
cpu->isar.mvfr1 = 0x11111111;
118
cpu->ctr = 0x8444c004;
119
cpu->reset_sctlr = 0x00c50078;
120
- cpu->id_pfr0 = 0x00001131;
121
- cpu->id_pfr1 = 0x00011011;
122
+ cpu->isar.id_pfr0 = 0x00001131;
123
+ cpu->isar.id_pfr1 = 0x00011011;
124
cpu->isar.id_dfr0 = 0x02010555;
125
cpu->id_afr0 = 0x00000000;
126
cpu->isar.id_mmfr0 = 0x10201105;
127
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
128
index XXXXXXX..XXXXXXX 100644
129
--- a/target/arm/cpu64.c
130
+++ b/target/arm/cpu64.c
131
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
132
cpu->isar.mvfr2 = 0x00000043;
133
cpu->ctr = 0x8444c004;
134
cpu->reset_sctlr = 0x00c50838;
135
- cpu->id_pfr0 = 0x00000131;
136
- cpu->id_pfr1 = 0x00011011;
137
+ cpu->isar.id_pfr0 = 0x00000131;
138
+ cpu->isar.id_pfr1 = 0x00011011;
139
cpu->isar.id_dfr0 = 0x03010066;
140
cpu->id_afr0 = 0x00000000;
141
cpu->isar.id_mmfr0 = 0x10101105;
142
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
143
cpu->isar.mvfr2 = 0x00000043;
144
cpu->ctr = 0x84448004; /* L1Ip = VIPT */
145
cpu->reset_sctlr = 0x00c50838;
146
- cpu->id_pfr0 = 0x00000131;
147
- cpu->id_pfr1 = 0x00011011;
148
+ cpu->isar.id_pfr0 = 0x00000131;
149
+ cpu->isar.id_pfr1 = 0x00011011;
150
cpu->isar.id_dfr0 = 0x03010066;
151
cpu->id_afr0 = 0x00000000;
152
cpu->isar.id_mmfr0 = 0x10101105;
153
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
154
cpu->isar.mvfr2 = 0x00000043;
155
cpu->ctr = 0x8444c004;
156
cpu->reset_sctlr = 0x00c50838;
157
- cpu->id_pfr0 = 0x00000131;
158
- cpu->id_pfr1 = 0x00011011;
159
+ cpu->isar.id_pfr0 = 0x00000131;
160
+ cpu->isar.id_pfr1 = 0x00011011;
161
cpu->isar.id_dfr0 = 0x03010066;
162
cpu->id_afr0 = 0x00000000;
163
cpu->isar.id_mmfr0 = 0x10201105;
164
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
165
index XXXXXXX..XXXXXXX 100644
166
--- a/target/arm/cpu_tcg.c
167
+++ b/target/arm/cpu_tcg.c
168
@@ -XXX,XX +XXX,XX @@ static void arm1136_r2_initfn(Object *obj)
169
cpu->isar.mvfr1 = 0x00000000;
170
cpu->ctr = 0x1dd20d2;
171
cpu->reset_sctlr = 0x00050078;
172
- cpu->id_pfr0 = 0x111;
173
- cpu->id_pfr1 = 0x1;
174
+ cpu->isar.id_pfr0 = 0x111;
175
+ cpu->isar.id_pfr1 = 0x1;
176
cpu->isar.id_dfr0 = 0x2;
177
cpu->id_afr0 = 0x3;
178
cpu->isar.id_mmfr0 = 0x01130003;
179
@@ -XXX,XX +XXX,XX @@ static void arm1136_initfn(Object *obj)
180
cpu->isar.mvfr1 = 0x00000000;
181
cpu->ctr = 0x1dd20d2;
182
cpu->reset_sctlr = 0x00050078;
183
- cpu->id_pfr0 = 0x111;
184
- cpu->id_pfr1 = 0x1;
185
+ cpu->isar.id_pfr0 = 0x111;
186
+ cpu->isar.id_pfr1 = 0x1;
187
cpu->isar.id_dfr0 = 0x2;
188
cpu->id_afr0 = 0x3;
189
cpu->isar.id_mmfr0 = 0x01130003;
190
@@ -XXX,XX +XXX,XX @@ static void arm1176_initfn(Object *obj)
191
cpu->isar.mvfr1 = 0x00000000;
192
cpu->ctr = 0x1dd20d2;
193
cpu->reset_sctlr = 0x00050078;
194
- cpu->id_pfr0 = 0x111;
195
- cpu->id_pfr1 = 0x11;
196
+ cpu->isar.id_pfr0 = 0x111;
197
+ cpu->isar.id_pfr1 = 0x11;
198
cpu->isar.id_dfr0 = 0x33;
199
cpu->id_afr0 = 0;
200
cpu->isar.id_mmfr0 = 0x01130003;
201
@@ -XXX,XX +XXX,XX @@ static void arm11mpcore_initfn(Object *obj)
202
cpu->isar.mvfr0 = 0x11111111;
203
cpu->isar.mvfr1 = 0x00000000;
204
cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
205
- cpu->id_pfr0 = 0x111;
206
- cpu->id_pfr1 = 0x1;
207
+ cpu->isar.id_pfr0 = 0x111;
208
+ cpu->isar.id_pfr1 = 0x1;
209
cpu->isar.id_dfr0 = 0;
210
cpu->id_afr0 = 0x2;
211
cpu->isar.id_mmfr0 = 0x01100103;
212
@@ -XXX,XX +XXX,XX @@ static void cortex_m3_initfn(Object *obj)
213
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
214
cpu->midr = 0x410fc231;
215
cpu->pmsav7_dregion = 8;
216
- cpu->id_pfr0 = 0x00000030;
217
- cpu->id_pfr1 = 0x00000200;
218
+ cpu->isar.id_pfr0 = 0x00000030;
219
+ cpu->isar.id_pfr1 = 0x00000200;
220
cpu->isar.id_dfr0 = 0x00100000;
221
cpu->id_afr0 = 0x00000000;
222
cpu->isar.id_mmfr0 = 0x00000030;
223
@@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj)
224
cpu->isar.mvfr0 = 0x10110021;
225
cpu->isar.mvfr1 = 0x11000011;
226
cpu->isar.mvfr2 = 0x00000000;
227
- cpu->id_pfr0 = 0x00000030;
228
- cpu->id_pfr1 = 0x00000200;
229
+ cpu->isar.id_pfr0 = 0x00000030;
230
+ cpu->isar.id_pfr1 = 0x00000200;
231
cpu->isar.id_dfr0 = 0x00100000;
232
cpu->id_afr0 = 0x00000000;
233
cpu->isar.id_mmfr0 = 0x00000030;
234
@@ -XXX,XX +XXX,XX @@ static void cortex_m7_initfn(Object *obj)
235
cpu->isar.mvfr0 = 0x10110221;
236
cpu->isar.mvfr1 = 0x12000011;
237
cpu->isar.mvfr2 = 0x00000040;
238
- cpu->id_pfr0 = 0x00000030;
239
- cpu->id_pfr1 = 0x00000200;
240
+ cpu->isar.id_pfr0 = 0x00000030;
241
+ cpu->isar.id_pfr1 = 0x00000200;
242
cpu->isar.id_dfr0 = 0x00100000;
243
cpu->id_afr0 = 0x00000000;
244
cpu->isar.id_mmfr0 = 0x00100030;
245
@@ -XXX,XX +XXX,XX @@ static void cortex_m33_initfn(Object *obj)
246
cpu->isar.mvfr0 = 0x10110021;
247
cpu->isar.mvfr1 = 0x11000011;
248
cpu->isar.mvfr2 = 0x00000040;
249
- cpu->id_pfr0 = 0x00000030;
250
- cpu->id_pfr1 = 0x00000210;
251
+ cpu->isar.id_pfr0 = 0x00000030;
252
+ cpu->isar.id_pfr1 = 0x00000210;
253
cpu->isar.id_dfr0 = 0x00200000;
254
cpu->id_afr0 = 0x00000000;
255
cpu->isar.id_mmfr0 = 0x00101F40;
256
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
257
set_feature(&cpu->env, ARM_FEATURE_PMSA);
258
set_feature(&cpu->env, ARM_FEATURE_PMU);
259
cpu->midr = 0x411fc153; /* r1p3 */
260
- cpu->id_pfr0 = 0x0131;
261
- cpu->id_pfr1 = 0x001;
262
+ cpu->isar.id_pfr0 = 0x0131;
263
+ cpu->isar.id_pfr1 = 0x001;
264
cpu->isar.id_dfr0 = 0x010400;
265
cpu->id_afr0 = 0x0;
266
cpu->isar.id_mmfr0 = 0x0210030;
34
diff --git a/target/arm/helper.c b/target/arm/helper.c
267
diff --git a/target/arm/helper.c b/target/arm/helper.c
35
index XXXXXXX..XXXXXXX 100644
268
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/helper.c
269
--- a/target/arm/helper.c
37
+++ b/target/arm/helper.c
270
+++ b/target/arm/helper.c
38
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = {
271
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
39
REGINFO_SENTINEL
272
static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
40
};
41
42
+static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
43
+ bool isread)
44
+{
45
+ if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) {
46
+ return CP_ACCESS_TRAP_EL2;
47
+ }
48
+
49
+ return CP_ACCESS_OK;
50
+}
51
+
52
+static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
53
+ bool isread)
54
+{
55
+ if (arm_feature(env, ARM_FEATURE_V8)) {
56
+ return access_aa64_tid3(env, ri, isread);
57
+ }
58
+
59
+ return CP_ACCESS_OK;
60
+}
61
+
62
void register_cp_regs_for_features(ARMCPU *cpu)
63
{
273
{
64
/* Register all the coprocessor registers based on feature bits */
274
ARMCPU *cpu = env_archcpu(env);
275
- uint64_t pfr1 = cpu->id_pfr1;
276
+ uint64_t pfr1 = cpu->isar.id_pfr1;
277
278
if (env->gicv3state) {
279
pfr1 |= 1 << 28;
65
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
280
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
66
{ .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
67
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
281
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
68
.access = PL1_R, .type = ARM_CP_CONST,
282
.access = PL1_R, .type = ARM_CP_CONST,
69
+ .accessfn = access_aa32_tid3,
283
.accessfn = access_aa32_tid3,
70
.resetvalue = cpu->id_pfr0 },
284
- .resetvalue = cpu->id_pfr0 },
285
+ .resetvalue = cpu->isar.id_pfr0 },
71
/* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
286
/* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
72
* the value of the GIC field until after we define these regs.
287
* the value of the GIC field until after we define these regs.
73
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
288
*/
74
{ .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
289
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
75
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
290
index XXXXXXX..XXXXXXX 100644
76
.access = PL1_R, .type = ARM_CP_NO_RAW,
291
--- a/target/arm/kvm64.c
77
+ .accessfn = access_aa32_tid3,
292
+++ b/target/arm/kvm64.c
78
.readfn = id_pfr1_read,
293
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
79
.writefn = arm_cp_write_ignore },
294
* than skipping the reads and leaving 0, as we must avoid
80
{ .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
295
* considering the values in every case.
81
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
296
*/
82
.access = PL1_R, .type = ARM_CP_CONST,
297
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0,
83
+ .accessfn = access_aa32_tid3,
298
+ ARM64_SYS_REG(3, 0, 0, 1, 0));
84
.resetvalue = cpu->id_dfr0 },
299
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1,
85
{ .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
300
+ ARM64_SYS_REG(3, 0, 0, 1, 1));
86
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
301
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
87
.access = PL1_R, .type = ARM_CP_CONST,
302
ARM64_SYS_REG(3, 0, 0, 1, 2));
88
+ .accessfn = access_aa32_tid3,
303
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
89
.resetvalue = cpu->id_afr0 },
90
{ .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
91
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
92
.access = PL1_R, .type = ARM_CP_CONST,
93
+ .accessfn = access_aa32_tid3,
94
.resetvalue = cpu->id_mmfr0 },
95
{ .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
96
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
97
.access = PL1_R, .type = ARM_CP_CONST,
98
+ .accessfn = access_aa32_tid3,
99
.resetvalue = cpu->id_mmfr1 },
100
{ .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
101
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
102
.access = PL1_R, .type = ARM_CP_CONST,
103
+ .accessfn = access_aa32_tid3,
104
.resetvalue = cpu->id_mmfr2 },
105
{ .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
106
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
107
.access = PL1_R, .type = ARM_CP_CONST,
108
+ .accessfn = access_aa32_tid3,
109
.resetvalue = cpu->id_mmfr3 },
110
{ .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
111
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
112
.access = PL1_R, .type = ARM_CP_CONST,
113
+ .accessfn = access_aa32_tid3,
114
.resetvalue = cpu->isar.id_isar0 },
115
{ .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
116
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
117
.access = PL1_R, .type = ARM_CP_CONST,
118
+ .accessfn = access_aa32_tid3,
119
.resetvalue = cpu->isar.id_isar1 },
120
{ .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
121
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
122
.access = PL1_R, .type = ARM_CP_CONST,
123
+ .accessfn = access_aa32_tid3,
124
.resetvalue = cpu->isar.id_isar2 },
125
{ .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
126
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
127
.access = PL1_R, .type = ARM_CP_CONST,
128
+ .accessfn = access_aa32_tid3,
129
.resetvalue = cpu->isar.id_isar3 },
130
{ .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
131
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
132
.access = PL1_R, .type = ARM_CP_CONST,
133
+ .accessfn = access_aa32_tid3,
134
.resetvalue = cpu->isar.id_isar4 },
135
{ .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
136
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
137
.access = PL1_R, .type = ARM_CP_CONST,
138
+ .accessfn = access_aa32_tid3,
139
.resetvalue = cpu->isar.id_isar5 },
140
{ .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
141
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
142
.access = PL1_R, .type = ARM_CP_CONST,
143
+ .accessfn = access_aa32_tid3,
144
.resetvalue = cpu->id_mmfr4 },
145
{ .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
146
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
147
.access = PL1_R, .type = ARM_CP_CONST,
148
+ .accessfn = access_aa32_tid3,
149
.resetvalue = cpu->isar.id_isar6 },
150
REGINFO_SENTINEL
151
};
152
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
153
{ .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
154
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
155
.access = PL1_R, .type = ARM_CP_NO_RAW,
156
+ .accessfn = access_aa64_tid3,
157
.readfn = id_aa64pfr0_read,
158
.writefn = arm_cp_write_ignore },
159
{ .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
160
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
161
.access = PL1_R, .type = ARM_CP_CONST,
162
+ .accessfn = access_aa64_tid3,
163
.resetvalue = cpu->isar.id_aa64pfr1},
164
{ .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
165
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
166
.access = PL1_R, .type = ARM_CP_CONST,
167
+ .accessfn = access_aa64_tid3,
168
.resetvalue = 0 },
169
{ .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
170
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
171
.access = PL1_R, .type = ARM_CP_CONST,
172
+ .accessfn = access_aa64_tid3,
173
.resetvalue = 0 },
174
{ .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64,
175
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
176
.access = PL1_R, .type = ARM_CP_CONST,
177
+ .accessfn = access_aa64_tid3,
178
/* At present, only SVEver == 0 is defined anyway. */
179
.resetvalue = 0 },
180
{ .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
181
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
182
.access = PL1_R, .type = ARM_CP_CONST,
183
+ .accessfn = access_aa64_tid3,
184
.resetvalue = 0 },
185
{ .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
186
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
187
.access = PL1_R, .type = ARM_CP_CONST,
188
+ .accessfn = access_aa64_tid3,
189
.resetvalue = 0 },
190
{ .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
191
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
192
.access = PL1_R, .type = ARM_CP_CONST,
193
+ .accessfn = access_aa64_tid3,
194
.resetvalue = 0 },
195
{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
196
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
197
.access = PL1_R, .type = ARM_CP_CONST,
198
+ .accessfn = access_aa64_tid3,
199
.resetvalue = cpu->id_aa64dfr0 },
200
{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
201
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
202
.access = PL1_R, .type = ARM_CP_CONST,
203
+ .accessfn = access_aa64_tid3,
204
.resetvalue = cpu->id_aa64dfr1 },
205
{ .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
206
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
207
.access = PL1_R, .type = ARM_CP_CONST,
208
+ .accessfn = access_aa64_tid3,
209
.resetvalue = 0 },
210
{ .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
211
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
212
.access = PL1_R, .type = ARM_CP_CONST,
213
+ .accessfn = access_aa64_tid3,
214
.resetvalue = 0 },
215
{ .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
216
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
217
.access = PL1_R, .type = ARM_CP_CONST,
218
+ .accessfn = access_aa64_tid3,
219
.resetvalue = cpu->id_aa64afr0 },
220
{ .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
221
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
222
.access = PL1_R, .type = ARM_CP_CONST,
223
+ .accessfn = access_aa64_tid3,
224
.resetvalue = cpu->id_aa64afr1 },
225
{ .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
226
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
227
.access = PL1_R, .type = ARM_CP_CONST,
228
+ .accessfn = access_aa64_tid3,
229
.resetvalue = 0 },
230
{ .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
231
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
232
.access = PL1_R, .type = ARM_CP_CONST,
233
+ .accessfn = access_aa64_tid3,
234
.resetvalue = 0 },
235
{ .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
236
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
237
.access = PL1_R, .type = ARM_CP_CONST,
238
+ .accessfn = access_aa64_tid3,
239
.resetvalue = cpu->isar.id_aa64isar0 },
240
{ .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
241
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
242
.access = PL1_R, .type = ARM_CP_CONST,
243
+ .accessfn = access_aa64_tid3,
244
.resetvalue = cpu->isar.id_aa64isar1 },
245
{ .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
246
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
247
.access = PL1_R, .type = ARM_CP_CONST,
248
+ .accessfn = access_aa64_tid3,
249
.resetvalue = 0 },
250
{ .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
251
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
252
.access = PL1_R, .type = ARM_CP_CONST,
253
+ .accessfn = access_aa64_tid3,
254
.resetvalue = 0 },
255
{ .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
256
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
257
.access = PL1_R, .type = ARM_CP_CONST,
258
+ .accessfn = access_aa64_tid3,
259
.resetvalue = 0 },
260
{ .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
261
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
262
.access = PL1_R, .type = ARM_CP_CONST,
263
+ .accessfn = access_aa64_tid3,
264
.resetvalue = 0 },
265
{ .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
266
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
267
.access = PL1_R, .type = ARM_CP_CONST,
268
+ .accessfn = access_aa64_tid3,
269
.resetvalue = 0 },
270
{ .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
271
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
272
.access = PL1_R, .type = ARM_CP_CONST,
273
+ .accessfn = access_aa64_tid3,
274
.resetvalue = 0 },
275
{ .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
276
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
277
.access = PL1_R, .type = ARM_CP_CONST,
278
+ .accessfn = access_aa64_tid3,
279
.resetvalue = cpu->isar.id_aa64mmfr0 },
280
{ .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
281
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
282
.access = PL1_R, .type = ARM_CP_CONST,
283
+ .accessfn = access_aa64_tid3,
284
.resetvalue = cpu->isar.id_aa64mmfr1 },
285
{ .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
286
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
287
.access = PL1_R, .type = ARM_CP_CONST,
288
+ .accessfn = access_aa64_tid3,
289
.resetvalue = 0 },
290
{ .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
291
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
292
.access = PL1_R, .type = ARM_CP_CONST,
293
+ .accessfn = access_aa64_tid3,
294
.resetvalue = 0 },
295
{ .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
296
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
297
.access = PL1_R, .type = ARM_CP_CONST,
298
+ .accessfn = access_aa64_tid3,
299
.resetvalue = 0 },
300
{ .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
301
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
302
.access = PL1_R, .type = ARM_CP_CONST,
303
+ .accessfn = access_aa64_tid3,
304
.resetvalue = 0 },
305
{ .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
306
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
307
.access = PL1_R, .type = ARM_CP_CONST,
308
+ .accessfn = access_aa64_tid3,
309
.resetvalue = 0 },
310
{ .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
311
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
312
.access = PL1_R, .type = ARM_CP_CONST,
313
+ .accessfn = access_aa64_tid3,
314
.resetvalue = 0 },
315
{ .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
316
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
317
.access = PL1_R, .type = ARM_CP_CONST,
318
+ .accessfn = access_aa64_tid3,
319
.resetvalue = cpu->isar.mvfr0 },
320
{ .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
321
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
322
.access = PL1_R, .type = ARM_CP_CONST,
323
+ .accessfn = access_aa64_tid3,
324
.resetvalue = cpu->isar.mvfr1 },
325
{ .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
326
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
327
.access = PL1_R, .type = ARM_CP_CONST,
328
+ .accessfn = access_aa64_tid3,
329
.resetvalue = cpu->isar.mvfr2 },
330
{ .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
331
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
332
.access = PL1_R, .type = ARM_CP_CONST,
333
+ .accessfn = access_aa64_tid3,
334
.resetvalue = 0 },
335
{ .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
336
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
337
.access = PL1_R, .type = ARM_CP_CONST,
338
+ .accessfn = access_aa64_tid3,
339
.resetvalue = 0 },
340
{ .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
341
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
342
.access = PL1_R, .type = ARM_CP_CONST,
343
+ .accessfn = access_aa64_tid3,
344
.resetvalue = 0 },
345
{ .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
346
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
347
.access = PL1_R, .type = ARM_CP_CONST,
348
+ .accessfn = access_aa64_tid3,
349
.resetvalue = 0 },
350
{ .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
351
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
352
.access = PL1_R, .type = ARM_CP_CONST,
353
+ .accessfn = access_aa64_tid3,
354
.resetvalue = 0 },
355
{ .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
356
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
357
--
304
--
358
2.20.1
305
2.20.1
359
306
360
307
diff view generated by jsdifflib
New patch
[PULL 03/18] hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs
1
M-profile CPUs only implement the ID registers as guest-visible if
2
the CPU implements the Main Extension (all our current CPUs except
3
the Cortex-M0 do).
1
4
5
Currently we handle this by having the Cortex-M0 leave the ID
6
register values in the ARMCPU struct as zero, but this conflicts with
7
our design decision to make QEMU behaviour be keyed off ID register
8
fields wherever possible.
9
10
Explicitly code the ID registers in the NVIC to return 0 if the Main
11
Extension is not implemented, so we can make the M0 model set the
12
ARMCPU struct fields to obtain the correct behaviour without those
13
values becoming guest-visible.
14
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20200910173855.4068-4-peter.maydell@linaro.org
18
---
19
hw/intc/armv7m_nvic.c | 42 ++++++++++++++++++++++++++++++++++++++++++
20
1 file changed, 42 insertions(+)
21
22
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/intc/armv7m_nvic.c
25
+++ b/hw/intc/armv7m_nvic.c
26
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
27
"Aux Fault status registers unimplemented\n");
28
return 0;
29
case 0xd40: /* PFR0. */
30
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
31
+ goto bad_offset;
32
+ }
33
return cpu->isar.id_pfr0;
34
case 0xd44: /* PFR1. */
35
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
36
+ goto bad_offset;
37
+ }
38
return cpu->isar.id_pfr1;
39
case 0xd48: /* DFR0. */
40
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
41
+ goto bad_offset;
42
+ }
43
return cpu->isar.id_dfr0;
44
case 0xd4c: /* AFR0. */
45
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
46
+ goto bad_offset;
47
+ }
48
return cpu->id_afr0;
49
case 0xd50: /* MMFR0. */
50
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
51
+ goto bad_offset;
52
+ }
53
return cpu->isar.id_mmfr0;
54
case 0xd54: /* MMFR1. */
55
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
56
+ goto bad_offset;
57
+ }
58
return cpu->isar.id_mmfr1;
59
case 0xd58: /* MMFR2. */
60
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
61
+ goto bad_offset;
62
+ }
63
return cpu->isar.id_mmfr2;
64
case 0xd5c: /* MMFR3. */
65
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
66
+ goto bad_offset;
67
+ }
68
return cpu->isar.id_mmfr3;
69
case 0xd60: /* ISAR0. */
70
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
71
+ goto bad_offset;
72
+ }
73
return cpu->isar.id_isar0;
74
case 0xd64: /* ISAR1. */
75
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
76
+ goto bad_offset;
77
+ }
78
return cpu->isar.id_isar1;
79
case 0xd68: /* ISAR2. */
80
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
81
+ goto bad_offset;
82
+ }
83
return cpu->isar.id_isar2;
84
case 0xd6c: /* ISAR3. */
85
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
86
+ goto bad_offset;
87
+ }
88
return cpu->isar.id_isar3;
89
case 0xd70: /* ISAR4. */
90
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
91
+ goto bad_offset;
92
+ }
93
return cpu->isar.id_isar4;
94
case 0xd74: /* ISAR5. */
95
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
96
+ goto bad_offset;
97
+ }
98
return cpu->isar.id_isar5;
99
case 0xd78: /* CLIDR */
100
return cpu->clidr;
101
--
102
2.20.1
103
104
diff view generated by jsdifflib
New patch
[PULL 04/18] target/arm: Add ID register values for Cortex-M0
1
Give the Cortex-M0 ID register values corresponding to its
2
implemented behaviour. These will not be guest-visible but will be
3
used to govern the behaviour of QEMU's emulation. We use the same
4
values that the Cortex-M3 does.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200910173855.4068-5-peter.maydell@linaro.org
9
---
10
target/arm/cpu_tcg.c | 24 ++++++++++++++++++++++++
11
1 file changed, 24 insertions(+)
12
13
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu_tcg.c
16
+++ b/target/arm/cpu_tcg.c
17
@@ -XXX,XX +XXX,XX @@ static void cortex_m0_initfn(Object *obj)
18
set_feature(&cpu->env, ARM_FEATURE_M);
19
20
cpu->midr = 0x410cc200;
21
+
22
+ /*
23
+ * These ID register values are not guest visible, because
24
+ * we do not implement the Main Extension. They must be set
25
+ * to values corresponding to the Cortex-M0's implemented
26
+ * features, because QEMU generally controls its emulation
27
+ * by looking at ID register fields. We use the same values as
28
+ * for the M3.
29
+ */
30
+ cpu->isar.id_pfr0 = 0x00000030;
31
+ cpu->isar.id_pfr1 = 0x00000200;
32
+ cpu->isar.id_dfr0 = 0x00100000;
33
+ cpu->id_afr0 = 0x00000000;
34
+ cpu->isar.id_mmfr0 = 0x00000030;
35
+ cpu->isar.id_mmfr1 = 0x00000000;
36
+ cpu->isar.id_mmfr2 = 0x00000000;
37
+ cpu->isar.id_mmfr3 = 0x00000000;
38
+ cpu->isar.id_isar0 = 0x01141110;
39
+ cpu->isar.id_isar1 = 0x02111000;
40
+ cpu->isar.id_isar2 = 0x21112231;
41
+ cpu->isar.id_isar3 = 0x01111110;
42
+ cpu->isar.id_isar4 = 0x01310102;
43
+ cpu->isar.id_isar5 = 0x00000000;
44
+ cpu->isar.id_isar6 = 0x00000000;
45
}
46
47
static void cortex_m3_initfn(Object *obj)
48
--
49
2.20.1
50
51
diff view generated by jsdifflib
New patch
[PULL 05/18] target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile
1
The M-profile definition of the MVFR1 ID register differs slightly
2
from the A-profile one, and in particular the check for "does the CPU
3
support fp16 arithmetic" is not the same.
1
4
5
We don't currently implement any M-profile CPUs with fp16 arithmetic,
6
so this is not yet a visible bug, but correcting the logic now
7
disarms this beartrap for when we eventually do.
8
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20200910173855.4068-6-peter.maydell@linaro.org
12
---
13
target/arm/cpu.h | 31 ++++++++++++++++++++++++++-----
14
1 file changed, 26 insertions(+), 5 deletions(-)
15
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
21
FIELD(ID_MMFR4, CCIDX, 24, 4)
22
FIELD(ID_MMFR4, EVT, 28, 4)
23
24
+FIELD(ID_PFR1, PROGMOD, 0, 4)
25
+FIELD(ID_PFR1, SECURITY, 4, 4)
26
+FIELD(ID_PFR1, MPROGMOD, 8, 4)
27
+FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
28
+FIELD(ID_PFR1, GENTIMER, 16, 4)
29
+FIELD(ID_PFR1, SEC_FRAC, 20, 4)
30
+FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
31
+FIELD(ID_PFR1, GIC, 28, 4)
32
+
33
FIELD(ID_AA64ISAR0, AES, 4, 4)
34
FIELD(ID_AA64ISAR0, SHA1, 8, 4)
35
FIELD(ID_AA64ISAR0, SHA2, 12, 4)
36
@@ -XXX,XX +XXX,XX @@ FIELD(MVFR0, FPROUND, 28, 4)
37
38
FIELD(MVFR1, FPFTZ, 0, 4)
39
FIELD(MVFR1, FPDNAN, 4, 4)
40
-FIELD(MVFR1, SIMDLS, 8, 4)
41
-FIELD(MVFR1, SIMDINT, 12, 4)
42
-FIELD(MVFR1, SIMDSP, 16, 4)
43
-FIELD(MVFR1, SIMDHP, 20, 4)
44
+FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
45
+FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
46
+FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
47
+FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
48
+FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
49
+FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
50
FIELD(MVFR1, FPHP, 24, 4)
51
FIELD(MVFR1, SIMDFMAC, 28, 4)
52
53
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
54
return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
55
}
56
57
+static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
58
+{
59
+ return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
60
+}
61
+
62
static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
63
{
64
- return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
65
+ /* Sadly this is encoded differently for A-profile and M-profile */
66
+ if (isar_feature_aa32_mprofile(id)) {
67
+ return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;
68
+ } else {
69
+ return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
70
+ }
71
}
72
73
static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
74
--
75
2.20.1
76
77
diff view generated by jsdifflib
New patch
[PULL 06/18] target/arm: Fix sve ldr/str
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The mte update missed a bit when producing clean addresses.
4
5
Fixes: b2aa8879b88
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200916014102.2446323-1-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 4 ++--
12
1 file changed, 2 insertions(+), 2 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
19
for (i = 0; i < len_align; i += 8) {
20
tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEQ);
21
tcg_gen_st_i64(t0, cpu_env, vofs + i);
22
- tcg_gen_addi_i64(clean_addr, cpu_reg_sp(s, rn), 8);
23
+ tcg_gen_addi_i64(clean_addr, clean_addr, 8);
24
}
25
tcg_temp_free_i64(t0);
26
} else {
27
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
28
for (i = 0; i < len_align; i += 8) {
29
tcg_gen_ld_i64(t0, cpu_env, vofs + i);
30
tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEQ);
31
- tcg_gen_addi_i64(clean_addr, cpu_reg_sp(s, rn), 8);
32
+ tcg_gen_addi_i64(clean_addr, clean_addr, 8);
33
}
34
tcg_temp_free_i64(t0);
35
} else {
36
--
37
2.20.1
38
39
diff view generated by jsdifflib
[PULL 1/4] target/arm: Fix handling of cortex-m FTYPE flag in EXCRET
[PULL 07/18] target/arm: Fix SVE splice
1
From: Jean-Hugues Deschênes <Jean-Hugues.Deschenes@ossiaco.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
According to the PushStack() pseudocode in the armv7m RM,
3
While converting to gen_gvec_ool_zzzp, we lost passing
4
bit 4 of the LR should be set to NOT(CONTROL.PFCA) when
4
a->esz as the data argument to the function.
5
an FPU is present. Current implementation is doing it for
6
armv8, but not for armv7. This patch makes the existing
7
logic applicable to both code paths.
8
5
9
Signed-off-by: Jean-Hugues Deschenes <jean-hugues.deschenes@ossiaco.com>
6
Fixes: 36cbb7a8e71
7
Cc: qemu-stable@nongnu.org
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200918000500.2690937-1-richard.henderson@linaro.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
12
---
13
target/arm/m_helper.c | 7 +++----
13
target/arm/translate-sve.c | 2 +-
14
1 file changed, 3 insertions(+), 4 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
15
16
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
16
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/m_helper.c
18
--- a/target/arm/translate-sve.c
19
+++ b/target/arm/m_helper.c
19
+++ b/target/arm/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
20
@@ -XXX,XX +XXX,XX @@ static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
21
if (env->v7m.secure) {
21
{
22
lr |= R_V7M_EXCRET_S_MASK;
22
if (sve_access_check(s)) {
23
}
23
gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
24
- if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
24
- a->rd, a->rn, a->rm, a->pg, 0);
25
- lr |= R_V7M_EXCRET_FTYPE_MASK;
25
+ a->rd, a->rn, a->rm, a->pg, a->esz);
26
- }
27
} else {
28
lr = R_V7M_EXCRET_RES1_MASK |
29
R_V7M_EXCRET_S_MASK |
30
R_V7M_EXCRET_DCRS_MASK |
31
- R_V7M_EXCRET_FTYPE_MASK |
32
R_V7M_EXCRET_ES_MASK;
33
if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) {
34
lr |= R_V7M_EXCRET_SPSEL_MASK;
35
}
36
}
26
}
37
+ if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
27
return true;
38
+ lr |= R_V7M_EXCRET_FTYPE_MASK;
28
}
39
+ }
40
if (!arm_v7m_is_handler_mode(env)) {
41
lr |= R_V7M_EXCRET_MODE_MASK;
42
}
43
--
29
--
44
2.20.1
30
2.20.1
45
31
46
32
diff view generated by jsdifflib
New patch
[PULL 08/18] hw/arm/raspi: Define various blocks base addresses
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
The Raspberry firmware is closed-source. While running it, it
4
accesses various I/O registers. Logging these accesses as UNIMP
5
(unimplemented) help to understand what the firmware is doing
6
(ideally we want it able to boot a Linux kernel).
7
8
Document various blocks we might use later.
9
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
13
Message-id: 20200921034729.432931-2-f4bug@amsat.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
include/hw/arm/raspi_platform.h | 51 +++++++++++++++++++++++++++------
17
1 file changed, 43 insertions(+), 8 deletions(-)
18
19
diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/raspi_platform.h
22
+++ b/include/hw/arm/raspi_platform.h
23
@@ -XXX,XX +XXX,XX @@
24
* You should have received a copy of the GNU General Public License
25
* along with this program; if not, write to the Free Software
26
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27
+ *
28
+ * Various undocumented addresses and names come from Herman Hermitage's VC4
29
+ * documentation:
30
+ * https://github.com/hermanhermitage/videocoreiv/wiki/MMIO-Register-map
31
*/
32
33
#ifndef HW_ARM_RASPI_PLATFORM_H
34
#define HW_ARM_RASPI_PLATFORM_H
35
36
#define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */
37
-#define IC0_OFFSET 0x2000
38
+#define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */
39
+#define INTE_OFFSET 0x2000 /* VC Interrupt controller */
40
#define ST_OFFSET 0x3000 /* System Timer */
41
+#define TXP_OFFSET 0x4000 /* Transposer */
42
+#define JPEG_OFFSET 0x5000
43
#define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
44
#define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
45
-#define ARM_OFFSET 0xB000 /* BCM2708 ARM control block */
46
+#define ARBA_OFFSET 0x9000
47
+#define BRDG_OFFSET 0xa000
48
+#define ARM_OFFSET 0xB000 /* ARM control block */
49
#define ARMCTRL_OFFSET (ARM_OFFSET + 0x000)
50
#define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */
51
-#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */
52
+#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */
53
#define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
54
* Doorbells & Mailboxes */
55
#define CPRMAN_OFFSET 0x100000 /* Power Management, Watchdog */
56
@@ -XXX,XX +XXX,XX @@
57
#define AVS_OFFSET 0x103000 /* Audio Video Standard */
58
#define RNG_OFFSET 0x104000
59
#define GPIO_OFFSET 0x200000
60
-#define UART0_OFFSET 0x201000
61
-#define MMCI0_OFFSET 0x202000
62
-#define I2S_OFFSET 0x203000
63
-#define SPI0_OFFSET 0x204000
64
+#define UART0_OFFSET 0x201000 /* PL011 */
65
+#define MMCI0_OFFSET 0x202000 /* Legacy MMC */
66
+#define I2S_OFFSET 0x203000 /* PCM */
67
+#define SPI0_OFFSET 0x204000 /* SPI master */
68
#define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */
69
+#define PIXV0_OFFSET 0x206000
70
+#define PIXV1_OFFSET 0x207000
71
+#define DPI_OFFSET 0x208000
72
+#define DSI0_OFFSET 0x209000 /* Display Serial Interface */
73
+#define PWM_OFFSET 0x20c000
74
+#define PERM_OFFSET 0x20d000
75
+#define TEC_OFFSET 0x20e000
76
#define OTP_OFFSET 0x20f000
77
+#define SLIM_OFFSET 0x210000 /* SLIMbus */
78
+#define CPG_OFFSET 0x211000
79
#define THERMAL_OFFSET 0x212000
80
-#define BSC_SL_OFFSET 0x214000 /* SPI slave */
81
+#define AVSP_OFFSET 0x213000
82
+#define BSC_SL_OFFSET 0x214000 /* SPI slave (bootrom) */
83
#define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */
84
#define EMMC1_OFFSET 0x300000
85
+#define EMMC2_OFFSET 0x340000
86
+#define HVS_OFFSET 0x400000
87
#define SMI_OFFSET 0x600000
88
+#define DSI1_OFFSET 0x700000
89
+#define UCAM_OFFSET 0x800000
90
+#define CMI_OFFSET 0x802000
91
#define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */
92
#define BSC2_OFFSET 0x805000 /* BSC2 I2C/TWI */
93
+#define VECA_OFFSET 0x806000
94
+#define PIXV2_OFFSET 0x807000
95
+#define HDMI_OFFSET 0x808000
96
+#define HDCP_OFFSET 0x809000
97
+#define ARBR0_OFFSET 0x80a000
98
#define DBUS_OFFSET 0x900000
99
#define AVE0_OFFSET 0x910000
100
#define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */
101
+#define V3D_OFFSET 0xc00000
102
#define SDRAMC_OFFSET 0xe00000
103
+#define L2CC_OFFSET 0xe01000 /* Level 2 Cache controller */
104
+#define L1CC_OFFSET 0xe02000 /* Level 1 Cache controller */
105
+#define ARBR1_OFFSET 0xe04000
106
#define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */
107
+#define DCRC_OFFSET 0xe07000
108
+#define AXIP_OFFSET 0xe08000
109
110
/* GPU interrupts */
111
#define INTERRUPT_TIMER0 0
112
--
113
2.20.1
114
115
diff view generated by jsdifflib
New patch
[PULL 09/18] hw/arm/bcm2835: Add more unimplemented peripherals
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
The bcm2835-v3d is used since Linux 4.7, see commit
4
49ac67e0c39c ("ARM: bcm2835: Add VC4 to the device tree"),
5
and the bcm2835-txp since Linux 4.19, see commit
6
b7dd29b401f5 ("ARM: dts: bcm283x: Add Transposer block").
7
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
10
Message-id: 20200921034729.432931-3-f4bug@amsat.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/hw/arm/bcm2835_peripherals.h | 2 ++
14
hw/arm/bcm2835_peripherals.c | 2 ++
15
2 files changed, 4 insertions(+)
16
17
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/bcm2835_peripherals.h
20
+++ b/include/hw/arm/bcm2835_peripherals.h
21
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
22
23
BCM2835SystemTimerState systmr;
24
BCM2835MphiState mphi;
25
+ UnimplementedDeviceState txp;
26
UnimplementedDeviceState armtmr;
27
UnimplementedDeviceState cprman;
28
UnimplementedDeviceState a2w;
29
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
30
UnimplementedDeviceState otp;
31
UnimplementedDeviceState dbus;
32
UnimplementedDeviceState ave0;
33
+ UnimplementedDeviceState v3d;
34
UnimplementedDeviceState bscsl;
35
UnimplementedDeviceState smi;
36
DWC2State dwc2;
37
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/arm/bcm2835_peripherals.c
40
+++ b/hw/arm/bcm2835_peripherals.c
41
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
42
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
43
INTERRUPT_USB));
44
45
+ create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
46
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
47
create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
48
create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
49
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
50
create_unimp(s, &s->otp, "bcm2835-otp", OTP_OFFSET, 0x80);
51
create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000);
52
create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000);
53
+ create_unimp(s, &s->v3d, "bcm2835-v3d", V3D_OFFSET, 0x1000);
54
create_unimp(s, &s->sdramc, "bcm2835-sdramc", SDRAMC_OFFSET, 0x100);
55
}
56
57
--
58
2.20.1
59
60
diff view generated by jsdifflib
New patch
[PULL 10/18] hw/arm/raspi: Remove ignore_memory_transaction_failures on the raspi2
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Commit 1c3db49d39 added the raspi3, which uses the same peripherals
4
than the raspi2 (but with different ARM cores). The raspi3 was
5
introduced without the ignore_memory_transaction_failures flag.
6
Almost 2 years later, the machine is usable running U-Boot and
7
Linux.
8
In commit 00cbd5bd74 we mapped a lot of unimplemented devices,
9
commit d442d95f added thermal block and commit 0e5bbd7406 the
10
system timer.
11
As we are happy with the raspi3, let's remove this flag on the
12
raspi2.
13
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-id: 20200921034729.432931-4-f4bug@amsat.org
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
hw/arm/raspi.c | 3 ---
21
1 file changed, 3 deletions(-)
22
23
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/raspi.c
26
+++ b/hw/arm/raspi.c
27
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_init(ObjectClass *oc, void *data)
28
mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev);
29
mc->default_ram_size = board_ram_size(board_rev);
30
mc->default_ram_id = "ram";
31
- if (board_version(board_rev) == 2) {
32
- mc->ignore_memory_transaction_failures = true;
33
- }
34
};
35
36
static const TypeInfo raspi_machine_types[] = {
37
--
38
2.20.1
39
40
diff view generated by jsdifflib
New patch
[PULL 11/18] hw/arm/raspi: Display the board revision in the machine description
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Display the board revision in the machine description.
4
5
Before:
6
7
$ qemu-system-aarch64 -M help | fgrep raspi
8
raspi2 Raspberry Pi 2B
9
raspi3 Raspberry Pi 3B
10
11
After:
12
13
raspi2 Raspberry Pi 2B (revision 1.1)
14
raspi3 Raspberry Pi 3B (revision 1.2)
15
16
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
17
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20200924111808.77168-2-f4bug@amsat.org
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
hw/arm/raspi.c | 4 +++-
22
1 file changed, 3 insertions(+), 1 deletion(-)
23
24
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/raspi.c
27
+++ b/hw/arm/raspi.c
28
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_init(ObjectClass *oc, void *data)
29
uint32_t board_rev = (uint32_t)(uintptr_t)data;
30
31
rmc->board_rev = board_rev;
32
- mc->desc = g_strdup_printf("Raspberry Pi %s", board_type(board_rev));
33
+ mc->desc = g_strdup_printf("Raspberry Pi %s (revision 1.%u)",
34
+ board_type(board_rev),
35
+ FIELD_EX32(board_rev, REV_CODE, REVISION));
36
mc->init = raspi_machine_init;
37
mc->block_default_type = IF_SD;
38
mc->no_parallel = 1;
39
--
40
2.20.1
41
42
diff view generated by jsdifflib
New patch
[PULL 12/18] hw/arm/raspi: Load the firmware on the first core
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
The 'first_cpu' is more a QEMU accelerator-related concept
4
than a variable the machine requires to use.
5
Since the machine is aware of its CPUs, directly use the
6
first one to load the firmware.
7
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20200924111808.77168-3-f4bug@amsat.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/raspi.c | 3 ++-
14
1 file changed, 2 insertions(+), 1 deletion(-)
15
16
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/raspi.c
19
+++ b/hw/arm/raspi.c
20
@@ -XXX,XX +XXX,XX @@ static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
21
22
static void setup_boot(MachineState *machine, int version, size_t ram_size)
23
{
24
+ RaspiMachineState *s = RASPI_MACHINE(machine);
25
static struct arm_boot_info binfo;
26
int r;
27
28
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
29
binfo.firmware_loaded = true;
30
}
31
32
- arm_load_kernel(ARM_CPU(first_cpu), machine, &binfo);
33
+ arm_load_kernel(&s->soc.cpu[0].core, machine, &binfo);
34
}
35
36
static void raspi_machine_init(MachineState *machine)
37
--
38
2.20.1
39
40
diff view generated by jsdifflib
New patch
[PULL 13/18] hw/arm/raspi: Move arm_boot_info structure to RaspiMachineState
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
The arm_boot_info structure belong to the machine,
4
move it to RaspiMachineState.
5
6
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20200924111808.77168-4-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/raspi.c | 30 +++++++++++++++---------------
12
1 file changed, 15 insertions(+), 15 deletions(-)
13
14
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/raspi.c
17
+++ b/hw/arm/raspi.c
18
@@ -XXX,XX +XXX,XX @@ struct RaspiMachineState {
19
MachineState parent_obj;
20
/*< public >*/
21
BCM283XState soc;
22
+ struct arm_boot_info binfo;
23
};
24
typedef struct RaspiMachineState RaspiMachineState;
25
26
@@ -XXX,XX +XXX,XX @@ static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
27
static void setup_boot(MachineState *machine, int version, size_t ram_size)
28
{
29
RaspiMachineState *s = RASPI_MACHINE(machine);
30
- static struct arm_boot_info binfo;
31
int r;
32
33
- binfo.board_id = MACH_TYPE_BCM2708;
34
- binfo.ram_size = ram_size;
35
- binfo.nb_cpus = machine->smp.cpus;
36
+ s->binfo.board_id = MACH_TYPE_BCM2708;
37
+ s->binfo.ram_size = ram_size;
38
+ s->binfo.nb_cpus = machine->smp.cpus;
39
40
if (version <= 2) {
41
/* The rpi1 and 2 require some custom setup code to run in Secure
42
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
43
* firmware for some cache maintenance operations.
44
* The rpi3 doesn't need this.
45
*/
46
- binfo.board_setup_addr = BOARDSETUP_ADDR;
47
- binfo.write_board_setup = write_board_setup;
48
- binfo.secure_board_setup = true;
49
- binfo.secure_boot = true;
50
+ s->binfo.board_setup_addr = BOARDSETUP_ADDR;
51
+ s->binfo.write_board_setup = write_board_setup;
52
+ s->binfo.secure_board_setup = true;
53
+ s->binfo.secure_boot = true;
54
}
55
56
/* Pi2 and Pi3 requires SMP setup */
57
if (version >= 2) {
58
- binfo.smp_loader_start = SMPBOOT_ADDR;
59
+ s->binfo.smp_loader_start = SMPBOOT_ADDR;
60
if (version == 2) {
61
- binfo.write_secondary_boot = write_smpboot;
62
+ s->binfo.write_secondary_boot = write_smpboot;
63
} else {
64
- binfo.write_secondary_boot = write_smpboot64;
65
+ s->binfo.write_secondary_boot = write_smpboot64;
66
}
67
- binfo.secondary_cpu_reset_hook = reset_secondary;
68
+ s->binfo.secondary_cpu_reset_hook = reset_secondary;
69
}
70
71
/* If the user specified a "firmware" image (e.g. UEFI), we bypass
72
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
73
exit(1);
74
}
75
76
- binfo.entry = firmware_addr;
77
- binfo.firmware_loaded = true;
78
+ s->binfo.entry = firmware_addr;
79
+ s->binfo.firmware_loaded = true;
80
}
81
82
- arm_load_kernel(&s->soc.cpu[0].core, machine, &binfo);
83
+ arm_load_kernel(&s->soc.cpu[0].core, machine, &s->binfo);
84
}
85
86
static void raspi_machine_init(MachineState *machine)
87
--
88
2.20.1
89
90
diff view generated by jsdifflib
New patch
[PULL 14/18] hw/arm/raspi: Avoid using TypeInfo::class_data pointer
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Using class_data pointer to create a MachineClass is not
4
the recommended way anymore. The correct way is to open-code
5
the MachineClass::fields in the class_init() method.
6
7
We can not use TYPE_RASPI_MACHINE::class_base_init() because
8
it is called *before* each machine class_init(), therefore the
9
board_rev field is not populated. We have to manually call
10
raspi_machine_class_common_init() for each machine.
11
12
This partly reverts commit a03bde3674e.
13
14
Suggested-by: Igor Mammedov <imammedo@redhat.com>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
17
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20200924111808.77168-5-f4bug@amsat.org
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
hw/arm/raspi.c | 34 ++++++++++++++++++++++++----------
22
1 file changed, 24 insertions(+), 10 deletions(-)
23
24
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/raspi.c
27
+++ b/hw/arm/raspi.c
28
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine)
29
setup_boot(machine, version, machine->ram_size - vcram_size);
30
}
31
32
-static void raspi_machine_class_init(ObjectClass *oc, void *data)
33
+static void raspi_machine_class_common_init(MachineClass *mc,
34
+ uint32_t board_rev)
35
{
36
- MachineClass *mc = MACHINE_CLASS(oc);
37
- RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
38
- uint32_t board_rev = (uint32_t)(uintptr_t)data;
39
-
40
- rmc->board_rev = board_rev;
41
mc->desc = g_strdup_printf("Raspberry Pi %s (revision 1.%u)",
42
board_type(board_rev),
43
FIELD_EX32(board_rev, REV_CODE, REVISION));
44
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_init(ObjectClass *oc, void *data)
45
mc->default_ram_id = "ram";
46
};
47
48
+static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
49
+{
50
+ MachineClass *mc = MACHINE_CLASS(oc);
51
+ RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
52
+
53
+ rmc->board_rev = 0xa21041;
54
+ raspi_machine_class_common_init(mc, rmc->board_rev);
55
+};
56
+
57
+#ifdef TARGET_AARCH64
58
+static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
59
+{
60
+ MachineClass *mc = MACHINE_CLASS(oc);
61
+ RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
62
+
63
+ rmc->board_rev = 0xa02082;
64
+ raspi_machine_class_common_init(mc, rmc->board_rev);
65
+};
66
+#endif /* TARGET_AARCH64 */
67
+
68
static const TypeInfo raspi_machine_types[] = {
69
{
70
.name = MACHINE_TYPE_NAME("raspi2"),
71
.parent = TYPE_RASPI_MACHINE,
72
- .class_init = raspi_machine_class_init,
73
- .class_data = (void *)0xa21041,
74
+ .class_init = raspi2b_machine_class_init,
75
#ifdef TARGET_AARCH64
76
}, {
77
.name = MACHINE_TYPE_NAME("raspi3"),
78
.parent = TYPE_RASPI_MACHINE,
79
- .class_init = raspi_machine_class_init,
80
- .class_data = (void *)0xa02082,
81
+ .class_init = raspi3b_machine_class_init,
82
#endif
83
}, {
84
.name = TYPE_RASPI_MACHINE,
85
--
86
2.20.1
87
88
diff view generated by jsdifflib
New patch
[PULL 15/18] hw/arm/raspi: Use more specific machine names
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Now that we can instantiate different machines based on their
4
board_rev register value, we can have various raspi2 and raspi3.
5
6
In commit fc78a990ec103 we corrected the machine description.
7
Correct the machine names too. For backward compatibility, add
8
an alias to the previous generic name.
9
10
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
11
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20200924111808.77168-6-f4bug@amsat.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/arm/raspi.c | 6 ++++--
16
1 file changed, 4 insertions(+), 2 deletions(-)
17
18
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/raspi.c
21
+++ b/hw/arm/raspi.c
22
@@ -XXX,XX +XXX,XX @@ static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
23
MachineClass *mc = MACHINE_CLASS(oc);
24
RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
25
26
+ mc->alias = "raspi2";
27
rmc->board_rev = 0xa21041;
28
raspi_machine_class_common_init(mc, rmc->board_rev);
29
};
30
@@ -XXX,XX +XXX,XX @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
31
MachineClass *mc = MACHINE_CLASS(oc);
32
RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
33
34
+ mc->alias = "raspi3";
35
rmc->board_rev = 0xa02082;
36
raspi_machine_class_common_init(mc, rmc->board_rev);
37
};
38
@@ -XXX,XX +XXX,XX @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
39
40
static const TypeInfo raspi_machine_types[] = {
41
{
42
- .name = MACHINE_TYPE_NAME("raspi2"),
43
+ .name = MACHINE_TYPE_NAME("raspi2b"),
44
.parent = TYPE_RASPI_MACHINE,
45
.class_init = raspi2b_machine_class_init,
46
#ifdef TARGET_AARCH64
47
}, {
48
- .name = MACHINE_TYPE_NAME("raspi3"),
49
+ .name = MACHINE_TYPE_NAME("raspi3b"),
50
.parent = TYPE_RASPI_MACHINE,
51
.class_init = raspi3b_machine_class_init,
52
#endif
53
--
54
2.20.1
55
56
diff view generated by jsdifflib
New patch
[PULL 16/18] hw/arm/raspi: Introduce RaspiProcessorId enum
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
As we only support a reduced set of the REV_CODE_PROCESSOR id
4
encoded in the board revision, define the PROCESSOR_ID values
5
as an enum. We can simplify the board_soc_type and cores_count
6
methods.
7
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20200924111808.77168-7-f4bug@amsat.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/raspi.c | 45 +++++++++++++++++++++------------------------
14
1 file changed, 21 insertions(+), 24 deletions(-)
15
16
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/raspi.c
19
+++ b/hw/arm/raspi.c
20
@@ -XXX,XX +XXX,XX @@ FIELD(REV_CODE, MANUFACTURER, 16, 4);
21
FIELD(REV_CODE, MEMORY_SIZE, 20, 3);
22
FIELD(REV_CODE, STYLE, 23, 1);
23
24
+typedef enum RaspiProcessorId {
25
+ PROCESSOR_ID_BCM2836 = 1,
26
+ PROCESSOR_ID_BCM2837 = 2,
27
+} RaspiProcessorId;
28
+
29
+static const struct {
30
+ const char *type;
31
+ int cores_count;
32
+} soc_property[] = {
33
+ [PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS},
34
+ [PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS},
35
+};
36
+
37
static uint64_t board_ram_size(uint32_t board_rev)
38
{
39
assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
40
return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE);
41
}
42
43
-static int board_processor_id(uint32_t board_rev)
44
+static RaspiProcessorId board_processor_id(uint32_t board_rev)
45
{
46
+ int proc_id = FIELD_EX32(board_rev, REV_CODE, PROCESSOR);
47
+
48
assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
49
- return FIELD_EX32(board_rev, REV_CODE, PROCESSOR);
50
+ assert(proc_id < ARRAY_SIZE(soc_property) && soc_property[proc_id].type);
51
+
52
+ return proc_id;
53
}
54
55
static int board_version(uint32_t board_rev)
56
@@ -XXX,XX +XXX,XX @@ static int board_version(uint32_t board_rev)
57
58
static const char *board_soc_type(uint32_t board_rev)
59
{
60
- static const char *soc_types[] = {
61
- NULL, TYPE_BCM2836, TYPE_BCM2837,
62
- };
63
- int proc_id = board_processor_id(board_rev);
64
-
65
- if (proc_id >= ARRAY_SIZE(soc_types) || !soc_types[proc_id]) {
66
- error_report("Unsupported processor id '%d' (board revision: 0x%x)",
67
- proc_id, board_rev);
68
- exit(1);
69
- }
70
- return soc_types[proc_id];
71
+ return soc_property[board_processor_id(board_rev)].type;
72
}
73
74
static int cores_count(uint32_t board_rev)
75
{
76
- static const int soc_cores_count[] = {
77
- 0, BCM283X_NCPUS, BCM283X_NCPUS,
78
- };
79
- int proc_id = board_processor_id(board_rev);
80
-
81
- if (proc_id >= ARRAY_SIZE(soc_cores_count) || !soc_cores_count[proc_id]) {
82
- error_report("Unsupported processor id '%d' (board revision: 0x%x)",
83
- proc_id, board_rev);
84
- exit(1);
85
- }
86
- return soc_cores_count[proc_id];
87
+ return soc_property[board_processor_id(board_rev)].cores_count;
88
}
89
90
static const char *board_type(uint32_t board_rev)
91
--
92
2.20.1
93
94
diff view generated by jsdifflib
New patch
[PULL 17/18] hw/arm/raspi: Use RaspiProcessorId to set the firmware load address
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
The firmware load address depends on the SoC ("processor id") used,
4
not on the version of the board.
5
6
Suggested-by: Luc Michel <luc.michel@greensocs.com>
7
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20200924111808.77168-8-f4bug@amsat.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/raspi.c | 3 ++-
13
1 file changed, 2 insertions(+), 1 deletion(-)
14
15
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/raspi.c
18
+++ b/hw/arm/raspi.c
19
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
20
* the normal Linux boot process
21
*/
22
if (machine->firmware) {
23
- hwaddr firmware_addr = version == 3 ? FIRMWARE_ADDR_3 : FIRMWARE_ADDR_2;
24
+ hwaddr firmware_addr = processor_id <= PROCESSOR_ID_BCM2836
25
+ ? FIRMWARE_ADDR_2 : FIRMWARE_ADDR_3;
26
/* load the firmware image (typically kernel.img) */
27
r = load_image_targphys(machine->firmware, firmware_addr,
28
ram_size - firmware_addr);
29
--
30
2.20.1
31
32
diff view generated by jsdifflib
[PULL 2/4] hw/arm: versal: Add the CRP as unimplemented
[PULL 18/18] hw/arm/raspi: Remove use of the 'version' value in the board code
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Add the CRP as unimplemented thus avoiding bus errors when
3
We expected the 'version' ID to match the board processor ID,
4
guests access these registers.
4
but this is not always true (for example boards with revision
5
id 0xa02042/0xa22042 are Raspberry Pi 2 with a BCM2837 SoC).
6
This was not important because we were not modelling them, but
7
since the recent refactor now allow to model these boards, it
8
is safer to check the processor id directly. Remove the version
9
check.
5
10
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
11
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
12
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
Message-id: 20191115154734.26449-2-edgar.iglesias@gmail.com
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20200924111808.77168-9-f4bug@amsat.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
16
---
12
include/hw/arm/xlnx-versal.h | 3 +++
17
hw/arm/raspi.c | 29 +++++++++++++----------------
13
hw/arm/xlnx-versal.c | 2 ++
18
1 file changed, 13 insertions(+), 16 deletions(-)
14
2 files changed, 5 insertions(+)
15
19
16
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
20
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
17
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/xlnx-versal.h
22
--- a/hw/arm/raspi.c
19
+++ b/include/hw/arm/xlnx-versal.h
23
+++ b/hw/arm/raspi.c
20
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
24
@@ -XXX,XX +XXX,XX @@ static RaspiProcessorId board_processor_id(uint32_t board_rev)
21
#define MM_IOU_SCNTRS_SIZE 0x10000
25
return proc_id;
22
#define MM_FPD_CRF 0xfd1a0000U
26
}
23
#define MM_FPD_CRF_SIZE 0x140000
27
24
+
28
-static int board_version(uint32_t board_rev)
25
+#define MM_PMC_CRP 0xf1260000U
29
-{
26
+#define MM_PMC_CRP_SIZE 0x10000
30
- return board_processor_id(board_rev) + 1;
27
#endif
31
-}
28
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
32
-
29
index XXXXXXX..XXXXXXX 100644
33
static const char *board_soc_type(uint32_t board_rev)
30
--- a/hw/arm/xlnx-versal.c
34
{
31
+++ b/hw/arm/xlnx-versal.c
35
return soc_property[board_processor_id(board_rev)].type;
32
@@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s)
36
@@ -XXX,XX +XXX,XX @@ static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
33
MM_CRL, MM_CRL_SIZE);
37
cpu_set_pc(cs, info->smp_loader_start);
34
versal_unimp_area(s, "crf", &s->mr_ps,
38
}
35
MM_FPD_CRF, MM_FPD_CRF_SIZE);
39
36
+ versal_unimp_area(s, "crp", &s->mr_ps,
40
-static void setup_boot(MachineState *machine, int version, size_t ram_size)
37
+ MM_PMC_CRP, MM_PMC_CRP_SIZE);
41
+static void setup_boot(MachineState *machine, RaspiProcessorId processor_id,
38
versal_unimp_area(s, "iou-scntr", &s->mr_ps,
42
+ size_t ram_size)
39
MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
43
{
40
versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,
44
RaspiMachineState *s = RASPI_MACHINE(machine);
45
int r;
46
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
47
s->binfo.ram_size = ram_size;
48
s->binfo.nb_cpus = machine->smp.cpus;
49
50
- if (version <= 2) {
51
- /* The rpi1 and 2 require some custom setup code to run in Secure
52
- * mode before booting a kernel (to set up the SMC vectors so
53
- * that we get a no-op SMC; this is used by Linux to call the
54
+ if (processor_id <= PROCESSOR_ID_BCM2836) {
55
+ /*
56
+ * The BCM2835 and BCM2836 require some custom setup code to run
57
+ * in Secure mode before booting a kernel (to set up the SMC vectors
58
+ * so that we get a no-op SMC; this is used by Linux to call the
59
* firmware for some cache maintenance operations.
60
- * The rpi3 doesn't need this.
61
+ * The BCM2837 doesn't need this.
62
*/
63
s->binfo.board_setup_addr = BOARDSETUP_ADDR;
64
s->binfo.write_board_setup = write_board_setup;
65
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
66
s->binfo.secure_boot = true;
67
}
68
69
- /* Pi2 and Pi3 requires SMP setup */
70
- if (version >= 2) {
71
+ /* BCM2836 and BCM2837 requires SMP setup */
72
+ if (processor_id >= PROCESSOR_ID_BCM2836) {
73
s->binfo.smp_loader_start = SMPBOOT_ADDR;
74
- if (version == 2) {
75
+ if (processor_id == PROCESSOR_ID_BCM2836) {
76
s->binfo.write_secondary_boot = write_smpboot;
77
} else {
78
s->binfo.write_secondary_boot = write_smpboot64;
79
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine)
80
RaspiMachineClass *mc = RASPI_MACHINE_GET_CLASS(machine);
81
RaspiMachineState *s = RASPI_MACHINE(machine);
82
uint32_t board_rev = mc->board_rev;
83
- int version = board_version(board_rev);
84
uint64_t ram_size = board_ram_size(board_rev);
85
uint32_t vcram_size;
86
DriveInfo *di;
87
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine)
88
89
vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size",
90
&error_abort);
91
- setup_boot(machine, version, machine->ram_size - vcram_size);
92
+ setup_boot(machine, board_processor_id(mc->board_rev),
93
+ machine->ram_size - vcram_size);
94
}
95
96
static void raspi_machine_class_common_init(MachineClass *mc,
41
--
97
--
42
2.20.1
98
2.20.1
43
99
44
100
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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