| 1 | Arm patches for rc3 : just a handful of bug fixes. | 1 | Not much here, mostly documentation, but a few bug fixes. |
|---|---|---|---|
| 2 | 2 | ||
| 3 | thanks | 3 | thanks |
| 4 | -- PMM | 4 | -- PMM |
| 5 | 5 | ||
| 6 | The following changes since commit 873ec69aeb12e24eec7fb317fd0cd8494e8489dd: | ||
| 6 | 7 | ||
| 7 | The following changes since commit 4ecc984210ca1bf508a96a550ec8a93a5f833f6c: | 8 | Merge remote-tracking branch 'remotes/cminyard/tags/for-qemu-i2c-5' into staging (2020-07-20 11:03:09 +0100) |
| 8 | |||
| 9 | Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc3' into staging (2019-11-26 12:36:40 +0000) | ||
| 10 | 9 | ||
| 11 | are available in the Git repository at: | 10 | are available in the Git repository at: |
| 12 | 11 | ||
| 13 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191126 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200720 |
| 14 | 13 | ||
| 15 | for you to fetch changes up to 6a4ef4e5d1084ce41fafa7d470a644b0fd3d9317: | 14 | for you to fetch changes up to 6a0b7505f1fd6769c3f1558fda76464d51e4118a: |
| 16 | 15 | ||
| 17 | target/arm: Honor HCR_EL2.TID3 trapping requirements (2019-11-26 13:55:37 +0000) | 16 | docs/system: Document the arm virt board (2020-07-20 11:35:17 +0100) |
| 18 | 17 | ||
| 19 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
| 20 | target-arm queue: | 19 | target-arm queue: |
| 21 | * handle FTYPE flag correctly in v7M exception return | 20 | * virt: Don't enable MTE emulation by default |
| 22 | for v7M CPUs with an FPU (v8M CPUs were already correct) | 21 | * virt: Diagnose attempts to use MTE with memory-hotplug or KVM |
| 23 | * versal: Add the CRP as unimplemented | 22 | (rather than silently not working correctly) |
| 24 | * Fix ISR_EL1 tracking when executing at EL2 | 23 | * util: Implement qemu_get_thread_id() for OpenBSD |
| 25 | * Honor HCR_EL2.TID3 trapping requirements | 24 | * qdev: Add doc comments for qdev_unrealize and GPIO functions, |
| 25 | and standardize on doc-comments-in-header-file | ||
| 26 | * hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize() | ||
| 27 | * docs/system: Document canon-a1100, collie, gumstix, virt boards | ||
| 26 | 28 | ||
| 27 | ---------------------------------------------------------------- | 29 | ---------------------------------------------------------------- |
| 28 | Edgar E. Iglesias (1): | 30 | David CARLIER (1): |
| 29 | hw/arm: versal: Add the CRP as unimplemented | 31 | util: Implement qemu_get_thread_id() for OpenBSD |
| 30 | 32 | ||
| 31 | Jean-Hugues Deschênes (1): | 33 | Peter Maydell (8): |
| 32 | target/arm: Fix handling of cortex-m FTYPE flag in EXCRET | 34 | qdev: Move doc comments from qdev.c to qdev-core.h |
| 35 | qdev: Document qdev_unrealize() | ||
| 36 | qdev: Document GPIO related functions | ||
| 37 | hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize() | ||
| 38 | docs/system: Briefly document canon-a1100 board | ||
| 39 | docs/system: Briefly document collie board | ||
| 40 | docs/system: Briefly document gumstix boards | ||
| 41 | docs/system: Document the arm virt board | ||
| 33 | 42 | ||
| 34 | Marc Zyngier (2): | 43 | Richard Henderson (3): |
| 35 | target/arm: Fix ISR_EL1 tracking when executing at EL2 | 44 | hw/arm/virt: Enable MTE via a machine property |
| 36 | target/arm: Honor HCR_EL2.TID3 trapping requirements | 45 | hw/arm/virt: Error for MTE enabled with KVM |
| 46 | hw/arm/virt: Disable memory hotplug when MTE is enabled | ||
| 37 | 47 | ||
| 38 | include/hw/arm/xlnx-versal.h | 3 ++ | 48 | docs/system/arm/collie.rst | 16 +++ |
| 39 | hw/arm/xlnx-versal.c | 2 ++ | 49 | docs/system/arm/digic.rst | 11 ++ |
| 40 | target/arm/helper.c | 83 ++++++++++++++++++++++++++++++++++++++++++-- | 50 | docs/system/arm/gumstix.rst | 21 ++++ |
| 41 | target/arm/m_helper.c | 7 ++-- | 51 | docs/system/arm/virt.rst | 161 ++++++++++++++++++++++++++ |
| 42 | 4 files changed, 89 insertions(+), 6 deletions(-) | 52 | docs/system/target-arm.rst | 4 + |
| 53 | include/hw/arm/virt.h | 1 + | ||
| 54 | include/hw/qdev-core.h | 267 ++++++++++++++++++++++++++++++++++++++++++- | ||
| 55 | include/hw/qdev-properties.h | 13 +++ | ||
| 56 | hw/arm/armsse.c | 2 + | ||
| 57 | hw/arm/virt.c | 50 +++++++- | ||
| 58 | hw/core/qdev.c | 33 ------ | ||
| 59 | target/arm/cpu.c | 19 +-- | ||
| 60 | target/arm/cpu64.c | 5 +- | ||
| 61 | util/oslib-posix.c | 2 + | ||
| 62 | MAINTAINERS | 4 + | ||
| 63 | 15 files changed, 559 insertions(+), 50 deletions(-) | ||
| 64 | create mode 100644 docs/system/arm/collie.rst | ||
| 65 | create mode 100644 docs/system/arm/digic.rst | ||
| 66 | create mode 100644 docs/system/arm/gumstix.rst | ||
| 67 | create mode 100644 docs/system/arm/virt.rst | ||
| 43 | 68 | diff view generated by jsdifflib |
| 1 | From: Marc Zyngier <maz@kernel.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | HCR_EL2.TID3 mandates that access from EL1 to a long list of id | 3 | Control this cpu feature via a machine property, much as we do |
| 4 | registers traps to EL2, and QEMU has so far ignored this requirement. | 4 | with secure=on, since both require specialized support in the |
| 5 | machine setup to be functional. | ||
| 5 | 6 | ||
| 6 | This breaks (among other things) KVM guests that have PtrAuth enabled, | 7 | Default MTE to off, since this feature implies extra overhead. |
| 7 | while the hypervisor doesn't want to expose the feature to its guest. | ||
| 8 | To achieve this, KVM traps the ID registers (ID_AA64ISAR1_EL1 in this | ||
| 9 | case), and masks out the unsupported feature. | ||
| 10 | 8 | ||
| 11 | QEMU not honoring the trap request means that the guest observes | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 12 | that the feature is present in the HW, starts using it, and dies | 10 | Message-id: 20200713213341.590275-2-richard.henderson@linaro.org |
| 13 | a horrible death when KVM injects an UNDEF, because the feature | ||
| 14 | *really* isn't supported. | ||
| 15 | |||
| 16 | Do the right thing by trapping to EL2 if HCR_EL2.TID3 is set. | ||
| 17 | |||
| 18 | Note that this change does not include trapping of the MVFR | ||
| 19 | registers from AArch32 (they are accessed via the VMRS | ||
| 20 | instruction and need to be handled in a different way). | ||
| 21 | |||
| 22 | Reported-by: Will Deacon <will@kernel.org> | ||
| 23 | Signed-off-by: Marc Zyngier <maz@kernel.org> | ||
| 24 | Tested-by: Will Deacon <will@kernel.org> | ||
| 25 | Message-id: 20191123115618.29230-1-maz@kernel.org | ||
| 26 | [PMM: added missing accessfn line for ID_AA4PFR2_EL1_RESERVED; | ||
| 27 | changed names of access functions to include _tid3] | ||
| 28 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 29 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 30 | --- | 13 | --- |
| 31 | target/arm/helper.c | 76 +++++++++++++++++++++++++++++++++++++++++++++ | 14 | include/hw/arm/virt.h | 1 + |
| 32 | 1 file changed, 76 insertions(+) | 15 | hw/arm/virt.c | 39 ++++++++++++++++++++++++++++++++++----- |
| 16 | target/arm/cpu.c | 19 +++++++++++-------- | ||
| 17 | target/arm/cpu64.c | 5 +++-- | ||
| 18 | 4 files changed, 49 insertions(+), 15 deletions(-) | ||
| 33 | 19 | ||
| 34 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 20 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h |
| 35 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
| 36 | --- a/target/arm/helper.c | 22 | --- a/include/hw/arm/virt.h |
| 37 | +++ b/target/arm/helper.c | 23 | +++ b/include/hw/arm/virt.h |
| 38 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = { | 24 | @@ -XXX,XX +XXX,XX @@ typedef struct { |
| 39 | REGINFO_SENTINEL | 25 | bool its; |
| 40 | }; | 26 | bool virt; |
| 41 | 27 | bool ras; | |
| 42 | +static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri, | 28 | + bool mte; |
| 43 | + bool isread) | 29 | OnOffAuto acpi; |
| 30 | VirtGICType gic_version; | ||
| 31 | VirtIOMMUType iommu; | ||
| 32 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
| 33 | index XXXXXXX..XXXXXXX 100644 | ||
| 34 | --- a/hw/arm/virt.c | ||
| 35 | +++ b/hw/arm/virt.c | ||
| 36 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
| 37 | OBJECT(secure_sysmem), &error_abort); | ||
| 38 | } | ||
| 39 | |||
| 40 | - /* | ||
| 41 | - * The cpu adds the property if and only if MemTag is supported. | ||
| 42 | - * If it is, we must allocate the ram to back that up. | ||
| 43 | - */ | ||
| 44 | - if (object_property_find(cpuobj, "tag-memory", NULL)) { | ||
| 45 | + if (vms->mte) { | ||
| 46 | + /* Create the memory region only once, but link to all cpus. */ | ||
| 47 | if (!tag_sysmem) { | ||
| 48 | + /* | ||
| 49 | + * The property exists only if MemTag is supported. | ||
| 50 | + * If it is, we must allocate the ram to back that up. | ||
| 51 | + */ | ||
| 52 | + if (!object_property_find(cpuobj, "tag-memory", NULL)) { | ||
| 53 | + error_report("MTE requested, but not supported " | ||
| 54 | + "by the guest CPU"); | ||
| 55 | + exit(1); | ||
| 56 | + } | ||
| 57 | + | ||
| 58 | tag_sysmem = g_new(MemoryRegion, 1); | ||
| 59 | memory_region_init(tag_sysmem, OBJECT(machine), | ||
| 60 | "tag-memory", UINT64_MAX / 32); | ||
| 61 | @@ -XXX,XX +XXX,XX @@ static void virt_set_ras(Object *obj, bool value, Error **errp) | ||
| 62 | vms->ras = value; | ||
| 63 | } | ||
| 64 | |||
| 65 | +static bool virt_get_mte(Object *obj, Error **errp) | ||
| 44 | +{ | 66 | +{ |
| 45 | + if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) { | 67 | + VirtMachineState *vms = VIRT_MACHINE(obj); |
| 46 | + return CP_ACCESS_TRAP_EL2; | ||
| 47 | + } | ||
| 48 | + | 68 | + |
| 49 | + return CP_ACCESS_OK; | 69 | + return vms->mte; |
| 50 | +} | 70 | +} |
| 51 | + | 71 | + |
| 52 | +static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri, | 72 | +static void virt_set_mte(Object *obj, bool value, Error **errp) |
| 53 | + bool isread) | ||
| 54 | +{ | 73 | +{ |
| 55 | + if (arm_feature(env, ARM_FEATURE_V8)) { | 74 | + VirtMachineState *vms = VIRT_MACHINE(obj); |
| 56 | + return access_aa64_tid3(env, ri, isread); | ||
| 57 | + } | ||
| 58 | + | 75 | + |
| 59 | + return CP_ACCESS_OK; | 76 | + vms->mte = value; |
| 60 | +} | 77 | +} |
| 61 | + | 78 | + |
| 62 | void register_cp_regs_for_features(ARMCPU *cpu) | 79 | static char *virt_get_gic_version(Object *obj, Error **errp) |
| 63 | { | 80 | { |
| 64 | /* Register all the coprocessor registers based on feature bits */ | 81 | VirtMachineState *vms = VIRT_MACHINE(obj); |
| 65 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | 82 | @@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj) |
| 66 | { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, | 83 | "Set on/off to enable/disable reporting host memory errors " |
| 67 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | 84 | "to a KVM guest using ACPI and guest external abort exceptions"); |
| 68 | .access = PL1_R, .type = ARM_CP_CONST, | 85 | |
| 69 | + .accessfn = access_aa32_tid3, | 86 | + /* MTE is disabled by default. */ |
| 70 | .resetvalue = cpu->id_pfr0 }, | 87 | + vms->mte = false; |
| 71 | /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know | 88 | + object_property_add_bool(obj, "mte", virt_get_mte, virt_set_mte); |
| 72 | * the value of the GIC field until after we define these regs. | 89 | + object_property_set_description(obj, "mte", |
| 73 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | 90 | + "Set on/off to enable/disable emulating a " |
| 74 | { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, | 91 | + "guest CPU which implements the ARM " |
| 75 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | 92 | + "Memory Tagging Extension"); |
| 76 | .access = PL1_R, .type = ARM_CP_NO_RAW, | 93 | + |
| 77 | + .accessfn = access_aa32_tid3, | 94 | vms->irqmap = a15irqmap; |
| 78 | .readfn = id_pfr1_read, | 95 | |
| 79 | .writefn = arm_cp_write_ignore }, | 96 | virt_flash_create(vms); |
| 80 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, | 97 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
| 81 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | 98 | index XXXXXXX..XXXXXXX 100644 |
| 82 | .access = PL1_R, .type = ARM_CP_CONST, | 99 | --- a/target/arm/cpu.c |
| 83 | + .accessfn = access_aa32_tid3, | 100 | +++ b/target/arm/cpu.c |
| 84 | .resetvalue = cpu->id_dfr0 }, | 101 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
| 85 | { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, | 102 | cpu->id_pfr1 &= ~0xf000; |
| 86 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, | 103 | } |
| 87 | .access = PL1_R, .type = ARM_CP_CONST, | 104 | |
| 88 | + .accessfn = access_aa32_tid3, | 105 | +#ifndef CONFIG_USER_ONLY |
| 89 | .resetvalue = cpu->id_afr0 }, | 106 | + if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { |
| 90 | { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, | 107 | + /* |
| 91 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, | 108 | + * Disable the MTE feature bits if we do not have tag-memory |
| 92 | .access = PL1_R, .type = ARM_CP_CONST, | 109 | + * provided by the machine. |
| 93 | + .accessfn = access_aa32_tid3, | 110 | + */ |
| 94 | .resetvalue = cpu->id_mmfr0 }, | 111 | + cpu->isar.id_aa64pfr1 = |
| 95 | { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, | 112 | + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); |
| 96 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, | 113 | + } |
| 97 | .access = PL1_R, .type = ARM_CP_CONST, | 114 | +#endif |
| 98 | + .accessfn = access_aa32_tid3, | 115 | + |
| 99 | .resetvalue = cpu->id_mmfr1 }, | 116 | /* MPU can be configured out of a PMSA CPU either by setting has-mpu |
| 100 | { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, | 117 | * to false or by setting pmsav7-dregion to 0. |
| 101 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, | 118 | */ |
| 102 | .access = PL1_R, .type = ARM_CP_CONST, | 119 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
| 103 | + .accessfn = access_aa32_tid3, | 120 | cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", |
| 104 | .resetvalue = cpu->id_mmfr2 }, | 121 | cpu->secure_tag_memory); |
| 105 | { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, | 122 | } |
| 106 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, | 123 | - } else if (cpu_isar_feature(aa64_mte, cpu)) { |
| 107 | .access = PL1_R, .type = ARM_CP_CONST, | 124 | - /* |
| 108 | + .accessfn = access_aa32_tid3, | 125 | - * Since there is no tag memory, we can't meaningfully support MTE |
| 109 | .resetvalue = cpu->id_mmfr3 }, | 126 | - * to its fullest. To avoid problems later, when we would come to |
| 110 | { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, | 127 | - * use the tag memory, downgrade support to insns only. |
| 111 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | 128 | - */ |
| 112 | .access = PL1_R, .type = ARM_CP_CONST, | 129 | - cpu->isar.id_aa64pfr1 = |
| 113 | + .accessfn = access_aa32_tid3, | 130 | - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); |
| 114 | .resetvalue = cpu->isar.id_isar0 }, | 131 | } |
| 115 | { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, | 132 | |
| 116 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, | 133 | cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); |
| 117 | .access = PL1_R, .type = ARM_CP_CONST, | 134 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
| 118 | + .accessfn = access_aa32_tid3, | 135 | index XXXXXXX..XXXXXXX 100644 |
| 119 | .resetvalue = cpu->isar.id_isar1 }, | 136 | --- a/target/arm/cpu64.c |
| 120 | { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, | 137 | +++ b/target/arm/cpu64.c |
| 121 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | 138 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
| 122 | .access = PL1_R, .type = ARM_CP_CONST, | 139 | t = cpu->isar.id_aa64pfr1; |
| 123 | + .accessfn = access_aa32_tid3, | 140 | t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); |
| 124 | .resetvalue = cpu->isar.id_isar2 }, | 141 | /* |
| 125 | { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, | 142 | - * Begin with full support for MTE; will be downgraded to MTE=1 |
| 126 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, | 143 | - * during realize if the board provides no tag memory. |
| 127 | .access = PL1_R, .type = ARM_CP_CONST, | 144 | + * Begin with full support for MTE. This will be downgraded to MTE=0 |
| 128 | + .accessfn = access_aa32_tid3, | 145 | + * during realize if the board provides no tag memory, much like |
| 129 | .resetvalue = cpu->isar.id_isar3 }, | 146 | + * we do for EL2 with the virtualization=on property. |
| 130 | { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, | 147 | */ |
| 131 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, | 148 | t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); |
| 132 | .access = PL1_R, .type = ARM_CP_CONST, | 149 | cpu->isar.id_aa64pfr1 = t; |
| 133 | + .accessfn = access_aa32_tid3, | ||
| 134 | .resetvalue = cpu->isar.id_isar4 }, | ||
| 135 | { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, | ||
| 136 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, | ||
| 137 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 138 | + .accessfn = access_aa32_tid3, | ||
| 139 | .resetvalue = cpu->isar.id_isar5 }, | ||
| 140 | { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, | ||
| 141 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, | ||
| 142 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 143 | + .accessfn = access_aa32_tid3, | ||
| 144 | .resetvalue = cpu->id_mmfr4 }, | ||
| 145 | { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH, | ||
| 146 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, | ||
| 147 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 148 | + .accessfn = access_aa32_tid3, | ||
| 149 | .resetvalue = cpu->isar.id_isar6 }, | ||
| 150 | REGINFO_SENTINEL | ||
| 151 | }; | ||
| 152 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
| 153 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, | ||
| 154 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | ||
| 155 | .access = PL1_R, .type = ARM_CP_NO_RAW, | ||
| 156 | + .accessfn = access_aa64_tid3, | ||
| 157 | .readfn = id_aa64pfr0_read, | ||
| 158 | .writefn = arm_cp_write_ignore }, | ||
| 159 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, | ||
| 160 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | ||
| 161 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 162 | + .accessfn = access_aa64_tid3, | ||
| 163 | .resetvalue = cpu->isar.id_aa64pfr1}, | ||
| 164 | { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 165 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, | ||
| 166 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 167 | + .accessfn = access_aa64_tid3, | ||
| 168 | .resetvalue = 0 }, | ||
| 169 | { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 170 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, | ||
| 171 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 172 | + .accessfn = access_aa64_tid3, | ||
| 173 | .resetvalue = 0 }, | ||
| 174 | { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64, | ||
| 175 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, | ||
| 176 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 177 | + .accessfn = access_aa64_tid3, | ||
| 178 | /* At present, only SVEver == 0 is defined anyway. */ | ||
| 179 | .resetvalue = 0 }, | ||
| 180 | { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 181 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, | ||
| 182 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 183 | + .accessfn = access_aa64_tid3, | ||
| 184 | .resetvalue = 0 }, | ||
| 185 | { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 186 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, | ||
| 187 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 188 | + .accessfn = access_aa64_tid3, | ||
| 189 | .resetvalue = 0 }, | ||
| 190 | { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 191 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, | ||
| 192 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 193 | + .accessfn = access_aa64_tid3, | ||
| 194 | .resetvalue = 0 }, | ||
| 195 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, | ||
| 196 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | ||
| 197 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 198 | + .accessfn = access_aa64_tid3, | ||
| 199 | .resetvalue = cpu->id_aa64dfr0 }, | ||
| 200 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, | ||
| 201 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | ||
| 202 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 203 | + .accessfn = access_aa64_tid3, | ||
| 204 | .resetvalue = cpu->id_aa64dfr1 }, | ||
| 205 | { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 206 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, | ||
| 207 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 208 | + .accessfn = access_aa64_tid3, | ||
| 209 | .resetvalue = 0 }, | ||
| 210 | { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 211 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, | ||
| 212 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 213 | + .accessfn = access_aa64_tid3, | ||
| 214 | .resetvalue = 0 }, | ||
| 215 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, | ||
| 216 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | ||
| 217 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 218 | + .accessfn = access_aa64_tid3, | ||
| 219 | .resetvalue = cpu->id_aa64afr0 }, | ||
| 220 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | ||
| 221 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | ||
| 222 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 223 | + .accessfn = access_aa64_tid3, | ||
| 224 | .resetvalue = cpu->id_aa64afr1 }, | ||
| 225 | { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 226 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, | ||
| 227 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 228 | + .accessfn = access_aa64_tid3, | ||
| 229 | .resetvalue = 0 }, | ||
| 230 | { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 231 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, | ||
| 232 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 233 | + .accessfn = access_aa64_tid3, | ||
| 234 | .resetvalue = 0 }, | ||
| 235 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, | ||
| 236 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | ||
| 237 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 238 | + .accessfn = access_aa64_tid3, | ||
| 239 | .resetvalue = cpu->isar.id_aa64isar0 }, | ||
| 240 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, | ||
| 241 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | ||
| 242 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 243 | + .accessfn = access_aa64_tid3, | ||
| 244 | .resetvalue = cpu->isar.id_aa64isar1 }, | ||
| 245 | { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 246 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, | ||
| 247 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 248 | + .accessfn = access_aa64_tid3, | ||
| 249 | .resetvalue = 0 }, | ||
| 250 | { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 251 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, | ||
| 252 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 253 | + .accessfn = access_aa64_tid3, | ||
| 254 | .resetvalue = 0 }, | ||
| 255 | { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 256 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, | ||
| 257 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 258 | + .accessfn = access_aa64_tid3, | ||
| 259 | .resetvalue = 0 }, | ||
| 260 | { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 261 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, | ||
| 262 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 263 | + .accessfn = access_aa64_tid3, | ||
| 264 | .resetvalue = 0 }, | ||
| 265 | { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 266 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, | ||
| 267 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 268 | + .accessfn = access_aa64_tid3, | ||
| 269 | .resetvalue = 0 }, | ||
| 270 | { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 271 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, | ||
| 272 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 273 | + .accessfn = access_aa64_tid3, | ||
| 274 | .resetvalue = 0 }, | ||
| 275 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, | ||
| 276 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | ||
| 277 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 278 | + .accessfn = access_aa64_tid3, | ||
| 279 | .resetvalue = cpu->isar.id_aa64mmfr0 }, | ||
| 280 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, | ||
| 281 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | ||
| 282 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 283 | + .accessfn = access_aa64_tid3, | ||
| 284 | .resetvalue = cpu->isar.id_aa64mmfr1 }, | ||
| 285 | { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 286 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, | ||
| 287 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 288 | + .accessfn = access_aa64_tid3, | ||
| 289 | .resetvalue = 0 }, | ||
| 290 | { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 291 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, | ||
| 292 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 293 | + .accessfn = access_aa64_tid3, | ||
| 294 | .resetvalue = 0 }, | ||
| 295 | { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 296 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, | ||
| 297 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 298 | + .accessfn = access_aa64_tid3, | ||
| 299 | .resetvalue = 0 }, | ||
| 300 | { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 301 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, | ||
| 302 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 303 | + .accessfn = access_aa64_tid3, | ||
| 304 | .resetvalue = 0 }, | ||
| 305 | { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 306 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, | ||
| 307 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 308 | + .accessfn = access_aa64_tid3, | ||
| 309 | .resetvalue = 0 }, | ||
| 310 | { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 311 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, | ||
| 312 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 313 | + .accessfn = access_aa64_tid3, | ||
| 314 | .resetvalue = 0 }, | ||
| 315 | { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, | ||
| 316 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | ||
| 317 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 318 | + .accessfn = access_aa64_tid3, | ||
| 319 | .resetvalue = cpu->isar.mvfr0 }, | ||
| 320 | { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, | ||
| 321 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | ||
| 322 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 323 | + .accessfn = access_aa64_tid3, | ||
| 324 | .resetvalue = cpu->isar.mvfr1 }, | ||
| 325 | { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, | ||
| 326 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | ||
| 327 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 328 | + .accessfn = access_aa64_tid3, | ||
| 329 | .resetvalue = cpu->isar.mvfr2 }, | ||
| 330 | { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 331 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, | ||
| 332 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 333 | + .accessfn = access_aa64_tid3, | ||
| 334 | .resetvalue = 0 }, | ||
| 335 | { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 336 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, | ||
| 337 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 338 | + .accessfn = access_aa64_tid3, | ||
| 339 | .resetvalue = 0 }, | ||
| 340 | { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 341 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, | ||
| 342 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 343 | + .accessfn = access_aa64_tid3, | ||
| 344 | .resetvalue = 0 }, | ||
| 345 | { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 346 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, | ||
| 347 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 348 | + .accessfn = access_aa64_tid3, | ||
| 349 | .resetvalue = 0 }, | ||
| 350 | { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
| 351 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, | ||
| 352 | .access = PL1_R, .type = ARM_CP_CONST, | ||
| 353 | + .accessfn = access_aa64_tid3, | ||
| 354 | .resetvalue = 0 }, | ||
| 355 | { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, | ||
| 356 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, | ||
| 357 | -- | 150 | -- |
| 358 | 2.20.1 | 151 | 2.20.1 |
| 359 | 152 | ||
| 360 | 153 | diff view generated by jsdifflib |
| 1 | From: Marc Zyngier <maz@kernel.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The ARMv8 ARM states when executing at EL2, EL3 or Secure EL1, | 3 | While we expect KVM to support MTE at some future point, |
| 4 | ISR_EL1 shows the pending status of the physical IRQ, FIQ, or | 4 | it certainly won't be ready in time for qemu 5.1. |
| 5 | SError interrupts. | ||
| 6 | 5 | ||
| 7 | Unfortunately, QEMU's implementation only considers the HCR_EL2 | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | bits, and ignores the current exception level. This means a hypervisor | 7 | Message-id: 20200713213341.590275-3-richard.henderson@linaro.org |
| 9 | trying to look at its own interrupt state actually sees the guest | ||
| 10 | state, which is unexpected and breaks KVM as of Linux 5.3. | ||
| 11 | |||
| 12 | Instead, check for the running EL and return the physical bits | ||
| 13 | if not running in a virtualized context. | ||
| 14 | |||
| 15 | Fixes: 636540e9c40b | ||
| 16 | Cc: qemu-stable@nongnu.org | ||
| 17 | Reported-by: Quentin Perret <qperret@google.com> | ||
| 18 | Signed-off-by: Marc Zyngier <maz@kernel.org> | ||
| 19 | Message-id: 20191122135833.28953-1-maz@kernel.org | ||
| 20 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 21 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 23 | --- | 10 | --- |
| 24 | target/arm/helper.c | 7 +++++-- | 11 | hw/arm/virt.c | 6 ++++++ |
| 25 | 1 file changed, 5 insertions(+), 2 deletions(-) | 12 | 1 file changed, 6 insertions(+) |
| 26 | 13 | ||
| 27 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 14 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
| 28 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 29 | --- a/target/arm/helper.c | 16 | --- a/hw/arm/virt.c |
| 30 | +++ b/target/arm/helper.c | 17 | +++ b/hw/arm/virt.c |
| 31 | @@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) | 18 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) |
| 32 | CPUState *cs = env_cpu(env); | 19 | exit(1); |
| 33 | uint64_t hcr_el2 = arm_hcr_el2_eff(env); | ||
| 34 | uint64_t ret = 0; | ||
| 35 | + bool allow_virt = (arm_current_el(env) == 1 && | ||
| 36 | + (!arm_is_secure_below_el3(env) || | ||
| 37 | + (env->cp15.scr_el3 & SCR_EEL2))); | ||
| 38 | |||
| 39 | - if (hcr_el2 & HCR_IMO) { | ||
| 40 | + if (allow_virt && (hcr_el2 & HCR_IMO)) { | ||
| 41 | if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { | ||
| 42 | ret |= CPSR_I; | ||
| 43 | } | ||
| 44 | @@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
| 45 | } | ||
| 46 | } | 20 | } |
| 47 | 21 | ||
| 48 | - if (hcr_el2 & HCR_FMO) { | 22 | + if (vms->mte && kvm_enabled()) { |
| 49 | + if (allow_virt && (hcr_el2 & HCR_FMO)) { | 23 | + error_report("mach-virt: KVM does not support providing " |
| 50 | if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { | 24 | + "MTE to the guest CPU"); |
| 51 | ret |= CPSR_F; | 25 | + exit(1); |
| 52 | } | 26 | + } |
| 27 | + | ||
| 28 | create_fdt(vms); | ||
| 29 | |||
| 30 | possible_cpus = mc->possible_cpu_arch_ids(machine); | ||
| 53 | -- | 31 | -- |
| 54 | 2.20.1 | 32 | 2.20.1 |
| 55 | 33 | ||
| 56 | 34 | diff view generated by jsdifflib |
| 1 | From: Jean-Hugues Deschênes <Jean-Hugues.Deschenes@ossiaco.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | According to the PushStack() pseudocode in the armv7m RM, | 3 | When MTE is enabled, tag memory must exist for all RAM. |
| 4 | bit 4 of the LR should be set to NOT(CONTROL.PFCA) when | ||
| 5 | an FPU is present. Current implementation is doing it for | ||
| 6 | armv8, but not for armv7. This patch makes the existing | ||
| 7 | logic applicable to both code paths. | ||
| 8 | 4 | ||
| 9 | Signed-off-by: Jean-Hugues Deschenes <jean-hugues.deschenes@ossiaco.com> | 5 | It might be possible to simultaneously hot plug tag memory |
| 6 | alongside the corresponding normal memory, but for now just | ||
| 7 | disable hotplug. | ||
| 8 | |||
| 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 10 | Message-id: 20200713213341.590275-4-richard.henderson@linaro.org | ||
| 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 12 | --- | 13 | --- |
| 13 | target/arm/m_helper.c | 7 +++---- | 14 | hw/arm/virt.c | 5 +++++ |
| 14 | 1 file changed, 3 insertions(+), 4 deletions(-) | 15 | 1 file changed, 5 insertions(+) |
| 15 | 16 | ||
| 16 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | 17 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
| 17 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/target/arm/m_helper.c | 19 | --- a/hw/arm/virt.c |
| 19 | +++ b/target/arm/m_helper.c | 20 | +++ b/hw/arm/virt.c |
| 20 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | 21 | @@ -XXX,XX +XXX,XX @@ static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
| 21 | if (env->v7m.secure) { | 22 | return; |
| 22 | lr |= R_V7M_EXCRET_S_MASK; | ||
| 23 | } | ||
| 24 | - if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) { | ||
| 25 | - lr |= R_V7M_EXCRET_FTYPE_MASK; | ||
| 26 | - } | ||
| 27 | } else { | ||
| 28 | lr = R_V7M_EXCRET_RES1_MASK | | ||
| 29 | R_V7M_EXCRET_S_MASK | | ||
| 30 | R_V7M_EXCRET_DCRS_MASK | | ||
| 31 | - R_V7M_EXCRET_FTYPE_MASK | | ||
| 32 | R_V7M_EXCRET_ES_MASK; | ||
| 33 | if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) { | ||
| 34 | lr |= R_V7M_EXCRET_SPSEL_MASK; | ||
| 35 | } | ||
| 36 | } | 23 | } |
| 37 | + if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) { | 24 | |
| 38 | + lr |= R_V7M_EXCRET_FTYPE_MASK; | 25 | + if (vms->mte) { |
| 26 | + error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); | ||
| 27 | + return; | ||
| 39 | + } | 28 | + } |
| 40 | if (!arm_v7m_is_handler_mode(env)) { | 29 | + |
| 41 | lr |= R_V7M_EXCRET_MODE_MASK; | 30 | if (is_nvdimm && !ms->nvdimms_state->is_enabled) { |
| 42 | } | 31 | error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); |
| 32 | return; | ||
| 43 | -- | 33 | -- |
| 44 | 2.20.1 | 34 | 2.20.1 |
| 45 | 35 | ||
| 46 | 36 | diff view generated by jsdifflib |
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: David CARLIER <devnexen@gmail.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Add the CRP as unimplemented thus avoiding bus errors when | 3 | Implement qemu_get_thread_id() for OpenBSD hosts, using |
| 4 | guests access these registers. | 4 | getthrid(). |
| 5 | 5 | ||
| 6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 6 | Signed-off-by: David Carlier <devnexen@gmail.com> |
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 7 | Reviewed-by: Brad Smith <brad@comstyle.com> |
| 8 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | 8 | Message-id: CA+XhMqxD6gQDBaj8tX0CMEj3si7qYKsM8u1km47e_-U7MC37Pg@mail.gmail.com |
| 9 | Message-id: 20191115154734.26449-2-edgar.iglesias@gmail.com | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | [PMM: tidied up commit message] | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | --- | 12 | --- |
| 12 | include/hw/arm/xlnx-versal.h | 3 +++ | 13 | util/oslib-posix.c | 2 ++ |
| 13 | hw/arm/xlnx-versal.c | 2 ++ | 14 | 1 file changed, 2 insertions(+) |
| 14 | 2 files changed, 5 insertions(+) | ||
| 15 | 15 | ||
| 16 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h | 16 | diff --git a/util/oslib-posix.c b/util/oslib-posix.c |
| 17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/include/hw/arm/xlnx-versal.h | 18 | --- a/util/oslib-posix.c |
| 19 | +++ b/include/hw/arm/xlnx-versal.h | 19 | +++ b/util/oslib-posix.c |
| 20 | @@ -XXX,XX +XXX,XX @@ typedef struct Versal { | 20 | @@ -XXX,XX +XXX,XX @@ int qemu_get_thread_id(void) |
| 21 | #define MM_IOU_SCNTRS_SIZE 0x10000 | 21 | return (int)tid; |
| 22 | #define MM_FPD_CRF 0xfd1a0000U | 22 | #elif defined(__NetBSD__) |
| 23 | #define MM_FPD_CRF_SIZE 0x140000 | 23 | return _lwp_self(); |
| 24 | + | 24 | +#elif defined(__OpenBSD__) |
| 25 | +#define MM_PMC_CRP 0xf1260000U | 25 | + return getthrid(); |
| 26 | +#define MM_PMC_CRP_SIZE 0x10000 | 26 | #else |
| 27 | return getpid(); | ||
| 27 | #endif | 28 | #endif |
| 28 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
| 29 | index XXXXXXX..XXXXXXX 100644 | ||
| 30 | --- a/hw/arm/xlnx-versal.c | ||
| 31 | +++ b/hw/arm/xlnx-versal.c | ||
| 32 | @@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s) | ||
| 33 | MM_CRL, MM_CRL_SIZE); | ||
| 34 | versal_unimp_area(s, "crf", &s->mr_ps, | ||
| 35 | MM_FPD_CRF, MM_FPD_CRF_SIZE); | ||
| 36 | + versal_unimp_area(s, "crp", &s->mr_ps, | ||
| 37 | + MM_PMC_CRP, MM_PMC_CRP_SIZE); | ||
| 38 | versal_unimp_area(s, "iou-scntr", &s->mr_ps, | ||
| 39 | MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE); | ||
| 40 | versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps, | ||
| 41 | -- | 29 | -- |
| 42 | 2.20.1 | 30 | 2.20.1 |
| 43 | 31 | ||
| 44 | 32 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | The doc-comments which document the qdev API are split between the | ||
| 2 | header file and the C source files, because as a project we haven't | ||
| 3 | been consistent about where we put them. | ||
| 1 | 4 | ||
| 5 | Move all the doc-comments in qdev.c to the header files, so that | ||
| 6 | users of the APIs don't have to look at the implementation files for | ||
| 7 | this information. | ||
| 8 | |||
| 9 | In the process, unify them into our doc-comment format and expand on | ||
| 10 | them in some cases to clarify expected use cases. | ||
| 11 | |||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 14 | Message-id: 20200711142425.16283-2-peter.maydell@linaro.org | ||
| 15 | --- | ||
| 16 | include/hw/qdev-core.h | 57 ++++++++++++++++++++++++++++++++++++ | ||
| 17 | include/hw/qdev-properties.h | 13 ++++++++ | ||
| 18 | hw/core/qdev.c | 33 --------------------- | ||
| 19 | 3 files changed, 70 insertions(+), 33 deletions(-) | ||
| 20 | |||
| 21 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | ||
| 22 | index XXXXXXX..XXXXXXX 100644 | ||
| 23 | --- a/include/hw/qdev-core.h | ||
| 24 | +++ b/include/hw/qdev-core.h | ||
| 25 | @@ -XXX,XX +XXX,XX @@ compat_props_add(GPtrArray *arr, | ||
| 26 | |||
| 27 | /*** Board API. This should go away once we have a machine config file. ***/ | ||
| 28 | |||
| 29 | +/** | ||
| 30 | + * qdev_new: Create a device on the heap | ||
| 31 | + * @name: device type to create (we assert() that this type exists) | ||
| 32 | + * | ||
| 33 | + * This only allocates the memory and initializes the device state | ||
| 34 | + * structure, ready for the caller to set properties if they wish. | ||
| 35 | + * The device still needs to be realized. | ||
| 36 | + * The returned object has a reference count of 1. | ||
| 37 | + */ | ||
| 38 | DeviceState *qdev_new(const char *name); | ||
| 39 | +/** | ||
| 40 | + * qdev_try_new: Try to create a device on the heap | ||
| 41 | + * @name: device type to create | ||
| 42 | + * | ||
| 43 | + * This is like qdev_new(), except it returns %NULL when type @name | ||
| 44 | + * does not exist, rather than asserting. | ||
| 45 | + */ | ||
| 46 | DeviceState *qdev_try_new(const char *name); | ||
| 47 | +/** | ||
| 48 | + * qdev_realize: Realize @dev. | ||
| 49 | + * @dev: device to realize | ||
| 50 | + * @bus: bus to plug it into (may be NULL) | ||
| 51 | + * @errp: pointer to error object | ||
| 52 | + * | ||
| 53 | + * "Realize" the device, i.e. perform the second phase of device | ||
| 54 | + * initialization. | ||
| 55 | + * @dev must not be plugged into a bus already. | ||
| 56 | + * If @bus, plug @dev into @bus. This takes a reference to @dev. | ||
| 57 | + * If @dev has no QOM parent, make one up, taking another reference. | ||
| 58 | + * On success, return true. | ||
| 59 | + * On failure, store an error through @errp and return false. | ||
| 60 | + * | ||
| 61 | + * If you created @dev using qdev_new(), you probably want to use | ||
| 62 | + * qdev_realize_and_unref() instead. | ||
| 63 | + */ | ||
| 64 | bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp); | ||
| 65 | +/** | ||
| 66 | + * qdev_realize_and_unref: Realize @dev and drop a reference | ||
| 67 | + * @dev: device to realize | ||
| 68 | + * @bus: bus to plug it into (may be NULL) | ||
| 69 | + * @errp: pointer to error object | ||
| 70 | + * | ||
| 71 | + * Realize @dev and drop a reference. | ||
| 72 | + * This is like qdev_realize(), except the caller must hold a | ||
| 73 | + * (private) reference, which is dropped on return regardless of | ||
| 74 | + * success or failure. Intended use:: | ||
| 75 | + * | ||
| 76 | + * dev = qdev_new(); | ||
| 77 | + * [...] | ||
| 78 | + * qdev_realize_and_unref(dev, bus, errp); | ||
| 79 | + * | ||
| 80 | + * Now @dev can go away without further ado. | ||
| 81 | + * | ||
| 82 | + * If you are embedding the device into some other QOM device and | ||
| 83 | + * initialized it via some variant on object_initialize_child() then | ||
| 84 | + * do not use this function, because that family of functions arrange | ||
| 85 | + * for the only reference to the child device to be held by the parent | ||
| 86 | + * via the child<> property, and so the reference-count-drop done here | ||
| 87 | + * would be incorrect. For that use case you want qdev_realize(). | ||
| 88 | + */ | ||
| 89 | bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp); | ||
| 90 | void qdev_unrealize(DeviceState *dev); | ||
| 91 | void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id, | ||
| 92 | diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h | ||
| 93 | index XXXXXXX..XXXXXXX 100644 | ||
| 94 | --- a/include/hw/qdev-properties.h | ||
| 95 | +++ b/include/hw/qdev-properties.h | ||
| 96 | @@ -XXX,XX +XXX,XX @@ void error_set_from_qdev_prop_error(Error **errp, int ret, DeviceState *dev, | ||
| 97 | */ | ||
| 98 | void qdev_property_add_static(DeviceState *dev, Property *prop); | ||
| 99 | |||
| 100 | +/** | ||
| 101 | + * qdev_alias_all_properties: Create aliases on source for all target properties | ||
| 102 | + * @target: Device which has properties to be aliased | ||
| 103 | + * @source: Object to add alias properties to | ||
| 104 | + * | ||
| 105 | + * Add alias properties to the @source object for all qdev properties on | ||
| 106 | + * the @target DeviceState. | ||
| 107 | + * | ||
| 108 | + * This is useful when @target is an internal implementation object | ||
| 109 | + * owned by @source, and you want to expose all the properties of that | ||
| 110 | + * implementation object as properties on the @source object so that users | ||
| 111 | + * of @source can set them. | ||
| 112 | + */ | ||
| 113 | void qdev_alias_all_properties(DeviceState *target, Object *source); | ||
| 114 | |||
| 115 | /** | ||
| 116 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | ||
| 117 | index XXXXXXX..XXXXXXX 100644 | ||
| 118 | --- a/hw/core/qdev.c | ||
| 119 | +++ b/hw/core/qdev.c | ||
| 120 | @@ -XXX,XX +XXX,XX @@ void qdev_set_parent_bus(DeviceState *dev, BusState *bus) | ||
| 121 | } | ||
| 122 | } | ||
| 123 | |||
| 124 | -/* | ||
| 125 | - * Create a device on the heap. | ||
| 126 | - * A type @name must exist. | ||
| 127 | - * This only initializes the device state structure and allows | ||
| 128 | - * properties to be set. The device still needs to be realized. See | ||
| 129 | - * qdev-core.h. | ||
| 130 | - */ | ||
| 131 | DeviceState *qdev_new(const char *name) | ||
| 132 | { | ||
| 133 | if (!object_class_by_name(name)) { | ||
| 134 | @@ -XXX,XX +XXX,XX @@ DeviceState *qdev_new(const char *name) | ||
| 135 | return DEVICE(object_new(name)); | ||
| 136 | } | ||
| 137 | |||
| 138 | -/* | ||
| 139 | - * Try to create a device on the heap. | ||
| 140 | - * This is like qdev_new(), except it returns %NULL when type @name | ||
| 141 | - * does not exist. | ||
| 142 | - */ | ||
| 143 | DeviceState *qdev_try_new(const char *name) | ||
| 144 | { | ||
| 145 | if (!module_object_class_by_name(name)) { | ||
| 146 | @@ -XXX,XX +XXX,XX @@ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev, | ||
| 147 | qdev_unrealize(dev); | ||
| 148 | } | ||
| 149 | |||
| 150 | -/* | ||
| 151 | - * Realize @dev. | ||
| 152 | - * @dev must not be plugged into a bus. | ||
| 153 | - * If @bus, plug @dev into @bus. This takes a reference to @dev. | ||
| 154 | - * If @dev has no QOM parent, make one up, taking another reference. | ||
| 155 | - * On success, return true. | ||
| 156 | - * On failure, store an error through @errp and return false. | ||
| 157 | - */ | ||
| 158 | bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp) | ||
| 159 | { | ||
| 160 | assert(!dev->realized && !dev->parent_bus); | ||
| 161 | @@ -XXX,XX +XXX,XX @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp) | ||
| 162 | return object_property_set_bool(OBJECT(dev), "realized", true, errp); | ||
| 163 | } | ||
| 164 | |||
| 165 | -/* | ||
| 166 | - * Realize @dev and drop a reference. | ||
| 167 | - * This is like qdev_realize(), except the caller must hold a | ||
| 168 | - * (private) reference, which is dropped on return regardless of | ||
| 169 | - * success or failure. Intended use: | ||
| 170 | - * dev = qdev_new(); | ||
| 171 | - * [...] | ||
| 172 | - * qdev_realize_and_unref(dev, bus, errp); | ||
| 173 | - * Now @dev can go away without further ado. | ||
| 174 | - */ | ||
| 175 | bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp) | ||
| 176 | { | ||
| 177 | bool ret; | ||
| 178 | @@ -XXX,XX +XXX,XX @@ static void qdev_class_add_property(DeviceClass *klass, Property *prop) | ||
| 179 | prop->info->description); | ||
| 180 | } | ||
| 181 | |||
| 182 | -/* @qdev_alias_all_properties - Add alias properties to the source object for | ||
| 183 | - * all qdev properties on the target DeviceState. | ||
| 184 | - */ | ||
| 185 | void qdev_alias_all_properties(DeviceState *target, Object *source) | ||
| 186 | { | ||
| 187 | ObjectClass *class; | ||
| 188 | -- | ||
| 189 | 2.20.1 | ||
| 190 | |||
| 191 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Add a doc comment for qdev_unrealize(), to go with the new | ||
| 2 | documentation for the realize part of the qdev lifecycle. | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20200711142425.16283-3-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | include/hw/qdev-core.h | 19 +++++++++++++++++++ | ||
| 9 | 1 file changed, 19 insertions(+) | ||
| 10 | |||
| 11 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | ||
| 12 | index XXXXXXX..XXXXXXX 100644 | ||
| 13 | --- a/include/hw/qdev-core.h | ||
| 14 | +++ b/include/hw/qdev-core.h | ||
| 15 | @@ -XXX,XX +XXX,XX @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp); | ||
| 16 | * would be incorrect. For that use case you want qdev_realize(). | ||
| 17 | */ | ||
| 18 | bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp); | ||
| 19 | +/** | ||
| 20 | + * qdev_unrealize: Unrealize a device | ||
| 21 | + * @dev: device to unrealize | ||
| 22 | + * | ||
| 23 | + * This function will "unrealize" a device, which is the first phase | ||
| 24 | + * of correctly destroying a device that has been realized. It will: | ||
| 25 | + * | ||
| 26 | + * - unrealize any child buses by calling qbus_unrealize() | ||
| 27 | + * (this will recursively unrealize any devices on those buses) | ||
| 28 | + * - call the the unrealize method of @dev | ||
| 29 | + * | ||
| 30 | + * The device can then be freed by causing its reference count to go | ||
| 31 | + * to zero. | ||
| 32 | + * | ||
| 33 | + * Warning: most devices in QEMU do not expect to be unrealized. Only | ||
| 34 | + * devices which are hot-unpluggable should be unrealized (as part of | ||
| 35 | + * the unplugging process); all other devices are expected to last for | ||
| 36 | + * the life of the simulation and should not be unrealized and freed. | ||
| 37 | + */ | ||
| 38 | void qdev_unrealize(DeviceState *dev); | ||
| 39 | void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id, | ||
| 40 | int required_for_version); | ||
| 41 | -- | ||
| 42 | 2.20.1 | ||
| 43 | |||
| 44 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | 1 | Add documentation comments for the various qdev functions | |
| 2 | related to creating and connecting GPIO lines. | ||
| 3 | |||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20200711142425.16283-4-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | include/hw/qdev-core.h | 191 ++++++++++++++++++++++++++++++++++++++++- | ||
| 9 | 1 file changed, 189 insertions(+), 2 deletions(-) | ||
| 10 | |||
| 11 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | ||
| 12 | index XXXXXXX..XXXXXXX 100644 | ||
| 13 | --- a/include/hw/qdev-core.h | ||
| 14 | +++ b/include/hw/qdev-core.h | ||
| 15 | @@ -XXX,XX +XXX,XX @@ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev, | ||
| 16 | void qdev_machine_creation_done(void); | ||
| 17 | bool qdev_machine_modified(void); | ||
| 18 | |||
| 19 | +/** | ||
| 20 | + * qdev_get_gpio_in: Get one of a device's anonymous input GPIO lines | ||
| 21 | + * @dev: Device whose GPIO we want | ||
| 22 | + * @n: Number of the anonymous GPIO line (which must be in range) | ||
| 23 | + * | ||
| 24 | + * Returns the qemu_irq corresponding to an anonymous input GPIO line | ||
| 25 | + * (which the device has set up with qdev_init_gpio_in()). The index | ||
| 26 | + * @n of the GPIO line must be valid (i.e. be at least 0 and less than | ||
| 27 | + * the total number of anonymous input GPIOs the device has); this | ||
| 28 | + * function will assert() if passed an invalid index. | ||
| 29 | + * | ||
| 30 | + * This function is intended to be used by board code or SoC "container" | ||
| 31 | + * device models to wire up the GPIO lines; usually the return value | ||
| 32 | + * will be passed to qdev_connect_gpio_out() or a similar function to | ||
| 33 | + * connect another device's output GPIO line to this input. | ||
| 34 | + * | ||
| 35 | + * For named input GPIO lines, use qdev_get_gpio_in_named(). | ||
| 36 | + */ | ||
| 37 | qemu_irq qdev_get_gpio_in(DeviceState *dev, int n); | ||
| 38 | +/** | ||
| 39 | + * qdev_get_gpio_in_named: Get one of a device's named input GPIO lines | ||
| 40 | + * @dev: Device whose GPIO we want | ||
| 41 | + * @name: Name of the input GPIO array | ||
| 42 | + * @n: Number of the GPIO line in that array (which must be in range) | ||
| 43 | + * | ||
| 44 | + * Returns the qemu_irq corresponding to a named input GPIO line | ||
| 45 | + * (which the device has set up with qdev_init_gpio_in_named()). | ||
| 46 | + * The @name string must correspond to an input GPIO array which exists on | ||
| 47 | + * the device, and the index @n of the GPIO line must be valid (i.e. | ||
| 48 | + * be at least 0 and less than the total number of input GPIOs in that | ||
| 49 | + * array); this function will assert() if passed an invalid name or index. | ||
| 50 | + * | ||
| 51 | + * For anonymous input GPIO lines, use qdev_get_gpio_in(). | ||
| 52 | + */ | ||
| 53 | qemu_irq qdev_get_gpio_in_named(DeviceState *dev, const char *name, int n); | ||
| 54 | |||
| 55 | +/** | ||
| 56 | + * qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines | ||
| 57 | + * @dev: Device whose GPIO to connect | ||
| 58 | + * @n: Number of the anonymous output GPIO line (which must be in range) | ||
| 59 | + * @pin: qemu_irq to connect the output line to | ||
| 60 | + * | ||
| 61 | + * This function connects an anonymous output GPIO line on a device | ||
| 62 | + * up to an arbitrary qemu_irq, so that when the device asserts that | ||
| 63 | + * output GPIO line, the qemu_irq's callback is invoked. | ||
| 64 | + * The index @n of the GPIO line must be valid (i.e. be at least 0 and | ||
| 65 | + * less than the total number of anonymous output GPIOs the device has | ||
| 66 | + * created with qdev_init_gpio_out()); otherwise this function will assert(). | ||
| 67 | + * | ||
| 68 | + * Outbound GPIO lines can be connected to any qemu_irq, but the common | ||
| 69 | + * case is connecting them to another device's inbound GPIO line, using | ||
| 70 | + * the qemu_irq returned by qdev_get_gpio_in() or qdev_get_gpio_in_named(). | ||
| 71 | + * | ||
| 72 | + * It is not valid to try to connect one outbound GPIO to multiple | ||
| 73 | + * qemu_irqs at once, or to connect multiple outbound GPIOs to the | ||
| 74 | + * same qemu_irq. (Warning: there is no assertion or other guard to | ||
| 75 | + * catch this error: the model will just not do the right thing.) | ||
| 76 | + * Instead, for fan-out you can use the TYPE_IRQ_SPLIT device: connect | ||
| 77 | + * a device's outbound GPIO to the splitter's input, and connect each | ||
| 78 | + * of the splitter's outputs to a different device. For fan-in you | ||
| 79 | + * can use the TYPE_OR_IRQ device, which is a model of a logical OR | ||
| 80 | + * gate with multiple inputs and one output. | ||
| 81 | + * | ||
| 82 | + * For named output GPIO lines, use qdev_connect_gpio_out_named(). | ||
| 83 | + */ | ||
| 84 | void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin); | ||
| 85 | +/** | ||
| 86 | + * qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines | ||
| 87 | + * @dev: Device whose GPIO to connect | ||
| 88 | + * @name: Name of the output GPIO array | ||
| 89 | + * @n: Number of the anonymous output GPIO line (which must be in range) | ||
| 90 | + * @pin: qemu_irq to connect the output line to | ||
| 91 | + * | ||
| 92 | + * This function connects an anonymous output GPIO line on a device | ||
| 93 | + * up to an arbitrary qemu_irq, so that when the device asserts that | ||
| 94 | + * output GPIO line, the qemu_irq's callback is invoked. | ||
| 95 | + * The @name string must correspond to an output GPIO array which exists on | ||
| 96 | + * the device, and the index @n of the GPIO line must be valid (i.e. | ||
| 97 | + * be at least 0 and less than the total number of input GPIOs in that | ||
| 98 | + * array); this function will assert() if passed an invalid name or index. | ||
| 99 | + * | ||
| 100 | + * Outbound GPIO lines can be connected to any qemu_irq, but the common | ||
| 101 | + * case is connecting them to another device's inbound GPIO line, using | ||
| 102 | + * the qemu_irq returned by qdev_get_gpio_in() or qdev_get_gpio_in_named(). | ||
| 103 | + * | ||
| 104 | + * It is not valid to try to connect one outbound GPIO to multiple | ||
| 105 | + * qemu_irqs at once, or to connect multiple outbound GPIOs to the | ||
| 106 | + * same qemu_irq; see qdev_connect_gpio_out() for details. | ||
| 107 | + * | ||
| 108 | + * For named output GPIO lines, use qdev_connect_gpio_out_named(). | ||
| 109 | + */ | ||
| 110 | void qdev_connect_gpio_out_named(DeviceState *dev, const char *name, int n, | ||
| 111 | qemu_irq pin); | ||
| 112 | +/** | ||
| 113 | + * qdev_get_gpio_out_connector: Get the qemu_irq connected to an output GPIO | ||
| 114 | + * @dev: Device whose output GPIO we are interested in | ||
| 115 | + * @name: Name of the output GPIO array | ||
| 116 | + * @n: Number of the output GPIO line within that array | ||
| 117 | + * | ||
| 118 | + * Returns whatever qemu_irq is currently connected to the specified | ||
| 119 | + * output GPIO line of @dev. This will be NULL if the output GPIO line | ||
| 120 | + * has never been wired up to the anything. Note that the qemu_irq | ||
| 121 | + * returned does not belong to @dev -- it will be the input GPIO or | ||
| 122 | + * IRQ of whichever device the board code has connected up to @dev's | ||
| 123 | + * output GPIO. | ||
| 124 | + * | ||
| 125 | + * You probably don't need to use this function -- it is used only | ||
| 126 | + * by the platform-bus subsystem. | ||
| 127 | + */ | ||
| 128 | qemu_irq qdev_get_gpio_out_connector(DeviceState *dev, const char *name, int n); | ||
| 129 | +/** | ||
| 130 | + * qdev_intercept_gpio_out: Intercept an existing GPIO connection | ||
| 131 | + * @dev: Device to intercept the outbound GPIO line from | ||
| 132 | + * @icpt: New qemu_irq to connect instead | ||
| 133 | + * @name: Name of the output GPIO array | ||
| 134 | + * @n: Number of the GPIO line in the array | ||
| 135 | + * | ||
| 136 | + * This function is provided only for use by the qtest testing framework | ||
| 137 | + * and is not suitable for use in non-testing parts of QEMU. | ||
| 138 | + * | ||
| 139 | + * This function breaks an existing connection of an outbound GPIO | ||
| 140 | + * line from @dev, and replaces it with the new qemu_irq @icpt, as if | ||
| 141 | + * ``qdev_connect_gpio_out_named(dev, icpt, name, n)`` had been called. | ||
| 142 | + * The previously connected qemu_irq is returned, so it can be restored | ||
| 143 | + * by a second call to qdev_intercept_gpio_out() if desired. | ||
| 144 | + */ | ||
| 145 | qemu_irq qdev_intercept_gpio_out(DeviceState *dev, qemu_irq icpt, | ||
| 146 | const char *name, int n); | ||
| 147 | |||
| 148 | @@ -XXX,XX +XXX,XX @@ BusState *qdev_get_child_bus(DeviceState *dev, const char *name); | ||
| 149 | |||
| 150 | /*** Device API. ***/ | ||
| 151 | |||
| 152 | -/* Register device properties. */ | ||
| 153 | -/* GPIO inputs also double as IRQ sinks. */ | ||
| 154 | +/** | ||
| 155 | + * qdev_init_gpio_in: create an array of anonymous input GPIO lines | ||
| 156 | + * @dev: Device to create input GPIOs for | ||
| 157 | + * @handler: Function to call when GPIO line value is set | ||
| 158 | + * @n: Number of GPIO lines to create | ||
| 159 | + * | ||
| 160 | + * Devices should use functions in the qdev_init_gpio_in* family in | ||
| 161 | + * their instance_init or realize methods to create any input GPIO | ||
| 162 | + * lines they need. There is no functional difference between | ||
| 163 | + * anonymous and named GPIO lines. Stylistically, named GPIOs are | ||
| 164 | + * preferable (easier to understand at callsites) unless a device | ||
| 165 | + * has exactly one uniform kind of GPIO input whose purpose is obvious. | ||
| 166 | + * Note that input GPIO lines can serve as 'sinks' for IRQ lines. | ||
| 167 | + * | ||
| 168 | + * See qdev_get_gpio_in() for how code that uses such a device can get | ||
| 169 | + * hold of an input GPIO line to manipulate it. | ||
| 170 | + */ | ||
| 171 | void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n); | ||
| 172 | +/** | ||
| 173 | + * qdev_init_gpio_out: create an array of anonymous output GPIO lines | ||
| 174 | + * @dev: Device to create output GPIOs for | ||
| 175 | + * @pins: Pointer to qemu_irq or qemu_irq array for the GPIO lines | ||
| 176 | + * @n: Number of GPIO lines to create | ||
| 177 | + * | ||
| 178 | + * Devices should use functions in the qdev_init_gpio_out* family | ||
| 179 | + * in their instance_init or realize methods to create any output | ||
| 180 | + * GPIO lines they need. There is no functional difference between | ||
| 181 | + * anonymous and named GPIO lines. Stylistically, named GPIOs are | ||
| 182 | + * preferable (easier to understand at callsites) unless a device | ||
| 183 | + * has exactly one uniform kind of GPIO output whose purpose is obvious. | ||
| 184 | + * | ||
| 185 | + * The @pins argument should be a pointer to either a "qemu_irq" | ||
| 186 | + * (if @n == 1) or a "qemu_irq []" array (if @n > 1) in the device's | ||
| 187 | + * state structure. The device implementation can then raise and | ||
| 188 | + * lower the GPIO line by calling qemu_set_irq(). (If anything is | ||
| 189 | + * connected to the other end of the GPIO this will cause the handler | ||
| 190 | + * function for that input GPIO to be called.) | ||
| 191 | + * | ||
| 192 | + * See qdev_connect_gpio_out() for how code that uses such a device | ||
| 193 | + * can connect to one of its output GPIO lines. | ||
| 194 | + */ | ||
| 195 | void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n); | ||
| 196 | +/** | ||
| 197 | + * qdev_init_gpio_out: create an array of named output GPIO lines | ||
| 198 | + * @dev: Device to create output GPIOs for | ||
| 199 | + * @pins: Pointer to qemu_irq or qemu_irq array for the GPIO lines | ||
| 200 | + * @name: Name to give this array of GPIO lines | ||
| 201 | + * @n: Number of GPIO lines to create | ||
| 202 | + * | ||
| 203 | + * Like qdev_init_gpio_out(), but creates an array of GPIO output lines | ||
| 204 | + * with a name. Code using the device can then connect these GPIO lines | ||
| 205 | + * using qdev_connect_gpio_out_named(). | ||
| 206 | + */ | ||
| 207 | void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins, | ||
| 208 | const char *name, int n); | ||
| 209 | /** | ||
| 210 | @@ -XXX,XX +XXX,XX @@ static inline void qdev_init_gpio_in_named(DeviceState *dev, | ||
| 211 | qdev_init_gpio_in_named_with_opaque(dev, handler, dev, name, n); | ||
| 212 | } | ||
| 213 | |||
| 214 | +/** | ||
| 215 | + * qdev_pass_gpios: create GPIO lines on container which pass through to device | ||
| 216 | + * @dev: Device which has GPIO lines | ||
| 217 | + * @container: Container device which needs to expose them | ||
| 218 | + * @name: Name of GPIO array to pass through (NULL for the anonymous GPIO array) | ||
| 219 | + * | ||
| 220 | + * In QEMU, complicated devices like SoCs are often modelled with a | ||
| 221 | + * "container" QOM device which itself contains other QOM devices and | ||
| 222 | + * which wires them up appropriately. This function allows the container | ||
| 223 | + * to create GPIO arrays on itself which simply pass through to a GPIO | ||
| 224 | + * array of one of its internal devices. | ||
| 225 | + * | ||
| 226 | + * If @dev has both input and output GPIOs named @name then both will | ||
| 227 | + * be passed through. It is not possible to pass a subset of the array | ||
| 228 | + * with this function. | ||
| 229 | + * | ||
| 230 | + * To users of the container device, the GPIO array created on @container | ||
| 231 | + * behaves exactly like any other. | ||
| 232 | + */ | ||
| 233 | void qdev_pass_gpios(DeviceState *dev, DeviceState *container, | ||
| 234 | const char *name); | ||
| 235 | |||
| 236 | -- | ||
| 237 | 2.20.1 | ||
| 238 | |||
| 239 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | In armsse_realize() we have a loop over [0, info->num_cpus), which | ||
| 2 | indexes into various fixed-size arrays in the ARMSSE struct. This | ||
| 3 | confuses Coverity, which warns that we might overrun those arrays | ||
| 4 | (CID 1430326, 1430337, 1430371, 1430414, 1430430). This can't | ||
| 5 | actually happen, because the info struct is always one of the entries | ||
| 6 | in the armsse_variants[] array and num_cpus is either 1 or 2; we also | ||
| 7 | already assert in armsse_init() that num_cpus is not too large. | ||
| 8 | However, adding an assert to armsse_realize() like the one in | ||
| 9 | armsse_init() should help Coverity figure out that these code paths | ||
| 10 | aren't possible. | ||
| 1 | 11 | ||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 13 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 14 | Message-id: 20200713143716.9881-1-peter.maydell@linaro.org | ||
| 15 | --- | ||
| 16 | hw/arm/armsse.c | 2 ++ | ||
| 17 | 1 file changed, 2 insertions(+) | ||
| 18 | |||
| 19 | diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c | ||
| 20 | index XXXXXXX..XXXXXXX 100644 | ||
| 21 | --- a/hw/arm/armsse.c | ||
| 22 | +++ b/hw/arm/armsse.c | ||
| 23 | @@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp) | ||
| 24 | return; | ||
| 25 | } | ||
| 26 | |||
| 27 | + assert(info->num_cpus <= SSE_MAX_CPUS); | ||
| 28 | + | ||
| 29 | /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ | ||
| 30 | assert(is_power_of_2(info->sram_banks)); | ||
| 31 | addr_width_max = 24 - ctz32(info->sram_banks); | ||
| 32 | -- | ||
| 33 | 2.20.1 | ||
| 34 | |||
| 35 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Add skeletal documentation of the canon-a1100 board. | ||
| 1 | 2 | ||
| 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 6 | Message-id: 20200713175746.5936-2-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | docs/system/arm/digic.rst | 11 +++++++++++ | ||
| 9 | docs/system/target-arm.rst | 1 + | ||
| 10 | MAINTAINERS | 1 + | ||
| 11 | 3 files changed, 13 insertions(+) | ||
| 12 | create mode 100644 docs/system/arm/digic.rst | ||
| 13 | |||
| 14 | diff --git a/docs/system/arm/digic.rst b/docs/system/arm/digic.rst | ||
| 15 | new file mode 100644 | ||
| 16 | index XXXXXXX..XXXXXXX | ||
| 17 | --- /dev/null | ||
| 18 | +++ b/docs/system/arm/digic.rst | ||
| 19 | @@ -XXX,XX +XXX,XX @@ | ||
| 20 | +Canon A1100 (``canon-a1100``) | ||
| 21 | +============================= | ||
| 22 | + | ||
| 23 | +This machine is a model of the Canon PowerShot A1100 camera, which | ||
| 24 | +uses the DIGIC SoC. This model is based on reverse engineering efforts | ||
| 25 | +by the contributors to the `CHDK <http://chdk.wikia.com/>`_ and | ||
| 26 | +`Magic Lantern <http://www.magiclantern.fm/>`_ projects. | ||
| 27 | + | ||
| 28 | +The emulation is incomplete. In particular it can't be used | ||
| 29 | +to run the original camera firmware, but it can successfully run | ||
| 30 | +an experimental version of the `barebox bootloader <http://www.barebox.org/>`_. | ||
| 31 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
| 32 | index XXXXXXX..XXXXXXX 100644 | ||
| 33 | --- a/docs/system/target-arm.rst | ||
| 34 | +++ b/docs/system/target-arm.rst | ||
| 35 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | ||
| 36 | arm/versatile | ||
| 37 | arm/vexpress | ||
| 38 | arm/aspeed | ||
| 39 | + arm/digic | ||
| 40 | arm/musicpal | ||
| 41 | arm/nseries | ||
| 42 | arm/orangepi | ||
| 43 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
| 44 | index XXXXXXX..XXXXXXX 100644 | ||
| 45 | --- a/MAINTAINERS | ||
| 46 | +++ b/MAINTAINERS | ||
| 47 | @@ -XXX,XX +XXX,XX @@ F: include/hw/arm/digic.h | ||
| 48 | F: hw/*/digic* | ||
| 49 | F: include/hw/*/digic* | ||
| 50 | F: tests/acceptance/machine_arm_canona1100.py | ||
| 51 | +F: docs/system/arm/digic.rst | ||
| 52 | |||
| 53 | Goldfish RTC | ||
| 54 | M: Anup Patel <anup.patel@wdc.com> | ||
| 55 | -- | ||
| 56 | 2.20.1 | ||
| 57 | |||
| 58 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Add skeletal documentation of the collie board. | ||
| 1 | 2 | ||
| 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 6 | Message-id: 20200713175746.5936-3-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | docs/system/arm/collie.rst | 16 ++++++++++++++++ | ||
| 9 | docs/system/target-arm.rst | 1 + | ||
| 10 | MAINTAINERS | 1 + | ||
| 11 | 3 files changed, 18 insertions(+) | ||
| 12 | create mode 100644 docs/system/arm/collie.rst | ||
| 13 | |||
| 14 | diff --git a/docs/system/arm/collie.rst b/docs/system/arm/collie.rst | ||
| 15 | new file mode 100644 | ||
| 16 | index XXXXXXX..XXXXXXX | ||
| 17 | --- /dev/null | ||
| 18 | +++ b/docs/system/arm/collie.rst | ||
| 19 | @@ -XXX,XX +XXX,XX @@ | ||
| 20 | +Sharp Zaurus SL-5500 (``collie``) | ||
| 21 | +================================= | ||
| 22 | + | ||
| 23 | +This machine is a model of the Sharp Zaurus SL-5500, which was | ||
| 24 | +a 1990s PDA based on the StrongARM SA1110. | ||
| 25 | + | ||
| 26 | +Implemented devices: | ||
| 27 | + | ||
| 28 | + * NOR flash | ||
| 29 | + * Interrupt controller | ||
| 30 | + * Timer | ||
| 31 | + * RTC | ||
| 32 | + * GPIO | ||
| 33 | + * Peripheral Pin Controller (PPC) | ||
| 34 | + * UARTs | ||
| 35 | + * Synchronous Serial Ports (SSP) | ||
| 36 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
| 37 | index XXXXXXX..XXXXXXX 100644 | ||
| 38 | --- a/docs/system/target-arm.rst | ||
| 39 | +++ b/docs/system/target-arm.rst | ||
| 40 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | ||
| 41 | arm/orangepi | ||
| 42 | arm/palm | ||
| 43 | arm/xscale | ||
| 44 | + arm/collie | ||
| 45 | arm/sx1 | ||
| 46 | arm/stellaris | ||
| 47 | |||
| 48 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
| 49 | index XXXXXXX..XXXXXXX 100644 | ||
| 50 | --- a/MAINTAINERS | ||
| 51 | +++ b/MAINTAINERS | ||
| 52 | @@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org | ||
| 53 | S: Odd Fixes | ||
| 54 | F: hw/arm/collie.c | ||
| 55 | F: hw/arm/strongarm* | ||
| 56 | +F: docs/system/arm/collie.rst | ||
| 57 | |||
| 58 | Stellaris | ||
| 59 | M: Peter Maydell <peter.maydell@linaro.org> | ||
| 60 | -- | ||
| 61 | 2.20.1 | ||
| 62 | |||
| 63 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Add skeletal documentation of the gumstix boards | ||
| 2 | ('connex' and 'verdex'). | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 7 | Message-id: 20200713175746.5936-4-peter.maydell@linaro.org | ||
| 8 | --- | ||
| 9 | docs/system/arm/gumstix.rst | 21 +++++++++++++++++++++ | ||
| 10 | docs/system/target-arm.rst | 1 + | ||
| 11 | MAINTAINERS | 1 + | ||
| 12 | 3 files changed, 23 insertions(+) | ||
| 13 | create mode 100644 docs/system/arm/gumstix.rst | ||
| 14 | |||
| 15 | diff --git a/docs/system/arm/gumstix.rst b/docs/system/arm/gumstix.rst | ||
| 16 | new file mode 100644 | ||
| 17 | index XXXXXXX..XXXXXXX | ||
| 18 | --- /dev/null | ||
| 19 | +++ b/docs/system/arm/gumstix.rst | ||
| 20 | @@ -XXX,XX +XXX,XX @@ | ||
| 21 | +Gumstix Connex and Verdex (``connex``, ``verdex``) | ||
| 22 | +================================================== | ||
| 23 | + | ||
| 24 | +These machines model the Gumstix Connex and Verdex boards. | ||
| 25 | +The Connex has a PXA255 CPU and the Verdex has a PXA270. | ||
| 26 | + | ||
| 27 | +Implemented devices: | ||
| 28 | + | ||
| 29 | + * NOR flash | ||
| 30 | + * SMC91C111 ethernet | ||
| 31 | + * Interrupt controller | ||
| 32 | + * DMA | ||
| 33 | + * Timer | ||
| 34 | + * GPIO | ||
| 35 | + * MMC/SD card | ||
| 36 | + * Fast infra-red communications port (FIR) | ||
| 37 | + * LCD controller | ||
| 38 | + * Synchronous serial ports (SPI) | ||
| 39 | + * PCMCIA interface | ||
| 40 | + * I2C | ||
| 41 | + * I2S | ||
| 42 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
| 43 | index XXXXXXX..XXXXXXX 100644 | ||
| 44 | --- a/docs/system/target-arm.rst | ||
| 45 | +++ b/docs/system/target-arm.rst | ||
| 46 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | ||
| 47 | arm/aspeed | ||
| 48 | arm/digic | ||
| 49 | arm/musicpal | ||
| 50 | + arm/gumstix | ||
| 51 | arm/nseries | ||
| 52 | arm/orangepi | ||
| 53 | arm/palm | ||
| 54 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
| 55 | index XXXXXXX..XXXXXXX 100644 | ||
| 56 | --- a/MAINTAINERS | ||
| 57 | +++ b/MAINTAINERS | ||
| 58 | @@ -XXX,XX +XXX,XX @@ R: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 59 | L: qemu-arm@nongnu.org | ||
| 60 | S: Odd Fixes | ||
| 61 | F: hw/arm/gumstix.c | ||
| 62 | +F: docs/system/arm/gumstix.rst | ||
| 63 | |||
| 64 | i.MX25 PDK | ||
| 65 | M: Peter Maydell <peter.maydell@linaro.org> | ||
| 66 | -- | ||
| 67 | 2.20.1 | ||
| 68 | |||
| 69 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | 1 | Document the arm 'virt' board, which has been undocumented | |
| 2 | for far too long given that it is the main recommended board | ||
| 3 | type for arm guests. | ||
| 4 | |||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 7 | Message-id: 20200713175746.5936-5-peter.maydell@linaro.org | ||
| 8 | --- | ||
| 9 | docs/system/arm/virt.rst | 161 +++++++++++++++++++++++++++++++++++++ | ||
| 10 | docs/system/target-arm.rst | 1 + | ||
| 11 | MAINTAINERS | 1 + | ||
| 12 | 3 files changed, 163 insertions(+) | ||
| 13 | create mode 100644 docs/system/arm/virt.rst | ||
| 14 | |||
| 15 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst | ||
| 16 | new file mode 100644 | ||
| 17 | index XXXXXXX..XXXXXXX | ||
| 18 | --- /dev/null | ||
| 19 | +++ b/docs/system/arm/virt.rst | ||
| 20 | @@ -XXX,XX +XXX,XX @@ | ||
| 21 | +'virt' generic virtual platform (``virt``) | ||
| 22 | +========================================== | ||
| 23 | + | ||
| 24 | +The `virt` board is a platform which does not correspond to any | ||
| 25 | +real hardware; it is designed for use in virtual machines. | ||
| 26 | +It is the recommended board type if you simply want to run | ||
| 27 | +a guest such as Linux and do not care about reproducing the | ||
| 28 | +idiosyncrasies and limitations of a particular bit of real-world | ||
| 29 | +hardware. | ||
| 30 | + | ||
| 31 | +This is a "versioned" board model, so as well as the ``virt`` machine | ||
| 32 | +type itself (which may have improvements, bugfixes and other minor | ||
| 33 | +changes between QEMU versions) a version is provided that guarantees | ||
| 34 | +to have the same behaviour as that of previous QEMU releases, so | ||
| 35 | +that VM migration will work between QEMU versions. For instance the | ||
| 36 | +``virt-5.0`` machine type will behave like the ``virt`` machine from | ||
| 37 | +the QEMU 5.0 release, and migration should work between ``virt-5.0`` | ||
| 38 | +of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration | ||
| 39 | +is not guaranteed to work between different QEMU releases for | ||
| 40 | +the non-versioned ``virt`` machine type. | ||
| 41 | + | ||
| 42 | +Supported devices | ||
| 43 | +""""""""""""""""" | ||
| 44 | + | ||
| 45 | +The virt board supports: | ||
| 46 | + | ||
| 47 | +- PCI/PCIe devices | ||
| 48 | +- Flash memory | ||
| 49 | +- One PL011 UART | ||
| 50 | +- An RTC | ||
| 51 | +- The fw_cfg device that allows a guest to obtain data from QEMU | ||
| 52 | +- A PL061 GPIO controller | ||
| 53 | +- An optional SMMUv3 IOMMU | ||
| 54 | +- hotpluggable DIMMs | ||
| 55 | +- hotpluggable NVDIMMs | ||
| 56 | +- An MSI controller (GICv2M or ITS). GICv2M is selected by default along | ||
| 57 | + with GICv2. ITS is selected by default with GICv3 (>= virt-2.7). Note | ||
| 58 | + that ITS is not modeled in TCG mode. | ||
| 59 | +- 32 virtio-mmio transport devices | ||
| 60 | +- running guests using the KVM accelerator on aarch64 hardware | ||
| 61 | +- large amounts of RAM (at least 255GB, and more if using highmem) | ||
| 62 | +- many CPUs (up to 512 if using a GICv3 and highmem) | ||
| 63 | +- Secure-World-only devices if the CPU has TrustZone: | ||
| 64 | + | ||
| 65 | + - A second PL011 UART | ||
| 66 | + - A secure flash memory | ||
| 67 | + - 16MB of secure RAM | ||
| 68 | + | ||
| 69 | +Supported guest CPU types: | ||
| 70 | + | ||
| 71 | +- ``cortex-a7`` (32-bit) | ||
| 72 | +- ``cortex-a15`` (32-bit; the default) | ||
| 73 | +- ``cortex-a53`` (64-bit) | ||
| 74 | +- ``cortex-a57`` (64-bit) | ||
| 75 | +- ``cortex-a72`` (64-bit) | ||
| 76 | +- ``host`` (with KVM only) | ||
| 77 | +- ``max`` (same as ``host`` for KVM; best possible emulation with TCG) | ||
| 78 | + | ||
| 79 | +Note that the default is ``cortex-a15``, so for an AArch64 guest you must | ||
| 80 | +specify a CPU type. | ||
| 81 | + | ||
| 82 | +Graphics output is available, but unlike the x86 PC machine types | ||
| 83 | +there is no default display device enabled: you should select one from | ||
| 84 | +the Display devices section of "-device help". The recommended option | ||
| 85 | +is ``virtio-gpu-pci``; this is the only one which will work correctly | ||
| 86 | +with KVM. You may also need to ensure your guest kernel is configured | ||
| 87 | +with support for this; see below. | ||
| 88 | + | ||
| 89 | +Machine-specific options | ||
| 90 | +"""""""""""""""""""""""" | ||
| 91 | + | ||
| 92 | +The following machine-specific options are supported: | ||
| 93 | + | ||
| 94 | +secure | ||
| 95 | + Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the | ||
| 96 | + Arm Security Extensions (TrustZone). The default is ``off``. | ||
| 97 | + | ||
| 98 | +virtualization | ||
| 99 | + Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the | ||
| 100 | + Arm Virtualization Extensions. The default is ``off``. | ||
| 101 | + | ||
| 102 | +highmem | ||
| 103 | + Set ``on``/``off`` to enable/disable placing devices and RAM in physical | ||
| 104 | + address space above 32 bits. The default is ``on`` for machine types | ||
| 105 | + later than ``virt-2.12``. | ||
| 106 | + | ||
| 107 | +gic-version | ||
| 108 | + Specify the version of the Generic Interrupt Controller (GIC) to provide. | ||
| 109 | + Valid values are: | ||
| 110 | + | ||
| 111 | + ``2`` | ||
| 112 | + GICv2 | ||
| 113 | + ``3`` | ||
| 114 | + GICv3 | ||
| 115 | + ``host`` | ||
| 116 | + Use the same GIC version the host provides, when using KVM | ||
| 117 | + ``max`` | ||
| 118 | + Use the best GIC version possible (same as host when using KVM; | ||
| 119 | + currently same as ``3``` for TCG, but this may change in future) | ||
| 120 | + | ||
| 121 | +its | ||
| 122 | + Set ``on``/``off`` to enable/disable ITS instantiation. The default is ``on`` | ||
| 123 | + for machine types later than ``virt-2.7``. | ||
| 124 | + | ||
| 125 | +iommu | ||
| 126 | + Set the IOMMU type to create for the guest. Valid values are: | ||
| 127 | + | ||
| 128 | + ``none`` | ||
| 129 | + Don't create an IOMMU (the default) | ||
| 130 | + ``smmuv3`` | ||
| 131 | + Create an SMMUv3 | ||
| 132 | + | ||
| 133 | +ras | ||
| 134 | + Set ``on``/``off`` to enable/disable reporting host memory errors to a guest | ||
| 135 | + using ACPI and guest external abort exceptions. The default is off. | ||
| 136 | + | ||
| 137 | +Linux guest kernel configuration | ||
| 138 | +"""""""""""""""""""""""""""""""" | ||
| 139 | + | ||
| 140 | +The 'defconfig' for Linux arm and arm64 kernels should include the | ||
| 141 | +right device drivers for virtio and the PCI controller; however some older | ||
| 142 | +kernel versions, especially for 32-bit Arm, did not have everything | ||
| 143 | +enabled by default. If you're not seeing PCI devices that you expect, | ||
| 144 | +then check that your guest config has:: | ||
| 145 | + | ||
| 146 | + CONFIG_PCI=y | ||
| 147 | + CONFIG_VIRTIO_PCI=y | ||
| 148 | + CONFIG_PCI_HOST_GENERIC=y | ||
| 149 | + | ||
| 150 | +If you want to use the ``virtio-gpu-pci`` graphics device you will also | ||
| 151 | +need:: | ||
| 152 | + | ||
| 153 | + CONFIG_DRM=y | ||
| 154 | + CONFIG_DRM_VIRTIO_GPU=y | ||
| 155 | + | ||
| 156 | +Hardware configuration information for bare-metal programming | ||
| 157 | +""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" | ||
| 158 | + | ||
| 159 | +The ``virt`` board automatically generates a device tree blob ("dtb") | ||
| 160 | +which it passes to the guest. This provides information about the | ||
| 161 | +addresses, interrupt lines and other configuration of the various devices | ||
| 162 | +in the system. Guest code can rely on and hard-code the following | ||
| 163 | +addresses: | ||
| 164 | + | ||
| 165 | +- Flash memory starts at address 0x0000_0000 | ||
| 166 | + | ||
| 167 | +- RAM starts at 0x4000_0000 | ||
| 168 | + | ||
| 169 | +All other information about device locations may change between | ||
| 170 | +QEMU versions, so guest code must look in the DTB. | ||
| 171 | + | ||
| 172 | +QEMU supports two types of guest image boot for ``virt``, and | ||
| 173 | +the way for the guest code to locate the dtb binary differs: | ||
| 174 | + | ||
| 175 | +- For guests using the Linux kernel boot protocol (this means any | ||
| 176 | + non-ELF file passed to the QEMU ``-kernel`` option) the address | ||
| 177 | + of the DTB is passed in a register (``r2`` for 32-bit guests, | ||
| 178 | + or ``x0`` for 64-bit guests) | ||
| 179 | + | ||
| 180 | +- For guests booting as "bare-metal" (any other kind of boot), | ||
| 181 | + the DTB is at the start of RAM (0x4000_0000) | ||
| 182 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
| 183 | index XXXXXXX..XXXXXXX 100644 | ||
| 184 | --- a/docs/system/target-arm.rst | ||
| 185 | +++ b/docs/system/target-arm.rst | ||
| 186 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | ||
| 187 | arm/collie | ||
| 188 | arm/sx1 | ||
| 189 | arm/stellaris | ||
| 190 | + arm/virt | ||
| 191 | |||
| 192 | Arm CPU features | ||
| 193 | ================ | ||
| 194 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
| 195 | index XXXXXXX..XXXXXXX 100644 | ||
| 196 | --- a/MAINTAINERS | ||
| 197 | +++ b/MAINTAINERS | ||
| 198 | @@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org | ||
| 199 | S: Maintained | ||
| 200 | F: hw/arm/virt* | ||
| 201 | F: include/hw/arm/virt.h | ||
| 202 | +F: docs/system/arm/virt.rst | ||
| 203 | |||
| 204 | Xilinx Zynq | ||
| 205 | M: Edgar E. Iglesias <edgar.iglesias@gmail.com> | ||
| 206 | -- | ||
| 207 | 2.20.1 | ||
| 208 | |||
| 209 | diff view generated by jsdifflib |