[v3] Refine Second-Level Paging Entries reserved fields checking

[PATCH v3 0/2] Refine Second-Level Paging Entries reserved fields checking

yadong.qi@intel.com posted 2 patches 5 years, 11 months ago

Diff against v3

Only 0 patches received!

hw/i386/intel_iommu.c          | 40 +++++++++++++++++++---------------
hw/i386/intel_iommu_internal.h | 18 +++++++++------
2 files changed, 34 insertions(+), 24 deletions(-)

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[PATCH v3 0/2] Refine Second-Level Paging Entries reserved fields checking

Posted by yadong.qi@intel.com 5 years, 11 months ago

From: "Qi, Yadong" <yadong.qi@intel.com>

The following patches are to refine/fix issues of reserved fields checking logic
of Second-Level Paging Entries of VT-d:
- split the resevred fields arrays into two ones,
- large page only effect for L2(2M) and L3(1G), so remove
  checking of L1 and L4 for large page,
- when dt is supported, TM filed should not be Reserved(0).

Changes in v3:
- large page only effect for L2(2M) and L3(1G), so remove
  checking of L1 and L4 for large page

Qi, Yadong (2):
  intel_iommu: refine SL-PEs reserved fields checking
  intel_iommu: TM field should not be in reserved bits

 hw/i386/intel_iommu.c          | 40 +++++++++++++++++++---------------
 hw/i386/intel_iommu_internal.h | 18 +++++++++------
 2 files changed, 34 insertions(+), 24 deletions(-)

-- 
2.17.1