[PULL 0/7] target-arm queue
[PULL v2 00/11] target-arm queue
1
Target-arm queue for rc2 -- just some minor bugfixes.
1
Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx
2
ethernet device failed 'make check' on big-endian hosts.
2
3
3
thanks
4
-- PMM
4
-- PMM
5
5
6
The following changes since commit 6e5d4999c761ffa082f60d72a14e5c953515b417:
6
The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf:
7
7
8
Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-11-19' into staging (2019-11-19 11:29:01 +0000)
8
Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000)
9
9
10
are available in the Git repository at:
10
are available in the Git repository at:
11
11
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191119
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1
13
13
14
for you to fetch changes up to 04c9c81b8fa2ee33f59a26265700fae6fc646062:
14
for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621:
15
15
16
target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY (2019-11-19 13:20:28 +0000)
16
target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000)
17
17
18
----------------------------------------------------------------
18
----------------------------------------------------------------
19
target-arm queue:
19
target-arm queue:
20
* Support EL0 v7m msr/mrs for CONFIG_USER_ONLY
20
* Correctly initialize MDCR_EL2.HPMN
21
* Relax r13 restriction for ldrex/strex for v8.0
21
* versal: Use nr_apu_cpus in favor of hard coding 2
22
* Do not reject rt == rt2 for strexd
22
* accel/tcg: Add URL of clang bug to comment about our workaround
23
* net/cadence_gem: Set PHY autonegotiation restart status
23
* Add support for FEAT_DIT, Data Independent Timing
24
* ssi: xilinx_spips: Skip spi bus update for a few register writes
24
* Remove GPIO from unimplemented NPCM7XX
25
* pl031: Expose RTCICR as proper WC register
25
* Fix SCR RES1 handling
26
* Don't migrate CPUARMState.features
26
27
27
----------------------------------------------------------------
28
----------------------------------------------------------------
28
Alexander Graf (1):
29
Aaron Lindsay (1):
29
pl031: Expose RTCICR as proper WC register
30
target/arm: Don't migrate CPUARMState.features
30
31
31
Linus Ziegert (1):
32
Daniel Müller (1):
32
net/cadence_gem: Set PHY autonegotiation restart status
33
target/arm: Correctly initialize MDCR_EL2.HPMN
33
34
34
Richard Henderson (4):
35
Edgar E. Iglesias (1):
35
target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller
36
hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
36
target/arm: Do not reject rt == rt2 for strexd
37
target/arm: Relax r13 restriction for ldrex/strex for v8.0
38
target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY
39
37
40
Sai Pavan Boddu (1):
38
Hao Wu (1):
41
ssi: xilinx_spips: Skip spi bus update for a few register writes
39
hw/arm: Remove GPIO from unimplemented NPCM7XX
42
40
43
target/arm/cpu.h | 5 +--
41
Mike Nawrocki (1):
44
hw/net/cadence_gem.c | 9 ++--
42
target/arm: Fix SCR RES1 handling
45
hw/rtc/pl031.c | 6 +--
46
hw/ssi/xilinx_spips.c | 22 ++++++++--
47
target/arm/cpu64.c | 15 -------
48
target/arm/helper.c | 9 +++-
49
target/arm/m_helper.c | 114 ++++++++++++++++++++++++++++++-------------------
50
target/arm/translate.c | 14 +++---
51
8 files changed, 113 insertions(+), 81 deletions(-)
52
43
44
Peter Maydell (2):
45
arm: Update infocenter.arm.com URLs
46
accel/tcg: Add URL of clang bug to comment about our workaround
47
48
Rebecca Cran (4):
49
target/arm: Add support for FEAT_DIT, Data Independent Timing
50
target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
51
target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
52
target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU
53
54
include/hw/dma/pl080.h | 7 ++--
55
include/hw/misc/arm_integrator_debug.h | 2 +-
56
include/hw/ssi/pl022.h | 5 ++-
57
target/arm/cpu.h | 17 ++++++++
58
target/arm/internals.h | 6 +++
59
accel/tcg/cpu-exec.c | 25 +++++++++---
60
hw/arm/aspeed_ast2600.c | 2 +-
61
hw/arm/musca.c | 4 +-
62
hw/arm/npcm7xx.c | 8 ----
63
hw/arm/xlnx-versal.c | 4 +-
64
hw/misc/arm_integrator_debug.c | 2 +-
65
hw/timer/arm_timer.c | 7 ++--
66
target/arm/cpu.c | 4 ++
67
target/arm/cpu64.c | 5 +++
68
target/arm/helper-a64.c | 27 +++++++++++--
69
target/arm/helper.c | 71 +++++++++++++++++++++++++++-------
70
target/arm/machine.c | 2 +-
71
target/arm/op_helper.c | 9 +----
72
target/arm/translate-a64.c | 12 ++++++
73
19 files changed, 164 insertions(+), 55 deletions(-)
74
diff view generated by jsdifflib
[PULL 1/7] pl031: Expose RTCICR as proper WC register
Deleted patch
1
From: Alexander Graf <graf@amazon.com>
2
1
3
The current PL031 RTCICR register implementation always clears the
4
IRQ pending status on a register write, regardless of the value the
5
guest writes.
6
7
To justify that behavior, it references the ARM926EJ-S Development
8
Chip Reference Manual (DDI0287B) and indicates that said document
9
states that any write clears the internal IRQ state. It is indeed
10
true that in section 11.1 this document says:
11
12
"The interrupt is cleared by writing any data value to the
13
interrupt clear register RTCICR".
14
15
However, later in section 11.2.2 it contradicts itself by saying:
16
17
"Writing 1 to bit 0 of RTCICR clears the RTCINTR flag."
18
19
The latter statement matches the PL031 TRM (DDI0224C), which says:
20
21
"Writing 1 to bit position 0 clears the corresponding interrupt.
22
Writing 0 has no effect."
23
24
Let's assume that the self-contradictory DDI0287B is in error, and
25
follow the reference manual for the device itself, by making the
26
register write-one-to-clear.
27
28
Reported-by: Hendrik Borghorst <hborghor@amazon.de>
29
Signed-off-by: Alexander Graf <graf@amazon.com>
30
Message-id: 20191104115228.30745-1-graf@amazon.com
31
[PMM: updated commit message to note that DDI0287B says two
32
conflicting things]
33
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
---
36
hw/rtc/pl031.c | 6 +-----
37
1 file changed, 1 insertion(+), 5 deletions(-)
38
39
diff --git a/hw/rtc/pl031.c b/hw/rtc/pl031.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/rtc/pl031.c
42
+++ b/hw/rtc/pl031.c
43
@@ -XXX,XX +XXX,XX @@ static void pl031_write(void * opaque, hwaddr offset,
44
pl031_update(s);
45
break;
46
case RTC_ICR:
47
- /* The PL031 documentation (DDI0224B) states that the interrupt is
48
- cleared when bit 0 of the written value is set. However the
49
- arm926e documentation (DDI0287B) states that the interrupt is
50
- cleared when any value is written. */
51
- s->is = 0;
52
+ s->is &= ~value;
53
pl031_update(s);
54
break;
55
case RTC_CR:
56
--
57
2.20.1
58
59
diff view generated by jsdifflib
[PULL 2/7] target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Coverity reports, in sve_zcr_get_valid_len,
4
5
"Subtract operation overflows on operands
6
arm_cpu_vq_map_next_smaller(cpu, start_vq + 1U) and 1U"
7
8
First, the aarch32 stub version of arm_cpu_vq_map_next_smaller,
9
returning 0, does exactly what Coverity reports. Remove it.
10
11
Second, the aarch64 version of arm_cpu_vq_map_next_smaller has
12
a set of asserts, but they don't cover the case in question.
13
Further, there is a fair amount of extra arithmetic needed to
14
convert from the 0-based zcr register, to the 1-base vq form,
15
to the 0-based bitmap, and back again. This can be simplified
16
by leaving the value in the 0-based form.
17
18
Finally, use test_bit to simplify the common case, where the
19
length in the zcr registers is in fact a supported length.
20
21
Reported-by: Coverity (CID 1407217)
22
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
23
Reviewed-by: Andrew Jones <drjones@redhat.com>
24
Message-id: 20191118091414.19440-1-richard.henderson@linaro.org
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
---
27
target/arm/cpu.h | 3 ---
28
target/arm/cpu64.c | 15 ---------------
29
target/arm/helper.c | 9 +++++++--
30
3 files changed, 7 insertions(+), 20 deletions(-)
31
32
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/cpu.h
35
+++ b/target/arm/cpu.h
36
@@ -XXX,XX +XXX,XX @@ typedef struct {
37
#ifdef TARGET_AARCH64
38
# define ARM_MAX_VQ 16
39
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
40
-uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq);
41
#else
42
# define ARM_MAX_VQ 1
43
static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
44
-static inline uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
45
-{ return 0; }
46
#endif
47
48
typedef struct ARMVectorReg {
49
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
50
index XXXXXXX..XXXXXXX 100644
51
--- a/target/arm/cpu64.c
52
+++ b/target/arm/cpu64.c
53
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
54
cpu->sve_max_vq = max_vq;
55
}
56
57
-uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
58
-{
59
- uint32_t bitnum;
60
-
61
- /*
62
- * We allow vq == ARM_MAX_VQ + 1 to be input because the caller may want
63
- * to find the maximum vq enabled, which may be ARM_MAX_VQ, but this
64
- * function always returns the next smaller than the input.
65
- */
66
- assert(vq && vq <= ARM_MAX_VQ + 1);
67
-
68
- bitnum = find_last_bit(cpu->sve_vq_map, vq - 1);
69
- return bitnum == vq - 1 ? 0 : bitnum + 1;
70
-}
71
-
72
static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
73
void *opaque, Error **errp)
74
{
75
diff --git a/target/arm/helper.c b/target/arm/helper.c
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/arm/helper.c
78
+++ b/target/arm/helper.c
79
@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
80
81
static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
82
{
83
- uint32_t start_vq = (start_len & 0xf) + 1;
84
+ uint32_t end_len;
85
86
- return arm_cpu_vq_map_next_smaller(cpu, start_vq + 1) - 1;
87
+ end_len = start_len &= 0xf;
88
+ if (!test_bit(start_len, cpu->sve_vq_map)) {
89
+ end_len = find_last_bit(cpu->sve_vq_map, start_len);
90
+ assert(end_len < start_len);
91
+ }
92
+ return end_len;
93
}
94
95
/*
96
--
97
2.20.1
98
99
diff view generated by jsdifflib
[PULL 3/7] ssi: xilinx_spips: Skip spi bus update for a few register writes
Deleted patch
1
From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
2
1
3
A few configuration register writes need not update the spi bus state, so just
4
return after the register write.
5
6
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
9
Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
10
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
11
Message-id: 1573830705-14579-1-git-send-email-sai.pavan.boddu@xilinx.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/ssi/xilinx_spips.c | 22 ++++++++++++++++++----
15
1 file changed, 18 insertions(+), 4 deletions(-)
16
17
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/ssi/xilinx_spips.c
20
+++ b/hw/ssi/xilinx_spips.c
21
@@ -XXX,XX +XXX,XX @@
22
#define R_GPIO (0x30 / 4)
23
#define R_LPBK_DLY_ADJ (0x38 / 4)
24
#define R_LPBK_DLY_ADJ_RESET (0x33)
25
+#define R_IOU_TAPDLY_BYPASS (0x3C / 4)
26
#define R_TXD1 (0x80 / 4)
27
#define R_TXD2 (0x84 / 4)
28
#define R_TXD3 (0x88 / 4)
29
@@ -XXX,XX +XXX,XX @@
30
#define R_LQSPI_STS (0xA4 / 4)
31
#define LQSPI_STS_WR_RECVD (1 << 1)
32
33
+#define R_DUMMY_CYCLE_EN (0xC8 / 4)
34
+#define R_ECO (0xF8 / 4)
35
#define R_MOD_ID (0xFC / 4)
36
37
#define R_GQSPI_SELECT (0x144 / 4)
38
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_write(void *opaque, hwaddr addr,
39
{
40
int mask = ~0;
41
XilinxSPIPS *s = opaque;
42
+ bool try_flush = true;
43
44
DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
45
addr >>= 2;
46
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_write(void *opaque, hwaddr addr,
47
tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3,
48
s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
49
goto no_reg_update;
50
+ /* Skip SPI bus update for below registers writes */
51
+ case R_GPIO:
52
+ case R_LPBK_DLY_ADJ:
53
+ case R_IOU_TAPDLY_BYPASS:
54
+ case R_DUMMY_CYCLE_EN:
55
+ case R_ECO:
56
+ try_flush = false;
57
+ break;
58
}
59
s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
60
no_reg_update:
61
- xilinx_spips_update_cs_lines(s);
62
- xilinx_spips_check_flush(s);
63
- xilinx_spips_update_cs_lines(s);
64
- xilinx_spips_update_ixr(s);
65
+ if (try_flush) {
66
+ xilinx_spips_update_cs_lines(s);
67
+ xilinx_spips_check_flush(s);
68
+ xilinx_spips_update_cs_lines(s);
69
+ xilinx_spips_update_ixr(s);
70
+ }
71
}
72
73
static const MemoryRegionOps spips_ops = {
74
--
75
2.20.1
76
77
diff view generated by jsdifflib
[PULL 4/7] net/cadence_gem: Set PHY autonegotiation restart status
Deleted patch
1
From: Linus Ziegert <linus.ziegert+qemu@holoplot.com>
2
1
3
The Linux kernel PHY driver sets AN_RESTART in the BMCR of the
4
PHY when autonegotiation is started.
5
Recently the kernel started to read back the PHY's AN_RESTART
6
bit and now checks whether the autonegotiation is complete and
7
the bit was cleared [1]. Otherwise the link status is down.
8
9
The emulated PHY needs to clear AN_RESTART immediately to inform
10
the kernel driver about the completion of autonegotiation phase.
11
12
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c36757eb9dee
13
14
Signed-off-by: Linus Ziegert <linus.ziegert+qemu@holoplot.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-id: 20191104181604.21943-1-linus.ziegert+qemu@holoplot.com
17
Cc: qemu-stable@nongnu.org
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
hw/net/cadence_gem.c | 9 +++++----
21
1 file changed, 5 insertions(+), 4 deletions(-)
22
23
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/net/cadence_gem.c
26
+++ b/hw/net/cadence_gem.c
27
@@ -XXX,XX +XXX,XX @@
28
#define PHY_REG_EXT_PHYSPCFC_ST 27
29
#define PHY_REG_CABLE_DIAG 28
30
31
-#define PHY_REG_CONTROL_RST 0x8000
32
-#define PHY_REG_CONTROL_LOOP 0x4000
33
-#define PHY_REG_CONTROL_ANEG 0x1000
34
+#define PHY_REG_CONTROL_RST 0x8000
35
+#define PHY_REG_CONTROL_LOOP 0x4000
36
+#define PHY_REG_CONTROL_ANEG 0x1000
37
+#define PHY_REG_CONTROL_ANRESTART 0x0200
38
39
#define PHY_REG_STATUS_LINK 0x0004
40
#define PHY_REG_STATUS_ANEGCMPL 0x0020
41
@@ -XXX,XX +XXX,XX @@ static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val)
42
}
43
if (val & PHY_REG_CONTROL_ANEG) {
44
/* Complete autonegotiation immediately */
45
- val &= ~PHY_REG_CONTROL_ANEG;
46
+ val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART);
47
s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL;
48
}
49
if (val & PHY_REG_CONTROL_LOOP) {
50
--
51
2.20.1
52
53
diff view generated by jsdifflib
[PULL 5/7] target/arm: Do not reject rt == rt2 for strexd
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
There was too much cut and paste between ldrexd and strexd,
4
as ldrexd does prohibit two output registers the same.
5
6
Fixes: af288228995
7
Reported-by: Michael Goffioul <michael.goffioul@gmail.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20191117090621.32425-2-richard.henderson@linaro.org
10
Reviewed-by: Robert Foley <robert.foley@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/translate.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/target/arm/translate.c b/target/arm/translate.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate.c
20
+++ b/target/arm/translate.c
21
@@ -XXX,XX +XXX,XX @@ static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel)
22
|| (s->thumb && (a->rd == 13 || a->rt == 13))
23
|| (mop == MO_64
24
&& (a->rt2 == 15
25
- || a->rd == a->rt2 || a->rt == a->rt2
26
+ || a->rd == a->rt2
27
|| (s->thumb && a->rt2 == 13)))) {
28
unallocated_encoding(s);
29
return true;
30
--
31
2.20.1
32
33
diff view generated by jsdifflib
[PULL 6/7] target/arm: Relax r13 restriction for ldrex/strex for v8.0
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Armv8-A removes UNPREDICTABLE for R13 for these cases.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20191117090621.32425-3-richard.henderson@linaro.org
7
[PMM: changed ENABLE_ARCH_8 checks to check a new bool 'v8a',
8
since these cases are still UNPREDICTABLE for v8M]
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate.c | 12 ++++++++----
13
1 file changed, 8 insertions(+), 4 deletions(-)
14
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.c
18
+++ b/target/arm/translate.c
19
@@ -XXX,XX +XXX,XX @@ static bool trans_SWPB(DisasContext *s, arg_SWP *a)
20
static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel)
21
{
22
TCGv_i32 addr;
23
+ /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */
24
+ bool v8a = ENABLE_ARCH_8 && !arm_dc_feature(s, ARM_FEATURE_M);
25
26
/* We UNDEF for these UNPREDICTABLE cases. */
27
if (a->rd == 15 || a->rn == 15 || a->rt == 15
28
|| a->rd == a->rn || a->rd == a->rt
29
- || (s->thumb && (a->rd == 13 || a->rt == 13))
30
+ || (!v8a && s->thumb && (a->rd == 13 || a->rt == 13))
31
|| (mop == MO_64
32
&& (a->rt2 == 15
33
|| a->rd == a->rt2
34
- || (s->thumb && a->rt2 == 13)))) {
35
+ || (!v8a && s->thumb && a->rt2 == 13)))) {
36
unallocated_encoding(s);
37
return true;
38
}
39
@@ -XXX,XX +XXX,XX @@ static bool trans_STLH(DisasContext *s, arg_STL *a)
40
static bool op_ldrex(DisasContext *s, arg_LDREX *a, MemOp mop, bool acq)
41
{
42
TCGv_i32 addr;
43
+ /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */
44
+ bool v8a = ENABLE_ARCH_8 && !arm_dc_feature(s, ARM_FEATURE_M);
45
46
/* We UNDEF for these UNPREDICTABLE cases. */
47
if (a->rn == 15 || a->rt == 15
48
- || (s->thumb && a->rt == 13)
49
+ || (!v8a && s->thumb && a->rt == 13)
50
|| (mop == MO_64
51
&& (a->rt2 == 15 || a->rt == a->rt2
52
- || (s->thumb && a->rt2 == 13)))) {
53
+ || (!v8a && s->thumb && a->rt2 == 13)))) {
54
unallocated_encoding(s);
55
return true;
56
}
57
--
58
2.20.1
59
60
diff view generated by jsdifflib
[PULL 7/7] target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Simply moving the non-stub helper_v7m_mrs/msr outside of
4
!CONFIG_USER_ONLY is not an option, because of all of the
5
other system-mode helpers that are called.
6
7
But we can split out a few subroutines to handle the few
8
EL0 accessible registers without duplicating code.
9
10
Reported-by: Christophe Lyon <christophe.lyon@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20191118194916.3670-1-richard.henderson@linaro.org
13
[PMM: deleted now-redundant comment; added a default case
14
to switch in v7m_msr helper]
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
target/arm/cpu.h | 2 +
19
target/arm/m_helper.c | 114 ++++++++++++++++++++++++++----------------
20
2 files changed, 73 insertions(+), 43 deletions(-)
21
22
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/cpu.h
25
+++ b/target/arm/cpu.h
26
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
27
if (mask & XPSR_GE) {
28
env->GE = (val & XPSR_GE) >> 16;
29
}
30
+#ifndef CONFIG_USER_ONLY
31
if (mask & XPSR_T) {
32
env->thumb = ((val & XPSR_T) != 0);
33
}
34
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
35
/* Note that this only happens on exception exit */
36
write_v7m_exception(env, val & XPSR_EXCP);
37
}
38
+#endif
39
}
40
41
#define HCR_VM (1ULL << 0)
42
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/m_helper.c
45
+++ b/target/arm/m_helper.c
46
@@ -XXX,XX +XXX,XX @@
47
#include "exec/cpu_ldst.h"
48
#endif
49
50
+static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask,
51
+ uint32_t reg, uint32_t val)
52
+{
53
+ /* Only APSR is actually writable */
54
+ if (!(reg & 4)) {
55
+ uint32_t apsrmask = 0;
56
+
57
+ if (mask & 8) {
58
+ apsrmask |= XPSR_NZCV | XPSR_Q;
59
+ }
60
+ if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
61
+ apsrmask |= XPSR_GE;
62
+ }
63
+ xpsr_write(env, val, apsrmask);
64
+ }
65
+}
66
+
67
+static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el)
68
+{
69
+ uint32_t mask = 0;
70
+
71
+ if ((reg & 1) && el) {
72
+ mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */
73
+ }
74
+ if (!(reg & 4)) {
75
+ mask |= XPSR_NZCV | XPSR_Q; /* APSR */
76
+ if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
77
+ mask |= XPSR_GE;
78
+ }
79
+ }
80
+ /* EPSR reads as zero */
81
+ return xpsr_read(env) & mask;
82
+}
83
+
84
+static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure)
85
+{
86
+ uint32_t value = env->v7m.control[secure];
87
+
88
+ if (!secure) {
89
+ /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank */
90
+ value |= env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK;
91
+ }
92
+ return value;
93
+}
94
+
95
#ifdef CONFIG_USER_ONLY
96
97
-/* These should probably raise undefined insn exceptions. */
98
-void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
99
+void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
100
{
101
- ARMCPU *cpu = env_archcpu(env);
102
+ uint32_t mask = extract32(maskreg, 8, 4);
103
+ uint32_t reg = extract32(maskreg, 0, 8);
104
105
- cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
106
+ switch (reg) {
107
+ case 0 ... 7: /* xPSR sub-fields */
108
+ v7m_msr_xpsr(env, mask, reg, val);
109
+ break;
110
+ case 20: /* CONTROL */
111
+ /* There are no sub-fields that are actually writable from EL0. */
112
+ break;
113
+ default:
114
+ /* Unprivileged writes to other registers are ignored */
115
+ break;
116
+ }
117
}
118
119
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
120
{
121
- ARMCPU *cpu = env_archcpu(env);
122
-
123
- cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
124
- return 0;
125
+ switch (reg) {
126
+ case 0 ... 7: /* xPSR sub-fields */
127
+ return v7m_mrs_xpsr(env, reg, 0);
128
+ case 20: /* CONTROL */
129
+ return v7m_mrs_control(env, 0);
130
+ default:
131
+ /* Unprivileged reads others as zero. */
132
+ return 0;
133
+ }
134
}
135
136
void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
137
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
138
139
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
140
{
141
- uint32_t mask;
142
unsigned el = arm_current_el(env);
143
144
/* First handle registers which unprivileged can read */
145
-
146
switch (reg) {
147
case 0 ... 7: /* xPSR sub-fields */
148
- mask = 0;
149
- if ((reg & 1) && el) {
150
- mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */
151
- }
152
- if (!(reg & 4)) {
153
- mask |= XPSR_NZCV | XPSR_Q; /* APSR */
154
- if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
155
- mask |= XPSR_GE;
156
- }
157
- }
158
- /* EPSR reads as zero */
159
- return xpsr_read(env) & mask;
160
- break;
161
+ return v7m_mrs_xpsr(env, reg, el);
162
case 20: /* CONTROL */
163
- {
164
- uint32_t value = env->v7m.control[env->v7m.secure];
165
- if (!env->v7m.secure) {
166
- /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank */
167
- value |= env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK;
168
- }
169
- return value;
170
- }
171
+ return v7m_mrs_control(env, env->v7m.secure);
172
case 0x94: /* CONTROL_NS */
173
/*
174
* We have to handle this here because unprivileged Secure code
175
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
176
177
switch (reg) {
178
case 0 ... 7: /* xPSR sub-fields */
179
- /* only APSR is actually writable */
180
- if (!(reg & 4)) {
181
- uint32_t apsrmask = 0;
182
-
183
- if (mask & 8) {
184
- apsrmask |= XPSR_NZCV | XPSR_Q;
185
- }
186
- if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
187
- apsrmask |= XPSR_GE;
188
- }
189
- xpsr_write(env, val, apsrmask);
190
- }
191
+ v7m_msr_xpsr(env, mask, reg, val);
192
break;
193
case 8: /* MSP */
194
if (v7m_using_psp(env)) {
195
--
196
2.20.1
197
198
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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