1 | Target-arm queue for rc2 -- just some minor bugfixes. | 1 | Patches for rc1: nothing major, just some minor bugfixes and |
---|---|---|---|
2 | code cleanups. | ||
2 | 3 | ||
3 | thanks | ||
4 | -- PMM | 4 | -- PMM |
5 | 5 | ||
6 | The following changes since commit 6e5d4999c761ffa082f60d72a14e5c953515b417: | 6 | The following changes since commit f7e1914adad8885a5d4c70239ab90d901ed97e9f: |
7 | 7 | ||
8 | Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-11-19' into staging (2019-11-19 11:29:01 +0000) | 8 | Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging (2020-11-10 09:24:56 +0000) |
9 | 9 | ||
10 | are available in the Git repository at: | 10 | are available in the Git repository at: |
11 | 11 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191119 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201110 |
13 | 13 | ||
14 | for you to fetch changes up to 04c9c81b8fa2ee33f59a26265700fae6fc646062: | 14 | for you to fetch changes up to b6c56c8a9a4064ea783f352f43c5df6231a110fa: |
15 | 15 | ||
16 | target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY (2019-11-19 13:20:28 +0000) | 16 | target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check (2020-11-10 11:03:48 +0000) |
17 | 17 | ||
18 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
19 | target-arm queue: | 19 | target-arm queue: |
20 | * Support EL0 v7m msr/mrs for CONFIG_USER_ONLY | 20 | * hw/arm/Kconfig: ARM_V7M depends on PTIMER |
21 | * Relax r13 restriction for ldrex/strex for v8.0 | 21 | * Minor coding style fixes |
22 | * Do not reject rt == rt2 for strexd | 22 | * docs: add some notes on the sbsa-ref machine |
23 | * net/cadence_gem: Set PHY autonegotiation restart status | 23 | * hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals |
24 | * ssi: xilinx_spips: Skip spi bus update for a few register writes | 24 | * target/arm: Fix neon VTBL/VTBX for len > 1 |
25 | * pl031: Expose RTCICR as proper WC register | 25 | * hw/arm/armsse: Correct expansion MPC interrupt lines |
26 | * hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ | ||
27 | * hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup() | ||
28 | * hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input | ||
29 | * hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary | ||
30 | * hw/arm/nseries: Check return value from load_image_targphys() | ||
31 | * tests/qtest/npcm7xx_rng-test: count runs properly | ||
32 | * target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check | ||
26 | 33 | ||
27 | ---------------------------------------------------------------- | 34 | ---------------------------------------------------------------- |
28 | Alexander Graf (1): | 35 | Alex Bennée (1): |
29 | pl031: Expose RTCICR as proper WC register | 36 | docs: add some notes on the sbsa-ref machine |
30 | 37 | ||
31 | Linus Ziegert (1): | 38 | AlexChen (1): |
32 | net/cadence_gem: Set PHY autonegotiation restart status | 39 | ssi: Fix bad printf format specifiers |
33 | 40 | ||
34 | Richard Henderson (4): | 41 | Andrew Jones (1): |
35 | target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller | 42 | hw/arm/Kconfig: ARM_V7M depends on PTIMER |
36 | target/arm: Do not reject rt == rt2 for strexd | ||
37 | target/arm: Relax r13 restriction for ldrex/strex for v8.0 | ||
38 | target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY | ||
39 | 43 | ||
40 | Sai Pavan Boddu (1): | 44 | Havard Skinnemoen (1): |
41 | ssi: xilinx_spips: Skip spi bus update for a few register writes | 45 | tests/qtest/npcm7xx_rng-test: count runs properly |
42 | 46 | ||
43 | target/arm/cpu.h | 5 +-- | 47 | Peter Maydell (2): |
44 | hw/net/cadence_gem.c | 9 ++-- | 48 | hw/arm/nseries: Check return value from load_image_targphys() |
45 | hw/rtc/pl031.c | 6 +-- | 49 | target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check |
46 | hw/ssi/xilinx_spips.c | 22 ++++++++-- | ||
47 | target/arm/cpu64.c | 15 ------- | ||
48 | target/arm/helper.c | 9 +++- | ||
49 | target/arm/m_helper.c | 114 ++++++++++++++++++++++++++++++------------------- | ||
50 | target/arm/translate.c | 14 +++--- | ||
51 | 8 files changed, 113 insertions(+), 81 deletions(-) | ||
52 | 50 | ||
51 | Philippe Mathieu-Daudé (6): | ||
52 | hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals | ||
53 | hw/arm/armsse: Correct expansion MPC interrupt lines | ||
54 | hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ | ||
55 | hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup() | ||
56 | hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input | ||
57 | hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary | ||
58 | |||
59 | Richard Henderson (1): | ||
60 | target/arm: Fix neon VTBL/VTBX for len > 1 | ||
61 | |||
62 | Xinhao Zhang (3): | ||
63 | target/arm: add spaces around operator | ||
64 | target/arm: Don't use '#' flag of printf format | ||
65 | target/arm: add space before the open parenthesis '(' | ||
66 | |||
67 | docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++ | ||
68 | docs/system/target-arm.rst | 1 + | ||
69 | include/hw/misc/stm32f2xx_syscfg.h | 2 -- | ||
70 | target/arm/helper.h | 2 +- | ||
71 | hw/arm/armsse.c | 3 +- | ||
72 | hw/arm/musicpal.c | 40 +++++++++++++++++---------- | ||
73 | hw/arm/nseries.c | 26 ++++++++---------- | ||
74 | hw/arm/stm32f205_soc.c | 1 - | ||
75 | hw/misc/stm32f2xx_syscfg.c | 2 -- | ||
76 | hw/ssi/imx_spi.c | 2 +- | ||
77 | hw/ssi/xilinx_spi.c | 2 +- | ||
78 | target/arm/arch_dump.c | 8 +++--- | ||
79 | target/arm/arm-semi.c | 8 +++--- | ||
80 | target/arm/helper.c | 2 +- | ||
81 | target/arm/op_helper.c | 23 +++++++++------- | ||
82 | target/arm/translate-a64.c | 4 +-- | ||
83 | target/arm/translate.c | 2 +- | ||
84 | tests/qtest/npcm7xx_rng-test.c | 2 +- | ||
85 | hw/arm/Kconfig | 3 +- | ||
86 | target/arm/translate-neon.c.inc | 56 ++++++++++++++------------------------ | ||
87 | 20 files changed, 123 insertions(+), 98 deletions(-) | ||
88 | create mode 100644 docs/system/arm/sbsa.rst | ||
89 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Andrew Jones <drjones@redhat.com> | ||
1 | 2 | ||
3 | commit 32bd322a0134 ("hw/timer/armv7m_systick: Rewrite to use ptimers") | ||
4 | changed armv7m_systick to build on ptimers. Make sure we have ptimers | ||
5 | in the build when building armv7m_systick. | ||
6 | |||
7 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
9 | Message-id: 20201104103343.30392-1-drjones@redhat.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | hw/arm/Kconfig | 1 + | ||
13 | 1 file changed, 1 insertion(+) | ||
14 | |||
15 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/hw/arm/Kconfig | ||
18 | +++ b/hw/arm/Kconfig | ||
19 | @@ -XXX,XX +XXX,XX @@ config ZYNQ | ||
20 | |||
21 | config ARM_V7M | ||
22 | bool | ||
23 | + select PTIMER | ||
24 | |||
25 | config ALLWINNER_A10 | ||
26 | bool | ||
27 | -- | ||
28 | 2.20.1 | ||
29 | |||
30 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: AlexChen <alex.chen@huawei.com> | ||
1 | 2 | ||
3 | We should use printf format specifier "%u" instead of "%d" for | ||
4 | argument of type "unsigned int". | ||
5 | |||
6 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
7 | Signed-off-by: Alex Chen <alex.chen@huawei.com> | ||
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
9 | Message-id: 5FA280F5.8060902@huawei.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | hw/ssi/imx_spi.c | 2 +- | ||
13 | hw/ssi/xilinx_spi.c | 2 +- | ||
14 | 2 files changed, 2 insertions(+), 2 deletions(-) | ||
15 | |||
16 | diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/hw/ssi/imx_spi.c | ||
19 | +++ b/hw/ssi/imx_spi.c | ||
20 | @@ -XXX,XX +XXX,XX @@ static const char *imx_spi_reg_name(uint32_t reg) | ||
21 | case ECSPI_MSGDATA: | ||
22 | return "ECSPI_MSGDATA"; | ||
23 | default: | ||
24 | - sprintf(unknown, "%d ?", reg); | ||
25 | + sprintf(unknown, "%u ?", reg); | ||
26 | return unknown; | ||
27 | } | ||
28 | } | ||
29 | diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/ssi/xilinx_spi.c | ||
32 | +++ b/hw/ssi/xilinx_spi.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void xlx_spi_update_irq(XilinxSPI *s) | ||
34 | irq chain unless things really changed. */ | ||
35 | if (pending != s->irqline) { | ||
36 | s->irqline = pending; | ||
37 | - DB_PRINT("irq_change of state %d ISR:%x IER:%X\n", | ||
38 | + DB_PRINT("irq_change of state %u ISR:%x IER:%X\n", | ||
39 | pending, s->regs[R_IPISR], s->regs[R_IPIER]); | ||
40 | qemu_set_irq(s->irq, pending); | ||
41 | } | ||
42 | -- | ||
43 | 2.20.1 | ||
44 | |||
45 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Xinhao Zhang <zhangxinhao1@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | Coverity reports, in sve_zcr_get_valid_len, | 3 | Fix code style. Operator needs spaces both sides. |
4 | 4 | ||
5 | "Subtract operation overflows on operands | 5 | Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com> |
6 | arm_cpu_vq_map_next_smaller(cpu, start_vq + 1U) and 1U" | 6 | Signed-off-by: Kai Deng <dengkai1@huawei.com> |
7 | 7 | Message-id: 20201103114529.638233-1-zhangxinhao1@huawei.com | |
8 | First, the aarch32 stub version of arm_cpu_vq_map_next_smaller, | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | returning 0, does exactly what Coverity reports. Remove it. | ||
10 | |||
11 | Second, the aarch64 version of arm_cpu_vq_map_next_smaller has | ||
12 | a set of asserts, but they don't cover the case in question. | ||
13 | Further, there is a fair amount of extra arithmetic needed to | ||
14 | convert from the 0-based zcr register, to the 1-base vq form, | ||
15 | to the 0-based bitmap, and back again. This can be simplified | ||
16 | by leaving the value in the 0-based form. | ||
17 | |||
18 | Finally, use test_bit to simplify the common case, where the | ||
19 | length in the zcr registers is in fact a supported length. | ||
20 | |||
21 | Reported-by: Coverity (CID 1407217) | ||
22 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
23 | Reviewed-by: Andrew Jones <drjones@redhat.com> | ||
24 | Message-id: 20191118091414.19440-1-richard.henderson@linaro.org | ||
25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
26 | --- | 10 | --- |
27 | target/arm/cpu.h | 3 --- | 11 | target/arm/arch_dump.c | 8 ++++---- |
28 | target/arm/cpu64.c | 15 --------------- | 12 | target/arm/arm-semi.c | 8 ++++---- |
29 | target/arm/helper.c | 9 +++++++-- | 13 | target/arm/helper.c | 2 +- |
30 | 3 files changed, 7 insertions(+), 20 deletions(-) | 14 | 3 files changed, 9 insertions(+), 9 deletions(-) |
31 | 15 | ||
32 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 16 | diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c |
33 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
34 | --- a/target/arm/cpu.h | 18 | --- a/target/arm/arch_dump.c |
35 | +++ b/target/arm/cpu.h | 19 | +++ b/target/arm/arch_dump.c |
36 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 20 | @@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f, |
37 | #ifdef TARGET_AARCH64 | 21 | |
38 | # define ARM_MAX_VQ 16 | 22 | for (i = 0; i < 32; ++i) { |
39 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); | 23 | uint64_t *q = aa64_vfp_qreg(env, i); |
40 | -uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq); | 24 | - note.vfp.vregs[2*i + 0] = cpu_to_dump64(s, q[0]); |
41 | #else | 25 | - note.vfp.vregs[2*i + 1] = cpu_to_dump64(s, q[1]); |
42 | # define ARM_MAX_VQ 1 | 26 | + note.vfp.vregs[2 * i + 0] = cpu_to_dump64(s, q[0]); |
43 | static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } | 27 | + note.vfp.vregs[2 * i + 1] = cpu_to_dump64(s, q[1]); |
44 | -static inline uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq) | 28 | } |
45 | -{ return 0; } | 29 | |
46 | #endif | 30 | if (s->dump_info.d_endian == ELFDATA2MSB) { |
47 | 31 | @@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f, | |
48 | typedef struct ARMVectorReg { | 32 | */ |
49 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 33 | for (i = 0; i < 32; ++i) { |
34 | uint64_t tmp = note.vfp.vregs[2*i]; | ||
35 | - note.vfp.vregs[2*i] = note.vfp.vregs[2*i+1]; | ||
36 | - note.vfp.vregs[2*i+1] = tmp; | ||
37 | + note.vfp.vregs[2 * i] = note.vfp.vregs[2 * i + 1]; | ||
38 | + note.vfp.vregs[2 * i + 1] = tmp; | ||
39 | } | ||
40 | } | ||
41 | |||
42 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | 43 | index XXXXXXX..XXXXXXX 100644 |
51 | --- a/target/arm/cpu64.c | 44 | --- a/target/arm/arm-semi.c |
52 | +++ b/target/arm/cpu64.c | 45 | +++ b/target/arm/arm-semi.c |
53 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) | 46 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) |
54 | cpu->sve_max_vq = max_vq; | 47 | if (use_gdb_syscalls()) { |
55 | } | 48 | arm_semi_open_guestfd = guestfd; |
56 | 49 | ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0, | |
57 | -uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq) | 50 | - (int)arg2+1, gdb_open_modeflags[arg1]); |
58 | -{ | 51 | + (int)arg2 + 1, gdb_open_modeflags[arg1]); |
59 | - uint32_t bitnum; | 52 | } else { |
60 | - | 53 | ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644)); |
61 | - /* | 54 | if (ret == (uint32_t)-1) { |
62 | - * We allow vq == ARM_MAX_VQ + 1 to be input because the caller may want | 55 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) |
63 | - * to find the maximum vq enabled, which may be ARM_MAX_VQ, but this | 56 | GET_ARG(1); |
64 | - * function always returns the next smaller than the input. | 57 | if (use_gdb_syscalls()) { |
65 | - */ | 58 | ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s", |
66 | - assert(vq && vq <= ARM_MAX_VQ + 1); | 59 | - arg0, (int)arg1+1); |
67 | - | 60 | + arg0, (int)arg1 + 1); |
68 | - bitnum = find_last_bit(cpu->sve_vq_map, vq - 1); | 61 | } else { |
69 | - return bitnum == vq - 1 ? 0 : bitnum + 1; | 62 | s = lock_user_string(arg0); |
70 | -} | 63 | if (!s) { |
71 | - | 64 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) |
72 | static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, | 65 | GET_ARG(3); |
73 | void *opaque, Error **errp) | 66 | if (use_gdb_syscalls()) { |
74 | { | 67 | return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s", |
68 | - arg0, (int)arg1+1, arg2, (int)arg3+1); | ||
69 | + arg0, (int)arg1 + 1, arg2, (int)arg3 + 1); | ||
70 | } else { | ||
71 | char *s2; | ||
72 | s = lock_user_string(arg0); | ||
73 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
74 | GET_ARG(1); | ||
75 | if (use_gdb_syscalls()) { | ||
76 | return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s", | ||
77 | - arg0, (int)arg1+1); | ||
78 | + arg0, (int)arg1 + 1); | ||
79 | } else { | ||
80 | s = lock_user_string(arg0); | ||
81 | if (!s) { | ||
75 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 82 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
76 | index XXXXXXX..XXXXXXX 100644 | 83 | index XXXXXXX..XXXXXXX 100644 |
77 | --- a/target/arm/helper.c | 84 | --- a/target/arm/helper.c |
78 | +++ b/target/arm/helper.c | 85 | +++ b/target/arm/helper.c |
79 | @@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el) | 86 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(usad8)(uint32_t a, uint32_t b) |
80 | 87 | uint32_t sum; | |
81 | static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) | 88 | sum = do_usad(a, b); |
82 | { | 89 | sum += do_usad(a >> 8, b >> 8); |
83 | - uint32_t start_vq = (start_len & 0xf) + 1; | 90 | - sum += do_usad(a >> 16, b >>16); |
84 | + uint32_t end_len; | 91 | + sum += do_usad(a >> 16, b >> 16); |
85 | 92 | sum += do_usad(a >> 24, b >> 24); | |
86 | - return arm_cpu_vq_map_next_smaller(cpu, start_vq + 1) - 1; | 93 | return sum; |
87 | + end_len = start_len &= 0xf; | ||
88 | + if (!test_bit(start_len, cpu->sve_vq_map)) { | ||
89 | + end_len = find_last_bit(cpu->sve_vq_map, start_len); | ||
90 | + assert(end_len < start_len); | ||
91 | + } | ||
92 | + return end_len; | ||
93 | } | 94 | } |
94 | |||
95 | /* | ||
96 | -- | 95 | -- |
97 | 2.20.1 | 96 | 2.20.1 |
98 | 97 | ||
99 | 98 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Xinhao Zhang <zhangxinhao1@huawei.com> | ||
1 | 2 | ||
3 | Fix code style. Don't use '#' flag of printf format ('%#') in | ||
4 | format strings, use '0x' prefix instead | ||
5 | |||
6 | Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com> | ||
7 | Signed-off-by: Kai Deng <dengkai1@huawei.com> | ||
8 | Message-id: 20201103114529.638233-2-zhangxinhao1@huawei.com | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/translate-a64.c | 4 ++-- | ||
13 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/translate-a64.c | ||
18 | +++ b/target/arm/translate-a64.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) | ||
20 | gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | ||
21 | break; | ||
22 | default: | ||
23 | - fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", | ||
24 | + fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64 "\n", | ||
25 | __func__, insn, fpopcode, s->pc_curr); | ||
26 | g_assert_not_reached(); | ||
27 | } | ||
28 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) | ||
29 | case 0x7f: /* FSQRT (vector) */ | ||
30 | break; | ||
31 | default: | ||
32 | - fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); | ||
33 | + fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fpop); | ||
34 | g_assert_not_reached(); | ||
35 | } | ||
36 | |||
37 | -- | ||
38 | 2.20.1 | ||
39 | |||
40 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Xinhao Zhang <zhangxinhao1@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | There was too much cut and paste between ldrexd and strexd, | 3 | Fix code style. Space required before the open parenthesis '('. |
4 | as ldrexd does prohibit two output registers the same. | ||
5 | 4 | ||
6 | Fixes: af288228995 | 5 | Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com> |
7 | Reported-by: Michael Goffioul <michael.goffioul@gmail.com> | 6 | Signed-off-by: Kai Deng <dengkai1@huawei.com> |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Message-id: 20201103114529.638233-3-zhangxinhao1@huawei.com |
9 | Message-id: 20191117090621.32425-2-richard.henderson@linaro.org | ||
10 | Reviewed-by: Robert Foley <robert.foley@linaro.org> | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 10 | --- |
14 | target/arm/translate.c | 2 +- | 11 | target/arm/translate.c | 2 +- |
15 | 1 file changed, 1 insertion(+), 1 deletion(-) | 12 | 1 file changed, 1 insertion(+), 1 deletion(-) |
16 | 13 | ||
17 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 14 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
18 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/translate.c | 16 | --- a/target/arm/translate.c |
20 | +++ b/target/arm/translate.c | 17 | +++ b/target/arm/translate.c |
21 | @@ -XXX,XX +XXX,XX @@ static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel) | 18 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) |
22 | || (s->thumb && (a->rd == 13 || a->rt == 13)) | 19 | - Hardware watchpoints. |
23 | || (mop == MO_64 | 20 | Hardware breakpoints have already been handled and skip this code. |
24 | && (a->rt2 == 15 | 21 | */ |
25 | - || a->rd == a->rt2 || a->rt == a->rt2 | 22 | - switch(dc->base.is_jmp) { |
26 | + || a->rd == a->rt2 | 23 | + switch (dc->base.is_jmp) { |
27 | || (s->thumb && a->rt2 == 13)))) { | 24 | case DISAS_NEXT: |
28 | unallocated_encoding(s); | 25 | case DISAS_TOO_MANY: |
29 | return true; | 26 | gen_goto_tb(dc, 1, dc->base.pc_next); |
30 | -- | 27 | -- |
31 | 2.20.1 | 28 | 2.20.1 |
32 | 29 | ||
33 | 30 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Alex Bennée <alex.bennee@linaro.org> | ||
1 | 2 | ||
3 | We should at least document what this machine is about. | ||
4 | |||
5 | Reviewed-by: Graeme Gregory <graeme@nuviainc.com> | ||
6 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
7 | Message-id: 20201104165254.24822-1-alex.bennee@linaro.org | ||
8 | Cc: Leif Lindholm <leif@nuviainc.com> | ||
9 | Cc: Shashi Mallela <shashi.mallela@linaro.org> | ||
10 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
11 | [PMM: fixed filename mismatch] | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++++++++++++ | ||
15 | docs/system/target-arm.rst | 1 + | ||
16 | 2 files changed, 33 insertions(+) | ||
17 | create mode 100644 docs/system/arm/sbsa.rst | ||
18 | |||
19 | diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst | ||
20 | new file mode 100644 | ||
21 | index XXXXXXX..XXXXXXX | ||
22 | --- /dev/null | ||
23 | +++ b/docs/system/arm/sbsa.rst | ||
24 | @@ -XXX,XX +XXX,XX @@ | ||
25 | +Arm Server Base System Architecture Reference board (``sbsa-ref``) | ||
26 | +================================================================== | ||
27 | + | ||
28 | +While the `virt` board is a generic board platform that doesn't match | ||
29 | +any real hardware the `sbsa-ref` board intends to look like real | ||
30 | +hardware. The `Server Base System Architecture | ||
31 | +<https://developer.arm.com/documentation/den0029/latest>` defines a | ||
32 | +minimum base line of hardware support and importantly how the firmware | ||
33 | +reports that to any operating system. It is a static system that | ||
34 | +reports a very minimal DT to the firmware for non-discoverable | ||
35 | +information about components affected by the qemu command line (i.e. | ||
36 | +cpus and memory). As a result it must have a firmware specifically | ||
37 | +built to expect a certain hardware layout (as you would in a real | ||
38 | +machine). | ||
39 | + | ||
40 | +It is intended to be a machine for developing firmware and testing | ||
41 | +standards compliance with operating systems. | ||
42 | + | ||
43 | +Supported devices | ||
44 | +""""""""""""""""" | ||
45 | + | ||
46 | +The sbsa-ref board supports: | ||
47 | + | ||
48 | + - A configurable number of AArch64 CPUs | ||
49 | + - GIC version 3 | ||
50 | + - System bus AHCI controller | ||
51 | + - System bus EHCI controller | ||
52 | + - CDROM and hard disc on AHCI bus | ||
53 | + - E1000E ethernet card on PCIe bus | ||
54 | + - VGA display adaptor on PCIe bus | ||
55 | + - A generic SBSA watchdog device | ||
56 | + | ||
57 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
58 | index XXXXXXX..XXXXXXX 100644 | ||
59 | --- a/docs/system/target-arm.rst | ||
60 | +++ b/docs/system/target-arm.rst | ||
61 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | ||
62 | arm/mps2 | ||
63 | arm/musca | ||
64 | arm/realview | ||
65 | + arm/sbsa | ||
66 | arm/versatile | ||
67 | arm/vexpress | ||
68 | arm/aspeed | ||
69 | -- | ||
70 | 2.20.1 | ||
71 | |||
72 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
1 | 2 | ||
3 | When using a Cortex-A15, the Virt machine does not use any | ||
4 | MPCore peripherals. Remove the dependency. | ||
5 | |||
6 | Fixes: 7951c7b7c05 ("hw/arm: Express dependencies of the virt machine with Kconfig") | ||
7 | Reported-by: Miroslav Rezanina <mrezanin@redhat.com> | ||
8 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
9 | Message-id: 20201107114852.271922-1-philmd@redhat.com | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | hw/arm/Kconfig | 1 - | ||
14 | 1 file changed, 1 deletion(-) | ||
15 | |||
16 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/hw/arm/Kconfig | ||
19 | +++ b/hw/arm/Kconfig | ||
20 | @@ -XXX,XX +XXX,XX @@ config ARM_VIRT | ||
21 | imply VFIO_PLATFORM | ||
22 | imply VFIO_XGMAC | ||
23 | imply TPM_TIS_SYSBUS | ||
24 | - select A15MPCORE | ||
25 | select ACPI | ||
26 | select ARM_SMMUV3 | ||
27 | select GPIO_KEY | ||
28 | -- | ||
29 | 2.20.1 | ||
30 | |||
31 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Simply moving the non-stub helper_v7m_mrs/msr outside of | 3 | The helper function did not get updated when we reorganized |
4 | !CONFIG_USER_ONLY is not an option, because of all of the | 4 | the vector register file for SVE. Since then, the neon dregs |
5 | other system-mode helpers that are called. | 5 | are non-sequential and cannot be simply indexed. |
6 | 6 | ||
7 | But we can split out a few subroutines to handle the few | 7 | At the same time, make the helper function operate on 64-bit |
8 | EL0 accessible registers without duplicating code. | 8 | quantities so that we do not have to call it twice. |
9 | 9 | ||
10 | Reported-by: Christophe Lyon <christophe.lyon@linaro.org> | 10 | Fixes: c39c2b9043e |
11 | Reported-by: Ard Biesheuvel <ardb@kernel.org> | ||
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
12 | Message-id: 20191118194916.3670-1-richard.henderson@linaro.org | 13 | [PMM: use aa32_vfp_dreg() rather than opencoding] |
13 | [PMM: deleted now-redundant comment; added a default case | 14 | Message-id: 20201105171126.88014-1-richard.henderson@linaro.org |
14 | to switch in v7m_msr helper] | ||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 17 | --- |
18 | target/arm/cpu.h | 2 + | 18 | target/arm/helper.h | 2 +- |
19 | target/arm/m_helper.c | 114 ++++++++++++++++++++++++++---------------- | 19 | target/arm/op_helper.c | 23 +++++++++-------- |
20 | 2 files changed, 73 insertions(+), 43 deletions(-) | 20 | target/arm/translate-neon.c.inc | 44 +++++++++++---------------------- |
21 | 3 files changed, 29 insertions(+), 40 deletions(-) | ||
21 | 22 | ||
22 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 23 | diff --git a/target/arm/helper.h b/target/arm/helper.h |
23 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/target/arm/cpu.h | 25 | --- a/target/arm/helper.h |
25 | +++ b/target/arm/cpu.h | 26 | +++ b/target/arm/helper.h |
26 | @@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | 27 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr) |
27 | if (mask & XPSR_GE) { | 28 | DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr) |
28 | env->GE = (val & XPSR_GE) >> 16; | 29 | DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32) |
30 | DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32) | ||
31 | -DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32) | ||
32 | +DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64) | ||
33 | |||
34 | DEF_HELPER_3(shl_cc, i32, env, i32, i32) | ||
35 | DEF_HELPER_3(shr_cc, i32, env, i32, i32) | ||
36 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/op_helper.c | ||
39 | +++ b/target/arm/op_helper.c | ||
40 | @@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, | ||
41 | cpu_loop_exit_restore(cs, ra); | ||
42 | } | ||
43 | |||
44 | -uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn, | ||
45 | - uint32_t maxindex) | ||
46 | +uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc, | ||
47 | + uint64_t ireg, uint64_t def) | ||
48 | { | ||
49 | - uint32_t val, shift; | ||
50 | - uint64_t *table = vn; | ||
51 | + uint64_t tmp, val = 0; | ||
52 | + uint32_t maxindex = ((desc & 3) + 1) * 8; | ||
53 | + uint32_t base_reg = desc >> 2; | ||
54 | + uint32_t shift, index, reg; | ||
55 | |||
56 | - val = 0; | ||
57 | - for (shift = 0; shift < 32; shift += 8) { | ||
58 | - uint32_t index = (ireg >> shift) & 0xff; | ||
59 | + for (shift = 0; shift < 64; shift += 8) { | ||
60 | + index = (ireg >> shift) & 0xff; | ||
61 | if (index < maxindex) { | ||
62 | - uint32_t tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff; | ||
63 | - val |= tmp << shift; | ||
64 | + reg = base_reg + (index >> 3); | ||
65 | + tmp = *aa32_vfp_dreg(env, reg); | ||
66 | + tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift; | ||
67 | } else { | ||
68 | - val |= def & (0xff << shift); | ||
69 | + tmp = def & (0xffull << shift); | ||
70 | } | ||
71 | + val |= tmp; | ||
29 | } | 72 | } |
30 | +#ifndef CONFIG_USER_ONLY | 73 | return val; |
31 | if (mask & XPSR_T) { | 74 | } |
32 | env->thumb = ((val & XPSR_T) != 0); | 75 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc |
76 | index XXXXXXX..XXXXXXX 100644 | ||
77 | --- a/target/arm/translate-neon.c.inc | ||
78 | +++ b/target/arm/translate-neon.c.inc | ||
79 | @@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) | ||
80 | |||
81 | static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
82 | { | ||
83 | - int n; | ||
84 | - TCGv_i32 tmp, tmp2, tmp3, tmp4; | ||
85 | - TCGv_ptr ptr1; | ||
86 | + TCGv_i64 val, def; | ||
87 | + TCGv_i32 desc; | ||
88 | |||
89 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
90 | return false; | ||
91 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
92 | return true; | ||
33 | } | 93 | } |
34 | @@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | 94 | |
35 | /* Note that this only happens on exception exit */ | 95 | - n = a->len + 1; |
36 | write_v7m_exception(env, val & XPSR_EXCP); | 96 | - if ((a->vn + n) > 32) { |
97 | + if ((a->vn + a->len + 1) > 32) { | ||
98 | /* | ||
99 | * This is UNPREDICTABLE; we choose to UNDEF to avoid the | ||
100 | * helper function running off the end of the register file. | ||
101 | */ | ||
102 | return false; | ||
37 | } | 103 | } |
38 | +#endif | 104 | - n <<= 3; |
105 | - tmp = tcg_temp_new_i32(); | ||
106 | - if (a->op) { | ||
107 | - read_neon_element32(tmp, a->vd, 0, MO_32); | ||
108 | - } else { | ||
109 | - tcg_gen_movi_i32(tmp, 0); | ||
110 | - } | ||
111 | - tmp2 = tcg_temp_new_i32(); | ||
112 | - read_neon_element32(tmp2, a->vm, 0, MO_32); | ||
113 | - ptr1 = vfp_reg_ptr(true, a->vn); | ||
114 | - tmp4 = tcg_const_i32(n); | ||
115 | - gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4); | ||
116 | |||
117 | + desc = tcg_const_i32((a->vn << 2) | a->len); | ||
118 | + def = tcg_temp_new_i64(); | ||
119 | if (a->op) { | ||
120 | - read_neon_element32(tmp, a->vd, 1, MO_32); | ||
121 | + read_neon_element64(def, a->vd, 0, MO_64); | ||
122 | } else { | ||
123 | - tcg_gen_movi_i32(tmp, 0); | ||
124 | + tcg_gen_movi_i64(def, 0); | ||
125 | } | ||
126 | - tmp3 = tcg_temp_new_i32(); | ||
127 | - read_neon_element32(tmp3, a->vm, 1, MO_32); | ||
128 | - gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4); | ||
129 | - tcg_temp_free_i32(tmp); | ||
130 | - tcg_temp_free_i32(tmp4); | ||
131 | - tcg_temp_free_ptr(ptr1); | ||
132 | + val = tcg_temp_new_i64(); | ||
133 | + read_neon_element64(val, a->vm, 0, MO_64); | ||
134 | |||
135 | - write_neon_element32(tmp2, a->vd, 0, MO_32); | ||
136 | - write_neon_element32(tmp3, a->vd, 1, MO_32); | ||
137 | - tcg_temp_free_i32(tmp2); | ||
138 | - tcg_temp_free_i32(tmp3); | ||
139 | + gen_helper_neon_tbl(val, cpu_env, desc, val, def); | ||
140 | + write_neon_element64(val, a->vd, 0, MO_64); | ||
141 | + | ||
142 | + tcg_temp_free_i64(def); | ||
143 | + tcg_temp_free_i64(val); | ||
144 | + tcg_temp_free_i32(desc); | ||
145 | return true; | ||
39 | } | 146 | } |
40 | 147 | ||
41 | #define HCR_VM (1ULL << 0) | ||
42 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/target/arm/m_helper.c | ||
45 | +++ b/target/arm/m_helper.c | ||
46 | @@ -XXX,XX +XXX,XX @@ | ||
47 | #include "exec/cpu_ldst.h" | ||
48 | #endif | ||
49 | |||
50 | +static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, | ||
51 | + uint32_t reg, uint32_t val) | ||
52 | +{ | ||
53 | + /* Only APSR is actually writable */ | ||
54 | + if (!(reg & 4)) { | ||
55 | + uint32_t apsrmask = 0; | ||
56 | + | ||
57 | + if (mask & 8) { | ||
58 | + apsrmask |= XPSR_NZCV | XPSR_Q; | ||
59 | + } | ||
60 | + if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { | ||
61 | + apsrmask |= XPSR_GE; | ||
62 | + } | ||
63 | + xpsr_write(env, val, apsrmask); | ||
64 | + } | ||
65 | +} | ||
66 | + | ||
67 | +static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el) | ||
68 | +{ | ||
69 | + uint32_t mask = 0; | ||
70 | + | ||
71 | + if ((reg & 1) && el) { | ||
72 | + mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */ | ||
73 | + } | ||
74 | + if (!(reg & 4)) { | ||
75 | + mask |= XPSR_NZCV | XPSR_Q; /* APSR */ | ||
76 | + if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) { | ||
77 | + mask |= XPSR_GE; | ||
78 | + } | ||
79 | + } | ||
80 | + /* EPSR reads as zero */ | ||
81 | + return xpsr_read(env) & mask; | ||
82 | +} | ||
83 | + | ||
84 | +static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure) | ||
85 | +{ | ||
86 | + uint32_t value = env->v7m.control[secure]; | ||
87 | + | ||
88 | + if (!secure) { | ||
89 | + /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank */ | ||
90 | + value |= env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK; | ||
91 | + } | ||
92 | + return value; | ||
93 | +} | ||
94 | + | ||
95 | #ifdef CONFIG_USER_ONLY | ||
96 | |||
97 | -/* These should probably raise undefined insn exceptions. */ | ||
98 | -void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) | ||
99 | +void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | ||
100 | { | ||
101 | - ARMCPU *cpu = env_archcpu(env); | ||
102 | + uint32_t mask = extract32(maskreg, 8, 4); | ||
103 | + uint32_t reg = extract32(maskreg, 0, 8); | ||
104 | |||
105 | - cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); | ||
106 | + switch (reg) { | ||
107 | + case 0 ... 7: /* xPSR sub-fields */ | ||
108 | + v7m_msr_xpsr(env, mask, reg, val); | ||
109 | + break; | ||
110 | + case 20: /* CONTROL */ | ||
111 | + /* There are no sub-fields that are actually writable from EL0. */ | ||
112 | + break; | ||
113 | + default: | ||
114 | + /* Unprivileged writes to other registers are ignored */ | ||
115 | + break; | ||
116 | + } | ||
117 | } | ||
118 | |||
119 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | ||
120 | { | ||
121 | - ARMCPU *cpu = env_archcpu(env); | ||
122 | - | ||
123 | - cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); | ||
124 | - return 0; | ||
125 | + switch (reg) { | ||
126 | + case 0 ... 7: /* xPSR sub-fields */ | ||
127 | + return v7m_mrs_xpsr(env, reg, 0); | ||
128 | + case 20: /* CONTROL */ | ||
129 | + return v7m_mrs_control(env, 0); | ||
130 | + default: | ||
131 | + /* Unprivileged reads others as zero. */ | ||
132 | + return 0; | ||
133 | + } | ||
134 | } | ||
135 | |||
136 | void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) | ||
137 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | ||
138 | |||
139 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | ||
140 | { | ||
141 | - uint32_t mask; | ||
142 | unsigned el = arm_current_el(env); | ||
143 | |||
144 | /* First handle registers which unprivileged can read */ | ||
145 | - | ||
146 | switch (reg) { | ||
147 | case 0 ... 7: /* xPSR sub-fields */ | ||
148 | - mask = 0; | ||
149 | - if ((reg & 1) && el) { | ||
150 | - mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */ | ||
151 | - } | ||
152 | - if (!(reg & 4)) { | ||
153 | - mask |= XPSR_NZCV | XPSR_Q; /* APSR */ | ||
154 | - if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) { | ||
155 | - mask |= XPSR_GE; | ||
156 | - } | ||
157 | - } | ||
158 | - /* EPSR reads as zero */ | ||
159 | - return xpsr_read(env) & mask; | ||
160 | - break; | ||
161 | + return v7m_mrs_xpsr(env, reg, el); | ||
162 | case 20: /* CONTROL */ | ||
163 | - { | ||
164 | - uint32_t value = env->v7m.control[env->v7m.secure]; | ||
165 | - if (!env->v7m.secure) { | ||
166 | - /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank */ | ||
167 | - value |= env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK; | ||
168 | - } | ||
169 | - return value; | ||
170 | - } | ||
171 | + return v7m_mrs_control(env, env->v7m.secure); | ||
172 | case 0x94: /* CONTROL_NS */ | ||
173 | /* | ||
174 | * We have to handle this here because unprivileged Secure code | ||
175 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | ||
176 | |||
177 | switch (reg) { | ||
178 | case 0 ... 7: /* xPSR sub-fields */ | ||
179 | - /* only APSR is actually writable */ | ||
180 | - if (!(reg & 4)) { | ||
181 | - uint32_t apsrmask = 0; | ||
182 | - | ||
183 | - if (mask & 8) { | ||
184 | - apsrmask |= XPSR_NZCV | XPSR_Q; | ||
185 | - } | ||
186 | - if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { | ||
187 | - apsrmask |= XPSR_GE; | ||
188 | - } | ||
189 | - xpsr_write(env, val, apsrmask); | ||
190 | - } | ||
191 | + v7m_msr_xpsr(env, mask, reg, val); | ||
192 | break; | ||
193 | case 8: /* MSP */ | ||
194 | if (v7m_using_psp(env)) { | ||
195 | -- | 148 | -- |
196 | 2.20.1 | 149 | 2.20.1 |
197 | 150 | ||
198 | 151 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
1 | 2 | ||
3 | We can use one MPC per SRAM bank, but we currently only wire the | ||
4 | IRQ from the first expansion MPC to the IRQ splitter. Fix that. | ||
5 | |||
6 | Fixes: bb75e16d5e6 ("hw/arm/iotkit: Wire up MPC interrupt lines") | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Message-id: 20201107193403.436146-2-f4bug@amsat.org | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | hw/arm/armsse.c | 3 ++- | ||
13 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
14 | |||
15 | diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/hw/arm/armsse.c | ||
18 | +++ b/hw/arm/armsse.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp) | ||
20 | qdev_get_gpio_in(dev_splitter, 0)); | ||
21 | qdev_connect_gpio_out(dev_splitter, 0, | ||
22 | qdev_get_gpio_in_named(dev_secctl, | ||
23 | - "mpc_status", 0)); | ||
24 | + "mpc_status", | ||
25 | + i - IOTS_NUM_EXP_MPC)); | ||
26 | } | ||
27 | |||
28 | qdev_connect_gpio_out(dev_splitter, 1, | ||
29 | -- | ||
30 | 2.20.1 | ||
31 | |||
32 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
1 | 2 | ||
3 | The system configuration controller (SYSCFG) doesn't have | ||
4 | any output IRQ (and the INTC input #71 belongs to the UART6). | ||
5 | Remove the invalid code. | ||
6 | |||
7 | Fixes: db635521a02 ("stm32f205: Add the stm32f205 SoC") | ||
8 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Message-id: 20201107193403.436146-3-f4bug@amsat.org | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | include/hw/misc/stm32f2xx_syscfg.h | 2 -- | ||
14 | hw/arm/stm32f205_soc.c | 1 - | ||
15 | hw/misc/stm32f2xx_syscfg.c | 2 -- | ||
16 | 3 files changed, 5 deletions(-) | ||
17 | |||
18 | diff --git a/include/hw/misc/stm32f2xx_syscfg.h b/include/hw/misc/stm32f2xx_syscfg.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/misc/stm32f2xx_syscfg.h | ||
21 | +++ b/include/hw/misc/stm32f2xx_syscfg.h | ||
22 | @@ -XXX,XX +XXX,XX @@ struct STM32F2XXSyscfgState { | ||
23 | uint32_t syscfg_exticr3; | ||
24 | uint32_t syscfg_exticr4; | ||
25 | uint32_t syscfg_cmpcr; | ||
26 | - | ||
27 | - qemu_irq irq; | ||
28 | }; | ||
29 | |||
30 | #endif /* HW_STM32F2XX_SYSCFG_H */ | ||
31 | diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/hw/arm/stm32f205_soc.c | ||
34 | +++ b/hw/arm/stm32f205_soc.c | ||
35 | @@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) | ||
36 | } | ||
37 | busdev = SYS_BUS_DEVICE(dev); | ||
38 | sysbus_mmio_map(busdev, 0, 0x40013800); | ||
39 | - sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71)); | ||
40 | |||
41 | /* Attach UART (uses USART registers) and USART controllers */ | ||
42 | for (i = 0; i < STM_NUM_USARTS; i++) { | ||
43 | diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/hw/misc/stm32f2xx_syscfg.c | ||
46 | +++ b/hw/misc/stm32f2xx_syscfg.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static void stm32f2xx_syscfg_init(Object *obj) | ||
48 | { | ||
49 | STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj); | ||
50 | |||
51 | - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); | ||
52 | - | ||
53 | memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s, | ||
54 | TYPE_STM32F2XX_SYSCFG, 0x400); | ||
55 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); | ||
56 | -- | ||
57 | 2.20.1 | ||
58 | |||
59 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | Armv8-A removes UNPREDICTABLE for R13 for these cases. | 3 | omap2420_mpu_init() introduced in commit 827df9f3c5f ("Add basic |
4 | OMAP2 chip support") takes care of creating the 3 UARTs. | ||
4 | 5 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Then commit 58a26b477e9 ("Emulate a serial bluetooth HCI with H4+ |
6 | Message-id: 20191117090621.32425-3-richard.henderson@linaro.org | 7 | extensions and attach to n8x0's UART") added n8x0_uart_setup() |
7 | [PMM: changed ENABLE_ARCH_8 checks to check a new bool 'v8a', | 8 | which create the UART and connects it to an IRQ output, |
8 | since these cases are still UNPREDICTABLE for v8M] | 9 | overwritting the existing peripheral and its IRQ connection. |
10 | This is incorrect. | ||
11 | |||
12 | Fortunately we don't need to fix this, because commit 6da68df7f9b | ||
13 | ("hw/arm/nseries: Replace the bluetooth chardev with a "null" | ||
14 | chardev") removed the use of this peripheral. We can simply | ||
15 | remove the code. | ||
16 | |||
17 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
18 | Message-id: 20201107193403.436146-4-f4bug@amsat.org | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 21 | --- |
12 | target/arm/translate.c | 12 ++++++++---- | 22 | hw/arm/nseries.c | 11 ----------- |
13 | 1 file changed, 8 insertions(+), 4 deletions(-) | 23 | 1 file changed, 11 deletions(-) |
14 | 24 | ||
15 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 25 | diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c |
16 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate.c | 27 | --- a/hw/arm/nseries.c |
18 | +++ b/target/arm/translate.c | 28 | +++ b/hw/arm/nseries.c |
19 | @@ -XXX,XX +XXX,XX @@ static bool trans_SWPB(DisasContext *s, arg_SWP *a) | 29 | @@ -XXX,XX +XXX,XX @@ static void n8x0_cbus_setup(struct n800_s *s) |
20 | static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel) | 30 | cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1)); |
31 | } | ||
32 | |||
33 | -static void n8x0_uart_setup(struct n800_s *s) | ||
34 | -{ | ||
35 | - Chardev *radio = qemu_chr_new("bt-dummy-uart", "null", NULL); | ||
36 | - /* | ||
37 | - * Note: We used to connect N8X0_BT_RESET_GPIO and N8X0_BT_WKUP_GPIO | ||
38 | - * here, but this code has been removed with the bluetooth backend. | ||
39 | - */ | ||
40 | - omap_uart_attach(s->mpu->uart[BT_UART], radio); | ||
41 | -} | ||
42 | - | ||
43 | static void n8x0_usb_setup(struct n800_s *s) | ||
21 | { | 44 | { |
22 | TCGv_i32 addr; | 45 | SysBusDevice *dev; |
23 | + /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */ | 46 | @@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine, |
24 | + bool v8a = ENABLE_ARCH_8 && !arm_dc_feature(s, ARM_FEATURE_M); | 47 | n8x0_spi_setup(s); |
25 | 48 | n8x0_dss_setup(s); | |
26 | /* We UNDEF for these UNPREDICTABLE cases. */ | 49 | n8x0_cbus_setup(s); |
27 | if (a->rd == 15 || a->rn == 15 || a->rt == 15 | 50 | - n8x0_uart_setup(s); |
28 | || a->rd == a->rn || a->rd == a->rt | 51 | if (machine_usb(machine)) { |
29 | - || (s->thumb && (a->rd == 13 || a->rt == 13)) | 52 | n8x0_usb_setup(s); |
30 | + || (!v8a && s->thumb && (a->rd == 13 || a->rt == 13)) | ||
31 | || (mop == MO_64 | ||
32 | && (a->rt2 == 15 | ||
33 | || a->rd == a->rt2 | ||
34 | - || (s->thumb && a->rt2 == 13)))) { | ||
35 | + || (!v8a && s->thumb && a->rt2 == 13)))) { | ||
36 | unallocated_encoding(s); | ||
37 | return true; | ||
38 | } | ||
39 | @@ -XXX,XX +XXX,XX @@ static bool trans_STLH(DisasContext *s, arg_STL *a) | ||
40 | static bool op_ldrex(DisasContext *s, arg_LDREX *a, MemOp mop, bool acq) | ||
41 | { | ||
42 | TCGv_i32 addr; | ||
43 | + /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */ | ||
44 | + bool v8a = ENABLE_ARCH_8 && !arm_dc_feature(s, ARM_FEATURE_M); | ||
45 | |||
46 | /* We UNDEF for these UNPREDICTABLE cases. */ | ||
47 | if (a->rn == 15 || a->rt == 15 | ||
48 | - || (s->thumb && a->rt == 13) | ||
49 | + || (!v8a && s->thumb && a->rt == 13) | ||
50 | || (mop == MO_64 | ||
51 | && (a->rt2 == 15 || a->rt == a->rt2 | ||
52 | - || (s->thumb && a->rt2 == 13)))) { | ||
53 | + || (!v8a && s->thumb && a->rt2 == 13)))) { | ||
54 | unallocated_encoding(s); | ||
55 | return true; | ||
56 | } | 53 | } |
57 | -- | 54 | -- |
58 | 2.20.1 | 55 | 2.20.1 |
59 | 56 | ||
60 | 57 | diff view generated by jsdifflib |
1 | From: Linus Ziegert <linus.ziegert+qemu@holoplot.com> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | The Linux kernel PHY driver sets AN_RESTART in the BMCR of the | 3 | The MusicPal board code connects both of the IRQ outputs of the UART |
4 | PHY when autonegotiation is started. | 4 | to the same INTC qemu_irq. Connecting two qemu_irqs outputs directly |
5 | Recently the kernel started to read back the PHY's AN_RESTART | 5 | to the same input is not valid as it produces subtly wrong behaviour |
6 | bit and now checks whether the autonegotiation is complete and | 6 | (for instance if both the IRQ lines are high, and then one goes |
7 | the bit was cleared [1]. Otherwise the link status is down. | 7 | low, the INTC input will see this as a high-to-low transition |
8 | even though the second IRQ line should still be holding it high). | ||
8 | 9 | ||
9 | The emulated PHY needs to clear AN_RESTART immediately to inform | 10 | This kind of wiring needs an explicitly created OR gate; add one. |
10 | the kernel driver about the completion of autonegotiation phase. | ||
11 | 11 | ||
12 | [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c36757eb9dee | 12 | Inspired-by: Peter Maydell <peter.maydell@linaro.org> |
13 | 13 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | |
14 | Signed-off-by: Linus Ziegert <linus.ziegert+qemu@holoplot.com> | 14 | Message-id: 20201107193403.436146-5-f4bug@amsat.org |
15 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Message-id: 20191104181604.21943-1-linus.ziegert+qemu@holoplot.com | ||
17 | Cc: qemu-stable@nongnu.org | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | --- | 17 | --- |
20 | hw/net/cadence_gem.c | 9 +++++---- | 18 | hw/arm/musicpal.c | 17 +++++++++++++---- |
21 | 1 file changed, 5 insertions(+), 4 deletions(-) | 19 | hw/arm/Kconfig | 1 + |
20 | 2 files changed, 14 insertions(+), 4 deletions(-) | ||
22 | 21 | ||
23 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c | 22 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c |
24 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/hw/net/cadence_gem.c | 24 | --- a/hw/arm/musicpal.c |
26 | +++ b/hw/net/cadence_gem.c | 25 | +++ b/hw/arm/musicpal.c |
27 | @@ -XXX,XX +XXX,XX @@ | 26 | @@ -XXX,XX +XXX,XX @@ |
28 | #define PHY_REG_EXT_PHYSPCFC_ST 27 | 27 | #include "ui/console.h" |
29 | #define PHY_REG_CABLE_DIAG 28 | 28 | #include "hw/i2c/i2c.h" |
30 | 29 | #include "hw/irq.h" | |
31 | -#define PHY_REG_CONTROL_RST 0x8000 | 30 | +#include "hw/or-irq.h" |
32 | -#define PHY_REG_CONTROL_LOOP 0x4000 | 31 | #include "hw/audio/wm8750.h" |
33 | -#define PHY_REG_CONTROL_ANEG 0x1000 | 32 | #include "sysemu/block-backend.h" |
34 | +#define PHY_REG_CONTROL_RST 0x8000 | 33 | #include "sysemu/runstate.h" |
35 | +#define PHY_REG_CONTROL_LOOP 0x4000 | 34 | @@ -XXX,XX +XXX,XX @@ |
36 | +#define PHY_REG_CONTROL_ANEG 0x1000 | 35 | #define MP_TIMER4_IRQ 7 |
37 | +#define PHY_REG_CONTROL_ANRESTART 0x0200 | 36 | #define MP_EHCI_IRQ 8 |
38 | 37 | #define MP_ETH_IRQ 9 | |
39 | #define PHY_REG_STATUS_LINK 0x0004 | 38 | -#define MP_UART1_IRQ 11 |
40 | #define PHY_REG_STATUS_ANEGCMPL 0x0020 | 39 | -#define MP_UART2_IRQ 11 |
41 | @@ -XXX,XX +XXX,XX @@ static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) | 40 | +#define MP_UART_SHARED_IRQ 11 |
42 | } | 41 | #define MP_GPIO_IRQ 12 |
43 | if (val & PHY_REG_CONTROL_ANEG) { | 42 | #define MP_RTC_IRQ 28 |
44 | /* Complete autonegotiation immediately */ | 43 | #define MP_AUDIO_IRQ 30 |
45 | - val &= ~PHY_REG_CONTROL_ANEG; | 44 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) |
46 | + val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART); | 45 | ARMCPU *cpu; |
47 | s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; | 46 | qemu_irq pic[32]; |
48 | } | 47 | DeviceState *dev; |
49 | if (val & PHY_REG_CONTROL_LOOP) { | 48 | + DeviceState *uart_orgate; |
49 | DeviceState *i2c_dev; | ||
50 | DeviceState *lcd_dev; | ||
51 | DeviceState *key_dev; | ||
52 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
53 | pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], | ||
54 | pic[MP_TIMER4_IRQ], NULL); | ||
55 | |||
56 | - serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ], | ||
57 | + /* Logically OR both UART IRQs together */ | ||
58 | + uart_orgate = DEVICE(object_new(TYPE_OR_IRQ)); | ||
59 | + object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal); | ||
60 | + qdev_realize_and_unref(uart_orgate, NULL, &error_fatal); | ||
61 | + qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]); | ||
62 | + | ||
63 | + serial_mm_init(address_space_mem, MP_UART1_BASE, 2, | ||
64 | + qdev_get_gpio_in(uart_orgate, 0), | ||
65 | 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN); | ||
66 | - serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ], | ||
67 | + serial_mm_init(address_space_mem, MP_UART2_BASE, 2, | ||
68 | + qdev_get_gpio_in(uart_orgate, 1), | ||
69 | 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN); | ||
70 | |||
71 | /* Register flash */ | ||
72 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
73 | index XXXXXXX..XXXXXXX 100644 | ||
74 | --- a/hw/arm/Kconfig | ||
75 | +++ b/hw/arm/Kconfig | ||
76 | @@ -XXX,XX +XXX,XX @@ config MUSCA | ||
77 | |||
78 | config MUSICPAL | ||
79 | bool | ||
80 | + select OR_IRQ | ||
81 | select BITBANG_I2C | ||
82 | select MARVELL_88W8618 | ||
83 | select PTIMER | ||
50 | -- | 84 | -- |
51 | 2.20.1 | 85 | 2.20.1 |
52 | 86 | ||
53 | 87 | diff view generated by jsdifflib |
1 | From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | A few configuration register writes need not update the spi bus state, so just | 3 | We don't need to fill the full pic[] array if we only use |
4 | return after the register write. | 4 | few of the interrupt lines. Directly call qdev_get_gpio_in() |
5 | when necessary. | ||
5 | 6 | ||
6 | Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> | 7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 8 | Message-id: 20201107193403.436146-6-f4bug@amsat.org |
8 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
10 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
11 | Message-id: 1573830705-14579-1-git-send-email-sai.pavan.boddu@xilinx.com | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 11 | --- |
14 | hw/ssi/xilinx_spips.c | 22 ++++++++++++++++++---- | 12 | hw/arm/musicpal.c | 25 +++++++++++++------------ |
15 | 1 file changed, 18 insertions(+), 4 deletions(-) | 13 | 1 file changed, 13 insertions(+), 12 deletions(-) |
16 | 14 | ||
17 | diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c | 15 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c |
18 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/ssi/xilinx_spips.c | 17 | --- a/hw/arm/musicpal.c |
20 | +++ b/hw/ssi/xilinx_spips.c | 18 | +++ b/hw/arm/musicpal.c |
21 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ static struct arm_boot_info musicpal_binfo = { |
22 | #define R_GPIO (0x30 / 4) | 20 | static void musicpal_init(MachineState *machine) |
23 | #define R_LPBK_DLY_ADJ (0x38 / 4) | ||
24 | #define R_LPBK_DLY_ADJ_RESET (0x33) | ||
25 | +#define R_IOU_TAPDLY_BYPASS (0x3C / 4) | ||
26 | #define R_TXD1 (0x80 / 4) | ||
27 | #define R_TXD2 (0x84 / 4) | ||
28 | #define R_TXD3 (0x88 / 4) | ||
29 | @@ -XXX,XX +XXX,XX @@ | ||
30 | #define R_LQSPI_STS (0xA4 / 4) | ||
31 | #define LQSPI_STS_WR_RECVD (1 << 1) | ||
32 | |||
33 | +#define R_DUMMY_CYCLE_EN (0xC8 / 4) | ||
34 | +#define R_ECO (0xF8 / 4) | ||
35 | #define R_MOD_ID (0xFC / 4) | ||
36 | |||
37 | #define R_GQSPI_SELECT (0x144 / 4) | ||
38 | @@ -XXX,XX +XXX,XX @@ static void xilinx_spips_write(void *opaque, hwaddr addr, | ||
39 | { | 21 | { |
40 | int mask = ~0; | 22 | ARMCPU *cpu; |
41 | XilinxSPIPS *s = opaque; | 23 | - qemu_irq pic[32]; |
42 | + bool try_flush = true; | 24 | DeviceState *dev; |
43 | 25 | + DeviceState *pic; | |
44 | DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); | 26 | DeviceState *uart_orgate; |
45 | addr >>= 2; | 27 | DeviceState *i2c_dev; |
46 | @@ -XXX,XX +XXX,XX @@ static void xilinx_spips_write(void *opaque, hwaddr addr, | 28 | DeviceState *lcd_dev; |
47 | tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, | 29 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) |
48 | s->regs[R_CONFIG] & R_CONFIG_ENDIAN); | 30 | &error_fatal); |
49 | goto no_reg_update; | 31 | memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram); |
50 | + /* Skip SPI bus update for below registers writes */ | 32 | |
51 | + case R_GPIO: | 33 | - dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE, |
52 | + case R_LPBK_DLY_ADJ: | 34 | + pic = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE, |
53 | + case R_IOU_TAPDLY_BYPASS: | 35 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); |
54 | + case R_DUMMY_CYCLE_EN: | 36 | - for (i = 0; i < 32; i++) { |
55 | + case R_ECO: | 37 | - pic[i] = qdev_get_gpio_in(dev, i); |
56 | + try_flush = false; | 38 | - } |
57 | + break; | 39 | - sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ], |
58 | } | 40 | - pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], |
59 | s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); | 41 | - pic[MP_TIMER4_IRQ], NULL); |
60 | no_reg_update: | 42 | + sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, |
61 | - xilinx_spips_update_cs_lines(s); | 43 | + qdev_get_gpio_in(pic, MP_TIMER1_IRQ), |
62 | - xilinx_spips_check_flush(s); | 44 | + qdev_get_gpio_in(pic, MP_TIMER2_IRQ), |
63 | - xilinx_spips_update_cs_lines(s); | 45 | + qdev_get_gpio_in(pic, MP_TIMER3_IRQ), |
64 | - xilinx_spips_update_ixr(s); | 46 | + qdev_get_gpio_in(pic, MP_TIMER4_IRQ), NULL); |
65 | + if (try_flush) { | 47 | |
66 | + xilinx_spips_update_cs_lines(s); | 48 | /* Logically OR both UART IRQs together */ |
67 | + xilinx_spips_check_flush(s); | 49 | uart_orgate = DEVICE(object_new(TYPE_OR_IRQ)); |
68 | + xilinx_spips_update_cs_lines(s); | 50 | object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal); |
69 | + xilinx_spips_update_ixr(s); | 51 | qdev_realize_and_unref(uart_orgate, NULL, &error_fatal); |
70 | + } | 52 | - qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]); |
71 | } | 53 | + qdev_connect_gpio_out(DEVICE(uart_orgate), 0, |
72 | 54 | + qdev_get_gpio_in(pic, MP_UART_SHARED_IRQ)); | |
73 | static const MemoryRegionOps spips_ops = { | 55 | |
56 | serial_mm_init(address_space_mem, MP_UART1_BASE, 2, | ||
57 | qdev_get_gpio_in(uart_orgate, 0), | ||
58 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
59 | OBJECT(get_system_memory()), &error_fatal); | ||
60 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
61 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE); | ||
62 | - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]); | ||
63 | + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, | ||
64 | + qdev_get_gpio_in(pic, MP_ETH_IRQ)); | ||
65 | |||
66 | sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); | ||
67 | |||
68 | sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL); | ||
69 | |||
70 | dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE, | ||
71 | - pic[MP_GPIO_IRQ]); | ||
72 | + qdev_get_gpio_in(pic, MP_GPIO_IRQ)); | ||
73 | i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL); | ||
74 | i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c"); | ||
75 | |||
76 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
77 | NULL); | ||
78 | sysbus_realize_and_unref(s, &error_fatal); | ||
79 | sysbus_mmio_map(s, 0, MP_AUDIO_BASE); | ||
80 | - sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]); | ||
81 | + sysbus_connect_irq(s, 0, qdev_get_gpio_in(pic, MP_AUDIO_IRQ)); | ||
82 | |||
83 | musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; | ||
84 | arm_load_kernel(cpu, machine, &musicpal_binfo); | ||
74 | -- | 85 | -- |
75 | 2.20.1 | 86 | 2.20.1 |
76 | 87 | ||
77 | 88 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The nseries machines have a codepath that allows them to load a | ||
2 | secondary bootloader. This code wasn't checking that the | ||
3 | load_image_targphys() succeeded. Check the return value and report | ||
4 | the error to the user. | ||
1 | 5 | ||
6 | While we're in the vicinity, fix the comment style of the | ||
7 | comment documenting what this image load is doing. | ||
8 | |||
9 | Fixes: Coverity CID 1192904 | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
12 | Message-id: 20201103114918.11807-1-peter.maydell@linaro.org | ||
13 | --- | ||
14 | hw/arm/nseries.c | 15 +++++++++++---- | ||
15 | 1 file changed, 11 insertions(+), 4 deletions(-) | ||
16 | |||
17 | diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/hw/arm/nseries.c | ||
20 | +++ b/hw/arm/nseries.c | ||
21 | @@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine, | ||
22 | /* No, wait, better start at the ROM. */ | ||
23 | s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000; | ||
24 | |||
25 | - /* This is intended for loading the `secondary.bin' program from | ||
26 | + /* | ||
27 | + * This is intended for loading the `secondary.bin' program from | ||
28 | * Nokia images (the NOLO bootloader). The entry point seems | ||
29 | * to be at OMAP2_Q2_BASE + 0x400000. | ||
30 | * | ||
31 | @@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine, | ||
32 | * for them the entry point needs to be set to OMAP2_SRAM_BASE. | ||
33 | * | ||
34 | * The code above is for loading the `zImage' file from Nokia | ||
35 | - * images. */ | ||
36 | - load_image_targphys(option_rom[0].name, OMAP2_Q2_BASE + 0x400000, | ||
37 | - machine->ram_size - 0x400000); | ||
38 | + * images. | ||
39 | + */ | ||
40 | + if (load_image_targphys(option_rom[0].name, | ||
41 | + OMAP2_Q2_BASE + 0x400000, | ||
42 | + machine->ram_size - 0x400000) < 0) { | ||
43 | + error_report("Failed to load secondary bootloader %s", | ||
44 | + option_rom[0].name); | ||
45 | + exit(EXIT_FAILURE); | ||
46 | + } | ||
47 | |||
48 | n800_setup_nolo_tags(nolo_tags); | ||
49 | cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000); | ||
50 | -- | ||
51 | 2.20.1 | ||
52 | |||
53 | diff view generated by jsdifflib |
1 | From: Alexander Graf <graf@amazon.com> | 1 | From: Havard Skinnemoen <hskinnemoen@google.com> |
---|---|---|---|
2 | 2 | ||
3 | The current PL031 RTCICR register implementation always clears the | 3 | The number of runs is equal to the number of 0-1 and 1-0 transitions, |
4 | IRQ pending status on a register write, regardless of the value the | 4 | plus one. Currently, it's counting the number of times these transitions |
5 | guest writes. | 5 | do _not_ happen, plus one. |
6 | 6 | ||
7 | To justify that behavior, it references the ARM926EJ-S Development | 7 | Source: |
8 | Chip Reference Manual (DDI0287B) and indicates that said document | 8 | https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-22r1a.pdf |
9 | states that any write clears the internal IRQ state. It is indeed | 9 | section 2.3.4 point (3). |
10 | true that in section 11.1 this document says: | ||
11 | 10 | ||
12 | "The interrupt is cleared by writing any data value to the | 11 | Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> |
13 | interrupt clear register RTCICR". | 12 | Message-id: 20201103011457.2959989-2-hskinnemoen@google.com |
14 | |||
15 | However, later in section 11.2.2 it contradicts itself by saying: | ||
16 | |||
17 | "Writing 1 to bit 0 of RTCICR clears the RTCINTR flag." | ||
18 | |||
19 | The latter statement matches the PL031 TRM (DDI0224C), which says: | ||
20 | |||
21 | "Writing 1 to bit position 0 clears the corresponding interrupt. | ||
22 | Writing 0 has no effect." | ||
23 | |||
24 | Let's assume that the self-contradictory DDI0287B is in error, and | ||
25 | follow the reference manual for the device itself, by making the | ||
26 | register write-one-to-clear. | ||
27 | |||
28 | Reported-by: Hendrik Borghorst <hborghor@amazon.de> | ||
29 | Signed-off-by: Alexander Graf <graf@amazon.com> | ||
30 | Message-id: 20191104115228.30745-1-graf@amazon.com | ||
31 | [PMM: updated commit message to note that DDI0287B says two | ||
32 | conflicting things] | ||
33 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
34 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
35 | --- | 15 | --- |
36 | hw/rtc/pl031.c | 6 +----- | 16 | tests/qtest/npcm7xx_rng-test.c | 2 +- |
37 | 1 file changed, 1 insertion(+), 5 deletions(-) | 17 | 1 file changed, 1 insertion(+), 1 deletion(-) |
38 | 18 | ||
39 | diff --git a/hw/rtc/pl031.c b/hw/rtc/pl031.c | 19 | diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c |
40 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
41 | --- a/hw/rtc/pl031.c | 21 | --- a/tests/qtest/npcm7xx_rng-test.c |
42 | +++ b/hw/rtc/pl031.c | 22 | +++ b/tests/qtest/npcm7xx_rng-test.c |
43 | @@ -XXX,XX +XXX,XX @@ static void pl031_write(void * opaque, hwaddr offset, | 23 | @@ -XXX,XX +XXX,XX @@ static double calc_runs_p(const unsigned long *buf, unsigned int nr_bits) |
44 | pl031_update(s); | 24 | pi = (double)nr_ones / nr_bits; |
45 | break; | 25 | |
46 | case RTC_ICR: | 26 | for (k = 0; k < nr_bits - 1; k++) { |
47 | - /* The PL031 documentation (DDI0224B) states that the interrupt is | 27 | - vn_obs += !(test_bit(k, buf) ^ test_bit(k + 1, buf)); |
48 | - cleared when bit 0 of the written value is set. However the | 28 | + vn_obs += (test_bit(k, buf) ^ test_bit(k + 1, buf)); |
49 | - arm926e documentation (DDI0287B) states that the interrupt is | 29 | } |
50 | - cleared when any value is written. */ | 30 | vn_obs += 1; |
51 | - s->is = 0; | 31 | |
52 | + s->is &= ~value; | ||
53 | pl031_update(s); | ||
54 | break; | ||
55 | case RTC_CR: | ||
56 | -- | 32 | -- |
57 | 2.20.1 | 33 | 2.20.1 |
58 | 34 | ||
59 | 35 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Checks for UNDEF cases should go before the "is VFP enabled?" access | ||
2 | check, except in special cases. Move a stray UNDEF check in the VTBL | ||
3 | trans function up above the access check. | ||
1 | 4 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20201109145324.2859-1-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/translate-neon.c.inc | 8 ++++---- | ||
10 | 1 file changed, 4 insertions(+), 4 deletions(-) | ||
11 | |||
12 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/translate-neon.c.inc | ||
15 | +++ b/target/arm/translate-neon.c.inc | ||
16 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
17 | return false; | ||
18 | } | ||
19 | |||
20 | - if (!vfp_access_check(s)) { | ||
21 | - return true; | ||
22 | - } | ||
23 | - | ||
24 | if ((a->vn + a->len + 1) > 32) { | ||
25 | /* | ||
26 | * This is UNPREDICTABLE; we choose to UNDEF to avoid the | ||
27 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
28 | return false; | ||
29 | } | ||
30 | |||
31 | + if (!vfp_access_check(s)) { | ||
32 | + return true; | ||
33 | + } | ||
34 | + | ||
35 | desc = tcg_const_i32((a->vn << 2) | a->len); | ||
36 | def = tcg_temp_new_i64(); | ||
37 | if (a->op) { | ||
38 | -- | ||
39 | 2.20.1 | ||
40 | |||
41 | diff view generated by jsdifflib |