[v1] target/i386: add PSCHANGE_NO bit for the ARCH_CAPABILITIES MSR

[PATCH] target/i386: add PSCHANGE_NO bit for the ARCH_CAPABILITIES MSR

Paolo Bonzini posted 1 patch 4 years, 5 months ago

Diff against v1
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git fetch https://github.com/patchew-project/qemu tags/patchew/20191113145446.16506-1-pbonzini@redhat.com

Maintainers: Paolo Bonzini <pbonzini@redhat.com>, Richard Henderson <rth@twiddle.net>, Eduardo Habkost <ehabkost@redhat.com>

target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

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[PATCH] target/i386: add PSCHANGE_NO bit for the ARCH_CAPABILITIES MSR

Posted by Paolo Bonzini 4 years, 5 months ago

This is required to disable ITLB multihit mitigations in nested
hypervisors.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index a624163ac2..2f60df37c4 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1204,7 +1204,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
         .type = MSR_FEATURE_WORD,
         .feat_names = {
             "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
-            "ssb-no", "mds-no", NULL, NULL,
+            "ssb-no", "mds-no", "pschange-mc-no", NULL,
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
-- 
2.21.0