1 | The following changes since commit 654efcb511d394c1d3f5292c28503d1d19e5b1d3: | 1 | The following changes since commit 40c67636f67c2a89745f2e698522fe917326a952: |
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2 | 2 | ||
3 | Merge remote-tracking branch 'remotes/vivier/tags/q800-branch-pull-request' into staging (2019-11-11 09:23:46 +0000) | 3 | Merge remote-tracking branch 'remotes/kraxel/tags/usb-20200317-pull-request' into staging (2020-03-17 14:00:56 +0000) |
4 | 4 | ||
5 | are available in the Git repository at: | 5 | are available in the Git repository at: |
6 | 6 | ||
7 | https://github.com/rth7680/qemu.git tags/pull-tcg-20191111 | 7 | https://github.com/rth7680/qemu.git tags/pull-tcg-20200317 |
8 | 8 | ||
9 | for you to fetch changes up to cb974c95df0e1c9e73a37facd3e13894bd3eedc2: | 9 | for you to fetch changes up to 0270bd503e3699b7202200a2d693ad1feb57473f: |
10 | 10 | ||
11 | tcg/LICENSE: Remove out of date claim about TCG subdirectory licensing (2019-11-11 15:11:21 +0100) | 11 | tcg: Remove tcg-runtime-gvec.c DO_CMP0 (2020-03-17 08:41:07 -0700) |
12 | 12 | ||
13 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
14 | Remove no-longer-true statement that TCG is BSD-licensed | 14 | Fix tcg/i386 bug vs sari_vec. |
15 | Fix tcg-runtime-gvec.c vs i386 without avx. | ||
15 | 16 | ||
16 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
17 | Peter Maydell (4): | 18 | Richard Henderson (5): |
18 | tcg/aarch64/tcg-target.opc.h: Add copyright/license | 19 | tcg/i386: Bound shift count expanding sari_vec |
19 | tcg/i386/tcg-target.opc.h: Add copyright/license | 20 | tcg: Remove CONFIG_VECTOR16 |
20 | tcg/ppc/tcg-target.opc.h: Add copyright/license | 21 | tcg: Tidy tcg-runtime-gvec.c types |
21 | tcg/LICENSE: Remove out of date claim about TCG subdirectory licensing | 22 | tcg: Tidy tcg-runtime-gvec.c DUP* |
23 | tcg: Remove tcg-runtime-gvec.c DO_CMP0 | ||
22 | 24 | ||
23 | tcg/aarch64/tcg-target.opc.h | 15 ++++++++++++--- | 25 | configure | 56 -------- |
24 | tcg/i386/tcg-target.opc.h | 28 +++++++++++++++++++++++++--- | 26 | accel/tcg/tcg-runtime-gvec.c | 298 +++++++++++++++++-------------------------- |
25 | tcg/ppc/tcg-target.opc.h | 20 ++++++++++++++++++++ | 27 | tcg/i386/tcg-target.inc.c | 9 +- |
26 | LICENSE | 5 +++-- | 28 | 3 files changed, 122 insertions(+), 241 deletions(-) |
27 | tcg/LICENSE | 3 --- | ||
28 | 5 files changed, 60 insertions(+), 11 deletions(-) | ||
29 | delete mode 100644 tcg/LICENSE | ||
30 | 29 | diff view generated by jsdifflib |
1 | From: Peter Maydell <peter.maydell@linaro.org> | 1 | A given RISU testcase for SVE can produce |
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2 | 2 | ||
3 | Since 2008 the tcg/LICENSE file has not changed: it claims that | 3 | tcg-op-vec.c:511: do_shifti: Assertion `i >= 0 && i < (8 << vece)' failed. |
4 | everything under tcg/ is BSD-licensed. | ||
5 | 4 | ||
6 | This is not true and hasn't been true for years: in 2013 we | 5 | because expand_vec_sari gave a shift count of 32 to a MO_32 |
7 | accepted the tcg/aarch64 target code under a GPLv2-or-later | 6 | vector shift. |
8 | license statement. We also have generic vector optimisation | ||
9 | code under the LGPL2.1-or-later, and the TCI backend is | ||
10 | GPLv2-or-later. Further, many of the files are not BSD | ||
11 | licensed but MIT licensed. | ||
12 | 7 | ||
13 | We don't really consider the tcg subdirectory to be a distinct part | 8 | In 44f1441dbe1, we changed from direct expansion of vector opcodes |
14 | of QEMU anyway. | 9 | to re-use of the tcg expanders. So while the comment correctly notes |
10 | that the hw will handle such a shift count, we now have to take our | ||
11 | own sanity checks into account. Which is easy in this particular case. | ||
15 | 12 | ||
16 | Remove the LICENSE file, since claiming false information | 13 | Fixes: 44f1441dbe1 |
17 | about the license of the code is confusing. | ||
18 | |||
19 | Update the main project LICENSE file also to be clearer about | ||
20 | the licenses used by TCG. | ||
21 | |||
22 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
24 | Message-Id: <20191025155848.17362-5-peter.maydell@linaro.org> | ||
25 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
26 | --- | 15 | --- |
27 | LICENSE | 5 +++-- | 16 | tcg/i386/tcg-target.inc.c | 9 ++++++--- |
28 | tcg/LICENSE | 3 --- | 17 | 1 file changed, 6 insertions(+), 3 deletions(-) |
29 | 2 files changed, 3 insertions(+), 5 deletions(-) | ||
30 | delete mode 100644 tcg/LICENSE | ||
31 | 18 | ||
32 | diff --git a/LICENSE b/LICENSE | 19 | diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c |
33 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
34 | --- a/LICENSE | 21 | --- a/tcg/i386/tcg-target.inc.c |
35 | +++ b/LICENSE | 22 | +++ b/tcg/i386/tcg-target.inc.c |
36 | @@ -XXX,XX +XXX,XX @@ As of July 2013, contributions under version 2 of the GNU General Public | 23 | @@ -XXX,XX +XXX,XX @@ static void expand_vec_sari(TCGType type, unsigned vece, |
37 | License (and no later version) are only accepted for the following files | 24 | |
38 | or directories: bsd-user/, linux-user/, hw/vfio/, hw/xen/xen_pt*. | 25 | case MO_64: |
39 | 26 | if (imm <= 32) { | |
40 | -3) The Tiny Code Generator (TCG) is released under the BSD license | 27 | - /* We can emulate a small sign extend by performing an arithmetic |
41 | - (see license headers in files). | 28 | + /* |
42 | +3) The Tiny Code Generator (TCG) is mostly under the BSD or MIT licenses; | 29 | + * We can emulate a small sign extend by performing an arithmetic |
43 | + but some parts may be GPLv2 or other licenses. Again, see the | 30 | * 32-bit shift and overwriting the high half of a 64-bit logical |
44 | + specific licensing information in each source file. | 31 | - * shift (note that the ISA says shift of 32 is valid). |
45 | 32 | + * shift. Note that the ISA says shift of 32 is valid, but TCG | |
46 | 4) QEMU is a trademark of Fabrice Bellard. | 33 | + * does not, so we have to bound the smaller shift -- we get the |
47 | 34 | + * same result in the high half either way. | |
48 | diff --git a/tcg/LICENSE b/tcg/LICENSE | 35 | */ |
49 | deleted file mode 100644 | 36 | t1 = tcg_temp_new_vec(type); |
50 | index XXXXXXX..XXXXXXX | 37 | - tcg_gen_sari_vec(MO_32, t1, v1, imm); |
51 | --- a/tcg/LICENSE | 38 | + tcg_gen_sari_vec(MO_32, t1, v1, MIN(imm, 31)); |
52 | +++ /dev/null | 39 | tcg_gen_shri_vec(MO_64, v0, v1, imm); |
53 | @@ -XXX,XX +XXX,XX @@ | 40 | vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32, |
54 | -All the files in this directory and subdirectories are released under | 41 | tcgv_vec_arg(v0), tcgv_vec_arg(v0), |
55 | -a BSD like license (see header in each file). No other license is | ||
56 | -accepted. | ||
57 | -- | 42 | -- |
58 | 2.17.1 | 43 | 2.20.1 |
59 | 44 | ||
60 | 45 | diff view generated by jsdifflib |
1 | From: Peter Maydell <peter.maydell@linaro.org> | 1 | The comment in tcg-runtime-gvec.c about CONFIG_VECTOR16 says that |
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2 | tcg-op-gvec.c has eliminated size 8 vectors, and only passes on | ||
3 | multiples of 16. This may have been true of the first few operations, | ||
4 | but is not true of all operations. | ||
2 | 5 | ||
3 | Add the copyright/license boilerplate for tcg/i386/tcg-target.opc.h. | 6 | In particular, multiply, shift by scalar, and compare of 8- and 16-bit |
4 | This file has had only two commits, 4b06c216826b7e4 and | 7 | elements are not expanded inline if host vector operations are not |
5 | d9897efa1fd3174ec, both by a Linaro engineer. | 8 | supported. |
6 | The license is MIT, since that's what the rest of tcg/ppc/ is. | ||
7 | 9 | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 10 | For an x86_64 host that does not support AVX, this means that we will |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | fall back to the helper, which will attempt to use SSE instructions, |
10 | Message-Id: <20191025155848.17362-4-peter.maydell@linaro.org> | 12 | which will SEGV on an invalid 8-byte aligned memory operation. |
13 | |||
14 | This patch simply removes the CONFIG_VECTOR16 code and configuration | ||
15 | without further simplification. | ||
16 | |||
17 | Buglink: https://bugs.launchpad.net/bugs/1863508 | ||
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 18 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
12 | --- | 19 | --- |
13 | tcg/ppc/tcg-target.opc.h | 20 ++++++++++++++++++++ | 20 | configure | 56 ------------------------------------ |
14 | 1 file changed, 20 insertions(+) | 21 | accel/tcg/tcg-runtime-gvec.c | 35 +--------------------- |
22 | 2 files changed, 1 insertion(+), 90 deletions(-) | ||
15 | 23 | ||
16 | diff --git a/tcg/ppc/tcg-target.opc.h b/tcg/ppc/tcg-target.opc.h | 24 | diff --git a/configure b/configure |
25 | index XXXXXXX..XXXXXXX 100755 | ||
26 | --- a/configure | ||
27 | +++ b/configure | ||
28 | @@ -XXX,XX +XXX,XX @@ if test "$plugins" = "yes" && | ||
29 | "for this purpose. You can't build with --static." | ||
30 | fi | ||
31 | |||
32 | -######################################## | ||
33 | -# See if 16-byte vector operations are supported. | ||
34 | -# Even without a vector unit the compiler may expand these. | ||
35 | -# There is a bug in old GCC for PPC that crashes here. | ||
36 | -# Unfortunately it's the system compiler for Centos 7. | ||
37 | - | ||
38 | -cat > $TMPC << EOF | ||
39 | -typedef unsigned char U1 __attribute__((vector_size(16))); | ||
40 | -typedef unsigned short U2 __attribute__((vector_size(16))); | ||
41 | -typedef unsigned int U4 __attribute__((vector_size(16))); | ||
42 | -typedef unsigned long long U8 __attribute__((vector_size(16))); | ||
43 | -typedef signed char S1 __attribute__((vector_size(16))); | ||
44 | -typedef signed short S2 __attribute__((vector_size(16))); | ||
45 | -typedef signed int S4 __attribute__((vector_size(16))); | ||
46 | -typedef signed long long S8 __attribute__((vector_size(16))); | ||
47 | -static U1 a1, b1; | ||
48 | -static U2 a2, b2; | ||
49 | -static U4 a4, b4; | ||
50 | -static U8 a8, b8; | ||
51 | -static S1 c1; | ||
52 | -static S2 c2; | ||
53 | -static S4 c4; | ||
54 | -static S8 c8; | ||
55 | -static int i; | ||
56 | -void helper(void *d, void *a, int shift, int i); | ||
57 | -void helper(void *d, void *a, int shift, int i) | ||
58 | -{ | ||
59 | - *(U1 *)(d + i) = *(U1 *)(a + i) << shift; | ||
60 | - *(U2 *)(d + i) = *(U2 *)(a + i) << shift; | ||
61 | - *(U4 *)(d + i) = *(U4 *)(a + i) << shift; | ||
62 | - *(U8 *)(d + i) = *(U8 *)(a + i) << shift; | ||
63 | -} | ||
64 | -int main(void) | ||
65 | -{ | ||
66 | - a1 += b1; a2 += b2; a4 += b4; a8 += b8; | ||
67 | - a1 -= b1; a2 -= b2; a4 -= b4; a8 -= b8; | ||
68 | - a1 *= b1; a2 *= b2; a4 *= b4; a8 *= b8; | ||
69 | - a1 &= b1; a2 &= b2; a4 &= b4; a8 &= b8; | ||
70 | - a1 |= b1; a2 |= b2; a4 |= b4; a8 |= b8; | ||
71 | - a1 ^= b1; a2 ^= b2; a4 ^= b4; a8 ^= b8; | ||
72 | - a1 <<= i; a2 <<= i; a4 <<= i; a8 <<= i; | ||
73 | - a1 >>= i; a2 >>= i; a4 >>= i; a8 >>= i; | ||
74 | - c1 >>= i; c2 >>= i; c4 >>= i; c8 >>= i; | ||
75 | - return 0; | ||
76 | -} | ||
77 | -EOF | ||
78 | - | ||
79 | -vector16=no | ||
80 | -if compile_prog "" "" ; then | ||
81 | - vector16=yes | ||
82 | -fi | ||
83 | - | ||
84 | ######################################## | ||
85 | # See if __attribute__((alias)) is supported. | ||
86 | # This false for Xcode 9, but has been remedied for Xcode 10. | ||
87 | @@ -XXX,XX +XXX,XX @@ if test "$atomic64" = "yes" ; then | ||
88 | echo "CONFIG_ATOMIC64=y" >> $config_host_mak | ||
89 | fi | ||
90 | |||
91 | -if test "$vector16" = "yes" ; then | ||
92 | - echo "CONFIG_VECTOR16=y" >> $config_host_mak | ||
93 | -fi | ||
94 | - | ||
95 | if test "$attralias" = "yes" ; then | ||
96 | echo "CONFIG_ATTRIBUTE_ALIAS=y" >> $config_host_mak | ||
97 | fi | ||
98 | diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | 99 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/tcg/ppc/tcg-target.opc.h | 100 | --- a/accel/tcg/tcg-runtime-gvec.c |
19 | +++ b/tcg/ppc/tcg-target.opc.h | 101 | +++ b/accel/tcg/tcg-runtime-gvec.c |
20 | @@ -XXX,XX +XXX,XX @@ | 102 | @@ -XXX,XX +XXX,XX @@ |
21 | /* | 103 | #include "tcg/tcg-gvec-desc.h" |
22 | + * Copyright (c) 2019 Linaro Limited | 104 | |
23 | + * | 105 | |
24 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | 106 | -/* Virtually all hosts support 16-byte vectors. Those that don't can emulate |
25 | + * of this software and associated documentation files (the "Software"), to deal | 107 | - * them via GCC's generic vector extension. This turns out to be simpler and |
26 | + * in the Software without restriction, including without limitation the rights | 108 | - * more reliable than getting the compiler to autovectorize. |
27 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | 109 | - * |
28 | + * copies of the Software, and to permit persons to whom the Software is | 110 | - * In tcg-op-gvec.c, we asserted that both the size and alignment of the data |
29 | + * furnished to do so, subject to the following conditions: | 111 | - * are multiples of 16. |
30 | + * | 112 | - * |
31 | + * The above copyright notice and this permission notice shall be included in | 113 | - * When the compiler does not support all of the operations we require, the |
32 | + * all copies or substantial portions of the Software. | 114 | - * loops are written so that we can always fall back on the base types. |
33 | + * | 115 | - */ |
34 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | 116 | -#ifdef CONFIG_VECTOR16 |
35 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | 117 | -typedef uint8_t vec8 __attribute__((vector_size(16))); |
36 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | 118 | -typedef uint16_t vec16 __attribute__((vector_size(16))); |
37 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | 119 | -typedef uint32_t vec32 __attribute__((vector_size(16))); |
38 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | 120 | -typedef uint64_t vec64 __attribute__((vector_size(16))); |
39 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | 121 | - |
40 | + * THE SOFTWARE. | 122 | -typedef int8_t svec8 __attribute__((vector_size(16))); |
41 | + * | 123 | -typedef int16_t svec16 __attribute__((vector_size(16))); |
42 | * Target-specific opcodes for host vector expansion. These will be | 124 | -typedef int32_t svec32 __attribute__((vector_size(16))); |
43 | * emitted by tcg_expand_vec_op. For those familiar with GCC internals, | 125 | -typedef int64_t svec64 __attribute__((vector_size(16))); |
44 | * consider these to be UNSPEC with names. | 126 | - |
127 | -#define DUP16(X) { X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X } | ||
128 | -#define DUP8(X) { X, X, X, X, X, X, X, X } | ||
129 | -#define DUP4(X) { X, X, X, X } | ||
130 | -#define DUP2(X) { X, X } | ||
131 | -#else | ||
132 | typedef uint8_t vec8; | ||
133 | typedef uint16_t vec16; | ||
134 | typedef uint32_t vec32; | ||
135 | @@ -XXX,XX +XXX,XX @@ typedef int64_t svec64; | ||
136 | #define DUP8(X) X | ||
137 | #define DUP4(X) X | ||
138 | #define DUP2(X) X | ||
139 | -#endif /* CONFIG_VECTOR16 */ | ||
140 | |||
141 | static inline void clear_high(void *d, intptr_t oprsz, uint32_t desc) | ||
142 | { | ||
143 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sar64v)(void *d, void *a, void *b, uint32_t desc) | ||
144 | clear_high(d, oprsz, desc); | ||
145 | } | ||
146 | |||
147 | -/* If vectors are enabled, the compiler fills in -1 for true. | ||
148 | - Otherwise, we must take care of this by hand. */ | ||
149 | -#ifdef CONFIG_VECTOR16 | ||
150 | -# define DO_CMP0(X) X | ||
151 | -#else | ||
152 | -# define DO_CMP0(X) -(X) | ||
153 | -#endif | ||
154 | +#define DO_CMP0(X) -(X) | ||
155 | |||
156 | #define DO_CMP1(NAME, TYPE, OP) \ | ||
157 | void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) \ | ||
45 | -- | 158 | -- |
46 | 2.17.1 | 159 | 2.20.1 |
47 | 160 | ||
48 | 161 | diff view generated by jsdifflib |
1 | From: Peter Maydell <peter.maydell@linaro.org> | 1 | Partial cleanup from the CONFIG_VECTOR16 removal. |
---|---|---|---|
2 | Replace the vec* types with their scalar expansions. | ||
2 | 3 | ||
3 | Add the copyright/license boilerplate for tcg/i386/tcg-target.opc.h. | 4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
4 | This file has had only one commit, 770c2fc7bb70804a, by | ||
5 | a Linaro engineer. | ||
6 | The license is MIT, since that's what the rest of tcg/i386/ is. | ||
7 | |||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Message-Id: <20191025155848.17362-3-peter.maydell@linaro.org> | ||
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
12 | --- | 6 | --- |
13 | tcg/i386/tcg-target.opc.h | 28 +++++++++++++++++++++++++--- | 7 | accel/tcg/tcg-runtime-gvec.c | 270 +++++++++++++++++------------------ |
14 | 1 file changed, 25 insertions(+), 3 deletions(-) | 8 | 1 file changed, 130 insertions(+), 140 deletions(-) |
15 | 9 | ||
16 | diff --git a/tcg/i386/tcg-target.opc.h b/tcg/i386/tcg-target.opc.h | 10 | diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c |
17 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/tcg/i386/tcg-target.opc.h | 12 | --- a/accel/tcg/tcg-runtime-gvec.c |
19 | +++ b/tcg/i386/tcg-target.opc.h | 13 | +++ b/accel/tcg/tcg-runtime-gvec.c |
20 | @@ -XXX,XX +XXX,XX @@ | 14 | @@ -XXX,XX +XXX,XX @@ |
21 | -/* Target-specific opcodes for host vector expansion. These will be | 15 | #include "tcg/tcg-gvec-desc.h" |
22 | - emitted by tcg_expand_vec_op. For those familiar with GCC internals, | 16 | |
23 | - consider these to be UNSPEC with names. */ | 17 | |
24 | +/* | 18 | -typedef uint8_t vec8; |
25 | + * Copyright (c) 2019 Linaro | 19 | -typedef uint16_t vec16; |
26 | + * | 20 | -typedef uint32_t vec32; |
27 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | 21 | -typedef uint64_t vec64; |
28 | + * of this software and associated documentation files (the "Software"), to deal | 22 | - |
29 | + * in the Software without restriction, including without limitation the rights | 23 | -typedef int8_t svec8; |
30 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | 24 | -typedef int16_t svec16; |
31 | + * copies of the Software, and to permit persons to whom the Software is | 25 | -typedef int32_t svec32; |
32 | + * furnished to do so, subject to the following conditions: | 26 | -typedef int64_t svec64; |
33 | + * | 27 | - |
34 | + * The above copyright notice and this permission notice shall be included in | 28 | #define DUP16(X) X |
35 | + * all copies or substantial portions of the Software. | 29 | #define DUP8(X) X |
36 | + * | 30 | #define DUP4(X) X |
37 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | 31 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_add8)(void *d, void *a, void *b, uint32_t desc) |
38 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | 32 | intptr_t oprsz = simd_oprsz(desc); |
39 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | 33 | intptr_t i; |
40 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | 34 | |
41 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | 35 | - for (i = 0; i < oprsz; i += sizeof(vec8)) { |
42 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | 36 | - *(vec8 *)(d + i) = *(vec8 *)(a + i) + *(vec8 *)(b + i); |
43 | + * THE SOFTWARE. | 37 | + for (i = 0; i < oprsz; i += sizeof(uint8_t)) { |
44 | + * | 38 | + *(uint8_t *)(d + i) = *(uint8_t *)(a + i) + *(uint8_t *)(b + i); |
45 | + * Target-specific opcodes for host vector expansion. These will be | 39 | } |
46 | + * emitted by tcg_expand_vec_op. For those familiar with GCC internals, | 40 | clear_high(d, oprsz, desc); |
47 | + * consider these to be UNSPEC with names. | 41 | } |
48 | + */ | 42 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_add16)(void *d, void *a, void *b, uint32_t desc) |
49 | 43 | intptr_t oprsz = simd_oprsz(desc); | |
50 | DEF(x86_shufps_vec, 1, 2, 1, IMPLVEC) | 44 | intptr_t i; |
51 | DEF(x86_vpblendvb_vec, 1, 3, 0, IMPLVEC) | 45 | |
46 | - for (i = 0; i < oprsz; i += sizeof(vec16)) { | ||
47 | - *(vec16 *)(d + i) = *(vec16 *)(a + i) + *(vec16 *)(b + i); | ||
48 | + for (i = 0; i < oprsz; i += sizeof(uint16_t)) { | ||
49 | + *(uint16_t *)(d + i) = *(uint16_t *)(a + i) + *(uint16_t *)(b + i); | ||
50 | } | ||
51 | clear_high(d, oprsz, desc); | ||
52 | } | ||
53 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_add32)(void *d, void *a, void *b, uint32_t desc) | ||
54 | intptr_t oprsz = simd_oprsz(desc); | ||
55 | intptr_t i; | ||
56 | |||
57 | - for (i = 0; i < oprsz; i += sizeof(vec32)) { | ||
58 | - *(vec32 *)(d + i) = *(vec32 *)(a + i) + *(vec32 *)(b + i); | ||
59 | + for (i = 0; i < oprsz; i += sizeof(uint32_t)) { | ||
60 | + *(uint32_t *)(d + i) = *(uint32_t *)(a + i) + *(uint32_t *)(b + i); | ||
61 | } | ||
62 | clear_high(d, oprsz, desc); | ||
63 | } | ||
64 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_add64)(void *d, void *a, void *b, uint32_t desc) | ||
65 | intptr_t oprsz = simd_oprsz(desc); | ||
66 | intptr_t i; | ||
67 | |||
68 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
69 | - *(vec64 *)(d + i) = *(vec64 *)(a + i) + *(vec64 *)(b + i); | ||
70 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
71 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) + *(uint64_t *)(b + i); | ||
72 | } | ||
73 | clear_high(d, oprsz, desc); | ||
74 | } | ||
75 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_add64)(void *d, void *a, void *b, uint32_t desc) | ||
76 | void HELPER(gvec_adds8)(void *d, void *a, uint64_t b, uint32_t desc) | ||
77 | { | ||
78 | intptr_t oprsz = simd_oprsz(desc); | ||
79 | - vec8 vecb = (vec8)DUP16(b); | ||
80 | + uint8_t vecb = (uint8_t)DUP16(b); | ||
81 | intptr_t i; | ||
82 | |||
83 | - for (i = 0; i < oprsz; i += sizeof(vec8)) { | ||
84 | - *(vec8 *)(d + i) = *(vec8 *)(a + i) + vecb; | ||
85 | + for (i = 0; i < oprsz; i += sizeof(uint8_t)) { | ||
86 | + *(uint8_t *)(d + i) = *(uint8_t *)(a + i) + vecb; | ||
87 | } | ||
88 | clear_high(d, oprsz, desc); | ||
89 | } | ||
90 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_adds8)(void *d, void *a, uint64_t b, uint32_t desc) | ||
91 | void HELPER(gvec_adds16)(void *d, void *a, uint64_t b, uint32_t desc) | ||
92 | { | ||
93 | intptr_t oprsz = simd_oprsz(desc); | ||
94 | - vec16 vecb = (vec16)DUP8(b); | ||
95 | + uint16_t vecb = (uint16_t)DUP8(b); | ||
96 | intptr_t i; | ||
97 | |||
98 | - for (i = 0; i < oprsz; i += sizeof(vec16)) { | ||
99 | - *(vec16 *)(d + i) = *(vec16 *)(a + i) + vecb; | ||
100 | + for (i = 0; i < oprsz; i += sizeof(uint16_t)) { | ||
101 | + *(uint16_t *)(d + i) = *(uint16_t *)(a + i) + vecb; | ||
102 | } | ||
103 | clear_high(d, oprsz, desc); | ||
104 | } | ||
105 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_adds16)(void *d, void *a, uint64_t b, uint32_t desc) | ||
106 | void HELPER(gvec_adds32)(void *d, void *a, uint64_t b, uint32_t desc) | ||
107 | { | ||
108 | intptr_t oprsz = simd_oprsz(desc); | ||
109 | - vec32 vecb = (vec32)DUP4(b); | ||
110 | + uint32_t vecb = (uint32_t)DUP4(b); | ||
111 | intptr_t i; | ||
112 | |||
113 | - for (i = 0; i < oprsz; i += sizeof(vec32)) { | ||
114 | - *(vec32 *)(d + i) = *(vec32 *)(a + i) + vecb; | ||
115 | + for (i = 0; i < oprsz; i += sizeof(uint32_t)) { | ||
116 | + *(uint32_t *)(d + i) = *(uint32_t *)(a + i) + vecb; | ||
117 | } | ||
118 | clear_high(d, oprsz, desc); | ||
119 | } | ||
120 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_adds32)(void *d, void *a, uint64_t b, uint32_t desc) | ||
121 | void HELPER(gvec_adds64)(void *d, void *a, uint64_t b, uint32_t desc) | ||
122 | { | ||
123 | intptr_t oprsz = simd_oprsz(desc); | ||
124 | - vec64 vecb = (vec64)DUP2(b); | ||
125 | + uint64_t vecb = (uint64_t)DUP2(b); | ||
126 | intptr_t i; | ||
127 | |||
128 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
129 | - *(vec64 *)(d + i) = *(vec64 *)(a + i) + vecb; | ||
130 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
131 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) + vecb; | ||
132 | } | ||
133 | clear_high(d, oprsz, desc); | ||
134 | } | ||
135 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sub8)(void *d, void *a, void *b, uint32_t desc) | ||
136 | intptr_t oprsz = simd_oprsz(desc); | ||
137 | intptr_t i; | ||
138 | |||
139 | - for (i = 0; i < oprsz; i += sizeof(vec8)) { | ||
140 | - *(vec8 *)(d + i) = *(vec8 *)(a + i) - *(vec8 *)(b + i); | ||
141 | + for (i = 0; i < oprsz; i += sizeof(uint8_t)) { | ||
142 | + *(uint8_t *)(d + i) = *(uint8_t *)(a + i) - *(uint8_t *)(b + i); | ||
143 | } | ||
144 | clear_high(d, oprsz, desc); | ||
145 | } | ||
146 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sub16)(void *d, void *a, void *b, uint32_t desc) | ||
147 | intptr_t oprsz = simd_oprsz(desc); | ||
148 | intptr_t i; | ||
149 | |||
150 | - for (i = 0; i < oprsz; i += sizeof(vec16)) { | ||
151 | - *(vec16 *)(d + i) = *(vec16 *)(a + i) - *(vec16 *)(b + i); | ||
152 | + for (i = 0; i < oprsz; i += sizeof(uint16_t)) { | ||
153 | + *(uint16_t *)(d + i) = *(uint16_t *)(a + i) - *(uint16_t *)(b + i); | ||
154 | } | ||
155 | clear_high(d, oprsz, desc); | ||
156 | } | ||
157 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sub32)(void *d, void *a, void *b, uint32_t desc) | ||
158 | intptr_t oprsz = simd_oprsz(desc); | ||
159 | intptr_t i; | ||
160 | |||
161 | - for (i = 0; i < oprsz; i += sizeof(vec32)) { | ||
162 | - *(vec32 *)(d + i) = *(vec32 *)(a + i) - *(vec32 *)(b + i); | ||
163 | + for (i = 0; i < oprsz; i += sizeof(uint32_t)) { | ||
164 | + *(uint32_t *)(d + i) = *(uint32_t *)(a + i) - *(uint32_t *)(b + i); | ||
165 | } | ||
166 | clear_high(d, oprsz, desc); | ||
167 | } | ||
168 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sub64)(void *d, void *a, void *b, uint32_t desc) | ||
169 | intptr_t oprsz = simd_oprsz(desc); | ||
170 | intptr_t i; | ||
171 | |||
172 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
173 | - *(vec64 *)(d + i) = *(vec64 *)(a + i) - *(vec64 *)(b + i); | ||
174 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
175 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) - *(uint64_t *)(b + i); | ||
176 | } | ||
177 | clear_high(d, oprsz, desc); | ||
178 | } | ||
179 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sub64)(void *d, void *a, void *b, uint32_t desc) | ||
180 | void HELPER(gvec_subs8)(void *d, void *a, uint64_t b, uint32_t desc) | ||
181 | { | ||
182 | intptr_t oprsz = simd_oprsz(desc); | ||
183 | - vec8 vecb = (vec8)DUP16(b); | ||
184 | + uint8_t vecb = (uint8_t)DUP16(b); | ||
185 | intptr_t i; | ||
186 | |||
187 | - for (i = 0; i < oprsz; i += sizeof(vec8)) { | ||
188 | - *(vec8 *)(d + i) = *(vec8 *)(a + i) - vecb; | ||
189 | + for (i = 0; i < oprsz; i += sizeof(uint8_t)) { | ||
190 | + *(uint8_t *)(d + i) = *(uint8_t *)(a + i) - vecb; | ||
191 | } | ||
192 | clear_high(d, oprsz, desc); | ||
193 | } | ||
194 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_subs8)(void *d, void *a, uint64_t b, uint32_t desc) | ||
195 | void HELPER(gvec_subs16)(void *d, void *a, uint64_t b, uint32_t desc) | ||
196 | { | ||
197 | intptr_t oprsz = simd_oprsz(desc); | ||
198 | - vec16 vecb = (vec16)DUP8(b); | ||
199 | + uint16_t vecb = (uint16_t)DUP8(b); | ||
200 | intptr_t i; | ||
201 | |||
202 | - for (i = 0; i < oprsz; i += sizeof(vec16)) { | ||
203 | - *(vec16 *)(d + i) = *(vec16 *)(a + i) - vecb; | ||
204 | + for (i = 0; i < oprsz; i += sizeof(uint16_t)) { | ||
205 | + *(uint16_t *)(d + i) = *(uint16_t *)(a + i) - vecb; | ||
206 | } | ||
207 | clear_high(d, oprsz, desc); | ||
208 | } | ||
209 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_subs16)(void *d, void *a, uint64_t b, uint32_t desc) | ||
210 | void HELPER(gvec_subs32)(void *d, void *a, uint64_t b, uint32_t desc) | ||
211 | { | ||
212 | intptr_t oprsz = simd_oprsz(desc); | ||
213 | - vec32 vecb = (vec32)DUP4(b); | ||
214 | + uint32_t vecb = (uint32_t)DUP4(b); | ||
215 | intptr_t i; | ||
216 | |||
217 | - for (i = 0; i < oprsz; i += sizeof(vec32)) { | ||
218 | - *(vec32 *)(d + i) = *(vec32 *)(a + i) - vecb; | ||
219 | + for (i = 0; i < oprsz; i += sizeof(uint32_t)) { | ||
220 | + *(uint32_t *)(d + i) = *(uint32_t *)(a + i) - vecb; | ||
221 | } | ||
222 | clear_high(d, oprsz, desc); | ||
223 | } | ||
224 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_subs32)(void *d, void *a, uint64_t b, uint32_t desc) | ||
225 | void HELPER(gvec_subs64)(void *d, void *a, uint64_t b, uint32_t desc) | ||
226 | { | ||
227 | intptr_t oprsz = simd_oprsz(desc); | ||
228 | - vec64 vecb = (vec64)DUP2(b); | ||
229 | + uint64_t vecb = (uint64_t)DUP2(b); | ||
230 | intptr_t i; | ||
231 | |||
232 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
233 | - *(vec64 *)(d + i) = *(vec64 *)(a + i) - vecb; | ||
234 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
235 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) - vecb; | ||
236 | } | ||
237 | clear_high(d, oprsz, desc); | ||
238 | } | ||
239 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_mul8)(void *d, void *a, void *b, uint32_t desc) | ||
240 | intptr_t oprsz = simd_oprsz(desc); | ||
241 | intptr_t i; | ||
242 | |||
243 | - for (i = 0; i < oprsz; i += sizeof(vec8)) { | ||
244 | - *(vec8 *)(d + i) = *(vec8 *)(a + i) * *(vec8 *)(b + i); | ||
245 | + for (i = 0; i < oprsz; i += sizeof(uint8_t)) { | ||
246 | + *(uint8_t *)(d + i) = *(uint8_t *)(a + i) * *(uint8_t *)(b + i); | ||
247 | } | ||
248 | clear_high(d, oprsz, desc); | ||
249 | } | ||
250 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_mul16)(void *d, void *a, void *b, uint32_t desc) | ||
251 | intptr_t oprsz = simd_oprsz(desc); | ||
252 | intptr_t i; | ||
253 | |||
254 | - for (i = 0; i < oprsz; i += sizeof(vec16)) { | ||
255 | - *(vec16 *)(d + i) = *(vec16 *)(a + i) * *(vec16 *)(b + i); | ||
256 | + for (i = 0; i < oprsz; i += sizeof(uint16_t)) { | ||
257 | + *(uint16_t *)(d + i) = *(uint16_t *)(a + i) * *(uint16_t *)(b + i); | ||
258 | } | ||
259 | clear_high(d, oprsz, desc); | ||
260 | } | ||
261 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_mul32)(void *d, void *a, void *b, uint32_t desc) | ||
262 | intptr_t oprsz = simd_oprsz(desc); | ||
263 | intptr_t i; | ||
264 | |||
265 | - for (i = 0; i < oprsz; i += sizeof(vec32)) { | ||
266 | - *(vec32 *)(d + i) = *(vec32 *)(a + i) * *(vec32 *)(b + i); | ||
267 | + for (i = 0; i < oprsz; i += sizeof(uint32_t)) { | ||
268 | + *(uint32_t *)(d + i) = *(uint32_t *)(a + i) * *(uint32_t *)(b + i); | ||
269 | } | ||
270 | clear_high(d, oprsz, desc); | ||
271 | } | ||
272 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_mul64)(void *d, void *a, void *b, uint32_t desc) | ||
273 | intptr_t oprsz = simd_oprsz(desc); | ||
274 | intptr_t i; | ||
275 | |||
276 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
277 | - *(vec64 *)(d + i) = *(vec64 *)(a + i) * *(vec64 *)(b + i); | ||
278 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
279 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) * *(uint64_t *)(b + i); | ||
280 | } | ||
281 | clear_high(d, oprsz, desc); | ||
282 | } | ||
283 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_mul64)(void *d, void *a, void *b, uint32_t desc) | ||
284 | void HELPER(gvec_muls8)(void *d, void *a, uint64_t b, uint32_t desc) | ||
285 | { | ||
286 | intptr_t oprsz = simd_oprsz(desc); | ||
287 | - vec8 vecb = (vec8)DUP16(b); | ||
288 | + uint8_t vecb = (uint8_t)DUP16(b); | ||
289 | intptr_t i; | ||
290 | |||
291 | - for (i = 0; i < oprsz; i += sizeof(vec8)) { | ||
292 | - *(vec8 *)(d + i) = *(vec8 *)(a + i) * vecb; | ||
293 | + for (i = 0; i < oprsz; i += sizeof(uint8_t)) { | ||
294 | + *(uint8_t *)(d + i) = *(uint8_t *)(a + i) * vecb; | ||
295 | } | ||
296 | clear_high(d, oprsz, desc); | ||
297 | } | ||
298 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_muls8)(void *d, void *a, uint64_t b, uint32_t desc) | ||
299 | void HELPER(gvec_muls16)(void *d, void *a, uint64_t b, uint32_t desc) | ||
300 | { | ||
301 | intptr_t oprsz = simd_oprsz(desc); | ||
302 | - vec16 vecb = (vec16)DUP8(b); | ||
303 | + uint16_t vecb = (uint16_t)DUP8(b); | ||
304 | intptr_t i; | ||
305 | |||
306 | - for (i = 0; i < oprsz; i += sizeof(vec16)) { | ||
307 | - *(vec16 *)(d + i) = *(vec16 *)(a + i) * vecb; | ||
308 | + for (i = 0; i < oprsz; i += sizeof(uint16_t)) { | ||
309 | + *(uint16_t *)(d + i) = *(uint16_t *)(a + i) * vecb; | ||
310 | } | ||
311 | clear_high(d, oprsz, desc); | ||
312 | } | ||
313 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_muls16)(void *d, void *a, uint64_t b, uint32_t desc) | ||
314 | void HELPER(gvec_muls32)(void *d, void *a, uint64_t b, uint32_t desc) | ||
315 | { | ||
316 | intptr_t oprsz = simd_oprsz(desc); | ||
317 | - vec32 vecb = (vec32)DUP4(b); | ||
318 | + uint32_t vecb = (uint32_t)DUP4(b); | ||
319 | intptr_t i; | ||
320 | |||
321 | - for (i = 0; i < oprsz; i += sizeof(vec32)) { | ||
322 | - *(vec32 *)(d + i) = *(vec32 *)(a + i) * vecb; | ||
323 | + for (i = 0; i < oprsz; i += sizeof(uint32_t)) { | ||
324 | + *(uint32_t *)(d + i) = *(uint32_t *)(a + i) * vecb; | ||
325 | } | ||
326 | clear_high(d, oprsz, desc); | ||
327 | } | ||
328 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_muls32)(void *d, void *a, uint64_t b, uint32_t desc) | ||
329 | void HELPER(gvec_muls64)(void *d, void *a, uint64_t b, uint32_t desc) | ||
330 | { | ||
331 | intptr_t oprsz = simd_oprsz(desc); | ||
332 | - vec64 vecb = (vec64)DUP2(b); | ||
333 | + uint64_t vecb = (uint64_t)DUP2(b); | ||
334 | intptr_t i; | ||
335 | |||
336 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
337 | - *(vec64 *)(d + i) = *(vec64 *)(a + i) * vecb; | ||
338 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
339 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) * vecb; | ||
340 | } | ||
341 | clear_high(d, oprsz, desc); | ||
342 | } | ||
343 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_neg8)(void *d, void *a, uint32_t desc) | ||
344 | intptr_t oprsz = simd_oprsz(desc); | ||
345 | intptr_t i; | ||
346 | |||
347 | - for (i = 0; i < oprsz; i += sizeof(vec8)) { | ||
348 | - *(vec8 *)(d + i) = -*(vec8 *)(a + i); | ||
349 | + for (i = 0; i < oprsz; i += sizeof(uint8_t)) { | ||
350 | + *(uint8_t *)(d + i) = -*(uint8_t *)(a + i); | ||
351 | } | ||
352 | clear_high(d, oprsz, desc); | ||
353 | } | ||
354 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_neg16)(void *d, void *a, uint32_t desc) | ||
355 | intptr_t oprsz = simd_oprsz(desc); | ||
356 | intptr_t i; | ||
357 | |||
358 | - for (i = 0; i < oprsz; i += sizeof(vec16)) { | ||
359 | - *(vec16 *)(d + i) = -*(vec16 *)(a + i); | ||
360 | + for (i = 0; i < oprsz; i += sizeof(uint16_t)) { | ||
361 | + *(uint16_t *)(d + i) = -*(uint16_t *)(a + i); | ||
362 | } | ||
363 | clear_high(d, oprsz, desc); | ||
364 | } | ||
365 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_neg32)(void *d, void *a, uint32_t desc) | ||
366 | intptr_t oprsz = simd_oprsz(desc); | ||
367 | intptr_t i; | ||
368 | |||
369 | - for (i = 0; i < oprsz; i += sizeof(vec32)) { | ||
370 | - *(vec32 *)(d + i) = -*(vec32 *)(a + i); | ||
371 | + for (i = 0; i < oprsz; i += sizeof(uint32_t)) { | ||
372 | + *(uint32_t *)(d + i) = -*(uint32_t *)(a + i); | ||
373 | } | ||
374 | clear_high(d, oprsz, desc); | ||
375 | } | ||
376 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_neg64)(void *d, void *a, uint32_t desc) | ||
377 | intptr_t oprsz = simd_oprsz(desc); | ||
378 | intptr_t i; | ||
379 | |||
380 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
381 | - *(vec64 *)(d + i) = -*(vec64 *)(a + i); | ||
382 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
383 | + *(uint64_t *)(d + i) = -*(uint64_t *)(a + i); | ||
384 | } | ||
385 | clear_high(d, oprsz, desc); | ||
386 | } | ||
387 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_not)(void *d, void *a, uint32_t desc) | ||
388 | intptr_t oprsz = simd_oprsz(desc); | ||
389 | intptr_t i; | ||
390 | |||
391 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
392 | - *(vec64 *)(d + i) = ~*(vec64 *)(a + i); | ||
393 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
394 | + *(uint64_t *)(d + i) = ~*(uint64_t *)(a + i); | ||
395 | } | ||
396 | clear_high(d, oprsz, desc); | ||
397 | } | ||
398 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_and)(void *d, void *a, void *b, uint32_t desc) | ||
399 | intptr_t oprsz = simd_oprsz(desc); | ||
400 | intptr_t i; | ||
401 | |||
402 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
403 | - *(vec64 *)(d + i) = *(vec64 *)(a + i) & *(vec64 *)(b + i); | ||
404 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
405 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) & *(uint64_t *)(b + i); | ||
406 | } | ||
407 | clear_high(d, oprsz, desc); | ||
408 | } | ||
409 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_or)(void *d, void *a, void *b, uint32_t desc) | ||
410 | intptr_t oprsz = simd_oprsz(desc); | ||
411 | intptr_t i; | ||
412 | |||
413 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
414 | - *(vec64 *)(d + i) = *(vec64 *)(a + i) | *(vec64 *)(b + i); | ||
415 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
416 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) | *(uint64_t *)(b + i); | ||
417 | } | ||
418 | clear_high(d, oprsz, desc); | ||
419 | } | ||
420 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_xor)(void *d, void *a, void *b, uint32_t desc) | ||
421 | intptr_t oprsz = simd_oprsz(desc); | ||
422 | intptr_t i; | ||
423 | |||
424 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
425 | - *(vec64 *)(d + i) = *(vec64 *)(a + i) ^ *(vec64 *)(b + i); | ||
426 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
427 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) ^ *(uint64_t *)(b + i); | ||
428 | } | ||
429 | clear_high(d, oprsz, desc); | ||
430 | } | ||
431 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_andc)(void *d, void *a, void *b, uint32_t desc) | ||
432 | intptr_t oprsz = simd_oprsz(desc); | ||
433 | intptr_t i; | ||
434 | |||
435 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
436 | - *(vec64 *)(d + i) = *(vec64 *)(a + i) &~ *(vec64 *)(b + i); | ||
437 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
438 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) &~ *(uint64_t *)(b + i); | ||
439 | } | ||
440 | clear_high(d, oprsz, desc); | ||
441 | } | ||
442 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_orc)(void *d, void *a, void *b, uint32_t desc) | ||
443 | intptr_t oprsz = simd_oprsz(desc); | ||
444 | intptr_t i; | ||
445 | |||
446 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
447 | - *(vec64 *)(d + i) = *(vec64 *)(a + i) |~ *(vec64 *)(b + i); | ||
448 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
449 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) |~ *(uint64_t *)(b + i); | ||
450 | } | ||
451 | clear_high(d, oprsz, desc); | ||
452 | } | ||
453 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_nand)(void *d, void *a, void *b, uint32_t desc) | ||
454 | intptr_t oprsz = simd_oprsz(desc); | ||
455 | intptr_t i; | ||
456 | |||
457 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
458 | - *(vec64 *)(d + i) = ~(*(vec64 *)(a + i) & *(vec64 *)(b + i)); | ||
459 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
460 | + *(uint64_t *)(d + i) = ~(*(uint64_t *)(a + i) & *(uint64_t *)(b + i)); | ||
461 | } | ||
462 | clear_high(d, oprsz, desc); | ||
463 | } | ||
464 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_nor)(void *d, void *a, void *b, uint32_t desc) | ||
465 | intptr_t oprsz = simd_oprsz(desc); | ||
466 | intptr_t i; | ||
467 | |||
468 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
469 | - *(vec64 *)(d + i) = ~(*(vec64 *)(a + i) | *(vec64 *)(b + i)); | ||
470 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
471 | + *(uint64_t *)(d + i) = ~(*(uint64_t *)(a + i) | *(uint64_t *)(b + i)); | ||
472 | } | ||
473 | clear_high(d, oprsz, desc); | ||
474 | } | ||
475 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_eqv)(void *d, void *a, void *b, uint32_t desc) | ||
476 | intptr_t oprsz = simd_oprsz(desc); | ||
477 | intptr_t i; | ||
478 | |||
479 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
480 | - *(vec64 *)(d + i) = ~(*(vec64 *)(a + i) ^ *(vec64 *)(b + i)); | ||
481 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
482 | + *(uint64_t *)(d + i) = ~(*(uint64_t *)(a + i) ^ *(uint64_t *)(b + i)); | ||
483 | } | ||
484 | clear_high(d, oprsz, desc); | ||
485 | } | ||
486 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_eqv)(void *d, void *a, void *b, uint32_t desc) | ||
487 | void HELPER(gvec_ands)(void *d, void *a, uint64_t b, uint32_t desc) | ||
488 | { | ||
489 | intptr_t oprsz = simd_oprsz(desc); | ||
490 | - vec64 vecb = (vec64)DUP2(b); | ||
491 | + uint64_t vecb = (uint64_t)DUP2(b); | ||
492 | intptr_t i; | ||
493 | |||
494 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
495 | - *(vec64 *)(d + i) = *(vec64 *)(a + i) & vecb; | ||
496 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
497 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) & vecb; | ||
498 | } | ||
499 | clear_high(d, oprsz, desc); | ||
500 | } | ||
501 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_ands)(void *d, void *a, uint64_t b, uint32_t desc) | ||
502 | void HELPER(gvec_xors)(void *d, void *a, uint64_t b, uint32_t desc) | ||
503 | { | ||
504 | intptr_t oprsz = simd_oprsz(desc); | ||
505 | - vec64 vecb = (vec64)DUP2(b); | ||
506 | + uint64_t vecb = (uint64_t)DUP2(b); | ||
507 | intptr_t i; | ||
508 | |||
509 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
510 | - *(vec64 *)(d + i) = *(vec64 *)(a + i) ^ vecb; | ||
511 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
512 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) ^ vecb; | ||
513 | } | ||
514 | clear_high(d, oprsz, desc); | ||
515 | } | ||
516 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_xors)(void *d, void *a, uint64_t b, uint32_t desc) | ||
517 | void HELPER(gvec_ors)(void *d, void *a, uint64_t b, uint32_t desc) | ||
518 | { | ||
519 | intptr_t oprsz = simd_oprsz(desc); | ||
520 | - vec64 vecb = (vec64)DUP2(b); | ||
521 | + uint64_t vecb = (uint64_t)DUP2(b); | ||
522 | intptr_t i; | ||
523 | |||
524 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
525 | - *(vec64 *)(d + i) = *(vec64 *)(a + i) | vecb; | ||
526 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
527 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) | vecb; | ||
528 | } | ||
529 | clear_high(d, oprsz, desc); | ||
530 | } | ||
531 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_shl8i)(void *d, void *a, uint32_t desc) | ||
532 | int shift = simd_data(desc); | ||
533 | intptr_t i; | ||
534 | |||
535 | - for (i = 0; i < oprsz; i += sizeof(vec8)) { | ||
536 | - *(vec8 *)(d + i) = *(vec8 *)(a + i) << shift; | ||
537 | + for (i = 0; i < oprsz; i += sizeof(uint8_t)) { | ||
538 | + *(uint8_t *)(d + i) = *(uint8_t *)(a + i) << shift; | ||
539 | } | ||
540 | clear_high(d, oprsz, desc); | ||
541 | } | ||
542 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_shl16i)(void *d, void *a, uint32_t desc) | ||
543 | int shift = simd_data(desc); | ||
544 | intptr_t i; | ||
545 | |||
546 | - for (i = 0; i < oprsz; i += sizeof(vec16)) { | ||
547 | - *(vec16 *)(d + i) = *(vec16 *)(a + i) << shift; | ||
548 | + for (i = 0; i < oprsz; i += sizeof(uint16_t)) { | ||
549 | + *(uint16_t *)(d + i) = *(uint16_t *)(a + i) << shift; | ||
550 | } | ||
551 | clear_high(d, oprsz, desc); | ||
552 | } | ||
553 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_shl32i)(void *d, void *a, uint32_t desc) | ||
554 | int shift = simd_data(desc); | ||
555 | intptr_t i; | ||
556 | |||
557 | - for (i = 0; i < oprsz; i += sizeof(vec32)) { | ||
558 | - *(vec32 *)(d + i) = *(vec32 *)(a + i) << shift; | ||
559 | + for (i = 0; i < oprsz; i += sizeof(uint32_t)) { | ||
560 | + *(uint32_t *)(d + i) = *(uint32_t *)(a + i) << shift; | ||
561 | } | ||
562 | clear_high(d, oprsz, desc); | ||
563 | } | ||
564 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_shl64i)(void *d, void *a, uint32_t desc) | ||
565 | int shift = simd_data(desc); | ||
566 | intptr_t i; | ||
567 | |||
568 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
569 | - *(vec64 *)(d + i) = *(vec64 *)(a + i) << shift; | ||
570 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
571 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) << shift; | ||
572 | } | ||
573 | clear_high(d, oprsz, desc); | ||
574 | } | ||
575 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_shr8i)(void *d, void *a, uint32_t desc) | ||
576 | int shift = simd_data(desc); | ||
577 | intptr_t i; | ||
578 | |||
579 | - for (i = 0; i < oprsz; i += sizeof(vec8)) { | ||
580 | - *(vec8 *)(d + i) = *(vec8 *)(a + i) >> shift; | ||
581 | + for (i = 0; i < oprsz; i += sizeof(uint8_t)) { | ||
582 | + *(uint8_t *)(d + i) = *(uint8_t *)(a + i) >> shift; | ||
583 | } | ||
584 | clear_high(d, oprsz, desc); | ||
585 | } | ||
586 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_shr16i)(void *d, void *a, uint32_t desc) | ||
587 | int shift = simd_data(desc); | ||
588 | intptr_t i; | ||
589 | |||
590 | - for (i = 0; i < oprsz; i += sizeof(vec16)) { | ||
591 | - *(vec16 *)(d + i) = *(vec16 *)(a + i) >> shift; | ||
592 | + for (i = 0; i < oprsz; i += sizeof(uint16_t)) { | ||
593 | + *(uint16_t *)(d + i) = *(uint16_t *)(a + i) >> shift; | ||
594 | } | ||
595 | clear_high(d, oprsz, desc); | ||
596 | } | ||
597 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_shr32i)(void *d, void *a, uint32_t desc) | ||
598 | int shift = simd_data(desc); | ||
599 | intptr_t i; | ||
600 | |||
601 | - for (i = 0; i < oprsz; i += sizeof(vec32)) { | ||
602 | - *(vec32 *)(d + i) = *(vec32 *)(a + i) >> shift; | ||
603 | + for (i = 0; i < oprsz; i += sizeof(uint32_t)) { | ||
604 | + *(uint32_t *)(d + i) = *(uint32_t *)(a + i) >> shift; | ||
605 | } | ||
606 | clear_high(d, oprsz, desc); | ||
607 | } | ||
608 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_shr64i)(void *d, void *a, uint32_t desc) | ||
609 | int shift = simd_data(desc); | ||
610 | intptr_t i; | ||
611 | |||
612 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
613 | - *(vec64 *)(d + i) = *(vec64 *)(a + i) >> shift; | ||
614 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
615 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) >> shift; | ||
616 | } | ||
617 | clear_high(d, oprsz, desc); | ||
618 | } | ||
619 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sar8i)(void *d, void *a, uint32_t desc) | ||
620 | int shift = simd_data(desc); | ||
621 | intptr_t i; | ||
622 | |||
623 | - for (i = 0; i < oprsz; i += sizeof(vec8)) { | ||
624 | - *(svec8 *)(d + i) = *(svec8 *)(a + i) >> shift; | ||
625 | + for (i = 0; i < oprsz; i += sizeof(uint8_t)) { | ||
626 | + *(int8_t *)(d + i) = *(int8_t *)(a + i) >> shift; | ||
627 | } | ||
628 | clear_high(d, oprsz, desc); | ||
629 | } | ||
630 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sar16i)(void *d, void *a, uint32_t desc) | ||
631 | int shift = simd_data(desc); | ||
632 | intptr_t i; | ||
633 | |||
634 | - for (i = 0; i < oprsz; i += sizeof(vec16)) { | ||
635 | - *(svec16 *)(d + i) = *(svec16 *)(a + i) >> shift; | ||
636 | + for (i = 0; i < oprsz; i += sizeof(uint16_t)) { | ||
637 | + *(int16_t *)(d + i) = *(int16_t *)(a + i) >> shift; | ||
638 | } | ||
639 | clear_high(d, oprsz, desc); | ||
640 | } | ||
641 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sar32i)(void *d, void *a, uint32_t desc) | ||
642 | int shift = simd_data(desc); | ||
643 | intptr_t i; | ||
644 | |||
645 | - for (i = 0; i < oprsz; i += sizeof(vec32)) { | ||
646 | - *(svec32 *)(d + i) = *(svec32 *)(a + i) >> shift; | ||
647 | + for (i = 0; i < oprsz; i += sizeof(uint32_t)) { | ||
648 | + *(int32_t *)(d + i) = *(int32_t *)(a + i) >> shift; | ||
649 | } | ||
650 | clear_high(d, oprsz, desc); | ||
651 | } | ||
652 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sar64i)(void *d, void *a, uint32_t desc) | ||
653 | int shift = simd_data(desc); | ||
654 | intptr_t i; | ||
655 | |||
656 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
657 | - *(svec64 *)(d + i) = *(svec64 *)(a + i) >> shift; | ||
658 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
659 | + *(int64_t *)(d + i) = *(int64_t *)(a + i) >> shift; | ||
660 | } | ||
661 | clear_high(d, oprsz, desc); | ||
662 | } | ||
663 | @@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) \ | ||
664 | } | ||
665 | |||
666 | #define DO_CMP2(SZ) \ | ||
667 | - DO_CMP1(gvec_eq##SZ, vec##SZ, ==) \ | ||
668 | - DO_CMP1(gvec_ne##SZ, vec##SZ, !=) \ | ||
669 | - DO_CMP1(gvec_lt##SZ, svec##SZ, <) \ | ||
670 | - DO_CMP1(gvec_le##SZ, svec##SZ, <=) \ | ||
671 | - DO_CMP1(gvec_ltu##SZ, vec##SZ, <) \ | ||
672 | - DO_CMP1(gvec_leu##SZ, vec##SZ, <=) | ||
673 | + DO_CMP1(gvec_eq##SZ, uint##SZ##_t, ==) \ | ||
674 | + DO_CMP1(gvec_ne##SZ, uint##SZ##_t, !=) \ | ||
675 | + DO_CMP1(gvec_lt##SZ, int##SZ##_t, <) \ | ||
676 | + DO_CMP1(gvec_le##SZ, int##SZ##_t, <=) \ | ||
677 | + DO_CMP1(gvec_ltu##SZ, uint##SZ##_t, <) \ | ||
678 | + DO_CMP1(gvec_leu##SZ, uint##SZ##_t, <=) | ||
679 | |||
680 | DO_CMP2(8) | ||
681 | DO_CMP2(16) | ||
682 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_bitsel)(void *d, void *a, void *b, void *c, uint32_t desc) | ||
683 | intptr_t oprsz = simd_oprsz(desc); | ||
684 | intptr_t i; | ||
685 | |||
686 | - for (i = 0; i < oprsz; i += sizeof(vec64)) { | ||
687 | - vec64 aa = *(vec64 *)(a + i); | ||
688 | - vec64 bb = *(vec64 *)(b + i); | ||
689 | - vec64 cc = *(vec64 *)(c + i); | ||
690 | - *(vec64 *)(d + i) = (bb & aa) | (cc & ~aa); | ||
691 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
692 | + uint64_t aa = *(uint64_t *)(a + i); | ||
693 | + uint64_t bb = *(uint64_t *)(b + i); | ||
694 | + uint64_t cc = *(uint64_t *)(c + i); | ||
695 | + *(uint64_t *)(d + i) = (bb & aa) | (cc & ~aa); | ||
696 | } | ||
697 | clear_high(d, oprsz, desc); | ||
698 | } | ||
52 | -- | 699 | -- |
53 | 2.17.1 | 700 | 2.20.1 |
54 | 701 | ||
55 | 702 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | Partial cleanup from the CONFIG_VECTOR16 removal. | |
2 | Replace the DUP* expansions with the scalar argument. | ||
3 | |||
4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | ||
7 | accel/tcg/tcg-runtime-gvec.c | 50 +++++++++++------------------------- | ||
8 | 1 file changed, 15 insertions(+), 35 deletions(-) | ||
9 | |||
10 | diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/accel/tcg/tcg-runtime-gvec.c | ||
13 | +++ b/accel/tcg/tcg-runtime-gvec.c | ||
14 | @@ -XXX,XX +XXX,XX @@ | ||
15 | #include "tcg/tcg-gvec-desc.h" | ||
16 | |||
17 | |||
18 | -#define DUP16(X) X | ||
19 | -#define DUP8(X) X | ||
20 | -#define DUP4(X) X | ||
21 | -#define DUP2(X) X | ||
22 | - | ||
23 | static inline void clear_high(void *d, intptr_t oprsz, uint32_t desc) | ||
24 | { | ||
25 | intptr_t maxsz = simd_maxsz(desc); | ||
26 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_add64)(void *d, void *a, void *b, uint32_t desc) | ||
27 | void HELPER(gvec_adds8)(void *d, void *a, uint64_t b, uint32_t desc) | ||
28 | { | ||
29 | intptr_t oprsz = simd_oprsz(desc); | ||
30 | - uint8_t vecb = (uint8_t)DUP16(b); | ||
31 | intptr_t i; | ||
32 | |||
33 | for (i = 0; i < oprsz; i += sizeof(uint8_t)) { | ||
34 | - *(uint8_t *)(d + i) = *(uint8_t *)(a + i) + vecb; | ||
35 | + *(uint8_t *)(d + i) = *(uint8_t *)(a + i) + (uint8_t)b; | ||
36 | } | ||
37 | clear_high(d, oprsz, desc); | ||
38 | } | ||
39 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_adds8)(void *d, void *a, uint64_t b, uint32_t desc) | ||
40 | void HELPER(gvec_adds16)(void *d, void *a, uint64_t b, uint32_t desc) | ||
41 | { | ||
42 | intptr_t oprsz = simd_oprsz(desc); | ||
43 | - uint16_t vecb = (uint16_t)DUP8(b); | ||
44 | intptr_t i; | ||
45 | |||
46 | for (i = 0; i < oprsz; i += sizeof(uint16_t)) { | ||
47 | - *(uint16_t *)(d + i) = *(uint16_t *)(a + i) + vecb; | ||
48 | + *(uint16_t *)(d + i) = *(uint16_t *)(a + i) + (uint16_t)b; | ||
49 | } | ||
50 | clear_high(d, oprsz, desc); | ||
51 | } | ||
52 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_adds16)(void *d, void *a, uint64_t b, uint32_t desc) | ||
53 | void HELPER(gvec_adds32)(void *d, void *a, uint64_t b, uint32_t desc) | ||
54 | { | ||
55 | intptr_t oprsz = simd_oprsz(desc); | ||
56 | - uint32_t vecb = (uint32_t)DUP4(b); | ||
57 | intptr_t i; | ||
58 | |||
59 | for (i = 0; i < oprsz; i += sizeof(uint32_t)) { | ||
60 | - *(uint32_t *)(d + i) = *(uint32_t *)(a + i) + vecb; | ||
61 | + *(uint32_t *)(d + i) = *(uint32_t *)(a + i) + (uint32_t)b; | ||
62 | } | ||
63 | clear_high(d, oprsz, desc); | ||
64 | } | ||
65 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_adds32)(void *d, void *a, uint64_t b, uint32_t desc) | ||
66 | void HELPER(gvec_adds64)(void *d, void *a, uint64_t b, uint32_t desc) | ||
67 | { | ||
68 | intptr_t oprsz = simd_oprsz(desc); | ||
69 | - uint64_t vecb = (uint64_t)DUP2(b); | ||
70 | intptr_t i; | ||
71 | |||
72 | for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
73 | - *(uint64_t *)(d + i) = *(uint64_t *)(a + i) + vecb; | ||
74 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) + b; | ||
75 | } | ||
76 | clear_high(d, oprsz, desc); | ||
77 | } | ||
78 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sub64)(void *d, void *a, void *b, uint32_t desc) | ||
79 | void HELPER(gvec_subs8)(void *d, void *a, uint64_t b, uint32_t desc) | ||
80 | { | ||
81 | intptr_t oprsz = simd_oprsz(desc); | ||
82 | - uint8_t vecb = (uint8_t)DUP16(b); | ||
83 | intptr_t i; | ||
84 | |||
85 | for (i = 0; i < oprsz; i += sizeof(uint8_t)) { | ||
86 | - *(uint8_t *)(d + i) = *(uint8_t *)(a + i) - vecb; | ||
87 | + *(uint8_t *)(d + i) = *(uint8_t *)(a + i) - (uint8_t)b; | ||
88 | } | ||
89 | clear_high(d, oprsz, desc); | ||
90 | } | ||
91 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_subs8)(void *d, void *a, uint64_t b, uint32_t desc) | ||
92 | void HELPER(gvec_subs16)(void *d, void *a, uint64_t b, uint32_t desc) | ||
93 | { | ||
94 | intptr_t oprsz = simd_oprsz(desc); | ||
95 | - uint16_t vecb = (uint16_t)DUP8(b); | ||
96 | intptr_t i; | ||
97 | |||
98 | for (i = 0; i < oprsz; i += sizeof(uint16_t)) { | ||
99 | - *(uint16_t *)(d + i) = *(uint16_t *)(a + i) - vecb; | ||
100 | + *(uint16_t *)(d + i) = *(uint16_t *)(a + i) - (uint16_t)b; | ||
101 | } | ||
102 | clear_high(d, oprsz, desc); | ||
103 | } | ||
104 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_subs16)(void *d, void *a, uint64_t b, uint32_t desc) | ||
105 | void HELPER(gvec_subs32)(void *d, void *a, uint64_t b, uint32_t desc) | ||
106 | { | ||
107 | intptr_t oprsz = simd_oprsz(desc); | ||
108 | - uint32_t vecb = (uint32_t)DUP4(b); | ||
109 | intptr_t i; | ||
110 | |||
111 | for (i = 0; i < oprsz; i += sizeof(uint32_t)) { | ||
112 | - *(uint32_t *)(d + i) = *(uint32_t *)(a + i) - vecb; | ||
113 | + *(uint32_t *)(d + i) = *(uint32_t *)(a + i) - (uint32_t)b; | ||
114 | } | ||
115 | clear_high(d, oprsz, desc); | ||
116 | } | ||
117 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_subs32)(void *d, void *a, uint64_t b, uint32_t desc) | ||
118 | void HELPER(gvec_subs64)(void *d, void *a, uint64_t b, uint32_t desc) | ||
119 | { | ||
120 | intptr_t oprsz = simd_oprsz(desc); | ||
121 | - uint64_t vecb = (uint64_t)DUP2(b); | ||
122 | intptr_t i; | ||
123 | |||
124 | for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
125 | - *(uint64_t *)(d + i) = *(uint64_t *)(a + i) - vecb; | ||
126 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) - b; | ||
127 | } | ||
128 | clear_high(d, oprsz, desc); | ||
129 | } | ||
130 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_mul64)(void *d, void *a, void *b, uint32_t desc) | ||
131 | void HELPER(gvec_muls8)(void *d, void *a, uint64_t b, uint32_t desc) | ||
132 | { | ||
133 | intptr_t oprsz = simd_oprsz(desc); | ||
134 | - uint8_t vecb = (uint8_t)DUP16(b); | ||
135 | intptr_t i; | ||
136 | |||
137 | for (i = 0; i < oprsz; i += sizeof(uint8_t)) { | ||
138 | - *(uint8_t *)(d + i) = *(uint8_t *)(a + i) * vecb; | ||
139 | + *(uint8_t *)(d + i) = *(uint8_t *)(a + i) * (uint8_t)b; | ||
140 | } | ||
141 | clear_high(d, oprsz, desc); | ||
142 | } | ||
143 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_muls8)(void *d, void *a, uint64_t b, uint32_t desc) | ||
144 | void HELPER(gvec_muls16)(void *d, void *a, uint64_t b, uint32_t desc) | ||
145 | { | ||
146 | intptr_t oprsz = simd_oprsz(desc); | ||
147 | - uint16_t vecb = (uint16_t)DUP8(b); | ||
148 | intptr_t i; | ||
149 | |||
150 | for (i = 0; i < oprsz; i += sizeof(uint16_t)) { | ||
151 | - *(uint16_t *)(d + i) = *(uint16_t *)(a + i) * vecb; | ||
152 | + *(uint16_t *)(d + i) = *(uint16_t *)(a + i) * (uint16_t)b; | ||
153 | } | ||
154 | clear_high(d, oprsz, desc); | ||
155 | } | ||
156 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_muls16)(void *d, void *a, uint64_t b, uint32_t desc) | ||
157 | void HELPER(gvec_muls32)(void *d, void *a, uint64_t b, uint32_t desc) | ||
158 | { | ||
159 | intptr_t oprsz = simd_oprsz(desc); | ||
160 | - uint32_t vecb = (uint32_t)DUP4(b); | ||
161 | intptr_t i; | ||
162 | |||
163 | for (i = 0; i < oprsz; i += sizeof(uint32_t)) { | ||
164 | - *(uint32_t *)(d + i) = *(uint32_t *)(a + i) * vecb; | ||
165 | + *(uint32_t *)(d + i) = *(uint32_t *)(a + i) * (uint32_t)b; | ||
166 | } | ||
167 | clear_high(d, oprsz, desc); | ||
168 | } | ||
169 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_muls32)(void *d, void *a, uint64_t b, uint32_t desc) | ||
170 | void HELPER(gvec_muls64)(void *d, void *a, uint64_t b, uint32_t desc) | ||
171 | { | ||
172 | intptr_t oprsz = simd_oprsz(desc); | ||
173 | - uint64_t vecb = (uint64_t)DUP2(b); | ||
174 | intptr_t i; | ||
175 | |||
176 | for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
177 | - *(uint64_t *)(d + i) = *(uint64_t *)(a + i) * vecb; | ||
178 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) * b; | ||
179 | } | ||
180 | clear_high(d, oprsz, desc); | ||
181 | } | ||
182 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_eqv)(void *d, void *a, void *b, uint32_t desc) | ||
183 | void HELPER(gvec_ands)(void *d, void *a, uint64_t b, uint32_t desc) | ||
184 | { | ||
185 | intptr_t oprsz = simd_oprsz(desc); | ||
186 | - uint64_t vecb = (uint64_t)DUP2(b); | ||
187 | intptr_t i; | ||
188 | |||
189 | for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
190 | - *(uint64_t *)(d + i) = *(uint64_t *)(a + i) & vecb; | ||
191 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) & b; | ||
192 | } | ||
193 | clear_high(d, oprsz, desc); | ||
194 | } | ||
195 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_ands)(void *d, void *a, uint64_t b, uint32_t desc) | ||
196 | void HELPER(gvec_xors)(void *d, void *a, uint64_t b, uint32_t desc) | ||
197 | { | ||
198 | intptr_t oprsz = simd_oprsz(desc); | ||
199 | - uint64_t vecb = (uint64_t)DUP2(b); | ||
200 | intptr_t i; | ||
201 | |||
202 | for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
203 | - *(uint64_t *)(d + i) = *(uint64_t *)(a + i) ^ vecb; | ||
204 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) ^ b; | ||
205 | } | ||
206 | clear_high(d, oprsz, desc); | ||
207 | } | ||
208 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_xors)(void *d, void *a, uint64_t b, uint32_t desc) | ||
209 | void HELPER(gvec_ors)(void *d, void *a, uint64_t b, uint32_t desc) | ||
210 | { | ||
211 | intptr_t oprsz = simd_oprsz(desc); | ||
212 | - uint64_t vecb = (uint64_t)DUP2(b); | ||
213 | intptr_t i; | ||
214 | |||
215 | for (i = 0; i < oprsz; i += sizeof(uint64_t)) { | ||
216 | - *(uint64_t *)(d + i) = *(uint64_t *)(a + i) | vecb; | ||
217 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) | b; | ||
218 | } | ||
219 | clear_high(d, oprsz, desc); | ||
220 | } | ||
221 | -- | ||
222 | 2.20.1 | ||
223 | |||
224 | diff view generated by jsdifflib |
1 | From: Peter Maydell <peter.maydell@linaro.org> | 1 | Partial cleanup from the CONFIG_VECTOR16 removal. |
---|---|---|---|
2 | Replace DO_CMP0 with its scalar expansion, a simple negation. | ||
2 | 3 | ||
3 | Add the copyright/license boilerplate for target/aarch64/tcg-target.opc.h. | ||
4 | This file has only had two commits: 14e4c1e2355473ccb29 | ||
5 | and 79525dfd08262d8, both by the same Linaro engineer. | ||
6 | The license is GPL-2-or-later, since that's what the | ||
7 | rest of tcg/aarch64 uses. | ||
8 | |||
9 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Message-Id: <20191025155848.17362-2-peter.maydell@linaro.org> | ||
13 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
14 | --- | 5 | --- |
15 | tcg/aarch64/tcg-target.opc.h | 15 ++++++++++++--- | 6 | accel/tcg/tcg-runtime-gvec.c | 5 +---- |
16 | 1 file changed, 12 insertions(+), 3 deletions(-) | 7 | 1 file changed, 1 insertion(+), 4 deletions(-) |
17 | 8 | ||
18 | diff --git a/tcg/aarch64/tcg-target.opc.h b/tcg/aarch64/tcg-target.opc.h | 9 | diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c |
19 | index XXXXXXX..XXXXXXX 100644 | 10 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/tcg/aarch64/tcg-target.opc.h | 11 | --- a/accel/tcg/tcg-runtime-gvec.c |
21 | +++ b/tcg/aarch64/tcg-target.opc.h | 12 | +++ b/accel/tcg/tcg-runtime-gvec.c |
22 | @@ -XXX,XX +XXX,XX @@ | 13 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sar64v)(void *d, void *a, void *b, uint32_t desc) |
23 | -/* Target-specific opcodes for host vector expansion. These will be | 14 | clear_high(d, oprsz, desc); |
24 | - emitted by tcg_expand_vec_op. For those familiar with GCC internals, | 15 | } |
25 | - consider these to be UNSPEC with names. */ | 16 | |
26 | +/* | 17 | -#define DO_CMP0(X) -(X) |
27 | + * Copyright (c) 2019 Linaro | 18 | - |
28 | + * | 19 | #define DO_CMP1(NAME, TYPE, OP) \ |
29 | + * This work is licensed under the terms of the GNU GPL, version 2 or | 20 | void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) \ |
30 | + * (at your option) any later version. | 21 | { \ |
31 | + * | 22 | intptr_t oprsz = simd_oprsz(desc); \ |
32 | + * See the COPYING file in the top-level directory for details. | 23 | intptr_t i; \ |
33 | + * | 24 | for (i = 0; i < oprsz; i += sizeof(TYPE)) { \ |
34 | + * Target-specific opcodes for host vector expansion. These will be | 25 | - *(TYPE *)(d + i) = DO_CMP0(*(TYPE *)(a + i) OP *(TYPE *)(b + i)); \ |
35 | + * emitted by tcg_expand_vec_op. For those familiar with GCC internals, | 26 | + *(TYPE *)(d + i) = -(*(TYPE *)(a + i) OP *(TYPE *)(b + i)); \ |
36 | + * consider these to be UNSPEC with names. | 27 | } \ |
37 | + */ | 28 | clear_high(d, oprsz, desc); \ |
38 | 29 | } | |
39 | DEF(aa64_sshl_vec, 1, 2, 0, IMPLVEC) | 30 | @@ -XXX,XX +XXX,XX @@ DO_CMP2(16) |
31 | DO_CMP2(32) | ||
32 | DO_CMP2(64) | ||
33 | |||
34 | -#undef DO_CMP0 | ||
35 | #undef DO_CMP1 | ||
36 | #undef DO_CMP2 | ||
37 | |||
40 | -- | 38 | -- |
41 | 2.17.1 | 39 | 2.20.1 |
42 | 40 | ||
43 | 41 | diff view generated by jsdifflib |