[PULL 0/3] target-arm queue
[PULL 00/26] target-arm queue
1
Arm patches for rc1:
1
The following changes since commit 65cc5ccf06a74c98de73ec683d9a543baa302a12:
2
* two final "remove the old API" patches for some API transitions
3
* bugfix for raspi/highbank Linux boot
4
2
5
thanks
3
Merge tag 'pull-riscv-to-apply-20230120' of https://github.com/alistair23/qemu into staging (2023-01-20 16:17:56 +0000)
6
-- PMM
7
8
The following changes since commit 654efcb511d394c1d3f5292c28503d1d19e5b1d3:
9
10
Merge remote-tracking branch 'remotes/vivier/tags/q800-branch-pull-request' into staging (2019-11-11 09:23:46 +0000)
11
4
12
are available in the Git repository at:
5
are available in the Git repository at:
13
6
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191111
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230123
15
8
16
for you to fetch changes up to 45c078f163fd47c35e7505d98928fae63baada7d:
9
for you to fetch changes up to 3b07a936d3bfe97b07ddffcfbb532985a88033dd:
17
10
18
hw/arm/boot: Set NSACR.{CP11, CP10} in dummy SMC setup routine (2019-11-11 13:44:16 +0000)
11
target/arm: Look up ARMCPRegInfo at runtime (2023-01-23 13:32:38 +0000)
19
12
20
----------------------------------------------------------------
13
----------------------------------------------------------------
21
target-arm queue:
14
target-arm queue:
22
* Remove old unassigned_access CPU hook API
15
* Widen cnthctl_el2 to uint64_t
23
* Remove old ptimer_init_with_bh() API
16
* Unify checking for M Main Extension in MRS/MSR
24
* hw/arm/boot: Set NSACR.{CP11, CP10} in dummy SMC setup routine
17
* bitbang_i2c, versatile_i2c: code cleanups
18
* SME: refactor SME SM/ZA handling
19
* Fix physical address resolution for MTE
20
* Fix in_debug path in S1_ptw_translate
21
* Don't set EXC_RETURN.ES if Security Extension not present
22
* Implement DBGCLAIM registers
23
* Provide stubs for more external debug registers
24
* Look up ARMCPRegInfo at runtime, not translate time
25
25
26
----------------------------------------------------------------
26
----------------------------------------------------------------
27
Clement Deschamps (1):
27
David Reiss (1):
28
hw/arm/boot: Set NSACR.{CP11, CP10} in dummy SMC setup routine
28
target/arm: Unify checking for M Main Extension in MRS/MSR
29
29
30
Peter Maydell (2):
30
Evgeny Iakovlev (2):
31
ptimer: Remove old ptimer_init_with_bh() API
31
target/arm: implement DBGCLAIM registers
32
Remove unassigned_access CPU hook
32
target/arm: provide stubs for more external debug registers
33
33
34
include/hw/arm/boot.h | 7 ++--
34
Peter Maydell (1):
35
include/hw/core/cpu.h | 24 --------------
35
target/arm: Don't set EXC_RETURN.ES if Security Extension not present
36
include/hw/ptimer.h | 45 ++++++++++++-------------
37
accel/tcg/cputlb.c | 2 --
38
hw/arm/boot.c | 3 ++
39
hw/core/ptimer.c | 91 +++++++++------------------------------------------
40
memory.c | 7 ----
41
7 files changed, 44 insertions(+), 135 deletions(-)
42
36
37
Philippe Mathieu-Daudé (10):
38
hw/i2c/bitbang_i2c: Define TYPE_GPIO_I2C in public header
39
hw/i2c/bitbang_i2c: Remove unused dummy MemoryRegion
40
hw/i2c/bitbang_i2c: Change state calling bitbang_i2c_set_state() helper
41
hw/i2c/bitbang_i2c: Trace state changes
42
hw/i2c/bitbang_i2c: Convert DPRINTF() to trace events
43
hw/i2c/versatile_i2c: Drop useless casts from void * to pointer
44
hw/i2c/versatile_i2c: Replace VersatileI2CState -> ArmSbconI2CState
45
hw/i2c/versatile_i2c: Replace TYPE_VERSATILE_I2C -> TYPE_ARM_SBCON_I2C
46
hw/i2c/versatile_i2c: Use ARM_SBCON_I2C() macro
47
hw/i2c/versatile_i2c: Rename versatile_i2c -> arm_sbcon_i2c
48
49
Richard Henderson (12):
50
target/arm: Widen cnthctl_el2 to uint64_t
51
target/arm/sme: Reorg SME access handling in handle_msr_i()
52
target/arm/sme: Rebuild hflags in set_pstate() helpers
53
target/arm/sme: Introduce aarch64_set_svcr()
54
target/arm/sme: Reset SVE state in aarch64_set_svcr()
55
target/arm/sme: Reset ZA state in aarch64_set_svcr()
56
target/arm/sme: Rebuild hflags in aarch64_set_svcr()
57
target/arm/sme: Unify set_pstate() SM/ZA helpers as set_svcr()
58
target/arm: Fix physical address resolution for MTE
59
target/arm: Fix in_debug path in S1_ptw_translate
60
target/arm: Reorg do_coproc_insn
61
target/arm: Look up ARMCPRegInfo at runtime
62
63
MAINTAINERS | 1 +
64
include/hw/i2c/arm_sbcon_i2c.h | 6 +-
65
include/hw/i2c/bitbang_i2c.h | 2 +
66
target/arm/cpu.h | 5 +-
67
target/arm/helper-sme.h | 3 +-
68
target/arm/helper.h | 11 +-
69
target/arm/translate.h | 7 +
70
hw/arm/musicpal.c | 3 +-
71
hw/arm/realview.c | 2 +-
72
hw/arm/versatilepb.c | 2 +-
73
hw/arm/vexpress.c | 2 +-
74
hw/i2c/{versatile_i2c.c => arm_sbcon_i2c.c} | 39 ++-
75
hw/i2c/bitbang_i2c.c | 80 ++++--
76
linux-user/aarch64/cpu_loop.c | 11 +-
77
linux-user/aarch64/signal.c | 13 +-
78
target/arm/debug_helper.c | 54 ++++
79
target/arm/helper.c | 41 ++-
80
target/arm/m_helper.c | 24 +-
81
target/arm/mte_helper.c | 2 +-
82
target/arm/op_helper.c | 27 +-
83
target/arm/ptw.c | 4 +-
84
target/arm/sme_helper.c | 37 +--
85
target/arm/translate-a64.c | 68 +++--
86
target/arm/translate.c | 430 +++++++++++++++-------------
87
hw/arm/Kconfig | 4 +-
88
hw/i2c/Kconfig | 2 +-
89
hw/i2c/meson.build | 2 +-
90
hw/i2c/trace-events | 7 +
91
28 files changed, 506 insertions(+), 383 deletions(-)
92
rename hw/i2c/{versatile_i2c.c => arm_sbcon_i2c.c} (70%)
93
diff view generated by jsdifflib
New patch
[PULL 01/26] target/arm: Widen cnthctl_el2 to uint64_t
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
This is a 64-bit register on AArch64, even if the high 44 bits
4
are RES0. Because this is defined as ARM_CP_STATE_BOTH, we are
5
asserting that the cpreg field is 64-bits.
6
7
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1400
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230115171633.3171890-1-richard.henderson@linaro.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/cpu.h | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
21
};
22
uint64_t c14_cntfrq; /* Counter Frequency register */
23
uint64_t c14_cntkctl; /* Timer Control register */
24
- uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */
25
+ uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */
26
uint64_t cntvoff_el2; /* Counter Virtual Offset register */
27
ARMGenericTimer c14_timer[NUM_GTIMERS];
28
uint32_t c15_cpar; /* XScale Coprocessor Access Register */
29
--
30
2.34.1
diff view generated by jsdifflib
New patch
[PULL 02/26] target/arm: Unify checking for M Main Extension in MRS/MSR
1
From: David Reiss <dreiss@meta.com>
1
2
3
BASEPRI, FAULTMASK, and their _NS equivalents only exist on devices with
4
the Main Extension. However, the MRS instruction did not check this,
5
and the MSR instruction handled it inconsistently (warning BASEPRI, but
6
silently ignoring writes to BASEPRI_NS). Unify this behavior and always
7
warn when reading or writing any of these registers if the extension is
8
not present.
9
10
Signed-off-by: David Reiss <dreiss@meta.com>
11
Message-id: 167330628518.10497.13100425787268927786-0@git.sr.ht
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/m_helper.c | 22 ++++++++++++++++++++--
16
1 file changed, 20 insertions(+), 2 deletions(-)
17
18
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/m_helper.c
21
+++ b/target/arm/m_helper.c
22
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
23
}
24
return env->v7m.primask[M_REG_NS];
25
case 0x91: /* BASEPRI_NS */
26
+ if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
27
+ goto bad_reg;
28
+ }
29
if (!env->v7m.secure) {
30
return 0;
31
}
32
return env->v7m.basepri[M_REG_NS];
33
case 0x93: /* FAULTMASK_NS */
34
+ if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
35
+ goto bad_reg;
36
+ }
37
if (!env->v7m.secure) {
38
return 0;
39
}
40
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
41
return env->v7m.primask[env->v7m.secure];
42
case 17: /* BASEPRI */
43
case 18: /* BASEPRI_MAX */
44
+ if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
45
+ goto bad_reg;
46
+ }
47
return env->v7m.basepri[env->v7m.secure];
48
case 19: /* FAULTMASK */
49
+ if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
50
+ goto bad_reg;
51
+ }
52
return env->v7m.faultmask[env->v7m.secure];
53
default:
54
bad_reg:
55
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
56
env->v7m.primask[M_REG_NS] = val & 1;
57
return;
58
case 0x91: /* BASEPRI_NS */
59
- if (!env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_MAIN)) {
60
+ if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
61
+ goto bad_reg;
62
+ }
63
+ if (!env->v7m.secure) {
64
return;
65
}
66
env->v7m.basepri[M_REG_NS] = val & 0xff;
67
return;
68
case 0x93: /* FAULTMASK_NS */
69
- if (!env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_MAIN)) {
70
+ if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
71
+ goto bad_reg;
72
+ }
73
+ if (!env->v7m.secure) {
74
return;
75
}
76
env->v7m.faultmask[M_REG_NS] = val & 1;
77
--
78
2.34.1
diff view generated by jsdifflib
New patch
[PULL 03/26] hw/i2c/bitbang_i2c: Define TYPE_GPIO_I2C in public header
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Define TYPE_GPIO_I2C in the public "hw/i2c/bitbang_i2c.h"
4
header and use it in hw/arm/musicpal.c.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Acked-by: Corey Minyard <cminyard@mvista.com>
9
Message-id: 20230111085016.44551-2-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/i2c/bitbang_i2c.h | 2 ++
13
hw/arm/musicpal.c | 3 ++-
14
hw/i2c/bitbang_i2c.c | 1 -
15
3 files changed, 4 insertions(+), 2 deletions(-)
16
17
diff --git a/include/hw/i2c/bitbang_i2c.h b/include/hw/i2c/bitbang_i2c.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/i2c/bitbang_i2c.h
20
+++ b/include/hw/i2c/bitbang_i2c.h
21
@@ -XXX,XX +XXX,XX @@
22
23
#include "hw/i2c/i2c.h"
24
25
+#define TYPE_GPIO_I2C "gpio_i2c"
26
+
27
typedef struct bitbang_i2c_interface bitbang_i2c_interface;
28
29
#define BITBANG_I2C_SDA 0
30
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/arm/musicpal.c
33
+++ b/hw/arm/musicpal.c
34
@@ -XXX,XX +XXX,XX @@
35
#include "hw/block/flash.h"
36
#include "ui/console.h"
37
#include "hw/i2c/i2c.h"
38
+#include "hw/i2c/bitbang_i2c.h"
39
#include "hw/irq.h"
40
#include "hw/or-irq.h"
41
#include "hw/audio/wm8750.h"
42
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
43
44
dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE,
45
qdev_get_gpio_in(pic, MP_GPIO_IRQ));
46
- i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
47
+ i2c_dev = sysbus_create_simple(TYPE_GPIO_I2C, -1, NULL);
48
i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c");
49
50
lcd_dev = sysbus_create_simple(TYPE_MUSICPAL_LCD, MP_LCD_BASE, NULL);
51
diff --git a/hw/i2c/bitbang_i2c.c b/hw/i2c/bitbang_i2c.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/i2c/bitbang_i2c.c
54
+++ b/hw/i2c/bitbang_i2c.c
55
@@ -XXX,XX +XXX,XX @@ void bitbang_i2c_init(bitbang_i2c_interface *s, I2CBus *bus)
56
57
/* GPIO interface. */
58
59
-#define TYPE_GPIO_I2C "gpio_i2c"
60
OBJECT_DECLARE_SIMPLE_TYPE(GPIOI2CState, GPIO_I2C)
61
62
struct GPIOI2CState {
63
--
64
2.34.1
65
66
diff view generated by jsdifflib
New patch
[PULL 04/26] hw/i2c/bitbang_i2c: Remove unused dummy MemoryRegion
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Acked-by: Corey Minyard <cminyard@mvista.com>
6
Message-id: 20230111085016.44551-3-philmd@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
hw/i2c/bitbang_i2c.c | 7 ++-----
10
1 file changed, 2 insertions(+), 5 deletions(-)
11
12
diff --git a/hw/i2c/bitbang_i2c.c b/hw/i2c/bitbang_i2c.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/i2c/bitbang_i2c.c
15
+++ b/hw/i2c/bitbang_i2c.c
16
@@ -XXX,XX +XXX,XX @@ void bitbang_i2c_init(bitbang_i2c_interface *s, I2CBus *bus)
17
OBJECT_DECLARE_SIMPLE_TYPE(GPIOI2CState, GPIO_I2C)
18
19
struct GPIOI2CState {
20
+ /*< private >*/
21
SysBusDevice parent_obj;
22
+ /*< public >*/
23
24
- MemoryRegion dummy_iomem;
25
bitbang_i2c_interface bitbang;
26
int last_level;
27
qemu_irq out;
28
@@ -XXX,XX +XXX,XX @@ static void gpio_i2c_init(Object *obj)
29
{
30
DeviceState *dev = DEVICE(obj);
31
GPIOI2CState *s = GPIO_I2C(obj);
32
- SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
33
I2CBus *bus;
34
35
- memory_region_init(&s->dummy_iomem, obj, "gpio_i2c", 0);
36
- sysbus_init_mmio(sbd, &s->dummy_iomem);
37
-
38
bus = i2c_init_bus(dev, "i2c");
39
bitbang_i2c_init(&s->bitbang, bus);
40
41
--
42
2.34.1
43
44
diff view generated by jsdifflib
New patch
[PULL 05/26] hw/i2c/bitbang_i2c: Change state calling bitbang_i2c_set_state() helper
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Acked-by: Corey Minyard <cminyard@mvista.com>
6
Message-id: 20230111085016.44551-4-philmd@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
hw/i2c/bitbang_i2c.c | 23 +++++++++++++++--------
10
1 file changed, 15 insertions(+), 8 deletions(-)
11
12
diff --git a/hw/i2c/bitbang_i2c.c b/hw/i2c/bitbang_i2c.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/i2c/bitbang_i2c.c
15
+++ b/hw/i2c/bitbang_i2c.c
16
@@ -XXX,XX +XXX,XX @@ do { printf("bitbang_i2c: " fmt , ## __VA_ARGS__); } while (0)
17
#define DPRINTF(fmt, ...) do {} while(0)
18
#endif
19
20
+static void bitbang_i2c_set_state(bitbang_i2c_interface *i2c,
21
+ bitbang_i2c_state state)
22
+{
23
+ i2c->state = state;
24
+}
25
+
26
static void bitbang_i2c_enter_stop(bitbang_i2c_interface *i2c)
27
{
28
DPRINTF("STOP\n");
29
if (i2c->current_addr >= 0)
30
i2c_end_transfer(i2c->bus);
31
i2c->current_addr = -1;
32
- i2c->state = STOPPED;
33
+ bitbang_i2c_set_state(i2c, STOPPED);
34
}
35
36
/* Set device data pin. */
37
@@ -XXX,XX +XXX,XX @@ int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level)
38
if (level == 0) {
39
DPRINTF("START\n");
40
/* START condition. */
41
- i2c->state = SENDING_BIT7;
42
+ bitbang_i2c_set_state(i2c, SENDING_BIT7);
43
i2c->current_addr = -1;
44
} else {
45
/* STOP condition. */
46
@@ -XXX,XX +XXX,XX @@ int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level)
47
case SENDING_BIT7 ... SENDING_BIT0:
48
i2c->buffer = (i2c->buffer << 1) | data;
49
/* will end up in WAITING_FOR_ACK */
50
- i2c->state++;
51
+ bitbang_i2c_set_state(i2c, i2c->state + 1);
52
return bitbang_i2c_ret(i2c, 1);
53
54
case WAITING_FOR_ACK:
55
@@ -XXX,XX +XXX,XX @@ int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level)
56
* device we were sending to decided to NACK us).
57
*/
58
DPRINTF("Got NACK\n");
59
+ bitbang_i2c_set_state(i2c, SENT_NACK);
60
bitbang_i2c_enter_stop(i2c);
61
return bitbang_i2c_ret(i2c, 1);
62
}
63
if (i2c->current_addr & 1) {
64
- i2c->state = RECEIVING_BIT7;
65
+ bitbang_i2c_set_state(i2c, RECEIVING_BIT7);
66
} else {
67
- i2c->state = SENDING_BIT7;
68
+ bitbang_i2c_set_state(i2c, SENDING_BIT7);
69
}
70
return bitbang_i2c_ret(i2c, 0);
71
}
72
@@ -XXX,XX +XXX,XX @@ int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level)
73
case RECEIVING_BIT6 ... RECEIVING_BIT0:
74
data = i2c->buffer >> 7;
75
/* will end up in SENDING_ACK */
76
- i2c->state++;
77
+ bitbang_i2c_set_state(i2c, i2c->state + 1);
78
i2c->buffer <<= 1;
79
return bitbang_i2c_ret(i2c, data);
80
81
case SENDING_ACK:
82
- i2c->state = RECEIVING_BIT7;
83
if (data != 0) {
84
DPRINTF("NACKED\n");
85
- i2c->state = SENT_NACK;
86
+ bitbang_i2c_set_state(i2c, SENT_NACK);
87
i2c_nack(i2c->bus);
88
} else {
89
DPRINTF("ACKED\n");
90
+ bitbang_i2c_set_state(i2c, RECEIVING_BIT7);
91
}
92
return bitbang_i2c_ret(i2c, 1);
93
}
94
--
95
2.34.1
96
97
diff view generated by jsdifflib
New patch
[PULL 06/26] hw/i2c/bitbang_i2c: Trace state changes
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Trace bitbang state machine changes with trace events.
4
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Acked-by: Corey Minyard <cminyard@mvista.com>
8
Message-id: 20230111085016.44551-5-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/i2c/bitbang_i2c.c | 33 ++++++++++++++++++++++++++++-----
12
hw/i2c/trace-events | 3 +++
13
2 files changed, 31 insertions(+), 5 deletions(-)
14
15
diff --git a/hw/i2c/bitbang_i2c.c b/hw/i2c/bitbang_i2c.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/i2c/bitbang_i2c.c
18
+++ b/hw/i2c/bitbang_i2c.c
19
@@ -XXX,XX +XXX,XX @@
20
#include "hw/sysbus.h"
21
#include "qemu/module.h"
22
#include "qom/object.h"
23
+#include "trace.h"
24
25
//#define DEBUG_BITBANG_I2C
26
27
@@ -XXX,XX +XXX,XX @@ do { printf("bitbang_i2c: " fmt , ## __VA_ARGS__); } while (0)
28
#define DPRINTF(fmt, ...) do {} while(0)
29
#endif
30
31
+/* bitbang_i2c_state enum to name */
32
+static const char * const sname[] = {
33
+#define NAME(e) [e] = stringify(e)
34
+ NAME(STOPPED),
35
+ [SENDING_BIT7] = "SENDING_BIT7 (START)",
36
+ NAME(SENDING_BIT6),
37
+ NAME(SENDING_BIT5),
38
+ NAME(SENDING_BIT4),
39
+ NAME(SENDING_BIT3),
40
+ NAME(SENDING_BIT2),
41
+ NAME(SENDING_BIT1),
42
+ NAME(SENDING_BIT0),
43
+ NAME(WAITING_FOR_ACK),
44
+ [RECEIVING_BIT7] = "RECEIVING_BIT7 (ACK)",
45
+ NAME(RECEIVING_BIT6),
46
+ NAME(RECEIVING_BIT5),
47
+ NAME(RECEIVING_BIT4),
48
+ NAME(RECEIVING_BIT3),
49
+ NAME(RECEIVING_BIT2),
50
+ NAME(RECEIVING_BIT1),
51
+ NAME(RECEIVING_BIT0),
52
+ NAME(SENDING_ACK),
53
+ NAME(SENT_NACK)
54
+#undef NAME
55
+};
56
+
57
static void bitbang_i2c_set_state(bitbang_i2c_interface *i2c,
58
bitbang_i2c_state state)
59
{
60
+ trace_bitbang_i2c_state(sname[i2c->state], sname[state]);
61
i2c->state = state;
62
}
63
64
static void bitbang_i2c_enter_stop(bitbang_i2c_interface *i2c)
65
{
66
- DPRINTF("STOP\n");
67
if (i2c->current_addr >= 0)
68
i2c_end_transfer(i2c->bus);
69
i2c->current_addr = -1;
70
@@ -XXX,XX +XXX,XX @@ int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level)
71
return bitbang_i2c_nop(i2c);
72
}
73
if (level == 0) {
74
- DPRINTF("START\n");
75
/* START condition. */
76
bitbang_i2c_set_state(i2c, SENDING_BIT7);
77
i2c->current_addr = -1;
78
@@ -XXX,XX +XXX,XX @@ int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level)
79
/* NACK (either addressing a nonexistent device, or the
80
* device we were sending to decided to NACK us).
81
*/
82
- DPRINTF("Got NACK\n");
83
bitbang_i2c_set_state(i2c, SENT_NACK);
84
bitbang_i2c_enter_stop(i2c);
85
return bitbang_i2c_ret(i2c, 1);
86
@@ -XXX,XX +XXX,XX @@ int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level)
87
88
case SENDING_ACK:
89
if (data != 0) {
90
- DPRINTF("NACKED\n");
91
bitbang_i2c_set_state(i2c, SENT_NACK);
92
i2c_nack(i2c->bus);
93
} else {
94
- DPRINTF("ACKED\n");
95
bitbang_i2c_set_state(i2c, RECEIVING_BIT7);
96
}
97
return bitbang_i2c_ret(i2c, 1);
98
diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events
99
index XXXXXXX..XXXXXXX 100644
100
--- a/hw/i2c/trace-events
101
+++ b/hw/i2c/trace-events
102
@@ -XXX,XX +XXX,XX @@
103
# See docs/devel/tracing.rst for syntax documentation.
104
105
+# bitbang_i2c.c
106
+bitbang_i2c_state(const char *old_state, const char *new_state) "state %s -> %s"
107
+
108
# core.c
109
110
i2c_event(const char *event, uint8_t address) "%s(addr:0x%02x)"
111
--
112
2.34.1
113
114
diff view generated by jsdifflib
New patch
[PULL 07/26] hw/i2c/bitbang_i2c: Convert DPRINTF() to trace events
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Convert the remaining DPRINTF debug macro uses to tracepoints.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Acked-by: Corey Minyard <cminyard@mvista.com>
8
Message-id: 20230111085016.44551-6-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/i2c/bitbang_i2c.c | 18 ++++++------------
12
hw/i2c/trace-events | 4 ++++
13
2 files changed, 10 insertions(+), 12 deletions(-)
14
15
diff --git a/hw/i2c/bitbang_i2c.c b/hw/i2c/bitbang_i2c.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/i2c/bitbang_i2c.c
18
+++ b/hw/i2c/bitbang_i2c.c
19
@@ -XXX,XX +XXX,XX @@
20
#include "qom/object.h"
21
#include "trace.h"
22
23
-//#define DEBUG_BITBANG_I2C
24
-
25
-#ifdef DEBUG_BITBANG_I2C
26
-#define DPRINTF(fmt, ...) \
27
-do { printf("bitbang_i2c: " fmt , ## __VA_ARGS__); } while (0)
28
-#else
29
-#define DPRINTF(fmt, ...) do {} while(0)
30
-#endif
31
32
/* bitbang_i2c_state enum to name */
33
static const char * const sname[] = {
34
@@ -XXX,XX +XXX,XX @@ static void bitbang_i2c_enter_stop(bitbang_i2c_interface *i2c)
35
/* Set device data pin. */
36
static int bitbang_i2c_ret(bitbang_i2c_interface *i2c, int level)
37
{
38
+ trace_bitbang_i2c_data(i2c->last_clock, i2c->last_data,
39
+ i2c->device_out, level);
40
i2c->device_out = level;
41
- //DPRINTF("%d %d %d\n", i2c->last_clock, i2c->last_data, i2c->device_out);
42
+
43
return level & i2c->last_data;
44
}
45
46
@@ -XXX,XX +XXX,XX @@ int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level)
47
48
if (i2c->current_addr < 0) {
49
i2c->current_addr = i2c->buffer;
50
- DPRINTF("Address 0x%02x\n", i2c->current_addr);
51
+ trace_bitbang_i2c_addr(i2c->current_addr);
52
ret = i2c_start_transfer(i2c->bus, i2c->current_addr >> 1,
53
i2c->current_addr & 1);
54
} else {
55
- DPRINTF("Sent 0x%02x\n", i2c->buffer);
56
+ trace_bitbang_i2c_send(i2c->buffer);
57
ret = i2c_send(i2c->bus, i2c->buffer);
58
}
59
if (ret) {
60
@@ -XXX,XX +XXX,XX @@ int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level)
61
}
62
case RECEIVING_BIT7:
63
i2c->buffer = i2c_recv(i2c->bus);
64
- DPRINTF("RX byte 0x%02x\n", i2c->buffer);
65
+ trace_bitbang_i2c_recv(i2c->buffer);
66
/* Fall through... */
67
case RECEIVING_BIT6 ... RECEIVING_BIT0:
68
data = i2c->buffer >> 7;
69
diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events
70
index XXXXXXX..XXXXXXX 100644
71
--- a/hw/i2c/trace-events
72
+++ b/hw/i2c/trace-events
73
@@ -XXX,XX +XXX,XX @@
74
75
# bitbang_i2c.c
76
bitbang_i2c_state(const char *old_state, const char *new_state) "state %s -> %s"
77
+bitbang_i2c_addr(uint8_t addr) "Address 0x%02x"
78
+bitbang_i2c_send(uint8_t byte) "TX byte 0x%02x"
79
+bitbang_i2c_recv(uint8_t byte) "RX byte 0x%02x"
80
+bitbang_i2c_data(unsigned dat, unsigned clk, unsigned old_out, unsigned new_out) "dat %u clk %u out %u -> %u"
81
82
# core.c
83
84
--
85
2.34.1
86
87
diff view generated by jsdifflib
New patch
[PULL 08/26] hw/i2c/versatile_i2c: Drop useless casts from void * to pointer
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20230110082508.24038-2-philmd@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/i2c/versatile_i2c.c | 4 ++--
9
1 file changed, 2 insertions(+), 2 deletions(-)
10
11
diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/i2c/versatile_i2c.c
14
+++ b/hw/i2c/versatile_i2c.c
15
@@ -XXX,XX +XXX,XX @@ REG32(CONTROL_CLR, 4)
16
static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
17
unsigned size)
18
{
19
- VersatileI2CState *s = (VersatileI2CState *)opaque;
20
+ VersatileI2CState *s = opaque;
21
22
switch (offset) {
23
case A_CONTROL_SET:
24
@@ -XXX,XX +XXX,XX @@ static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
25
static void versatile_i2c_write(void *opaque, hwaddr offset,
26
uint64_t value, unsigned size)
27
{
28
- VersatileI2CState *s = (VersatileI2CState *)opaque;
29
+ VersatileI2CState *s = opaque;
30
31
switch (offset) {
32
case A_CONTROL_SET:
33
--
34
2.34.1
35
36
diff view generated by jsdifflib
New patch
[PULL 09/26] hw/i2c/versatile_i2c: Replace VersatileI2CState -> ArmSbconI2CState
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
In order to rename TYPE_VERSATILE_I2C as TYPE_ARM_SBCON_I2C
4
(the formal ARM naming), start renaming its state.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230110082508.24038-3-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/i2c/arm_sbcon_i2c.h | 3 +--
12
hw/i2c/versatile_i2c.c | 10 +++++-----
13
2 files changed, 6 insertions(+), 7 deletions(-)
14
15
diff --git a/include/hw/i2c/arm_sbcon_i2c.h b/include/hw/i2c/arm_sbcon_i2c.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/i2c/arm_sbcon_i2c.h
18
+++ b/include/hw/i2c/arm_sbcon_i2c.h
19
@@ -XXX,XX +XXX,XX @@
20
#define TYPE_ARM_SBCON_I2C TYPE_VERSATILE_I2C
21
22
typedef struct ArmSbconI2CState ArmSbconI2CState;
23
-DECLARE_INSTANCE_CHECKER(ArmSbconI2CState, ARM_SBCON_I2C,
24
- TYPE_ARM_SBCON_I2C)
25
+DECLARE_INSTANCE_CHECKER(ArmSbconI2CState, ARM_SBCON_I2C, TYPE_ARM_SBCON_I2C)
26
27
struct ArmSbconI2CState {
28
/*< private >*/
29
diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/i2c/versatile_i2c.c
32
+++ b/hw/i2c/versatile_i2c.c
33
@@ -XXX,XX +XXX,XX @@
34
#include "qom/object.h"
35
36
typedef ArmSbconI2CState VersatileI2CState;
37
-DECLARE_INSTANCE_CHECKER(VersatileI2CState, VERSATILE_I2C,
38
+DECLARE_INSTANCE_CHECKER(ArmSbconI2CState, VERSATILE_I2C,
39
TYPE_VERSATILE_I2C)
40
41
42
@@ -XXX,XX +XXX,XX @@ REG32(CONTROL_CLR, 4)
43
static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
44
unsigned size)
45
{
46
- VersatileI2CState *s = opaque;
47
+ ArmSbconI2CState *s = opaque;
48
49
switch (offset) {
50
case A_CONTROL_SET:
51
@@ -XXX,XX +XXX,XX @@ static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
52
static void versatile_i2c_write(void *opaque, hwaddr offset,
53
uint64_t value, unsigned size)
54
{
55
- VersatileI2CState *s = opaque;
56
+ ArmSbconI2CState *s = opaque;
57
58
switch (offset) {
59
case A_CONTROL_SET:
60
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps versatile_i2c_ops = {
61
static void versatile_i2c_init(Object *obj)
62
{
63
DeviceState *dev = DEVICE(obj);
64
- VersatileI2CState *s = VERSATILE_I2C(obj);
65
+ ArmSbconI2CState *s = VERSATILE_I2C(obj);
66
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
67
I2CBus *bus;
68
69
@@ -XXX,XX +XXX,XX @@ static void versatile_i2c_init(Object *obj)
70
static const TypeInfo versatile_i2c_info = {
71
.name = TYPE_VERSATILE_I2C,
72
.parent = TYPE_SYS_BUS_DEVICE,
73
- .instance_size = sizeof(VersatileI2CState),
74
+ .instance_size = sizeof(ArmSbconI2CState),
75
.instance_init = versatile_i2c_init,
76
};
77
78
--
79
2.34.1
80
81
diff view generated by jsdifflib
New patch
[PULL 10/26] hw/i2c/versatile_i2c: Replace TYPE_VERSATILE_I2C -> TYPE_ARM_SBCON_I2C
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20230110082508.24038-4-philmd@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
include/hw/i2c/arm_sbcon_i2c.h | 3 +--
9
hw/arm/realview.c | 2 +-
10
hw/arm/versatilepb.c | 2 +-
11
hw/arm/vexpress.c | 2 +-
12
hw/i2c/versatile_i2c.c | 4 ++--
13
5 files changed, 6 insertions(+), 7 deletions(-)
14
15
diff --git a/include/hw/i2c/arm_sbcon_i2c.h b/include/hw/i2c/arm_sbcon_i2c.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/i2c/arm_sbcon_i2c.h
18
+++ b/include/hw/i2c/arm_sbcon_i2c.h
19
@@ -XXX,XX +XXX,XX @@
20
#include "hw/i2c/bitbang_i2c.h"
21
#include "qom/object.h"
22
23
-#define TYPE_VERSATILE_I2C "versatile_i2c"
24
-#define TYPE_ARM_SBCON_I2C TYPE_VERSATILE_I2C
25
+#define TYPE_ARM_SBCON_I2C "versatile_i2c"
26
27
typedef struct ArmSbconI2CState ArmSbconI2CState;
28
DECLARE_INSTANCE_CHECKER(ArmSbconI2CState, ARM_SBCON_I2C, TYPE_ARM_SBCON_I2C)
29
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/arm/realview.c
32
+++ b/hw/arm/realview.c
33
@@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine,
34
}
35
}
36
37
- dev = sysbus_create_simple(TYPE_VERSATILE_I2C, 0x10002000, NULL);
38
+ dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, 0x10002000, NULL);
39
i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
40
i2c_slave_create_simple(i2c, "ds1338", 0x68);
41
42
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/arm/versatilepb.c
45
+++ b/hw/arm/versatilepb.c
46
@@ -XXX,XX +XXX,XX @@ static void versatile_init(MachineState *machine, int board_id)
47
/* Add PL031 Real Time Clock. */
48
sysbus_create_simple("pl031", 0x101e8000, pic[10]);
49
50
- dev = sysbus_create_simple(TYPE_VERSATILE_I2C, 0x10002000, NULL);
51
+ dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, 0x10002000, NULL);
52
i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
53
i2c_slave_create_simple(i2c, "ds1338", 0x68);
54
55
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/arm/vexpress.c
58
+++ b/hw/arm/vexpress.c
59
@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
60
sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
61
sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
62
63
- dev = sysbus_create_simple(TYPE_VERSATILE_I2C, map[VE_SERIALDVI], NULL);
64
+ dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, map[VE_SERIALDVI], NULL);
65
i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
66
i2c_slave_create_simple(i2c, "sii9022", 0x39);
67
68
diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/i2c/versatile_i2c.c
71
+++ b/hw/i2c/versatile_i2c.c
72
@@ -XXX,XX +XXX,XX @@
73
74
typedef ArmSbconI2CState VersatileI2CState;
75
DECLARE_INSTANCE_CHECKER(ArmSbconI2CState, VERSATILE_I2C,
76
- TYPE_VERSATILE_I2C)
77
+ TYPE_ARM_SBCON_I2C)
78
79
80
81
@@ -XXX,XX +XXX,XX @@ static void versatile_i2c_init(Object *obj)
82
}
83
84
static const TypeInfo versatile_i2c_info = {
85
- .name = TYPE_VERSATILE_I2C,
86
+ .name = TYPE_ARM_SBCON_I2C,
87
.parent = TYPE_SYS_BUS_DEVICE,
88
.instance_size = sizeof(ArmSbconI2CState),
89
.instance_init = versatile_i2c_init,
90
--
91
2.34.1
92
93
diff view generated by jsdifflib
New patch
[PULL 11/26] hw/i2c/versatile_i2c: Use ARM_SBCON_I2C() macro
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
ARM_SBCON_I2C() macro and ArmSbconI2CState typedef are
4
already declared via the QOM DECLARE_INSTANCE_CHECKER()
5
macro in "hw/i2c/arm_sbcon_i2c.h". Drop the VERSATILE_I2C
6
declarations from versatile_i2c.c.
7
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20230110082508.24038-5-philmd@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/i2c/versatile_i2c.c | 7 +------
14
1 file changed, 1 insertion(+), 6 deletions(-)
15
16
diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/i2c/versatile_i2c.c
19
+++ b/hw/i2c/versatile_i2c.c
20
@@ -XXX,XX +XXX,XX @@
21
#include "qemu/module.h"
22
#include "qom/object.h"
23
24
-typedef ArmSbconI2CState VersatileI2CState;
25
-DECLARE_INSTANCE_CHECKER(ArmSbconI2CState, VERSATILE_I2C,
26
- TYPE_ARM_SBCON_I2C)
27
-
28
-
29
30
REG32(CONTROL_GET, 0)
31
REG32(CONTROL_SET, 0)
32
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps versatile_i2c_ops = {
33
static void versatile_i2c_init(Object *obj)
34
{
35
DeviceState *dev = DEVICE(obj);
36
- ArmSbconI2CState *s = VERSATILE_I2C(obj);
37
+ ArmSbconI2CState *s = ARM_SBCON_I2C(obj);
38
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
39
I2CBus *bus;
40
41
--
42
2.34.1
43
44
diff view generated by jsdifflib
[PULL 1/3] ptimer: Remove old ptimer_init_with_bh() API
[PULL 12/26] hw/i2c/versatile_i2c: Rename versatile_i2c -> arm_sbcon_i2c
1
Now all the users of ptimers have converted to the transaction-based
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
API, we can remove ptimer_init_with_bh() and all the code paths
3
that are used only by bottom-half based ptimers, and tidy up the
4
documentation comments to consider the transaction-based API the
5
only possibility.
6
2
7
The code changes result from:
3
This device model started with the Versatile board, named
8
* s->bh no longer exists
4
TYPE_VERSATILE_I2C, then ended up renamed TYPE_ARM_SBCON_I2C
9
* s->callback is now always non-NULL
5
as per the official "ARM SBCon two-wire serial bus interface"
6
description from:
7
https://developer.arm.com/documentation/dui0440/b/programmer-s-reference/two-wire-serial-bus-interface--sbcon
10
8
9
Use the latter name as a better description.
10
11
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20230110082508.24038-6-philmd@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20191025142411.17085-1-peter.maydell@linaro.org
14
---
15
---
15
include/hw/ptimer.h | 45 +++++++++++-----------
16
MAINTAINERS | 1 +
16
hw/core/ptimer.c | 91 ++++++++-------------------------------------
17
hw/i2c/{versatile_i2c.c => arm_sbcon_i2c.c} | 24 ++++++++++-----------
17
2 files changed, 36 insertions(+), 100 deletions(-)
18
hw/arm/Kconfig | 4 ++--
19
hw/i2c/Kconfig | 2 +-
20
hw/i2c/meson.build | 2 +-
21
5 files changed, 17 insertions(+), 16 deletions(-)
22
rename hw/i2c/{versatile_i2c.c => arm_sbcon_i2c.c} (81%)
18
23
19
diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
24
diff --git a/MAINTAINERS b/MAINTAINERS
20
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/ptimer.h
26
--- a/MAINTAINERS
22
+++ b/include/hw/ptimer.h
27
+++ b/MAINTAINERS
23
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
24
29
L: qemu-arm@nongnu.org
25
#include "qemu/timer.h"
30
S: Maintained
26
31
F: hw/*/versatile*
27
-/* The ptimer API implements a simple periodic countdown timer.
32
+F: hw/i2c/arm_sbcon_i2c.c
28
+/*
33
F: include/hw/i2c/arm_sbcon_i2c.h
29
+ * The ptimer API implements a simple periodic countdown timer.
34
F: hw/misc/arm_sysctl.c
30
* The countdown timer has a value (which can be read and written via
35
F: docs/system/arm/versatile.rst
31
* ptimer_get_count() and ptimer_set_count()). When it is enabled
36
diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/arm_sbcon_i2c.c
32
* using ptimer_run(), the value will count downwards at the frequency
37
similarity index 81%
33
* which has been configured using ptimer_set_period() or ptimer_set_freq().
38
rename from hw/i2c/versatile_i2c.c
34
- * When it reaches zero it will trigger a QEMU bottom half handler, and
39
rename to hw/i2c/arm_sbcon_i2c.c
35
+ * When it reaches zero it will trigger a callback function, and
36
* can be set to either reload itself from a specified limit value
37
* and keep counting down, or to stop (as a one-shot timer).
38
*
39
+ * A transaction-based API is used for modifying ptimer state: all calls
40
+ * to functions which modify ptimer state must be between matched calls to
41
+ * ptimer_transaction_begin() and ptimer_transaction_commit().
42
+ * When ptimer_transaction_commit() is called it will evaluate the state
43
+ * of the timer after all the changes in the transaction, and call the
44
+ * callback if necessary. (See the ptimer_init() documentation for the full
45
+ * list of state-modifying functions and detailed semantics of the callback.)
46
+ *
47
* Forgetting to set the period/frequency (or setting it to zero) is a
48
* bug in the QEMU device and will cause warning messages to be printed
49
* to stderr when the guest attempts to enable the timer.
50
@@ -XXX,XX +XXX,XX @@
51
* ptimer_set_count() or ptimer_set_limit() will not trigger the timer
52
* (though it will cause a reload). Only a counter decrement to "0"
53
* will cause a trigger. Not compatible with NO_IMMEDIATE_TRIGGER;
54
- * ptimer_init_with_bh() will assert() that you don't set both.
55
+ * ptimer_init() will assert() that you don't set both.
56
*/
57
#define PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT (1 << 5)
58
59
@@ -XXX,XX +XXX,XX @@
60
typedef struct ptimer_state ptimer_state;
61
typedef void (*ptimer_cb)(void *opaque);
62
63
-/**
64
- * ptimer_init_with_bh - Allocate and return a new ptimer
65
- * @bh: QEMU bottom half which is run on timer expiry
66
- * @policy: PTIMER_POLICY_* bits specifying behaviour
67
- *
68
- * The ptimer returned must be freed using ptimer_free().
69
- * The ptimer takes ownership of @bh and will delete it
70
- * when the ptimer is eventually freed.
71
- */
72
-ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask);
73
-
74
/**
75
* ptimer_init - Allocate and return a new ptimer
76
* @callback: function to call on ptimer expiry
77
@@ -XXX,XX +XXX,XX @@ ptimer_state *ptimer_init(ptimer_cb callback,
78
* ptimer_free - Free a ptimer
79
* @s: timer to free
80
*
81
- * Free a ptimer created using ptimer_init_with_bh() (including
82
- * deleting the bottom half which it is using).
83
+ * Free a ptimer created using ptimer_init().
84
*/
85
void ptimer_free(ptimer_state *s);
86
87
@@ -XXX,XX +XXX,XX @@ void ptimer_transaction_commit(ptimer_state *s);
88
* may be more appropriate.
89
*
90
* This function will assert if it is called outside a
91
- * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer.
92
+ * ptimer_transaction_begin/commit block.
93
*/
94
void ptimer_set_period(ptimer_state *s, int64_t period);
95
96
@@ -XXX,XX +XXX,XX @@ void ptimer_set_period(ptimer_state *s, int64_t period);
97
* precise to fractions of a nanosecond, avoiding rounding errors.
98
*
99
* This function will assert if it is called outside a
100
- * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer.
101
+ * ptimer_transaction_begin/commit block.
102
*/
103
void ptimer_set_freq(ptimer_state *s, uint32_t freq);
104
105
@@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_limit(ptimer_state *s);
106
* reload the counter when their reload register is written to.
107
*
108
* This function will assert if it is called outside a
109
- * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer.
110
+ * ptimer_transaction_begin/commit block.
111
*/
112
void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
113
114
@@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_count(ptimer_state *s);
115
* point in the future.
116
*
117
* This function will assert if it is called outside a
118
- * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer.
119
+ * ptimer_transaction_begin/commit block.
120
*/
121
void ptimer_set_count(ptimer_state *s, uint64_t count);
122
123
@@ -XXX,XX +XXX,XX @@ void ptimer_set_count(ptimer_state *s, uint64_t count);
124
* @s: ptimer
125
* @oneshot: non-zero if this timer should only count down once
126
*
127
- * Start a ptimer counting down; when it reaches zero the bottom half
128
- * passed to ptimer_init_with_bh() will be invoked.
129
+ * Start a ptimer counting down; when it reaches zero the callback function
130
+ * passed to ptimer_init() will be invoked.
131
* If the @oneshot argument is zero,
132
* the counter value will then be reloaded from the limit and it will
133
* start counting down again. If @oneshot is non-zero, then the counter
134
* will disable itself when it reaches zero.
135
*
136
* This function will assert if it is called outside a
137
- * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer.
138
+ * ptimer_transaction_begin/commit block.
139
*/
140
void ptimer_run(ptimer_state *s, int oneshot);
141
142
@@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot);
143
* restarted.
144
*
145
* This function will assert if it is called outside a
146
- * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer.
147
+ * ptimer_transaction_begin/commit block.
148
*/
149
void ptimer_stop(ptimer_state *s);
150
151
diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c
152
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
153
--- a/hw/core/ptimer.c
41
--- a/hw/i2c/versatile_i2c.c
154
+++ b/hw/core/ptimer.c
42
+++ b/hw/i2c/arm_sbcon_i2c.c
155
@@ -XXX,XX +XXX,XX @@ struct ptimer_state
43
@@ -XXX,XX +XXX,XX @@ REG32(CONTROL_CLR, 4)
156
int64_t last_event;
44
#define SCL BIT(0)
157
int64_t next_event;
45
#define SDA BIT(1)
158
uint8_t policy_mask;
46
159
- QEMUBH *bh;
47
-static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
160
QEMUTimer *timer;
48
+static uint64_t arm_sbcon_i2c_read(void *opaque, hwaddr offset,
161
ptimer_cb callback;
49
unsigned size)
162
void *callback_opaque;
163
@@ -XXX,XX +XXX,XX @@ struct ptimer_state
164
/* Use a bottom-half routine to avoid reentrancy issues. */
165
static void ptimer_trigger(ptimer_state *s)
166
{
50
{
167
- if (s->bh) {
51
ArmSbconI2CState *s = opaque;
168
- replay_bh_schedule_event(s->bh);
52
@@ -XXX,XX +XXX,XX @@ static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
169
- }
170
- if (s->callback) {
171
- s->callback(s->callback_opaque);
172
- }
173
+ s->callback(s->callback_opaque);
174
}
175
176
static void ptimer_reload(ptimer_state *s, int delta_adjust)
177
@@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_count(ptimer_state *s)
178
179
void ptimer_set_count(ptimer_state *s, uint64_t count)
180
{
181
- assert(s->in_transaction || !s->callback);
182
+ assert(s->in_transaction);
183
s->delta = count;
184
if (s->enabled) {
185
- if (!s->callback) {
186
- s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
187
- ptimer_reload(s, 0);
188
- } else {
189
- s->need_reload = true;
190
- }
191
+ s->need_reload = true;
192
}
53
}
193
}
54
}
194
55
195
@@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot)
56
-static void versatile_i2c_write(void *opaque, hwaddr offset,
57
+static void arm_sbcon_i2c_write(void *opaque, hwaddr offset,
58
uint64_t value, unsigned size)
196
{
59
{
197
bool was_disabled = !s->enabled;
60
ArmSbconI2CState *s = opaque;
198
61
@@ -XXX,XX +XXX,XX @@ static void versatile_i2c_write(void *opaque, hwaddr offset,
199
- assert(s->in_transaction || !s->callback);
62
s->in = bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SDA, (s->out & SDA) != 0);
200
+ assert(s->in_transaction);
201
202
if (was_disabled && s->period == 0) {
203
if (!qtest_enabled()) {
204
@@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot)
205
}
206
s->enabled = oneshot ? 2 : 1;
207
if (was_disabled) {
208
- if (!s->callback) {
209
- s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
210
- ptimer_reload(s, 0);
211
- } else {
212
- s->need_reload = true;
213
- }
214
+ s->need_reload = true;
215
}
216
}
63
}
217
64
218
@@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot)
65
-static const MemoryRegionOps versatile_i2c_ops = {
219
is immediately restarted. */
66
- .read = versatile_i2c_read,
220
void ptimer_stop(ptimer_state *s)
67
- .write = versatile_i2c_write,
68
+static const MemoryRegionOps arm_sbcon_i2c_ops = {
69
+ .read = arm_sbcon_i2c_read,
70
+ .write = arm_sbcon_i2c_write,
71
.endianness = DEVICE_NATIVE_ENDIAN,
72
};
73
74
-static void versatile_i2c_init(Object *obj)
75
+static void arm_sbcon_i2c_init(Object *obj)
221
{
76
{
222
- assert(s->in_transaction || !s->callback);
77
DeviceState *dev = DEVICE(obj);
223
+ assert(s->in_transaction);
78
ArmSbconI2CState *s = ARM_SBCON_I2C(obj);
224
79
@@ -XXX,XX +XXX,XX @@ static void versatile_i2c_init(Object *obj)
225
if (!s->enabled)
80
226
return;
81
bus = i2c_init_bus(dev, "i2c");
227
@@ -XXX,XX +XXX,XX @@ void ptimer_stop(ptimer_state *s)
82
bitbang_i2c_init(&s->bitbang, bus);
228
s->delta = ptimer_get_count(s);
83
- memory_region_init_io(&s->iomem, obj, &versatile_i2c_ops, s,
229
timer_del(s->timer);
84
+ memory_region_init_io(&s->iomem, obj, &arm_sbcon_i2c_ops, s,
230
s->enabled = 0;
85
"arm_sbcon_i2c", 0x1000);
231
- if (s->callback) {
86
sysbus_init_mmio(sbd, &s->iomem);
232
- s->need_reload = false;
233
- }
234
+ s->need_reload = false;
235
}
87
}
236
88
237
/* Set counter increment interval in nanoseconds. */
89
-static const TypeInfo versatile_i2c_info = {
238
void ptimer_set_period(ptimer_state *s, int64_t period)
90
+static const TypeInfo arm_sbcon_i2c_info = {
91
.name = TYPE_ARM_SBCON_I2C,
92
.parent = TYPE_SYS_BUS_DEVICE,
93
.instance_size = sizeof(ArmSbconI2CState),
94
- .instance_init = versatile_i2c_init,
95
+ .instance_init = arm_sbcon_i2c_init,
96
};
97
98
-static void versatile_i2c_register_types(void)
99
+static void arm_sbcon_i2c_register_types(void)
239
{
100
{
240
- assert(s->in_transaction || !s->callback);
101
- type_register_static(&versatile_i2c_info);
241
+ assert(s->in_transaction);
102
+ type_register_static(&arm_sbcon_i2c_info);
242
s->delta = ptimer_get_count(s);
243
s->period = period;
244
s->period_frac = 0;
245
if (s->enabled) {
246
- if (!s->callback) {
247
- s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
248
- ptimer_reload(s, 0);
249
- } else {
250
- s->need_reload = true;
251
- }
252
+ s->need_reload = true;
253
}
254
}
103
}
255
104
256
/* Set counter frequency in Hz. */
105
-type_init(versatile_i2c_register_types)
257
void ptimer_set_freq(ptimer_state *s, uint32_t freq)
106
+type_init(arm_sbcon_i2c_register_types)
258
{
107
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
259
- assert(s->in_transaction || !s->callback);
108
index XXXXXXX..XXXXXXX 100644
260
+ assert(s->in_transaction);
109
--- a/hw/arm/Kconfig
261
s->delta = ptimer_get_count(s);
110
+++ b/hw/arm/Kconfig
262
s->period = 1000000000ll / freq;
111
@@ -XXX,XX +XXX,XX @@ config REALVIEW
263
s->period_frac = (1000000000ll << 32) / freq;
112
select PL110
264
if (s->enabled) {
113
select PL181 # display
265
- if (!s->callback) {
114
select PL310 # cache controller
266
- s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
115
- select VERSATILE_I2C
267
- ptimer_reload(s, 0);
116
+ select ARM_SBCON_I2C
268
- } else {
117
select DS1338 # I2C RTC+NVRAM
269
- s->need_reload = true;
118
select USB_OHCI
270
- }
119
271
+ s->need_reload = true;
120
@@ -XXX,XX +XXX,XX @@ config MPS2
272
}
121
select SPLIT_IRQ
273
}
122
select UNIMP
274
123
select CMSDK_APB_WATCHDOG
275
@@ -XXX,XX +XXX,XX @@ void ptimer_set_freq(ptimer_state *s, uint32_t freq)
124
- select VERSATILE_I2C
276
count = limit. */
125
+ select ARM_SBCON_I2C
277
void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload)
126
278
{
127
config FSL_IMX7
279
- assert(s->in_transaction || !s->callback);
128
bool
280
+ assert(s->in_transaction);
129
diff --git a/hw/i2c/Kconfig b/hw/i2c/Kconfig
281
s->limit = limit;
130
index XXXXXXX..XXXXXXX 100644
282
if (reload)
131
--- a/hw/i2c/Kconfig
283
s->delta = limit;
132
+++ b/hw/i2c/Kconfig
284
if (s->enabled && reload) {
133
@@ -XXX,XX +XXX,XX @@ config SMBUS_EEPROM
285
- if (!s->callback) {
134
bool
286
- s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
135
select SMBUS
287
- ptimer_reload(s, 0);
136
288
- } else {
137
-config VERSATILE_I2C
289
- s->need_reload = true;
138
+config ARM_SBCON_I2C
290
- }
139
bool
291
+ s->need_reload = true;
140
select BITBANG_I2C
292
}
141
293
}
142
diff --git a/hw/i2c/meson.build b/hw/i2c/meson.build
294
143
index XXXXXXX..XXXXXXX 100644
295
@@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_limit(ptimer_state *s)
144
--- a/hw/i2c/meson.build
296
145
+++ b/hw/i2c/meson.build
297
void ptimer_transaction_begin(ptimer_state *s)
146
@@ -XXX,XX +XXX,XX @@ i2c_ss.add(when: 'CONFIG_ALLWINNER_I2C', if_true: files('allwinner-i2c.c'))
298
{
147
i2c_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('microbit_i2c.c'))
299
- assert(!s->in_transaction || !s->callback);
148
i2c_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_smbus.c'))
300
+ assert(!s->in_transaction);
149
i2c_ss.add(when: 'CONFIG_SMBUS_EEPROM', if_true: files('smbus_eeprom.c'))
301
s->in_transaction = true;
150
-i2c_ss.add(when: 'CONFIG_VERSATILE_I2C', if_true: files('versatile_i2c.c'))
302
s->need_reload = false;
151
+i2c_ss.add(when: 'CONFIG_ARM_SBCON_I2C', if_true: files('arm_sbcon_i2c.c'))
303
}
152
i2c_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_i2c.c'))
304
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_ptimer = {
153
i2c_ss.add(when: 'CONFIG_PPC4XX', if_true: files('ppc4xx_i2c.c'))
305
}
154
i2c_ss.add(when: 'CONFIG_PCA954X', if_true: files('i2c_mux_pca954x.c'))
306
};
307
308
-ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask)
309
-{
310
- ptimer_state *s;
311
-
312
- s = (ptimer_state *)g_malloc0(sizeof(ptimer_state));
313
- s->bh = bh;
314
- s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s);
315
- s->policy_mask = policy_mask;
316
-
317
- /*
318
- * These two policies are incompatible -- trigger-on-decrement implies
319
- * a timer trigger when the count becomes 0, but no-immediate-trigger
320
- * implies a trigger when the count stops being 0.
321
- */
322
- assert(!((policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) &&
323
- (policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)));
324
- return s;
325
-}
326
-
327
ptimer_state *ptimer_init(ptimer_cb callback, void *callback_opaque,
328
uint8_t policy_mask)
329
{
330
ptimer_state *s;
331
332
- /*
333
- * The callback function is mandatory; so we use it to distinguish
334
- * old-style QEMUBH ptimers from new transaction API ptimers.
335
- * (ptimer_init_with_bh() allows a NULL bh pointer and at least
336
- * one device (digic-timer) passes NULL, so it's not the case
337
- * that either s->bh != NULL or s->callback != NULL.)
338
- */
339
+ /* The callback function is mandatory. */
340
assert(callback);
341
342
s = g_new0(ptimer_state, 1);
343
@@ -XXX,XX +XXX,XX @@ ptimer_state *ptimer_init(ptimer_cb callback, void *callback_opaque,
344
345
void ptimer_free(ptimer_state *s)
346
{
347
- if (s->bh) {
348
- qemu_bh_delete(s->bh);
349
- }
350
timer_free(s->timer);
351
g_free(s);
352
}
353
--
155
--
354
2.20.1
156
2.34.1
355
157
356
158
diff view generated by jsdifflib
New patch
[PULL 13/26] target/arm/sme: Reorg SME access handling in handle_msr_i()
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Fabiano Rosas <farosas@suse.de>
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Message-id: 20230112102436.1913-2-philmd@linaro.org
7
Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org>
8
[PMD: Split patch in multiple tiny steps]
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-a64.c | 24 +++++++++++++-----------
13
1 file changed, 13 insertions(+), 11 deletions(-)
14
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
19
@@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
20
goto do_unallocated;
21
}
22
if (sme_access_check(s)) {
23
- bool i = crm & 1;
24
- bool changed = false;
25
+ int old = s->pstate_sm | (s->pstate_za << 1);
26
+ int new = (crm & 1) * 3;
27
+ int msk = (crm >> 1) & 3;
28
29
- if ((crm & 2) && i != s->pstate_sm) {
30
- gen_helper_set_pstate_sm(cpu_env, tcg_constant_i32(i));
31
- changed = true;
32
- }
33
- if ((crm & 4) && i != s->pstate_za) {
34
- gen_helper_set_pstate_za(cpu_env, tcg_constant_i32(i));
35
- changed = true;
36
- }
37
- if (changed) {
38
+ if ((old ^ new) & msk) {
39
+ /* At least one bit changes. */
40
+ bool i = crm & 1;
41
+
42
+ if ((crm & 2) && i != s->pstate_sm) {
43
+ gen_helper_set_pstate_sm(cpu_env, tcg_constant_i32(i));
44
+ }
45
+ if ((crm & 4) && i != s->pstate_za) {
46
+ gen_helper_set_pstate_za(cpu_env, tcg_constant_i32(i));
47
+ }
48
gen_rebuild_hflags(s);
49
} else {
50
s->base.is_jmp = DISAS_NEXT;
51
--
52
2.34.1
53
54
diff view generated by jsdifflib
New patch
[PULL 14/26] target/arm/sme: Rebuild hflags in set_pstate() helpers
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Fabiano Rosas <farosas@suse.de>
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Message-id: 20230112102436.1913-3-philmd@linaro.org
7
Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org>
8
[PMD: Split patch in multiple tiny steps]
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/sme_helper.c | 2 ++
13
target/arm/translate-a64.c | 1 -
14
2 files changed, 2 insertions(+), 1 deletion(-)
15
16
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/sme_helper.c
19
+++ b/target/arm/sme_helper.c
20
@@ -XXX,XX +XXX,XX @@ void helper_set_pstate_sm(CPUARMState *env, uint32_t i)
21
}
22
env->svcr ^= R_SVCR_SM_MASK;
23
arm_reset_sve_state(env);
24
+ arm_rebuild_hflags(env);
25
}
26
27
void helper_set_pstate_za(CPUARMState *env, uint32_t i)
28
@@ -XXX,XX +XXX,XX @@ void helper_set_pstate_za(CPUARMState *env, uint32_t i)
29
if (i) {
30
memset(env->zarray, 0, sizeof(env->zarray));
31
}
32
+ arm_rebuild_hflags(env);
33
}
34
35
void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl)
36
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/translate-a64.c
39
+++ b/target/arm/translate-a64.c
40
@@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
41
if ((crm & 4) && i != s->pstate_za) {
42
gen_helper_set_pstate_za(cpu_env, tcg_constant_i32(i));
43
}
44
- gen_rebuild_hflags(s);
45
} else {
46
s->base.is_jmp = DISAS_NEXT;
47
}
48
--
49
2.34.1
50
51
diff view generated by jsdifflib
New patch
[PULL 15/26] target/arm/sme: Introduce aarch64_set_svcr()
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Fabiano Rosas <farosas@suse.de>
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Message-id: 20230112102436.1913-4-philmd@linaro.org
7
Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org>
8
[PMD: Split patch in multiple tiny steps]
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/cpu.h | 1 +
13
linux-user/aarch64/cpu_loop.c | 2 +-
14
linux-user/aarch64/signal.c | 2 +-
15
target/arm/helper.c | 8 ++++++++
16
target/arm/sme_helper.c | 4 ++--
17
5 files changed, 13 insertions(+), 4 deletions(-)
18
19
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/cpu.h
22
+++ b/target/arm/cpu.h
23
@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
24
void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
25
void aarch64_sve_change_el(CPUARMState *env, int old_el,
26
int new_el, bool el0_a64);
27
+void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask);
28
void arm_reset_sve_state(CPUARMState *env);
29
30
/*
31
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/linux-user/aarch64/cpu_loop.c
34
+++ b/linux-user/aarch64/cpu_loop.c
35
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
36
* On syscall, PSTATE.ZA is preserved, along with the ZA matrix.
37
* PSTATE.SM is cleared, per SMSTOP, which does ResetSVEState.
38
*/
39
+ aarch64_set_svcr(env, 0, R_SVCR_SM_MASK);
40
if (FIELD_EX64(env->svcr, SVCR, SM)) {
41
- env->svcr = FIELD_DP64(env->svcr, SVCR, SM, 0);
42
arm_rebuild_hflags(env);
43
arm_reset_sve_state(env);
44
}
45
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/linux-user/aarch64/signal.c
48
+++ b/linux-user/aarch64/signal.c
49
@@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
50
* Invoke the signal handler with both SM and ZA disabled.
51
* When clearing SM, ResetSVEState, per SMSTOP.
52
*/
53
+ aarch64_set_svcr(env, 0, R_SVCR_SM_MASK | R_SVCR_ZA_MASK);
54
if (FIELD_EX64(env->svcr, SVCR, SM)) {
55
arm_reset_sve_state(env);
56
}
57
if (env->svcr) {
58
- env->svcr = 0;
59
arm_rebuild_hflags(env);
60
}
61
62
diff --git a/target/arm/helper.c b/target/arm/helper.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/target/arm/helper.c
65
+++ b/target/arm/helper.c
66
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_esm(CPUARMState *env, const ARMCPRegInfo *ri,
67
return CP_ACCESS_OK;
68
}
69
70
+void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask)
71
+{
72
+ uint64_t change = (env->svcr ^ new) & mask;
73
+
74
+ env->svcr ^= change;
75
+}
76
+
77
static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
78
uint64_t value)
79
{
80
helper_set_pstate_sm(env, FIELD_EX64(value, SVCR, SM));
81
helper_set_pstate_za(env, FIELD_EX64(value, SVCR, ZA));
82
+ aarch64_set_svcr(env, value, -1);
83
arm_rebuild_hflags(env);
84
}
85
86
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/target/arm/sme_helper.c
89
+++ b/target/arm/sme_helper.c
90
@@ -XXX,XX +XXX,XX @@ void helper_set_pstate_sm(CPUARMState *env, uint32_t i)
91
if (i == FIELD_EX64(env->svcr, SVCR, SM)) {
92
return;
93
}
94
- env->svcr ^= R_SVCR_SM_MASK;
95
+ aarch64_set_svcr(env, 0, R_SVCR_SM_MASK);
96
arm_reset_sve_state(env);
97
arm_rebuild_hflags(env);
98
}
99
@@ -XXX,XX +XXX,XX @@ void helper_set_pstate_za(CPUARMState *env, uint32_t i)
100
if (i == FIELD_EX64(env->svcr, SVCR, ZA)) {
101
return;
102
}
103
- env->svcr ^= R_SVCR_ZA_MASK;
104
+ aarch64_set_svcr(env, 0, R_SVCR_ZA_MASK);
105
106
/*
107
* ResetSMEState.
108
--
109
2.34.1
110
111
diff view generated by jsdifflib
New patch
[PULL 16/26] target/arm/sme: Reset SVE state in aarch64_set_svcr()
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Move arm_reset_sve_state() calls to aarch64_set_svcr().
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Fabiano Rosas <farosas@suse.de>
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20230112102436.1913-5-philmd@linaro.org
9
Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org>
10
[PMD: Split patch in multiple tiny steps]
11
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/cpu.h | 1 -
15
linux-user/aarch64/cpu_loop.c | 1 -
16
linux-user/aarch64/signal.c | 8 +-------
17
target/arm/helper.c | 13 +++++++++++++
18
target/arm/sme_helper.c | 10 ----------
19
5 files changed, 14 insertions(+), 19 deletions(-)
20
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.h
24
+++ b/target/arm/cpu.h
25
@@ -XXX,XX +XXX,XX @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
26
void aarch64_sve_change_el(CPUARMState *env, int old_el,
27
int new_el, bool el0_a64);
28
void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask);
29
-void arm_reset_sve_state(CPUARMState *env);
30
31
/*
32
* SVE registers are encoded in KVM's memory in an endianness-invariant format.
33
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/linux-user/aarch64/cpu_loop.c
36
+++ b/linux-user/aarch64/cpu_loop.c
37
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
38
aarch64_set_svcr(env, 0, R_SVCR_SM_MASK);
39
if (FIELD_EX64(env->svcr, SVCR, SM)) {
40
arm_rebuild_hflags(env);
41
- arm_reset_sve_state(env);
42
}
43
ret = do_syscall(env,
44
env->xregs[8],
45
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/linux-user/aarch64/signal.c
48
+++ b/linux-user/aarch64/signal.c
49
@@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
50
env->btype = 2;
51
}
52
53
- /*
54
- * Invoke the signal handler with both SM and ZA disabled.
55
- * When clearing SM, ResetSVEState, per SMSTOP.
56
- */
57
+ /* Invoke the signal handler with both SM and ZA disabled. */
58
aarch64_set_svcr(env, 0, R_SVCR_SM_MASK | R_SVCR_ZA_MASK);
59
- if (FIELD_EX64(env->svcr, SVCR, SM)) {
60
- arm_reset_sve_state(env);
61
- }
62
if (env->svcr) {
63
arm_rebuild_hflags(env);
64
}
65
diff --git a/target/arm/helper.c b/target/arm/helper.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/target/arm/helper.c
68
+++ b/target/arm/helper.c
69
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_esm(CPUARMState *env, const ARMCPRegInfo *ri,
70
return CP_ACCESS_OK;
71
}
72
73
+/* ResetSVEState */
74
+static void arm_reset_sve_state(CPUARMState *env)
75
+{
76
+ memset(env->vfp.zregs, 0, sizeof(env->vfp.zregs));
77
+ /* Recall that FFR is stored as pregs[16]. */
78
+ memset(env->vfp.pregs, 0, sizeof(env->vfp.pregs));
79
+ vfp_set_fpcr(env, 0x0800009f);
80
+}
81
+
82
void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask)
83
{
84
uint64_t change = (env->svcr ^ new) & mask;
85
86
env->svcr ^= change;
87
+
88
+ if (change & R_SVCR_SM_MASK) {
89
+ arm_reset_sve_state(env);
90
+ }
91
}
92
93
static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
94
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
95
index XXXXXXX..XXXXXXX 100644
96
--- a/target/arm/sme_helper.c
97
+++ b/target/arm/sme_helper.c
98
@@ -XXX,XX +XXX,XX @@
99
#include "vec_internal.h"
100
#include "sve_ldst_internal.h"
101
102
-/* ResetSVEState */
103
-void arm_reset_sve_state(CPUARMState *env)
104
-{
105
- memset(env->vfp.zregs, 0, sizeof(env->vfp.zregs));
106
- /* Recall that FFR is stored as pregs[16]. */
107
- memset(env->vfp.pregs, 0, sizeof(env->vfp.pregs));
108
- vfp_set_fpcr(env, 0x0800009f);
109
-}
110
-
111
void helper_set_pstate_sm(CPUARMState *env, uint32_t i)
112
{
113
if (i == FIELD_EX64(env->svcr, SVCR, SM)) {
114
return;
115
}
116
aarch64_set_svcr(env, 0, R_SVCR_SM_MASK);
117
- arm_reset_sve_state(env);
118
arm_rebuild_hflags(env);
119
}
120
121
--
122
2.34.1
123
124
diff view generated by jsdifflib
New patch
[PULL 17/26] target/arm/sme: Reset ZA state in aarch64_set_svcr()
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Fabiano Rosas <farosas@suse.de>
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Message-id: 20230112102436.1913-6-philmd@linaro.org
7
Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org>
8
[PMD: Split patch in multiple tiny steps]
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/helper.c | 12 ++++++++++++
13
target/arm/sme_helper.c | 12 ------------
14
2 files changed, 12 insertions(+), 12 deletions(-)
15
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
19
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask)
21
if (change & R_SVCR_SM_MASK) {
22
arm_reset_sve_state(env);
23
}
24
+
25
+ /*
26
+ * ResetSMEState.
27
+ *
28
+ * SetPSTATE_ZA zeros on enable and disable. We can zero this only
29
+ * on enable: while disabled, the storage is inaccessible and the
30
+ * value does not matter. We're not saving the storage in vmstate
31
+ * when disabled either.
32
+ */
33
+ if (change & new & R_SVCR_ZA_MASK) {
34
+ memset(env->zarray, 0, sizeof(env->zarray));
35
+ }
36
}
37
38
static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
39
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/sme_helper.c
42
+++ b/target/arm/sme_helper.c
43
@@ -XXX,XX +XXX,XX @@ void helper_set_pstate_za(CPUARMState *env, uint32_t i)
44
return;
45
}
46
aarch64_set_svcr(env, 0, R_SVCR_ZA_MASK);
47
-
48
- /*
49
- * ResetSMEState.
50
- *
51
- * SetPSTATE_ZA zeros on enable and disable. We can zero this only
52
- * on enable: while disabled, the storage is inaccessible and the
53
- * value does not matter. We're not saving the storage in vmstate
54
- * when disabled either.
55
- */
56
- if (i) {
57
- memset(env->zarray, 0, sizeof(env->zarray));
58
- }
59
arm_rebuild_hflags(env);
60
}
61
62
--
63
2.34.1
64
65
diff view generated by jsdifflib
New patch
[PULL 18/26] target/arm/sme: Rebuild hflags in aarch64_set_svcr()
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Fabiano Rosas <farosas@suse.de>
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Message-id: 20230112102436.1913-7-philmd@linaro.org
7
Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org>
8
[PMD: Split patch in multiple tiny steps]
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
linux-user/aarch64/cpu_loop.c | 8 +-------
13
linux-user/aarch64/signal.c | 3 ---
14
target/arm/helper.c | 6 +++++-
15
target/arm/sme_helper.c | 8 --------
16
4 files changed, 6 insertions(+), 19 deletions(-)
17
18
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/linux-user/aarch64/cpu_loop.c
21
+++ b/linux-user/aarch64/cpu_loop.c
22
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
23
24
switch (trapnr) {
25
case EXCP_SWI:
26
- /*
27
- * On syscall, PSTATE.ZA is preserved, along with the ZA matrix.
28
- * PSTATE.SM is cleared, per SMSTOP, which does ResetSVEState.
29
- */
30
+ /* On syscall, PSTATE.ZA is preserved, PSTATE.SM is cleared. */
31
aarch64_set_svcr(env, 0, R_SVCR_SM_MASK);
32
- if (FIELD_EX64(env->svcr, SVCR, SM)) {
33
- arm_rebuild_hflags(env);
34
- }
35
ret = do_syscall(env,
36
env->xregs[8],
37
env->xregs[0],
38
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/linux-user/aarch64/signal.c
41
+++ b/linux-user/aarch64/signal.c
42
@@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
43
44
/* Invoke the signal handler with both SM and ZA disabled. */
45
aarch64_set_svcr(env, 0, R_SVCR_SM_MASK | R_SVCR_ZA_MASK);
46
- if (env->svcr) {
47
- arm_rebuild_hflags(env);
48
- }
49
50
if (info) {
51
tswap_siginfo(&frame->info, info);
52
diff --git a/target/arm/helper.c b/target/arm/helper.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/helper.c
55
+++ b/target/arm/helper.c
56
@@ -XXX,XX +XXX,XX @@ void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask)
57
{
58
uint64_t change = (env->svcr ^ new) & mask;
59
60
+ if (change == 0) {
61
+ return;
62
+ }
63
env->svcr ^= change;
64
65
if (change & R_SVCR_SM_MASK) {
66
@@ -XXX,XX +XXX,XX @@ void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask)
67
if (change & new & R_SVCR_ZA_MASK) {
68
memset(env->zarray, 0, sizeof(env->zarray));
69
}
70
+
71
+ arm_rebuild_hflags(env);
72
}
73
74
static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
75
@@ -XXX,XX +XXX,XX @@ static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
76
helper_set_pstate_sm(env, FIELD_EX64(value, SVCR, SM));
77
helper_set_pstate_za(env, FIELD_EX64(value, SVCR, ZA));
78
aarch64_set_svcr(env, value, -1);
79
- arm_rebuild_hflags(env);
80
}
81
82
static void smcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
83
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
84
index XXXXXXX..XXXXXXX 100644
85
--- a/target/arm/sme_helper.c
86
+++ b/target/arm/sme_helper.c
87
@@ -XXX,XX +XXX,XX @@
88
89
void helper_set_pstate_sm(CPUARMState *env, uint32_t i)
90
{
91
- if (i == FIELD_EX64(env->svcr, SVCR, SM)) {
92
- return;
93
- }
94
aarch64_set_svcr(env, 0, R_SVCR_SM_MASK);
95
- arm_rebuild_hflags(env);
96
}
97
98
void helper_set_pstate_za(CPUARMState *env, uint32_t i)
99
{
100
- if (i == FIELD_EX64(env->svcr, SVCR, ZA)) {
101
- return;
102
- }
103
aarch64_set_svcr(env, 0, R_SVCR_ZA_MASK);
104
- arm_rebuild_hflags(env);
105
}
106
107
void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl)
108
--
109
2.34.1
110
111
diff view generated by jsdifflib
[PULL 3/3] hw/arm/boot: Set NSACR.{CP11, CP10} in dummy SMC setup routine
[PULL 19/26] target/arm/sme: Unify set_pstate() SM/ZA helpers as set_svcr()
1
From: Clement Deschamps <clement.deschamps@greensocs.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The boot.c code usually puts the CPU into NS mode directly when it is
3
Unify the two helper_set_pstate_{sm,za} in this function.
4
booting a kernel. Since fc1120a7f5f2d4b6 this has included a
4
Do not call helper_* functions from svcr_write.
5
requirement to set NSACR to give NS state access to the FPU; we fixed
6
that for the usual code path in ece628fcf6. However, it is also
7
possible for a board model to request an alternative mode of booting,
8
where its 'board_setup' code hook runs in Secure state and is
9
responsible for doing the S->NS transition after it has done whatever
10
work it must do in Secure state. In this situation the board_setup
11
code now also needs to update NSACR.
12
5
13
This affects all boards which set info->secure_board_setup, which is
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
currently the 'raspi' and 'highbank' families. They both use the
7
Reviewed-by: Fabiano Rosas <farosas@suse.de>
15
common arm_write_secure_board_setup_dummy_smc().
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
16
9
Message-id: 20230112102436.1913-8-philmd@linaro.org
17
Set the NSACR CP11 and CP10 bits in the code written by that
10
Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org>
18
function, to allow FPU access in Non-Secure state when using dummy
11
[PMD: Split patch in multiple tiny steps]
19
SMC setup routine. Otherwise an AArch32 kernel booted on the
12
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
20
highbank or raspi boards will UNDEF as soon as it tries to use the
21
FPU.
22
23
Update the comment describing secure_board_setup to note the new
24
requirements on users of it.
25
26
This fixes a kernel panic when booting raspbian on raspi2.
27
28
Successfully tested with:
29
2017-01-11-raspbian-jessie-lite.img
30
2018-11-13-raspbian-stretch-lite.img
31
2019-07-10-raspbian-buster-lite.img
32
33
Fixes: fc1120a7f5
34
Signed-off-by: Clement Deschamps <clement.deschamps@greensocs.com>
35
Tested-by: Laurent Bonnans <laurent.bonnans@here.com>
36
Message-id: 20191104151137.81931-1-clement.deschamps@greensocs.com
37
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
38
[PMM: updated comment to boot.h to note new requirement on
39
users of secure_board_setup; edited/rewrote commit message]
40
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
41
---
14
---
42
include/hw/arm/boot.h | 7 +++++--
15
target/arm/helper-sme.h | 3 +--
43
hw/arm/boot.c | 3 +++
16
target/arm/helper.c | 2 --
44
2 files changed, 8 insertions(+), 2 deletions(-)
17
target/arm/sme_helper.c | 9 ++-------
18
target/arm/translate-a64.c | 10 ++--------
19
4 files changed, 5 insertions(+), 19 deletions(-)
45
20
46
diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h
21
diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
47
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
48
--- a/include/hw/arm/boot.h
23
--- a/target/arm/helper-sme.h
49
+++ b/include/hw/arm/boot.h
24
+++ b/target/arm/helper-sme.h
50
@@ -XXX,XX +XXX,XX @@ struct arm_boot_info {
25
@@ -XXX,XX +XXX,XX @@
51
void (*write_board_setup)(ARMCPU *cpu,
26
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
52
const struct arm_boot_info *info);
27
*/
53
28
54
- /* If set, the board specific loader/setup blob will be run from secure
29
-DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32)
55
+ /*
30
-DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32)
56
+ * If set, the board specific loader/setup blob will be run from secure
31
+DEF_HELPER_FLAGS_3(set_svcr, TCG_CALL_NO_RWG, void, env, i32, i32)
57
* mode, regardless of secure_boot. The blob becomes responsible for
32
58
- * changing to non-secure state if implementing a non-secure boot
33
DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32)
59
+ * changing to non-secure state if implementing a non-secure boot,
34
60
+ * including setting up EL3/Secure registers such as the NSACR as
35
diff --git a/target/arm/helper.c b/target/arm/helper.c
61
+ * required by the Linux booting ABI before the switch to non-secure.
62
*/
63
bool secure_board_setup;
64
65
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
66
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
67
--- a/hw/arm/boot.c
37
--- a/target/arm/helper.c
68
+++ b/hw/arm/boot.c
38
+++ b/target/arm/helper.c
69
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
39
@@ -XXX,XX +XXX,XX @@ void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask)
70
};
40
static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
71
uint32_t board_setup_blob[] = {
41
uint64_t value)
72
/* board setup addr */
42
{
73
+ 0xee110f51, /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */
43
- helper_set_pstate_sm(env, FIELD_EX64(value, SVCR, SM));
74
+ 0xe3800b03, /* orr r0, #0xc00 ;set CP11, CP10 */
44
- helper_set_pstate_za(env, FIELD_EX64(value, SVCR, ZA));
75
+ 0xee010f51, /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */
45
aarch64_set_svcr(env, value, -1);
76
0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */
46
}
77
0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */
47
78
0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */
48
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/sme_helper.c
51
+++ b/target/arm/sme_helper.c
52
@@ -XXX,XX +XXX,XX @@
53
#include "vec_internal.h"
54
#include "sve_ldst_internal.h"
55
56
-void helper_set_pstate_sm(CPUARMState *env, uint32_t i)
57
+void helper_set_svcr(CPUARMState *env, uint32_t val, uint32_t mask)
58
{
59
- aarch64_set_svcr(env, 0, R_SVCR_SM_MASK);
60
-}
61
-
62
-void helper_set_pstate_za(CPUARMState *env, uint32_t i)
63
-{
64
- aarch64_set_svcr(env, 0, R_SVCR_ZA_MASK);
65
+ aarch64_set_svcr(env, val, mask);
66
}
67
68
void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl)
69
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/target/arm/translate-a64.c
72
+++ b/target/arm/translate-a64.c
73
@@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
74
75
if ((old ^ new) & msk) {
76
/* At least one bit changes. */
77
- bool i = crm & 1;
78
-
79
- if ((crm & 2) && i != s->pstate_sm) {
80
- gen_helper_set_pstate_sm(cpu_env, tcg_constant_i32(i));
81
- }
82
- if ((crm & 4) && i != s->pstate_za) {
83
- gen_helper_set_pstate_za(cpu_env, tcg_constant_i32(i));
84
- }
85
+ gen_helper_set_svcr(cpu_env, tcg_constant_i32(new),
86
+ tcg_constant_i32(msk));
87
} else {
88
s->base.is_jmp = DISAS_NEXT;
89
}
79
--
90
--
80
2.20.1
91
2.34.1
81
92
82
93
diff view generated by jsdifflib
New patch
[PULL 20/26] target/arm: Fix physical address resolution for MTE
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Conversion to probe_access_full missed applying the page offset.
4
5
Fixes: b8967ddf ("target/arm: Use probe_access_full for MTE")
6
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1416
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230114031213.2970349-1-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/mte_helper.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/mte_helper.c
18
+++ b/target/arm/mte_helper.c
19
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
20
* Remember these values across the second lookup below,
21
* which may invalidate this pointer via tlb resize.
22
*/
23
- ptr_paddr = full->phys_addr;
24
+ ptr_paddr = full->phys_addr | (ptr & ~TARGET_PAGE_MASK);
25
attrs = full->attrs;
26
full = NULL;
27
28
--
29
2.34.1
diff view generated by jsdifflib
New patch
[PULL 21/26] target/arm: Fix in_debug path in S1_ptw_translate
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
During the conversion, the test against get_phys_addr_lpae got inverted,
4
meaning that successful translations went to the 'failed' label.
5
6
Cc: qemu-stable@nongnu.org
7
Fixes: f3639a64f60 ("target/arm: Use softmmu tlbs for page table walking")
8
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1417
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20230114054605.2977022-1-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/ptw.c | 4 ++--
15
1 file changed, 2 insertions(+), 2 deletions(-)
16
17
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/ptw.c
20
+++ b/target/arm/ptw.c
21
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
22
};
23
GetPhysAddrResult s2 = { };
24
25
- if (!get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD,
26
- false, &s2, fi)) {
27
+ if (get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD,
28
+ false, &s2, fi)) {
29
goto fail;
30
}
31
ptw->out_phys = s2.f.phys_addr;
32
--
33
2.34.1
diff view generated by jsdifflib
New patch
[PULL 22/26] target/arm: Don't set EXC_RETURN.ES if Security Extension not present
1
In v7m_exception_taken(), for v8M we set the EXC_RETURN.ES bit if
2
either the exception targets Secure or if the CPU doesn't implement
3
the Security Extension. This is incorrect: the v8M Arm ARM specifies
4
that the ES bit should be RES0 if the Security Extension is not
5
implemented, and the pseudocode agrees.
1
6
7
Remove the incorrect condition, so that we leave the ES bit 0
8
if the Security Extension isn't implemented.
9
10
This doesn't have any guest-visible effects for our current set of
11
emulated CPUs, because all our v8M CPUs implement the Security
12
Extension; but it's worth fixing in case we add a v8M CPU without
13
the extension in future.
14
15
Reported-by: Igor Kotrasinski <i.kotrasinsk@samsung.com>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
---
19
target/arm/m_helper.c | 2 +-
20
1 file changed, 1 insertion(+), 1 deletion(-)
21
22
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/m_helper.c
25
+++ b/target/arm/m_helper.c
26
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
27
}
28
29
lr &= ~R_V7M_EXCRET_ES_MASK;
30
- if (targets_secure || !arm_feature(env, ARM_FEATURE_M_SECURITY)) {
31
+ if (targets_secure) {
32
lr |= R_V7M_EXCRET_ES_MASK;
33
}
34
lr &= ~R_V7M_EXCRET_SPSEL_MASK;
35
--
36
2.34.1
diff view generated by jsdifflib
New patch
[PULL 23/26] target/arm: implement DBGCLAIM registers
1
From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
1
2
3
The architecture does not define any functionality for the CLAIM tag bits.
4
So we will just keep the raw bits, as per spec.
5
6
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230120155929.32384-2-eiakovlev@linux.microsoft.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/cpu.h | 1 +
13
target/arm/debug_helper.c | 33 +++++++++++++++++++++++++++++++++
14
2 files changed, 34 insertions(+)
15
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
21
uint64_t dbgbcr[16]; /* breakpoint control registers */
22
uint64_t dbgwvr[16]; /* watchpoint value registers */
23
uint64_t dbgwcr[16]; /* watchpoint control registers */
24
+ uint64_t dbgclaim; /* DBGCLAIM bits */
25
uint64_t mdscr_el1;
26
uint64_t oslsr_el1; /* OS Lock Status */
27
uint64_t osdlr_el1; /* OS DoubleLock status */
28
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/debug_helper.c
31
+++ b/target/arm/debug_helper.c
32
@@ -XXX,XX +XXX,XX @@ static void osdlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
33
}
34
}
35
36
+static void dbgclaimset_write(CPUARMState *env, const ARMCPRegInfo *ri,
37
+ uint64_t value)
38
+{
39
+ env->cp15.dbgclaim |= (value & 0xFF);
40
+}
41
+
42
+static uint64_t dbgclaimset_read(CPUARMState *env, const ARMCPRegInfo *ri)
43
+{
44
+ /* CLAIM bits are RAO */
45
+ return 0xFF;
46
+}
47
+
48
+static void dbgclaimclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
49
+ uint64_t value)
50
+{
51
+ env->cp15.dbgclaim &= ~(value & 0xFF);
52
+}
53
+
54
static const ARMCPRegInfo debug_cp_reginfo[] = {
55
/*
56
* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
57
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
58
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
59
.access = PL1_RW, .accessfn = access_tda,
60
.type = ARM_CP_NOP },
61
+ /*
62
+ * Dummy DBGCLAIM registers.
63
+ * "The architecture does not define any functionality for the CLAIM tag bits.",
64
+ * so we only keep the raw bits
65
+ */
66
+ { .name = "DBGCLAIMSET_EL1", .state = ARM_CP_STATE_BOTH,
67
+ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 6,
68
+ .type = ARM_CP_ALIAS,
69
+ .access = PL1_RW, .accessfn = access_tda,
70
+ .writefn = dbgclaimset_write, .readfn = dbgclaimset_read },
71
+ { .name = "DBGCLAIMCLR_EL1", .state = ARM_CP_STATE_BOTH,
72
+ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 6,
73
+ .access = PL1_RW, .accessfn = access_tda,
74
+ .writefn = dbgclaimclr_write, .raw_writefn = raw_write,
75
+ .fieldoffset = offsetof(CPUARMState, cp15.dbgclaim) },
76
};
77
78
static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
79
--
80
2.34.1
diff view generated by jsdifflib
New patch
[PULL 24/26] target/arm: provide stubs for more external debug registers
1
From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
1
2
3
Qemu doesn't implement Debug Communication Channel, as well as the rest
4
of external debug interface. However, Microsoft Hyper-V in tries to
5
access some of those registers during an EL2 context switch.
6
7
Since there is no architectural way to not advertise support for external
8
debug, provide RAZ/WI stubs for OSDTRRX_EL1, OSDTRTX_EL1 and OSECCR_EL1
9
registers in the same way the rest of DCM is currently done. Do account
10
for access traps though with access_tda.
11
12
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Message-id: 20230120155929.32384-3-eiakovlev@linux.microsoft.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/debug_helper.c | 21 +++++++++++++++++++++
18
1 file changed, 21 insertions(+)
19
20
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/debug_helper.c
23
+++ b/target/arm/debug_helper.c
24
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
25
.opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
26
.access = PL0_R, .accessfn = access_tda,
27
.type = ARM_CP_CONST, .resetvalue = 0 },
28
+ /*
29
+ * OSDTRRX_EL1/OSDTRTX_EL1 are used for save and restore of DBGDTRRX_EL0.
30
+ * It is a component of the Debug Communications Channel, which is not implemented.
31
+ */
32
+ { .name = "OSDTRRX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
33
+ .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2,
34
+ .access = PL1_RW, .accessfn = access_tda,
35
+ .type = ARM_CP_CONST, .resetvalue = 0 },
36
+ { .name = "OSDTRTX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
37
+ .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
38
+ .access = PL1_RW, .accessfn = access_tda,
39
+ .type = ARM_CP_CONST, .resetvalue = 0 },
40
+ /*
41
+ * OSECCR_EL1 provides a mechanism for an operating system
42
+ * to access the contents of EDECCR. EDECCR is not implemented though,
43
+ * as is the rest of external device mechanism.
44
+ */
45
+ { .name = "OSECCR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
46
+ .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
47
+ .access = PL1_RW, .accessfn = access_tda,
48
+ .type = ARM_CP_CONST, .resetvalue = 0 },
49
/*
50
* DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as
51
* it is unlikely a guest will care.
52
--
53
2.34.1
diff view generated by jsdifflib
[PULL 2/3] Remove unassigned_access CPU hook
[PULL 25/26] target/arm: Reorg do_coproc_insn
1
All targets have now migrated away from the old unassigned_access
1
From: Richard Henderson <richard.henderson@linaro.org>
2
hook to the new do_transaction_failed hook. This means we can remove
3
the core-code infrastructure for that hook and the code that calls it.
4
2
3
Move the ri == NULL case to the top of the function and return.
4
This allows the else to be removed and the code unindented.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20230106194451.1213153-2-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20191108173732.11816-1-peter.maydell@linaro.org
9
---
11
---
10
include/hw/core/cpu.h | 24 ------------------------
12
target/arm/translate.c | 406 ++++++++++++++++++++---------------------
11
accel/tcg/cputlb.c | 2 --
13
1 file changed, 203 insertions(+), 203 deletions(-)
12
memory.c | 7 -------
13
3 files changed, 33 deletions(-)
14
14
15
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/core/cpu.h
17
--- a/target/arm/translate.c
18
+++ b/include/hw/core/cpu.h
18
+++ b/target/arm/translate.c
19
@@ -XXX,XX +XXX,XX @@ typedef enum MMUAccessType {
19
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
20
20
bool isread, int rt, int rt2)
21
typedef struct CPUWatchpoint CPUWatchpoint;
21
{
22
22
const ARMCPRegInfo *ri;
23
-typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
23
+ bool need_exit_tb;
24
- bool is_write, bool is_exec, int opaque,
24
25
- unsigned size);
25
ri = get_arm_cp_reginfo(s->cp_regs,
26
-
26
ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2));
27
struct TranslationBlock;
27
- if (ri) {
28
28
- bool need_exit_tb;
29
/**
29
30
@@ -XXX,XX +XXX,XX @@ struct TranslationBlock;
30
- /* Check access permissions */
31
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
31
- if (!cp_access_ok(s->current_el, ri, isread)) {
32
* @has_work: Callback for checking if there is work to do.
32
- unallocated_encoding(s);
33
* @do_interrupt: Callback for interrupt handling.
33
- return;
34
- * @do_unassigned_access: Callback for unassigned access handling.
34
- }
35
- * (this is deprecated: new targets should use do_transaction_failed instead)
35
-
36
* @do_unaligned_access: Callback for unaligned access handling, if
36
- if (s->hstr_active || ri->accessfn ||
37
* the target defines #TARGET_ALIGNED_ONLY.
37
- (arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
38
* @do_transaction_failed: Callback for handling failed memory transactions
38
- /* Emit code to perform further access permissions checks at
39
@@ -XXX,XX +XXX,XX @@ typedef struct CPUClass {
39
- * runtime; this may result in an exception.
40
int reset_dump_flags;
40
- * Note that on XScale all cp0..c13 registers do an access check
41
bool (*has_work)(CPUState *cpu);
41
- * call in order to handle c15_cpar.
42
void (*do_interrupt)(CPUState *cpu);
42
- */
43
- CPUUnassignedAccess do_unassigned_access;
43
- uint32_t syndrome;
44
void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
44
-
45
MMUAccessType access_type,
45
- /* Note that since we are an implementation which takes an
46
int mmu_idx, uintptr_t retaddr);
46
- * exception on a trapped conditional instruction only if the
47
@@ -XXX,XX +XXX,XX @@ struct CPUState {
47
- * instruction passes its condition code check, we can take
48
* we store some rarely used information in the CPU context.
48
- * advantage of the clause in the ARM ARM that allows us to set
49
*/
49
- * the COND field in the instruction to 0xE in all cases.
50
uintptr_t mem_io_pc;
50
- * We could fish the actual condition out of the insn (ARM)
51
- /*
51
- * or the condexec bits (Thumb) but it isn't necessary.
52
- * This is only needed for the legacy cpu_unassigned_access() hook;
52
- */
53
- * when all targets using it have been converted to use
53
- switch (cpnum) {
54
- * cpu_transaction_failed() instead it can be removed.
54
- case 14:
55
- if (is64) {
56
- syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
57
- isread, false);
58
- } else {
59
- syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
60
- rt, isread, false);
61
- }
62
- break;
63
- case 15:
64
- if (is64) {
65
- syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
66
- isread, false);
67
- } else {
68
- syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
69
- rt, isread, false);
70
- }
71
- break;
72
- default:
73
- /* ARMv8 defines that only coprocessors 14 and 15 exist,
74
- * so this can only happen if this is an ARMv7 or earlier CPU,
75
- * in which case the syndrome information won't actually be
76
- * guest visible.
77
- */
78
- assert(!arm_dc_feature(s, ARM_FEATURE_V8));
79
- syndrome = syn_uncategorized();
80
- break;
81
- }
82
-
83
- gen_set_condexec(s);
84
- gen_update_pc(s, 0);
85
- gen_helper_access_check_cp_reg(cpu_env,
86
- tcg_constant_ptr(ri),
87
- tcg_constant_i32(syndrome),
88
- tcg_constant_i32(isread));
89
- } else if (ri->type & ARM_CP_RAISES_EXC) {
90
- /*
91
- * The readfn or writefn might raise an exception;
92
- * synchronize the CPU state in case it does.
93
- */
94
- gen_set_condexec(s);
95
- gen_update_pc(s, 0);
96
- }
97
-
98
- /* Handle special cases first */
99
- switch (ri->type & ARM_CP_SPECIAL_MASK) {
100
- case 0:
101
- break;
102
- case ARM_CP_NOP:
103
- return;
104
- case ARM_CP_WFI:
105
- if (isread) {
106
- unallocated_encoding(s);
107
- return;
108
- }
109
- gen_update_pc(s, curr_insn_len(s));
110
- s->base.is_jmp = DISAS_WFI;
111
- return;
112
- default:
113
- g_assert_not_reached();
114
- }
115
-
116
- if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
117
- gen_io_start();
118
- }
119
-
120
- if (isread) {
121
- /* Read */
122
- if (is64) {
123
- TCGv_i64 tmp64;
124
- TCGv_i32 tmp;
125
- if (ri->type & ARM_CP_CONST) {
126
- tmp64 = tcg_constant_i64(ri->resetvalue);
127
- } else if (ri->readfn) {
128
- tmp64 = tcg_temp_new_i64();
129
- gen_helper_get_cp_reg64(tmp64, cpu_env,
130
- tcg_constant_ptr(ri));
131
- } else {
132
- tmp64 = tcg_temp_new_i64();
133
- tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset);
134
- }
135
- tmp = tcg_temp_new_i32();
136
- tcg_gen_extrl_i64_i32(tmp, tmp64);
137
- store_reg(s, rt, tmp);
138
- tmp = tcg_temp_new_i32();
139
- tcg_gen_extrh_i64_i32(tmp, tmp64);
140
- tcg_temp_free_i64(tmp64);
141
- store_reg(s, rt2, tmp);
142
- } else {
143
- TCGv_i32 tmp;
144
- if (ri->type & ARM_CP_CONST) {
145
- tmp = tcg_constant_i32(ri->resetvalue);
146
- } else if (ri->readfn) {
147
- tmp = tcg_temp_new_i32();
148
- gen_helper_get_cp_reg(tmp, cpu_env, tcg_constant_ptr(ri));
149
- } else {
150
- tmp = load_cpu_offset(ri->fieldoffset);
151
- }
152
- if (rt == 15) {
153
- /* Destination register of r15 for 32 bit loads sets
154
- * the condition codes from the high 4 bits of the value
155
- */
156
- gen_set_nzcv(tmp);
157
- tcg_temp_free_i32(tmp);
158
- } else {
159
- store_reg(s, rt, tmp);
160
- }
161
- }
162
+ if (!ri) {
163
+ /*
164
+ * Unknown register; this might be a guest error or a QEMU
165
+ * unimplemented feature.
166
+ */
167
+ if (is64) {
168
+ qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
169
+ "64 bit system register cp:%d opc1: %d crm:%d "
170
+ "(%s)\n",
171
+ isread ? "read" : "write", cpnum, opc1, crm,
172
+ s->ns ? "non-secure" : "secure");
173
} else {
174
- /* Write */
175
- if (ri->type & ARM_CP_CONST) {
176
- /* If not forbidden by access permissions, treat as WI */
177
- return;
178
- }
179
-
180
- if (is64) {
181
- TCGv_i32 tmplo, tmphi;
182
- TCGv_i64 tmp64 = tcg_temp_new_i64();
183
- tmplo = load_reg(s, rt);
184
- tmphi = load_reg(s, rt2);
185
- tcg_gen_concat_i32_i64(tmp64, tmplo, tmphi);
186
- tcg_temp_free_i32(tmplo);
187
- tcg_temp_free_i32(tmphi);
188
- if (ri->writefn) {
189
- gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri),
190
- tmp64);
191
- } else {
192
- tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset);
193
- }
194
- tcg_temp_free_i64(tmp64);
195
- } else {
196
- TCGv_i32 tmp = load_reg(s, rt);
197
- if (ri->writefn) {
198
- gen_helper_set_cp_reg(cpu_env, tcg_constant_ptr(ri), tmp);
199
- tcg_temp_free_i32(tmp);
200
- } else {
201
- store_cpu_offset(tmp, ri->fieldoffset, 4);
202
- }
203
- }
204
+ qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
205
+ "system register cp:%d opc1:%d crn:%d crm:%d "
206
+ "opc2:%d (%s)\n",
207
+ isread ? "read" : "write", cpnum, opc1, crn,
208
+ crm, opc2, s->ns ? "non-secure" : "secure");
209
}
210
-
211
- /* I/O operations must end the TB here (whether read or write) */
212
- need_exit_tb = ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) &&
213
- (ri->type & ARM_CP_IO));
214
-
215
- if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
216
- /*
217
- * A write to any coprocessor register that ends a TB
218
- * must rebuild the hflags for the next TB.
219
- */
220
- gen_rebuild_hflags(s, ri->type & ARM_CP_NEWEL);
221
- /*
222
- * We default to ending the TB on a coprocessor register write,
223
- * but allow this to be suppressed by the register definition
224
- * (usually only necessary to work around guest bugs).
225
- */
226
- need_exit_tb = true;
227
- }
228
- if (need_exit_tb) {
229
- gen_lookup_tb(s);
230
- }
231
-
232
+ unallocated_encoding(s);
233
return;
234
}
235
236
- /* Unknown register; this might be a guest error or a QEMU
237
- * unimplemented feature.
55
- */
238
- */
56
- MMUAccessType mem_io_access_type;
239
- if (is64) {
57
240
- qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
58
int kvm_fd;
241
- "64 bit system register cp:%d opc1: %d crm:%d "
59
struct KVMState *kvm_state;
242
- "(%s)\n",
60
@@ -XXX,XX +XXX,XX @@ void cpu_interrupt(CPUState *cpu, int mask);
243
- isread ? "read" : "write", cpnum, opc1, crm,
61
#ifdef NEED_CPU_H
244
- s->ns ? "non-secure" : "secure");
62
245
- } else {
63
#ifdef CONFIG_SOFTMMU
246
- qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
64
-static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
247
- "system register cp:%d opc1:%d crn:%d crm:%d opc2:%d "
65
- bool is_write, bool is_exec,
248
- "(%s)\n",
66
- int opaque, unsigned size)
249
- isread ? "read" : "write", cpnum, opc1, crn, crm, opc2,
67
-{
250
- s->ns ? "non-secure" : "secure");
68
- CPUClass *cc = CPU_GET_CLASS(cpu);
251
+ /* Check access permissions */
69
-
252
+ if (!cp_access_ok(s->current_el, ri, isread)) {
70
- if (cc->do_unassigned_access) {
253
+ unallocated_encoding(s);
71
- cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
254
+ return;
72
- }
73
-}
74
-
75
static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
76
MMUAccessType access_type,
77
int mmu_idx, uintptr_t retaddr)
78
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/accel/tcg/cputlb.c
81
+++ b/accel/tcg/cputlb.c
82
@@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
83
cpu_io_recompile(cpu, retaddr);
84
}
255
}
85
256
86
- cpu->mem_io_access_type = access_type;
257
- unallocated_encoding(s);
87
-
258
- return;
88
if (mr->global_locking && !qemu_mutex_iothread_locked()) {
259
+ if (s->hstr_active || ri->accessfn ||
89
qemu_mutex_lock_iothread();
260
+ (arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
90
locked = true;
261
+ /*
91
diff --git a/memory.c b/memory.c
262
+ * Emit code to perform further access permissions checks at
92
index XXXXXXX..XXXXXXX 100644
263
+ * runtime; this may result in an exception.
93
--- a/memory.c
264
+ * Note that on XScale all cp0..c13 registers do an access check
94
+++ b/memory.c
265
+ * call in order to handle c15_cpar.
95
@@ -XXX,XX +XXX,XX @@ static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
266
+ */
96
#ifdef DEBUG_UNASSIGNED
267
+ uint32_t syndrome;
97
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
268
+
98
#endif
269
+ /*
99
- if (current_cpu != NULL) {
270
+ * Note that since we are an implementation which takes an
100
- bool is_exec = current_cpu->mem_io_access_type == MMU_INST_FETCH;
271
+ * exception on a trapped conditional instruction only if the
101
- cpu_unassigned_access(current_cpu, addr, false, is_exec, 0, size);
272
+ * instruction passes its condition code check, we can take
102
- }
273
+ * advantage of the clause in the ARM ARM that allows us to set
103
return 0;
274
+ * the COND field in the instruction to 0xE in all cases.
275
+ * We could fish the actual condition out of the insn (ARM)
276
+ * or the condexec bits (Thumb) but it isn't necessary.
277
+ */
278
+ switch (cpnum) {
279
+ case 14:
280
+ if (is64) {
281
+ syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
282
+ isread, false);
283
+ } else {
284
+ syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
285
+ rt, isread, false);
286
+ }
287
+ break;
288
+ case 15:
289
+ if (is64) {
290
+ syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
291
+ isread, false);
292
+ } else {
293
+ syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
294
+ rt, isread, false);
295
+ }
296
+ break;
297
+ default:
298
+ /*
299
+ * ARMv8 defines that only coprocessors 14 and 15 exist,
300
+ * so this can only happen if this is an ARMv7 or earlier CPU,
301
+ * in which case the syndrome information won't actually be
302
+ * guest visible.
303
+ */
304
+ assert(!arm_dc_feature(s, ARM_FEATURE_V8));
305
+ syndrome = syn_uncategorized();
306
+ break;
307
+ }
308
+
309
+ gen_set_condexec(s);
310
+ gen_update_pc(s, 0);
311
+ gen_helper_access_check_cp_reg(cpu_env,
312
+ tcg_constant_ptr(ri),
313
+ tcg_constant_i32(syndrome),
314
+ tcg_constant_i32(isread));
315
+ } else if (ri->type & ARM_CP_RAISES_EXC) {
316
+ /*
317
+ * The readfn or writefn might raise an exception;
318
+ * synchronize the CPU state in case it does.
319
+ */
320
+ gen_set_condexec(s);
321
+ gen_update_pc(s, 0);
322
+ }
323
+
324
+ /* Handle special cases first */
325
+ switch (ri->type & ARM_CP_SPECIAL_MASK) {
326
+ case 0:
327
+ break;
328
+ case ARM_CP_NOP:
329
+ return;
330
+ case ARM_CP_WFI:
331
+ if (isread) {
332
+ unallocated_encoding(s);
333
+ return;
334
+ }
335
+ gen_update_pc(s, curr_insn_len(s));
336
+ s->base.is_jmp = DISAS_WFI;
337
+ return;
338
+ default:
339
+ g_assert_not_reached();
340
+ }
341
+
342
+ if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
343
+ gen_io_start();
344
+ }
345
+
346
+ if (isread) {
347
+ /* Read */
348
+ if (is64) {
349
+ TCGv_i64 tmp64;
350
+ TCGv_i32 tmp;
351
+ if (ri->type & ARM_CP_CONST) {
352
+ tmp64 = tcg_constant_i64(ri->resetvalue);
353
+ } else if (ri->readfn) {
354
+ tmp64 = tcg_temp_new_i64();
355
+ gen_helper_get_cp_reg64(tmp64, cpu_env,
356
+ tcg_constant_ptr(ri));
357
+ } else {
358
+ tmp64 = tcg_temp_new_i64();
359
+ tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset);
360
+ }
361
+ tmp = tcg_temp_new_i32();
362
+ tcg_gen_extrl_i64_i32(tmp, tmp64);
363
+ store_reg(s, rt, tmp);
364
+ tmp = tcg_temp_new_i32();
365
+ tcg_gen_extrh_i64_i32(tmp, tmp64);
366
+ tcg_temp_free_i64(tmp64);
367
+ store_reg(s, rt2, tmp);
368
+ } else {
369
+ TCGv_i32 tmp;
370
+ if (ri->type & ARM_CP_CONST) {
371
+ tmp = tcg_constant_i32(ri->resetvalue);
372
+ } else if (ri->readfn) {
373
+ tmp = tcg_temp_new_i32();
374
+ gen_helper_get_cp_reg(tmp, cpu_env, tcg_constant_ptr(ri));
375
+ } else {
376
+ tmp = load_cpu_offset(ri->fieldoffset);
377
+ }
378
+ if (rt == 15) {
379
+ /* Destination register of r15 for 32 bit loads sets
380
+ * the condition codes from the high 4 bits of the value
381
+ */
382
+ gen_set_nzcv(tmp);
383
+ tcg_temp_free_i32(tmp);
384
+ } else {
385
+ store_reg(s, rt, tmp);
386
+ }
387
+ }
388
+ } else {
389
+ /* Write */
390
+ if (ri->type & ARM_CP_CONST) {
391
+ /* If not forbidden by access permissions, treat as WI */
392
+ return;
393
+ }
394
+
395
+ if (is64) {
396
+ TCGv_i32 tmplo, tmphi;
397
+ TCGv_i64 tmp64 = tcg_temp_new_i64();
398
+ tmplo = load_reg(s, rt);
399
+ tmphi = load_reg(s, rt2);
400
+ tcg_gen_concat_i32_i64(tmp64, tmplo, tmphi);
401
+ tcg_temp_free_i32(tmplo);
402
+ tcg_temp_free_i32(tmphi);
403
+ if (ri->writefn) {
404
+ gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri), tmp64);
405
+ } else {
406
+ tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset);
407
+ }
408
+ tcg_temp_free_i64(tmp64);
409
+ } else {
410
+ TCGv_i32 tmp = load_reg(s, rt);
411
+ if (ri->writefn) {
412
+ gen_helper_set_cp_reg(cpu_env, tcg_constant_ptr(ri), tmp);
413
+ tcg_temp_free_i32(tmp);
414
+ } else {
415
+ store_cpu_offset(tmp, ri->fieldoffset, 4);
416
+ }
417
+ }
418
+ }
419
+
420
+ /* I/O operations must end the TB here (whether read or write) */
421
+ need_exit_tb = ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) &&
422
+ (ri->type & ARM_CP_IO));
423
+
424
+ if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
425
+ /*
426
+ * A write to any coprocessor register that ends a TB
427
+ * must rebuild the hflags for the next TB.
428
+ */
429
+ gen_rebuild_hflags(s, ri->type & ARM_CP_NEWEL);
430
+ /*
431
+ * We default to ending the TB on a coprocessor register write,
432
+ * but allow this to be suppressed by the register definition
433
+ * (usually only necessary to work around guest bugs).
434
+ */
435
+ need_exit_tb = true;
436
+ }
437
+ if (need_exit_tb) {
438
+ gen_lookup_tb(s);
439
+ }
104
}
440
}
105
441
106
@@ -XXX,XX +XXX,XX @@ static void unassigned_mem_write(void *opaque, hwaddr addr,
442
/* Decode XScale DSP or iWMMXt insn (in the copro space, cp=0 or 1) */
107
#ifdef DEBUG_UNASSIGNED
108
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
109
#endif
110
- if (current_cpu != NULL) {
111
- cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
112
- }
113
}
114
115
static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
116
--
443
--
117
2.20.1
444
2.34.1
118
445
119
446
diff view generated by jsdifflib
New patch
[PULL 26/26] target/arm: Look up ARMCPRegInfo at runtime
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Do not encode the pointer as a constant in the opcode stream.
4
This pointer is specific to the cpu that first generated the
5
translation, which runs into problems with both hot-pluggable
6
cpus and user-only threads, as cpus are removed. It's also a
7
potential correctness issue in the theoretical case of a
8
slightly-heterogenous system, because if CPU 0 generates a
9
TB and then CPU 1 executes it, CPU 1 will end up using CPU 0's
10
hash table, which might have a wrong set of registers in it.
11
(All our current systems are either completely homogenous,
12
M-profile, or have CPUs sufficiently different that they
13
wouldn't be sharing TBs anyway because the differences would
14
show up in the TB flags, so the correctness issue is only
15
theoretical, not practical.)
16
17
Perform the lookup in either helper_access_check_cp_reg,
18
or a new helper_lookup_cp_reg.
19
20
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 20230106194451.1213153-3-richard.henderson@linaro.org
22
[PMM: added note in commit message about correctness issue]
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
---
26
target/arm/helper.h | 11 +++++----
27
target/arm/translate.h | 7 ++++++
28
target/arm/op_helper.c | 27 ++++++++++++++------
29
target/arm/translate-a64.c | 49 ++++++++++++++++++++++---------------
30
target/arm/translate.c | 50 +++++++++++++++++++++++++-------------
31
5 files changed, 95 insertions(+), 49 deletions(-)
32
33
diff --git a/target/arm/helper.h b/target/arm/helper.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/helper.h
36
+++ b/target/arm/helper.h
37
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(v8m_stackcheck, void, env, i32)
38
39
DEF_HELPER_FLAGS_2(check_bxj_trap, TCG_CALL_NO_WG, void, env, i32)
40
41
-DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32)
42
-DEF_HELPER_3(set_cp_reg, void, env, ptr, i32)
43
-DEF_HELPER_2(get_cp_reg, i32, env, ptr)
44
-DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64)
45
-DEF_HELPER_2(get_cp_reg64, i64, env, ptr)
46
+DEF_HELPER_4(access_check_cp_reg, cptr, env, i32, i32, i32)
47
+DEF_HELPER_FLAGS_2(lookup_cp_reg, TCG_CALL_NO_RWG_SE, cptr, env, i32)
48
+DEF_HELPER_3(set_cp_reg, void, env, cptr, i32)
49
+DEF_HELPER_2(get_cp_reg, i32, env, cptr)
50
+DEF_HELPER_3(set_cp_reg64, void, env, cptr, i64)
51
+DEF_HELPER_2(get_cp_reg64, i64, env, cptr)
52
53
DEF_HELPER_2(get_r13_banked, i32, env, i32)
54
DEF_HELPER_3(set_r13_banked, void, env, i32, i32)
55
diff --git a/target/arm/translate.h b/target/arm/translate.h
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/arm/translate.h
58
+++ b/target/arm/translate.h
59
@@ -XXX,XX +XXX,XX @@ static inline void set_disas_label(DisasContext *s, DisasLabel l)
60
s->pc_save = l.pc_save;
61
}
62
63
+static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key)
64
+{
65
+ TCGv_ptr ret = tcg_temp_new_ptr();
66
+ gen_helper_lookup_cp_reg(ret, cpu_env, tcg_constant_i32(key));
67
+ return ret;
68
+}
69
+
70
/*
71
* Helpers for implementing sets of trans_* functions.
72
* Defer the implementation of NAME to FUNC, with optional extra arguments.
73
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/target/arm/op_helper.c
76
+++ b/target/arm/op_helper.c
77
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno)
78
}
79
}
80
81
-void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
82
- uint32_t isread)
83
+const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
84
+ uint32_t syndrome, uint32_t isread)
85
{
86
ARMCPU *cpu = env_archcpu(env);
87
- const ARMCPRegInfo *ri = rip;
88
+ const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, key);
89
CPAccessResult res = CP_ACCESS_OK;
90
int target_el;
91
92
+ assert(ri != NULL);
93
+
94
if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14
95
&& extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) {
96
res = CP_ACCESS_TRAP;
97
@@ -XXX,XX +XXX,XX @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
98
res = ri->accessfn(env, ri, isread);
99
}
100
if (likely(res == CP_ACCESS_OK)) {
101
- return;
102
+ return ri;
103
}
104
105
fail:
106
@@ -XXX,XX +XXX,XX @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
107
raise_exception(env, EXCP_UDEF, syndrome, target_el);
108
}
109
110
-void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
111
+const void *HELPER(lookup_cp_reg)(CPUARMState *env, uint32_t key)
112
+{
113
+ ARMCPU *cpu = env_archcpu(env);
114
+ const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, key);
115
+
116
+ assert(ri != NULL);
117
+ return ri;
118
+}
119
+
120
+void HELPER(set_cp_reg)(CPUARMState *env, const void *rip, uint32_t value)
121
{
122
const ARMCPRegInfo *ri = rip;
123
124
@@ -XXX,XX +XXX,XX @@ void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
125
}
126
}
127
128
-uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
129
+uint32_t HELPER(get_cp_reg)(CPUARMState *env, const void *rip)
130
{
131
const ARMCPRegInfo *ri = rip;
132
uint32_t res;
133
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
134
return res;
135
}
136
137
-void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value)
138
+void HELPER(set_cp_reg64)(CPUARMState *env, const void *rip, uint64_t value)
139
{
140
const ARMCPRegInfo *ri = rip;
141
142
@@ -XXX,XX +XXX,XX @@ void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value)
143
}
144
}
145
146
-uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
147
+uint64_t HELPER(get_cp_reg64)(CPUARMState *env, const void *rip)
148
{
149
const ARMCPRegInfo *ri = rip;
150
uint64_t res;
151
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
152
index XXXXXXX..XXXXXXX 100644
153
--- a/target/arm/translate-a64.c
154
+++ b/target/arm/translate-a64.c
155
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
156
unsigned int op0, unsigned int op1, unsigned int op2,
157
unsigned int crn, unsigned int crm, unsigned int rt)
158
{
159
- const ARMCPRegInfo *ri;
160
+ uint32_t key = ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
161
+ crn, crm, op0, op1, op2);
162
+ const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key);
163
+ TCGv_ptr tcg_ri = NULL;
164
TCGv_i64 tcg_rt;
165
166
- ri = get_arm_cp_reginfo(s->cp_regs,
167
- ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
168
- crn, crm, op0, op1, op2));
169
-
170
if (!ri) {
171
/* Unknown register; this might be a guest error or a QEMU
172
* unimplemented feature.
173
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
174
175
syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
176
gen_a64_update_pc(s, 0);
177
- gen_helper_access_check_cp_reg(cpu_env,
178
- tcg_constant_ptr(ri),
179
+ tcg_ri = tcg_temp_new_ptr();
180
+ gen_helper_access_check_cp_reg(tcg_ri, cpu_env,
181
+ tcg_constant_i32(key),
182
tcg_constant_i32(syndrome),
183
tcg_constant_i32(isread));
184
} else if (ri->type & ARM_CP_RAISES_EXC) {
185
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
186
case 0:
187
break;
188
case ARM_CP_NOP:
189
- return;
190
+ goto exit;
191
case ARM_CP_NZCV:
192
tcg_rt = cpu_reg(s, rt);
193
if (isread) {
194
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
195
} else {
196
gen_set_nzcv(tcg_rt);
197
}
198
- return;
199
+ goto exit;
200
case ARM_CP_CURRENTEL:
201
/* Reads as current EL value from pstate, which is
202
* guaranteed to be constant by the tb flags.
203
*/
204
tcg_rt = cpu_reg(s, rt);
205
tcg_gen_movi_i64(tcg_rt, s->current_el << 2);
206
- return;
207
+ goto exit;
208
case ARM_CP_DC_ZVA:
209
/* Writes clear the aligned block of memory which rt points into. */
210
if (s->mte_active[0]) {
211
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
212
tcg_rt = clean_data_tbi(s, cpu_reg(s, rt));
213
}
214
gen_helper_dc_zva(cpu_env, tcg_rt);
215
- return;
216
+ goto exit;
217
case ARM_CP_DC_GVA:
218
{
219
TCGv_i64 clean_addr, tag;
220
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
221
tcg_temp_free_i64(tag);
222
}
223
}
224
- return;
225
+ goto exit;
226
case ARM_CP_DC_GZVA:
227
{
228
TCGv_i64 clean_addr, tag;
229
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
230
tcg_temp_free_i64(tag);
231
}
232
}
233
- return;
234
+ goto exit;
235
default:
236
g_assert_not_reached();
237
}
238
if ((ri->type & ARM_CP_FPU) && !fp_access_check_only(s)) {
239
- return;
240
+ goto exit;
241
} else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) {
242
- return;
243
+ goto exit;
244
} else if ((ri->type & ARM_CP_SME) && !sme_access_check(s)) {
245
- return;
246
+ goto exit;
247
}
248
249
if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
250
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
251
if (ri->type & ARM_CP_CONST) {
252
tcg_gen_movi_i64(tcg_rt, ri->resetvalue);
253
} else if (ri->readfn) {
254
- gen_helper_get_cp_reg64(tcg_rt, cpu_env, tcg_constant_ptr(ri));
255
+ if (!tcg_ri) {
256
+ tcg_ri = gen_lookup_cp_reg(key);
257
+ }
258
+ gen_helper_get_cp_reg64(tcg_rt, cpu_env, tcg_ri);
259
} else {
260
tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset);
261
}
262
} else {
263
if (ri->type & ARM_CP_CONST) {
264
/* If not forbidden by access permissions, treat as WI */
265
- return;
266
+ goto exit;
267
} else if (ri->writefn) {
268
- gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri), tcg_rt);
269
+ if (!tcg_ri) {
270
+ tcg_ri = gen_lookup_cp_reg(key);
271
+ }
272
+ gen_helper_set_cp_reg64(cpu_env, tcg_ri, tcg_rt);
273
} else {
274
tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset);
275
}
276
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
277
*/
278
s->base.is_jmp = DISAS_UPDATE_EXIT;
279
}
280
+
281
+ exit:
282
+ if (tcg_ri) {
283
+ tcg_temp_free_ptr(tcg_ri);
284
+ }
285
}
286
287
/* System
288
diff --git a/target/arm/translate.c b/target/arm/translate.c
289
index XXXXXXX..XXXXXXX 100644
290
--- a/target/arm/translate.c
291
+++ b/target/arm/translate.c
292
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
293
int opc1, int crn, int crm, int opc2,
294
bool isread, int rt, int rt2)
295
{
296
- const ARMCPRegInfo *ri;
297
+ uint32_t key = ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2);
298
+ const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key);
299
+ TCGv_ptr tcg_ri = NULL;
300
bool need_exit_tb;
301
302
- ri = get_arm_cp_reginfo(s->cp_regs,
303
- ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2));
304
-
305
if (!ri) {
306
/*
307
* Unknown register; this might be a guest error or a QEMU
308
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
309
310
gen_set_condexec(s);
311
gen_update_pc(s, 0);
312
- gen_helper_access_check_cp_reg(cpu_env,
313
- tcg_constant_ptr(ri),
314
+ tcg_ri = tcg_temp_new_ptr();
315
+ gen_helper_access_check_cp_reg(tcg_ri, cpu_env,
316
+ tcg_constant_i32(key),
317
tcg_constant_i32(syndrome),
318
tcg_constant_i32(isread));
319
} else if (ri->type & ARM_CP_RAISES_EXC) {
320
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
321
case 0:
322
break;
323
case ARM_CP_NOP:
324
- return;
325
+ goto exit;
326
case ARM_CP_WFI:
327
if (isread) {
328
unallocated_encoding(s);
329
- return;
330
+ } else {
331
+ gen_update_pc(s, curr_insn_len(s));
332
+ s->base.is_jmp = DISAS_WFI;
333
}
334
- gen_update_pc(s, curr_insn_len(s));
335
- s->base.is_jmp = DISAS_WFI;
336
- return;
337
+ goto exit;
338
default:
339
g_assert_not_reached();
340
}
341
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
342
if (ri->type & ARM_CP_CONST) {
343
tmp64 = tcg_constant_i64(ri->resetvalue);
344
} else if (ri->readfn) {
345
+ if (!tcg_ri) {
346
+ tcg_ri = gen_lookup_cp_reg(key);
347
+ }
348
tmp64 = tcg_temp_new_i64();
349
- gen_helper_get_cp_reg64(tmp64, cpu_env,
350
- tcg_constant_ptr(ri));
351
+ gen_helper_get_cp_reg64(tmp64, cpu_env, tcg_ri);
352
} else {
353
tmp64 = tcg_temp_new_i64();
354
tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset);
355
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
356
if (ri->type & ARM_CP_CONST) {
357
tmp = tcg_constant_i32(ri->resetvalue);
358
} else if (ri->readfn) {
359
+ if (!tcg_ri) {
360
+ tcg_ri = gen_lookup_cp_reg(key);
361
+ }
362
tmp = tcg_temp_new_i32();
363
- gen_helper_get_cp_reg(tmp, cpu_env, tcg_constant_ptr(ri));
364
+ gen_helper_get_cp_reg(tmp, cpu_env, tcg_ri);
365
} else {
366
tmp = load_cpu_offset(ri->fieldoffset);
367
}
368
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
369
/* Write */
370
if (ri->type & ARM_CP_CONST) {
371
/* If not forbidden by access permissions, treat as WI */
372
- return;
373
+ goto exit;
374
}
375
376
if (is64) {
377
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
378
tcg_temp_free_i32(tmplo);
379
tcg_temp_free_i32(tmphi);
380
if (ri->writefn) {
381
- gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri), tmp64);
382
+ if (!tcg_ri) {
383
+ tcg_ri = gen_lookup_cp_reg(key);
384
+ }
385
+ gen_helper_set_cp_reg64(cpu_env, tcg_ri, tmp64);
386
} else {
387
tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset);
388
}
389
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
390
} else {
391
TCGv_i32 tmp = load_reg(s, rt);
392
if (ri->writefn) {
393
- gen_helper_set_cp_reg(cpu_env, tcg_constant_ptr(ri), tmp);
394
+ if (!tcg_ri) {
395
+ tcg_ri = gen_lookup_cp_reg(key);
396
+ }
397
+ gen_helper_set_cp_reg(cpu_env, tcg_ri, tmp);
398
tcg_temp_free_i32(tmp);
399
} else {
400
store_cpu_offset(tmp, ri->fieldoffset, 4);
401
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
402
if (need_exit_tb) {
403
gen_lookup_tb(s);
404
}
405
+
406
+ exit:
407
+ if (tcg_ri) {
408
+ tcg_temp_free_ptr(tcg_ri);
409
+ }
410
}
411
412
/* Decode XScale DSP or iWMMXt insn (in the copro space, cp=0 or 1) */
413
--
414
2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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