[PULL 0/3] target-arm queue
[PULL v2 00/57] target-arm queue
1
Arm patches for rc1:
1
Squashed in a trivial fix for 32-bit hosts:
2
* two final "remove the old API" patches for some API transitions
3
* bugfix for raspi/highbank Linux boot
4
2
5
thanks
3
--- a/target/arm/mve_helper.c
4
+++ b/target/arm/mve_helper.c
5
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
6
acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
7
m[H##ESIZE(e)])); \
8
} \
9
- acc = int128_add(acc, 1 << 7); \
10
+ acc = int128_add(acc, int128_make64(1 << 7)); \
11
} \
12
} \
13
mve_advance_vpt(env); \
14
6
-- PMM
15
-- PMM
7
16
8
The following changes since commit 654efcb511d394c1d3f5292c28503d1d19e5b1d3:
17
The following changes since commit 53f306f316549d20c76886903181413d20842423:
9
18
10
Merge remote-tracking branch 'remotes/vivier/tags/q800-branch-pull-request' into staging (2019-11-11 09:23:46 +0000)
19
Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
11
20
12
are available in the Git repository at:
21
are available in the Git repository at:
13
22
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191111
23
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
15
24
16
for you to fetch changes up to 45c078f163fd47c35e7505d98928fae63baada7d:
25
for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
17
26
18
hw/arm/boot: Set NSACR.{CP11, CP10} in dummy SMC setup routine (2019-11-11 13:44:16 +0000)
27
docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
19
28
20
----------------------------------------------------------------
29
----------------------------------------------------------------
21
target-arm queue:
30
target-arm queue:
22
* Remove old unassigned_access CPU hook API
31
* Don't require 'virt' board to be compiled in for ACPI GHES code
23
* Remove old ptimer_init_with_bh() API
32
* docs: Document which architecture extensions we emulate
24
* hw/arm/boot: Set NSACR.{CP11, CP10} in dummy SMC setup routine
33
* Fix bugs in M-profile FPCXT_NS accesses
34
* First slice of MVE patches
35
* Implement MTE3
36
* docs/system: arm: Add nRF boards description
25
37
26
----------------------------------------------------------------
38
----------------------------------------------------------------
27
Clement Deschamps (1):
39
Alexandre Iooss (1):
28
hw/arm/boot: Set NSACR.{CP11, CP10} in dummy SMC setup routine
40
docs/system: arm: Add nRF boards description
29
41
30
Peter Maydell (2):
42
Peter Collingbourne (1):
31
ptimer: Remove old ptimer_init_with_bh() API
43
target/arm: Implement MTE3
32
Remove unassigned_access CPU hook
33
44
34
include/hw/arm/boot.h | 7 ++--
45
Peter Maydell (55):
35
include/hw/core/cpu.h | 24 --------------
46
hw/acpi: Provide stub version of acpi_ghes_record_errors()
36
include/hw/ptimer.h | 45 ++++++++++++-------------
47
hw/acpi: Provide function acpi_ghes_present()
37
accel/tcg/cputlb.c | 2 --
48
target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
38
hw/arm/boot.c | 3 ++
49
docs/system/arm: Document which architecture extensions we emulate
39
hw/core/ptimer.c | 91 +++++++++------------------------------------------
50
target/arm/translate-vfp.c: Whitespace fixes
40
memory.c | 7 ----
51
target/arm: Handle FPU being disabled in FPCXT_NS accesses
41
7 files changed, 44 insertions(+), 135 deletions(-)
52
target/arm: Don't NOCP fault for FPCXT_NS accesses
53
target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
54
target/arm: Factor FP context update code out into helper function
55
target/arm: Split vfp_access_check() into A and M versions
56
target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
57
target/arm: Implement MVE VLDR/VSTR (non-widening forms)
58
target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
59
target/arm: Implement MVE VCLZ
60
target/arm: Implement MVE VCLS
61
target/arm: Implement MVE VREV16, VREV32, VREV64
62
target/arm: Implement MVE VMVN (register)
63
target/arm: Implement MVE VABS
64
target/arm: Implement MVE VNEG
65
tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
66
target/arm: Implement MVE VDUP
67
target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
68
target/arm: Implement MVE VADD, VSUB, VMUL
69
target/arm: Implement MVE VMULH
70
target/arm: Implement MVE VRMULH
71
target/arm: Implement MVE VMAX, VMIN
72
target/arm: Implement MVE VABD
73
target/arm: Implement MVE VHADD, VHSUB
74
target/arm: Implement MVE VMULL
75
target/arm: Implement MVE VMLALDAV
76
target/arm: Implement MVE VMLSLDAV
77
target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
78
target/arm: Implement MVE VADD (scalar)
79
target/arm: Implement MVE VSUB, VMUL (scalar)
80
target/arm: Implement MVE VHADD, VHSUB (scalar)
81
target/arm: Implement MVE VBRSR
82
target/arm: Implement MVE VPST
83
target/arm: Implement MVE VQADD and VQSUB
84
target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
85
target/arm: Implement MVE VQDMULL scalar
86
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
87
target/arm: Implement MVE VQADD, VQSUB (vector)
88
target/arm: Implement MVE VQSHL (vector)
89
target/arm: Implement MVE VQRSHL
90
target/arm: Implement MVE VSHL insn
91
target/arm: Implement MVE VRSHL
92
target/arm: Implement MVE VQDMLADH and VQRDMLADH
93
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
94
target/arm: Implement MVE VQDMULL (vector)
95
target/arm: Implement MVE VRHADD
96
target/arm: Implement MVE VADC, VSBC
97
target/arm: Implement MVE VCADD
98
target/arm: Implement MVE VHCADD
99
target/arm: Implement MVE VADDV
100
target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
42
101
102
docs/system/arm/emulation.rst | 103 ++++
103
docs/system/arm/nrf.rst | 51 ++
104
docs/system/target-arm.rst | 7 +
105
include/hw/acpi/ghes.h | 9 +
106
include/tcg/tcg-op.h | 8 +
107
include/tcg/tcg.h | 1 -
108
target/arm/helper-mve.h | 357 +++++++++++++
109
target/arm/helper.h | 2 +
110
target/arm/internals.h | 11 +
111
target/arm/translate-a32.h | 3 +
112
target/arm/translate.h | 10 +
113
target/arm/m-nocp.decode | 24 +
114
target/arm/mve.decode | 240 +++++++++
115
target/arm/vfp.decode | 14 -
116
hw/acpi/ghes-stub.c | 22 +
117
hw/acpi/ghes.c | 17 +
118
target/arm/cpu64.c | 2 +-
119
target/arm/kvm64.c | 6 +-
120
target/arm/mte_helper.c | 82 +--
121
target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++
122
target/arm/translate-m-nocp.c | 550 +++++++++++++++++++
123
target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++
124
target/arm/translate-vfp.c | 741 +++++++-------------------
125
tcg/tcg-op-gvec.c | 20 +-
126
MAINTAINERS | 1 +
127
hw/acpi/meson.build | 6 +-
128
target/arm/meson.build | 1 +
129
27 files changed, 3578 insertions(+), 629 deletions(-)
130
create mode 100644 docs/system/arm/emulation.rst
131
create mode 100644 docs/system/arm/nrf.rst
132
create mode 100644 target/arm/helper-mve.h
133
create mode 100644 hw/acpi/ghes-stub.c
134
create mode 100644 target/arm/mve_helper.c
135
diff view generated by jsdifflib
[PULL 1/3] ptimer: Remove old ptimer_init_with_bh() API
Deleted patch
1
Now all the users of ptimers have converted to the transaction-based
2
API, we can remove ptimer_init_with_bh() and all the code paths
3
that are used only by bottom-half based ptimers, and tidy up the
4
documentation comments to consider the transaction-based API the
5
only possibility.
6
1
7
The code changes result from:
8
* s->bh no longer exists
9
* s->callback is now always non-NULL
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20191025142411.17085-1-peter.maydell@linaro.org
14
---
15
include/hw/ptimer.h | 45 +++++++++++-----------
16
hw/core/ptimer.c | 91 ++++++++-------------------------------------
17
2 files changed, 36 insertions(+), 100 deletions(-)
18
19
diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/ptimer.h
22
+++ b/include/hw/ptimer.h
23
@@ -XXX,XX +XXX,XX @@
24
25
#include "qemu/timer.h"
26
27
-/* The ptimer API implements a simple periodic countdown timer.
28
+/*
29
+ * The ptimer API implements a simple periodic countdown timer.
30
* The countdown timer has a value (which can be read and written via
31
* ptimer_get_count() and ptimer_set_count()). When it is enabled
32
* using ptimer_run(), the value will count downwards at the frequency
33
* which has been configured using ptimer_set_period() or ptimer_set_freq().
34
- * When it reaches zero it will trigger a QEMU bottom half handler, and
35
+ * When it reaches zero it will trigger a callback function, and
36
* can be set to either reload itself from a specified limit value
37
* and keep counting down, or to stop (as a one-shot timer).
38
*
39
+ * A transaction-based API is used for modifying ptimer state: all calls
40
+ * to functions which modify ptimer state must be between matched calls to
41
+ * ptimer_transaction_begin() and ptimer_transaction_commit().
42
+ * When ptimer_transaction_commit() is called it will evaluate the state
43
+ * of the timer after all the changes in the transaction, and call the
44
+ * callback if necessary. (See the ptimer_init() documentation for the full
45
+ * list of state-modifying functions and detailed semantics of the callback.)
46
+ *
47
* Forgetting to set the period/frequency (or setting it to zero) is a
48
* bug in the QEMU device and will cause warning messages to be printed
49
* to stderr when the guest attempts to enable the timer.
50
@@ -XXX,XX +XXX,XX @@
51
* ptimer_set_count() or ptimer_set_limit() will not trigger the timer
52
* (though it will cause a reload). Only a counter decrement to "0"
53
* will cause a trigger. Not compatible with NO_IMMEDIATE_TRIGGER;
54
- * ptimer_init_with_bh() will assert() that you don't set both.
55
+ * ptimer_init() will assert() that you don't set both.
56
*/
57
#define PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT (1 << 5)
58
59
@@ -XXX,XX +XXX,XX @@
60
typedef struct ptimer_state ptimer_state;
61
typedef void (*ptimer_cb)(void *opaque);
62
63
-/**
64
- * ptimer_init_with_bh - Allocate and return a new ptimer
65
- * @bh: QEMU bottom half which is run on timer expiry
66
- * @policy: PTIMER_POLICY_* bits specifying behaviour
67
- *
68
- * The ptimer returned must be freed using ptimer_free().
69
- * The ptimer takes ownership of @bh and will delete it
70
- * when the ptimer is eventually freed.
71
- */
72
-ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask);
73
-
74
/**
75
* ptimer_init - Allocate and return a new ptimer
76
* @callback: function to call on ptimer expiry
77
@@ -XXX,XX +XXX,XX @@ ptimer_state *ptimer_init(ptimer_cb callback,
78
* ptimer_free - Free a ptimer
79
* @s: timer to free
80
*
81
- * Free a ptimer created using ptimer_init_with_bh() (including
82
- * deleting the bottom half which it is using).
83
+ * Free a ptimer created using ptimer_init().
84
*/
85
void ptimer_free(ptimer_state *s);
86
87
@@ -XXX,XX +XXX,XX @@ void ptimer_transaction_commit(ptimer_state *s);
88
* may be more appropriate.
89
*
90
* This function will assert if it is called outside a
91
- * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer.
92
+ * ptimer_transaction_begin/commit block.
93
*/
94
void ptimer_set_period(ptimer_state *s, int64_t period);
95
96
@@ -XXX,XX +XXX,XX @@ void ptimer_set_period(ptimer_state *s, int64_t period);
97
* precise to fractions of a nanosecond, avoiding rounding errors.
98
*
99
* This function will assert if it is called outside a
100
- * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer.
101
+ * ptimer_transaction_begin/commit block.
102
*/
103
void ptimer_set_freq(ptimer_state *s, uint32_t freq);
104
105
@@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_limit(ptimer_state *s);
106
* reload the counter when their reload register is written to.
107
*
108
* This function will assert if it is called outside a
109
- * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer.
110
+ * ptimer_transaction_begin/commit block.
111
*/
112
void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
113
114
@@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_count(ptimer_state *s);
115
* point in the future.
116
*
117
* This function will assert if it is called outside a
118
- * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer.
119
+ * ptimer_transaction_begin/commit block.
120
*/
121
void ptimer_set_count(ptimer_state *s, uint64_t count);
122
123
@@ -XXX,XX +XXX,XX @@ void ptimer_set_count(ptimer_state *s, uint64_t count);
124
* @s: ptimer
125
* @oneshot: non-zero if this timer should only count down once
126
*
127
- * Start a ptimer counting down; when it reaches zero the bottom half
128
- * passed to ptimer_init_with_bh() will be invoked.
129
+ * Start a ptimer counting down; when it reaches zero the callback function
130
+ * passed to ptimer_init() will be invoked.
131
* If the @oneshot argument is zero,
132
* the counter value will then be reloaded from the limit and it will
133
* start counting down again. If @oneshot is non-zero, then the counter
134
* will disable itself when it reaches zero.
135
*
136
* This function will assert if it is called outside a
137
- * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer.
138
+ * ptimer_transaction_begin/commit block.
139
*/
140
void ptimer_run(ptimer_state *s, int oneshot);
141
142
@@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot);
143
* restarted.
144
*
145
* This function will assert if it is called outside a
146
- * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer.
147
+ * ptimer_transaction_begin/commit block.
148
*/
149
void ptimer_stop(ptimer_state *s);
150
151
diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c
152
index XXXXXXX..XXXXXXX 100644
153
--- a/hw/core/ptimer.c
154
+++ b/hw/core/ptimer.c
155
@@ -XXX,XX +XXX,XX @@ struct ptimer_state
156
int64_t last_event;
157
int64_t next_event;
158
uint8_t policy_mask;
159
- QEMUBH *bh;
160
QEMUTimer *timer;
161
ptimer_cb callback;
162
void *callback_opaque;
163
@@ -XXX,XX +XXX,XX @@ struct ptimer_state
164
/* Use a bottom-half routine to avoid reentrancy issues. */
165
static void ptimer_trigger(ptimer_state *s)
166
{
167
- if (s->bh) {
168
- replay_bh_schedule_event(s->bh);
169
- }
170
- if (s->callback) {
171
- s->callback(s->callback_opaque);
172
- }
173
+ s->callback(s->callback_opaque);
174
}
175
176
static void ptimer_reload(ptimer_state *s, int delta_adjust)
177
@@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_count(ptimer_state *s)
178
179
void ptimer_set_count(ptimer_state *s, uint64_t count)
180
{
181
- assert(s->in_transaction || !s->callback);
182
+ assert(s->in_transaction);
183
s->delta = count;
184
if (s->enabled) {
185
- if (!s->callback) {
186
- s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
187
- ptimer_reload(s, 0);
188
- } else {
189
- s->need_reload = true;
190
- }
191
+ s->need_reload = true;
192
}
193
}
194
195
@@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot)
196
{
197
bool was_disabled = !s->enabled;
198
199
- assert(s->in_transaction || !s->callback);
200
+ assert(s->in_transaction);
201
202
if (was_disabled && s->period == 0) {
203
if (!qtest_enabled()) {
204
@@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot)
205
}
206
s->enabled = oneshot ? 2 : 1;
207
if (was_disabled) {
208
- if (!s->callback) {
209
- s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
210
- ptimer_reload(s, 0);
211
- } else {
212
- s->need_reload = true;
213
- }
214
+ s->need_reload = true;
215
}
216
}
217
218
@@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot)
219
is immediately restarted. */
220
void ptimer_stop(ptimer_state *s)
221
{
222
- assert(s->in_transaction || !s->callback);
223
+ assert(s->in_transaction);
224
225
if (!s->enabled)
226
return;
227
@@ -XXX,XX +XXX,XX @@ void ptimer_stop(ptimer_state *s)
228
s->delta = ptimer_get_count(s);
229
timer_del(s->timer);
230
s->enabled = 0;
231
- if (s->callback) {
232
- s->need_reload = false;
233
- }
234
+ s->need_reload = false;
235
}
236
237
/* Set counter increment interval in nanoseconds. */
238
void ptimer_set_period(ptimer_state *s, int64_t period)
239
{
240
- assert(s->in_transaction || !s->callback);
241
+ assert(s->in_transaction);
242
s->delta = ptimer_get_count(s);
243
s->period = period;
244
s->period_frac = 0;
245
if (s->enabled) {
246
- if (!s->callback) {
247
- s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
248
- ptimer_reload(s, 0);
249
- } else {
250
- s->need_reload = true;
251
- }
252
+ s->need_reload = true;
253
}
254
}
255
256
/* Set counter frequency in Hz. */
257
void ptimer_set_freq(ptimer_state *s, uint32_t freq)
258
{
259
- assert(s->in_transaction || !s->callback);
260
+ assert(s->in_transaction);
261
s->delta = ptimer_get_count(s);
262
s->period = 1000000000ll / freq;
263
s->period_frac = (1000000000ll << 32) / freq;
264
if (s->enabled) {
265
- if (!s->callback) {
266
- s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
267
- ptimer_reload(s, 0);
268
- } else {
269
- s->need_reload = true;
270
- }
271
+ s->need_reload = true;
272
}
273
}
274
275
@@ -XXX,XX +XXX,XX @@ void ptimer_set_freq(ptimer_state *s, uint32_t freq)
276
count = limit. */
277
void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload)
278
{
279
- assert(s->in_transaction || !s->callback);
280
+ assert(s->in_transaction);
281
s->limit = limit;
282
if (reload)
283
s->delta = limit;
284
if (s->enabled && reload) {
285
- if (!s->callback) {
286
- s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
287
- ptimer_reload(s, 0);
288
- } else {
289
- s->need_reload = true;
290
- }
291
+ s->need_reload = true;
292
}
293
}
294
295
@@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_limit(ptimer_state *s)
296
297
void ptimer_transaction_begin(ptimer_state *s)
298
{
299
- assert(!s->in_transaction || !s->callback);
300
+ assert(!s->in_transaction);
301
s->in_transaction = true;
302
s->need_reload = false;
303
}
304
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_ptimer = {
305
}
306
};
307
308
-ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask)
309
-{
310
- ptimer_state *s;
311
-
312
- s = (ptimer_state *)g_malloc0(sizeof(ptimer_state));
313
- s->bh = bh;
314
- s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s);
315
- s->policy_mask = policy_mask;
316
-
317
- /*
318
- * These two policies are incompatible -- trigger-on-decrement implies
319
- * a timer trigger when the count becomes 0, but no-immediate-trigger
320
- * implies a trigger when the count stops being 0.
321
- */
322
- assert(!((policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) &&
323
- (policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)));
324
- return s;
325
-}
326
-
327
ptimer_state *ptimer_init(ptimer_cb callback, void *callback_opaque,
328
uint8_t policy_mask)
329
{
330
ptimer_state *s;
331
332
- /*
333
- * The callback function is mandatory; so we use it to distinguish
334
- * old-style QEMUBH ptimers from new transaction API ptimers.
335
- * (ptimer_init_with_bh() allows a NULL bh pointer and at least
336
- * one device (digic-timer) passes NULL, so it's not the case
337
- * that either s->bh != NULL or s->callback != NULL.)
338
- */
339
+ /* The callback function is mandatory. */
340
assert(callback);
341
342
s = g_new0(ptimer_state, 1);
343
@@ -XXX,XX +XXX,XX @@ ptimer_state *ptimer_init(ptimer_cb callback, void *callback_opaque,
344
345
void ptimer_free(ptimer_state *s)
346
{
347
- if (s->bh) {
348
- qemu_bh_delete(s->bh);
349
- }
350
timer_free(s->timer);
351
g_free(s);
352
}
353
--
354
2.20.1
355
356
diff view generated by jsdifflib
[PULL 2/3] Remove unassigned_access CPU hook
Deleted patch
1
All targets have now migrated away from the old unassigned_access
2
hook to the new do_transaction_failed hook. This means we can remove
3
the core-code infrastructure for that hook and the code that calls it.
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20191108173732.11816-1-peter.maydell@linaro.org
9
---
10
include/hw/core/cpu.h | 24 ------------------------
11
accel/tcg/cputlb.c | 2 --
12
memory.c | 7 -------
13
3 files changed, 33 deletions(-)
14
15
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/core/cpu.h
18
+++ b/include/hw/core/cpu.h
19
@@ -XXX,XX +XXX,XX @@ typedef enum MMUAccessType {
20
21
typedef struct CPUWatchpoint CPUWatchpoint;
22
23
-typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
24
- bool is_write, bool is_exec, int opaque,
25
- unsigned size);
26
-
27
struct TranslationBlock;
28
29
/**
30
@@ -XXX,XX +XXX,XX @@ struct TranslationBlock;
31
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
32
* @has_work: Callback for checking if there is work to do.
33
* @do_interrupt: Callback for interrupt handling.
34
- * @do_unassigned_access: Callback for unassigned access handling.
35
- * (this is deprecated: new targets should use do_transaction_failed instead)
36
* @do_unaligned_access: Callback for unaligned access handling, if
37
* the target defines #TARGET_ALIGNED_ONLY.
38
* @do_transaction_failed: Callback for handling failed memory transactions
39
@@ -XXX,XX +XXX,XX @@ typedef struct CPUClass {
40
int reset_dump_flags;
41
bool (*has_work)(CPUState *cpu);
42
void (*do_interrupt)(CPUState *cpu);
43
- CPUUnassignedAccess do_unassigned_access;
44
void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
45
MMUAccessType access_type,
46
int mmu_idx, uintptr_t retaddr);
47
@@ -XXX,XX +XXX,XX @@ struct CPUState {
48
* we store some rarely used information in the CPU context.
49
*/
50
uintptr_t mem_io_pc;
51
- /*
52
- * This is only needed for the legacy cpu_unassigned_access() hook;
53
- * when all targets using it have been converted to use
54
- * cpu_transaction_failed() instead it can be removed.
55
- */
56
- MMUAccessType mem_io_access_type;
57
58
int kvm_fd;
59
struct KVMState *kvm_state;
60
@@ -XXX,XX +XXX,XX @@ void cpu_interrupt(CPUState *cpu, int mask);
61
#ifdef NEED_CPU_H
62
63
#ifdef CONFIG_SOFTMMU
64
-static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
65
- bool is_write, bool is_exec,
66
- int opaque, unsigned size)
67
-{
68
- CPUClass *cc = CPU_GET_CLASS(cpu);
69
-
70
- if (cc->do_unassigned_access) {
71
- cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
72
- }
73
-}
74
-
75
static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
76
MMUAccessType access_type,
77
int mmu_idx, uintptr_t retaddr)
78
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/accel/tcg/cputlb.c
81
+++ b/accel/tcg/cputlb.c
82
@@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
83
cpu_io_recompile(cpu, retaddr);
84
}
85
86
- cpu->mem_io_access_type = access_type;
87
-
88
if (mr->global_locking && !qemu_mutex_iothread_locked()) {
89
qemu_mutex_lock_iothread();
90
locked = true;
91
diff --git a/memory.c b/memory.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/memory.c
94
+++ b/memory.c
95
@@ -XXX,XX +XXX,XX @@ static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
96
#ifdef DEBUG_UNASSIGNED
97
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
98
#endif
99
- if (current_cpu != NULL) {
100
- bool is_exec = current_cpu->mem_io_access_type == MMU_INST_FETCH;
101
- cpu_unassigned_access(current_cpu, addr, false, is_exec, 0, size);
102
- }
103
return 0;
104
}
105
106
@@ -XXX,XX +XXX,XX @@ static void unassigned_mem_write(void *opaque, hwaddr addr,
107
#ifdef DEBUG_UNASSIGNED
108
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
109
#endif
110
- if (current_cpu != NULL) {
111
- cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
112
- }
113
}
114
115
static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
116
--
117
2.20.1
118
119
diff view generated by jsdifflib
[PULL 3/3] hw/arm/boot: Set NSACR.{CP11, CP10} in dummy SMC setup routine
Deleted patch
1
From: Clement Deschamps <clement.deschamps@greensocs.com>
2
1
3
The boot.c code usually puts the CPU into NS mode directly when it is
4
booting a kernel. Since fc1120a7f5f2d4b6 this has included a
5
requirement to set NSACR to give NS state access to the FPU; we fixed
6
that for the usual code path in ece628fcf6. However, it is also
7
possible for a board model to request an alternative mode of booting,
8
where its 'board_setup' code hook runs in Secure state and is
9
responsible for doing the S->NS transition after it has done whatever
10
work it must do in Secure state. In this situation the board_setup
11
code now also needs to update NSACR.
12
13
This affects all boards which set info->secure_board_setup, which is
14
currently the 'raspi' and 'highbank' families. They both use the
15
common arm_write_secure_board_setup_dummy_smc().
16
17
Set the NSACR CP11 and CP10 bits in the code written by that
18
function, to allow FPU access in Non-Secure state when using dummy
19
SMC setup routine. Otherwise an AArch32 kernel booted on the
20
highbank or raspi boards will UNDEF as soon as it tries to use the
21
FPU.
22
23
Update the comment describing secure_board_setup to note the new
24
requirements on users of it.
25
26
This fixes a kernel panic when booting raspbian on raspi2.
27
28
Successfully tested with:
29
2017-01-11-raspbian-jessie-lite.img
30
2018-11-13-raspbian-stretch-lite.img
31
2019-07-10-raspbian-buster-lite.img
32
33
Fixes: fc1120a7f5
34
Signed-off-by: Clement Deschamps <clement.deschamps@greensocs.com>
35
Tested-by: Laurent Bonnans <laurent.bonnans@here.com>
36
Message-id: 20191104151137.81931-1-clement.deschamps@greensocs.com
37
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
38
[PMM: updated comment to boot.h to note new requirement on
39
users of secure_board_setup; edited/rewrote commit message]
40
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
41
---
42
include/hw/arm/boot.h | 7 +++++--
43
hw/arm/boot.c | 3 +++
44
2 files changed, 8 insertions(+), 2 deletions(-)
45
46
diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/include/hw/arm/boot.h
49
+++ b/include/hw/arm/boot.h
50
@@ -XXX,XX +XXX,XX @@ struct arm_boot_info {
51
void (*write_board_setup)(ARMCPU *cpu,
52
const struct arm_boot_info *info);
53
54
- /* If set, the board specific loader/setup blob will be run from secure
55
+ /*
56
+ * If set, the board specific loader/setup blob will be run from secure
57
* mode, regardless of secure_boot. The blob becomes responsible for
58
- * changing to non-secure state if implementing a non-secure boot
59
+ * changing to non-secure state if implementing a non-secure boot,
60
+ * including setting up EL3/Secure registers such as the NSACR as
61
+ * required by the Linux booting ABI before the switch to non-secure.
62
*/
63
bool secure_board_setup;
64
65
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/hw/arm/boot.c
68
+++ b/hw/arm/boot.c
69
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
70
};
71
uint32_t board_setup_blob[] = {
72
/* board setup addr */
73
+ 0xee110f51, /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */
74
+ 0xe3800b03, /* orr r0, #0xc00 ;set CP11, CP10 */
75
+ 0xee010f51, /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */
76
0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */
77
0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */
78
0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */
79
--
80
2.20.1
81
82
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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