1 | Arm patches for rc1: | 1 | Nothing too exciting, but does include the last bits of v8.1M support work. |
---|---|---|---|
2 | * two final "remove the old API" patches for some API transitions | ||
3 | * bugfix for raspi/highbank Linux boot | ||
4 | 2 | ||
5 | thanks | ||
6 | -- PMM | 3 | -- PMM |
7 | 4 | ||
8 | The following changes since commit 654efcb511d394c1d3f5292c28503d1d19e5b1d3: | 5 | The following changes since commit e79de63ab1bd1f6550e7b915e433bec1ad1a870a: |
9 | 6 | ||
10 | Merge remote-tracking branch 'remotes/vivier/tags/q800-branch-pull-request' into staging (2019-11-11 09:23:46 +0000) | 7 | Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210107' into staging (2021-01-07 20:34:05 +0000) |
11 | 8 | ||
12 | are available in the Git repository at: | 9 | are available in the Git repository at: |
13 | 10 | ||
14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191111 | 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210108 |
15 | 12 | ||
16 | for you to fetch changes up to 45c078f163fd47c35e7505d98928fae63baada7d: | 13 | for you to fetch changes up to c9f8511ea8d2b80723af0fea1f716d752c1b5208: |
17 | 14 | ||
18 | hw/arm/boot: Set NSACR.{CP11, CP10} in dummy SMC setup routine (2019-11-11 13:44:16 +0000) | 15 | docs/system: arm: Add sabrelite board description (2021-01-08 15:13:39 +0000) |
19 | 16 | ||
20 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
21 | target-arm queue: | 18 | target-arm queue: |
22 | * Remove old unassigned_access CPU hook API | 19 | * intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs |
23 | * Remove old ptimer_init_with_bh() API | 20 | * target/arm: Fix MTE0_ACTIVE |
24 | * hw/arm/boot: Set NSACR.{CP11, CP10} in dummy SMC setup routine | 21 | * target/arm: Implement v8.1M and Cortex-M55 model |
22 | * hw/arm/highbank: Drop dead KVM support code | ||
23 | * util/qemu-timer: Make timer_free() imply timer_del() | ||
24 | * various devices: Use ptimer_free() in finalize function | ||
25 | * docs/system: arm: Add sabrelite board description | ||
26 | * sabrelite: Minor fixes to allow booting U-Boot | ||
25 | 27 | ||
26 | ---------------------------------------------------------------- | 28 | ---------------------------------------------------------------- |
27 | Clement Deschamps (1): | 29 | Andrew Jones (1): |
28 | hw/arm/boot: Set NSACR.{CP11, CP10} in dummy SMC setup routine | 30 | hw/arm/virt: Remove virt machine state 'smp_cpus' |
29 | 31 | ||
30 | Peter Maydell (2): | 32 | Bin Meng (4): |
31 | ptimer: Remove old ptimer_init_with_bh() API | 33 | hw/misc: imx6_ccm: Update PMU_MISC0 reset value |
32 | Remove unassigned_access CPU hook | 34 | hw/msic: imx6_ccm: Correct register value for silicon type |
35 | hw/arm: sabrelite: Connect the Ethernet PHY at address 6 | ||
36 | docs/system: arm: Add sabrelite board description | ||
33 | 37 | ||
34 | include/hw/arm/boot.h | 7 ++-- | 38 | Edgar E. Iglesias (1): |
35 | include/hw/core/cpu.h | 24 -------------- | 39 | intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs |
36 | include/hw/ptimer.h | 45 ++++++++++++------------- | ||
37 | accel/tcg/cputlb.c | 2 -- | ||
38 | hw/arm/boot.c | 3 ++ | ||
39 | hw/core/ptimer.c | 91 +++++++++------------------------------------------ | ||
40 | memory.c | 7 ---- | ||
41 | 7 files changed, 44 insertions(+), 135 deletions(-) | ||
42 | 40 | ||
41 | Gan Qixin (7): | ||
42 | digic-timer: Use ptimer_free() in the finalize function to avoid memleaks | ||
43 | allwinner-a10-pit: Use ptimer_free() in the finalize function to avoid memleaks | ||
44 | exynos4210_rtc: Use ptimer_free() in the finalize function to avoid memleaks | ||
45 | exynos4210_pwm: Use ptimer_free() in the finalize function to avoid memleaks | ||
46 | mss-timer: Use ptimer_free() in the finalize function to avoid memleaks | ||
47 | musicpal: Use ptimer_free() in the finalize function to avoid memleaks | ||
48 | exynos4210_mct: Use ptimer_free() in the finalize function to avoid memleaks | ||
49 | |||
50 | Peter Maydell (9): | ||
51 | hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN | ||
52 | target/arm: Correct store of FPSCR value via FPCXT_S | ||
53 | target/arm: Implement FPCXT_NS fp system register | ||
54 | target/arm: Implement Cortex-M55 model | ||
55 | hw/arm/highbank: Drop dead KVM support code | ||
56 | util/qemu-timer: Make timer_free() imply timer_del() | ||
57 | scripts/coccinelle: New script to remove unnecessary timer_del() calls | ||
58 | Remove superfluous timer_del() calls | ||
59 | target/arm: Remove timer_del()/timer_deinit() before timer_free() | ||
60 | |||
61 | Richard Henderson (1): | ||
62 | target/arm: Fix MTE0_ACTIVE | ||
63 | |||
64 | docs/system/arm/sabrelite.rst | 119 ++++++++++++++++++++++++++ | ||
65 | docs/system/target-arm.rst | 1 + | ||
66 | scripts/coccinelle/timer-del-timer-free.cocci | 18 ++++ | ||
67 | include/hw/arm/virt.h | 3 +- | ||
68 | include/qemu/timer.h | 24 +++--- | ||
69 | block/iscsi.c | 2 - | ||
70 | block/nbd.c | 1 - | ||
71 | block/qcow2.c | 1 - | ||
72 | hw/arm/highbank.c | 14 +-- | ||
73 | hw/arm/musicpal.c | 12 +++ | ||
74 | hw/arm/sabrelite.c | 4 + | ||
75 | hw/arm/virt-acpi-build.c | 9 +- | ||
76 | hw/arm/virt.c | 21 +++-- | ||
77 | hw/block/nvme.c | 2 - | ||
78 | hw/char/serial.c | 2 - | ||
79 | hw/char/virtio-serial-bus.c | 2 - | ||
80 | hw/ide/core.c | 1 - | ||
81 | hw/input/hid.c | 1 - | ||
82 | hw/intc/apic.c | 1 - | ||
83 | hw/intc/arm_gic.c | 4 +- | ||
84 | hw/intc/armv7m_nvic.c | 15 ++++ | ||
85 | hw/intc/ioapic.c | 1 - | ||
86 | hw/ipmi/ipmi_bmc_extern.c | 1 - | ||
87 | hw/misc/imx6_ccm.c | 4 +- | ||
88 | hw/net/e1000.c | 3 - | ||
89 | hw/net/e1000e_core.c | 8 -- | ||
90 | hw/net/pcnet-pci.c | 1 - | ||
91 | hw/net/rtl8139.c | 1 - | ||
92 | hw/net/spapr_llan.c | 1 - | ||
93 | hw/net/virtio-net.c | 2 - | ||
94 | hw/rtc/exynos4210_rtc.c | 9 ++ | ||
95 | hw/s390x/s390-pci-inst.c | 1 - | ||
96 | hw/sd/sd.c | 1 - | ||
97 | hw/sd/sdhci.c | 2 - | ||
98 | hw/timer/allwinner-a10-pit.c | 11 +++ | ||
99 | hw/timer/digic-timer.c | 8 ++ | ||
100 | hw/timer/exynos4210_mct.c | 14 +++ | ||
101 | hw/timer/exynos4210_pwm.c | 11 +++ | ||
102 | hw/timer/mss-timer.c | 13 +++ | ||
103 | hw/usb/dev-hub.c | 1 - | ||
104 | hw/usb/hcd-ehci.c | 1 - | ||
105 | hw/usb/hcd-ohci-pci.c | 1 - | ||
106 | hw/usb/hcd-uhci.c | 1 - | ||
107 | hw/usb/hcd-xhci.c | 1 - | ||
108 | hw/usb/redirect.c | 1 - | ||
109 | hw/vfio/display.c | 1 - | ||
110 | hw/virtio/vhost-vsock-common.c | 1 - | ||
111 | hw/virtio/virtio-balloon.c | 1 - | ||
112 | hw/virtio/virtio-rng.c | 1 - | ||
113 | hw/watchdog/wdt_diag288.c | 1 - | ||
114 | hw/watchdog/wdt_i6300esb.c | 1 - | ||
115 | migration/colo.c | 1 - | ||
116 | monitor/hmp-cmds.c | 1 - | ||
117 | net/announce.c | 1 - | ||
118 | net/colo-compare.c | 1 - | ||
119 | net/slirp.c | 1 - | ||
120 | replay/replay-debugging.c | 1 - | ||
121 | target/arm/cpu.c | 2 - | ||
122 | target/arm/cpu_tcg.c | 42 +++++++++ | ||
123 | target/arm/helper.c | 2 +- | ||
124 | target/s390x/cpu.c | 2 - | ||
125 | ui/console.c | 1 - | ||
126 | ui/spice-core.c | 1 - | ||
127 | util/throttle.c | 1 - | ||
128 | target/arm/translate-vfp.c.inc | 114 ++++++++++++++++++++++-- | ||
129 | 65 files changed, 421 insertions(+), 111 deletions(-) | ||
130 | create mode 100644 docs/system/arm/sabrelite.rst | ||
131 | create mode 100644 scripts/coccinelle/timer-del-timer-free.cocci | ||
132 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | ||
1 | 2 | ||
3 | Correct the indexing into s->cpu_ctlr for vCPUs. | ||
4 | |||
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | ||
8 | Message-id: 20201214222154.3480243-2-edgar.iglesias@gmail.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | hw/intc/arm_gic.c | 4 +++- | ||
12 | 1 file changed, 3 insertions(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/intc/arm_gic.c | ||
17 | +++ b/hw/intc/arm_gic.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static inline void gic_get_best_virq(GICState *s, int cpu, | ||
19 | static inline bool gic_irq_signaling_enabled(GICState *s, int cpu, bool virt, | ||
20 | int group_mask) | ||
21 | { | ||
22 | + int cpu_iface = virt ? (cpu + GIC_NCPU) : cpu; | ||
23 | + | ||
24 | if (!virt && !(s->ctlr & group_mask)) { | ||
25 | return false; | ||
26 | } | ||
27 | @@ -XXX,XX +XXX,XX @@ static inline bool gic_irq_signaling_enabled(GICState *s, int cpu, bool virt, | ||
28 | return false; | ||
29 | } | ||
30 | |||
31 | - if (!(s->cpu_ctlr[cpu] & group_mask)) { | ||
32 | + if (!(s->cpu_ctlr[cpu_iface] & group_mask)) { | ||
33 | return false; | ||
34 | } | ||
35 | |||
36 | -- | ||
37 | 2.20.1 | ||
38 | |||
39 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Andrew Jones <drjones@redhat.com> | ||
1 | 2 | ||
3 | virt machine's 'smp_cpus' and machine->smp.cpus must always have the | ||
4 | same value. And, anywhere we have virt machine state we have machine | ||
5 | state. So let's remove the redundancy. Also, to make it easier to see | ||
6 | that machine->smp is the true source for "smp_cpus" and "max_cpus", | ||
7 | avoid passing them in function parameters, preferring instead to get | ||
8 | them from the state. | ||
9 | |||
10 | No functional change intended. | ||
11 | |||
12 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
13 | Reviewed-by: David Edmondson <david.edmondson@oracle.com> | ||
14 | Reviewed-by: Ying Fang <fangying1@huawei.com> | ||
15 | Message-id: 20201215174815.51520-1-drjones@redhat.com | ||
16 | [PMM: minor formatting tweak to smp_cpus variable declaration] | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | --- | ||
19 | include/hw/arm/virt.h | 3 +-- | ||
20 | hw/arm/virt-acpi-build.c | 9 +++++---- | ||
21 | hw/arm/virt.c | 21 ++++++++++----------- | ||
22 | 3 files changed, 16 insertions(+), 17 deletions(-) | ||
23 | |||
24 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/include/hw/arm/virt.h | ||
27 | +++ b/include/hw/arm/virt.h | ||
28 | @@ -XXX,XX +XXX,XX @@ struct VirtMachineState { | ||
29 | MemMapEntry *memmap; | ||
30 | char *pciehb_nodename; | ||
31 | const int *irqmap; | ||
32 | - int smp_cpus; | ||
33 | void *fdt; | ||
34 | int fdt_size; | ||
35 | uint32_t clock_phandle; | ||
36 | @@ -XXX,XX +XXX,XX @@ static inline int virt_gicv3_redist_region_count(VirtMachineState *vms) | ||
37 | |||
38 | assert(vms->gic_version == VIRT_GIC_VERSION_3); | ||
39 | |||
40 | - return vms->smp_cpus > redist0_capacity ? 2 : 1; | ||
41 | + return MACHINE(vms)->smp.cpus > redist0_capacity ? 2 : 1; | ||
42 | } | ||
43 | |||
44 | #endif /* QEMU_ARM_VIRT_H */ | ||
45 | diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/hw/arm/virt-acpi-build.c | ||
48 | +++ b/hw/arm/virt-acpi-build.c | ||
49 | @@ -XXX,XX +XXX,XX @@ | ||
50 | |||
51 | #define ACPI_BUILD_TABLE_SIZE 0x20000 | ||
52 | |||
53 | -static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) | ||
54 | +static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms) | ||
55 | { | ||
56 | + MachineState *ms = MACHINE(vms); | ||
57 | uint16_t i; | ||
58 | |||
59 | - for (i = 0; i < smp_cpus; i++) { | ||
60 | + for (i = 0; i < ms->smp.cpus; i++) { | ||
61 | Aml *dev = aml_device("C%.03X", i); | ||
62 | aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); | ||
63 | aml_append(dev, aml_name_decl("_UID", aml_int(i))); | ||
64 | @@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | ||
65 | gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base); | ||
66 | gicd->version = vms->gic_version; | ||
67 | |||
68 | - for (i = 0; i < vms->smp_cpus; i++) { | ||
69 | + for (i = 0; i < MACHINE(vms)->smp.cpus; i++) { | ||
70 | AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data, | ||
71 | sizeof(*gicc)); | ||
72 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); | ||
73 | @@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | ||
74 | * the RTC ACPI device at all when using UEFI. | ||
75 | */ | ||
76 | scope = aml_scope("\\_SB"); | ||
77 | - acpi_dsdt_add_cpus(scope, vms->smp_cpus); | ||
78 | + acpi_dsdt_add_cpus(scope, vms); | ||
79 | acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], | ||
80 | (irqmap[VIRT_UART] + ARM_SPI_BASE)); | ||
81 | if (vmc->acpi_expose_flash) { | ||
82 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
83 | index XXXXXXX..XXXXXXX 100644 | ||
84 | --- a/hw/arm/virt.c | ||
85 | +++ b/hw/arm/virt.c | ||
86 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms) | ||
87 | if (vms->gic_version == VIRT_GIC_VERSION_2) { | ||
88 | irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, | ||
89 | GIC_FDT_IRQ_PPI_CPU_WIDTH, | ||
90 | - (1 << vms->smp_cpus) - 1); | ||
91 | + (1 << MACHINE(vms)->smp.cpus) - 1); | ||
92 | } | ||
93 | |||
94 | qemu_fdt_add_subnode(vms->fdt, "/timer"); | ||
95 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms) | ||
96 | int cpu; | ||
97 | int addr_cells = 1; | ||
98 | const MachineState *ms = MACHINE(vms); | ||
99 | + int smp_cpus = ms->smp.cpus; | ||
100 | |||
101 | /* | ||
102 | * From Documentation/devicetree/bindings/arm/cpus.txt | ||
103 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms) | ||
104 | * The simplest way to go is to examine affinity IDs of all our CPUs. If | ||
105 | * at least one of them has Aff3 populated, we set #address-cells to 2. | ||
106 | */ | ||
107 | - for (cpu = 0; cpu < vms->smp_cpus; cpu++) { | ||
108 | + for (cpu = 0; cpu < smp_cpus; cpu++) { | ||
109 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); | ||
110 | |||
111 | if (armcpu->mp_affinity & ARM_AFF3_MASK) { | ||
112 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms) | ||
113 | qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); | ||
114 | qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); | ||
115 | |||
116 | - for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { | ||
117 | + for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { | ||
118 | char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); | ||
119 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); | ||
120 | CPUState *cs = CPU(armcpu); | ||
121 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms) | ||
122 | qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", | ||
123 | armcpu->dtb_compatible); | ||
124 | |||
125 | - if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED | ||
126 | - && vms->smp_cpus > 1) { | ||
127 | + if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { | ||
128 | qemu_fdt_setprop_string(vms->fdt, nodename, | ||
129 | "enable-method", "psci"); | ||
130 | } | ||
131 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms) | ||
132 | if (vms->gic_version == VIRT_GIC_VERSION_2) { | ||
133 | irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, | ||
134 | GIC_FDT_IRQ_PPI_CPU_WIDTH, | ||
135 | - (1 << vms->smp_cpus) - 1); | ||
136 | + (1 << MACHINE(vms)->smp.cpus) - 1); | ||
137 | } | ||
138 | |||
139 | qemu_fdt_add_subnode(vms->fdt, "/pmu"); | ||
140 | @@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms) | ||
141 | * virt_cpu_post_init() must be called after the CPUs have | ||
142 | * been realized and the GIC has been created. | ||
143 | */ | ||
144 | -static void virt_cpu_post_init(VirtMachineState *vms, int max_cpus, | ||
145 | - MemoryRegion *sysmem) | ||
146 | +static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) | ||
147 | { | ||
148 | + int max_cpus = MACHINE(vms)->smp.max_cpus; | ||
149 | bool aarch64, pmu, steal_time; | ||
150 | CPUState *cpu; | ||
151 | |||
152 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
153 | exit(1); | ||
154 | } | ||
155 | |||
156 | - vms->smp_cpus = smp_cpus; | ||
157 | - | ||
158 | if (vms->virt && kvm_enabled()) { | ||
159 | error_report("mach-virt: KVM does not support providing " | ||
160 | "Virtualization extensions to the guest CPU"); | ||
161 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
162 | create_fdt(vms); | ||
163 | |||
164 | possible_cpus = mc->possible_cpu_arch_ids(machine); | ||
165 | + assert(possible_cpus->len == max_cpus); | ||
166 | for (n = 0; n < possible_cpus->len; n++) { | ||
167 | Object *cpuobj; | ||
168 | CPUState *cs; | ||
169 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
170 | |||
171 | create_gic(vms); | ||
172 | |||
173 | - virt_cpu_post_init(vms, possible_cpus->len, sysmem); | ||
174 | + virt_cpu_post_init(vms, sysmem); | ||
175 | |||
176 | fdt_add_pmu_nodes(vms); | ||
177 | |||
178 | -- | ||
179 | 2.20.1 | ||
180 | |||
181 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | In 50244cc76abc we updated mte_check_fail to match the ARM | ||
4 | pseudocode, using the correct EL to select the TCF field. | ||
5 | But we failed to update MTE0_ACTIVE the same way, which led | ||
6 | to g_assert_not_reached(). | ||
7 | |||
8 | Cc: qemu-stable@nongnu.org | ||
9 | Buglink: https://bugs.launchpad.net/bugs/1907137 | ||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20201221204426.88514-1-richard.henderson@linaro.org | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | target/arm/helper.c | 2 +- | ||
16 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
17 | |||
18 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/arm/helper.c | ||
21 | +++ b/target/arm/helper.c | ||
22 | @@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, | ||
23 | if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV) | ||
24 | && tbid | ||
25 | && !(env->pstate & PSTATE_TCO) | ||
26 | - && (sctlr & SCTLR_TCF0) | ||
27 | + && (sctlr & SCTLR_TCF) | ||
28 | && allocation_tag_access_enabled(env, 0, sctlr)) { | ||
29 | flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1); | ||
30 | } | ||
31 | -- | ||
32 | 2.20.1 | ||
33 | |||
34 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The CCR is a register most of whose bits are banked between security | ||
2 | states but where BFHFNMIGN is not, and we keep it in the non-secure | ||
3 | entry of the v7m.ccr[] array. The logic which tries to handle this | ||
4 | bit fails to implement the "RAZ/WI from Nonsecure if AIRCR.BFHFNMINS | ||
5 | is zero" requirement; correct the omission. | ||
1 | 6 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20201210201433.26262-2-peter.maydell@linaro.org | ||
10 | --- | ||
11 | hw/intc/armv7m_nvic.c | 15 +++++++++++++++ | ||
12 | 1 file changed, 15 insertions(+) | ||
13 | |||
14 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/intc/armv7m_nvic.c | ||
17 | +++ b/hw/intc/armv7m_nvic.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | ||
19 | */ | ||
20 | val = cpu->env.v7m.ccr[attrs.secure]; | ||
21 | val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; | ||
22 | + /* BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0 */ | ||
23 | + if (!attrs.secure) { | ||
24 | + if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { | ||
25 | + val &= ~R_V7M_CCR_BFHFNMIGN_MASK; | ||
26 | + } | ||
27 | + } | ||
28 | return val; | ||
29 | case 0xd24: /* System Handler Control and State (SHCSR) */ | ||
30 | if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { | ||
31 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
32 | (cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK) | ||
33 | | (value & R_V7M_CCR_BFHFNMIGN_MASK); | ||
34 | value &= ~R_V7M_CCR_BFHFNMIGN_MASK; | ||
35 | + } else { | ||
36 | + /* | ||
37 | + * BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0, so | ||
38 | + * preserve the state currently in the NS element of the array | ||
39 | + */ | ||
40 | + if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { | ||
41 | + value &= ~R_V7M_CCR_BFHFNMIGN_MASK; | ||
42 | + value |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; | ||
43 | + } | ||
44 | } | ||
45 | |||
46 | cpu->env.v7m.ccr[attrs.secure] = value; | ||
47 | -- | ||
48 | 2.20.1 | ||
49 | |||
50 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In commit 64f863baeedc8659 we implemented the v8.1M FPCXT_S register, | ||
2 | but we got the write behaviour wrong. On read, this register reads | ||
3 | bits [27:0] of FPSCR plus the CONTROL.SFPA bit. On write, it doesn't | ||
4 | just write back those bits -- it writes a value to the whole FPSCR, | ||
5 | whose upper 4 bits are zeroes. | ||
1 | 6 | ||
7 | We also incorrectly implemented the write-to-FPSCR as a simple store | ||
8 | to vfp.xregs; this skips the "update the softfloat flags" part of | ||
9 | the vfp_set_fpscr helper so the value would read back correctly but | ||
10 | not actually take effect. | ||
11 | |||
12 | Fix both of these things by doing a complete write to the FPSCR | ||
13 | using the helper function. | ||
14 | |||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
17 | Message-id: 20201210201433.26262-3-peter.maydell@linaro.org | ||
18 | --- | ||
19 | target/arm/translate-vfp.c.inc | 12 ++++++------ | ||
20 | 1 file changed, 6 insertions(+), 6 deletions(-) | ||
21 | |||
22 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/target/arm/translate-vfp.c.inc | ||
25 | +++ b/target/arm/translate-vfp.c.inc | ||
26 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
27 | } | ||
28 | case ARM_VFP_FPCXT_S: | ||
29 | { | ||
30 | - TCGv_i32 sfpa, control, fpscr; | ||
31 | - /* Set FPSCR[27:0] and CONTROL.SFPA from value */ | ||
32 | + TCGv_i32 sfpa, control; | ||
33 | + /* | ||
34 | + * Set FPSCR and CONTROL.SFPA from value; the new FPSCR takes | ||
35 | + * bits [27:0] from value and zeroes bits [31:28]. | ||
36 | + */ | ||
37 | tmp = loadfn(s, opaque); | ||
38 | sfpa = tcg_temp_new_i32(); | ||
39 | tcg_gen_shri_i32(sfpa, tmp, 31); | ||
40 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
41 | tcg_gen_deposit_i32(control, control, sfpa, | ||
42 | R_V7M_CONTROL_SFPA_SHIFT, 1); | ||
43 | store_cpu_field(control, v7m.control[M_REG_S]); | ||
44 | - fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); | ||
45 | - tcg_gen_andi_i32(fpscr, fpscr, FPCR_NZCV_MASK); | ||
46 | tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); | ||
47 | - tcg_gen_or_i32(fpscr, fpscr, tmp); | ||
48 | - store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]); | ||
49 | + gen_helper_vfp_set_fpscr(cpu_env, tmp); | ||
50 | tcg_temp_free_i32(tmp); | ||
51 | tcg_temp_free_i32(sfpa); | ||
52 | break; | ||
53 | -- | ||
54 | 2.20.1 | ||
55 | |||
56 | diff view generated by jsdifflib |
1 | Now all the users of ptimers have converted to the transaction-based | 1 | Implement the v8.1M FPCXT_NS floating-point system register. This is |
---|---|---|---|
2 | API, we can remove ptimer_init_with_bh() and all the code paths | 2 | a little more complicated than FPCXT_S, because it has specific |
3 | that are used only by bottom-half based ptimers, and tidy up the | 3 | handling for "current FP state is inactive", and it only wants to do |
4 | documentation comments to consider the transaction-based API the | 4 | PreserveFPState(), not the full set of actions done by |
5 | only possibility. | 5 | ExecuteFPCheck() which vfp_access_check() implements. |
6 | |||
7 | The code changes result from: | ||
8 | * s->bh no longer exists | ||
9 | * s->callback is now always non-NULL | ||
10 | 6 | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
13 | Message-id: 20191025142411.17085-1-peter.maydell@linaro.org | 9 | Message-id: 20201210201433.26262-4-peter.maydell@linaro.org |
14 | --- | 10 | --- |
15 | include/hw/ptimer.h | 45 +++++++++++----------- | 11 | target/arm/translate-vfp.c.inc | 102 ++++++++++++++++++++++++++++++++- |
16 | hw/core/ptimer.c | 91 ++++++++------------------------------------- | 12 | 1 file changed, 99 insertions(+), 3 deletions(-) |
17 | 2 files changed, 36 insertions(+), 100 deletions(-) | ||
18 | 13 | ||
19 | diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h | 14 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc |
20 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/include/hw/ptimer.h | 16 | --- a/target/arm/translate-vfp.c.inc |
22 | +++ b/include/hw/ptimer.h | 17 | +++ b/target/arm/translate-vfp.c.inc |
23 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno) |
24 | 19 | } | |
25 | #include "qemu/timer.h" | 20 | break; |
26 | 21 | case ARM_VFP_FPCXT_S: | |
27 | -/* The ptimer API implements a simple periodic countdown timer. | 22 | + case ARM_VFP_FPCXT_NS: |
28 | +/* | 23 | if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { |
29 | + * The ptimer API implements a simple periodic countdown timer. | 24 | return false; |
30 | * The countdown timer has a value (which can be read and written via | 25 | } |
31 | * ptimer_get_count() and ptimer_set_count()). When it is enabled | 26 | @@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno) |
32 | * using ptimer_run(), the value will count downwards at the frequency | 27 | return FPSysRegCheckFailed; |
33 | * which has been configured using ptimer_set_period() or ptimer_set_freq(). | 28 | } |
34 | - * When it reaches zero it will trigger a QEMU bottom half handler, and | 29 | |
35 | + * When it reaches zero it will trigger a callback function, and | 30 | - if (!vfp_access_check(s)) { |
36 | * can be set to either reload itself from a specified limit value | 31 | + /* |
37 | * and keep counting down, or to stop (as a one-shot timer). | 32 | + * FPCXT_NS is a special case: it has specific handling for |
38 | * | 33 | + * "current FP state is inactive", and must do the PreserveFPState() |
39 | + * A transaction-based API is used for modifying ptimer state: all calls | 34 | + * but not the usual full set of actions done by ExecuteFPCheck(). |
40 | + * to functions which modify ptimer state must be between matched calls to | 35 | + * So we don't call vfp_access_check() and the callers must handle this. |
41 | + * ptimer_transaction_begin() and ptimer_transaction_commit(). | 36 | + */ |
42 | + * When ptimer_transaction_commit() is called it will evaluate the state | 37 | + if (regno != ARM_VFP_FPCXT_NS && !vfp_access_check(s)) { |
43 | + * of the timer after all the changes in the transaction, and call the | 38 | return FPSysRegCheckDone; |
44 | + * callback if necessary. (See the ptimer_init() documentation for the full | 39 | } |
45 | + * list of state-modifying functions and detailed semantics of the callback.) | ||
46 | + * | ||
47 | * Forgetting to set the period/frequency (or setting it to zero) is a | ||
48 | * bug in the QEMU device and will cause warning messages to be printed | ||
49 | * to stderr when the guest attempts to enable the timer. | ||
50 | @@ -XXX,XX +XXX,XX @@ | ||
51 | * ptimer_set_count() or ptimer_set_limit() will not trigger the timer | ||
52 | * (though it will cause a reload). Only a counter decrement to "0" | ||
53 | * will cause a trigger. Not compatible with NO_IMMEDIATE_TRIGGER; | ||
54 | - * ptimer_init_with_bh() will assert() that you don't set both. | ||
55 | + * ptimer_init() will assert() that you don't set both. | ||
56 | */ | ||
57 | #define PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT (1 << 5) | ||
58 | |||
59 | @@ -XXX,XX +XXX,XX @@ | ||
60 | typedef struct ptimer_state ptimer_state; | ||
61 | typedef void (*ptimer_cb)(void *opaque); | ||
62 | |||
63 | -/** | ||
64 | - * ptimer_init_with_bh - Allocate and return a new ptimer | ||
65 | - * @bh: QEMU bottom half which is run on timer expiry | ||
66 | - * @policy: PTIMER_POLICY_* bits specifying behaviour | ||
67 | - * | ||
68 | - * The ptimer returned must be freed using ptimer_free(). | ||
69 | - * The ptimer takes ownership of @bh and will delete it | ||
70 | - * when the ptimer is eventually freed. | ||
71 | - */ | ||
72 | -ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask); | ||
73 | - | 40 | - |
74 | /** | 41 | return FPSysRegCheckContinue; |
75 | * ptimer_init - Allocate and return a new ptimer | 42 | } |
76 | * @callback: function to call on ptimer expiry | 43 | |
77 | @@ -XXX,XX +XXX,XX @@ ptimer_state *ptimer_init(ptimer_cb callback, | 44 | +static void gen_branch_fpInactive(DisasContext *s, TCGCond cond, |
78 | * ptimer_free - Free a ptimer | 45 | + TCGLabel *label) |
79 | * @s: timer to free | 46 | +{ |
80 | * | 47 | + /* |
81 | - * Free a ptimer created using ptimer_init_with_bh() (including | 48 | + * FPCXT_NS is a special case: it has specific handling for |
82 | - * deleting the bottom half which it is using). | 49 | + * "current FP state is inactive", and must do the PreserveFPState() |
83 | + * Free a ptimer created using ptimer_init(). | 50 | + * but not the usual full set of actions done by ExecuteFPCheck(). |
84 | */ | 51 | + * We don't have a TB flag that matches the fpInactive check, so we |
85 | void ptimer_free(ptimer_state *s); | 52 | + * do it at runtime as we don't expect FPCXT_NS accesses to be frequent. |
86 | 53 | + * | |
87 | @@ -XXX,XX +XXX,XX @@ void ptimer_transaction_commit(ptimer_state *s); | 54 | + * Emit code that checks fpInactive and does a conditional |
88 | * may be more appropriate. | 55 | + * branch to label based on it: |
89 | * | 56 | + * if cond is TCG_COND_NE then branch if fpInactive != 0 (ie if inactive) |
90 | * This function will assert if it is called outside a | 57 | + * if cond is TCG_COND_EQ then branch if fpInactive == 0 (ie if active) |
91 | - * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. | 58 | + */ |
92 | + * ptimer_transaction_begin/commit block. | 59 | + assert(cond == TCG_COND_EQ || cond == TCG_COND_NE); |
93 | */ | 60 | + |
94 | void ptimer_set_period(ptimer_state *s, int64_t period); | 61 | + /* fpInactive = FPCCR_NS.ASPEN == 1 && CONTROL.FPCA == 0 */ |
95 | 62 | + TCGv_i32 aspen, fpca; | |
96 | @@ -XXX,XX +XXX,XX @@ void ptimer_set_period(ptimer_state *s, int64_t period); | 63 | + aspen = load_cpu_field(v7m.fpccr[M_REG_NS]); |
97 | * precise to fractions of a nanosecond, avoiding rounding errors. | 64 | + fpca = load_cpu_field(v7m.control[M_REG_S]); |
98 | * | 65 | + tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); |
99 | * This function will assert if it is called outside a | 66 | + tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); |
100 | - * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. | 67 | + tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK); |
101 | + * ptimer_transaction_begin/commit block. | 68 | + tcg_gen_or_i32(fpca, fpca, aspen); |
102 | */ | 69 | + tcg_gen_brcondi_i32(tcg_invert_cond(cond), fpca, 0, label); |
103 | void ptimer_set_freq(ptimer_state *s, uint32_t freq); | 70 | + tcg_temp_free_i32(aspen); |
104 | 71 | + tcg_temp_free_i32(fpca); | |
105 | @@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_limit(ptimer_state *s); | 72 | +} |
106 | * reload the counter when their reload register is written to. | 73 | + |
107 | * | 74 | static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, |
108 | * This function will assert if it is called outside a | 75 | |
109 | - * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. | 76 | fp_sysreg_loadfn *loadfn, |
110 | + * ptimer_transaction_begin/commit block. | 77 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, |
111 | */ | ||
112 | void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload); | ||
113 | |||
114 | @@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_count(ptimer_state *s); | ||
115 | * point in the future. | ||
116 | * | ||
117 | * This function will assert if it is called outside a | ||
118 | - * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. | ||
119 | + * ptimer_transaction_begin/commit block. | ||
120 | */ | ||
121 | void ptimer_set_count(ptimer_state *s, uint64_t count); | ||
122 | |||
123 | @@ -XXX,XX +XXX,XX @@ void ptimer_set_count(ptimer_state *s, uint64_t count); | ||
124 | * @s: ptimer | ||
125 | * @oneshot: non-zero if this timer should only count down once | ||
126 | * | ||
127 | - * Start a ptimer counting down; when it reaches zero the bottom half | ||
128 | - * passed to ptimer_init_with_bh() will be invoked. | ||
129 | + * Start a ptimer counting down; when it reaches zero the callback function | ||
130 | + * passed to ptimer_init() will be invoked. | ||
131 | * If the @oneshot argument is zero, | ||
132 | * the counter value will then be reloaded from the limit and it will | ||
133 | * start counting down again. If @oneshot is non-zero, then the counter | ||
134 | * will disable itself when it reaches zero. | ||
135 | * | ||
136 | * This function will assert if it is called outside a | ||
137 | - * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. | ||
138 | + * ptimer_transaction_begin/commit block. | ||
139 | */ | ||
140 | void ptimer_run(ptimer_state *s, int oneshot); | ||
141 | |||
142 | @@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot); | ||
143 | * restarted. | ||
144 | * | ||
145 | * This function will assert if it is called outside a | ||
146 | - * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. | ||
147 | + * ptimer_transaction_begin/commit block. | ||
148 | */ | ||
149 | void ptimer_stop(ptimer_state *s); | ||
150 | |||
151 | diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c | ||
152 | index XXXXXXX..XXXXXXX 100644 | ||
153 | --- a/hw/core/ptimer.c | ||
154 | +++ b/hw/core/ptimer.c | ||
155 | @@ -XXX,XX +XXX,XX @@ struct ptimer_state | ||
156 | int64_t last_event; | ||
157 | int64_t next_event; | ||
158 | uint8_t policy_mask; | ||
159 | - QEMUBH *bh; | ||
160 | QEMUTimer *timer; | ||
161 | ptimer_cb callback; | ||
162 | void *callback_opaque; | ||
163 | @@ -XXX,XX +XXX,XX @@ struct ptimer_state | ||
164 | /* Use a bottom-half routine to avoid reentrancy issues. */ | ||
165 | static void ptimer_trigger(ptimer_state *s) | ||
166 | { | 78 | { |
167 | - if (s->bh) { | 79 | /* Do a write to an M-profile floating point system register */ |
168 | - replay_bh_schedule_event(s->bh); | 80 | TCGv_i32 tmp; |
169 | - } | 81 | + TCGLabel *lab_end = NULL; |
170 | - if (s->callback) { | 82 | |
171 | - s->callback(s->callback_opaque); | 83 | switch (fp_sysreg_checks(s, regno)) { |
172 | - } | 84 | case FPSysRegCheckFailed: |
173 | + s->callback(s->callback_opaque); | 85 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, |
86 | tcg_temp_free_i32(tmp); | ||
87 | break; | ||
88 | } | ||
89 | + case ARM_VFP_FPCXT_NS: | ||
90 | + lab_end = gen_new_label(); | ||
91 | + /* fpInactive case: write is a NOP, so branch to end */ | ||
92 | + gen_branch_fpInactive(s, TCG_COND_NE, lab_end); | ||
93 | + /* !fpInactive: PreserveFPState(), and reads same as FPCXT_S */ | ||
94 | + gen_preserve_fp_state(s); | ||
95 | + /* fall through */ | ||
96 | case ARM_VFP_FPCXT_S: | ||
97 | { | ||
98 | TCGv_i32 sfpa, control; | ||
99 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
100 | default: | ||
101 | g_assert_not_reached(); | ||
102 | } | ||
103 | + if (lab_end) { | ||
104 | + gen_set_label(lab_end); | ||
105 | + } | ||
106 | return true; | ||
174 | } | 107 | } |
175 | 108 | ||
176 | static void ptimer_reload(ptimer_state *s, int delta_adjust) | 109 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, |
177 | @@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_count(ptimer_state *s) | ||
178 | |||
179 | void ptimer_set_count(ptimer_state *s, uint64_t count) | ||
180 | { | 110 | { |
181 | - assert(s->in_transaction || !s->callback); | 111 | /* Do a read from an M-profile floating point system register */ |
182 | + assert(s->in_transaction); | 112 | TCGv_i32 tmp; |
183 | s->delta = count; | 113 | + TCGLabel *lab_end = NULL; |
184 | if (s->enabled) { | 114 | + bool lookup_tb = false; |
185 | - if (!s->callback) { | 115 | |
186 | - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | 116 | switch (fp_sysreg_checks(s, regno)) { |
187 | - ptimer_reload(s, 0); | 117 | case FPSysRegCheckFailed: |
188 | - } else { | 118 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, |
189 | - s->need_reload = true; | 119 | fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); |
190 | - } | 120 | gen_helper_vfp_set_fpscr(cpu_env, fpscr); |
191 | + s->need_reload = true; | 121 | tcg_temp_free_i32(fpscr); |
122 | - gen_lookup_tb(s); | ||
123 | + lookup_tb = true; | ||
124 | + break; | ||
125 | + } | ||
126 | + case ARM_VFP_FPCXT_NS: | ||
127 | + { | ||
128 | + TCGv_i32 control, sfpa, fpscr, fpdscr, zero; | ||
129 | + TCGLabel *lab_active = gen_new_label(); | ||
130 | + | ||
131 | + lookup_tb = true; | ||
132 | + | ||
133 | + gen_branch_fpInactive(s, TCG_COND_EQ, lab_active); | ||
134 | + /* fpInactive case: reads as FPDSCR_NS */ | ||
135 | + TCGv_i32 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]); | ||
136 | + storefn(s, opaque, tmp); | ||
137 | + lab_end = gen_new_label(); | ||
138 | + tcg_gen_br(lab_end); | ||
139 | + | ||
140 | + gen_set_label(lab_active); | ||
141 | + /* !fpInactive: Reads the same as FPCXT_S, but side effects differ */ | ||
142 | + gen_preserve_fp_state(s); | ||
143 | + tmp = tcg_temp_new_i32(); | ||
144 | + sfpa = tcg_temp_new_i32(); | ||
145 | + fpscr = tcg_temp_new_i32(); | ||
146 | + gen_helper_vfp_get_fpscr(fpscr, cpu_env); | ||
147 | + tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK); | ||
148 | + control = load_cpu_field(v7m.control[M_REG_S]); | ||
149 | + tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); | ||
150 | + tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); | ||
151 | + tcg_gen_or_i32(tmp, tmp, sfpa); | ||
152 | + tcg_temp_free_i32(control); | ||
153 | + /* Store result before updating FPSCR, in case it faults */ | ||
154 | + storefn(s, opaque, tmp); | ||
155 | + /* If SFPA is zero then set FPSCR from FPDSCR_NS */ | ||
156 | + fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); | ||
157 | + zero = tcg_const_i32(0); | ||
158 | + tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, zero, fpdscr, fpscr); | ||
159 | + gen_helper_vfp_set_fpscr(cpu_env, fpscr); | ||
160 | + tcg_temp_free_i32(zero); | ||
161 | + tcg_temp_free_i32(sfpa); | ||
162 | + tcg_temp_free_i32(fpdscr); | ||
163 | + tcg_temp_free_i32(fpscr); | ||
164 | break; | ||
192 | } | 165 | } |
166 | default: | ||
167 | g_assert_not_reached(); | ||
168 | } | ||
169 | + | ||
170 | + if (lab_end) { | ||
171 | + gen_set_label(lab_end); | ||
172 | + } | ||
173 | + if (lookup_tb) { | ||
174 | + gen_lookup_tb(s); | ||
175 | + } | ||
176 | return true; | ||
193 | } | 177 | } |
194 | 178 | ||
195 | @@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot) | ||
196 | { | ||
197 | bool was_disabled = !s->enabled; | ||
198 | |||
199 | - assert(s->in_transaction || !s->callback); | ||
200 | + assert(s->in_transaction); | ||
201 | |||
202 | if (was_disabled && s->period == 0) { | ||
203 | if (!qtest_enabled()) { | ||
204 | @@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot) | ||
205 | } | ||
206 | s->enabled = oneshot ? 2 : 1; | ||
207 | if (was_disabled) { | ||
208 | - if (!s->callback) { | ||
209 | - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
210 | - ptimer_reload(s, 0); | ||
211 | - } else { | ||
212 | - s->need_reload = true; | ||
213 | - } | ||
214 | + s->need_reload = true; | ||
215 | } | ||
216 | } | ||
217 | |||
218 | @@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot) | ||
219 | is immediately restarted. */ | ||
220 | void ptimer_stop(ptimer_state *s) | ||
221 | { | ||
222 | - assert(s->in_transaction || !s->callback); | ||
223 | + assert(s->in_transaction); | ||
224 | |||
225 | if (!s->enabled) | ||
226 | return; | ||
227 | @@ -XXX,XX +XXX,XX @@ void ptimer_stop(ptimer_state *s) | ||
228 | s->delta = ptimer_get_count(s); | ||
229 | timer_del(s->timer); | ||
230 | s->enabled = 0; | ||
231 | - if (s->callback) { | ||
232 | - s->need_reload = false; | ||
233 | - } | ||
234 | + s->need_reload = false; | ||
235 | } | ||
236 | |||
237 | /* Set counter increment interval in nanoseconds. */ | ||
238 | void ptimer_set_period(ptimer_state *s, int64_t period) | ||
239 | { | ||
240 | - assert(s->in_transaction || !s->callback); | ||
241 | + assert(s->in_transaction); | ||
242 | s->delta = ptimer_get_count(s); | ||
243 | s->period = period; | ||
244 | s->period_frac = 0; | ||
245 | if (s->enabled) { | ||
246 | - if (!s->callback) { | ||
247 | - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
248 | - ptimer_reload(s, 0); | ||
249 | - } else { | ||
250 | - s->need_reload = true; | ||
251 | - } | ||
252 | + s->need_reload = true; | ||
253 | } | ||
254 | } | ||
255 | |||
256 | /* Set counter frequency in Hz. */ | ||
257 | void ptimer_set_freq(ptimer_state *s, uint32_t freq) | ||
258 | { | ||
259 | - assert(s->in_transaction || !s->callback); | ||
260 | + assert(s->in_transaction); | ||
261 | s->delta = ptimer_get_count(s); | ||
262 | s->period = 1000000000ll / freq; | ||
263 | s->period_frac = (1000000000ll << 32) / freq; | ||
264 | if (s->enabled) { | ||
265 | - if (!s->callback) { | ||
266 | - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
267 | - ptimer_reload(s, 0); | ||
268 | - } else { | ||
269 | - s->need_reload = true; | ||
270 | - } | ||
271 | + s->need_reload = true; | ||
272 | } | ||
273 | } | ||
274 | |||
275 | @@ -XXX,XX +XXX,XX @@ void ptimer_set_freq(ptimer_state *s, uint32_t freq) | ||
276 | count = limit. */ | ||
277 | void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload) | ||
278 | { | ||
279 | - assert(s->in_transaction || !s->callback); | ||
280 | + assert(s->in_transaction); | ||
281 | s->limit = limit; | ||
282 | if (reload) | ||
283 | s->delta = limit; | ||
284 | if (s->enabled && reload) { | ||
285 | - if (!s->callback) { | ||
286 | - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
287 | - ptimer_reload(s, 0); | ||
288 | - } else { | ||
289 | - s->need_reload = true; | ||
290 | - } | ||
291 | + s->need_reload = true; | ||
292 | } | ||
293 | } | ||
294 | |||
295 | @@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_limit(ptimer_state *s) | ||
296 | |||
297 | void ptimer_transaction_begin(ptimer_state *s) | ||
298 | { | ||
299 | - assert(!s->in_transaction || !s->callback); | ||
300 | + assert(!s->in_transaction); | ||
301 | s->in_transaction = true; | ||
302 | s->need_reload = false; | ||
303 | } | ||
304 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_ptimer = { | ||
305 | } | ||
306 | }; | ||
307 | |||
308 | -ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask) | ||
309 | -{ | ||
310 | - ptimer_state *s; | ||
311 | - | ||
312 | - s = (ptimer_state *)g_malloc0(sizeof(ptimer_state)); | ||
313 | - s->bh = bh; | ||
314 | - s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s); | ||
315 | - s->policy_mask = policy_mask; | ||
316 | - | ||
317 | - /* | ||
318 | - * These two policies are incompatible -- trigger-on-decrement implies | ||
319 | - * a timer trigger when the count becomes 0, but no-immediate-trigger | ||
320 | - * implies a trigger when the count stops being 0. | ||
321 | - */ | ||
322 | - assert(!((policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) && | ||
323 | - (policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER))); | ||
324 | - return s; | ||
325 | -} | ||
326 | - | ||
327 | ptimer_state *ptimer_init(ptimer_cb callback, void *callback_opaque, | ||
328 | uint8_t policy_mask) | ||
329 | { | ||
330 | ptimer_state *s; | ||
331 | |||
332 | - /* | ||
333 | - * The callback function is mandatory; so we use it to distinguish | ||
334 | - * old-style QEMUBH ptimers from new transaction API ptimers. | ||
335 | - * (ptimer_init_with_bh() allows a NULL bh pointer and at least | ||
336 | - * one device (digic-timer) passes NULL, so it's not the case | ||
337 | - * that either s->bh != NULL or s->callback != NULL.) | ||
338 | - */ | ||
339 | + /* The callback function is mandatory. */ | ||
340 | assert(callback); | ||
341 | |||
342 | s = g_new0(ptimer_state, 1); | ||
343 | @@ -XXX,XX +XXX,XX @@ ptimer_state *ptimer_init(ptimer_cb callback, void *callback_opaque, | ||
344 | |||
345 | void ptimer_free(ptimer_state *s) | ||
346 | { | ||
347 | - if (s->bh) { | ||
348 | - qemu_bh_delete(s->bh); | ||
349 | - } | ||
350 | timer_free(s->timer); | ||
351 | g_free(s); | ||
352 | } | ||
353 | -- | 179 | -- |
354 | 2.20.1 | 180 | 2.20.1 |
355 | 181 | ||
356 | 182 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Now that we have implemented all the features needed by the v8.1M | ||
2 | architecture, we can add the model of the Cortex-M55. This is the | ||
3 | configuration without MVE support; we'll add MVE later. | ||
1 | 4 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20201210201433.26262-5-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/cpu_tcg.c | 42 ++++++++++++++++++++++++++++++++++++++++++ | ||
10 | 1 file changed, 42 insertions(+) | ||
11 | |||
12 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/cpu_tcg.c | ||
15 | +++ b/target/arm/cpu_tcg.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void cortex_m33_initfn(Object *obj) | ||
17 | cpu->ctr = 0x8000c000; | ||
18 | } | ||
19 | |||
20 | +static void cortex_m55_initfn(Object *obj) | ||
21 | +{ | ||
22 | + ARMCPU *cpu = ARM_CPU(obj); | ||
23 | + | ||
24 | + set_feature(&cpu->env, ARM_FEATURE_V8); | ||
25 | + set_feature(&cpu->env, ARM_FEATURE_V8_1M); | ||
26 | + set_feature(&cpu->env, ARM_FEATURE_M); | ||
27 | + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); | ||
28 | + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); | ||
29 | + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | ||
30 | + cpu->midr = 0x410fd221; /* r0p1 */ | ||
31 | + cpu->revidr = 0; | ||
32 | + cpu->pmsav7_dregion = 16; | ||
33 | + cpu->sau_sregion = 8; | ||
34 | + /* | ||
35 | + * These are the MVFR* values for the FPU, no MVE configuration; | ||
36 | + * we will update them later when we implement MVE | ||
37 | + */ | ||
38 | + cpu->isar.mvfr0 = 0x10110221; | ||
39 | + cpu->isar.mvfr1 = 0x12100011; | ||
40 | + cpu->isar.mvfr2 = 0x00000040; | ||
41 | + cpu->isar.id_pfr0 = 0x20000030; | ||
42 | + cpu->isar.id_pfr1 = 0x00000230; | ||
43 | + cpu->isar.id_dfr0 = 0x10200000; | ||
44 | + cpu->id_afr0 = 0x00000000; | ||
45 | + cpu->isar.id_mmfr0 = 0x00111040; | ||
46 | + cpu->isar.id_mmfr1 = 0x00000000; | ||
47 | + cpu->isar.id_mmfr2 = 0x01000000; | ||
48 | + cpu->isar.id_mmfr3 = 0x00000011; | ||
49 | + cpu->isar.id_isar0 = 0x01103110; | ||
50 | + cpu->isar.id_isar1 = 0x02212000; | ||
51 | + cpu->isar.id_isar2 = 0x20232232; | ||
52 | + cpu->isar.id_isar3 = 0x01111131; | ||
53 | + cpu->isar.id_isar4 = 0x01310132; | ||
54 | + cpu->isar.id_isar5 = 0x00000000; | ||
55 | + cpu->isar.id_isar6 = 0x00000000; | ||
56 | + cpu->clidr = 0x00000000; /* caches not implemented */ | ||
57 | + cpu->ctr = 0x8303c003; | ||
58 | +} | ||
59 | + | ||
60 | static const ARMCPRegInfo cortexr5_cp_reginfo[] = { | ||
61 | /* Dummy the TCM region regs for the moment */ | ||
62 | { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | ||
63 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = { | ||
64 | .class_init = arm_v7m_class_init }, | ||
65 | { .name = "cortex-m33", .initfn = cortex_m33_initfn, | ||
66 | .class_init = arm_v7m_class_init }, | ||
67 | + { .name = "cortex-m55", .initfn = cortex_m55_initfn, | ||
68 | + .class_init = arm_v7m_class_init }, | ||
69 | { .name = "cortex-r5", .initfn = cortex_r5_initfn }, | ||
70 | { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, | ||
71 | { .name = "ti925t", .initfn = ti925t_initfn }, | ||
72 | -- | ||
73 | 2.20.1 | ||
74 | |||
75 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Support for running KVM on 32-bit Arm hosts was removed in commit | ||
2 | 82bf7ae84ce739e. You can still run a 32-bit guest on a 64-bit Arm | ||
3 | host CPU, but because Arm KVM requires the host and guest CPU types | ||
4 | to match, it is not possible to run a guest that requires a Cortex-A9 | ||
5 | or Cortex-A15 CPU there. That means that the code in the | ||
6 | highbank/midway board models to support KVM is no longer used, and we | ||
7 | can delete it. | ||
1 | 8 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
12 | Message-id: 20201215144215.28482-1-peter.maydell@linaro.org | ||
13 | --- | ||
14 | hw/arm/highbank.c | 14 ++++---------- | ||
15 | 1 file changed, 4 insertions(+), 10 deletions(-) | ||
16 | |||
17 | diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/hw/arm/highbank.c | ||
20 | +++ b/hw/arm/highbank.c | ||
21 | @@ -XXX,XX +XXX,XX @@ | ||
22 | #include "hw/arm/boot.h" | ||
23 | #include "hw/loader.h" | ||
24 | #include "net/net.h" | ||
25 | -#include "sysemu/kvm.h" | ||
26 | #include "sysemu/runstate.h" | ||
27 | #include "sysemu/sysemu.h" | ||
28 | #include "hw/boards.h" | ||
29 | @@ -XXX,XX +XXX,XX @@ | ||
30 | #include "hw/cpu/a15mpcore.h" | ||
31 | #include "qemu/log.h" | ||
32 | #include "qom/object.h" | ||
33 | +#include "cpu.h" | ||
34 | |||
35 | #define SMP_BOOT_ADDR 0x100 | ||
36 | #define SMP_BOOT_REG 0x40 | ||
37 | @@ -XXX,XX +XXX,XX @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) | ||
38 | highbank_binfo.loader_start = 0; | ||
39 | highbank_binfo.write_secondary_boot = hb_write_secondary; | ||
40 | highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary; | ||
41 | - if (!kvm_enabled()) { | ||
42 | - highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR; | ||
43 | - highbank_binfo.write_board_setup = hb_write_board_setup; | ||
44 | - highbank_binfo.secure_board_setup = true; | ||
45 | - } else { | ||
46 | - warn_report("cannot load built-in Monitor support " | ||
47 | - "if KVM is enabled. Some guests (such as Linux) " | ||
48 | - "may not boot."); | ||
49 | - } | ||
50 | + highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR; | ||
51 | + highbank_binfo.write_board_setup = hb_write_board_setup; | ||
52 | + highbank_binfo.secure_board_setup = true; | ||
53 | |||
54 | arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo); | ||
55 | } | ||
56 | -- | ||
57 | 2.20.1 | ||
58 | |||
59 | diff view generated by jsdifflib |
1 | All targets have now migrated away from the old unassigned_access | 1 | Currently timer_free() is a simple wrapper for g_free(). This means |
---|---|---|---|
2 | hook to the new do_transaction_failed hook. This means we can remove | 2 | that the timer being freed must not be currently active, as otherwise |
3 | the core-code infrastructure for that hook and the code that calls it. | 3 | QEMU might crash later when the active list is processed and still |
4 | has a pointer to freed memory on it. As a result almost all calls to | ||
5 | timer_free() are preceded by a timer_del() call, as can be seen in | ||
6 | the output of | ||
7 | git grep -B1 '\<timer_free\>' | ||
8 | |||
9 | This is unfortunate API design as it makes it easy to accidentally | ||
10 | misuse (by forgetting the timer_del()), and the correct use is | ||
11 | annoyingly verbose. | ||
12 | |||
13 | Make timer_free() imply a timer_del(). | ||
4 | 14 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 16 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20191108173732.11816-1-peter.maydell@linaro.org | 18 | Message-id: 20201215154107.3255-2-peter.maydell@linaro.org |
9 | --- | 19 | --- |
10 | include/hw/core/cpu.h | 24 ------------------------ | 20 | include/qemu/timer.h | 24 +++++++++++++----------- |
11 | accel/tcg/cputlb.c | 2 -- | 21 | 1 file changed, 13 insertions(+), 11 deletions(-) |
12 | memory.c | 7 ------- | ||
13 | 3 files changed, 33 deletions(-) | ||
14 | 22 | ||
15 | diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h | 23 | diff --git a/include/qemu/timer.h b/include/qemu/timer.h |
16 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/include/hw/core/cpu.h | 25 | --- a/include/qemu/timer.h |
18 | +++ b/include/hw/core/cpu.h | 26 | +++ b/include/qemu/timer.h |
19 | @@ -XXX,XX +XXX,XX @@ typedef enum MMUAccessType { | 27 | @@ -XXX,XX +XXX,XX @@ static inline QEMUTimer *timer_new_ms(QEMUClockType type, QEMUTimerCB *cb, |
20 | 28 | */ | |
21 | typedef struct CPUWatchpoint CPUWatchpoint; | 29 | void timer_deinit(QEMUTimer *ts); |
22 | 30 | ||
23 | -typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr, | 31 | -/** |
24 | - bool is_write, bool is_exec, int opaque, | 32 | - * timer_free: |
25 | - unsigned size); | 33 | - * @ts: the timer |
26 | - | 34 | - * |
27 | struct TranslationBlock; | 35 | - * Free a timer (it must not be on the active list) |
28 | 36 | - */ | |
29 | /** | 37 | -static inline void timer_free(QEMUTimer *ts) |
30 | @@ -XXX,XX +XXX,XX @@ struct TranslationBlock; | ||
31 | * @reset_dump_flags: #CPUDumpFlags to use for reset logging. | ||
32 | * @has_work: Callback for checking if there is work to do. | ||
33 | * @do_interrupt: Callback for interrupt handling. | ||
34 | - * @do_unassigned_access: Callback for unassigned access handling. | ||
35 | - * (this is deprecated: new targets should use do_transaction_failed instead) | ||
36 | * @do_unaligned_access: Callback for unaligned access handling, if | ||
37 | * the target defines #TARGET_ALIGNED_ONLY. | ||
38 | * @do_transaction_failed: Callback for handling failed memory transactions | ||
39 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUClass { | ||
40 | int reset_dump_flags; | ||
41 | bool (*has_work)(CPUState *cpu); | ||
42 | void (*do_interrupt)(CPUState *cpu); | ||
43 | - CPUUnassignedAccess do_unassigned_access; | ||
44 | void (*do_unaligned_access)(CPUState *cpu, vaddr addr, | ||
45 | MMUAccessType access_type, | ||
46 | int mmu_idx, uintptr_t retaddr); | ||
47 | @@ -XXX,XX +XXX,XX @@ struct CPUState { | ||
48 | * we store some rarely used information in the CPU context. | ||
49 | */ | ||
50 | uintptr_t mem_io_pc; | ||
51 | - /* | ||
52 | - * This is only needed for the legacy cpu_unassigned_access() hook; | ||
53 | - * when all targets using it have been converted to use | ||
54 | - * cpu_transaction_failed() instead it can be removed. | ||
55 | - */ | ||
56 | - MMUAccessType mem_io_access_type; | ||
57 | |||
58 | int kvm_fd; | ||
59 | struct KVMState *kvm_state; | ||
60 | @@ -XXX,XX +XXX,XX @@ void cpu_interrupt(CPUState *cpu, int mask); | ||
61 | #ifdef NEED_CPU_H | ||
62 | |||
63 | #ifdef CONFIG_SOFTMMU | ||
64 | -static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr, | ||
65 | - bool is_write, bool is_exec, | ||
66 | - int opaque, unsigned size) | ||
67 | -{ | 38 | -{ |
68 | - CPUClass *cc = CPU_GET_CLASS(cpu); | 39 | - g_free(ts); |
69 | - | ||
70 | - if (cc->do_unassigned_access) { | ||
71 | - cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size); | ||
72 | - } | ||
73 | -} | 40 | -} |
74 | - | 41 | - |
75 | static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, | 42 | /** |
76 | MMUAccessType access_type, | 43 | * timer_del: |
77 | int mmu_idx, uintptr_t retaddr) | 44 | * @ts: the timer |
78 | diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c | 45 | @@ -XXX,XX +XXX,XX @@ static inline void timer_free(QEMUTimer *ts) |
79 | index XXXXXXX..XXXXXXX 100644 | 46 | */ |
80 | --- a/accel/tcg/cputlb.c | 47 | void timer_del(QEMUTimer *ts); |
81 | +++ b/accel/tcg/cputlb.c | 48 | |
82 | @@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, | 49 | +/** |
83 | cpu_io_recompile(cpu, retaddr); | 50 | + * timer_free: |
84 | } | 51 | + * @ts: the timer |
85 | 52 | + * | |
86 | - cpu->mem_io_access_type = access_type; | 53 | + * Free a timer. This will call timer_del() for you to remove |
87 | - | 54 | + * the timer from the active list if it was still active. |
88 | if (mr->global_locking && !qemu_mutex_iothread_locked()) { | 55 | + */ |
89 | qemu_mutex_lock_iothread(); | 56 | +static inline void timer_free(QEMUTimer *ts) |
90 | locked = true; | 57 | +{ |
91 | diff --git a/memory.c b/memory.c | 58 | + timer_del(ts); |
92 | index XXXXXXX..XXXXXXX 100644 | 59 | + g_free(ts); |
93 | --- a/memory.c | 60 | +} |
94 | +++ b/memory.c | 61 | + |
95 | @@ -XXX,XX +XXX,XX @@ static uint64_t unassigned_mem_read(void *opaque, hwaddr addr, | 62 | /** |
96 | #ifdef DEBUG_UNASSIGNED | 63 | * timer_mod_ns: |
97 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | 64 | * @ts: the timer |
98 | #endif | ||
99 | - if (current_cpu != NULL) { | ||
100 | - bool is_exec = current_cpu->mem_io_access_type == MMU_INST_FETCH; | ||
101 | - cpu_unassigned_access(current_cpu, addr, false, is_exec, 0, size); | ||
102 | - } | ||
103 | return 0; | ||
104 | } | ||
105 | |||
106 | @@ -XXX,XX +XXX,XX @@ static void unassigned_mem_write(void *opaque, hwaddr addr, | ||
107 | #ifdef DEBUG_UNASSIGNED | ||
108 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val); | ||
109 | #endif | ||
110 | - if (current_cpu != NULL) { | ||
111 | - cpu_unassigned_access(current_cpu, addr, true, false, 0, size); | ||
112 | - } | ||
113 | } | ||
114 | |||
115 | static bool unassigned_mem_accepts(void *opaque, hwaddr addr, | ||
116 | -- | 65 | -- |
117 | 2.20.1 | 66 | 2.20.1 |
118 | 67 | ||
119 | 68 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Now that timer_free() implicitly calls timer_del(), sequences | ||
2 | timer_del(mytimer); | ||
3 | timer_free(mytimer); | ||
1 | 4 | ||
5 | can be simplified to just | ||
6 | timer_free(mytimer); | ||
7 | |||
8 | Add a Coccinelle script to do this transformation. | ||
9 | |||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Acked-by: Paolo Bonzini <pbonzini@redhat.com> | ||
12 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Message-id: 20201215154107.3255-3-peter.maydell@linaro.org | ||
15 | --- | ||
16 | scripts/coccinelle/timer-del-timer-free.cocci | 18 ++++++++++++++++++ | ||
17 | 1 file changed, 18 insertions(+) | ||
18 | create mode 100644 scripts/coccinelle/timer-del-timer-free.cocci | ||
19 | |||
20 | diff --git a/scripts/coccinelle/timer-del-timer-free.cocci b/scripts/coccinelle/timer-del-timer-free.cocci | ||
21 | new file mode 100644 | ||
22 | index XXXXXXX..XXXXXXX | ||
23 | --- /dev/null | ||
24 | +++ b/scripts/coccinelle/timer-del-timer-free.cocci | ||
25 | @@ -XXX,XX +XXX,XX @@ | ||
26 | +// Remove superfluous timer_del() calls | ||
27 | +// | ||
28 | +// Copyright Linaro Limited 2020 | ||
29 | +// This work is licensed under the terms of the GNU GPLv2 or later. | ||
30 | +// | ||
31 | +// spatch --macro-file scripts/cocci-macro-file.h \ | ||
32 | +// --sp-file scripts/coccinelle/timer-del-timer-free.cocci \ | ||
33 | +// --in-place --dir . | ||
34 | +// | ||
35 | +// The timer_free() function now implicitly calls timer_del() | ||
36 | +// for you, so calls to timer_del() immediately before the | ||
37 | +// timer_free() of the same timer can be deleted. | ||
38 | + | ||
39 | +@@ | ||
40 | +expression T; | ||
41 | +@@ | ||
42 | +-timer_del(T); | ||
43 | + timer_free(T); | ||
44 | -- | ||
45 | 2.20.1 | ||
46 | |||
47 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | This commit is the result of running the timer-del-timer-free.cocci | ||
2 | script on the whole source tree. | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Acked-by: Corey Minyard <cminyard@mvista.com> | ||
6 | Acked-by: Paolo Bonzini <pbonzini@redhat.com> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20201215154107.3255-4-peter.maydell@linaro.org | ||
10 | --- | ||
11 | block/iscsi.c | 2 -- | ||
12 | block/nbd.c | 1 - | ||
13 | block/qcow2.c | 1 - | ||
14 | hw/block/nvme.c | 2 -- | ||
15 | hw/char/serial.c | 2 -- | ||
16 | hw/char/virtio-serial-bus.c | 2 -- | ||
17 | hw/ide/core.c | 1 - | ||
18 | hw/input/hid.c | 1 - | ||
19 | hw/intc/apic.c | 1 - | ||
20 | hw/intc/ioapic.c | 1 - | ||
21 | hw/ipmi/ipmi_bmc_extern.c | 1 - | ||
22 | hw/net/e1000.c | 3 --- | ||
23 | hw/net/e1000e_core.c | 8 -------- | ||
24 | hw/net/pcnet-pci.c | 1 - | ||
25 | hw/net/rtl8139.c | 1 - | ||
26 | hw/net/spapr_llan.c | 1 - | ||
27 | hw/net/virtio-net.c | 2 -- | ||
28 | hw/s390x/s390-pci-inst.c | 1 - | ||
29 | hw/sd/sd.c | 1 - | ||
30 | hw/sd/sdhci.c | 2 -- | ||
31 | hw/usb/dev-hub.c | 1 - | ||
32 | hw/usb/hcd-ehci.c | 1 - | ||
33 | hw/usb/hcd-ohci-pci.c | 1 - | ||
34 | hw/usb/hcd-uhci.c | 1 - | ||
35 | hw/usb/hcd-xhci.c | 1 - | ||
36 | hw/usb/redirect.c | 1 - | ||
37 | hw/vfio/display.c | 1 - | ||
38 | hw/virtio/vhost-vsock-common.c | 1 - | ||
39 | hw/virtio/virtio-balloon.c | 1 - | ||
40 | hw/virtio/virtio-rng.c | 1 - | ||
41 | hw/watchdog/wdt_diag288.c | 1 - | ||
42 | hw/watchdog/wdt_i6300esb.c | 1 - | ||
43 | migration/colo.c | 1 - | ||
44 | monitor/hmp-cmds.c | 1 - | ||
45 | net/announce.c | 1 - | ||
46 | net/colo-compare.c | 1 - | ||
47 | net/slirp.c | 1 - | ||
48 | replay/replay-debugging.c | 1 - | ||
49 | target/s390x/cpu.c | 2 -- | ||
50 | ui/console.c | 1 - | ||
51 | ui/spice-core.c | 1 - | ||
52 | util/throttle.c | 1 - | ||
53 | 42 files changed, 58 deletions(-) | ||
54 | |||
55 | diff --git a/block/iscsi.c b/block/iscsi.c | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/block/iscsi.c | ||
58 | +++ b/block/iscsi.c | ||
59 | @@ -XXX,XX +XXX,XX @@ static void iscsi_detach_aio_context(BlockDriverState *bs) | ||
60 | iscsilun->events = 0; | ||
61 | |||
62 | if (iscsilun->nop_timer) { | ||
63 | - timer_del(iscsilun->nop_timer); | ||
64 | timer_free(iscsilun->nop_timer); | ||
65 | iscsilun->nop_timer = NULL; | ||
66 | } | ||
67 | if (iscsilun->event_timer) { | ||
68 | - timer_del(iscsilun->event_timer); | ||
69 | timer_free(iscsilun->event_timer); | ||
70 | iscsilun->event_timer = NULL; | ||
71 | } | ||
72 | diff --git a/block/nbd.c b/block/nbd.c | ||
73 | index XXXXXXX..XXXXXXX 100644 | ||
74 | --- a/block/nbd.c | ||
75 | +++ b/block/nbd.c | ||
76 | @@ -XXX,XX +XXX,XX @@ static void nbd_recv_coroutines_wake_all(BDRVNBDState *s) | ||
77 | static void reconnect_delay_timer_del(BDRVNBDState *s) | ||
78 | { | ||
79 | if (s->reconnect_delay_timer) { | ||
80 | - timer_del(s->reconnect_delay_timer); | ||
81 | timer_free(s->reconnect_delay_timer); | ||
82 | s->reconnect_delay_timer = NULL; | ||
83 | } | ||
84 | diff --git a/block/qcow2.c b/block/qcow2.c | ||
85 | index XXXXXXX..XXXXXXX 100644 | ||
86 | --- a/block/qcow2.c | ||
87 | +++ b/block/qcow2.c | ||
88 | @@ -XXX,XX +XXX,XX @@ static void cache_clean_timer_del(BlockDriverState *bs) | ||
89 | { | ||
90 | BDRVQcow2State *s = bs->opaque; | ||
91 | if (s->cache_clean_timer) { | ||
92 | - timer_del(s->cache_clean_timer); | ||
93 | timer_free(s->cache_clean_timer); | ||
94 | s->cache_clean_timer = NULL; | ||
95 | } | ||
96 | diff --git a/hw/block/nvme.c b/hw/block/nvme.c | ||
97 | index XXXXXXX..XXXXXXX 100644 | ||
98 | --- a/hw/block/nvme.c | ||
99 | +++ b/hw/block/nvme.c | ||
100 | @@ -XXX,XX +XXX,XX @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest *req) | ||
101 | static void nvme_free_sq(NvmeSQueue *sq, NvmeCtrl *n) | ||
102 | { | ||
103 | n->sq[sq->sqid] = NULL; | ||
104 | - timer_del(sq->timer); | ||
105 | timer_free(sq->timer); | ||
106 | g_free(sq->io_req); | ||
107 | if (sq->sqid) { | ||
108 | @@ -XXX,XX +XXX,XX @@ static uint16_t nvme_get_log(NvmeCtrl *n, NvmeRequest *req) | ||
109 | static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n) | ||
110 | { | ||
111 | n->cq[cq->cqid] = NULL; | ||
112 | - timer_del(cq->timer); | ||
113 | timer_free(cq->timer); | ||
114 | msix_vector_unuse(&n->parent_obj, cq->vector); | ||
115 | if (cq->cqid) { | ||
116 | diff --git a/hw/char/serial.c b/hw/char/serial.c | ||
117 | index XXXXXXX..XXXXXXX 100644 | ||
118 | --- a/hw/char/serial.c | ||
119 | +++ b/hw/char/serial.c | ||
120 | @@ -XXX,XX +XXX,XX @@ static void serial_unrealize(DeviceState *dev) | ||
121 | |||
122 | qemu_chr_fe_deinit(&s->chr, false); | ||
123 | |||
124 | - timer_del(s->modem_status_poll); | ||
125 | timer_free(s->modem_status_poll); | ||
126 | |||
127 | - timer_del(s->fifo_timeout_timer); | ||
128 | timer_free(s->fifo_timeout_timer); | ||
129 | |||
130 | fifo8_destroy(&s->recv_fifo); | ||
131 | diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c | ||
132 | index XXXXXXX..XXXXXXX 100644 | ||
133 | --- a/hw/char/virtio-serial-bus.c | ||
134 | +++ b/hw/char/virtio-serial-bus.c | ||
135 | @@ -XXX,XX +XXX,XX @@ static void virtio_serial_post_load_timer_cb(void *opaque) | ||
136 | } | ||
137 | } | ||
138 | g_free(s->post_load->connected); | ||
139 | - timer_del(s->post_load->timer); | ||
140 | timer_free(s->post_load->timer); | ||
141 | g_free(s->post_load); | ||
142 | s->post_load = NULL; | ||
143 | @@ -XXX,XX +XXX,XX @@ static void virtio_serial_device_unrealize(DeviceState *dev) | ||
144 | g_free(vser->ports_map); | ||
145 | if (vser->post_load) { | ||
146 | g_free(vser->post_load->connected); | ||
147 | - timer_del(vser->post_load->timer); | ||
148 | timer_free(vser->post_load->timer); | ||
149 | g_free(vser->post_load); | ||
150 | } | ||
151 | diff --git a/hw/ide/core.c b/hw/ide/core.c | ||
152 | index XXXXXXX..XXXXXXX 100644 | ||
153 | --- a/hw/ide/core.c | ||
154 | +++ b/hw/ide/core.c | ||
155 | @@ -XXX,XX +XXX,XX @@ void ide_init2(IDEBus *bus, qemu_irq irq) | ||
156 | |||
157 | void ide_exit(IDEState *s) | ||
158 | { | ||
159 | - timer_del(s->sector_write_timer); | ||
160 | timer_free(s->sector_write_timer); | ||
161 | qemu_vfree(s->smart_selftest_data); | ||
162 | qemu_vfree(s->io_buffer); | ||
163 | diff --git a/hw/input/hid.c b/hw/input/hid.c | ||
164 | index XXXXXXX..XXXXXXX 100644 | ||
165 | --- a/hw/input/hid.c | ||
166 | +++ b/hw/input/hid.c | ||
167 | @@ -XXX,XX +XXX,XX @@ static void hid_idle_timer(void *opaque) | ||
168 | static void hid_del_idle_timer(HIDState *hs) | ||
169 | { | ||
170 | if (hs->idle_timer) { | ||
171 | - timer_del(hs->idle_timer); | ||
172 | timer_free(hs->idle_timer); | ||
173 | hs->idle_timer = NULL; | ||
174 | } | ||
175 | diff --git a/hw/intc/apic.c b/hw/intc/apic.c | ||
176 | index XXXXXXX..XXXXXXX 100644 | ||
177 | --- a/hw/intc/apic.c | ||
178 | +++ b/hw/intc/apic.c | ||
179 | @@ -XXX,XX +XXX,XX @@ static void apic_unrealize(DeviceState *dev) | ||
180 | { | ||
181 | APICCommonState *s = APIC(dev); | ||
182 | |||
183 | - timer_del(s->timer); | ||
184 | timer_free(s->timer); | ||
185 | local_apics[s->id] = NULL; | ||
186 | } | ||
187 | diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c | ||
188 | index XXXXXXX..XXXXXXX 100644 | ||
189 | --- a/hw/intc/ioapic.c | ||
190 | +++ b/hw/intc/ioapic.c | ||
191 | @@ -XXX,XX +XXX,XX @@ static void ioapic_unrealize(DeviceState *dev) | ||
192 | { | ||
193 | IOAPICCommonState *s = IOAPIC_COMMON(dev); | ||
194 | |||
195 | - timer_del(s->delayed_ioapic_service_timer); | ||
196 | timer_free(s->delayed_ioapic_service_timer); | ||
197 | } | ||
198 | |||
199 | diff --git a/hw/ipmi/ipmi_bmc_extern.c b/hw/ipmi/ipmi_bmc_extern.c | ||
200 | index XXXXXXX..XXXXXXX 100644 | ||
201 | --- a/hw/ipmi/ipmi_bmc_extern.c | ||
202 | +++ b/hw/ipmi/ipmi_bmc_extern.c | ||
203 | @@ -XXX,XX +XXX,XX @@ static void ipmi_bmc_extern_finalize(Object *obj) | ||
204 | { | ||
205 | IPMIBmcExtern *ibe = IPMI_BMC_EXTERN(obj); | ||
206 | |||
207 | - timer_del(ibe->extern_timer); | ||
208 | timer_free(ibe->extern_timer); | ||
209 | } | ||
210 | |||
211 | diff --git a/hw/net/e1000.c b/hw/net/e1000.c | ||
212 | index XXXXXXX..XXXXXXX 100644 | ||
213 | --- a/hw/net/e1000.c | ||
214 | +++ b/hw/net/e1000.c | ||
215 | @@ -XXX,XX +XXX,XX @@ pci_e1000_uninit(PCIDevice *dev) | ||
216 | { | ||
217 | E1000State *d = E1000(dev); | ||
218 | |||
219 | - timer_del(d->autoneg_timer); | ||
220 | timer_free(d->autoneg_timer); | ||
221 | - timer_del(d->mit_timer); | ||
222 | timer_free(d->mit_timer); | ||
223 | - timer_del(d->flush_queue_timer); | ||
224 | timer_free(d->flush_queue_timer); | ||
225 | qemu_del_nic(d->nic); | ||
226 | } | ||
227 | diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c | ||
228 | index XXXXXXX..XXXXXXX 100644 | ||
229 | --- a/hw/net/e1000e_core.c | ||
230 | +++ b/hw/net/e1000e_core.c | ||
231 | @@ -XXX,XX +XXX,XX @@ e1000e_intrmgr_pci_unint(E1000ECore *core) | ||
232 | { | ||
233 | int i; | ||
234 | |||
235 | - timer_del(core->radv.timer); | ||
236 | timer_free(core->radv.timer); | ||
237 | - timer_del(core->rdtr.timer); | ||
238 | timer_free(core->rdtr.timer); | ||
239 | - timer_del(core->raid.timer); | ||
240 | timer_free(core->raid.timer); | ||
241 | |||
242 | - timer_del(core->tadv.timer); | ||
243 | timer_free(core->tadv.timer); | ||
244 | - timer_del(core->tidv.timer); | ||
245 | timer_free(core->tidv.timer); | ||
246 | |||
247 | - timer_del(core->itr.timer); | ||
248 | timer_free(core->itr.timer); | ||
249 | |||
250 | for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { | ||
251 | - timer_del(core->eitr[i].timer); | ||
252 | timer_free(core->eitr[i].timer); | ||
253 | } | ||
254 | } | ||
255 | @@ -XXX,XX +XXX,XX @@ e1000e_core_pci_uninit(E1000ECore *core) | ||
256 | { | ||
257 | int i; | ||
258 | |||
259 | - timer_del(core->autoneg_timer); | ||
260 | timer_free(core->autoneg_timer); | ||
261 | |||
262 | e1000e_intrmgr_pci_unint(core); | ||
263 | diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c | ||
264 | index XXXXXXX..XXXXXXX 100644 | ||
265 | --- a/hw/net/pcnet-pci.c | ||
266 | +++ b/hw/net/pcnet-pci.c | ||
267 | @@ -XXX,XX +XXX,XX @@ static void pci_pcnet_uninit(PCIDevice *dev) | ||
268 | PCIPCNetState *d = PCI_PCNET(dev); | ||
269 | |||
270 | qemu_free_irq(d->state.irq); | ||
271 | - timer_del(d->state.poll_timer); | ||
272 | timer_free(d->state.poll_timer); | ||
273 | qemu_del_nic(d->state.nic); | ||
274 | } | ||
275 | diff --git a/hw/net/rtl8139.c b/hw/net/rtl8139.c | ||
276 | index XXXXXXX..XXXXXXX 100644 | ||
277 | --- a/hw/net/rtl8139.c | ||
278 | +++ b/hw/net/rtl8139.c | ||
279 | @@ -XXX,XX +XXX,XX @@ static void pci_rtl8139_uninit(PCIDevice *dev) | ||
280 | |||
281 | g_free(s->cplus_txbuffer); | ||
282 | s->cplus_txbuffer = NULL; | ||
283 | - timer_del(s->timer); | ||
284 | timer_free(s->timer); | ||
285 | qemu_del_nic(s->nic); | ||
286 | } | ||
287 | diff --git a/hw/net/spapr_llan.c b/hw/net/spapr_llan.c | ||
288 | index XXXXXXX..XXXXXXX 100644 | ||
289 | --- a/hw/net/spapr_llan.c | ||
290 | +++ b/hw/net/spapr_llan.c | ||
291 | @@ -XXX,XX +XXX,XX @@ static void spapr_vlan_instance_finalize(Object *obj) | ||
292 | } | ||
293 | |||
294 | if (dev->rxp_timer) { | ||
295 | - timer_del(dev->rxp_timer); | ||
296 | timer_free(dev->rxp_timer); | ||
297 | } | ||
298 | } | ||
299 | diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c | ||
300 | index XXXXXXX..XXXXXXX 100644 | ||
301 | --- a/hw/net/virtio-net.c | ||
302 | +++ b/hw/net/virtio-net.c | ||
303 | @@ -XXX,XX +XXX,XX @@ static void virtio_net_rsc_cleanup(VirtIONet *n) | ||
304 | g_free(seg); | ||
305 | } | ||
306 | |||
307 | - timer_del(chain->drain_timer); | ||
308 | timer_free(chain->drain_timer); | ||
309 | QTAILQ_REMOVE(&n->rsc_chains, chain, next); | ||
310 | g_free(chain); | ||
311 | @@ -XXX,XX +XXX,XX @@ static void virtio_net_del_queue(VirtIONet *n, int index) | ||
312 | |||
313 | virtio_del_queue(vdev, index * 2); | ||
314 | if (q->tx_timer) { | ||
315 | - timer_del(q->tx_timer); | ||
316 | timer_free(q->tx_timer); | ||
317 | q->tx_timer = NULL; | ||
318 | } else { | ||
319 | diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c | ||
320 | index XXXXXXX..XXXXXXX 100644 | ||
321 | --- a/hw/s390x/s390-pci-inst.c | ||
322 | +++ b/hw/s390x/s390-pci-inst.c | ||
323 | @@ -XXX,XX +XXX,XX @@ void pci_dereg_ioat(S390PCIIOMMU *iommu) | ||
324 | void fmb_timer_free(S390PCIBusDevice *pbdev) | ||
325 | { | ||
326 | if (pbdev->fmb_timer) { | ||
327 | - timer_del(pbdev->fmb_timer); | ||
328 | timer_free(pbdev->fmb_timer); | ||
329 | pbdev->fmb_timer = NULL; | ||
330 | } | ||
331 | diff --git a/hw/sd/sd.c b/hw/sd/sd.c | ||
332 | index XXXXXXX..XXXXXXX 100644 | ||
333 | --- a/hw/sd/sd.c | ||
334 | +++ b/hw/sd/sd.c | ||
335 | @@ -XXX,XX +XXX,XX @@ static void sd_instance_finalize(Object *obj) | ||
336 | { | ||
337 | SDState *sd = SD_CARD(obj); | ||
338 | |||
339 | - timer_del(sd->ocr_power_timer); | ||
340 | timer_free(sd->ocr_power_timer); | ||
341 | } | ||
342 | |||
343 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | ||
344 | index XXXXXXX..XXXXXXX 100644 | ||
345 | --- a/hw/sd/sdhci.c | ||
346 | +++ b/hw/sd/sdhci.c | ||
347 | @@ -XXX,XX +XXX,XX @@ void sdhci_initfn(SDHCIState *s) | ||
348 | |||
349 | void sdhci_uninitfn(SDHCIState *s) | ||
350 | { | ||
351 | - timer_del(s->insert_timer); | ||
352 | timer_free(s->insert_timer); | ||
353 | - timer_del(s->transfer_timer); | ||
354 | timer_free(s->transfer_timer); | ||
355 | |||
356 | g_free(s->fifo_buffer); | ||
357 | diff --git a/hw/usb/dev-hub.c b/hw/usb/dev-hub.c | ||
358 | index XXXXXXX..XXXXXXX 100644 | ||
359 | --- a/hw/usb/dev-hub.c | ||
360 | +++ b/hw/usb/dev-hub.c | ||
361 | @@ -XXX,XX +XXX,XX @@ static void usb_hub_unrealize(USBDevice *dev) | ||
362 | &s->ports[i].port); | ||
363 | } | ||
364 | |||
365 | - timer_del(s->port_timer); | ||
366 | timer_free(s->port_timer); | ||
367 | } | ||
368 | |||
369 | diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c | ||
370 | index XXXXXXX..XXXXXXX 100644 | ||
371 | --- a/hw/usb/hcd-ehci.c | ||
372 | +++ b/hw/usb/hcd-ehci.c | ||
373 | @@ -XXX,XX +XXX,XX @@ void usb_ehci_unrealize(EHCIState *s, DeviceState *dev) | ||
374 | trace_usb_ehci_unrealize(); | ||
375 | |||
376 | if (s->frame_timer) { | ||
377 | - timer_del(s->frame_timer); | ||
378 | timer_free(s->frame_timer); | ||
379 | s->frame_timer = NULL; | ||
380 | } | ||
381 | diff --git a/hw/usb/hcd-ohci-pci.c b/hw/usb/hcd-ohci-pci.c | ||
382 | index XXXXXXX..XXXXXXX 100644 | ||
383 | --- a/hw/usb/hcd-ohci-pci.c | ||
384 | +++ b/hw/usb/hcd-ohci-pci.c | ||
385 | @@ -XXX,XX +XXX,XX @@ static void usb_ohci_exit(PCIDevice *dev) | ||
386 | usb_bus_release(&s->bus); | ||
387 | } | ||
388 | |||
389 | - timer_del(s->eof_timer); | ||
390 | timer_free(s->eof_timer); | ||
391 | } | ||
392 | |||
393 | diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c | ||
394 | index XXXXXXX..XXXXXXX 100644 | ||
395 | --- a/hw/usb/hcd-uhci.c | ||
396 | +++ b/hw/usb/hcd-uhci.c | ||
397 | @@ -XXX,XX +XXX,XX @@ static void usb_uhci_exit(PCIDevice *dev) | ||
398 | trace_usb_uhci_exit(); | ||
399 | |||
400 | if (s->frame_timer) { | ||
401 | - timer_del(s->frame_timer); | ||
402 | timer_free(s->frame_timer); | ||
403 | s->frame_timer = NULL; | ||
404 | } | ||
405 | diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c | ||
406 | index XXXXXXX..XXXXXXX 100644 | ||
407 | --- a/hw/usb/hcd-xhci.c | ||
408 | +++ b/hw/usb/hcd-xhci.c | ||
409 | @@ -XXX,XX +XXX,XX @@ static void usb_xhci_unrealize(DeviceState *dev) | ||
410 | } | ||
411 | |||
412 | if (xhci->mfwrap_timer) { | ||
413 | - timer_del(xhci->mfwrap_timer); | ||
414 | timer_free(xhci->mfwrap_timer); | ||
415 | xhci->mfwrap_timer = NULL; | ||
416 | } | ||
417 | diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c | ||
418 | index XXXXXXX..XXXXXXX 100644 | ||
419 | --- a/hw/usb/redirect.c | ||
420 | +++ b/hw/usb/redirect.c | ||
421 | @@ -XXX,XX +XXX,XX @@ static void usbredir_unrealize(USBDevice *udev) | ||
422 | qemu_bh_delete(dev->chardev_close_bh); | ||
423 | qemu_bh_delete(dev->device_reject_bh); | ||
424 | |||
425 | - timer_del(dev->attach_timer); | ||
426 | timer_free(dev->attach_timer); | ||
427 | |||
428 | usbredir_cleanup_device_queues(dev); | ||
429 | diff --git a/hw/vfio/display.c b/hw/vfio/display.c | ||
430 | index XXXXXXX..XXXXXXX 100644 | ||
431 | --- a/hw/vfio/display.c | ||
432 | +++ b/hw/vfio/display.c | ||
433 | @@ -XXX,XX +XXX,XX @@ static void vfio_display_edid_exit(VFIODisplay *dpy) | ||
434 | |||
435 | g_free(dpy->edid_regs); | ||
436 | g_free(dpy->edid_blob); | ||
437 | - timer_del(dpy->edid_link_timer); | ||
438 | timer_free(dpy->edid_link_timer); | ||
439 | } | ||
440 | |||
441 | diff --git a/hw/virtio/vhost-vsock-common.c b/hw/virtio/vhost-vsock-common.c | ||
442 | index XXXXXXX..XXXXXXX 100644 | ||
443 | --- a/hw/virtio/vhost-vsock-common.c | ||
444 | +++ b/hw/virtio/vhost-vsock-common.c | ||
445 | @@ -XXX,XX +XXX,XX @@ static void vhost_vsock_common_post_load_timer_cleanup(VHostVSockCommon *vvc) | ||
446 | return; | ||
447 | } | ||
448 | |||
449 | - timer_del(vvc->post_load_timer); | ||
450 | timer_free(vvc->post_load_timer); | ||
451 | vvc->post_load_timer = NULL; | ||
452 | } | ||
453 | diff --git a/hw/virtio/virtio-balloon.c b/hw/virtio/virtio-balloon.c | ||
454 | index XXXXXXX..XXXXXXX 100644 | ||
455 | --- a/hw/virtio/virtio-balloon.c | ||
456 | +++ b/hw/virtio/virtio-balloon.c | ||
457 | @@ -XXX,XX +XXX,XX @@ static bool balloon_stats_enabled(const VirtIOBalloon *s) | ||
458 | static void balloon_stats_destroy_timer(VirtIOBalloon *s) | ||
459 | { | ||
460 | if (balloon_stats_enabled(s)) { | ||
461 | - timer_del(s->stats_timer); | ||
462 | timer_free(s->stats_timer); | ||
463 | s->stats_timer = NULL; | ||
464 | s->stats_poll_interval = 0; | ||
465 | diff --git a/hw/virtio/virtio-rng.c b/hw/virtio/virtio-rng.c | ||
466 | index XXXXXXX..XXXXXXX 100644 | ||
467 | --- a/hw/virtio/virtio-rng.c | ||
468 | +++ b/hw/virtio/virtio-rng.c | ||
469 | @@ -XXX,XX +XXX,XX @@ static void virtio_rng_device_unrealize(DeviceState *dev) | ||
470 | VirtIORNG *vrng = VIRTIO_RNG(dev); | ||
471 | |||
472 | qemu_del_vm_change_state_handler(vrng->vmstate); | ||
473 | - timer_del(vrng->rate_limit_timer); | ||
474 | timer_free(vrng->rate_limit_timer); | ||
475 | virtio_del_queue(vdev, 0); | ||
476 | virtio_cleanup(vdev); | ||
477 | diff --git a/hw/watchdog/wdt_diag288.c b/hw/watchdog/wdt_diag288.c | ||
478 | index XXXXXXX..XXXXXXX 100644 | ||
479 | --- a/hw/watchdog/wdt_diag288.c | ||
480 | +++ b/hw/watchdog/wdt_diag288.c | ||
481 | @@ -XXX,XX +XXX,XX @@ static void wdt_diag288_unrealize(DeviceState *dev) | ||
482 | { | ||
483 | DIAG288State *diag288 = DIAG288(dev); | ||
484 | |||
485 | - timer_del(diag288->timer); | ||
486 | timer_free(diag288->timer); | ||
487 | } | ||
488 | |||
489 | diff --git a/hw/watchdog/wdt_i6300esb.c b/hw/watchdog/wdt_i6300esb.c | ||
490 | index XXXXXXX..XXXXXXX 100644 | ||
491 | --- a/hw/watchdog/wdt_i6300esb.c | ||
492 | +++ b/hw/watchdog/wdt_i6300esb.c | ||
493 | @@ -XXX,XX +XXX,XX @@ static void i6300esb_exit(PCIDevice *dev) | ||
494 | { | ||
495 | I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev); | ||
496 | |||
497 | - timer_del(d->timer); | ||
498 | timer_free(d->timer); | ||
499 | } | ||
500 | |||
501 | diff --git a/migration/colo.c b/migration/colo.c | ||
502 | index XXXXXXX..XXXXXXX 100644 | ||
503 | --- a/migration/colo.c | ||
504 | +++ b/migration/colo.c | ||
505 | @@ -XXX,XX +XXX,XX @@ out: | ||
506 | * error. | ||
507 | */ | ||
508 | colo_compare_unregister_notifier(&packets_compare_notifier); | ||
509 | - timer_del(s->colo_delay_timer); | ||
510 | timer_free(s->colo_delay_timer); | ||
511 | qemu_event_destroy(&s->colo_checkpoint_event); | ||
512 | |||
513 | diff --git a/monitor/hmp-cmds.c b/monitor/hmp-cmds.c | ||
514 | index XXXXXXX..XXXXXXX 100644 | ||
515 | --- a/monitor/hmp-cmds.c | ||
516 | +++ b/monitor/hmp-cmds.c | ||
517 | @@ -XXX,XX +XXX,XX @@ static void hmp_migrate_status_cb(void *opaque) | ||
518 | error_report("%s", info->error_desc); | ||
519 | } | ||
520 | monitor_resume(status->mon); | ||
521 | - timer_del(status->timer); | ||
522 | timer_free(status->timer); | ||
523 | g_free(status); | ||
524 | } | ||
525 | diff --git a/net/announce.c b/net/announce.c | ||
526 | index XXXXXXX..XXXXXXX 100644 | ||
527 | --- a/net/announce.c | ||
528 | +++ b/net/announce.c | ||
529 | @@ -XXX,XX +XXX,XX @@ void qemu_announce_timer_del(AnnounceTimer *timer, bool free_named) | ||
530 | { | ||
531 | bool free_timer = false; | ||
532 | if (timer->tm) { | ||
533 | - timer_del(timer->tm); | ||
534 | timer_free(timer->tm); | ||
535 | timer->tm = NULL; | ||
536 | } | ||
537 | diff --git a/net/colo-compare.c b/net/colo-compare.c | ||
538 | index XXXXXXX..XXXXXXX 100644 | ||
539 | --- a/net/colo-compare.c | ||
540 | +++ b/net/colo-compare.c | ||
541 | @@ -XXX,XX +XXX,XX @@ static void colo_compare_timer_init(CompareState *s) | ||
542 | static void colo_compare_timer_del(CompareState *s) | ||
543 | { | ||
544 | if (s->packet_check_timer) { | ||
545 | - timer_del(s->packet_check_timer); | ||
546 | timer_free(s->packet_check_timer); | ||
547 | s->packet_check_timer = NULL; | ||
548 | } | ||
549 | diff --git a/net/slirp.c b/net/slirp.c | ||
550 | index XXXXXXX..XXXXXXX 100644 | ||
551 | --- a/net/slirp.c | ||
552 | +++ b/net/slirp.c | ||
553 | @@ -XXX,XX +XXX,XX @@ static void *net_slirp_timer_new(SlirpTimerCb cb, | ||
554 | |||
555 | static void net_slirp_timer_free(void *timer, void *opaque) | ||
556 | { | ||
557 | - timer_del(timer); | ||
558 | timer_free(timer); | ||
559 | } | ||
560 | |||
561 | diff --git a/replay/replay-debugging.c b/replay/replay-debugging.c | ||
562 | index XXXXXXX..XXXXXXX 100644 | ||
563 | --- a/replay/replay-debugging.c | ||
564 | +++ b/replay/replay-debugging.c | ||
565 | @@ -XXX,XX +XXX,XX @@ static void replay_delete_break(void) | ||
566 | assert(replay_mutex_locked()); | ||
567 | |||
568 | if (replay_break_timer) { | ||
569 | - timer_del(replay_break_timer); | ||
570 | timer_free(replay_break_timer); | ||
571 | replay_break_timer = NULL; | ||
572 | } | ||
573 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c | ||
574 | index XXXXXXX..XXXXXXX 100644 | ||
575 | --- a/target/s390x/cpu.c | ||
576 | +++ b/target/s390x/cpu.c | ||
577 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_finalize(Object *obj) | ||
578 | #if !defined(CONFIG_USER_ONLY) | ||
579 | S390CPU *cpu = S390_CPU(obj); | ||
580 | |||
581 | - timer_del(cpu->env.tod_timer); | ||
582 | timer_free(cpu->env.tod_timer); | ||
583 | - timer_del(cpu->env.cpu_timer); | ||
584 | timer_free(cpu->env.cpu_timer); | ||
585 | |||
586 | qemu_unregister_reset(s390_cpu_machine_reset_cb, cpu); | ||
587 | diff --git a/ui/console.c b/ui/console.c | ||
588 | index XXXXXXX..XXXXXXX 100644 | ||
589 | --- a/ui/console.c | ||
590 | +++ b/ui/console.c | ||
591 | @@ -XXX,XX +XXX,XX @@ static void gui_setup_refresh(DisplayState *ds) | ||
592 | timer_mod(ds->gui_timer, qemu_clock_get_ms(QEMU_CLOCK_REALTIME)); | ||
593 | } | ||
594 | if (!need_timer && ds->gui_timer != NULL) { | ||
595 | - timer_del(ds->gui_timer); | ||
596 | timer_free(ds->gui_timer); | ||
597 | ds->gui_timer = NULL; | ||
598 | } | ||
599 | diff --git a/ui/spice-core.c b/ui/spice-core.c | ||
600 | index XXXXXXX..XXXXXXX 100644 | ||
601 | --- a/ui/spice-core.c | ||
602 | +++ b/ui/spice-core.c | ||
603 | @@ -XXX,XX +XXX,XX @@ static void timer_cancel(SpiceTimer *timer) | ||
604 | |||
605 | static void timer_remove(SpiceTimer *timer) | ||
606 | { | ||
607 | - timer_del(timer->timer); | ||
608 | timer_free(timer->timer); | ||
609 | g_free(timer); | ||
610 | } | ||
611 | diff --git a/util/throttle.c b/util/throttle.c | ||
612 | index XXXXXXX..XXXXXXX 100644 | ||
613 | --- a/util/throttle.c | ||
614 | +++ b/util/throttle.c | ||
615 | @@ -XXX,XX +XXX,XX @@ static void throttle_timer_destroy(QEMUTimer **timer) | ||
616 | { | ||
617 | assert(*timer != NULL); | ||
618 | |||
619 | - timer_del(*timer); | ||
620 | timer_free(*timer); | ||
621 | *timer = NULL; | ||
622 | } | ||
623 | -- | ||
624 | 2.20.1 | ||
625 | |||
626 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The Arm CPU finalize function uses a sequence of timer_del(), timer_deinit(), | ||
2 | timer_free() to free the timer. The timer_deinit() step in this was always | ||
3 | unnecessary, and now the timer_del() is implied by timer_free(), so we can | ||
4 | collapse this down to simply calling timer_free(). | ||
1 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20201215154107.3255-5-peter.maydell@linaro.org | ||
10 | --- | ||
11 | target/arm/cpu.c | 2 -- | ||
12 | 1 file changed, 2 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/cpu.c | ||
17 | +++ b/target/arm/cpu.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_finalizefn(Object *obj) | ||
19 | } | ||
20 | #ifndef CONFIG_USER_ONLY | ||
21 | if (cpu->pmu_timer) { | ||
22 | - timer_del(cpu->pmu_timer); | ||
23 | - timer_deinit(cpu->pmu_timer); | ||
24 | timer_free(cpu->pmu_timer); | ||
25 | } | ||
26 | #endif | ||
27 | -- | ||
28 | 2.20.1 | ||
29 | |||
30 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Gan Qixin <ganqixin@huawei.com> | ||
1 | 2 | ||
3 | When running device-introspect-test, a memory leak occurred in the | ||
4 | digic_timer_init function, so use ptimer_free() in the finalize function to | ||
5 | avoid it. | ||
6 | |||
7 | ASAN shows memory leak stack: | ||
8 | |||
9 | Indirect leak of 288 byte(s) in 3 object(s) allocated from: | ||
10 | #0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0) | ||
11 | #1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800) | ||
12 | #2 0xaaabf555db78 in ptimer_init /qemu/hw/core/ptimer.c:432 | ||
13 | #3 0xaaabf5b04084 in digic_timer_init /qemu/hw/timer/digic-timer.c:142 | ||
14 | #4 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 | ||
15 | #5 0xaaabf633ca04 in object_initialize_child_with_propsv /qemu/qom/object.c:564 | ||
16 | #6 0xaaabf633cc08 in object_initialize_child_with_props /qemu/qom/object.c:547 | ||
17 | #7 0xaaabf5b40e84 in digic_init /qemu/hw/arm/digic.c:46 | ||
18 | #8 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 | ||
19 | #9 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729 | ||
20 | #10 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153 | ||
21 | #11 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59 | ||
22 | #12 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110 | ||
23 | |||
24 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
25 | Signed-off-by: Gan Qixin <ganqixin@huawei.com> | ||
26 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
28 | --- | ||
29 | hw/timer/digic-timer.c | 8 ++++++++ | ||
30 | 1 file changed, 8 insertions(+) | ||
31 | |||
32 | diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/hw/timer/digic-timer.c | ||
35 | +++ b/hw/timer/digic-timer.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static void digic_timer_init(Object *obj) | ||
37 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); | ||
38 | } | ||
39 | |||
40 | +static void digic_timer_finalize(Object *obj) | ||
41 | +{ | ||
42 | + DigicTimerState *s = DIGIC_TIMER(obj); | ||
43 | + | ||
44 | + ptimer_free(s->ptimer); | ||
45 | +} | ||
46 | + | ||
47 | static void digic_timer_class_init(ObjectClass *klass, void *class_data) | ||
48 | { | ||
49 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
50 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo digic_timer_info = { | ||
51 | .parent = TYPE_SYS_BUS_DEVICE, | ||
52 | .instance_size = sizeof(DigicTimerState), | ||
53 | .instance_init = digic_timer_init, | ||
54 | + .instance_finalize = digic_timer_finalize, | ||
55 | .class_init = digic_timer_class_init, | ||
56 | }; | ||
57 | |||
58 | -- | ||
59 | 2.20.1 | ||
60 | |||
61 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Gan Qixin <ganqixin@huawei.com> | ||
1 | 2 | ||
3 | When running device-introspect-test, a memory leak occurred in the a10_pit_init | ||
4 | function, so use ptimer_free() in the finalize function to avoid it. | ||
5 | |||
6 | ASAN shows memory leak stack: | ||
7 | |||
8 | Indirect leak of 288 byte(s) in 6 object(s) allocated from: | ||
9 | #0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0) | ||
10 | #1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800) | ||
11 | #2 0xaaabf555db84 in timer_new_full /qemu/include/qemu/timer.h:523 | ||
12 | #3 0xaaabf555db84 in timer_new /qemu/include/qemu/timer.h:544 | ||
13 | #4 0xaaabf555db84 in timer_new_ns /qemu/include/qemu/timer.h:562 | ||
14 | #5 0xaaabf555db84 in ptimer_init /qemu/hw/core/ptimer.c:433 | ||
15 | #6 0xaaabf57415e8 in a10_pit_init /qemu/hw/timer/allwinner-a10-pit.c:278 | ||
16 | #7 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 | ||
17 | #8 0xaaabf633ca04 in object_initialize_child_with_propsv /qemu/qom/object.c:564 | ||
18 | #9 0xaaabf633cc08 in object_initialize_child_with_props /qemu/qom/object.c:547 | ||
19 | #10 0xaaabf5b94680 in aw_a10_init /qemu/hw/arm/allwinner-a10.c:49 | ||
20 | #11 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 | ||
21 | #12 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729 | ||
22 | |||
23 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
24 | Signed-off-by: Gan Qixin <ganqixin@huawei.com> | ||
25 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
27 | --- | ||
28 | hw/timer/allwinner-a10-pit.c | 11 +++++++++++ | ||
29 | 1 file changed, 11 insertions(+) | ||
30 | |||
31 | diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/hw/timer/allwinner-a10-pit.c | ||
34 | +++ b/hw/timer/allwinner-a10-pit.c | ||
35 | @@ -XXX,XX +XXX,XX @@ static void a10_pit_init(Object *obj) | ||
36 | } | ||
37 | } | ||
38 | |||
39 | +static void a10_pit_finalize(Object *obj) | ||
40 | +{ | ||
41 | + AwA10PITState *s = AW_A10_PIT(obj); | ||
42 | + int i; | ||
43 | + | ||
44 | + for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { | ||
45 | + ptimer_free(s->timer[i]); | ||
46 | + } | ||
47 | +} | ||
48 | + | ||
49 | static void a10_pit_class_init(ObjectClass *klass, void *data) | ||
50 | { | ||
51 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
52 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo a10_pit_info = { | ||
53 | .parent = TYPE_SYS_BUS_DEVICE, | ||
54 | .instance_size = sizeof(AwA10PITState), | ||
55 | .instance_init = a10_pit_init, | ||
56 | + .instance_finalize = a10_pit_finalize, | ||
57 | .class_init = a10_pit_class_init, | ||
58 | }; | ||
59 | |||
60 | -- | ||
61 | 2.20.1 | ||
62 | |||
63 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Gan Qixin <ganqixin@huawei.com> | ||
1 | 2 | ||
3 | When running device-introspect-test, a memory leak occurred in the | ||
4 | exynos4210_rtc_init function, so use ptimer_free() in the finalize function to | ||
5 | avoid it. | ||
6 | |||
7 | ASAN shows memory leak stack: | ||
8 | |||
9 | Indirect leak of 96 byte(s) in 1 object(s) allocated from: | ||
10 | #0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0) | ||
11 | #1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800) | ||
12 | #2 0xaaabf555db78 in ptimer_init /qemu/hw/core/ptimer.c:432 | ||
13 | #3 0xaaabf57b3934 in exynos4210_rtc_init /qemu/hw/rtc/exynos4210_rtc.c:567 | ||
14 | #4 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 | ||
15 | #5 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729 | ||
16 | #6 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153 | ||
17 | #7 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59 | ||
18 | #8 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110 | ||
19 | #9 0xaaabf6552708 in aio_bh_call /qemu/util/async.c:136 | ||
20 | #10 0xaaabf6552708 in aio_bh_poll /qemu/util/async.c:164 | ||
21 | #11 0xaaabf655f19c in aio_dispatch /qemu/util/aio-posix.c:381 | ||
22 | #12 0xaaabf65523f4 in aio_ctx_dispatch /qemu/util/async.c:306 | ||
23 | |||
24 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
25 | Signed-off-by: Gan Qixin <ganqixin@huawei.com> | ||
26 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
28 | --- | ||
29 | hw/rtc/exynos4210_rtc.c | 9 +++++++++ | ||
30 | 1 file changed, 9 insertions(+) | ||
31 | |||
32 | diff --git a/hw/rtc/exynos4210_rtc.c b/hw/rtc/exynos4210_rtc.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/hw/rtc/exynos4210_rtc.c | ||
35 | +++ b/hw/rtc/exynos4210_rtc.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_init(Object *obj) | ||
37 | sysbus_init_mmio(dev, &s->iomem); | ||
38 | } | ||
39 | |||
40 | +static void exynos4210_rtc_finalize(Object *obj) | ||
41 | +{ | ||
42 | + Exynos4210RTCState *s = EXYNOS4210_RTC(obj); | ||
43 | + | ||
44 | + ptimer_free(s->ptimer); | ||
45 | + ptimer_free(s->ptimer_1Hz); | ||
46 | +} | ||
47 | + | ||
48 | static void exynos4210_rtc_class_init(ObjectClass *klass, void *data) | ||
49 | { | ||
50 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
51 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo exynos4210_rtc_info = { | ||
52 | .parent = TYPE_SYS_BUS_DEVICE, | ||
53 | .instance_size = sizeof(Exynos4210RTCState), | ||
54 | .instance_init = exynos4210_rtc_init, | ||
55 | + .instance_finalize = exynos4210_rtc_finalize, | ||
56 | .class_init = exynos4210_rtc_class_init, | ||
57 | }; | ||
58 | |||
59 | -- | ||
60 | 2.20.1 | ||
61 | |||
62 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Gan Qixin <ganqixin@huawei.com> | ||
1 | 2 | ||
3 | When running device-introspect-test, a memory leak occurred in the | ||
4 | exynos4210_pwm_init function, so use ptimer_free() in the finalize function to | ||
5 | avoid it. | ||
6 | |||
7 | ASAN shows memory leak stack: | ||
8 | |||
9 | Indirect leak of 240 byte(s) in 5 object(s) allocated from: | ||
10 | #0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0) | ||
11 | #1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800) | ||
12 | #2 0xaaabf555db84 in timer_new_full /qemu/include/qemu/timer.h:523 | ||
13 | #3 0xaaabf555db84 in timer_new /qemu/include/qemu/timer.h:544 | ||
14 | #4 0xaaabf555db84 in timer_new_ns /qemu/include/qemu/timer.h:562 | ||
15 | #5 0xaaabf555db84 in ptimer_init /qemu/hw/core/ptimer.c:433 | ||
16 | #6 0xaaabf56a36cc in exynos4210_pwm_init /qemu/hw/timer/exynos4210_pwm.c:401 | ||
17 | #7 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 | ||
18 | #8 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729 | ||
19 | #9 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153 | ||
20 | #10 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59 | ||
21 | #11 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110 | ||
22 | #12 0xaaabf6552708 in aio_bh_call /qemu/util/async.c:136 | ||
23 | |||
24 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
25 | Signed-off-by: Gan Qixin <ganqixin@huawei.com> | ||
26 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
28 | --- | ||
29 | hw/timer/exynos4210_pwm.c | 11 +++++++++++ | ||
30 | 1 file changed, 11 insertions(+) | ||
31 | |||
32 | diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/hw/timer/exynos4210_pwm.c | ||
35 | +++ b/hw/timer/exynos4210_pwm.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_init(Object *obj) | ||
37 | sysbus_init_mmio(dev, &s->iomem); | ||
38 | } | ||
39 | |||
40 | +static void exynos4210_pwm_finalize(Object *obj) | ||
41 | +{ | ||
42 | + Exynos4210PWMState *s = EXYNOS4210_PWM(obj); | ||
43 | + int i; | ||
44 | + | ||
45 | + for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { | ||
46 | + ptimer_free(s->timer[i].ptimer); | ||
47 | + } | ||
48 | +} | ||
49 | + | ||
50 | static void exynos4210_pwm_class_init(ObjectClass *klass, void *data) | ||
51 | { | ||
52 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
53 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo exynos4210_pwm_info = { | ||
54 | .parent = TYPE_SYS_BUS_DEVICE, | ||
55 | .instance_size = sizeof(Exynos4210PWMState), | ||
56 | .instance_init = exynos4210_pwm_init, | ||
57 | + .instance_finalize = exynos4210_pwm_finalize, | ||
58 | .class_init = exynos4210_pwm_class_init, | ||
59 | }; | ||
60 | |||
61 | -- | ||
62 | 2.20.1 | ||
63 | |||
64 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Gan Qixin <ganqixin@huawei.com> | ||
1 | 2 | ||
3 | When running device-introspect-test, a memory leak occurred in the | ||
4 | mss_timer_init function, so use ptimer_free() in the finalize function to avoid | ||
5 | it. | ||
6 | |||
7 | ASAN shows memory leak stack: | ||
8 | |||
9 | Indirect leak of 192 byte(s) in 2 object(s) allocated from: | ||
10 | #0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0) | ||
11 | #1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800) | ||
12 | #2 0xaaabf555db78 in ptimer_init /qemu/hw/core/ptimer.c:432 | ||
13 | #3 0xaaabf58a0010 in mss_timer_init /qemu/hw/timer/mss-timer.c:235 | ||
14 | #4 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 | ||
15 | #5 0xaaabf633ca04 in object_initialize_child_with_propsv /qemu/qom/object.c:564 | ||
16 | #6 0xaaabf633cc08 in object_initialize_child_with_props /qemu/qom/object.c:547 | ||
17 | #7 0xaaabf5b8316c in m2sxxx_soc_initfn /qemu/hw/arm/msf2-soc.c:70 | ||
18 | #8 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 | ||
19 | #9 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729 | ||
20 | #10 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153 | ||
21 | #11 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59 | ||
22 | #12 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110 | ||
23 | |||
24 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
25 | Signed-off-by: Gan Qixin <ganqixin@huawei.com> | ||
26 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
28 | --- | ||
29 | hw/timer/mss-timer.c | 13 +++++++++++++ | ||
30 | 1 file changed, 13 insertions(+) | ||
31 | |||
32 | diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/hw/timer/mss-timer.c | ||
35 | +++ b/hw/timer/mss-timer.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static void mss_timer_init(Object *obj) | ||
37 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio); | ||
38 | } | ||
39 | |||
40 | +static void mss_timer_finalize(Object *obj) | ||
41 | +{ | ||
42 | + MSSTimerState *t = MSS_TIMER(obj); | ||
43 | + int i; | ||
44 | + | ||
45 | + for (i = 0; i < NUM_TIMERS; i++) { | ||
46 | + struct Msf2Timer *st = &t->timers[i]; | ||
47 | + | ||
48 | + ptimer_free(st->ptimer); | ||
49 | + } | ||
50 | +} | ||
51 | + | ||
52 | static const VMStateDescription vmstate_timers = { | ||
53 | .name = "mss-timer-block", | ||
54 | .version_id = 1, | ||
55 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo mss_timer_info = { | ||
56 | .parent = TYPE_SYS_BUS_DEVICE, | ||
57 | .instance_size = sizeof(MSSTimerState), | ||
58 | .instance_init = mss_timer_init, | ||
59 | + .instance_finalize = mss_timer_finalize, | ||
60 | .class_init = mss_timer_class_init, | ||
61 | }; | ||
62 | |||
63 | -- | ||
64 | 2.20.1 | ||
65 | |||
66 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Gan Qixin <ganqixin@huawei.com> | ||
1 | 2 | ||
3 | When running device-introspect-test, a memory leak occurred in the | ||
4 | mv88w8618_pit_init function, so use ptimer_free() in the finalize function to | ||
5 | avoid it. | ||
6 | |||
7 | ASAN shows memory leak stack: | ||
8 | |||
9 | Indirect leak of 192 byte(s) in 4 object(s) allocated from: | ||
10 | #0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0) | ||
11 | #1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800) | ||
12 | #2 0xaaabf555db84 in timer_new_full /qemu/include/qemu/timer.h:523 | ||
13 | #3 0xaaabf555db84 in timer_new /qemu/include/qemu/timer.h:544 | ||
14 | #4 0xaaabf555db84 in timer_new_ns /qemu/include/qemu/timer.h:562 | ||
15 | #5 0xaaabf555db84 in ptimer_init /qemu/hw/core/ptimer.c:433 | ||
16 | #6 0xaaabf5bb2290 in mv88w8618_timer_init /qemu/hw/arm/musicpal.c:862 | ||
17 | #7 0xaaabf5bb2290 in mv88w8618_pit_init /qemu/hw/arm/musicpal.c:954 | ||
18 | #8 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 | ||
19 | #9 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729 | ||
20 | #10 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153 | ||
21 | #11 0xaaabf5a95540 in qdev_device_help /qemu/softmmu/qdev-monitor.c:283 | ||
22 | #12 0xaaabf5a96940 in qmp_device_add /qemu/softmmu/qdev-monitor.c:801 | ||
23 | |||
24 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
25 | Signed-off-by: Gan Qixin <ganqixin@huawei.com> | ||
26 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
28 | --- | ||
29 | hw/arm/musicpal.c | 12 ++++++++++++ | ||
30 | 1 file changed, 12 insertions(+) | ||
31 | |||
32 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/hw/arm/musicpal.c | ||
35 | +++ b/hw/arm/musicpal.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static void mv88w8618_pit_init(Object *obj) | ||
37 | sysbus_init_mmio(dev, &s->iomem); | ||
38 | } | ||
39 | |||
40 | +static void mv88w8618_pit_finalize(Object *obj) | ||
41 | +{ | ||
42 | + SysBusDevice *dev = SYS_BUS_DEVICE(obj); | ||
43 | + mv88w8618_pit_state *s = MV88W8618_PIT(dev); | ||
44 | + int i; | ||
45 | + | ||
46 | + for (i = 0; i < 4; i++) { | ||
47 | + ptimer_free(s->timer[i].ptimer); | ||
48 | + } | ||
49 | +} | ||
50 | + | ||
51 | static const VMStateDescription mv88w8618_timer_vmsd = { | ||
52 | .name = "timer", | ||
53 | .version_id = 1, | ||
54 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo mv88w8618_pit_info = { | ||
55 | .parent = TYPE_SYS_BUS_DEVICE, | ||
56 | .instance_size = sizeof(mv88w8618_pit_state), | ||
57 | .instance_init = mv88w8618_pit_init, | ||
58 | + .instance_finalize = mv88w8618_pit_finalize, | ||
59 | .class_init = mv88w8618_pit_class_init, | ||
60 | }; | ||
61 | |||
62 | -- | ||
63 | 2.20.1 | ||
64 | |||
65 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Gan Qixin <ganqixin@huawei.com> | ||
1 | 2 | ||
3 | When running device-introspect-test, a memory leak occurred in the | ||
4 | exynos4210_mct_init function, so use ptimer_free() in the finalize function to | ||
5 | avoid it. | ||
6 | |||
7 | ASAN shows memory leak stack: | ||
8 | |||
9 | Indirect leak of 96 byte(s) in 1 object(s) allocated from: | ||
10 | #0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0) | ||
11 | #1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800) | ||
12 | #2 0xaaabf555db78 in ptimer_init /qemu/hw/core/ptimer.c:432 | ||
13 | #3 0xaaabf56b01a0 in exynos4210_mct_init /qemu/hw/timer/exynos4210_mct.c:1505 | ||
14 | #4 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 | ||
15 | #5 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729 | ||
16 | #6 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153 | ||
17 | #7 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59 | ||
18 | #8 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110 | ||
19 | #9 0xaaabf6552708 in aio_bh_call /qemu/util/async.c:136 | ||
20 | #10 0xaaabf6552708 in aio_bh_poll /qemu/util/async.c:164 | ||
21 | #11 0xaaabf655f19c in aio_dispatch /qemu/util/aio-posix.c:381 | ||
22 | #12 0xaaabf65523f4 in aio_ctx_dispatch /qemu/util/async.c:306 | ||
23 | |||
24 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
25 | Signed-off-by: Gan Qixin <ganqixin@huawei.com> | ||
26 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
28 | --- | ||
29 | hw/timer/exynos4210_mct.c | 14 ++++++++++++++ | ||
30 | 1 file changed, 14 insertions(+) | ||
31 | |||
32 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/hw/timer/exynos4210_mct.c | ||
35 | +++ b/hw/timer/exynos4210_mct.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_init(Object *obj) | ||
37 | sysbus_init_mmio(dev, &s->iomem); | ||
38 | } | ||
39 | |||
40 | +static void exynos4210_mct_finalize(Object *obj) | ||
41 | +{ | ||
42 | + int i; | ||
43 | + Exynos4210MCTState *s = EXYNOS4210_MCT(obj); | ||
44 | + | ||
45 | + ptimer_free(s->g_timer.ptimer_frc); | ||
46 | + | ||
47 | + for (i = 0; i < 2; i++) { | ||
48 | + ptimer_free(s->l_timer[i].tick_timer.ptimer_tick); | ||
49 | + ptimer_free(s->l_timer[i].ptimer_frc); | ||
50 | + } | ||
51 | +} | ||
52 | + | ||
53 | static void exynos4210_mct_class_init(ObjectClass *klass, void *data) | ||
54 | { | ||
55 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
56 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo exynos4210_mct_info = { | ||
57 | .parent = TYPE_SYS_BUS_DEVICE, | ||
58 | .instance_size = sizeof(Exynos4210MCTState), | ||
59 | .instance_init = exynos4210_mct_init, | ||
60 | + .instance_finalize = exynos4210_mct_finalize, | ||
61 | .class_init = exynos4210_mct_class_init, | ||
62 | }; | ||
63 | |||
64 | -- | ||
65 | 2.20.1 | ||
66 | |||
67 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bin Meng <bin.meng@windriver.com> | ||
1 | 2 | ||
3 | U-Boot expects PMU_MISC0 register bit 7 is set (see init_bandgap() | ||
4 | in arch/arm/mach-imx/mx6/soc.c) during boot. This bit indicates the | ||
5 | bandgap has stabilized. | ||
6 | |||
7 | With this change, the latest upstream U-Boot (v2021.01-rc3) for imx6 | ||
8 | sabrelite board (mx6qsabrelite_defconfig), with a slight change made | ||
9 | by switching CONFIG_OF_SEPARATE to CONFIG_OF_EMBED, boots to U-Boot | ||
10 | shell on QEMU with the following command: | ||
11 | |||
12 | $ qemu-system-arm -M sabrelite -smp 4 -m 1G -kernel u-boot \ | ||
13 | -display none -serial null -serial stdio | ||
14 | |||
15 | Boot log below: | ||
16 | |||
17 | U-Boot 2021.01-rc3 (Dec 12 2020 - 17:40:02 +0800) | ||
18 | |||
19 | CPU: Freescale i.MX?? rev1.0 at 792 MHz | ||
20 | Reset cause: POR | ||
21 | Model: Freescale i.MX6 Quad SABRE Lite Board | ||
22 | Board: SABRE Lite | ||
23 | I2C: ready | ||
24 | DRAM: 1 GiB | ||
25 | force_idle_bus: sda=0 scl=0 sda.gp=0x5c scl.gp=0x55 | ||
26 | force_idle_bus: failed to clear bus, sda=0 scl=0 | ||
27 | force_idle_bus: sda=0 scl=0 sda.gp=0x6d scl.gp=0x6c | ||
28 | force_idle_bus: failed to clear bus, sda=0 scl=0 | ||
29 | force_idle_bus: sda=0 scl=0 sda.gp=0xcb scl.gp=0x5 | ||
30 | force_idle_bus: failed to clear bus, sda=0 scl=0 | ||
31 | MMC: FSL_SDHC: 0, FSL_SDHC: 1 | ||
32 | Loading Environment from MMC... *** Warning - No block device, using default environment | ||
33 | |||
34 | In: serial | ||
35 | Out: serial | ||
36 | Err: serial | ||
37 | Net: Board Net Initialization Failed | ||
38 | No ethernet found. | ||
39 | starting USB... | ||
40 | Bus usb@2184000: usb dr_mode not found | ||
41 | USB EHCI 1.00 | ||
42 | Bus usb@2184200: USB EHCI 1.00 | ||
43 | scanning bus usb@2184000 for devices... 1 USB Device(s) found | ||
44 | scanning bus usb@2184200 for devices... 1 USB Device(s) found | ||
45 | scanning usb for storage devices... 0 Storage Device(s) found | ||
46 | scanning usb for ethernet devices... 0 Ethernet Device(s) found | ||
47 | Hit any key to stop autoboot: 0 | ||
48 | => | ||
49 | |||
50 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
51 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
52 | Message-id: 20210106063504.10841-2-bmeng.cn@gmail.com | ||
53 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
54 | --- | ||
55 | hw/misc/imx6_ccm.c | 2 +- | ||
56 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
57 | |||
58 | diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/hw/misc/imx6_ccm.c | ||
61 | +++ b/hw/misc/imx6_ccm.c | ||
62 | @@ -XXX,XX +XXX,XX @@ static void imx6_ccm_reset(DeviceState *dev) | ||
63 | s->analog[PMU_REG_3P0] = 0x00000F74; | ||
64 | s->analog[PMU_REG_2P5] = 0x00005071; | ||
65 | s->analog[PMU_REG_CORE] = 0x00402010; | ||
66 | - s->analog[PMU_MISC0] = 0x04000000; | ||
67 | + s->analog[PMU_MISC0] = 0x04000080; | ||
68 | s->analog[PMU_MISC1] = 0x00000000; | ||
69 | s->analog[PMU_MISC2] = 0x00272727; | ||
70 | |||
71 | -- | ||
72 | 2.20.1 | ||
73 | |||
74 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bin Meng <bin.meng@windriver.com> | ||
1 | 2 | ||
3 | Currently when U-Boot boots, it prints "??" for i.MX processor: | ||
4 | |||
5 | CPU: Freescale i.MX?? rev1.0 at 792 MHz | ||
6 | |||
7 | The register that was used to determine the silicon type is | ||
8 | undocumented in the latest IMX6DQRM (Rev. 6, 05/2020), but we | ||
9 | can refer to get_cpu_rev() in arch/arm/mach-imx/mx6/soc.c in | ||
10 | the U-Boot source codes that USB_ANALOG_DIGPROG is used. | ||
11 | |||
12 | Update its reset value to indicate i.MX6Q. | ||
13 | |||
14 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
15 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
16 | Message-id: 20210106063504.10841-3-bmeng.cn@gmail.com | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | --- | ||
19 | hw/misc/imx6_ccm.c | 2 +- | ||
20 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
21 | |||
22 | diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/hw/misc/imx6_ccm.c | ||
25 | +++ b/hw/misc/imx6_ccm.c | ||
26 | @@ -XXX,XX +XXX,XX @@ static void imx6_ccm_reset(DeviceState *dev) | ||
27 | s->analog[USB_ANALOG_USB2_VBUS_DETECT] = 0x00000004; | ||
28 | s->analog[USB_ANALOG_USB2_CHRG_DETECT] = 0x00000000; | ||
29 | s->analog[USB_ANALOG_USB2_MISC] = 0x00000002; | ||
30 | - s->analog[USB_ANALOG_DIGPROG] = 0x00000000; | ||
31 | + s->analog[USB_ANALOG_DIGPROG] = 0x00630000; | ||
32 | |||
33 | /* all PLLs need to be locked */ | ||
34 | s->analog[CCM_ANALOG_PLL_ARM] |= CCM_ANALOG_PLL_LOCK; | ||
35 | -- | ||
36 | 2.20.1 | ||
37 | |||
38 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bin Meng <bin.meng@windriver.com> | ||
1 | 2 | ||
3 | At present, when booting U-Boot on QEMU sabrelite, we see: | ||
4 | |||
5 | Net: Board Net Initialization Failed | ||
6 | No ethernet found. | ||
7 | |||
8 | U-Boot scans PHY at address 4/5/6/7 (see board_eth_init() in the | ||
9 | U-Boot source: board/boundary/nitrogen6x/nitrogen6x.c). On the real | ||
10 | board, the Ethernet PHY is at address 6. Adjust this by updating the | ||
11 | "fec-phy-num" property of the fsl_imx6 SoC object. | ||
12 | |||
13 | With this change, U-Boot sees the PHY but complains MAC address: | ||
14 | |||
15 | Net: using phy at 6 | ||
16 | FEC [PRIME] | ||
17 | Error: FEC address not set. | ||
18 | |||
19 | This is due to U-Boot tries to read the MAC address from the fuse, | ||
20 | which QEMU does not have any valid content filled in. However this | ||
21 | does not prevent the Ethernet from working in QEMU. We just need to | ||
22 | set up the MAC address later in the U-Boot command shell, by: | ||
23 | |||
24 | => setenv ethaddr 00:11:22:33:44:55 | ||
25 | |||
26 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
27 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
28 | Message-id: 20210106063504.10841-4-bmeng.cn@gmail.com | ||
29 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
30 | --- | ||
31 | hw/arm/sabrelite.c | 4 ++++ | ||
32 | 1 file changed, 4 insertions(+) | ||
33 | |||
34 | diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/hw/arm/sabrelite.c | ||
37 | +++ b/hw/arm/sabrelite.c | ||
38 | @@ -XXX,XX +XXX,XX @@ static void sabrelite_init(MachineState *machine) | ||
39 | |||
40 | s = FSL_IMX6(object_new(TYPE_FSL_IMX6)); | ||
41 | object_property_add_child(OBJECT(machine), "soc", OBJECT(s)); | ||
42 | + | ||
43 | + /* Ethernet PHY address is 6 */ | ||
44 | + object_property_set_int(OBJECT(s), "fec-phy-num", 6, &error_fatal); | ||
45 | + | ||
46 | qdev_realize(DEVICE(s), NULL, &error_fatal); | ||
47 | |||
48 | memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR, | ||
49 | -- | ||
50 | 2.20.1 | ||
51 | |||
52 | diff view generated by jsdifflib |
1 | From: Clement Deschamps <clement.deschamps@greensocs.com> | 1 | From: Bin Meng <bin.meng@windriver.com> |
---|---|---|---|
2 | 2 | ||
3 | The boot.c code usually puts the CPU into NS mode directly when it is | 3 | This adds the target guide for SABRE Lite board, and documents how |
4 | booting a kernel. Since fc1120a7f5f2d4b6 this has included a | 4 | to boot a Linux kernel and U-Boot bootloader. |
5 | requirement to set NSACR to give NS state access to the FPU; we fixed | ||
6 | that for the usual code path in ece628fcf6. However, it is also | ||
7 | possible for a board model to request an alternative mode of booting, | ||
8 | where its 'board_setup' code hook runs in Secure state and is | ||
9 | responsible for doing the S->NS transition after it has done whatever | ||
10 | work it must do in Secure state. In this situation the board_setup | ||
11 | code now also needs to update NSACR. | ||
12 | 5 | ||
13 | This affects all boards which set info->secure_board_setup, which is | 6 | Signed-off-by: Bin Meng <bin.meng@windriver.com> |
14 | currently the 'raspi' and 'highbank' families. They both use the | 7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
15 | common arm_write_secure_board_setup_dummy_smc(). | 8 | Message-id: 20210106063504.10841-5-bmeng.cn@gmail.com |
16 | |||
17 | Set the NSACR CP11 and CP10 bits in the code written by that | ||
18 | function, to allow FPU access in Non-Secure state when using dummy | ||
19 | SMC setup routine. Otherwise an AArch32 kernel booted on the | ||
20 | highbank or raspi boards will UNDEF as soon as it tries to use the | ||
21 | FPU. | ||
22 | |||
23 | Update the comment describing secure_board_setup to note the new | ||
24 | requirements on users of it. | ||
25 | |||
26 | This fixes a kernel panic when booting raspbian on raspi2. | ||
27 | |||
28 | Successfully tested with: | ||
29 | 2017-01-11-raspbian-jessie-lite.img | ||
30 | 2018-11-13-raspbian-stretch-lite.img | ||
31 | 2019-07-10-raspbian-buster-lite.img | ||
32 | |||
33 | Fixes: fc1120a7f5 | ||
34 | Signed-off-by: Clement Deschamps <clement.deschamps@greensocs.com> | ||
35 | Tested-by: Laurent Bonnans <laurent.bonnans@here.com> | ||
36 | Message-id: 20191104151137.81931-1-clement.deschamps@greensocs.com | ||
37 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
38 | [PMM: updated comment to boot.h to note new requirement on | ||
39 | users of secure_board_setup; edited/rewrote commit message] | ||
40 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
41 | --- | 10 | --- |
42 | include/hw/arm/boot.h | 7 +++++-- | 11 | docs/system/arm/sabrelite.rst | 119 ++++++++++++++++++++++++++++++++++ |
43 | hw/arm/boot.c | 3 +++ | 12 | docs/system/target-arm.rst | 1 + |
44 | 2 files changed, 8 insertions(+), 2 deletions(-) | 13 | 2 files changed, 120 insertions(+) |
14 | create mode 100644 docs/system/arm/sabrelite.rst | ||
45 | 15 | ||
46 | diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h | 16 | diff --git a/docs/system/arm/sabrelite.rst b/docs/system/arm/sabrelite.rst |
17 | new file mode 100644 | ||
18 | index XXXXXXX..XXXXXXX | ||
19 | --- /dev/null | ||
20 | +++ b/docs/system/arm/sabrelite.rst | ||
21 | @@ -XXX,XX +XXX,XX @@ | ||
22 | +Boundary Devices SABRE Lite (``sabrelite``) | ||
23 | +=========================================== | ||
24 | + | ||
25 | +Boundary Devices SABRE Lite i.MX6 Development Board is a low-cost development | ||
26 | +platform featuring the powerful Freescale / NXP Semiconductor's i.MX 6 Quad | ||
27 | +Applications Processor. | ||
28 | + | ||
29 | +Supported devices | ||
30 | +----------------- | ||
31 | + | ||
32 | +The SABRE Lite machine supports the following devices: | ||
33 | + | ||
34 | + * Up to 4 Cortex A9 cores | ||
35 | + * Generic Interrupt Controller | ||
36 | + * 1 Clock Controller Module | ||
37 | + * 1 System Reset Controller | ||
38 | + * 5 UARTs | ||
39 | + * 2 EPIC timers | ||
40 | + * 1 GPT timer | ||
41 | + * 2 Watchdog timers | ||
42 | + * 1 FEC Ethernet controller | ||
43 | + * 3 I2C controllers | ||
44 | + * 7 GPIO controllers | ||
45 | + * 4 SDHC storage controllers | ||
46 | + * 4 USB 2.0 host controllers | ||
47 | + * 5 ECSPI controllers | ||
48 | + * 1 SST 25VF016B flash | ||
49 | + | ||
50 | +Please note above list is a complete superset the QEMU SABRE Lite machine can | ||
51 | +support. For a normal use case, a device tree blob that represents a real world | ||
52 | +SABRE Lite board, only exposes a subset of devices to the guest software. | ||
53 | + | ||
54 | +Boot options | ||
55 | +------------ | ||
56 | + | ||
57 | +The SABRE Lite machine can start using the standard -kernel functionality | ||
58 | +for loading a Linux kernel, U-Boot bootloader or ELF executable. | ||
59 | + | ||
60 | +Running Linux kernel | ||
61 | +-------------------- | ||
62 | + | ||
63 | +Linux mainline v5.10 release is tested at the time of writing. To build a Linux | ||
64 | +mainline kernel that can be booted by the SABRE Lite machine, simply configure | ||
65 | +the kernel using the imx_v6_v7_defconfig configuration: | ||
66 | + | ||
67 | +.. code-block:: bash | ||
68 | + | ||
69 | + $ export ARCH=arm | ||
70 | + $ export CROSS_COMPILE=arm-linux-gnueabihf- | ||
71 | + $ make imx_v6_v7_defconfig | ||
72 | + $ make | ||
73 | + | ||
74 | +To boot the newly built Linux kernel in QEMU with the SABRE Lite machine, use: | ||
75 | + | ||
76 | +.. code-block:: bash | ||
77 | + | ||
78 | + $ qemu-system-arm -M sabrelite -smp 4 -m 1G \ | ||
79 | + -display none -serial null -serial stdio \ | ||
80 | + -kernel arch/arm/boot/zImage \ | ||
81 | + -dtb arch/arm/boot/dts/imx6q-sabrelite.dtb \ | ||
82 | + -initrd /path/to/rootfs.ext4 \ | ||
83 | + -append "root=/dev/ram" | ||
84 | + | ||
85 | +Running U-Boot | ||
86 | +-------------- | ||
87 | + | ||
88 | +U-Boot mainline v2020.10 release is tested at the time of writing. To build a | ||
89 | +U-Boot mainline bootloader that can be booted by the SABRE Lite machine, use | ||
90 | +the mx6qsabrelite_defconfig with similar commands as described above for Linux: | ||
91 | + | ||
92 | +.. code-block:: bash | ||
93 | + | ||
94 | + $ export CROSS_COMPILE=arm-linux-gnueabihf- | ||
95 | + $ make mx6qsabrelite_defconfig | ||
96 | + | ||
97 | +Note we need to adjust settings by: | ||
98 | + | ||
99 | +.. code-block:: bash | ||
100 | + | ||
101 | + $ make menuconfig | ||
102 | + | ||
103 | +then manually select the following configuration in U-Boot: | ||
104 | + | ||
105 | + Device Tree Control > Provider of DTB for DT Control > Embedded DTB | ||
106 | + | ||
107 | +To start U-Boot using the SABRE Lite machine, provide the u-boot binary to | ||
108 | +the -kernel argument, along with an SD card image with rootfs: | ||
109 | + | ||
110 | +.. code-block:: bash | ||
111 | + | ||
112 | + $ qemu-system-arm -M sabrelite -smp 4 -m 1G \ | ||
113 | + -display none -serial null -serial stdio \ | ||
114 | + -kernel u-boot | ||
115 | + | ||
116 | +The following example shows booting Linux kernel from dhcp, and uses the | ||
117 | +rootfs on an SD card. This requires some additional command line parameters | ||
118 | +for QEMU: | ||
119 | + | ||
120 | +.. code-block:: none | ||
121 | + | ||
122 | + -nic user,tftp=/path/to/kernel/zImage \ | ||
123 | + -drive file=sdcard.img,id=rootfs -device sd-card,drive=rootfs | ||
124 | + | ||
125 | +The directory for the built-in TFTP server should also contain the device tree | ||
126 | +blob of the SABRE Lite board. The sample SD card image was populated with the | ||
127 | +root file system with one single partition. You may adjust the kernel "root=" | ||
128 | +boot parameter accordingly. | ||
129 | + | ||
130 | +After U-Boot boots, type the following commands in the U-Boot command shell to | ||
131 | +boot the Linux kernel: | ||
132 | + | ||
133 | +.. code-block:: none | ||
134 | + | ||
135 | + => setenv ethaddr 00:11:22:33:44:55 | ||
136 | + => setenv bootfile zImage | ||
137 | + => dhcp | ||
138 | + => tftpboot 14000000 imx6q-sabrelite.dtb | ||
139 | + => setenv bootargs root=/dev/mmcblk3p1 | ||
140 | + => bootz 12000000 - 14000000 | ||
141 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
47 | index XXXXXXX..XXXXXXX 100644 | 142 | index XXXXXXX..XXXXXXX 100644 |
48 | --- a/include/hw/arm/boot.h | 143 | --- a/docs/system/target-arm.rst |
49 | +++ b/include/hw/arm/boot.h | 144 | +++ b/docs/system/target-arm.rst |
50 | @@ -XXX,XX +XXX,XX @@ struct arm_boot_info { | 145 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running |
51 | void (*write_board_setup)(ARMCPU *cpu, | 146 | arm/versatile |
52 | const struct arm_boot_info *info); | 147 | arm/vexpress |
53 | 148 | arm/aspeed | |
54 | - /* If set, the board specific loader/setup blob will be run from secure | 149 | + arm/sabrelite |
55 | + /* | 150 | arm/digic |
56 | + * If set, the board specific loader/setup blob will be run from secure | 151 | arm/musicpal |
57 | * mode, regardless of secure_boot. The blob becomes responsible for | 152 | arm/gumstix |
58 | - * changing to non-secure state if implementing a non-secure boot | ||
59 | + * changing to non-secure state if implementing a non-secure boot, | ||
60 | + * including setting up EL3/Secure registers such as the NSACR as | ||
61 | + * required by the Linux booting ABI before the switch to non-secure. | ||
62 | */ | ||
63 | bool secure_board_setup; | ||
64 | |||
65 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | ||
66 | index XXXXXXX..XXXXXXX 100644 | ||
67 | --- a/hw/arm/boot.c | ||
68 | +++ b/hw/arm/boot.c | ||
69 | @@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, | ||
70 | }; | ||
71 | uint32_t board_setup_blob[] = { | ||
72 | /* board setup addr */ | ||
73 | + 0xee110f51, /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */ | ||
74 | + 0xe3800b03, /* orr r0, #0xc00 ;set CP11, CP10 */ | ||
75 | + 0xee010f51, /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */ | ||
76 | 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ | ||
77 | 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ | ||
78 | 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ | ||
79 | -- | 153 | -- |
80 | 2.20.1 | 154 | 2.20.1 |
81 | 155 | ||
82 | 156 | diff view generated by jsdifflib |