[PULL 00/11] target-arm queue
[PULL 0/5] target-arm queue
1
target-arm queue: two bug fixes, plus the KVM/SVE patchset,
1
Hi; here's a collection of Arm bug fixes for rc2.
2
which is a new feature but one which was in my pre-softfreeze
3
pullreq (it just had to be dropped due to an unexpected test failure.)
4
2
5
thanks
3
thanks
6
-- PMM
4
-- PMM
7
5
8
The following changes since commit b7c9a7f353c0e260519bf735ff0d4aa01e72784b:
6
The following changes since commit a082fab9d259473a9d5d53307cf83b1223301181:
9
7
10
Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging (2019-10-31 15:57:30 +0000)
8
Merge tag 'pull-ppc-20221117' of https://gitlab.com/danielhb/qemu into staging (2022-11-17 12:39:38 -0500)
11
9
12
are available in the Git repository at:
10
are available in the Git repository at:
13
11
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191101-1
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221121
15
13
16
for you to fetch changes up to d9ae7624b659362cb2bb2b04fee53bf50829ca56:
14
for you to fetch changes up to 312b71abce3005ca7294dc0db7d548dc7cc41fbf:
17
15
18
target/arm: Allow reading flags from FPSCR for M-profile (2019-11-01 08:49:10 +0000)
16
target/arm: Limit LPA2 effective output address when TCR.DS == 0 (2022-11-21 11:46:46 +0000)
19
17
20
----------------------------------------------------------------
18
----------------------------------------------------------------
21
target-arm queue:
19
target-arm queue:
22
* Support SVE in KVM guests
20
* hw/sd: Fix sun4i allwinner-sdhost for U-Boot
23
* Don't UNDEF on M-profile 'vmrs apsr_nzcv, fpscr'
21
* hw/intc: add implementation of GICD_IIDR to Arm GIC
24
* Update hflags after boot.c modifies CPU state
22
* tests/avocado/boot_linux.py: Bump aarch64 virt test timeout
23
* target/arm: Limit LPA2 effective output address when TCR.DS == 0
25
24
26
----------------------------------------------------------------
25
----------------------------------------------------------------
27
Andrew Jones (9):
26
Alex Bennée (2):
28
target/arm/monitor: Introduce qmp_query_cpu_model_expansion
27
hw/intc: clean-up access to GIC multi-byte registers
29
tests: arm: Introduce cpu feature tests
28
hw/intc: add implementation of GICD_IIDR to Arm GIC
30
target/arm: Allow SVE to be disabled via a CPU property
31
target/arm/cpu64: max cpu: Introduce sve<N> properties
32
target/arm/kvm64: Add kvm_arch_get/put_sve
33
target/arm/kvm64: max cpu: Enable SVE when available
34
target/arm/kvm: scratch vcpu: Preserve input kvm_vcpu_init features
35
target/arm/cpu64: max cpu: Support sve properties with KVM
36
target/arm/kvm: host cpu: Add support for sve<N> properties
37
29
38
Christophe Lyon (1):
30
Ard Biesheuvel (1):
39
target/arm: Allow reading flags from FPSCR for M-profile
31
target/arm: Limit LPA2 effective output address when TCR.DS == 0
40
32
41
Edgar E. Iglesias (1):
33
Peter Maydell (1):
42
hw/arm/boot: Rebuild hflags when modifying CPUState at boot
34
tests/avocado/boot_linux.py: Bump aarch64 virt test timeout to 720s
43
35
44
tests/Makefile.include | 5 +-
36
Strahinja Jankovic (1):
45
qapi/machine-target.json | 6 +-
37
hw/sd: Fix sun4i allwinner-sdhost for U-Boot
46
include/qemu/bitops.h | 1 +
47
target/arm/cpu.h | 21 ++
48
target/arm/kvm_arm.h | 39 +++
49
hw/arm/boot.c | 1 +
50
target/arm/cpu.c | 25 +-
51
target/arm/cpu64.c | 364 +++++++++++++++++++++++++--
52
target/arm/helper.c | 10 +-
53
target/arm/kvm.c | 25 +-
54
target/arm/kvm32.c | 6 +-
55
target/arm/kvm64.c | 325 +++++++++++++++++++++---
56
target/arm/monitor.c | 158 ++++++++++++
57
target/arm/translate-vfp.inc.c | 5 +-
58
tests/arm-cpu-features.c | 551 +++++++++++++++++++++++++++++++++++++++++
59
docs/arm-cpu-features.rst | 317 ++++++++++++++++++++++++
60
16 files changed, 1795 insertions(+), 64 deletions(-)
61
create mode 100644 tests/arm-cpu-features.c
62
create mode 100644 docs/arm-cpu-features.rst
63
38
39
include/hw/sd/allwinner-sdhost.h | 1 +
40
hw/intc/arm_gic.c | 28 ++++++++++++-----
41
hw/sd/allwinner-sdhost.c | 67 +++++++++++++++++++++++++++-------------
42
target/arm/ptw.c | 8 +++++
43
tests/avocado/boot_linux.py | 2 +-
44
5 files changed, 77 insertions(+), 29 deletions(-)
45
diff view generated by jsdifflib
[PULL 01/11] target/arm/monitor: Introduce qmp_query_cpu_model_expansion
Deleted patch
1
From: Andrew Jones <drjones@redhat.com>
2
1
3
Add support for the query-cpu-model-expansion QMP command to Arm. We
4
do this selectively, only exposing CPU properties which represent
5
optional CPU features which the user may want to enable/disable.
6
Additionally we restrict the list of queryable cpu models to 'max',
7
'host', or the current type when KVM is in use. And, finally, we only
8
implement expansion type 'full', as Arm does not yet have a "base"
9
CPU type. More details and example queries are described in a new
10
document (docs/arm-cpu-features.rst).
11
12
Note, certainly more features may be added to the list of advertised
13
features, e.g. 'vfp' and 'neon'. The only requirement is that we can
14
detect invalid configurations and emit failures at QMP query time.
15
For 'vfp' and 'neon' this will require some refactoring to share a
16
validation function between the QMP query and the CPU realize
17
functions.
18
19
Signed-off-by: Andrew Jones <drjones@redhat.com>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Reviewed-by: Eric Auger <eric.auger@redhat.com>
22
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
23
Message-id: 20191031142734.8590-2-drjones@redhat.com
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
---
26
qapi/machine-target.json | 6 +-
27
target/arm/monitor.c | 146 ++++++++++++++++++++++++++++++++++++++
28
docs/arm-cpu-features.rst | 137 +++++++++++++++++++++++++++++++++++
29
3 files changed, 286 insertions(+), 3 deletions(-)
30
create mode 100644 docs/arm-cpu-features.rst
31
32
diff --git a/qapi/machine-target.json b/qapi/machine-target.json
33
index XXXXXXX..XXXXXXX 100644
34
--- a/qapi/machine-target.json
35
+++ b/qapi/machine-target.json
36
@@ -XXX,XX +XXX,XX @@
37
##
38
{ 'struct': 'CpuModelExpansionInfo',
39
'data': { 'model': 'CpuModelInfo' },
40
- 'if': 'defined(TARGET_S390X) || defined(TARGET_I386)' }
41
+ 'if': 'defined(TARGET_S390X) || defined(TARGET_I386) || defined(TARGET_ARM)' }
42
43
##
44
# @query-cpu-model-expansion:
45
@@ -XXX,XX +XXX,XX @@
46
# query-cpu-model-expansion while using these is not advised.
47
#
48
# Some architectures may not support all expansion types. s390x supports
49
-# "full" and "static".
50
+# "full" and "static". Arm only supports "full".
51
#
52
# Returns: a CpuModelExpansionInfo. Returns an error if expanding CPU models is
53
# not supported, if the model cannot be expanded, if the model contains
54
@@ -XXX,XX +XXX,XX @@
55
'data': { 'type': 'CpuModelExpansionType',
56
'model': 'CpuModelInfo' },
57
'returns': 'CpuModelExpansionInfo',
58
- 'if': 'defined(TARGET_S390X) || defined(TARGET_I386)' }
59
+ 'if': 'defined(TARGET_S390X) || defined(TARGET_I386) || defined(TARGET_ARM)' }
60
61
##
62
# @CpuDefinitionInfo:
63
diff --git a/target/arm/monitor.c b/target/arm/monitor.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/monitor.c
66
+++ b/target/arm/monitor.c
67
@@ -XXX,XX +XXX,XX @@
68
*/
69
70
#include "qemu/osdep.h"
71
+#include "hw/boards.h"
72
#include "kvm_arm.h"
73
+#include "qapi/error.h"
74
+#include "qapi/visitor.h"
75
+#include "qapi/qobject-input-visitor.h"
76
+#include "qapi/qapi-commands-machine-target.h"
77
#include "qapi/qapi-commands-misc-target.h"
78
+#include "qapi/qmp/qerror.h"
79
+#include "qapi/qmp/qdict.h"
80
+#include "qom/qom-qobject.h"
81
82
static GICCapability *gic_cap_new(int version)
83
{
84
@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
85
86
return head;
87
}
88
+
89
+/*
90
+ * These are cpu model features we want to advertise. The order here
91
+ * matters as this is the order in which qmp_query_cpu_model_expansion
92
+ * will attempt to set them. If there are dependencies between features,
93
+ * then the order that considers those dependencies must be used.
94
+ */
95
+static const char *cpu_model_advertised_features[] = {
96
+ "aarch64", "pmu",
97
+ NULL
98
+};
99
+
100
+CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
101
+ CpuModelInfo *model,
102
+ Error **errp)
103
+{
104
+ CpuModelExpansionInfo *expansion_info;
105
+ const QDict *qdict_in = NULL;
106
+ QDict *qdict_out;
107
+ ObjectClass *oc;
108
+ Object *obj;
109
+ const char *name;
110
+ int i;
111
+
112
+ if (type != CPU_MODEL_EXPANSION_TYPE_FULL) {
113
+ error_setg(errp, "The requested expansion type is not supported");
114
+ return NULL;
115
+ }
116
+
117
+ if (!kvm_enabled() && !strcmp(model->name, "host")) {
118
+ error_setg(errp, "The CPU type '%s' requires KVM", model->name);
119
+ return NULL;
120
+ }
121
+
122
+ oc = cpu_class_by_name(TYPE_ARM_CPU, model->name);
123
+ if (!oc) {
124
+ error_setg(errp, "The CPU type '%s' is not a recognized ARM CPU type",
125
+ model->name);
126
+ return NULL;
127
+ }
128
+
129
+ if (kvm_enabled()) {
130
+ const char *cpu_type = current_machine->cpu_type;
131
+ int len = strlen(cpu_type) - strlen(ARM_CPU_TYPE_SUFFIX);
132
+ bool supported = false;
133
+
134
+ if (!strcmp(model->name, "host") || !strcmp(model->name, "max")) {
135
+ /* These are kvmarm's recommended cpu types */
136
+ supported = true;
137
+ } else if (strlen(model->name) == len &&
138
+ !strncmp(model->name, cpu_type, len)) {
139
+ /* KVM is enabled and we're using this type, so it works. */
140
+ supported = true;
141
+ }
142
+ if (!supported) {
143
+ error_setg(errp, "We cannot guarantee the CPU type '%s' works "
144
+ "with KVM on this host", model->name);
145
+ return NULL;
146
+ }
147
+ }
148
+
149
+ if (model->props) {
150
+ qdict_in = qobject_to(QDict, model->props);
151
+ if (!qdict_in) {
152
+ error_setg(errp, QERR_INVALID_PARAMETER_TYPE, "props", "dict");
153
+ return NULL;
154
+ }
155
+ }
156
+
157
+ obj = object_new(object_class_get_name(oc));
158
+
159
+ if (qdict_in) {
160
+ Visitor *visitor;
161
+ Error *err = NULL;
162
+
163
+ visitor = qobject_input_visitor_new(model->props);
164
+ visit_start_struct(visitor, NULL, NULL, 0, &err);
165
+ if (err) {
166
+ visit_free(visitor);
167
+ object_unref(obj);
168
+ error_propagate(errp, err);
169
+ return NULL;
170
+ }
171
+
172
+ i = 0;
173
+ while ((name = cpu_model_advertised_features[i++]) != NULL) {
174
+ if (qdict_get(qdict_in, name)) {
175
+ object_property_set(obj, visitor, name, &err);
176
+ if (err) {
177
+ break;
178
+ }
179
+ }
180
+ }
181
+
182
+ if (!err) {
183
+ visit_check_struct(visitor, &err);
184
+ }
185
+ visit_end_struct(visitor, NULL);
186
+ visit_free(visitor);
187
+ if (err) {
188
+ object_unref(obj);
189
+ error_propagate(errp, err);
190
+ return NULL;
191
+ }
192
+ }
193
+
194
+ expansion_info = g_new0(CpuModelExpansionInfo, 1);
195
+ expansion_info->model = g_malloc0(sizeof(*expansion_info->model));
196
+ expansion_info->model->name = g_strdup(model->name);
197
+
198
+ qdict_out = qdict_new();
199
+
200
+ i = 0;
201
+ while ((name = cpu_model_advertised_features[i++]) != NULL) {
202
+ ObjectProperty *prop = object_property_find(obj, name, NULL);
203
+ if (prop) {
204
+ Error *err = NULL;
205
+ QObject *value;
206
+
207
+ assert(prop->get);
208
+ value = object_property_get_qobject(obj, name, &err);
209
+ assert(!err);
210
+
211
+ qdict_put_obj(qdict_out, name, value);
212
+ }
213
+ }
214
+
215
+ if (!qdict_size(qdict_out)) {
216
+ qobject_unref(qdict_out);
217
+ } else {
218
+ expansion_info->model->props = QOBJECT(qdict_out);
219
+ expansion_info->model->has_props = true;
220
+ }
221
+
222
+ object_unref(obj);
223
+
224
+ return expansion_info;
225
+}
226
diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
227
new file mode 100644
228
index XXXXXXX..XXXXXXX
229
--- /dev/null
230
+++ b/docs/arm-cpu-features.rst
231
@@ -XXX,XX +XXX,XX @@
232
+================
233
+ARM CPU Features
234
+================
235
+
236
+Examples of probing and using ARM CPU features
237
+
238
+Introduction
239
+============
240
+
241
+CPU features are optional features that a CPU of supporting type may
242
+choose to implement or not. In QEMU, optional CPU features have
243
+corresponding boolean CPU proprieties that, when enabled, indicate
244
+that the feature is implemented, and, conversely, when disabled,
245
+indicate that it is not implemented. An example of an ARM CPU feature
246
+is the Performance Monitoring Unit (PMU). CPU types such as the
247
+Cortex-A15 and the Cortex-A57, which respectively implement ARM
248
+architecture reference manuals ARMv7-A and ARMv8-A, may both optionally
249
+implement PMUs. For example, if a user wants to use a Cortex-A15 without
250
+a PMU, then the `-cpu` parameter should contain `pmu=off` on the QEMU
251
+command line, i.e. `-cpu cortex-a15,pmu=off`.
252
+
253
+As not all CPU types support all optional CPU features, then whether or
254
+not a CPU property exists depends on the CPU type. For example, CPUs
255
+that implement the ARMv8-A architecture reference manual may optionally
256
+support the AArch32 CPU feature, which may be enabled by disabling the
257
+`aarch64` CPU property. A CPU type such as the Cortex-A15, which does
258
+not implement ARMv8-A, will not have the `aarch64` CPU property.
259
+
260
+QEMU's support may be limited for some CPU features, only partially
261
+supporting the feature or only supporting the feature under certain
262
+configurations. For example, the `aarch64` CPU feature, which, when
263
+disabled, enables the optional AArch32 CPU feature, is only supported
264
+when using the KVM accelerator and when running on a host CPU type that
265
+supports the feature.
266
+
267
+CPU Feature Probing
268
+===================
269
+
270
+Determining which CPU features are available and functional for a given
271
+CPU type is possible with the `query-cpu-model-expansion` QMP command.
272
+Below are some examples where `scripts/qmp/qmp-shell` (see the top comment
273
+block in the script for usage) is used to issue the QMP commands.
274
+
275
+(1) Determine which CPU features are available for the `max` CPU type
276
+ (Note, we started QEMU with qemu-system-aarch64, so `max` is
277
+ implementing the ARMv8-A reference manual in this case)::
278
+
279
+ (QEMU) query-cpu-model-expansion type=full model={"name":"max"}
280
+ { "return": {
281
+ "model": { "name": "max", "props": {
282
+ "pmu": true, "aarch64": true
283
+ }}}}
284
+
285
+We see that the `max` CPU type has the `pmu` and `aarch64` CPU features.
286
+We also see that the CPU features are enabled, as they are all `true`.
287
+
288
+(2) Let's try to disable the PMU::
289
+
290
+ (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"pmu":false}}
291
+ { "return": {
292
+ "model": { "name": "max", "props": {
293
+ "pmu": false, "aarch64": true
294
+ }}}}
295
+
296
+We see it worked, as `pmu` is now `false`.
297
+
298
+(3) Let's try to disable `aarch64`, which enables the AArch32 CPU feature::
299
+
300
+ (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"aarch64":false}}
301
+ {"error": {
302
+ "class": "GenericError", "desc":
303
+ "'aarch64' feature cannot be disabled unless KVM is enabled and 32-bit EL1 is supported"
304
+ }}
305
+
306
+It looks like this feature is limited to a configuration we do not
307
+currently have.
308
+
309
+(4) Let's try probing CPU features for the Cortex-A15 CPU type::
310
+
311
+ (QEMU) query-cpu-model-expansion type=full model={"name":"cortex-a15"}
312
+ {"return": {"model": {"name": "cortex-a15", "props": {"pmu": true}}}}
313
+
314
+Only the `pmu` CPU feature is available.
315
+
316
+A note about CPU feature dependencies
317
+-------------------------------------
318
+
319
+It's possible for features to have dependencies on other features. I.e.
320
+it may be possible to change one feature at a time without error, but
321
+when attempting to change all features at once an error could occur
322
+depending on the order they are processed. It's also possible changing
323
+all at once doesn't generate an error, because a feature's dependencies
324
+are satisfied with other features, but the same feature cannot be changed
325
+independently without error. For these reasons callers should always
326
+attempt to make their desired changes all at once in order to ensure the
327
+collection is valid.
328
+
329
+A note about CPU models and KVM
330
+-------------------------------
331
+
332
+Named CPU models generally do not work with KVM. There are a few cases
333
+that do work, e.g. using the named CPU model `cortex-a57` with KVM on a
334
+seattle host, but mostly if KVM is enabled the `host` CPU type must be
335
+used. This means the guest is provided all the same CPU features as the
336
+host CPU type has. And, for this reason, the `host` CPU type should
337
+enable all CPU features that the host has by default. Indeed it's even
338
+a bit strange to allow disabling CPU features that the host has when using
339
+the `host` CPU type, but in the absence of CPU models it's the best we can
340
+do if we want to launch guests without all the host's CPU features enabled.
341
+
342
+Enabling KVM also affects the `query-cpu-model-expansion` QMP command. The
343
+affect is not only limited to specific features, as pointed out in example
344
+(3) of "CPU Feature Probing", but also to which CPU types may be expanded.
345
+When KVM is enabled, only the `max`, `host`, and current CPU type may be
346
+expanded. This restriction is necessary as it's not possible to know all
347
+CPU types that may work with KVM, but it does impose a small risk of users
348
+experiencing unexpected errors. For example on a seattle, as mentioned
349
+above, the `cortex-a57` CPU type is also valid when KVM is enabled.
350
+Therefore a user could use the `host` CPU type for the current type, but
351
+then attempt to query `cortex-a57`, however that query will fail with our
352
+restrictions. This shouldn't be an issue though as management layers and
353
+users have been preferring the `host` CPU type for use with KVM for quite
354
+some time. Additionally, if the KVM-enabled QEMU instance running on a
355
+seattle host is using the `cortex-a57` CPU type, then querying `cortex-a57`
356
+will work.
357
+
358
+Using CPU Features
359
+==================
360
+
361
+After determining which CPU features are available and supported for a
362
+given CPU type, then they may be selectively enabled or disabled on the
363
+QEMU command line with that CPU type::
364
+
365
+ $ qemu-system-aarch64 -M virt -cpu max,pmu=off
366
+
367
+The example above disables the PMU for the `max` CPU type.
368
+
369
--
370
2.20.1
371
372
diff view generated by jsdifflib
[PULL 02/11] tests: arm: Introduce cpu feature tests
Deleted patch
1
From: Andrew Jones <drjones@redhat.com>
2
1
3
Now that Arm CPUs have advertised features lets add tests to ensure
4
we maintain their expected availability with and without KVM.
5
6
Signed-off-by: Andrew Jones <drjones@redhat.com>
7
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Message-id: 20191031142734.8590-3-drjones@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
tests/Makefile.include | 5 +-
12
tests/arm-cpu-features.c | 253 +++++++++++++++++++++++++++++++++++++++
13
2 files changed, 257 insertions(+), 1 deletion(-)
14
create mode 100644 tests/arm-cpu-features.c
15
16
diff --git a/tests/Makefile.include b/tests/Makefile.include
17
index XXXXXXX..XXXXXXX 100644
18
--- a/tests/Makefile.include
19
+++ b/tests/Makefile.include
20
@@ -XXX,XX +XXX,XX @@ check-qtest-sparc64-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF)
21
check-qtest-sparc64-y += tests/prom-env-test$(EXESUF)
22
check-qtest-sparc64-y += tests/boot-serial-test$(EXESUF)
23
24
+check-qtest-arm-y += tests/arm-cpu-features$(EXESUF)
25
check-qtest-arm-y += tests/microbit-test$(EXESUF)
26
check-qtest-arm-y += tests/m25p80-test$(EXESUF)
27
check-qtest-arm-y += tests/test-arm-mptimer$(EXESUF)
28
@@ -XXX,XX +XXX,XX @@ check-qtest-arm-y += tests/boot-serial-test$(EXESUF)
29
check-qtest-arm-y += tests/hexloader-test$(EXESUF)
30
check-qtest-arm-$(CONFIG_PFLASH_CFI02) += tests/pflash-cfi02-test$(EXESUF)
31
32
-check-qtest-aarch64-y = tests/numa-test$(EXESUF)
33
+check-qtest-aarch64-y += tests/arm-cpu-features$(EXESUF)
34
+check-qtest-aarch64-y += tests/numa-test$(EXESUF)
35
check-qtest-aarch64-y += tests/boot-serial-test$(EXESUF)
36
check-qtest-aarch64-y += tests/migration-test$(EXESUF)
37
# TODO: once aarch64 TCG is fixed on ARM 32 bit host, make test unconditional
38
@@ -XXX,XX +XXX,XX @@ tests/test-qapi-util$(EXESUF): tests/test-qapi-util.o $(test-util-obj-y)
39
tests/numa-test$(EXESUF): tests/numa-test.o
40
tests/vmgenid-test$(EXESUF): tests/vmgenid-test.o tests/boot-sector.o tests/acpi-utils.o
41
tests/cdrom-test$(EXESUF): tests/cdrom-test.o tests/boot-sector.o $(libqos-obj-y)
42
+tests/arm-cpu-features$(EXESUF): tests/arm-cpu-features.o
43
44
tests/migration/stress$(EXESUF): tests/migration/stress.o
45
    $(call quiet-command, $(LINKPROG) -static -O3 $(PTHREAD_LIB) -o $@ $< ,"LINK","$(TARGET_DIR)$@")
46
diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
47
new file mode 100644
48
index XXXXXXX..XXXXXXX
49
--- /dev/null
50
+++ b/tests/arm-cpu-features.c
51
@@ -XXX,XX +XXX,XX @@
52
+/*
53
+ * Arm CPU feature test cases
54
+ *
55
+ * Copyright (c) 2019 Red Hat Inc.
56
+ * Authors:
57
+ * Andrew Jones <drjones@redhat.com>
58
+ *
59
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
60
+ * See the COPYING file in the top-level directory.
61
+ */
62
+#include "qemu/osdep.h"
63
+#include "libqtest.h"
64
+#include "qapi/qmp/qdict.h"
65
+#include "qapi/qmp/qjson.h"
66
+
67
+#define MACHINE "-machine virt,gic-version=max,accel=tcg "
68
+#define MACHINE_KVM "-machine virt,gic-version=max,accel=kvm:tcg "
69
+#define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \
70
+ " 'arguments': { 'type': 'full', "
71
+#define QUERY_TAIL "}}"
72
+
73
+static bool kvm_enabled(QTestState *qts)
74
+{
75
+ QDict *resp, *qdict;
76
+ bool enabled;
77
+
78
+ resp = qtest_qmp(qts, "{ 'execute': 'query-kvm' }");
79
+ g_assert(qdict_haskey(resp, "return"));
80
+ qdict = qdict_get_qdict(resp, "return");
81
+ g_assert(qdict_haskey(qdict, "enabled"));
82
+ enabled = qdict_get_bool(qdict, "enabled");
83
+ qobject_unref(resp);
84
+
85
+ return enabled;
86
+}
87
+
88
+static QDict *do_query_no_props(QTestState *qts, const char *cpu_type)
89
+{
90
+ return qtest_qmp(qts, QUERY_HEAD "'model': { 'name': %s }"
91
+ QUERY_TAIL, cpu_type);
92
+}
93
+
94
+static QDict *do_query(QTestState *qts, const char *cpu_type,
95
+ const char *fmt, ...)
96
+{
97
+ QDict *resp;
98
+
99
+ if (fmt) {
100
+ QDict *args;
101
+ va_list ap;
102
+
103
+ va_start(ap, fmt);
104
+ args = qdict_from_vjsonf_nofail(fmt, ap);
105
+ va_end(ap);
106
+
107
+ resp = qtest_qmp(qts, QUERY_HEAD "'model': { 'name': %s, "
108
+ "'props': %p }"
109
+ QUERY_TAIL, cpu_type, args);
110
+ } else {
111
+ resp = do_query_no_props(qts, cpu_type);
112
+ }
113
+
114
+ return resp;
115
+}
116
+
117
+static const char *resp_get_error(QDict *resp)
118
+{
119
+ QDict *qdict;
120
+
121
+ g_assert(resp);
122
+
123
+ qdict = qdict_get_qdict(resp, "error");
124
+ if (qdict) {
125
+ return qdict_get_str(qdict, "desc");
126
+ }
127
+
128
+ return NULL;
129
+}
130
+
131
+#define assert_error(qts, cpu_type, expected_error, fmt, ...) \
132
+({ \
133
+ QDict *_resp; \
134
+ const char *_error; \
135
+ \
136
+ _resp = do_query(qts, cpu_type, fmt, ##__VA_ARGS__); \
137
+ g_assert(_resp); \
138
+ _error = resp_get_error(_resp); \
139
+ g_assert(_error); \
140
+ g_assert(g_str_equal(_error, expected_error)); \
141
+ qobject_unref(_resp); \
142
+})
143
+
144
+static bool resp_has_props(QDict *resp)
145
+{
146
+ QDict *qdict;
147
+
148
+ g_assert(resp);
149
+
150
+ if (!qdict_haskey(resp, "return")) {
151
+ return false;
152
+ }
153
+ qdict = qdict_get_qdict(resp, "return");
154
+
155
+ if (!qdict_haskey(qdict, "model")) {
156
+ return false;
157
+ }
158
+ qdict = qdict_get_qdict(qdict, "model");
159
+
160
+ return qdict_haskey(qdict, "props");
161
+}
162
+
163
+static QDict *resp_get_props(QDict *resp)
164
+{
165
+ QDict *qdict;
166
+
167
+ g_assert(resp);
168
+ g_assert(resp_has_props(resp));
169
+
170
+ qdict = qdict_get_qdict(resp, "return");
171
+ qdict = qdict_get_qdict(qdict, "model");
172
+ qdict = qdict_get_qdict(qdict, "props");
173
+
174
+ return qdict;
175
+}
176
+
177
+#define assert_has_feature(qts, cpu_type, feature) \
178
+({ \
179
+ QDict *_resp = do_query_no_props(qts, cpu_type); \
180
+ g_assert(_resp); \
181
+ g_assert(resp_has_props(_resp)); \
182
+ g_assert(qdict_get(resp_get_props(_resp), feature)); \
183
+ qobject_unref(_resp); \
184
+})
185
+
186
+#define assert_has_not_feature(qts, cpu_type, feature) \
187
+({ \
188
+ QDict *_resp = do_query_no_props(qts, cpu_type); \
189
+ g_assert(_resp); \
190
+ g_assert(!resp_has_props(_resp) || \
191
+ !qdict_get(resp_get_props(_resp), feature)); \
192
+ qobject_unref(_resp); \
193
+})
194
+
195
+static void assert_type_full(QTestState *qts)
196
+{
197
+ const char *error;
198
+ QDict *resp;
199
+
200
+ resp = qtest_qmp(qts, "{ 'execute': 'query-cpu-model-expansion', "
201
+ "'arguments': { 'type': 'static', "
202
+ "'model': { 'name': 'foo' }}}");
203
+ g_assert(resp);
204
+ error = resp_get_error(resp);
205
+ g_assert(error);
206
+ g_assert(g_str_equal(error,
207
+ "The requested expansion type is not supported"));
208
+ qobject_unref(resp);
209
+}
210
+
211
+static void assert_bad_props(QTestState *qts, const char *cpu_type)
212
+{
213
+ const char *error;
214
+ QDict *resp;
215
+
216
+ resp = qtest_qmp(qts, "{ 'execute': 'query-cpu-model-expansion', "
217
+ "'arguments': { 'type': 'full', "
218
+ "'model': { 'name': %s, "
219
+ "'props': false }}}",
220
+ cpu_type);
221
+ g_assert(resp);
222
+ error = resp_get_error(resp);
223
+ g_assert(error);
224
+ g_assert(g_str_equal(error,
225
+ "Invalid parameter type for 'props', expected: dict"));
226
+ qobject_unref(resp);
227
+}
228
+
229
+static void test_query_cpu_model_expansion(const void *data)
230
+{
231
+ QTestState *qts;
232
+
233
+ qts = qtest_init(MACHINE "-cpu max");
234
+
235
+ /* Test common query-cpu-model-expansion input validation */
236
+ assert_type_full(qts);
237
+ assert_bad_props(qts, "max");
238
+ assert_error(qts, "foo", "The CPU type 'foo' is not a recognized "
239
+ "ARM CPU type", NULL);
240
+ assert_error(qts, "max", "Parameter 'not-a-prop' is unexpected",
241
+ "{ 'not-a-prop': false }");
242
+ assert_error(qts, "host", "The CPU type 'host' requires KVM", NULL);
243
+
244
+ /* Test expected feature presence/absence for some cpu types */
245
+ assert_has_feature(qts, "max", "pmu");
246
+ assert_has_feature(qts, "cortex-a15", "pmu");
247
+ assert_has_not_feature(qts, "cortex-a15", "aarch64");
248
+
249
+ if (g_str_equal(qtest_get_arch(), "aarch64")) {
250
+ assert_has_feature(qts, "max", "aarch64");
251
+ assert_has_feature(qts, "cortex-a57", "pmu");
252
+ assert_has_feature(qts, "cortex-a57", "aarch64");
253
+
254
+ /* Test that features that depend on KVM generate errors without. */
255
+ assert_error(qts, "max",
256
+ "'aarch64' feature cannot be disabled "
257
+ "unless KVM is enabled and 32-bit EL1 "
258
+ "is supported",
259
+ "{ 'aarch64': false }");
260
+ }
261
+
262
+ qtest_quit(qts);
263
+}
264
+
265
+static void test_query_cpu_model_expansion_kvm(const void *data)
266
+{
267
+ QTestState *qts;
268
+
269
+ qts = qtest_init(MACHINE_KVM "-cpu max");
270
+
271
+ /*
272
+ * These tests target the 'host' CPU type, so KVM must be enabled.
273
+ */
274
+ if (!kvm_enabled(qts)) {
275
+ qtest_quit(qts);
276
+ return;
277
+ }
278
+
279
+ if (g_str_equal(qtest_get_arch(), "aarch64")) {
280
+ assert_has_feature(qts, "host", "aarch64");
281
+ assert_has_feature(qts, "host", "pmu");
282
+
283
+ assert_error(qts, "cortex-a15",
284
+ "We cannot guarantee the CPU type 'cortex-a15' works "
285
+ "with KVM on this host", NULL);
286
+ } else {
287
+ assert_has_not_feature(qts, "host", "aarch64");
288
+ assert_has_not_feature(qts, "host", "pmu");
289
+ }
290
+
291
+ qtest_quit(qts);
292
+}
293
+
294
+int main(int argc, char **argv)
295
+{
296
+ g_test_init(&argc, &argv, NULL);
297
+
298
+ qtest_add_data_func("/arm/query-cpu-model-expansion",
299
+ NULL, test_query_cpu_model_expansion);
300
+ qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
301
+ NULL, test_query_cpu_model_expansion_kvm);
302
+
303
+ return g_test_run();
304
+}
305
--
306
2.20.1
307
308
diff view generated by jsdifflib
[PULL 03/11] target/arm: Allow SVE to be disabled via a CPU property
Deleted patch
1
From: Andrew Jones <drjones@redhat.com>
2
1
3
Since 97a28b0eeac14 ("target/arm: Allow VFP and Neon to be disabled via
4
a CPU property") we can disable the 'max' cpu model's VFP and neon
5
features, but there's no way to disable SVE. Add the 'sve=on|off'
6
property to give it that flexibility. We also rename
7
cpu_max_get/set_sve_vq to cpu_max_get/set_sve_max_vq in order for them
8
to follow the typical *_get/set_<property-name> pattern.
9
10
Signed-off-by: Andrew Jones <drjones@redhat.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Eric Auger <eric.auger@redhat.com>
13
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
14
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
15
Message-id: 20191031142734.8590-4-drjones@redhat.com
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
target/arm/cpu.c | 3 ++-
19
target/arm/cpu64.c | 52 ++++++++++++++++++++++++++++++++++------
20
target/arm/monitor.c | 2 +-
21
tests/arm-cpu-features.c | 1 +
22
4 files changed, 49 insertions(+), 9 deletions(-)
23
24
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/cpu.c
27
+++ b/target/arm/cpu.c
28
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
29
env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
30
env->cp15.cptr_el[3] |= CPTR_EZ;
31
/* with maximum vector length */
32
- env->vfp.zcr_el[1] = cpu->sve_max_vq - 1;
33
+ env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ?
34
+ cpu->sve_max_vq - 1 : 0;
35
env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
36
env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
37
/*
38
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/cpu64.c
41
+++ b/target/arm/cpu64.c
42
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
43
define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
44
}
45
46
-static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
47
- void *opaque, Error **errp)
48
+static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
49
+ void *opaque, Error **errp)
50
{
51
ARMCPU *cpu = ARM_CPU(obj);
52
- visit_type_uint32(v, name, &cpu->sve_max_vq, errp);
53
+ uint32_t value;
54
+
55
+ /* All vector lengths are disabled when SVE is off. */
56
+ if (!cpu_isar_feature(aa64_sve, cpu)) {
57
+ value = 0;
58
+ } else {
59
+ value = cpu->sve_max_vq;
60
+ }
61
+ visit_type_uint32(v, name, &value, errp);
62
}
63
64
-static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
65
- void *opaque, Error **errp)
66
+static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
67
+ void *opaque, Error **errp)
68
{
69
ARMCPU *cpu = ARM_CPU(obj);
70
Error *err = NULL;
71
@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
72
error_propagate(errp, err);
73
}
74
75
+static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name,
76
+ void *opaque, Error **errp)
77
+{
78
+ ARMCPU *cpu = ARM_CPU(obj);
79
+ bool value = cpu_isar_feature(aa64_sve, cpu);
80
+
81
+ visit_type_bool(v, name, &value, errp);
82
+}
83
+
84
+static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
85
+ void *opaque, Error **errp)
86
+{
87
+ ARMCPU *cpu = ARM_CPU(obj);
88
+ Error *err = NULL;
89
+ bool value;
90
+ uint64_t t;
91
+
92
+ visit_type_bool(v, name, &value, &err);
93
+ if (err) {
94
+ error_propagate(errp, err);
95
+ return;
96
+ }
97
+
98
+ t = cpu->isar.id_aa64pfr0;
99
+ t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);
100
+ cpu->isar.id_aa64pfr0 = t;
101
+}
102
+
103
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
104
* otherwise, a CPU with as many features enabled as our emulation supports.
105
* The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
106
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
107
#endif
108
109
cpu->sve_max_vq = ARM_MAX_VQ;
110
- object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq,
111
- cpu_max_set_sve_vq, NULL, NULL, &error_fatal);
112
+ object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
113
+ cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
114
+ object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
115
+ cpu_arm_set_sve, NULL, NULL, &error_fatal);
116
}
117
}
118
119
diff --git a/target/arm/monitor.c b/target/arm/monitor.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/target/arm/monitor.c
122
+++ b/target/arm/monitor.c
123
@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
124
* then the order that considers those dependencies must be used.
125
*/
126
static const char *cpu_model_advertised_features[] = {
127
- "aarch64", "pmu",
128
+ "aarch64", "pmu", "sve",
129
NULL
130
};
131
132
diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
133
index XXXXXXX..XXXXXXX 100644
134
--- a/tests/arm-cpu-features.c
135
+++ b/tests/arm-cpu-features.c
136
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
137
138
if (g_str_equal(qtest_get_arch(), "aarch64")) {
139
assert_has_feature(qts, "max", "aarch64");
140
+ assert_has_feature(qts, "max", "sve");
141
assert_has_feature(qts, "cortex-a57", "pmu");
142
assert_has_feature(qts, "cortex-a57", "aarch64");
143
144
--
145
2.20.1
146
147
diff view generated by jsdifflib
[PULL 04/11] target/arm/cpu64: max cpu: Introduce sve<N> properties
Deleted patch
1
From: Andrew Jones <drjones@redhat.com>
2
1
3
Introduce cpu properties to give fine control over SVE vector lengths.
4
We introduce a property for each valid length up to the current
5
maximum supported, which is 2048-bits. The properties are named, e.g.
6
sve128, sve256, sve384, sve512, ..., where the number is the number of
7
bits. See the updates to docs/arm-cpu-features.rst for a description
8
of the semantics and for example uses.
9
10
Note, as sve-max-vq is still present and we'd like to be able to
11
support qmp_query_cpu_model_expansion with guests launched with e.g.
12
-cpu max,sve-max-vq=8 on their command lines, then we do allow
13
sve-max-vq and sve<N> properties to be provided at the same time, but
14
this is not recommended, and is why sve-max-vq is not mentioned in the
15
document. If sve-max-vq is provided then it enables all lengths smaller
16
than and including the max and disables all lengths larger. It also has
17
the side-effect that no larger lengths may be enabled and that the max
18
itself cannot be disabled. Smaller non-power-of-two lengths may,
19
however, be disabled, e.g. -cpu max,sve-max-vq=4,sve384=off provides a
20
guest the vector lengths 128, 256, and 512 bits.
21
22
This patch has been co-authored with Richard Henderson, who reworked
23
the target/arm/cpu64.c changes in order to push all the validation and
24
auto-enabling/disabling steps into the finalizer, resulting in a nice
25
LOC reduction.
26
27
Signed-off-by: Andrew Jones <drjones@redhat.com>
28
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
29
Reviewed-by: Eric Auger <eric.auger@redhat.com>
30
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
31
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
32
Message-id: 20191031142734.8590-5-drjones@redhat.com
33
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
34
---
35
include/qemu/bitops.h | 1 +
36
target/arm/cpu.h | 19 ++++
37
target/arm/cpu.c | 19 ++++
38
target/arm/cpu64.c | 192 ++++++++++++++++++++++++++++++++++++-
39
target/arm/helper.c | 10 +-
40
target/arm/monitor.c | 12 +++
41
tests/arm-cpu-features.c | 194 ++++++++++++++++++++++++++++++++++++++
42
docs/arm-cpu-features.rst | 168 +++++++++++++++++++++++++++++++--
43
8 files changed, 606 insertions(+), 9 deletions(-)
44
45
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
46
index XXXXXXX..XXXXXXX 100644
47
--- a/include/qemu/bitops.h
48
+++ b/include/qemu/bitops.h
49
@@ -XXX,XX +XXX,XX @@
50
#define BITS_PER_LONG (sizeof (unsigned long) * BITS_PER_BYTE)
51
52
#define BIT(nr) (1UL << (nr))
53
+#define BIT_ULL(nr) (1ULL << (nr))
54
#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))
55
#define BIT_WORD(nr) ((nr) / BITS_PER_LONG)
56
#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
57
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/cpu.h
60
+++ b/target/arm/cpu.h
61
@@ -XXX,XX +XXX,XX @@ typedef struct {
62
63
#ifdef TARGET_AARCH64
64
# define ARM_MAX_VQ 16
65
+void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
66
+uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq);
67
#else
68
# define ARM_MAX_VQ 1
69
+static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
70
+static inline uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
71
+{ return 0; }
72
#endif
73
74
typedef struct ARMVectorReg {
75
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
76
77
/* Used to set the maximum vector length the cpu will support. */
78
uint32_t sve_max_vq;
79
+
80
+ /*
81
+ * In sve_vq_map each set bit is a supported vector length of
82
+ * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector
83
+ * length in quadwords.
84
+ *
85
+ * While processing properties during initialization, corresponding
86
+ * sve_vq_init bits are set for bits in sve_vq_map that have been
87
+ * set by properties.
88
+ */
89
+ DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ);
90
+ DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ);
91
};
92
93
void arm_cpu_post_init(Object *obj);
94
@@ -XXX,XX +XXX,XX @@ static inline int arm_feature(CPUARMState *env, int feature)
95
return (env->features & (1ULL << feature)) != 0;
96
}
97
98
+void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
99
+
100
#if !defined(CONFIG_USER_ONLY)
101
/* Return true if exception levels below EL3 are in secure state,
102
* or would be following an exception return to that level.
103
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/target/arm/cpu.c
106
+++ b/target/arm/cpu.c
107
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_finalizefn(Object *obj)
108
#endif
109
}
110
111
+void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
112
+{
113
+ Error *local_err = NULL;
114
+
115
+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
116
+ arm_cpu_sve_finalize(cpu, &local_err);
117
+ if (local_err != NULL) {
118
+ error_propagate(errp, local_err);
119
+ return;
120
+ }
121
+ }
122
+}
123
+
124
static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
125
{
126
CPUState *cs = CPU(dev);
127
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
128
return;
129
}
130
131
+ arm_cpu_finalize_features(cpu, &local_err);
132
+ if (local_err != NULL) {
133
+ error_propagate(errp, local_err);
134
+ return;
135
+ }
136
+
137
if (arm_feature(env, ARM_FEATURE_AARCH64) &&
138
cpu->has_vfp != cpu->has_neon) {
139
/*
140
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
141
index XXXXXXX..XXXXXXX 100644
142
--- a/target/arm/cpu64.c
143
+++ b/target/arm/cpu64.c
144
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
145
define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
146
}
147
148
+void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
149
+{
150
+ /*
151
+ * If any vector lengths are explicitly enabled with sve<N> properties,
152
+ * then all other lengths are implicitly disabled. If sve-max-vq is
153
+ * specified then it is the same as explicitly enabling all lengths
154
+ * up to and including the specified maximum, which means all larger
155
+ * lengths will be implicitly disabled. If no sve<N> properties
156
+ * are enabled and sve-max-vq is not specified, then all lengths not
157
+ * explicitly disabled will be enabled. Additionally, all power-of-two
158
+ * vector lengths less than the maximum enabled length will be
159
+ * automatically enabled and all vector lengths larger than the largest
160
+ * disabled power-of-two vector length will be automatically disabled.
161
+ * Errors are generated if the user provided input that interferes with
162
+ * any of the above. Finally, if SVE is not disabled, then at least one
163
+ * vector length must be enabled.
164
+ */
165
+ DECLARE_BITMAP(tmp, ARM_MAX_VQ);
166
+ uint32_t vq, max_vq = 0;
167
+
168
+ /*
169
+ * Process explicit sve<N> properties.
170
+ * From the properties, sve_vq_map<N> implies sve_vq_init<N>.
171
+ * Check first for any sve<N> enabled.
172
+ */
173
+ if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) {
174
+ max_vq = find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1;
175
+
176
+ if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) {
177
+ error_setg(errp, "cannot enable sve%d", max_vq * 128);
178
+ error_append_hint(errp, "sve%d is larger than the maximum vector "
179
+ "length, sve-max-vq=%d (%d bits)\n",
180
+ max_vq * 128, cpu->sve_max_vq,
181
+ cpu->sve_max_vq * 128);
182
+ return;
183
+ }
184
+
185
+ /* Propagate enabled bits down through required powers-of-two. */
186
+ for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
187
+ if (!test_bit(vq - 1, cpu->sve_vq_init)) {
188
+ set_bit(vq - 1, cpu->sve_vq_map);
189
+ }
190
+ }
191
+ } else if (cpu->sve_max_vq == 0) {
192
+ /*
193
+ * No explicit bits enabled, and no implicit bits from sve-max-vq.
194
+ */
195
+ if (!cpu_isar_feature(aa64_sve, cpu)) {
196
+ /* SVE is disabled and so are all vector lengths. Good. */
197
+ return;
198
+ }
199
+
200
+ /* Disabling a power-of-two disables all larger lengths. */
201
+ if (test_bit(0, cpu->sve_vq_init)) {
202
+ error_setg(errp, "cannot disable sve128");
203
+ error_append_hint(errp, "Disabling sve128 results in all vector "
204
+ "lengths being disabled.\n");
205
+ error_append_hint(errp, "With SVE enabled, at least one vector "
206
+ "length must be enabled.\n");
207
+ return;
208
+ }
209
+ for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) {
210
+ if (test_bit(vq - 1, cpu->sve_vq_init)) {
211
+ break;
212
+ }
213
+ }
214
+ max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
215
+
216
+ bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq);
217
+ max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1;
218
+ }
219
+
220
+ /*
221
+ * Process the sve-max-vq property.
222
+ * Note that we know from the above that no bit above
223
+ * sve-max-vq is currently set.
224
+ */
225
+ if (cpu->sve_max_vq != 0) {
226
+ max_vq = cpu->sve_max_vq;
227
+
228
+ if (!test_bit(max_vq - 1, cpu->sve_vq_map) &&
229
+ test_bit(max_vq - 1, cpu->sve_vq_init)) {
230
+ error_setg(errp, "cannot disable sve%d", max_vq * 128);
231
+ error_append_hint(errp, "The maximum vector length must be "
232
+ "enabled, sve-max-vq=%d (%d bits)\n",
233
+ max_vq, max_vq * 128);
234
+ return;
235
+ }
236
+
237
+ /* Set all bits not explicitly set within sve-max-vq. */
238
+ bitmap_complement(tmp, cpu->sve_vq_init, max_vq);
239
+ bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq);
240
+ }
241
+
242
+ /*
243
+ * We should know what max-vq is now. Also, as we're done
244
+ * manipulating sve-vq-map, we ensure any bits above max-vq
245
+ * are clear, just in case anybody looks.
246
+ */
247
+ assert(max_vq != 0);
248
+ bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq);
249
+
250
+ /* Ensure all required powers-of-two are enabled. */
251
+ for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
252
+ if (!test_bit(vq - 1, cpu->sve_vq_map)) {
253
+ error_setg(errp, "cannot disable sve%d", vq * 128);
254
+ error_append_hint(errp, "sve%d is required as it "
255
+ "is a power-of-two length smaller than "
256
+ "the maximum, sve%d\n",
257
+ vq * 128, max_vq * 128);
258
+ return;
259
+ }
260
+ }
261
+
262
+ /*
263
+ * Now that we validated all our vector lengths, the only question
264
+ * left to answer is if we even want SVE at all.
265
+ */
266
+ if (!cpu_isar_feature(aa64_sve, cpu)) {
267
+ error_setg(errp, "cannot enable sve%d", max_vq * 128);
268
+ error_append_hint(errp, "SVE must be enabled to enable vector "
269
+ "lengths.\n");
270
+ error_append_hint(errp, "Add sve=on to the CPU property list.\n");
271
+ return;
272
+ }
273
+
274
+ /* From now on sve_max_vq is the actual maximum supported length. */
275
+ cpu->sve_max_vq = max_vq;
276
+}
277
+
278
+uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
279
+{
280
+ uint32_t bitnum;
281
+
282
+ /*
283
+ * We allow vq == ARM_MAX_VQ + 1 to be input because the caller may want
284
+ * to find the maximum vq enabled, which may be ARM_MAX_VQ, but this
285
+ * function always returns the next smaller than the input.
286
+ */
287
+ assert(vq && vq <= ARM_MAX_VQ + 1);
288
+
289
+ bitnum = find_last_bit(cpu->sve_vq_map, vq - 1);
290
+ return bitnum == vq - 1 ? 0 : bitnum + 1;
291
+}
292
+
293
static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
294
void *opaque, Error **errp)
295
{
296
@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
297
error_propagate(errp, err);
298
}
299
300
+static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name,
301
+ void *opaque, Error **errp)
302
+{
303
+ ARMCPU *cpu = ARM_CPU(obj);
304
+ uint32_t vq = atoi(&name[3]) / 128;
305
+ bool value;
306
+
307
+ /* All vector lengths are disabled when SVE is off. */
308
+ if (!cpu_isar_feature(aa64_sve, cpu)) {
309
+ value = false;
310
+ } else {
311
+ value = test_bit(vq - 1, cpu->sve_vq_map);
312
+ }
313
+ visit_type_bool(v, name, &value, errp);
314
+}
315
+
316
+static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name,
317
+ void *opaque, Error **errp)
318
+{
319
+ ARMCPU *cpu = ARM_CPU(obj);
320
+ uint32_t vq = atoi(&name[3]) / 128;
321
+ Error *err = NULL;
322
+ bool value;
323
+
324
+ visit_type_bool(v, name, &value, &err);
325
+ if (err) {
326
+ error_propagate(errp, err);
327
+ return;
328
+ }
329
+
330
+ if (value) {
331
+ set_bit(vq - 1, cpu->sve_vq_map);
332
+ } else {
333
+ clear_bit(vq - 1, cpu->sve_vq_map);
334
+ }
335
+ set_bit(vq - 1, cpu->sve_vq_init);
336
+}
337
+
338
static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name,
339
void *opaque, Error **errp)
340
{
341
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
342
static void aarch64_max_initfn(Object *obj)
343
{
344
ARMCPU *cpu = ARM_CPU(obj);
345
+ uint32_t vq;
346
347
if (kvm_enabled()) {
348
kvm_arm_set_cpu_features_from_host(cpu);
349
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
350
cpu->dcz_blocksize = 7; /* 512 bytes */
351
#endif
352
353
- cpu->sve_max_vq = ARM_MAX_VQ;
354
object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
355
cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
356
object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
357
cpu_arm_set_sve, NULL, NULL, &error_fatal);
358
+
359
+ for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
360
+ char name[8];
361
+ sprintf(name, "sve%d", vq * 128);
362
+ object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
363
+ cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
364
+ }
365
}
366
}
367
368
diff --git a/target/arm/helper.c b/target/arm/helper.c
369
index XXXXXXX..XXXXXXX 100644
370
--- a/target/arm/helper.c
371
+++ b/target/arm/helper.c
372
@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
373
return 0;
374
}
375
376
+static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
377
+{
378
+ uint32_t start_vq = (start_len & 0xf) + 1;
379
+
380
+ return arm_cpu_vq_map_next_smaller(cpu, start_vq + 1) - 1;
381
+}
382
+
383
/*
384
* Given that SVE is enabled, return the vector length for EL.
385
*/
386
@@ -XXX,XX +XXX,XX @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
387
if (arm_feature(env, ARM_FEATURE_EL3)) {
388
zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
389
}
390
- return zcr_len;
391
+
392
+ return sve_zcr_get_valid_len(cpu, zcr_len);
393
}
394
395
static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
396
diff --git a/target/arm/monitor.c b/target/arm/monitor.c
397
index XXXXXXX..XXXXXXX 100644
398
--- a/target/arm/monitor.c
399
+++ b/target/arm/monitor.c
400
@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
401
return head;
402
}
403
404
+QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16);
405
+
406
/*
407
* These are cpu model features we want to advertise. The order here
408
* matters as this is the order in which qmp_query_cpu_model_expansion
409
@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
410
*/
411
static const char *cpu_model_advertised_features[] = {
412
"aarch64", "pmu", "sve",
413
+ "sve128", "sve256", "sve384", "sve512",
414
+ "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280",
415
+ "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048",
416
NULL
417
};
418
419
@@ -XXX,XX +XXX,XX @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
420
if (!err) {
421
visit_check_struct(visitor, &err);
422
}
423
+ if (!err) {
424
+ arm_cpu_finalize_features(ARM_CPU(obj), &err);
425
+ }
426
visit_end_struct(visitor, NULL);
427
visit_free(visitor);
428
if (err) {
429
@@ -XXX,XX +XXX,XX @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
430
error_propagate(errp, err);
431
return NULL;
432
}
433
+ } else {
434
+ Error *err = NULL;
435
+ arm_cpu_finalize_features(ARM_CPU(obj), &err);
436
+ assert(err == NULL);
437
}
438
439
expansion_info = g_new0(CpuModelExpansionInfo, 1);
440
diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
441
index XXXXXXX..XXXXXXX 100644
442
--- a/tests/arm-cpu-features.c
443
+++ b/tests/arm-cpu-features.c
444
@@ -XXX,XX +XXX,XX @@
445
* See the COPYING file in the top-level directory.
446
*/
447
#include "qemu/osdep.h"
448
+#include "qemu/bitops.h"
449
#include "libqtest.h"
450
#include "qapi/qmp/qdict.h"
451
#include "qapi/qmp/qjson.h"
452
453
+/*
454
+ * We expect the SVE max-vq to be 16. Also it must be <= 64
455
+ * for our test code, otherwise 'vls' can't just be a uint64_t.
456
+ */
457
+#define SVE_MAX_VQ 16
458
+
459
#define MACHINE "-machine virt,gic-version=max,accel=tcg "
460
#define MACHINE_KVM "-machine virt,gic-version=max,accel=kvm:tcg "
461
#define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \
462
@@ -XXX,XX +XXX,XX @@ static void assert_bad_props(QTestState *qts, const char *cpu_type)
463
qobject_unref(resp);
464
}
465
466
+static uint64_t resp_get_sve_vls(QDict *resp)
467
+{
468
+ QDict *props;
469
+ const QDictEntry *e;
470
+ uint64_t vls = 0;
471
+ int n = 0;
472
+
473
+ g_assert(resp);
474
+ g_assert(resp_has_props(resp));
475
+
476
+ props = resp_get_props(resp);
477
+
478
+ for (e = qdict_first(props); e; e = qdict_next(props, e)) {
479
+ if (strlen(e->key) > 3 && !strncmp(e->key, "sve", 3) &&
480
+ g_ascii_isdigit(e->key[3])) {
481
+ char *endptr;
482
+ int bits;
483
+
484
+ bits = g_ascii_strtoll(&e->key[3], &endptr, 10);
485
+ if (!bits || *endptr != '\0') {
486
+ continue;
487
+ }
488
+
489
+ if (qdict_get_bool(props, e->key)) {
490
+ vls |= BIT_ULL((bits / 128) - 1);
491
+ }
492
+ ++n;
493
+ }
494
+ }
495
+
496
+ g_assert(n == SVE_MAX_VQ);
497
+
498
+ return vls;
499
+}
500
+
501
+#define assert_sve_vls(qts, cpu_type, expected_vls, fmt, ...) \
502
+({ \
503
+ QDict *_resp = do_query(qts, cpu_type, fmt, ##__VA_ARGS__); \
504
+ g_assert(_resp); \
505
+ g_assert(resp_has_props(_resp)); \
506
+ g_assert(resp_get_sve_vls(_resp) == expected_vls); \
507
+ qobject_unref(_resp); \
508
+})
509
+
510
+static void sve_tests_default(QTestState *qts, const char *cpu_type)
511
+{
512
+ /*
513
+ * With no sve-max-vq or sve<N> properties on the command line
514
+ * the default is to have all vector lengths enabled. This also
515
+ * tests that 'sve' is 'on' by default.
516
+ */
517
+ assert_sve_vls(qts, cpu_type, BIT_ULL(SVE_MAX_VQ) - 1, NULL);
518
+
519
+ /* With SVE off, all vector lengths should also be off. */
520
+ assert_sve_vls(qts, cpu_type, 0, "{ 'sve': false }");
521
+
522
+ /* With SVE on, we must have at least one vector length enabled. */
523
+ assert_error(qts, cpu_type, "cannot disable sve128", "{ 'sve128': false }");
524
+
525
+ /* Basic enable/disable tests. */
526
+ assert_sve_vls(qts, cpu_type, 0x7, "{ 'sve384': true }");
527
+ assert_sve_vls(qts, cpu_type, ((BIT_ULL(SVE_MAX_VQ) - 1) & ~BIT_ULL(2)),
528
+ "{ 'sve384': false }");
529
+
530
+ /*
531
+ * ---------------------------------------------------------------------
532
+ * power-of-two(vq) all-power- can can
533
+ * of-two(< vq) enable disable
534
+ * ---------------------------------------------------------------------
535
+ * vq < max_vq no MUST* yes yes
536
+ * vq < max_vq yes MUST* yes no
537
+ * ---------------------------------------------------------------------
538
+ * vq == max_vq n/a MUST* yes** yes**
539
+ * ---------------------------------------------------------------------
540
+ * vq > max_vq n/a no no yes
541
+ * vq > max_vq n/a yes yes yes
542
+ * ---------------------------------------------------------------------
543
+ *
544
+ * [*] "MUST" means this requirement must already be satisfied,
545
+ * otherwise 'max_vq' couldn't itself be enabled.
546
+ *
547
+ * [**] Not testable with the QMP interface, only with the command line.
548
+ */
549
+
550
+ /* max_vq := 8 */
551
+ assert_sve_vls(qts, cpu_type, 0x8b, "{ 'sve1024': true }");
552
+
553
+ /* max_vq := 8, vq < max_vq, !power-of-two(vq) */
554
+ assert_sve_vls(qts, cpu_type, 0x8f,
555
+ "{ 'sve1024': true, 'sve384': true }");
556
+ assert_sve_vls(qts, cpu_type, 0x8b,
557
+ "{ 'sve1024': true, 'sve384': false }");
558
+
559
+ /* max_vq := 8, vq < max_vq, power-of-two(vq) */
560
+ assert_sve_vls(qts, cpu_type, 0x8b,
561
+ "{ 'sve1024': true, 'sve256': true }");
562
+ assert_error(qts, cpu_type, "cannot disable sve256",
563
+ "{ 'sve1024': true, 'sve256': false }");
564
+
565
+ /* max_vq := 3, vq > max_vq, !all-power-of-two(< vq) */
566
+ assert_error(qts, cpu_type, "cannot disable sve512",
567
+ "{ 'sve384': true, 'sve512': false, 'sve640': true }");
568
+
569
+ /*
570
+ * We can disable power-of-two vector lengths when all larger lengths
571
+ * are also disabled. We only need to disable the power-of-two length,
572
+ * as all non-enabled larger lengths will then be auto-disabled.
573
+ */
574
+ assert_sve_vls(qts, cpu_type, 0x7, "{ 'sve512': false }");
575
+
576
+ /* max_vq := 3, vq > max_vq, all-power-of-two(< vq) */
577
+ assert_sve_vls(qts, cpu_type, 0x1f,
578
+ "{ 'sve384': true, 'sve512': true, 'sve640': true }");
579
+ assert_sve_vls(qts, cpu_type, 0xf,
580
+ "{ 'sve384': true, 'sve512': true, 'sve640': false }");
581
+}
582
+
583
+static void sve_tests_sve_max_vq_8(const void *data)
584
+{
585
+ QTestState *qts;
586
+
587
+ qts = qtest_init(MACHINE "-cpu max,sve-max-vq=8");
588
+
589
+ assert_sve_vls(qts, "max", BIT_ULL(8) - 1, NULL);
590
+
591
+ /*
592
+ * Disabling the max-vq set by sve-max-vq is not allowed, but
593
+ * of course enabling it is OK.
594
+ */
595
+ assert_error(qts, "max", "cannot disable sve1024", "{ 'sve1024': false }");
596
+ assert_sve_vls(qts, "max", 0xff, "{ 'sve1024': true }");
597
+
598
+ /*
599
+ * Enabling anything larger than max-vq set by sve-max-vq is not
600
+ * allowed, but of course disabling everything larger is OK.
601
+ */
602
+ assert_error(qts, "max", "cannot enable sve1152", "{ 'sve1152': true }");
603
+ assert_sve_vls(qts, "max", 0xff, "{ 'sve1152': false }");
604
+
605
+ /*
606
+ * We can enable/disable non power-of-two lengths smaller than the
607
+ * max-vq set by sve-max-vq, but, while we can enable power-of-two
608
+ * lengths, we can't disable them.
609
+ */
610
+ assert_sve_vls(qts, "max", 0xff, "{ 'sve384': true }");
611
+ assert_sve_vls(qts, "max", 0xfb, "{ 'sve384': false }");
612
+ assert_sve_vls(qts, "max", 0xff, "{ 'sve256': true }");
613
+ assert_error(qts, "max", "cannot disable sve256", "{ 'sve256': false }");
614
+
615
+ qtest_quit(qts);
616
+}
617
+
618
+static void sve_tests_sve_off(const void *data)
619
+{
620
+ QTestState *qts;
621
+
622
+ qts = qtest_init(MACHINE "-cpu max,sve=off");
623
+
624
+ /* SVE is off, so the map should be empty. */
625
+ assert_sve_vls(qts, "max", 0, NULL);
626
+
627
+ /* The map stays empty even if we turn lengths off. */
628
+ assert_sve_vls(qts, "max", 0, "{ 'sve128': false }");
629
+
630
+ /* It's an error to enable lengths when SVE is off. */
631
+ assert_error(qts, "max", "cannot enable sve128", "{ 'sve128': true }");
632
+
633
+ /* With SVE re-enabled we should get all vector lengths enabled. */
634
+ assert_sve_vls(qts, "max", BIT_ULL(SVE_MAX_VQ) - 1, "{ 'sve': true }");
635
+
636
+ /* Or enable SVE with just specific vector lengths. */
637
+ assert_sve_vls(qts, "max", 0x3,
638
+ "{ 'sve': true, 'sve128': true, 'sve256': true }");
639
+
640
+ qtest_quit(qts);
641
+}
642
+
643
static void test_query_cpu_model_expansion(const void *data)
644
{
645
QTestState *qts;
646
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
647
if (g_str_equal(qtest_get_arch(), "aarch64")) {
648
assert_has_feature(qts, "max", "aarch64");
649
assert_has_feature(qts, "max", "sve");
650
+ assert_has_feature(qts, "max", "sve128");
651
assert_has_feature(qts, "cortex-a57", "pmu");
652
assert_has_feature(qts, "cortex-a57", "aarch64");
653
654
+ sve_tests_default(qts, "max");
655
+
656
/* Test that features that depend on KVM generate errors without. */
657
assert_error(qts, "max",
658
"'aarch64' feature cannot be disabled "
659
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
660
qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
661
NULL, test_query_cpu_model_expansion_kvm);
662
663
+ if (g_str_equal(qtest_get_arch(), "aarch64")) {
664
+ qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
665
+ NULL, sve_tests_sve_max_vq_8);
666
+ qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
667
+ NULL, sve_tests_sve_off);
668
+ }
669
+
670
return g_test_run();
671
}
672
diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
673
index XXXXXXX..XXXXXXX 100644
674
--- a/docs/arm-cpu-features.rst
675
+++ b/docs/arm-cpu-features.rst
676
@@ -XXX,XX +XXX,XX @@ block in the script for usage) is used to issue the QMP commands.
677
(QEMU) query-cpu-model-expansion type=full model={"name":"max"}
678
{ "return": {
679
"model": { "name": "max", "props": {
680
- "pmu": true, "aarch64": true
681
+ "sve1664": true, "pmu": true, "sve1792": true, "sve1920": true,
682
+ "sve128": true, "aarch64": true, "sve1024": true, "sve": true,
683
+ "sve640": true, "sve768": true, "sve1408": true, "sve256": true,
684
+ "sve1152": true, "sve512": true, "sve384": true, "sve1536": true,
685
+ "sve896": true, "sve1280": true, "sve2048": true
686
}}}}
687
688
-We see that the `max` CPU type has the `pmu` and `aarch64` CPU features.
689
-We also see that the CPU features are enabled, as they are all `true`.
690
+We see that the `max` CPU type has the `pmu`, `aarch64`, `sve`, and many
691
+`sve<N>` CPU features. We also see that all the CPU features are
692
+enabled, as they are all `true`. (The `sve<N>` CPU features are all
693
+optional SVE vector lengths (see "SVE CPU Properties"). While with TCG
694
+all SVE vector lengths can be supported, when KVM is in use it's more
695
+likely that only a few lengths will be supported, if SVE is supported at
696
+all.)
697
698
(2) Let's try to disable the PMU::
699
700
(QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"pmu":false}}
701
{ "return": {
702
"model": { "name": "max", "props": {
703
- "pmu": false, "aarch64": true
704
+ "sve1664": true, "pmu": false, "sve1792": true, "sve1920": true,
705
+ "sve128": true, "aarch64": true, "sve1024": true, "sve": true,
706
+ "sve640": true, "sve768": true, "sve1408": true, "sve256": true,
707
+ "sve1152": true, "sve512": true, "sve384": true, "sve1536": true,
708
+ "sve896": true, "sve1280": true, "sve2048": true
709
}}}}
710
711
We see it worked, as `pmu` is now `false`.
712
@@ -XXX,XX +XXX,XX @@ We see it worked, as `pmu` is now `false`.
713
It looks like this feature is limited to a configuration we do not
714
currently have.
715
716
-(4) Let's try probing CPU features for the Cortex-A15 CPU type::
717
+(4) Let's disable `sve` and see what happens to all the optional SVE
718
+ vector lengths::
719
+
720
+ (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"sve":false}}
721
+ { "return": {
722
+ "model": { "name": "max", "props": {
723
+ "sve1664": false, "pmu": true, "sve1792": false, "sve1920": false,
724
+ "sve128": false, "aarch64": true, "sve1024": false, "sve": false,
725
+ "sve640": false, "sve768": false, "sve1408": false, "sve256": false,
726
+ "sve1152": false, "sve512": false, "sve384": false, "sve1536": false,
727
+ "sve896": false, "sve1280": false, "sve2048": false
728
+ }}}}
729
+
730
+As expected they are now all `false`.
731
+
732
+(5) Let's try probing CPU features for the Cortex-A15 CPU type::
733
734
(QEMU) query-cpu-model-expansion type=full model={"name":"cortex-a15"}
735
{"return": {"model": {"name": "cortex-a15", "props": {"pmu": true}}}}
736
@@ -XXX,XX +XXX,XX @@ After determining which CPU features are available and supported for a
737
given CPU type, then they may be selectively enabled or disabled on the
738
QEMU command line with that CPU type::
739
740
- $ qemu-system-aarch64 -M virt -cpu max,pmu=off
741
+ $ qemu-system-aarch64 -M virt -cpu max,pmu=off,sve=on,sve128=on,sve256=on
742
743
-The example above disables the PMU for the `max` CPU type.
744
+The example above disables the PMU and enables the first two SVE vector
745
+lengths for the `max` CPU type. Note, the `sve=on` isn't actually
746
+necessary, because, as we observed above with our probe of the `max` CPU
747
+type, `sve` is already on by default. Also, based on our probe of
748
+defaults, it would seem we need to disable many SVE vector lengths, rather
749
+than only enabling the two we want. This isn't the case, because, as
750
+disabling many SVE vector lengths would be quite verbose, the `sve<N>` CPU
751
+properties have special semantics (see "SVE CPU Property Parsing
752
+Semantics").
753
+
754
+SVE CPU Properties
755
+==================
756
+
757
+There are two types of SVE CPU properties: `sve` and `sve<N>`. The first
758
+is used to enable or disable the entire SVE feature, just as the `pmu`
759
+CPU property completely enables or disables the PMU. The second type
760
+is used to enable or disable specific vector lengths, where `N` is the
761
+number of bits of the length. The `sve<N>` CPU properties have special
762
+dependencies and constraints, see "SVE CPU Property Dependencies and
763
+Constraints" below. Additionally, as we want all supported vector lengths
764
+to be enabled by default, then, in order to avoid overly verbose command
765
+lines (command lines full of `sve<N>=off`, for all `N` not wanted), we
766
+provide the parsing semantics listed in "SVE CPU Property Parsing
767
+Semantics".
768
+
769
+SVE CPU Property Dependencies and Constraints
770
+---------------------------------------------
771
+
772
+ 1) At least one vector length must be enabled when `sve` is enabled.
773
+
774
+ 2) If a vector length `N` is enabled, then all power-of-two vector
775
+ lengths smaller than `N` must also be enabled. E.g. if `sve512`
776
+ is enabled, then the 128-bit and 256-bit vector lengths must also
777
+ be enabled.
778
+
779
+SVE CPU Property Parsing Semantics
780
+----------------------------------
781
+
782
+ 1) If SVE is disabled (`sve=off`), then which SVE vector lengths
783
+ are enabled or disabled is irrelevant to the guest, as the entire
784
+ SVE feature is disabled and that disables all vector lengths for
785
+ the guest. However QEMU will still track any `sve<N>` CPU
786
+ properties provided by the user. If later an `sve=on` is provided,
787
+ then the guest will get only the enabled lengths. If no `sve=on`
788
+ is provided and there are explicitly enabled vector lengths, then
789
+ an error is generated.
790
+
791
+ 2) If SVE is enabled (`sve=on`), but no `sve<N>` CPU properties are
792
+ provided, then all supported vector lengths are enabled, including
793
+ the non-power-of-two lengths.
794
+
795
+ 3) If SVE is enabled, then an error is generated when attempting to
796
+ disable the last enabled vector length (see constraint (1) of "SVE
797
+ CPU Property Dependencies and Constraints").
798
+
799
+ 4) If one or more vector lengths have been explicitly enabled and at
800
+ at least one of the dependency lengths of the maximum enabled length
801
+ has been explicitly disabled, then an error is generated (see
802
+ constraint (2) of "SVE CPU Property Dependencies and Constraints").
803
+
804
+ 5) If one or more `sve<N>` CPU properties are set `off`, but no `sve<N>`,
805
+ CPU properties are set `on`, then the specified vector lengths are
806
+ disabled but the default for any unspecified lengths remains enabled.
807
+ Disabling a power-of-two vector length also disables all vector
808
+ lengths larger than the power-of-two length (see constraint (2) of
809
+ "SVE CPU Property Dependencies and Constraints").
810
+
811
+ 6) If one or more `sve<N>` CPU properties are set to `on`, then they
812
+ are enabled and all unspecified lengths default to disabled, except
813
+ for the required lengths per constraint (2) of "SVE CPU Property
814
+ Dependencies and Constraints", which will even be auto-enabled if
815
+ they were not explicitly enabled.
816
+
817
+ 7) If SVE was disabled (`sve=off`), allowing all vector lengths to be
818
+ explicitly disabled (i.e. avoiding the error specified in (3) of
819
+ "SVE CPU Property Parsing Semantics"), then if later an `sve=on` is
820
+ provided an error will be generated. To avoid this error, one must
821
+ enable at least one vector length prior to enabling SVE.
822
+
823
+SVE CPU Property Examples
824
+-------------------------
825
+
826
+ 1) Disable SVE::
827
+
828
+ $ qemu-system-aarch64 -M virt -cpu max,sve=off
829
+
830
+ 2) Implicitly enable all vector lengths for the `max` CPU type::
831
+
832
+ $ qemu-system-aarch64 -M virt -cpu max
833
+
834
+ 3) Only enable the 128-bit vector length::
835
+
836
+ $ qemu-system-aarch64 -M virt -cpu max,sve128=on
837
+
838
+ 4) Disable the 512-bit vector length and all larger vector lengths,
839
+ since 512 is a power-of-two. This results in all the smaller,
840
+ uninitialized lengths (128, 256, and 384) defaulting to enabled::
841
+
842
+ $ qemu-system-aarch64 -M virt -cpu max,sve512=off
843
+
844
+ 5) Enable the 128-bit, 256-bit, and 512-bit vector lengths::
845
+
846
+ $ qemu-system-aarch64 -M virt -cpu max,sve128=on,sve256=on,sve512=on
847
+
848
+ 6) The same as (5), but since the 128-bit and 256-bit vector
849
+ lengths are required for the 512-bit vector length to be enabled,
850
+ then allow them to be auto-enabled::
851
+
852
+ $ qemu-system-aarch64 -M virt -cpu max,sve512=on
853
+
854
+ 7) Do the same as (6), but by first disabling SVE and then re-enabling it::
855
+
856
+ $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve512=on,sve=on
857
+
858
+ 8) Force errors regarding the last vector length::
859
+
860
+ $ qemu-system-aarch64 -M virt -cpu max,sve128=off
861
+ $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve128=off,sve=on
862
+
863
+SVE CPU Property Recommendations
864
+--------------------------------
865
+
866
+The examples in "SVE CPU Property Examples" exhibit many ways to select
867
+vector lengths which developers may find useful in order to avoid overly
868
+verbose command lines. However, the recommended way to select vector
869
+lengths is to explicitly enable each desired length. Therefore only
870
+example's (1), (3), and (5) exhibit recommended uses of the properties.
871
872
--
873
2.20.1
874
875
diff view generated by jsdifflib
[PULL 05/11] target/arm/kvm64: Add kvm_arch_get/put_sve
Deleted patch
1
From: Andrew Jones <drjones@redhat.com>
2
1
3
These are the SVE equivalents to kvm_arch_get/put_fpsimd. Note, the
4
swabbing is different than it is for fpsmid because the vector format
5
is a little-endian stream of words.
6
7
Signed-off-by: Andrew Jones <drjones@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
11
Message-id: 20191031142734.8590-6-drjones@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/kvm64.c | 185 ++++++++++++++++++++++++++++++++++++++-------
15
1 file changed, 156 insertions(+), 29 deletions(-)
16
17
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/kvm64.c
20
+++ b/target/arm/kvm64.c
21
@@ -XXX,XX +XXX,XX @@ int kvm_arch_destroy_vcpu(CPUState *cs)
22
bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
23
{
24
/* Return true if the regidx is a register we should synchronize
25
- * via the cpreg_tuples array (ie is not a core reg we sync by
26
- * hand in kvm_arch_get/put_registers())
27
+ * via the cpreg_tuples array (ie is not a core or sve reg that
28
+ * we sync by hand in kvm_arch_get/put_registers())
29
*/
30
switch (regidx & KVM_REG_ARM_COPROC_MASK) {
31
case KVM_REG_ARM_CORE:
32
+ case KVM_REG_ARM64_SVE:
33
return false;
34
default:
35
return true;
36
@@ -XXX,XX +XXX,XX @@ int kvm_arm_cpreg_level(uint64_t regidx)
37
38
static int kvm_arch_put_fpsimd(CPUState *cs)
39
{
40
- ARMCPU *cpu = ARM_CPU(cs);
41
- CPUARMState *env = &cpu->env;
42
+ CPUARMState *env = &ARM_CPU(cs)->env;
43
struct kvm_one_reg reg;
44
- uint32_t fpr;
45
int i, ret;
46
47
for (i = 0; i < 32; i++) {
48
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_fpsimd(CPUState *cs)
49
}
50
}
51
52
- reg.addr = (uintptr_t)(&fpr);
53
- fpr = vfp_get_fpsr(env);
54
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
55
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
56
- if (ret) {
57
- return ret;
58
+ return 0;
59
+}
60
+
61
+/*
62
+ * SVE registers are encoded in KVM's memory in an endianness-invariant format.
63
+ * The byte at offset i from the start of the in-memory representation contains
64
+ * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
65
+ * lowest offsets are stored in the lowest memory addresses, then that nearly
66
+ * matches QEMU's representation, which is to use an array of host-endian
67
+ * uint64_t's, where the lower offsets are at the lower indices. To complete
68
+ * the translation we just need to byte swap the uint64_t's on big-endian hosts.
69
+ */
70
+static uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
71
+{
72
+#ifdef HOST_WORDS_BIGENDIAN
73
+ int i;
74
+
75
+ for (i = 0; i < nr; ++i) {
76
+ dst[i] = bswap64(src[i]);
77
}
78
79
- reg.addr = (uintptr_t)(&fpr);
80
- fpr = vfp_get_fpcr(env);
81
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
82
+ return dst;
83
+#else
84
+ return src;
85
+#endif
86
+}
87
+
88
+/*
89
+ * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits
90
+ * and PREGS and the FFR have a slice size of 256 bits. However we simply hard
91
+ * code the slice index to zero for now as it's unlikely we'll need more than
92
+ * one slice for quite some time.
93
+ */
94
+static int kvm_arch_put_sve(CPUState *cs)
95
+{
96
+ ARMCPU *cpu = ARM_CPU(cs);
97
+ CPUARMState *env = &cpu->env;
98
+ uint64_t tmp[ARM_MAX_VQ * 2];
99
+ uint64_t *r;
100
+ struct kvm_one_reg reg;
101
+ int n, ret;
102
+
103
+ for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
104
+ r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2);
105
+ reg.addr = (uintptr_t)r;
106
+ reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
107
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
108
+ if (ret) {
109
+ return ret;
110
+ }
111
+ }
112
+
113
+ for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
114
+ r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0],
115
+ DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
116
+ reg.addr = (uintptr_t)r;
117
+ reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
118
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
119
+ if (ret) {
120
+ return ret;
121
+ }
122
+ }
123
+
124
+ r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0],
125
+ DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
126
+ reg.addr = (uintptr_t)r;
127
+ reg.id = KVM_REG_ARM64_SVE_FFR(0);
128
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
129
if (ret) {
130
return ret;
131
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
132
{
133
struct kvm_one_reg reg;
134
uint64_t val;
135
+ uint32_t fpr;
136
int i, ret;
137
unsigned int el;
138
139
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
140
}
141
}
142
143
- ret = kvm_arch_put_fpsimd(cs);
144
+ if (cpu_isar_feature(aa64_sve, cpu)) {
145
+ ret = kvm_arch_put_sve(cs);
146
+ } else {
147
+ ret = kvm_arch_put_fpsimd(cs);
148
+ }
149
+ if (ret) {
150
+ return ret;
151
+ }
152
+
153
+ reg.addr = (uintptr_t)(&fpr);
154
+ fpr = vfp_get_fpsr(env);
155
+ reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
156
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
157
+ if (ret) {
158
+ return ret;
159
+ }
160
+
161
+ reg.addr = (uintptr_t)(&fpr);
162
+ fpr = vfp_get_fpcr(env);
163
+ reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
164
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
165
if (ret) {
166
return ret;
167
}
168
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
169
170
static int kvm_arch_get_fpsimd(CPUState *cs)
171
{
172
- ARMCPU *cpu = ARM_CPU(cs);
173
- CPUARMState *env = &cpu->env;
174
+ CPUARMState *env = &ARM_CPU(cs)->env;
175
struct kvm_one_reg reg;
176
- uint32_t fpr;
177
int i, ret;
178
179
for (i = 0; i < 32; i++) {
180
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_fpsimd(CPUState *cs)
181
}
182
}
183
184
- reg.addr = (uintptr_t)(&fpr);
185
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
186
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
187
- if (ret) {
188
- return ret;
189
- }
190
- vfp_set_fpsr(env, fpr);
191
+ return 0;
192
+}
193
194
- reg.addr = (uintptr_t)(&fpr);
195
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
196
+/*
197
+ * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits
198
+ * and PREGS and the FFR have a slice size of 256 bits. However we simply hard
199
+ * code the slice index to zero for now as it's unlikely we'll need more than
200
+ * one slice for quite some time.
201
+ */
202
+static int kvm_arch_get_sve(CPUState *cs)
203
+{
204
+ ARMCPU *cpu = ARM_CPU(cs);
205
+ CPUARMState *env = &cpu->env;
206
+ struct kvm_one_reg reg;
207
+ uint64_t *r;
208
+ int n, ret;
209
+
210
+ for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
211
+ r = &env->vfp.zregs[n].d[0];
212
+ reg.addr = (uintptr_t)r;
213
+ reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
214
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
215
+ if (ret) {
216
+ return ret;
217
+ }
218
+ sve_bswap64(r, r, cpu->sve_max_vq * 2);
219
+ }
220
+
221
+ for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
222
+ r = &env->vfp.pregs[n].p[0];
223
+ reg.addr = (uintptr_t)r;
224
+ reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
225
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
226
+ if (ret) {
227
+ return ret;
228
+ }
229
+ sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
230
+ }
231
+
232
+ r = &env->vfp.pregs[FFR_PRED_NUM].p[0];
233
+ reg.addr = (uintptr_t)r;
234
+ reg.id = KVM_REG_ARM64_SVE_FFR(0);
235
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
236
if (ret) {
237
return ret;
238
}
239
- vfp_set_fpcr(env, fpr);
240
+ sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
241
242
return 0;
243
}
244
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
245
struct kvm_one_reg reg;
246
uint64_t val;
247
unsigned int el;
248
+ uint32_t fpr;
249
int i, ret;
250
251
ARMCPU *cpu = ARM_CPU(cs);
252
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
253
env->spsr = env->banked_spsr[i];
254
}
255
256
- ret = kvm_arch_get_fpsimd(cs);
257
+ if (cpu_isar_feature(aa64_sve, cpu)) {
258
+ ret = kvm_arch_get_sve(cs);
259
+ } else {
260
+ ret = kvm_arch_get_fpsimd(cs);
261
+ }
262
if (ret) {
263
return ret;
264
}
265
266
+ reg.addr = (uintptr_t)(&fpr);
267
+ reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
268
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
269
+ if (ret) {
270
+ return ret;
271
+ }
272
+ vfp_set_fpsr(env, fpr);
273
+
274
+ reg.addr = (uintptr_t)(&fpr);
275
+ reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
276
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
277
+ if (ret) {
278
+ return ret;
279
+ }
280
+ vfp_set_fpcr(env, fpr);
281
+
282
ret = kvm_get_vcpu_events(cpu);
283
if (ret) {
284
return ret;
285
--
286
2.20.1
287
288
diff view generated by jsdifflib
[PULL 08/11] target/arm/cpu64: max cpu: Support sve properties with KVM
[PULL 1/5] hw/sd: Fix sun4i allwinner-sdhost for U-Boot
1
From: Andrew Jones <drjones@redhat.com>
1
From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
2
2
3
Extend the SVE vq map initialization and validation with KVM's
3
Trying to run U-Boot for Cubieboard (Allwinner A10) fails because it cannot
4
supported vector lengths when KVM is enabled. In order to determine
4
access SD card. The problem is that FIFO register in current
5
and select supported lengths we add two new KVM functions for getting
5
allwinner-sdhost implementation is at the address corresponding to
6
and setting the KVM_REG_ARM64_SVE_VLS pseudo-register.
6
Allwinner H3, but not A10.
7
Linux kernel is not affected since Linux driver uses DMA access and does
8
not use FIFO register for reading/writing.
7
9
8
This patch has been co-authored with Richard Henderson, who reworked
10
This patch adds new class parameter `is_sun4i` and based on that
9
the target/arm/cpu64.c changes in order to push all the validation and
11
parameter uses register at offset 0x100 either as FIFO register (if
10
auto-enabling/disabling steps into the finalizer, resulting in a nice
12
sun4i) or as threshold register (if not sun4i; in this case register at
11
LOC reduction.
13
0x200 is FIFO register).
12
14
13
Signed-off-by: Andrew Jones <drjones@redhat.com>
15
Tested with U-Boot and Linux kernel image built for Cubieboard and
14
Reviewed-by: Eric Auger <eric.auger@redhat.com>
16
OrangePi PC.
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
16
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
18
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
17
Message-id: 20191031142734.8590-9-drjones@redhat.com
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
Message-id: 20221112214900.24152-1-strahinja.p.jankovic@gmail.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
22
---
20
target/arm/kvm_arm.h | 12 +++
23
include/hw/sd/allwinner-sdhost.h | 1 +
21
target/arm/cpu64.c | 176 ++++++++++++++++++++++++++++----------
24
hw/sd/allwinner-sdhost.c | 67 ++++++++++++++++++++++----------
22
target/arm/kvm64.c | 100 +++++++++++++++++++++-
25
2 files changed, 47 insertions(+), 21 deletions(-)
23
tests/arm-cpu-features.c | 104 +++++++++++++++++++++-
24
docs/arm-cpu-features.rst | 45 +++++++---
25
5 files changed, 379 insertions(+), 58 deletions(-)
26
26
27
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
27
diff --git a/include/hw/sd/allwinner-sdhost.h b/include/hw/sd/allwinner-sdhost.h
28
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/kvm_arm.h
29
--- a/include/hw/sd/allwinner-sdhost.h
30
+++ b/target/arm/kvm_arm.h
30
+++ b/include/hw/sd/allwinner-sdhost.h
31
@@ -XXX,XX +XXX,XX @@ typedef struct ARMHostCPUFeatures {
31
@@ -XXX,XX +XXX,XX @@ struct AwSdHostClass {
32
*/
32
33
bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf);
33
/** Maximum buffer size in bytes per DMA descriptor */
34
34
size_t max_desc_size;
35
+/**
35
+ bool is_sun4i;
36
+ * kvm_arm_sve_get_vls:
36
37
+ * @cs: CPUState
37
};
38
+ * @map: bitmap to fill in
38
39
+ *
39
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
40
+ * Get all the SVE vector lengths supported by the KVM host, setting
40
index XXXXXXX..XXXXXXX 100644
41
+ * the bits corresponding to their length in quadwords minus one
41
--- a/hw/sd/allwinner-sdhost.c
42
+ * (vq - 1) in @map up to ARM_MAX_VQ.
42
+++ b/hw/sd/allwinner-sdhost.c
43
+ */
43
@@ -XXX,XX +XXX,XX @@ enum {
44
+void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map);
44
REG_SD_DLBA = 0x84, /* Descriptor List Base Address */
45
REG_SD_IDST = 0x88, /* Internal DMA Controller Status */
46
REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */
47
- REG_SD_THLDC = 0x100, /* Card Threshold Control */
48
+ REG_SD_THLDC = 0x100, /* Card Threshold Control / FIFO (sun4i only)*/
49
REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */
50
REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */
51
REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */
52
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_dma(AwSdHostState *s)
53
}
54
}
55
56
+static uint32_t allwinner_sdhost_fifo_read(AwSdHostState *s)
57
+{
58
+ uint32_t res = 0;
45
+
59
+
46
/**
60
+ if (sdbus_data_ready(&s->sdbus)) {
47
* kvm_arm_set_cpu_features_from_host:
61
+ sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t));
48
* @cpu: ARMCPU to set the features for
62
+ le32_to_cpus(&res);
49
@@ -XXX,XX +XXX,XX @@ static inline int kvm_arm_vgic_probe(void)
63
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
50
static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {}
64
+ allwinner_sdhost_auto_stop(s);
51
static inline void kvm_arm_pmu_init(CPUState *cs) {}
65
+ allwinner_sdhost_update_irq(s);
52
66
+ } else {
53
+static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) {}
67
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
54
#endif
68
+ __func__);
55
56
static inline const char *gic_class_name(void)
57
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/cpu64.c
60
+++ b/target/arm/cpu64.c
61
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
62
* any of the above. Finally, if SVE is not disabled, then at least one
63
* vector length must be enabled.
64
*/
65
+ DECLARE_BITMAP(kvm_supported, ARM_MAX_VQ);
66
DECLARE_BITMAP(tmp, ARM_MAX_VQ);
67
uint32_t vq, max_vq = 0;
68
69
+ /* Collect the set of vector lengths supported by KVM. */
70
+ bitmap_zero(kvm_supported, ARM_MAX_VQ);
71
+ if (kvm_enabled() && kvm_arm_sve_supported(CPU(cpu))) {
72
+ kvm_arm_sve_get_vls(CPU(cpu), kvm_supported);
73
+ } else if (kvm_enabled()) {
74
+ assert(!cpu_isar_feature(aa64_sve, cpu));
75
+ }
69
+ }
76
+
70
+
77
/*
71
+ return res;
78
* Process explicit sve<N> properties.
79
* From the properties, sve_vq_map<N> implies sve_vq_init<N>.
80
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
81
return;
82
}
83
84
- /* Propagate enabled bits down through required powers-of-two. */
85
- for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
86
- if (!test_bit(vq - 1, cpu->sve_vq_init)) {
87
- set_bit(vq - 1, cpu->sve_vq_map);
88
+ if (kvm_enabled()) {
89
+ /*
90
+ * For KVM we have to automatically enable all supported unitialized
91
+ * lengths, even when the smaller lengths are not all powers-of-two.
92
+ */
93
+ bitmap_andnot(tmp, kvm_supported, cpu->sve_vq_init, max_vq);
94
+ bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq);
95
+ } else {
96
+ /* Propagate enabled bits down through required powers-of-two. */
97
+ for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
98
+ if (!test_bit(vq - 1, cpu->sve_vq_init)) {
99
+ set_bit(vq - 1, cpu->sve_vq_map);
100
+ }
101
}
102
}
103
} else if (cpu->sve_max_vq == 0) {
104
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
105
return;
106
}
107
108
- /* Disabling a power-of-two disables all larger lengths. */
109
- if (test_bit(0, cpu->sve_vq_init)) {
110
- error_setg(errp, "cannot disable sve128");
111
- error_append_hint(errp, "Disabling sve128 results in all vector "
112
- "lengths being disabled.\n");
113
- error_append_hint(errp, "With SVE enabled, at least one vector "
114
- "length must be enabled.\n");
115
- return;
116
- }
117
- for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) {
118
- if (test_bit(vq - 1, cpu->sve_vq_init)) {
119
- break;
120
+ if (kvm_enabled()) {
121
+ /* Disabling a supported length disables all larger lengths. */
122
+ for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
123
+ if (test_bit(vq - 1, cpu->sve_vq_init) &&
124
+ test_bit(vq - 1, kvm_supported)) {
125
+ break;
126
+ }
127
}
128
+ max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
129
+ bitmap_andnot(cpu->sve_vq_map, kvm_supported,
130
+ cpu->sve_vq_init, max_vq);
131
+ if (max_vq == 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) {
132
+ error_setg(errp, "cannot disable sve%d", vq * 128);
133
+ error_append_hint(errp, "Disabling sve%d results in all "
134
+ "vector lengths being disabled.\n",
135
+ vq * 128);
136
+ error_append_hint(errp, "With SVE enabled, at least one "
137
+ "vector length must be enabled.\n");
138
+ return;
139
+ }
140
+ } else {
141
+ /* Disabling a power-of-two disables all larger lengths. */
142
+ if (test_bit(0, cpu->sve_vq_init)) {
143
+ error_setg(errp, "cannot disable sve128");
144
+ error_append_hint(errp, "Disabling sve128 results in all "
145
+ "vector lengths being disabled.\n");
146
+ error_append_hint(errp, "With SVE enabled, at least one "
147
+ "vector length must be enabled.\n");
148
+ return;
149
+ }
150
+ for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) {
151
+ if (test_bit(vq - 1, cpu->sve_vq_init)) {
152
+ break;
153
+ }
154
+ }
155
+ max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
156
+ bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq);
157
}
158
- max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
159
160
- bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq);
161
max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1;
162
}
163
164
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
165
assert(max_vq != 0);
166
bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq);
167
168
- /* Ensure all required powers-of-two are enabled. */
169
- for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
170
- if (!test_bit(vq - 1, cpu->sve_vq_map)) {
171
- error_setg(errp, "cannot disable sve%d", vq * 128);
172
- error_append_hint(errp, "sve%d is required as it "
173
- "is a power-of-two length smaller than "
174
- "the maximum, sve%d\n",
175
- vq * 128, max_vq * 128);
176
+ if (kvm_enabled()) {
177
+ /* Ensure the set of lengths matches what KVM supports. */
178
+ bitmap_xor(tmp, cpu->sve_vq_map, kvm_supported, max_vq);
179
+ if (!bitmap_empty(tmp, max_vq)) {
180
+ vq = find_last_bit(tmp, max_vq) + 1;
181
+ if (test_bit(vq - 1, cpu->sve_vq_map)) {
182
+ if (cpu->sve_max_vq) {
183
+ error_setg(errp, "cannot set sve-max-vq=%d",
184
+ cpu->sve_max_vq);
185
+ error_append_hint(errp, "This KVM host does not support "
186
+ "the vector length %d-bits.\n",
187
+ vq * 128);
188
+ error_append_hint(errp, "It may not be possible to use "
189
+ "sve-max-vq with this KVM host. Try "
190
+ "using only sve<N> properties.\n");
191
+ } else {
192
+ error_setg(errp, "cannot enable sve%d", vq * 128);
193
+ error_append_hint(errp, "This KVM host does not support "
194
+ "the vector length %d-bits.\n",
195
+ vq * 128);
196
+ }
197
+ } else {
198
+ error_setg(errp, "cannot disable sve%d", vq * 128);
199
+ error_append_hint(errp, "The KVM host requires all "
200
+ "supported vector lengths smaller "
201
+ "than %d bits to also be enabled.\n",
202
+ max_vq * 128);
203
+ }
204
return;
205
}
206
+ } else {
207
+ /* Ensure all required powers-of-two are enabled. */
208
+ for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
209
+ if (!test_bit(vq - 1, cpu->sve_vq_map)) {
210
+ error_setg(errp, "cannot disable sve%d", vq * 128);
211
+ error_append_hint(errp, "sve%d is required as it "
212
+ "is a power-of-two length smaller than "
213
+ "the maximum, sve%d\n",
214
+ vq * 128, max_vq * 128);
215
+ return;
216
+ }
217
+ }
218
}
219
220
/*
221
@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
222
{
223
ARMCPU *cpu = ARM_CPU(obj);
224
Error *err = NULL;
225
+ uint32_t max_vq;
226
227
- visit_type_uint32(v, name, &cpu->sve_max_vq, &err);
228
-
229
- if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) {
230
- error_setg(&err, "unsupported SVE vector length");
231
- error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n",
232
- ARM_MAX_VQ);
233
+ visit_type_uint32(v, name, &max_vq, &err);
234
+ if (err) {
235
+ error_propagate(errp, err);
236
+ return;
237
}
238
- error_propagate(errp, err);
239
+
240
+ if (kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
241
+ error_setg(errp, "cannot set sve-max-vq");
242
+ error_append_hint(errp, "SVE not supported by KVM on this host\n");
243
+ return;
244
+ }
245
+
246
+ if (max_vq == 0 || max_vq > ARM_MAX_VQ) {
247
+ error_setg(errp, "unsupported SVE vector length");
248
+ error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n",
249
+ ARM_MAX_VQ);
250
+ return;
251
+ }
252
+
253
+ cpu->sve_max_vq = max_vq;
254
}
255
256
static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name,
257
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name,
258
return;
259
}
260
261
+ if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
262
+ error_setg(errp, "cannot enable %s", name);
263
+ error_append_hint(errp, "SVE not supported by KVM on this host\n");
264
+ return;
265
+ }
266
+
267
if (value) {
268
set_bit(vq - 1, cpu->sve_vq_map);
269
} else {
270
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
271
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
272
cpu->dcz_blocksize = 7; /* 512 bytes */
273
#endif
274
-
275
- object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
276
- cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
277
-
278
- for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
279
- char name[8];
280
- sprintf(name, "sve%d", vq * 128);
281
- object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
282
- cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
283
- }
284
}
285
286
object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
287
cpu_arm_set_sve, NULL, NULL, &error_fatal);
288
+ object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
289
+ cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
290
+
291
+ for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
292
+ char name[8];
293
+ sprintf(name, "sve%d", vq * 128);
294
+ object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
295
+ cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
296
+ }
297
}
298
299
struct ARMCPUInfo {
300
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
301
index XXXXXXX..XXXXXXX 100644
302
--- a/target/arm/kvm64.c
303
+++ b/target/arm/kvm64.c
304
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_sve_supported(CPUState *cpu)
305
return kvm_check_extension(s, KVM_CAP_ARM_SVE);
306
}
307
308
+QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1);
309
+
310
+void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map)
311
+{
312
+ /* Only call this function if kvm_arm_sve_supported() returns true. */
313
+ static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS];
314
+ static bool probed;
315
+ uint32_t vq = 0;
316
+ int i, j;
317
+
318
+ bitmap_clear(map, 0, ARM_MAX_VQ);
319
+
320
+ /*
321
+ * KVM ensures all host CPUs support the same set of vector lengths.
322
+ * So we only need to create the scratch VCPUs once and then cache
323
+ * the results.
324
+ */
325
+ if (!probed) {
326
+ struct kvm_vcpu_init init = {
327
+ .target = -1,
328
+ .features[0] = (1 << KVM_ARM_VCPU_SVE),
329
+ };
330
+ struct kvm_one_reg reg = {
331
+ .id = KVM_REG_ARM64_SVE_VLS,
332
+ .addr = (uint64_t)&vls[0],
333
+ };
334
+ int fdarray[3], ret;
335
+
336
+ probed = true;
337
+
338
+ if (!kvm_arm_create_scratch_host_vcpu(NULL, fdarray, &init)) {
339
+ error_report("failed to create scratch VCPU with SVE enabled");
340
+ abort();
341
+ }
342
+ ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &reg);
343
+ kvm_arm_destroy_scratch_host_vcpu(fdarray);
344
+ if (ret) {
345
+ error_report("failed to get KVM_REG_ARM64_SVE_VLS: %s",
346
+ strerror(errno));
347
+ abort();
348
+ }
349
+
350
+ for (i = KVM_ARM64_SVE_VLS_WORDS - 1; i >= 0; --i) {
351
+ if (vls[i]) {
352
+ vq = 64 - clz64(vls[i]) + i * 64;
353
+ break;
354
+ }
355
+ }
356
+ if (vq > ARM_MAX_VQ) {
357
+ warn_report("KVM supports vector lengths larger than "
358
+ "QEMU can enable");
359
+ }
360
+ }
361
+
362
+ for (i = 0; i < KVM_ARM64_SVE_VLS_WORDS; ++i) {
363
+ if (!vls[i]) {
364
+ continue;
365
+ }
366
+ for (j = 1; j <= 64; ++j) {
367
+ vq = j + i * 64;
368
+ if (vq > ARM_MAX_VQ) {
369
+ return;
370
+ }
371
+ if (vls[i] & (1UL << (j - 1))) {
372
+ set_bit(vq - 1, map);
373
+ }
374
+ }
375
+ }
376
+}
72
+}
377
+
73
+
378
+static int kvm_arm_sve_set_vls(CPUState *cs)
74
static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
75
unsigned size)
76
{
77
AwSdHostState *s = AW_SDHOST(opaque);
78
+ AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s);
79
uint32_t res = 0;
80
81
switch (offset) {
82
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
83
case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
84
res = s->dmac_irq;
85
break;
86
- case REG_SD_THLDC: /* Card Threshold Control */
87
- res = s->card_threshold;
88
+ case REG_SD_THLDC: /* Card Threshold Control or FIFO register (sun4i) */
89
+ if (sc->is_sun4i) {
90
+ res = allwinner_sdhost_fifo_read(s);
91
+ } else {
92
+ res = s->card_threshold;
93
+ }
94
break;
95
case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
96
res = s->startbit_detect;
97
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
98
res = s->status_crc;
99
break;
100
case REG_SD_FIFO: /* Read/Write FIFO */
101
- if (sdbus_data_ready(&s->sdbus)) {
102
- sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t));
103
- le32_to_cpus(&res);
104
- allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
105
- allwinner_sdhost_auto_stop(s);
106
- allwinner_sdhost_update_irq(s);
107
- } else {
108
- qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
109
- __func__);
110
- }
111
+ res = allwinner_sdhost_fifo_read(s);
112
break;
113
default:
114
qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
115
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
116
return res;
117
}
118
119
+static void allwinner_sdhost_fifo_write(AwSdHostState *s, uint64_t value)
379
+{
120
+{
380
+ uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = {0};
121
+ uint32_t u32 = cpu_to_le32(value);
381
+ struct kvm_one_reg reg = {
122
+ sdbus_write_data(&s->sdbus, &u32, sizeof(u32));
382
+ .id = KVM_REG_ARM64_SVE_VLS,
123
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(u32));
383
+ .addr = (uint64_t)&vls[0],
124
+ allwinner_sdhost_auto_stop(s);
384
+ };
125
+ allwinner_sdhost_update_irq(s);
385
+ ARMCPU *cpu = ARM_CPU(cs);
386
+ uint32_t vq;
387
+ int i, j;
388
+
389
+ assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX);
390
+
391
+ for (vq = 1; vq <= cpu->sve_max_vq; ++vq) {
392
+ if (test_bit(vq - 1, cpu->sve_vq_map)) {
393
+ i = (vq - 1) / 64;
394
+ j = (vq - 1) % 64;
395
+ vls[i] |= 1UL << j;
396
+ }
397
+ }
398
+
399
+ return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
400
+}
126
+}
401
+
127
+
402
#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
128
static void allwinner_sdhost_write(void *opaque, hwaddr offset,
403
129
uint64_t value, unsigned size)
404
int kvm_arch_init_vcpu(CPUState *cs)
130
{
405
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
131
AwSdHostState *s = AW_SDHOST(opaque);
406
132
- uint32_t u32;
407
if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
133
+ AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s);
408
!object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
134
409
- fprintf(stderr, "KVM is not supported for this guest CPU type\n");
135
trace_allwinner_sdhost_write(offset, value, size);
410
+ error_report("KVM is not supported for this guest CPU type");
136
411
return -EINVAL;
137
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_write(void *opaque, hwaddr offset,
412
}
138
s->dmac_irq = value;
413
139
allwinner_sdhost_update_irq(s);
414
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
140
break;
415
}
141
- case REG_SD_THLDC: /* Card Threshold Control */
416
142
- s->card_threshold = value;
417
if (cpu_isar_feature(aa64_sve, cpu)) {
143
+ case REG_SD_THLDC: /* Card Threshold Control or FIFO (sun4i) */
418
+ ret = kvm_arm_sve_set_vls(cs);
144
+ if (sc->is_sun4i) {
419
+ if (ret) {
145
+ allwinner_sdhost_fifo_write(s, value);
420
+ return ret;
146
+ } else {
147
+ s->card_threshold = value;
421
+ }
148
+ }
422
ret = kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE);
149
break;
423
if (ret) {
150
case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
424
return ret;
151
s->startbit_detect = value;
425
diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
152
break;
426
index XXXXXXX..XXXXXXX 100644
153
case REG_SD_FIFO: /* Read/Write FIFO */
427
--- a/tests/arm-cpu-features.c
154
- u32 = cpu_to_le32(value);
428
+++ b/tests/arm-cpu-features.c
155
- sdbus_write_data(&s->sdbus, &u32, sizeof(u32));
429
@@ -XXX,XX +XXX,XX @@ static QDict *resp_get_props(QDict *resp)
156
- allwinner_sdhost_update_transfer_cnt(s, sizeof(u32));
430
return qdict;
157
- allwinner_sdhost_auto_stop(s);
158
- allwinner_sdhost_update_irq(s);
159
+ allwinner_sdhost_fifo_write(s, value);
160
break;
161
case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
162
case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
163
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
164
{
165
AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
166
sc->max_desc_size = 8 * KiB;
167
+ sc->is_sun4i = true;
431
}
168
}
432
169
433
+static bool resp_get_feature(QDict *resp, const char *feature)
170
static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
434
+{
171
{
435
+ QDict *props;
172
AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
436
+
173
sc->max_desc_size = 64 * KiB;
437
+ g_assert(resp);
174
+ sc->is_sun4i = false;
438
+ g_assert(resp_has_props(resp));
439
+ props = resp_get_props(resp);
440
+ g_assert(qdict_get(props, feature));
441
+ return qdict_get_bool(props, feature);
442
+}
443
+
444
#define assert_has_feature(qts, cpu_type, feature) \
445
({ \
446
QDict *_resp = do_query_no_props(qts, cpu_type); \
447
@@ -XXX,XX +XXX,XX @@ static void sve_tests_sve_off(const void *data)
448
qtest_quit(qts);
449
}
175
}
450
176
451
+static void sve_tests_sve_off_kvm(const void *data)
177
static const TypeInfo allwinner_sdhost_info = {
452
+{
453
+ QTestState *qts;
454
+
455
+ qts = qtest_init(MACHINE_KVM "-cpu max,sve=off");
456
+
457
+ /*
458
+ * We don't know if this host supports SVE so we don't
459
+ * attempt to test enabling anything. We only test that
460
+ * everything is disabled (as it should be with sve=off)
461
+ * and that using sve<N>=off to explicitly disable vector
462
+ * lengths is OK too.
463
+ */
464
+ assert_sve_vls(qts, "max", 0, NULL);
465
+ assert_sve_vls(qts, "max", 0, "{ 'sve128': false }");
466
+
467
+ qtest_quit(qts);
468
+}
469
+
470
static void test_query_cpu_model_expansion(const void *data)
471
{
472
QTestState *qts;
473
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
474
}
475
476
if (g_str_equal(qtest_get_arch(), "aarch64")) {
477
+ bool kvm_supports_sve;
478
+ char max_name[8], name[8];
479
+ uint32_t max_vq, vq;
480
+ uint64_t vls;
481
+ QDict *resp;
482
+ char *error;
483
+
484
assert_has_feature(qts, "host", "aarch64");
485
assert_has_feature(qts, "host", "pmu");
486
487
- assert_has_feature(qts, "max", "sve");
488
-
489
assert_error(qts, "cortex-a15",
490
"We cannot guarantee the CPU type 'cortex-a15' works "
491
"with KVM on this host", NULL);
492
+
493
+ assert_has_feature(qts, "max", "sve");
494
+ resp = do_query_no_props(qts, "max");
495
+ kvm_supports_sve = resp_get_feature(resp, "sve");
496
+ vls = resp_get_sve_vls(resp);
497
+ qobject_unref(resp);
498
+
499
+ if (kvm_supports_sve) {
500
+ g_assert(vls != 0);
501
+ max_vq = 64 - __builtin_clzll(vls);
502
+ sprintf(max_name, "sve%d", max_vq * 128);
503
+
504
+ /* Enabling a supported length is of course fine. */
505
+ assert_sve_vls(qts, "max", vls, "{ %s: true }", max_name);
506
+
507
+ /* Get the next supported length smaller than max-vq. */
508
+ vq = 64 - __builtin_clzll(vls & ~BIT_ULL(max_vq - 1));
509
+ if (vq) {
510
+ /*
511
+ * We have at least one length smaller than max-vq,
512
+ * so we can disable max-vq.
513
+ */
514
+ assert_sve_vls(qts, "max", (vls & ~BIT_ULL(max_vq - 1)),
515
+ "{ %s: false }", max_name);
516
+
517
+ /*
518
+ * Smaller, supported vector lengths cannot be disabled
519
+ * unless all larger, supported vector lengths are also
520
+ * disabled.
521
+ */
522
+ sprintf(name, "sve%d", vq * 128);
523
+ error = g_strdup_printf("cannot disable %s", name);
524
+ assert_error(qts, "max", error,
525
+ "{ %s: true, %s: false }",
526
+ max_name, name);
527
+ g_free(error);
528
+ }
529
+
530
+ /*
531
+ * The smallest, supported vector length is required, because
532
+ * we need at least one vector length enabled.
533
+ */
534
+ vq = __builtin_ffsll(vls);
535
+ sprintf(name, "sve%d", vq * 128);
536
+ error = g_strdup_printf("cannot disable %s", name);
537
+ assert_error(qts, "max", error, "{ %s: false }", name);
538
+ g_free(error);
539
+
540
+ /* Get an unsupported length. */
541
+ for (vq = 1; vq <= max_vq; ++vq) {
542
+ if (!(vls & BIT_ULL(vq - 1))) {
543
+ break;
544
+ }
545
+ }
546
+ if (vq <= SVE_MAX_VQ) {
547
+ sprintf(name, "sve%d", vq * 128);
548
+ error = g_strdup_printf("cannot enable %s", name);
549
+ assert_error(qts, "max", error, "{ %s: true }", name);
550
+ g_free(error);
551
+ }
552
+ } else {
553
+ g_assert(vls == 0);
554
+ }
555
} else {
556
assert_has_not_feature(qts, "host", "aarch64");
557
assert_has_not_feature(qts, "host", "pmu");
558
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
559
NULL, sve_tests_sve_max_vq_8);
560
qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
561
NULL, sve_tests_sve_off);
562
+ qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
563
+ NULL, sve_tests_sve_off_kvm);
564
}
565
566
return g_test_run();
567
diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
568
index XXXXXXX..XXXXXXX 100644
569
--- a/docs/arm-cpu-features.rst
570
+++ b/docs/arm-cpu-features.rst
571
@@ -XXX,XX +XXX,XX @@ SVE CPU Property Dependencies and Constraints
572
573
1) At least one vector length must be enabled when `sve` is enabled.
574
575
- 2) If a vector length `N` is enabled, then all power-of-two vector
576
- lengths smaller than `N` must also be enabled. E.g. if `sve512`
577
- is enabled, then the 128-bit and 256-bit vector lengths must also
578
- be enabled.
579
+ 2) If a vector length `N` is enabled, then, when KVM is enabled, all
580
+ smaller, host supported vector lengths must also be enabled. If
581
+ KVM is not enabled, then only all the smaller, power-of-two vector
582
+ lengths must be enabled. E.g. with KVM if the host supports all
583
+ vector lengths up to 512-bits (128, 256, 384, 512), then if `sve512`
584
+ is enabled, the 128-bit vector length, 256-bit vector length, and
585
+ 384-bit vector length must also be enabled. Without KVM, the 384-bit
586
+ vector length would not be required.
587
+
588
+ 3) If KVM is enabled then only vector lengths that the host CPU type
589
+ support may be enabled. If SVE is not supported by the host, then
590
+ no `sve*` properties may be enabled.
591
592
SVE CPU Property Parsing Semantics
593
----------------------------------
594
@@ -XXX,XX +XXX,XX @@ SVE CPU Property Parsing Semantics
595
an error is generated.
596
597
2) If SVE is enabled (`sve=on`), but no `sve<N>` CPU properties are
598
- provided, then all supported vector lengths are enabled, including
599
- the non-power-of-two lengths.
600
+ provided, then all supported vector lengths are enabled, which when
601
+ KVM is not in use means including the non-power-of-two lengths, and,
602
+ when KVM is in use, it means all vector lengths supported by the host
603
+ processor.
604
605
3) If SVE is enabled, then an error is generated when attempting to
606
disable the last enabled vector length (see constraint (1) of "SVE
607
@@ -XXX,XX +XXX,XX @@ SVE CPU Property Parsing Semantics
608
has been explicitly disabled, then an error is generated (see
609
constraint (2) of "SVE CPU Property Dependencies and Constraints").
610
611
- 5) If one or more `sve<N>` CPU properties are set `off`, but no `sve<N>`,
612
+ 5) When KVM is enabled, if the host does not support SVE, then an error
613
+ is generated when attempting to enable any `sve*` properties (see
614
+ constraint (3) of "SVE CPU Property Dependencies and Constraints").
615
+
616
+ 6) When KVM is enabled, if the host does support SVE, then an error is
617
+ generated when attempting to enable any vector lengths not supported
618
+ by the host (see constraint (3) of "SVE CPU Property Dependencies and
619
+ Constraints").
620
+
621
+ 7) If one or more `sve<N>` CPU properties are set `off`, but no `sve<N>`,
622
CPU properties are set `on`, then the specified vector lengths are
623
disabled but the default for any unspecified lengths remains enabled.
624
- Disabling a power-of-two vector length also disables all vector
625
- lengths larger than the power-of-two length (see constraint (2) of
626
- "SVE CPU Property Dependencies and Constraints").
627
+ When KVM is not enabled, disabling a power-of-two vector length also
628
+ disables all vector lengths larger than the power-of-two length.
629
+ When KVM is enabled, then disabling any supported vector length also
630
+ disables all larger vector lengths (see constraint (2) of "SVE CPU
631
+ Property Dependencies and Constraints").
632
633
- 6) If one or more `sve<N>` CPU properties are set to `on`, then they
634
+ 8) If one or more `sve<N>` CPU properties are set to `on`, then they
635
are enabled and all unspecified lengths default to disabled, except
636
for the required lengths per constraint (2) of "SVE CPU Property
637
Dependencies and Constraints", which will even be auto-enabled if
638
they were not explicitly enabled.
639
640
- 7) If SVE was disabled (`sve=off`), allowing all vector lengths to be
641
+ 9) If SVE was disabled (`sve=off`), allowing all vector lengths to be
642
explicitly disabled (i.e. avoiding the error specified in (3) of
643
"SVE CPU Property Parsing Semantics"), then if later an `sve=on` is
644
provided an error will be generated. To avoid this error, one must
645
--
178
--
646
2.20.1
179
2.25.1
647
648
diff view generated by jsdifflib
[PULL 10/11] hw/arm/boot: Rebuild hflags when modifying CPUState at boot
[PULL 2/5] hw/intc: clean-up access to GIC multi-byte registers
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
Rebuild hflags when modifying CPUState at boot.
3
gic_dist_readb was returning a word value which just happened to work
4
as a result of the way we OR the data together. Lets fix it so only
5
the explicit byte is returned for each part of GICD_TYPER. I've
6
changed the return type to uint8_t although the overflow is only
7
detected with an explicit -Wconversion.
4
8
5
Fixes: e979972a6a
9
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
10
Message-id: 20191031040830.18800-2-edgar.iglesias@xilinx.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
14
---
13
hw/arm/boot.c | 1 +
15
hw/intc/arm_gic.c | 16 ++++++++++------
14
1 file changed, 1 insertion(+)
16
1 file changed, 10 insertions(+), 6 deletions(-)
15
17
16
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
18
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
17
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/boot.c
20
--- a/hw/intc/arm_gic.c
19
+++ b/hw/arm/boot.c
21
+++ b/hw/intc/arm_gic.c
20
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
22
@@ -XXX,XX +XXX,XX @@ static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
21
info->secondary_cpu_reset_hook(cpu, info);
23
gic_update(s);
24
}
25
26
-static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
27
+static uint8_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
28
{
29
GICState *s = (GICState *)opaque;
30
uint32_t res;
31
@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
32
cm = 1 << cpu;
33
if (offset < 0x100) {
34
if (offset == 0) { /* GICD_CTLR */
35
+ /* We rely here on the only non-zero bits being in byte 0 */
36
if (s->security_extn && !attrs.secure) {
37
/* The NS bank of this register is just an alias of the
38
* EnableGrp1 bit in the S bank version.
39
@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
40
return s->ctlr;
22
}
41
}
23
}
42
}
24
+ arm_rebuild_hflags(env);
43
- if (offset == 4)
25
}
44
- /* Interrupt Controller Type Register */
26
}
45
- return ((s->num_irq / 32) - 1)
27
46
- | ((s->num_cpu - 1) << 5)
47
- | (s->security_extn << 10);
48
+ if (offset == 4) {
49
+ /* GICD_TYPER byte 0 */
50
+ return ((s->num_irq / 32) - 1) | ((s->num_cpu - 1) << 5);
51
+ }
52
+ if (offset == 5) {
53
+ /* GICD_TYPER byte 1 */
54
+ return (s->security_extn << 2);
55
+ }
56
if (offset < 0x08)
57
return 0;
58
if (offset >= 0x80) {
28
--
59
--
29
2.20.1
60
2.25.1
30
61
31
62
diff view generated by jsdifflib
[PULL 11/11] target/arm: Allow reading flags from FPSCR for M-profile
[PULL 3/5] hw/intc: add implementation of GICD_IIDR to Arm GIC
1
From: Christophe Lyon <christophe.lyon@linaro.org>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
rt==15 is a special case when reading the flags: it means the
3
a66a24585f (hw/intc/arm_gic: Implement read of GICC_IIDR) implemented
4
destination is APSR. This patch avoids rejecting
4
this for the CPU interface register. The fact we don't implement it
5
vmrs apsr_nzcv, fpscr
5
shows up when running Xen with -d guest_error which is definitely
6
as illegal instruction.
6
wrong because the guest is perfectly entitled to read it.
7
7
8
Cc: qemu-stable@nongnu.org
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Christophe Lyon <christophe.lyon@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-id: 20191025095711.10853-1-christophe.lyon@linaro.org
11
[PMM: updated the comment]
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
12
---
15
target/arm/translate-vfp.inc.c | 5 +++--
13
hw/intc/arm_gic.c | 12 +++++++++++-
16
1 file changed, 3 insertions(+), 2 deletions(-)
14
1 file changed, 11 insertions(+), 1 deletion(-)
17
15
18
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
16
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
19
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate-vfp.inc.c
18
--- a/hw/intc/arm_gic.c
21
+++ b/target/arm/translate-vfp.inc.c
19
+++ b/hw/intc/arm_gic.c
22
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
20
@@ -XXX,XX +XXX,XX @@ static uint8_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
23
if (arm_dc_feature(s, ARM_FEATURE_M)) {
21
/* GICD_TYPER byte 1 */
24
/*
22
return (s->security_extn << 2);
25
* The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
26
- * Writes to R15 are UNPREDICTABLE; we choose to undef.
27
+ * Accesses to R15 are UNPREDICTABLE; we choose to undef.
28
+ * (FPSCR -> r15 is a special case which writes to the PSR flags.)
29
*/
30
- if (a->rt == 15 || a->reg != ARM_VFP_FPSCR) {
31
+ if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) {
32
return false;
33
}
23
}
34
}
24
- if (offset < 0x08)
25
+ if (offset == 8) {
26
+ /* GICD_IIDR byte 0 */
27
+ return 0x3b; /* Arm JEP106 identity */
28
+ }
29
+ if (offset == 9) {
30
+ /* GICD_IIDR byte 1 */
31
+ return 0x04; /* Arm JEP106 identity */
32
+ }
33
+ if (offset < 0x0c) {
34
+ /* All other bytes in this range are RAZ */
35
return 0;
36
+ }
37
if (offset >= 0x80) {
38
/* Interrupt Group Registers: these RAZ/WI if this is an NS
39
* access to a GIC with the security extensions, or if the GIC
35
--
40
--
36
2.20.1
41
2.25.1
37
42
38
43
diff view generated by jsdifflib
[PULL 09/11] target/arm/kvm: host cpu: Add support for sve<N> properties
[PULL 4/5] tests/avocado/boot_linux.py: Bump aarch64 virt test timeout to 720s
1
From: Andrew Jones <drjones@redhat.com>
1
The two tests
2
tests/avocado/boot_linux.py:BootLinuxAarch64.test_virt_tcg_gicv2
3
tests/avocado/boot_linux.py:BootLinuxAarch64.test_virt_tcg_gicv3
2
4
3
Allow cpu 'host' to enable SVE when it's available, unless the
5
take quite a long time to run, and the current timeout of 240s
4
user chooses to disable it with the added 'sve=off' cpu property.
6
is not enough for the tests to complete on slow machines:
5
Also give the user the ability to select vector lengths with the
7
we've seen these tests time out in the gitlab CI in the
6
sve<N> properties. We don't adopt 'max' cpu's other sve property,
8
'avocado-system-alpine' CI job, for instance. The timeout
7
sve-max-vq, because that property is difficult to use with KVM.
9
is also insufficient for running the test with a debug build
8
That property assumes all vector lengths in the range from 1 up
10
of QEMU: on my machine the tests take over 10 minutes to run
9
to and including the specified maximum length are supported, but
11
in that config.
10
there may be optional lengths not supported by the host in that
11
range. With KVM one must be more specific when enabling vector
12
lengths.
13
12
14
Signed-off-by: Andrew Jones <drjones@redhat.com>
13
Push the timeout up to 720s so that the test definitely has
15
Reviewed-by: Eric Auger <eric.auger@redhat.com>
14
enough time to complete.
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
17
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
18
Message-id: 20191031142734.8590-10-drjones@redhat.com
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Thomas Huth <thuth@redhat.com>
18
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
20
---
19
---
21
target/arm/cpu.h | 2 ++
20
tests/avocado/boot_linux.py | 2 +-
22
target/arm/cpu.c | 3 +++
21
1 file changed, 1 insertion(+), 1 deletion(-)
23
target/arm/cpu64.c | 33 +++++++++++++++++----------------
24
target/arm/kvm64.c | 14 +++++++++++++-
25
tests/arm-cpu-features.c | 17 ++++++++---------
26
docs/arm-cpu-features.rst | 19 ++++++++++++-------
27
6 files changed, 55 insertions(+), 33 deletions(-)
28
22
29
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
23
diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
30
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/cpu.h
25
--- a/tests/avocado/boot_linux.py
32
+++ b/target/arm/cpu.h
26
+++ b/tests/avocado/boot_linux.py
33
@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
27
@@ -XXX,XX +XXX,XX @@ class BootLinuxAarch64(LinuxTest):
34
void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
28
:avocado: tags=machine:virt
35
void aarch64_sve_change_el(CPUARMState *env, int old_el,
29
:avocado: tags=machine:gic-version=2
36
int new_el, bool el0_a64);
30
"""
37
+void aarch64_add_sve_properties(Object *obj);
31
- timeout = 240
38
#else
32
+ timeout = 720
39
static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
33
40
static inline void aarch64_sve_change_el(CPUARMState *env, int o,
34
def add_common_args(self):
41
int n, bool a)
35
self.vm.add_args('-bios',
42
{ }
43
+static inline void aarch64_add_sve_properties(Object *obj) { }
44
#endif
45
46
#if !defined(CONFIG_TCG)
47
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/cpu.c
50
+++ b/target/arm/cpu.c
51
@@ -XXX,XX +XXX,XX @@ static void arm_host_initfn(Object *obj)
52
ARMCPU *cpu = ARM_CPU(obj);
53
54
kvm_arm_set_cpu_features_from_host(cpu);
55
+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
56
+ aarch64_add_sve_properties(obj);
57
+ }
58
arm_cpu_post_init(obj);
59
}
60
61
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/target/arm/cpu64.c
64
+++ b/target/arm/cpu64.c
65
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
66
cpu->isar.id_aa64pfr0 = t;
67
}
68
69
+void aarch64_add_sve_properties(Object *obj)
70
+{
71
+ uint32_t vq;
72
+
73
+ object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
74
+ cpu_arm_set_sve, NULL, NULL, &error_fatal);
75
+
76
+ for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
77
+ char name[8];
78
+ sprintf(name, "sve%d", vq * 128);
79
+ object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
80
+ cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
81
+ }
82
+}
83
+
84
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
85
* otherwise, a CPU with as many features enabled as our emulation supports.
86
* The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
87
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
88
static void aarch64_max_initfn(Object *obj)
89
{
90
ARMCPU *cpu = ARM_CPU(obj);
91
- uint32_t vq;
92
- uint64_t t;
93
94
if (kvm_enabled()) {
95
kvm_arm_set_cpu_features_from_host(cpu);
96
- if (kvm_arm_sve_supported(CPU(cpu))) {
97
- t = cpu->isar.id_aa64pfr0;
98
- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
99
- cpu->isar.id_aa64pfr0 = t;
100
- }
101
} else {
102
+ uint64_t t;
103
uint32_t u;
104
aarch64_a57_initfn(obj);
105
106
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
107
#endif
108
}
109
110
- object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
111
- cpu_arm_set_sve, NULL, NULL, &error_fatal);
112
+ aarch64_add_sve_properties(obj);
113
object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
114
cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
115
-
116
- for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
117
- char name[8];
118
- sprintf(name, "sve%d", vq * 128);
119
- object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
120
- cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
121
- }
122
}
123
124
struct ARMCPUInfo {
125
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
126
index XXXXXXX..XXXXXXX 100644
127
--- a/target/arm/kvm64.c
128
+++ b/target/arm/kvm64.c
129
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
130
* and then query that CPU for the relevant ID registers.
131
*/
132
int fdarray[3];
133
+ bool sve_supported;
134
uint64_t features = 0;
135
+ uint64_t t;
136
int err;
137
138
/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
139
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
140
ARM64_SYS_REG(3, 0, 0, 3, 2));
141
}
142
143
+ sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
144
+
145
kvm_arm_destroy_scratch_host_vcpu(fdarray);
146
147
if (err < 0) {
148
return false;
149
}
150
151
- /* We can assume any KVM supporting CPU is at least a v8
152
+ /* Add feature bits that can't appear until after VCPU init. */
153
+ if (sve_supported) {
154
+ t = ahcf->isar.id_aa64pfr0;
155
+ t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
156
+ ahcf->isar.id_aa64pfr0 = t;
157
+ }
158
+
159
+ /*
160
+ * We can assume any KVM supporting CPU is at least a v8
161
* with VFPv4+Neon; this in turn implies most of the other
162
* feature bits.
163
*/
164
diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
165
index XXXXXXX..XXXXXXX 100644
166
--- a/tests/arm-cpu-features.c
167
+++ b/tests/arm-cpu-features.c
168
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
169
"We cannot guarantee the CPU type 'cortex-a15' works "
170
"with KVM on this host", NULL);
171
172
- assert_has_feature(qts, "max", "sve");
173
- resp = do_query_no_props(qts, "max");
174
+ assert_has_feature(qts, "host", "sve");
175
+ resp = do_query_no_props(qts, "host");
176
kvm_supports_sve = resp_get_feature(resp, "sve");
177
vls = resp_get_sve_vls(resp);
178
qobject_unref(resp);
179
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
180
sprintf(max_name, "sve%d", max_vq * 128);
181
182
/* Enabling a supported length is of course fine. */
183
- assert_sve_vls(qts, "max", vls, "{ %s: true }", max_name);
184
+ assert_sve_vls(qts, "host", vls, "{ %s: true }", max_name);
185
186
/* Get the next supported length smaller than max-vq. */
187
vq = 64 - __builtin_clzll(vls & ~BIT_ULL(max_vq - 1));
188
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
189
* We have at least one length smaller than max-vq,
190
* so we can disable max-vq.
191
*/
192
- assert_sve_vls(qts, "max", (vls & ~BIT_ULL(max_vq - 1)),
193
+ assert_sve_vls(qts, "host", (vls & ~BIT_ULL(max_vq - 1)),
194
"{ %s: false }", max_name);
195
196
/*
197
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
198
*/
199
sprintf(name, "sve%d", vq * 128);
200
error = g_strdup_printf("cannot disable %s", name);
201
- assert_error(qts, "max", error,
202
+ assert_error(qts, "host", error,
203
"{ %s: true, %s: false }",
204
max_name, name);
205
g_free(error);
206
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
207
vq = __builtin_ffsll(vls);
208
sprintf(name, "sve%d", vq * 128);
209
error = g_strdup_printf("cannot disable %s", name);
210
- assert_error(qts, "max", error, "{ %s: false }", name);
211
+ assert_error(qts, "host", error, "{ %s: false }", name);
212
g_free(error);
213
214
/* Get an unsupported length. */
215
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
216
if (vq <= SVE_MAX_VQ) {
217
sprintf(name, "sve%d", vq * 128);
218
error = g_strdup_printf("cannot enable %s", name);
219
- assert_error(qts, "max", error, "{ %s: true }", name);
220
+ assert_error(qts, "host", error, "{ %s: true }", name);
221
g_free(error);
222
}
223
} else {
224
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
225
} else {
226
assert_has_not_feature(qts, "host", "aarch64");
227
assert_has_not_feature(qts, "host", "pmu");
228
-
229
- assert_has_not_feature(qts, "max", "sve");
230
+ assert_has_not_feature(qts, "host", "sve");
231
}
232
233
qtest_quit(qts);
234
diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
235
index XXXXXXX..XXXXXXX 100644
236
--- a/docs/arm-cpu-features.rst
237
+++ b/docs/arm-cpu-features.rst
238
@@ -XXX,XX +XXX,XX @@ SVE CPU Property Examples
239
240
$ qemu-system-aarch64 -M virt -cpu max
241
242
- 3) Only enable the 128-bit vector length::
243
+ 3) When KVM is enabled, implicitly enable all host CPU supported vector
244
+ lengths with the `host` CPU type::
245
+
246
+ $ qemu-system-aarch64 -M virt,accel=kvm -cpu host
247
+
248
+ 4) Only enable the 128-bit vector length::
249
250
$ qemu-system-aarch64 -M virt -cpu max,sve128=on
251
252
- 4) Disable the 512-bit vector length and all larger vector lengths,
253
+ 5) Disable the 512-bit vector length and all larger vector lengths,
254
since 512 is a power-of-two. This results in all the smaller,
255
uninitialized lengths (128, 256, and 384) defaulting to enabled::
256
257
$ qemu-system-aarch64 -M virt -cpu max,sve512=off
258
259
- 5) Enable the 128-bit, 256-bit, and 512-bit vector lengths::
260
+ 6) Enable the 128-bit, 256-bit, and 512-bit vector lengths::
261
262
$ qemu-system-aarch64 -M virt -cpu max,sve128=on,sve256=on,sve512=on
263
264
- 6) The same as (5), but since the 128-bit and 256-bit vector
265
+ 7) The same as (6), but since the 128-bit and 256-bit vector
266
lengths are required for the 512-bit vector length to be enabled,
267
then allow them to be auto-enabled::
268
269
$ qemu-system-aarch64 -M virt -cpu max,sve512=on
270
271
- 7) Do the same as (6), but by first disabling SVE and then re-enabling it::
272
+ 8) Do the same as (7), but by first disabling SVE and then re-enabling it::
273
274
$ qemu-system-aarch64 -M virt -cpu max,sve=off,sve512=on,sve=on
275
276
- 8) Force errors regarding the last vector length::
277
+ 9) Force errors regarding the last vector length::
278
279
$ qemu-system-aarch64 -M virt -cpu max,sve128=off
280
$ qemu-system-aarch64 -M virt -cpu max,sve=off,sve128=off,sve=on
281
@@ -XXX,XX +XXX,XX @@ The examples in "SVE CPU Property Examples" exhibit many ways to select
282
vector lengths which developers may find useful in order to avoid overly
283
verbose command lines. However, the recommended way to select vector
284
lengths is to explicitly enable each desired length. Therefore only
285
-example's (1), (3), and (5) exhibit recommended uses of the properties.
286
+example's (1), (4), and (6) exhibit recommended uses of the properties.
287
288
--
36
--
289
2.20.1
37
2.25.1
290
38
291
39
diff view generated by jsdifflib
[PULL 06/11] target/arm/kvm64: max cpu: Enable SVE when available
[PULL 5/5] target/arm: Limit LPA2 effective output address when TCR.DS == 0
1
From: Andrew Jones <drjones@redhat.com>
1
From: Ard Biesheuvel <ardb@kernel.org>
2
2
3
Enable SVE in the KVM guest when the 'max' cpu type is configured
3
With LPA2, the effective output address size is at most 48 bits when
4
and KVM supports it. KVM SVE requires use of the new finalize
4
TCR.DS == 0. This case is currently unhandled in the page table walker,
5
vcpu ioctl, so we add that now too. For starters SVE can only be
5
where we happily assume LVA/64k granule when outputsize > 48 and
6
turned on or off, getting all vector lengths the host CPU supports
6
param.ds == 0, resulting in the wrong conversion to be used from a
7
when on. We'll add the other SVE CPU properties in later patches.
7
page table descriptor to a physical address.
8
8
9
Signed-off-by: Andrew Jones <drjones@redhat.com>
9
if (outputsize > 48) {
10
if (param.ds) {
11
descaddr |= extract64(descriptor, 8, 2) << 50;
12
} else {
13
descaddr |= extract64(descriptor, 12, 4) << 48;
14
}
15
16
So cap the outputsize to 48 when TCR.DS is cleared, as per the
17
architecture.
18
19
Cc: Peter Maydell <peter.maydell@linaro.org>
20
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
21
Cc: Richard Henderson <richard.henderson@linaro.org>
22
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
24
Message-id: 20221116170316.259695-1-ardb@kernel.org
12
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
13
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
14
Message-id: 20191031142734.8590-7-drjones@redhat.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
26
---
17
target/arm/kvm_arm.h | 27 +++++++++++++++++++++++++++
27
target/arm/ptw.c | 8 ++++++++
18
target/arm/cpu64.c | 17 ++++++++++++++---
28
1 file changed, 8 insertions(+)
19
target/arm/kvm.c | 5 +++++
20
target/arm/kvm64.c | 20 +++++++++++++++++++-
21
tests/arm-cpu-features.c | 4 ++++
22
5 files changed, 69 insertions(+), 4 deletions(-)
23
29
24
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
30
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
25
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/kvm_arm.h
32
--- a/target/arm/ptw.c
27
+++ b/target/arm/kvm_arm.h
33
+++ b/target/arm/ptw.c
28
@@ -XXX,XX +XXX,XX @@
34
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
29
*/
35
ps = MIN(ps, param.ps);
30
int kvm_arm_vcpu_init(CPUState *cs);
36
assert(ps < ARRAY_SIZE(pamax_map));
31
37
outputsize = pamax_map[ps];
32
+/**
33
+ * kvm_arm_vcpu_finalize
34
+ * @cs: CPUState
35
+ * @feature: int
36
+ *
37
+ * Finalizes the configuration of the specified VCPU feature by
38
+ * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring
39
+ * this are documented in the "KVM_ARM_VCPU_FINALIZE" section of
40
+ * KVM's API documentation.
41
+ *
42
+ * Returns: 0 if success else < 0 error code
43
+ */
44
+int kvm_arm_vcpu_finalize(CPUState *cs, int feature);
45
+
38
+
46
/**
39
+ /*
47
* kvm_arm_register_device:
40
+ * With LPA2, the effective output address (OA) size is at most 48 bits
48
* @mr: memory region for this device
41
+ * unless TCR.DS == 1
49
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_aarch32_supported(CPUState *cs);
42
+ */
50
*/
43
+ if (!param.ds && param.gran != Gran64K) {
51
bool kvm_arm_pmu_supported(CPUState *cs);
44
+ outputsize = MIN(outputsize, 48);
52
53
+/**
54
+ * bool kvm_arm_sve_supported:
55
+ * @cs: CPUState
56
+ *
57
+ * Returns true if the KVM VCPU can enable SVE and false otherwise.
58
+ */
59
+bool kvm_arm_sve_supported(CPUState *cs);
60
+
61
/**
62
* kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the
63
* IPA address space supported by KVM
64
@@ -XXX,XX +XXX,XX @@ static inline bool kvm_arm_pmu_supported(CPUState *cs)
65
return false;
66
}
67
68
+static inline bool kvm_arm_sve_supported(CPUState *cs)
69
+{
70
+ return false;
71
+}
72
+
73
static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
74
{
75
return -ENOENT;
76
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/cpu64.c
79
+++ b/target/arm/cpu64.c
80
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
81
return;
82
}
83
84
+ if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
85
+ error_setg(errp, "'sve' feature not supported by KVM on this host");
86
+ return;
87
+ }
88
+
89
t = cpu->isar.id_aa64pfr0;
90
t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);
91
cpu->isar.id_aa64pfr0 = t;
92
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
93
{
94
ARMCPU *cpu = ARM_CPU(obj);
95
uint32_t vq;
96
+ uint64_t t;
97
98
if (kvm_enabled()) {
99
kvm_arm_set_cpu_features_from_host(cpu);
100
+ if (kvm_arm_sve_supported(CPU(cpu))) {
101
+ t = cpu->isar.id_aa64pfr0;
102
+ t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
103
+ cpu->isar.id_aa64pfr0 = t;
104
+ }
45
+ }
105
} else {
46
} else {
106
- uint64_t t;
47
param = aa32_va_parameters(env, address, mmu_idx);
107
uint32_t u;
48
level = 1;
108
aarch64_a57_initfn(obj);
109
110
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
111
112
object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
113
cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
114
- object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
115
- cpu_arm_set_sve, NULL, NULL, &error_fatal);
116
117
for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
118
char name[8];
119
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
120
cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
121
}
122
}
123
+
124
+ object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
125
+ cpu_arm_set_sve, NULL, NULL, &error_fatal);
126
}
127
128
struct ARMCPUInfo {
129
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
130
index XXXXXXX..XXXXXXX 100644
131
--- a/target/arm/kvm.c
132
+++ b/target/arm/kvm.c
133
@@ -XXX,XX +XXX,XX @@ int kvm_arm_vcpu_init(CPUState *cs)
134
return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
135
}
136
137
+int kvm_arm_vcpu_finalize(CPUState *cs, int feature)
138
+{
139
+ return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_FINALIZE, &feature);
140
+}
141
+
142
void kvm_arm_init_serror_injection(CPUState *cs)
143
{
144
cap_has_inject_serror_esr = kvm_check_extension(cs->kvm_state,
145
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
146
index XXXXXXX..XXXXXXX 100644
147
--- a/target/arm/kvm64.c
148
+++ b/target/arm/kvm64.c
149
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_aarch32_supported(CPUState *cpu)
150
return kvm_check_extension(s, KVM_CAP_ARM_EL1_32BIT);
151
}
152
153
+bool kvm_arm_sve_supported(CPUState *cpu)
154
+{
155
+ KVMState *s = KVM_STATE(current_machine->accelerator);
156
+
157
+ return kvm_check_extension(s, KVM_CAP_ARM_SVE);
158
+}
159
+
160
#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
161
162
int kvm_arch_init_vcpu(CPUState *cs)
163
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
164
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;
165
}
166
if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) {
167
- cpu->has_pmu = false;
168
+ cpu->has_pmu = false;
169
}
170
if (cpu->has_pmu) {
171
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
172
} else {
173
unset_feature(&env->features, ARM_FEATURE_PMU);
174
}
175
+ if (cpu_isar_feature(aa64_sve, cpu)) {
176
+ assert(kvm_arm_sve_supported(cs));
177
+ cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE;
178
+ }
179
180
/* Do KVM_ARM_VCPU_INIT ioctl */
181
ret = kvm_arm_vcpu_init(cs);
182
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
183
return ret;
184
}
185
186
+ if (cpu_isar_feature(aa64_sve, cpu)) {
187
+ ret = kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE);
188
+ if (ret) {
189
+ return ret;
190
+ }
191
+ }
192
+
193
/*
194
* When KVM is in use, PSCI is emulated in-kernel and not by qemu.
195
* Currently KVM has its own idea about MPIDR assignment, so we
196
diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
197
index XXXXXXX..XXXXXXX 100644
198
--- a/tests/arm-cpu-features.c
199
+++ b/tests/arm-cpu-features.c
200
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
201
assert_has_feature(qts, "host", "aarch64");
202
assert_has_feature(qts, "host", "pmu");
203
204
+ assert_has_feature(qts, "max", "sve");
205
+
206
assert_error(qts, "cortex-a15",
207
"We cannot guarantee the CPU type 'cortex-a15' works "
208
"with KVM on this host", NULL);
209
} else {
210
assert_has_not_feature(qts, "host", "aarch64");
211
assert_has_not_feature(qts, "host", "pmu");
212
+
213
+ assert_has_not_feature(qts, "max", "sve");
214
}
215
216
qtest_quit(qts);
217
--
49
--
218
2.20.1
50
2.25.1
219
51
220
52
diff view generated by jsdifflib
[PULL 07/11] target/arm/kvm: scratch vcpu: Preserve input kvm_vcpu_init features
Deleted patch
1
From: Andrew Jones <drjones@redhat.com>
2
1
3
kvm_arm_create_scratch_host_vcpu() takes a struct kvm_vcpu_init
4
parameter. Rather than just using it as an output parameter to
5
pass back the preferred target, use it also as an input parameter,
6
allowing a caller to pass a selected target if they wish and to
7
also pass cpu features. If the caller doesn't want to select a
8
target they can pass -1 for the target which indicates they want
9
to use the preferred target and have it passed back like before.
10
11
Signed-off-by: Andrew Jones <drjones@redhat.com>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Eric Auger <eric.auger@redhat.com>
14
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
15
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
16
Message-id: 20191031142734.8590-8-drjones@redhat.com
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
target/arm/kvm.c | 20 +++++++++++++++-----
20
target/arm/kvm32.c | 6 +++++-
21
target/arm/kvm64.c | 6 +++++-
22
3 files changed, 25 insertions(+), 7 deletions(-)
23
24
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/kvm.c
27
+++ b/target/arm/kvm.c
28
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
29
int *fdarray,
30
struct kvm_vcpu_init *init)
31
{
32
- int ret, kvmfd = -1, vmfd = -1, cpufd = -1;
33
+ int ret = 0, kvmfd = -1, vmfd = -1, cpufd = -1;
34
35
kvmfd = qemu_open("/dev/kvm", O_RDWR);
36
if (kvmfd < 0) {
37
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
38
goto finish;
39
}
40
41
- ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, init);
42
+ if (init->target == -1) {
43
+ struct kvm_vcpu_init preferred;
44
+
45
+ ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, &preferred);
46
+ if (!ret) {
47
+ init->target = preferred.target;
48
+ }
49
+ }
50
if (ret >= 0) {
51
ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
52
if (ret < 0) {
53
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
54
* creating one kind of guest CPU which is its preferred
55
* CPU type.
56
*/
57
+ struct kvm_vcpu_init try;
58
+
59
while (*cpus_to_try != QEMU_KVM_ARM_TARGET_NONE) {
60
- init->target = *cpus_to_try++;
61
- memset(init->features, 0, sizeof(init->features));
62
- ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
63
+ try.target = *cpus_to_try++;
64
+ memcpy(try.features, init->features, sizeof(init->features));
65
+ ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, &try);
66
if (ret >= 0) {
67
break;
68
}
69
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
70
if (ret < 0) {
71
goto err;
72
}
73
+ init->target = try.target;
74
} else {
75
/* Treat a NULL cpus_to_try argument the same as an empty
76
* list, which means we will fail the call since this must
77
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/target/arm/kvm32.c
80
+++ b/target/arm/kvm32.c
81
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
82
QEMU_KVM_ARM_TARGET_CORTEX_A15,
83
QEMU_KVM_ARM_TARGET_NONE
84
};
85
- struct kvm_vcpu_init init;
86
+ /*
87
+ * target = -1 informs kvm_arm_create_scratch_host_vcpu()
88
+ * to use the preferred target
89
+ */
90
+ struct kvm_vcpu_init init = { .target = -1, };
91
92
if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
93
return false;
94
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
95
index XXXXXXX..XXXXXXX 100644
96
--- a/target/arm/kvm64.c
97
+++ b/target/arm/kvm64.c
98
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
99
KVM_ARM_TARGET_CORTEX_A57,
100
QEMU_KVM_ARM_TARGET_NONE
101
};
102
- struct kvm_vcpu_init init;
103
+ /*
104
+ * target = -1 informs kvm_arm_create_scratch_host_vcpu()
105
+ * to use the preferred target
106
+ */
107
+ struct kvm_vcpu_init init = { .target = -1, };
108
109
if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
110
return false;
111
--
112
2.20.1
113
114
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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