Series comparison

-[PULL v2 00/12] tcg patch queue
+[PULL v2 00/29] tcg patch queue
-V2 fixes a build problem that affected win32.
+v2: Fix FreeBSD build error in patch 18.
 r~
-The following changes since commit 187f35512106501fe9a11057f4d8705431e0026d:
+The following changes since commit 0d239e513e0117e66fa739fb71a43b9383a108ff:
-  Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-next-251019-3' into staging (2019-10-26 10:13:48 +0100)
+  Merge tag 'pull-lu-20231018' of https://gitlab.com/rth7680/qemu into staging (2023-10-19 10:20:57 -0700)
 are available in the Git repository at:
-  https://github.com/rth7680/qemu.git tags/pull-tcg-20191028
+  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20231018-2
-for you to fetch changes up to fe9b676fb3160496b4b2bf0c57d33be724bf04c3:
+for you to fetch changes up to a75f704d972b9408f5e2843784b3add48c724c52:
-  translate-all: Remove tb_alloc (2019-10-28 10:35:23 +0100)
+  target/i386: Use i128 for 128 and 256-bit loads and stores (2023-10-19 21:11:44 -0700)
 ----------------------------------------------------------------
-Improvements for TARGET_PAGE_BITS_VARY
+tcg: Drop unused tcg_temp_free define
-Fix for TCI ld16u_i64.
+tcg: Introduce tcg_use_softmmu
-Fix for segv on icount execute from i/o memory.
+tcg: Optimize past conditional branches
-Two misc cleanups.
+tcg: Use constant zero when expanding with divu2
 tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TB
 tcg/ppc: Use ADDPCIS for power9
 tcg/ppc: Use prefixed instructions for power10
 tcg/ppc: Disable TCG_REG_TB for Power9/Power10
 ----------------------------------------------------------------
-Alex Bennée (1):
+Jordan Niethe (1):
-      cputlb: ensure _cmmu helper functions follow the naming standard
+      tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TB
-Clement Deschamps (1):
+Mike Frysinger (1):
-      translate-all: fix uninitialized tb->orig_tb
+      tcg: drop unused tcg_temp_free define
-Richard Henderson (8):
+Richard Henderson (27):
-      exec: Split out variable page size support to exec-vary.c
+      tcg/ppc: Untabify tcg-target.c.inc
-      configure: Detect compiler support for __attribute__((alias))
+      tcg/ppc: Reinterpret tb-relative to TB+4
-      exec: Use const alias for TARGET_PAGE_BITS_VARY
+      tcg/ppc: Use ADDPCIS in tcg_out_tb_start
-      exec: Restrict TARGET_PAGE_BITS_VARY assert to CONFIG_DEBUG_TCG
+      tcg/ppc: Use ADDPCIS in tcg_out_movi_int
-      exec: Promote TARGET_PAGE_MASK to target_long
+      tcg/ppc: Use ADDPCIS for the constant pool
-      exec: Cache TARGET_PAGE_MASK for TARGET_PAGE_BITS_VARY
+      tcg/ppc: Use ADDPCIS in tcg_out_goto_tb
-      cputlb: Fix tlb_vaddr_to_host
+      tcg/ppc: Use PADDI in tcg_out_movi
-      translate-all: Remove tb_alloc
+      tcg/ppc: Use prefixed instructions in tcg_out_mem_long
       tcg/ppc: Use PLD in tcg_out_movi for constant pool
       tcg/ppc: Use prefixed instructions in tcg_out_dupi_vec
       tcg/ppc: Use PLD in tcg_out_goto_tb
       tcg/ppc: Disable TCG_REG_TB for Power9/Power10
       tcg: Introduce tcg_use_softmmu
       tcg: Provide guest_base fallback for system mode
       tcg/arm: Use tcg_use_softmmu
       tcg/aarch64: Use tcg_use_softmmu
       tcg/i386: Use tcg_use_softmmu
       tcg/loongarch64: Use tcg_use_softmmu
       tcg/mips: Use tcg_use_softmmu
       tcg/ppc: Use tcg_use_softmmu
       tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zero
       tcg/riscv: Use tcg_use_softmmu
       tcg/s390x: Use tcg_use_softmmu
       tcg: Use constant zero when expanding with divu2
       tcg: Optimize past conditional branches
       tcg: Add tcg_gen_{ld,st}_i128
       target/i386: Use i128 for 128 and 256-bit loads and stores
-Stefan Weil (1):
+ include/tcg/tcg-op-common.h      |   3 +
-      tci: Add implementation for INDEX_op_ld16u_i64
+ include/tcg/tcg-op.h             |   2 -
+ include/tcg/tcg.h                |   8 +-
-Wei Yang (1):
+ target/i386/tcg/translate.c      |  63 ++---
-      cpu: use ROUND_UP() to define xxx_PAGE_ALIGN
+ tcg/optimize.c                   |   8 +-
+ tcg/tcg-op-ldst.c                |  14 +-
- Makefile.target                  |   2 +-
+ tcg/tcg-op.c                     |  38 ++-
- include/exec/cpu-all.h           |  33 ++++++++----
+ tcg/tcg.c                        |  13 +-
- include/exec/cpu_ldst_template.h |   4 +-
+ tcg/aarch64/tcg-target.c.inc     | 177 ++++++------
- include/qemu-common.h            |   6 +++
+ tcg/arm/tcg-target.c.inc         | 203 +++++++-------
- tcg/tcg.h                        |  20 +++++---
+ tcg/i386/tcg-target.c.inc        | 198 +++++++-------
- accel/tcg/cputlb.c               |  26 ++++++++--
+ tcg/loongarch64/tcg-target.c.inc | 126 +++++----
- accel/tcg/translate-all.c        |  21 ++------
+ tcg/mips/tcg-target.c.inc        | 231 ++++++++--------
- exec-vary.c                      | 108 +++++++++++++++++++++++++++++++++++++++
+ tcg/ppc/tcg-target.c.inc         | 561 ++++++++++++++++++++++++++-------------
- exec.c                           |  34 ------------
+ tcg/riscv/tcg-target.c.inc       | 189 ++++++-------
- target/cris/translate_v10.inc.c  |   3 +-
+ tcg/s390x/tcg-target.c.inc       | 161 ++++++-----
- tcg/tci.c                        |  15 ++++++
+files changed, 1102 insertions(+), 893 deletions(-)
  configure                        |  19 +++++++
 files changed, 214 insertions(+), 77 deletions(-)
  create mode 100644 exec-vary.c

-[PULL v2 01/12] tci: Add implementation for INDEX_op_ld16u_i64
+Deleted patch
-From: Stefan Weil <sw@weilnetz.de>
-This fixes "make check-tcg" on a Debian x86_64 host.
-Signed-off-by: Stefan Weil <sw@weilnetz.de>
-Tested-by: Thomas Huth <thuth@redhat.com>
-Message-Id: <20190410194838.10123-1-sw@weilnetz.de>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/tci.c | 15 +++++++++++++++
-file changed, 15 insertions(+)
-diff --git a/tcg/tci.c b/tcg/tci.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tci.c
-+++ b/tcg/tci.c
-@@ -XXX,XX +XXX,XX @@ static void tci_write_reg8(tcg_target_ulong *regs, TCGReg index, uint8_t value)
-     tci_write_reg(regs, index, value);
- }
-+static void
-+tci_write_reg16(tcg_target_ulong *regs, TCGReg index, uint16_t value)
-+{
-+    tci_write_reg(regs, index, value);
-+}
-+
- static void
- tci_write_reg32(tcg_target_ulong *regs, TCGReg index, uint32_t value)
- {
-@@ -XXX,XX +XXX,XX @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
-             tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2));
-             break;
-         case INDEX_op_ld8s_i32:
-+            TODO();
-+            break;
-         case INDEX_op_ld16u_i32:
-             TODO();
-             break;
-@@ -XXX,XX +XXX,XX @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
-             tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2));
-             break;
-         case INDEX_op_ld8s_i64:
-+            TODO();
-+            break;
-         case INDEX_op_ld16u_i64:
-+            t0 = *tb_ptr++;
-+            t1 = tci_read_r(regs, &tb_ptr);
-+            t2 = tci_read_s32(&tb_ptr);
-+            tci_write_reg16(regs, t0, *(uint16_t *)(t1 + t2));
-+            break;
-         case INDEX_op_ld16s_i64:
-             TODO();
-             break;
---
-.17.1

-[PULL v2 02/12] cputlb: ensure _cmmu helper functions follow the naming standard
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-We document this in docs/devel/load-stores.rst so lets follow it. The
-bit and 64 bit access functions have historically not included the
-sign so we leave those as is. We also introduce some signed helpers
-which are used for loading immediate values in the translator.
-Fixes: 282dffc8
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Message-Id: <20191021150910.23216-1-alex.bennee@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- include/exec/cpu_ldst_template.h |  4 ++--
- tcg/tcg.h                        | 20 ++++++++++++++------
- accel/tcg/cputlb.c               | 24 +++++++++++++++++++++---
- target/cris/translate_v10.inc.c  |  3 +--
-files changed, 38 insertions(+), 13 deletions(-)
-diff --git a/include/exec/cpu_ldst_template.h b/include/exec/cpu_ldst_template.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/cpu_ldst_template.h
-+++ b/include/exec/cpu_ldst_template.h
-@@ -XXX,XX +XXX,XX @@
- #ifdef SOFTMMU_CODE_ACCESS
- #define ADDR_READ addr_code
- #define MMUSUFFIX _cmmu
--#define URETSUFFIX SUFFIX
--#define SRETSUFFIX SUFFIX
-+#define URETSUFFIX USUFFIX
-+#define SRETSUFFIX glue(s, SUFFIX)
- #else
- #define ADDR_READ addr_read
- #define MMUSUFFIX _mmu
-diff --git a/tcg/tcg.h b/tcg/tcg.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg.h
-+++ b/tcg/tcg.h
-@@ -XXX,XX +XXX,XX @@ void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
- void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
-                        TCGMemOpIdx oi, uintptr_t retaddr);
--uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
-+uint8_t helper_ret_ldub_cmmu(CPUArchState *env, target_ulong addr,
-                             TCGMemOpIdx oi, uintptr_t retaddr);
--uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
-+int8_t helper_ret_ldsb_cmmu(CPUArchState *env, target_ulong addr,
-                             TCGMemOpIdx oi, uintptr_t retaddr);
-+uint16_t helper_le_lduw_cmmu(CPUArchState *env, target_ulong addr,
-+                             TCGMemOpIdx oi, uintptr_t retaddr);
-+int16_t helper_le_ldsw_cmmu(CPUArchState *env, target_ulong addr,
-+                             TCGMemOpIdx oi, uintptr_t retaddr);
- uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
-                             TCGMemOpIdx oi, uintptr_t retaddr);
- uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
-                             TCGMemOpIdx oi, uintptr_t retaddr);
--uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
--                            TCGMemOpIdx oi, uintptr_t retaddr);
-+uint16_t helper_be_lduw_cmmu(CPUArchState *env, target_ulong addr,
-+                             TCGMemOpIdx oi, uintptr_t retaddr);
-+int16_t helper_be_ldsw_cmmu(CPUArchState *env, target_ulong addr,
-+                             TCGMemOpIdx oi, uintptr_t retaddr);
- uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
-                             TCGMemOpIdx oi, uintptr_t retaddr);
- uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
-@@ -XXX,XX +XXX,XX @@ uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
- # define helper_ret_stw_mmu   helper_be_stw_mmu
- # define helper_ret_stl_mmu   helper_be_stl_mmu
- # define helper_ret_stq_mmu   helper_be_stq_mmu
--# define helper_ret_ldw_cmmu  helper_be_ldw_cmmu
-+# define helper_ret_lduw_cmmu  helper_be_lduw_cmmu
-+# define helper_ret_ldsw_cmmu  helper_be_ldsw_cmmu
- # define helper_ret_ldl_cmmu  helper_be_ldl_cmmu
- # define helper_ret_ldq_cmmu  helper_be_ldq_cmmu
- #else
-@@ -XXX,XX +XXX,XX @@ uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
- # define helper_ret_stw_mmu   helper_le_stw_mmu
- # define helper_ret_stl_mmu   helper_le_stl_mmu
- # define helper_ret_stq_mmu   helper_le_stq_mmu
--# define helper_ret_ldw_cmmu  helper_le_ldw_cmmu
-+# define helper_ret_lduw_cmmu  helper_le_lduw_cmmu
-+# define helper_ret_ldsw_cmmu  helper_le_ldsw_cmmu
- # define helper_ret_ldl_cmmu  helper_le_ldl_cmmu
- # define helper_ret_ldq_cmmu  helper_le_ldq_cmmu
- #endif
-diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
-index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/cputlb.c
-+++ b/accel/tcg/cputlb.c
-@@ -XXX,XX +XXX,XX @@ static uint64_t full_ldub_cmmu(CPUArchState *env, target_ulong addr,
-     return load_helper(env, addr, oi, retaddr, MO_8, true, full_ldub_cmmu);
- }
--uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
-+uint8_t helper_ret_ldub_cmmu(CPUArchState *env, target_ulong addr,
-                             TCGMemOpIdx oi, uintptr_t retaddr)
- {
-     return full_ldub_cmmu(env, addr, oi, retaddr);
- }
-+int8_t helper_ret_ldsb_cmmu(CPUArchState *env, target_ulong addr,
-+                            TCGMemOpIdx oi, uintptr_t retaddr)
-+{
-+    return (int8_t) full_ldub_cmmu(env, addr, oi, retaddr);
-+}
-+
- static uint64_t full_le_lduw_cmmu(CPUArchState *env, target_ulong addr,
-                                   TCGMemOpIdx oi, uintptr_t retaddr)
- {
-@@ -XXX,XX +XXX,XX @@ static uint64_t full_le_lduw_cmmu(CPUArchState *env, target_ulong addr,
-                        full_le_lduw_cmmu);
- }
--uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
-+uint16_t helper_le_lduw_cmmu(CPUArchState *env, target_ulong addr,
-                             TCGMemOpIdx oi, uintptr_t retaddr)
- {
-     return full_le_lduw_cmmu(env, addr, oi, retaddr);
- }
-+int16_t helper_le_ldsw_cmmu(CPUArchState *env, target_ulong addr,
-+                            TCGMemOpIdx oi, uintptr_t retaddr)
-+{
-+    return (int16_t) full_le_lduw_cmmu(env, addr, oi, retaddr);
-+}
-+
- static uint64_t full_be_lduw_cmmu(CPUArchState *env, target_ulong addr,
-                                   TCGMemOpIdx oi, uintptr_t retaddr)
- {
-@@ -XXX,XX +XXX,XX @@ static uint64_t full_be_lduw_cmmu(CPUArchState *env, target_ulong addr,
-                        full_be_lduw_cmmu);
- }
--uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
-+uint16_t helper_be_lduw_cmmu(CPUArchState *env, target_ulong addr,
-                             TCGMemOpIdx oi, uintptr_t retaddr)
- {
-     return full_be_lduw_cmmu(env, addr, oi, retaddr);
- }
-+int16_t helper_be_ldsw_cmmu(CPUArchState *env, target_ulong addr,
-+                            TCGMemOpIdx oi, uintptr_t retaddr)
-+{
-+    return (int16_t) full_be_lduw_cmmu(env, addr, oi, retaddr);
-+}
-+
- static uint64_t full_le_ldul_cmmu(CPUArchState *env, target_ulong addr,
-                                   TCGMemOpIdx oi, uintptr_t retaddr)
- {
-diff --git a/target/cris/translate_v10.inc.c b/target/cris/translate_v10.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/cris/translate_v10.inc.c
-+++ b/target/cris/translate_v10.inc.c
-@@ -XXX,XX +XXX,XX @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
-         case CRISV10_IND_BCC_M:
-             cris_cc_mask(dc, 0);
--            imm = cpu_ldsw_code(env, dc->pc + 2);
--            simm = (int16_t)imm;
-+            simm = cpu_ldsw_code(env, dc->pc + 2);
-             simm += 4;
-             LOG_DIS("bcc_m: b%s %x\n", cc_name(dc->cond), dc->pc + simm);
---
-.17.1

-[PULL v2 03/12] cpu: use ROUND_UP() to define xxx_PAGE_ALIGN
+Deleted patch
-From: Wei Yang <richardw.yang@linux.intel.com>
-Use ROUND_UP() to define, which is a little bit easy to read.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
-Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
-Reviewed-by: Juan Quintela <quintela@redhat.com>
-Signed-off-by: Wei Yang <richardw.yang@linux.intel.com>
-Message-Id: <20191013021145.16011-2-richardw.yang@linux.intel.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- include/exec/cpu-all.h | 7 +++----
-file changed, 3 insertions(+), 4 deletions(-)
-diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/cpu-all.h
-+++ b/include/exec/cpu-all.h
-@@ -XXX,XX +XXX,XX @@ extern int target_page_bits;
- #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
- #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
--#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
-+#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
- /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even
-  * when intptr_t is 32-bit and we are aligning a long long.
-@@ -XXX,XX +XXX,XX @@ extern int target_page_bits;
- extern uintptr_t qemu_host_page_size;
- extern intptr_t qemu_host_page_mask;
--#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
--#define REAL_HOST_PAGE_ALIGN(addr) (((addr) + qemu_real_host_page_size - 1) & \
--                                    qemu_real_host_page_mask)
-+#define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size)
-+#define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size)
- /* same as PROT_xxx */
- #define PAGE_READ      0x0001
---
-.17.1

-[PULL v2 04/12] exec: Split out variable page size support to exec-vary.c
+Deleted patch
-The next patch will play a trick with "const" that will
-confuse the compiler about the uses of target_page_bits
-within exec.c.  Moving everything to a new file prevents
-this confusion.
-No functional change so far.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- Makefile.target       |  2 +-
- include/qemu-common.h |  6 +++++
- exec-vary.c           | 57 +++++++++++++++++++++++++++++++++++++++++++
- exec.c                | 34 --------------------------
-files changed, 64 insertions(+), 35 deletions(-)
- create mode 100644 exec-vary.c
-diff --git a/Makefile.target b/Makefile.target
-index XXXXXXX..XXXXXXX 100644
---- a/Makefile.target
-+++ b/Makefile.target
-@@ -XXX,XX +XXX,XX @@ obj-y += trace/
- #########################################################
- # cpu emulator library
--obj-y += exec.o
-+obj-y += exec.o exec-vary.o
- obj-y += accel/
- obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/tcg-op-vec.o tcg/tcg-op-gvec.o
- obj-$(CONFIG_TCG) += tcg/tcg-common.o tcg/optimize.o
-diff --git a/include/qemu-common.h b/include/qemu-common.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/qemu-common.h
-+++ b/include/qemu-common.h
-@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu);
-  */
- bool set_preferred_target_page_bits(int bits);
-+/**
-+ * finalize_target_page_bits:
-+ * Commit the final value set by set_preferred_target_page_bits.
-+ */
-+void finalize_target_page_bits(void);
-+
- /**
-  * Sends a (part of) iovec down a socket, yielding when the socket is full, or
-  * Receives data into a (part of) iovec from a socket,
-diff --git a/exec-vary.c b/exec-vary.c
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/exec-vary.c
-@@ -XXX,XX +XXX,XX @@
-+/*
-+ * Variable page size handling
-+ *
-+ *  Copyright (c) 2003 Fabrice Bellard
-+ *
-+ * This library is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU Lesser General Public
-+ * License as published by the Free Software Foundation; either
-+ * version 2 of the License, or (at your option) any later version.
-+ *
-+ * This library is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * Lesser General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU Lesser General Public
-+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include "qemu/osdep.h"
-+#include "qemu-common.h"
-+#include "exec/exec-all.h"
-+
-+#ifdef TARGET_PAGE_BITS_VARY
-+int target_page_bits;
-+bool target_page_bits_decided;
-+#endif
-+
-+bool set_preferred_target_page_bits(int bits)
-+{
-+    /*
-+     * The target page size is the lowest common denominator for all
-+     * the CPUs in the system, so we can only make it smaller, never
-+     * larger. And we can't make it smaller once we've committed to
-+     * a particular size.
-+     */
-+#ifdef TARGET_PAGE_BITS_VARY
-+    assert(bits >= TARGET_PAGE_BITS_MIN);
-+    if (target_page_bits == 0 || target_page_bits > bits) {
-+        if (target_page_bits_decided) {
-+            return false;
-+        }
-+        target_page_bits = bits;
-+    }
-+#endif
-+    return true;
-+}
-+
-+void finalize_target_page_bits(void)
-+{
-+#ifdef TARGET_PAGE_BITS_VARY
-+    if (target_page_bits == 0) {
-+        target_page_bits = TARGET_PAGE_BITS_MIN;
-+    }
-+    target_page_bits_decided = true;
-+#endif
-+}
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ AddressSpace address_space_memory;
- static MemoryRegion io_mem_unassigned;
- #endif
--#ifdef TARGET_PAGE_BITS_VARY
--int target_page_bits;
--bool target_page_bits_decided;
--#endif
--
- CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
- /* current CPU in the current thread. It is only valid inside
-@@ -XXX,XX +XXX,XX @@ int use_icount;
- uintptr_t qemu_host_page_size;
- intptr_t qemu_host_page_mask;
--bool set_preferred_target_page_bits(int bits)
--{
--    /* The target page size is the lowest common denominator for all
--     * the CPUs in the system, so we can only make it smaller, never
--     * larger. And we can't make it smaller once we've committed to
--     * a particular size.
--     */
--#ifdef TARGET_PAGE_BITS_VARY
--    assert(bits >= TARGET_PAGE_BITS_MIN);
--    if (target_page_bits == 0 || target_page_bits > bits) {
--        if (target_page_bits_decided) {
--            return false;
--        }
--        target_page_bits = bits;
--    }
--#endif
--    return true;
--}
--
- #if !defined(CONFIG_USER_ONLY)
--static void finalize_target_page_bits(void)
--{
--#ifdef TARGET_PAGE_BITS_VARY
--    if (target_page_bits == 0) {
--        target_page_bits = TARGET_PAGE_BITS_MIN;
--    }
--    target_page_bits_decided = true;
--#endif
--}
--
- typedef struct PhysPageEntry PhysPageEntry;
- struct PhysPageEntry {
---
-.17.1

-[PULL v2 05/12] configure: Detect compiler support for __attribute__((alias))
+Deleted patch
-Such support is present almost everywhere, except for Xcode 9.
-It is added in Xcode 10, but travis uses xcode9 by default,
-so we should support it for a while yet.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- configure | 19 +++++++++++++++++++
-file changed, 19 insertions(+)
-diff --git a/configure b/configure
-index XXXXXXX..XXXXXXX 100755
---- a/configure
-+++ b/configure
-@@ -XXX,XX +XXX,XX @@ if compile_prog "" "" ; then
-   vector16=yes
- fi
-+########################################
-+# See if __attribute__((alias)) is supported.
-+# This false for Xcode 9, but has been remedied for Xcode 10.
-+# Unfortunately, travis uses Xcode 9 by default.
-+
-+attralias=no
-+cat > $TMPC << EOF
-+int x = 1;
-+extern const int y __attribute__((alias("x")));
-+int main(void) { return 0; }
-+EOF
-+if compile_prog "" "" ; then
-+    attralias=yes
-+fi
-+
- ########################################
- # check if getauxval is available.
-@@ -XXX,XX +XXX,XX @@ if test "$vector16" = "yes" ; then
-   echo "CONFIG_VECTOR16=y" >> $config_host_mak
- fi
-+if test "$attralias" = "yes" ; then
-+  echo "CONFIG_ATTRIBUTE_ALIAS=y" >> $config_host_mak
-+fi
-+
- if test "$getauxval" = "yes" ; then
-   echo "CONFIG_GETAUXVAL=y" >> $config_host_mak
- fi
---
-.17.1

-[PULL v2 06/12] exec: Use const alias for TARGET_PAGE_BITS_VARY
+Deleted patch
-Using a variable that is declared "const" for this tells the
-compiler that it may read the value once and assume that it
-does not change across function calls.
-For target_page_size, this means we have only one assert per
-function, and one read of the variable.
-This reduces the size of qemu-system-aarch64 by 8k.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- include/exec/cpu-all.h | 14 ++++++---
- exec-vary.c            | 66 +++++++++++++++++++++++++++++++++++++-----
-files changed, 68 insertions(+), 12 deletions(-)
-diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/cpu-all.h
-+++ b/include/exec/cpu-all.h
-@@ -XXX,XX +XXX,XX @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val
- /* page related stuff */
- #ifdef TARGET_PAGE_BITS_VARY
--extern bool target_page_bits_decided;
--extern int target_page_bits;
--#define TARGET_PAGE_BITS ({ assert(target_page_bits_decided); \
--                            target_page_bits; })
-+typedef struct {
-+    bool decided;
-+    int bits;
-+} TargetPageBits;
-+#if defined(CONFIG_ATTRIBUTE_ALIAS) || !defined(IN_EXEC_VARY)
-+extern const TargetPageBits target_page;
-+#else
-+extern TargetPageBits target_page;
-+#endif
-+#define TARGET_PAGE_BITS   ({ assert(target_page.decided); target_page.bits; })
- #else
- #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
- #endif
-diff --git a/exec-vary.c b/exec-vary.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec-vary.c
-+++ b/exec-vary.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/osdep.h"
- #include "qemu-common.h"
-+
-+#define IN_EXEC_VARY 1
-+
- #include "exec/exec-all.h"
- #ifdef TARGET_PAGE_BITS_VARY
--int target_page_bits;
--bool target_page_bits_decided;
-+# ifdef CONFIG_ATTRIBUTE_ALIAS
-+/*
-+ * We want to declare the "target_page" variable as const, which tells
-+ * the compiler that it can cache any value that it reads across calls.
-+ * This avoids multiple assertions and multiple reads within any one user.
-+ *
-+ * This works because we finish initializing the data before we ever read
-+ * from the "target_page" symbol.
-+ *
-+ * This also requires that we have a non-constant symbol by which we can
-+ * perform the actual initialization, and which forces the data to be
-+ * allocated within writable memory.  Thus "init_target_page", and we use
-+ * that symbol exclusively in the two functions that initialize this value.
-+ *
-+ * The "target_page" symbol is created as an alias of "init_target_page".
-+ */
-+static TargetPageBits init_target_page;
-+
-+/*
-+ * Note that this is *not* a redundant decl, this is the definition of
-+ * the "target_page" symbol.  The syntax for this definition requires
-+ * the use of the extern keyword.  This seems to be a GCC bug in
-+ * either the syntax for the alias attribute or in -Wredundant-decls.
-+ *
-+ * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91765
-+ */
-+#  pragma GCC diagnostic push
-+#  pragma GCC diagnostic ignored "-Wredundant-decls"
-+
-+extern const TargetPageBits target_page
-+    __attribute__((alias("init_target_page")));
-+
-+#  pragma GCC diagnostic pop
-+# else
-+/*
-+ * When aliases are not supported then we force two different declarations,
-+ * by way of suppressing the header declaration with IN_EXEC_VARY.
-+ * We assume that on such an old compiler, LTO cannot be used, and so the
-+ * compiler cannot not detect the mismatched declarations, and all is well.
-+ */
-+TargetPageBits target_page;
-+#  define init_target_page target_page
-+# endif
- #endif
- bool set_preferred_target_page_bits(int bits)
-@@ -XXX,XX +XXX,XX @@ bool set_preferred_target_page_bits(int bits)
-      */
- #ifdef TARGET_PAGE_BITS_VARY
-     assert(bits >= TARGET_PAGE_BITS_MIN);
--    if (target_page_bits == 0 || target_page_bits > bits) {
--        if (target_page_bits_decided) {
-+    if (init_target_page.bits == 0 || init_target_page.bits > bits) {
-+        if (init_target_page.decided) {
-             return false;
-         }
--        target_page_bits = bits;
-+        init_target_page.bits = bits;
-     }
- #endif
-     return true;
-@@ -XXX,XX +XXX,XX @@ bool set_preferred_target_page_bits(int bits)
- void finalize_target_page_bits(void)
- {
- #ifdef TARGET_PAGE_BITS_VARY
--    if (target_page_bits == 0) {
--        target_page_bits = TARGET_PAGE_BITS_MIN;
-+    if (init_target_page.bits == 0) {
-+        init_target_page.bits = TARGET_PAGE_BITS_MIN;
-     }
--    target_page_bits_decided = true;
-+    init_target_page.decided = true;
-+
-+    /*
-+     * For the benefit of an -flto build, prevent the compiler from
-+     * hoisting a read from target_page before we finish initializing.
-+     */
-+    barrier();
- #endif
- }
---
-.17.1

-[PULL v2 07/12] exec: Restrict TARGET_PAGE_BITS_VARY assert to CONFIG_DEBUG_TCG
+Deleted patch
-This reduces the size of a release build by about 10k.
-Noticably, within the tlb miss helpers.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- include/exec/cpu-all.h | 4 ++++
-file changed, 4 insertions(+)
-diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/cpu-all.h
-+++ b/include/exec/cpu-all.h
-@@ -XXX,XX +XXX,XX @@ extern const TargetPageBits target_page;
- #else
- extern TargetPageBits target_page;
- #endif
-+#ifdef CONFIG_DEBUG_TCG
- #define TARGET_PAGE_BITS   ({ assert(target_page.decided); target_page.bits; })
- #else
-+#define TARGET_PAGE_BITS   target_page.bits
-+#endif
-+#else
- #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
- #endif
---
-.17.1

-[PULL v2 08/12] exec: Promote TARGET_PAGE_MASK to target_long
+Deleted patch
-There are some uint64_t uses that expect TARGET_PAGE_MASK to
-extend for a 32-bit, so this must continue to be a signed type.
-Define based on TARGET_PAGE_BITS not TARGET_PAGE_SIZE; this
-will make a following patch more clear.
-This should not have a functional effect so far.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- include/exec/cpu-all.h | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/cpu-all.h
-+++ b/include/exec/cpu-all.h
-@@ -XXX,XX +XXX,XX @@ extern TargetPageBits target_page;
- #endif
- #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
--#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
-+#define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS)
- #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
- /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even
---
-.17.1

-[PULL v2 09/12] exec: Cache TARGET_PAGE_MASK for TARGET_PAGE_BITS_VARY
+[PULL v2 18/29] tcg/i386: Use tcg_use_softmmu
-This eliminates a set of runtime shifts.  It turns out that we
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 require TARGET_PAGE_MASK more often than TARGET_PAGE_SIZE, so
 redefine TARGET_PAGE_SIZE based on TARGET_PAGE_MASK instead of
 the other way around.
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: David Hildenbrand <david@redhat.com>
 Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- include/exec/cpu-all.h | 8 ++++++--
+ tcg/i386/tcg-target.c.inc | 198 +++++++++++++++++++-------------------
- exec-vary.c            | 1 +
+file changed, 98 insertions(+), 100 deletions(-)
 files changed, 7 insertions(+), 2 deletions(-)
-diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
+diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/include/exec/cpu-all.h
+--- a/tcg/i386/tcg-target.c.inc
-+++ b/include/exec/cpu-all.h
++++ b/tcg/i386/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val
+@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
- typedef struct {
+ # define ALL_VECTOR_REGS       0x00ff0000u
-     bool decided;
+ # define ALL_BYTEL_REGS        0x0000000fu
      int bits;
 +    target_long mask;
  } TargetPageBits;
  #if defined(CONFIG_ATTRIBUTE_ALIAS) || !defined(IN_EXEC_VARY)
  extern const TargetPageBits target_page;
@@ -XXX,XX +XXX,XX @@ extern TargetPageBits target_page;
  #endif
- #ifdef CONFIG_DEBUG_TCG
+-#ifdef CONFIG_SOFTMMU
- #define TARGET_PAGE_BITS   ({ assert(target_page.decided); target_page.bits; })
+-# define SOFTMMU_RESERVE_REGS  ((1 << TCG_REG_L0) | (1 << TCG_REG_L1))
-+#define TARGET_PAGE_MASK   ({ assert(target_page.decided); target_page.mask; })
+-#else
 -# define SOFTMMU_RESERVE_REGS  0
 -#endif
 +#define SOFTMMU_RESERVE_REGS \
 +    (tcg_use_softmmu ? (1 << TCG_REG_L0) | (1 << TCG_REG_L1) : 0)
  /* For 64-bit, we always know that CMOV is available.  */
  #if TCG_TARGET_REG_BITS == 64
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
      return true;
  }
 -#ifndef CONFIG_SOFTMMU
 +#ifdef CONFIG_USER_ONLY
  static HostAddress x86_guest_base = {
      .index = -1
  };
@@ -XXX,XX +XXX,XX @@ static inline int setup_guest_base_seg(void)
      }
      return 0;
  }
 +#define setup_guest_base_seg  setup_guest_base_seg
  #elif defined(__x86_64__) && \
        (defined (__FreeBSD__) || defined (__FreeBSD_kernel__))
  # include <machine/sysarch.h>
@@ -XXX,XX +XXX,XX @@ static inline int setup_guest_base_seg(void)
      }
      return 0;
  }
 +#define setup_guest_base_seg  setup_guest_base_seg
 +#endif
  #else
- #define TARGET_PAGE_BITS   target_page.bits
+-static inline int setup_guest_base_seg(void)
-+#define TARGET_PAGE_MASK   target_page.mask
+-{
- #endif
+-    return 0;
-+#define TARGET_PAGE_SIZE   (-(int)TARGET_PAGE_MASK)
+-}
- #else
+-#endif /* setup_guest_base_seg */
- #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
+-#endif /* !SOFTMMU */
-+#define TARGET_PAGE_SIZE   (1 << TARGET_PAGE_BITS)
++# define x86_guest_base (*(HostAddress *)({ qemu_build_not_reached(); NULL; }))
-+#define TARGET_PAGE_MASK   ((target_long)-1 << TARGET_PAGE_BITS)
++#endif /* CONFIG_USER_ONLY */
- #endif
++#ifndef setup_guest_base_seg
++# define setup_guest_base_seg()  0
--#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
++#endif
--#define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS)
- #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
+ #define MIN_TLB_MASK_TABLE_OFS  INT_MIN
- /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even
+@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
-diff --git a/exec-vary.c b/exec-vary.c
+     MemOp s_bits = opc & MO_SIZE;
-index XXXXXXX..XXXXXXX 100644
+     unsigned a_mask;
---- a/exec-vary.c
-+++ b/exec-vary.c
+-#ifdef CONFIG_SOFTMMU
-@@ -XXX,XX +XXX,XX @@ void finalize_target_page_bits(void)
+-    h->index = TCG_REG_L0;
-     if (init_target_page.bits == 0) {
+-    h->ofs = 0;
-         init_target_page.bits = TARGET_PAGE_BITS_MIN;
+-    h->seg = 0;
-     }
+-#else
-+    init_target_page.mask = (target_long)-1 << init_target_page.bits;
+-    *h = x86_guest_base;
-     init_target_page.decided = true;
+-#endif
 +    if (tcg_use_softmmu) {
 +        h->index = TCG_REG_L0;
 +        h->ofs = 0;
 +        h->seg = 0;
 +    } else {
 +        *h = x86_guest_base;
 +    }
      h->base = addrlo;
      h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128);
      a_mask = (1 << h->aa.align) - 1;
 -#ifdef CONFIG_SOFTMMU
 -    int cmp_ofs = is_ld ? offsetof(CPUTLBEntry, addr_read)
 -                        : offsetof(CPUTLBEntry, addr_write);
 -    TCGType ttype = TCG_TYPE_I32;
 -    TCGType tlbtype = TCG_TYPE_I32;
 -    int trexw = 0, hrexw = 0, tlbrexw = 0;
 -    unsigned mem_index = get_mmuidx(oi);
 -    unsigned s_mask = (1 << s_bits) - 1;
 -    int fast_ofs = tlb_mask_table_ofs(s, mem_index);
 -    int tlb_mask;
 +    if (tcg_use_softmmu) {
 +        int cmp_ofs = is_ld ? offsetof(CPUTLBEntry, addr_read)
 +                            : offsetof(CPUTLBEntry, addr_write);
 +        TCGType ttype = TCG_TYPE_I32;
 +        TCGType tlbtype = TCG_TYPE_I32;
 +        int trexw = 0, hrexw = 0, tlbrexw = 0;
 +        unsigned mem_index = get_mmuidx(oi);
 +        unsigned s_mask = (1 << s_bits) - 1;
 +        int fast_ofs = tlb_mask_table_ofs(s, mem_index);
 +        int tlb_mask;
 -    ldst = new_ldst_label(s);
 -    ldst->is_ld = is_ld;
 -    ldst->oi = oi;
 -    ldst->addrlo_reg = addrlo;
 -    ldst->addrhi_reg = addrhi;
 +        ldst = new_ldst_label(s);
 +        ldst->is_ld = is_ld;
 +        ldst->oi = oi;
 +        ldst->addrlo_reg = addrlo;
 +        ldst->addrhi_reg = addrhi;
 -    if (TCG_TARGET_REG_BITS == 64) {
 -        ttype = s->addr_type;
 -        trexw = (ttype == TCG_TYPE_I32 ? 0 : P_REXW);
 -        if (TCG_TYPE_PTR == TCG_TYPE_I64) {
 -            hrexw = P_REXW;
 -            if (s->page_bits + s->tlb_dyn_max_bits > 32) {
 -                tlbtype = TCG_TYPE_I64;
 -                tlbrexw = P_REXW;
 +        if (TCG_TARGET_REG_BITS == 64) {
 +            ttype = s->addr_type;
 +            trexw = (ttype == TCG_TYPE_I32 ? 0 : P_REXW);
 +            if (TCG_TYPE_PTR == TCG_TYPE_I64) {
 +                hrexw = P_REXW;
 +                if (s->page_bits + s->tlb_dyn_max_bits > 32) {
 +                    tlbtype = TCG_TYPE_I64;
 +                    tlbrexw = P_REXW;
 +                }
              }
          }
 -    }
 -    tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo);
 -    tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0,
 -                   s->page_bits - CPU_TLB_ENTRY_BITS);
 +        tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo);
 +        tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0,
 +                       s->page_bits - CPU_TLB_ENTRY_BITS);
 -    tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0,
 -                         fast_ofs + offsetof(CPUTLBDescFast, mask));
 +        tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0,
 +                             fast_ofs + offsetof(CPUTLBDescFast, mask));
 -    tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0,
 -                         fast_ofs + offsetof(CPUTLBDescFast, table));
 +        tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0,
 +                             fast_ofs + offsetof(CPUTLBDescFast, table));
 -    /*
 -     * If the required alignment is at least as large as the access, simply
 -     * copy the address and mask.  For lesser alignments, check that we don't
 -     * cross pages for the complete access.
 -     */
 -    if (a_mask >= s_mask) {
 -        tcg_out_mov(s, ttype, TCG_REG_L1, addrlo);
 -    } else {
 -        tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1,
 -                             addrlo, s_mask - a_mask);
 -    }
 -    tlb_mask = s->page_mask | a_mask;
 -    tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0);
 +        /*
 +         * If the required alignment is at least as large as the access,
 +         * simply copy the address and mask.  For lesser alignments,
 +         * check that we don't cross pages for the complete access.
 +         */
 +        if (a_mask >= s_mask) {
 +            tcg_out_mov(s, ttype, TCG_REG_L1, addrlo);
 +        } else {
 +            tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1,
 +                                 addrlo, s_mask - a_mask);
 +        }
 +        tlb_mask = s->page_mask | a_mask;
 +        tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0);
 -    /* cmp 0(TCG_REG_L0), TCG_REG_L1 */
 -    tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw,
 -                         TCG_REG_L1, TCG_REG_L0, cmp_ofs);
 -
 -    /* jne slow_path */
 -    tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
 -    ldst->label_ptr[0] = s->code_ptr;
 -    s->code_ptr += 4;
 -
 -    if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I64) {
 -        /* cmp 4(TCG_REG_L0), addrhi */
 -        tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, TCG_REG_L0, cmp_ofs + 4);
 +        /* cmp 0(TCG_REG_L0), TCG_REG_L1 */
 +        tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw,
 +                             TCG_REG_L1, TCG_REG_L0, cmp_ofs);
          /* jne slow_path */
          tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
 -        ldst->label_ptr[1] = s->code_ptr;
 +        ldst->label_ptr[0] = s->code_ptr;
          s->code_ptr += 4;
 -    }
 -    /* TLB Hit.  */
 -    tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0,
 -               offsetof(CPUTLBEntry, addend));
 -#else
 -    if (a_mask) {
 +        if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I64) {
 +            /* cmp 4(TCG_REG_L0), addrhi */
 +            tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi,
 +                                 TCG_REG_L0, cmp_ofs + 4);
 +
 +            /* jne slow_path */
 +            tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
 +            ldst->label_ptr[1] = s->code_ptr;
 +            s->code_ptr += 4;
 +        }
 +
 +        /* TLB Hit.  */
 +        tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0,
 +                   offsetof(CPUTLBEntry, addend));
 +    } else if (a_mask) {
          ldst = new_ldst_label(s);
          ldst->is_ld = is_ld;
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
          ldst->label_ptr[0] = s->code_ptr;
          s->code_ptr += 4;
      }
 -#endif
      return ldst;
  }
@@ -XXX,XX +XXX,XX @@ static void tcg_target_qemu_prologue(TCGContext *s)
          tcg_out_push(s, tcg_target_callee_save_regs[i]);
      }
 -#if TCG_TARGET_REG_BITS == 32
 -    tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP,
 -               (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4);
 -    tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
 -    /* jmp *tb.  */
 -    tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP,
 -                         (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4
 -                         + stack_addend);
 -#else
 -# if !defined(CONFIG_SOFTMMU)
 -    if (guest_base) {
 +    if (!tcg_use_softmmu && guest_base) {
          int seg = setup_guest_base_seg();
          if (seg != 0) {
              x86_guest_base.seg = seg;
          } else if (guest_base == (int32_t)guest_base) {
              x86_guest_base.ofs = guest_base;
          } else {
 +            assert(TCG_TARGET_REG_BITS == 64);
              /* Choose R12 because, as a base, it requires a SIB byte. */
              x86_guest_base.index = TCG_REG_R12;
              tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base.index, guest_base);
              tcg_regset_set_reg(s->reserved_regs, x86_guest_base.index);
          }
      }
 -# endif
 -    tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
 -    tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
 -    /* jmp *tb.  */
 -    tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]);
 -#endif
 +
 +    if (TCG_TARGET_REG_BITS == 32) {
 +        tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP,
 +                   (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4);
 +        tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
 +        /* jmp *tb.  */
 +        tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP,
 +                             (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4
 +                             + stack_addend);
 +    } else {
 +        tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
 +        tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
 +        /* jmp *tb.  */
 +        tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]);
 +    }
      /*
+      * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
 --
-.17.1
+.34.1

-[PULL v2 10/12] cputlb: Fix tlb_vaddr_to_host
+Deleted patch
-Using uintptr_t instead of target_ulong meant that, for 64-bit guest
-and 32-bit host, we truncated the guest address comparator and so may
-not hit the tlb when we should.
-Fixes: 4811e9095c0
-Reviewed-by: David Hildenbrand <david@redhat.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- accel/tcg/cputlb.c | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
-index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/cputlb.c
-+++ b/accel/tcg/cputlb.c
-@@ -XXX,XX +XXX,XX @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
-                         MMUAccessType access_type, int mmu_idx)
- {
-     CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
--    uintptr_t tlb_addr, page;
-+    target_ulong tlb_addr, page;
-     size_t elt_ofs;
-     switch (access_type) {
---
-.17.1

-[PULL v2 11/12] translate-all: fix uninitialized tb->orig_tb
+Deleted patch
-From: Clement Deschamps <clement.deschamps@greensocs.com>
-This fixes a segmentation fault in icount mode when executing
-from an IO region.
-TB is marked as CF_NOCACHE but tb->orig_tb is not initialized
-(equals previous value in code_gen_buffer).
-The issue happens in cpu_io_recompile() when it tries to invalidate orig_tb.
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Signed-off-by: Clement Deschamps <clement.deschamps@greensocs.com>
-Message-Id: <20191022140016.918371-1-clement.deschamps@greensocs.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- accel/tcg/translate-all.c | 1 +
-file changed, 1 insertion(+)
-diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
-index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/translate-all.c
-+++ b/accel/tcg/translate-all.c
-@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
-     tb->cs_base = cs_base;
-     tb->flags = flags;
-     tb->cflags = cflags;
-+    tb->orig_tb = NULL;
-     tb->trace_vcpu_dstate = *cpu->trace_dstate;
-     tcg_ctx->tb_cflags = cflags;
-  tb_overflow:
---
-.17.1

-[PULL v2 12/12] translate-all: Remove tb_alloc
+Deleted patch
-Since 2ac01d6dafab, this function does only two things: assert a
-lock is held, and call tcg_tb_alloc.  It is used exactly once,
-and its user has already done the assert.
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Reviewed-by: Clement Deschamps <clement.deschamps@greensocs.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- accel/tcg/translate-all.c | 20 ++------------------
-file changed, 2 insertions(+), 18 deletions(-)
-diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
-index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/translate-all.c
-+++ b/accel/tcg/translate-all.c
-@@ -XXX,XX +XXX,XX @@ void tcg_exec_init(unsigned long tb_size)
- #endif
- }
--/*
-- * Allocate a new translation block. Flush the translation buffer if
-- * too many translation blocks or too much generated code.
-- */
--static TranslationBlock *tb_alloc(target_ulong pc)
--{
--    TranslationBlock *tb;
--
--    assert_memory_lock();
--
--    tb = tcg_tb_alloc(tcg_ctx);
--    if (unlikely(tb == NULL)) {
--        return NULL;
--    }
--    return tb;
--}
--
- /* call with @p->lock held */
- static inline void invalidate_page_bitmap(PageDesc *p)
- {
-@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
-     TCGProfile *prof = &tcg_ctx->prof;
-     int64_t ti;
- #endif
-+
-     assert_memory_lock();
-     phys_pc = get_page_addr_code(env, pc);
-@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
-     }
-  buffer_overflow:
--    tb = tb_alloc(pc);
-+    tb = tcg_tb_alloc(tcg_ctx);
-     if (unlikely(!tb)) {
-         /* flush must be done */
-         tb_flush(cpu);
---
-.17.1

V2 fixes a build problem that affected win32.

The following changes since commit 187f35512106501fe9a11057f4d8705431e0026d:

Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-next-251019-3' into staging (2019-10-26 10:13:48 +0100)

are available in the Git repository at:

https://github.com/rth7680/qemu.git tags/pull-tcg-20191028

for you to fetch changes up to fe9b676fb3160496b4b2bf0c57d33be724bf04c3:

translate-all: Remove tb_alloc (2019-10-28 10:35:23 +0100)

----------------------------------------------------------------
Improvements for TARGET_PAGE_BITS_VARY
Fix for TCI ld16u_i64.
Fix for segv on icount execute from i/o memory.
Two misc cleanups.

----------------------------------------------------------------
Alex Bennée (1):
      cputlb: ensure _cmmu helper functions follow the naming standard

Clement Deschamps (1):
      translate-all: fix uninitialized tb->orig_tb

Richard Henderson (8):
      exec: Split out variable page size support to exec-vary.c
      configure: Detect compiler support for __attribute__((alias))
      exec: Use const alias for TARGET_PAGE_BITS_VARY
      exec: Restrict TARGET_PAGE_BITS_VARY assert to CONFIG_DEBUG_TCG
      exec: Promote TARGET_PAGE_MASK to target_long
      exec: Cache TARGET_PAGE_MASK for TARGET_PAGE_BITS_VARY
      cputlb: Fix tlb_vaddr_to_host
      translate-all: Remove tb_alloc

Stefan Weil (1):
      tci: Add implementation for INDEX_op_ld16u_i64

Wei Yang (1):
      cpu: use ROUND_UP() to define xxx_PAGE_ALIGN

From: Stefan Weil <sw@weilnetz.de>

This fixes "make check-tcg" on a Debian x86_64 host.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Tested-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20190410194838.10123-1-sw@weilnetz.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tci.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/tcg/tci.c b/tcg/tci.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -XXX,XX +XXX,XX @@ static void tci_write_reg8(tcg_target_ulong *regs, TCGReg index, uint8_t value)
     tci_write_reg(regs, index, value);
 }
 
+static void
+tci_write_reg16(tcg_target_ulong *regs, TCGReg index, uint16_t value)
+{
+    tci_write_reg(regs, index, value);
+}
+
 static void
 tci_write_reg32(tcg_target_ulong *regs, TCGReg index, uint32_t value)
 {
@@ -XXX,XX +XXX,XX @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
             tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2));
             break;
         case INDEX_op_ld8s_i32:
+            TODO();
+            break;
         case INDEX_op_ld16u_i32:
             TODO();
             break;
@@ -XXX,XX +XXX,XX @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
             tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2));
             break;
         case INDEX_op_ld8s_i64:
+            TODO();
+            break;
         case INDEX_op_ld16u_i64:
+            t0 = *tb_ptr++;
+            t1 = tci_read_r(regs, &tb_ptr);
+            t2 = tci_read_s32(&tb_ptr);
+            tci_write_reg16(regs, t0, *(uint16_t *)(t1 + t2));
+            break;
         case INDEX_op_ld16s_i64:
             TODO();
             break;
-- 
2.17.1

From: Alex Bennée <alex.bennee@linaro.org>

We document this in docs/devel/load-stores.rst so lets follow it. The
32 bit and 64 bit access functions have historically not included the
sign so we leave those as is. We also introduce some signed helpers
which are used for loading immediate values in the translator.

Fixes: 282dffc8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20191021150910.23216-1-alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu_ldst_template.h |  4 ++--
 tcg/tcg.h                        | 20 ++++++++++++++------
 accel/tcg/cputlb.c               | 24 +++++++++++++++++++++---
 target/cris/translate_v10.inc.c  |  3 +--
 4 files changed, 38 insertions(+), 13 deletions(-)

diff --git a/include/exec/cpu_ldst_template.h b/include/exec/cpu_ldst_template.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/cpu_ldst_template.h
+++ b/include/exec/cpu_ldst_template.h
@@ -XXX,XX +XXX,XX @@
 #ifdef SOFTMMU_CODE_ACCESS
 #define ADDR_READ addr_code
 #define MMUSUFFIX _cmmu
-#define URETSUFFIX SUFFIX
-#define SRETSUFFIX SUFFIX
+#define URETSUFFIX USUFFIX
+#define SRETSUFFIX glue(s, SUFFIX)
 #else
 #define ADDR_READ addr_read
 #define MMUSUFFIX _mmu
diff --git a/tcg/tcg.h b/tcg/tcg.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -XXX,XX +XXX,XX @@ void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
                        TCGMemOpIdx oi, uintptr_t retaddr);
 
-uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
+uint8_t helper_ret_ldub_cmmu(CPUArchState *env, target_ulong addr,
                             TCGMemOpIdx oi, uintptr_t retaddr);
-uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
+int8_t helper_ret_ldsb_cmmu(CPUArchState *env, target_ulong addr,
                             TCGMemOpIdx oi, uintptr_t retaddr);
+uint16_t helper_le_lduw_cmmu(CPUArchState *env, target_ulong addr,
+                             TCGMemOpIdx oi, uintptr_t retaddr);
+int16_t helper_le_ldsw_cmmu(CPUArchState *env, target_ulong addr,
+                             TCGMemOpIdx oi, uintptr_t retaddr);
 uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
                             TCGMemOpIdx oi, uintptr_t retaddr);
 uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
                             TCGMemOpIdx oi, uintptr_t retaddr);
-uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
-                            TCGMemOpIdx oi, uintptr_t retaddr);
+uint16_t helper_be_lduw_cmmu(CPUArchState *env, target_ulong addr,
+                             TCGMemOpIdx oi, uintptr_t retaddr);
+int16_t helper_be_ldsw_cmmu(CPUArchState *env, target_ulong addr,
+                             TCGMemOpIdx oi, uintptr_t retaddr);
 uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
                             TCGMemOpIdx oi, uintptr_t retaddr);
 uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
@@ -XXX,XX +XXX,XX @@ uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
 # define helper_ret_stw_mmu   helper_be_stw_mmu
 # define helper_ret_stl_mmu   helper_be_stl_mmu
 # define helper_ret_stq_mmu   helper_be_stq_mmu
-# define helper_ret_ldw_cmmu  helper_be_ldw_cmmu
+# define helper_ret_lduw_cmmu  helper_be_lduw_cmmu
+# define helper_ret_ldsw_cmmu  helper_be_ldsw_cmmu
 # define helper_ret_ldl_cmmu  helper_be_ldl_cmmu
 # define helper_ret_ldq_cmmu  helper_be_ldq_cmmu
 #else
@@ -XXX,XX +XXX,XX @@ uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
 # define helper_ret_stw_mmu   helper_le_stw_mmu
 # define helper_ret_stl_mmu   helper_le_stl_mmu
 # define helper_ret_stq_mmu   helper_le_stq_mmu
-# define helper_ret_ldw_cmmu  helper_le_ldw_cmmu
+# define helper_ret_lduw_cmmu  helper_le_lduw_cmmu
+# define helper_ret_ldsw_cmmu  helper_le_ldsw_cmmu
 # define helper_ret_ldl_cmmu  helper_le_ldl_cmmu
 # define helper_ret_ldq_cmmu  helper_le_ldq_cmmu
 #endif
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static uint64_t full_ldub_cmmu(CPUArchState *env, target_ulong addr,
     return load_helper(env, addr, oi, retaddr, MO_8, true, full_ldub_cmmu);
 }
 
-uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
+uint8_t helper_ret_ldub_cmmu(CPUArchState *env, target_ulong addr,
                             TCGMemOpIdx oi, uintptr_t retaddr)
 {
     return full_ldub_cmmu(env, addr, oi, retaddr);
 }
 
+int8_t helper_ret_ldsb_cmmu(CPUArchState *env, target_ulong addr,
+                            TCGMemOpIdx oi, uintptr_t retaddr)
+{
+    return (int8_t) full_ldub_cmmu(env, addr, oi, retaddr);
+}
+
 static uint64_t full_le_lduw_cmmu(CPUArchState *env, target_ulong addr,
                                   TCGMemOpIdx oi, uintptr_t retaddr)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t full_le_lduw_cmmu(CPUArchState *env, target_ulong addr,
                        full_le_lduw_cmmu);
 }
 
-uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
+uint16_t helper_le_lduw_cmmu(CPUArchState *env, target_ulong addr,
                             TCGMemOpIdx oi, uintptr_t retaddr)
 {
     return full_le_lduw_cmmu(env, addr, oi, retaddr);
 }
 
+int16_t helper_le_ldsw_cmmu(CPUArchState *env, target_ulong addr,
+                            TCGMemOpIdx oi, uintptr_t retaddr)
+{
+    return (int16_t) full_le_lduw_cmmu(env, addr, oi, retaddr);
+}
+
 static uint64_t full_be_lduw_cmmu(CPUArchState *env, target_ulong addr,
                                   TCGMemOpIdx oi, uintptr_t retaddr)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t full_be_lduw_cmmu(CPUArchState *env, target_ulong addr,
                        full_be_lduw_cmmu);
 }
 
-uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
+uint16_t helper_be_lduw_cmmu(CPUArchState *env, target_ulong addr,
                             TCGMemOpIdx oi, uintptr_t retaddr)
 {
     return full_be_lduw_cmmu(env, addr, oi, retaddr);
 }
 
+int16_t helper_be_ldsw_cmmu(CPUArchState *env, target_ulong addr,
+                            TCGMemOpIdx oi, uintptr_t retaddr)
+{
+    return (int16_t) full_be_lduw_cmmu(env, addr, oi, retaddr);
+}
+
 static uint64_t full_le_ldul_cmmu(CPUArchState *env, target_ulong addr,
                                   TCGMemOpIdx oi, uintptr_t retaddr)
 {
diff --git a/target/cris/translate_v10.inc.c b/target/cris/translate_v10.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/cris/translate_v10.inc.c
+++ b/target/cris/translate_v10.inc.c
@@ -XXX,XX +XXX,XX @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
         case CRISV10_IND_BCC_M:
 
             cris_cc_mask(dc, 0);
-            imm = cpu_ldsw_code(env, dc->pc + 2);
-            simm = (int16_t)imm;
+            simm = cpu_ldsw_code(env, dc->pc + 2);
             simm += 4;
 
             LOG_DIS("bcc_m: b%s %x\n", cc_name(dc->cond), dc->pc + simm);
-- 
2.17.1

From: Wei Yang <richardw.yang@linux.intel.com>

Use ROUND_UP() to define, which is a little bit easy to read.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Wei Yang <richardw.yang@linux.intel.com>
Message-Id: <20191013021145.16011-2-richardw.yang@linux.intel.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu-all.h | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -XXX,XX +XXX,XX @@ extern int target_page_bits;
 
 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
-#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
+#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
 
 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even
  * when intptr_t is 32-bit and we are aligning a long long.
@@ -XXX,XX +XXX,XX @@ extern int target_page_bits;
 extern uintptr_t qemu_host_page_size;
 extern intptr_t qemu_host_page_mask;
 
-#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
-#define REAL_HOST_PAGE_ALIGN(addr) (((addr) + qemu_real_host_page_size - 1) & \
-                                    qemu_real_host_page_mask)
+#define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size)
+#define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size)
 
 /* same as PROT_xxx */
 #define PAGE_READ      0x0001
-- 
2.17.1

The next patch will play a trick with "const" that will
confuse the compiler about the uses of target_page_bits
within exec.c.  Moving everything to a new file prevents
this confusion.

No functional change so far.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 Makefile.target       |  2 +-
 include/qemu-common.h |  6 +++++
 exec-vary.c           | 57 +++++++++++++++++++++++++++++++++++++++++++
 exec.c                | 34 --------------------------
 4 files changed, 64 insertions(+), 35 deletions(-)
 create mode 100644 exec-vary.c

diff --git a/Makefile.target b/Makefile.target
index XXXXXXX..XXXXXXX 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -XXX,XX +XXX,XX @@ obj-y += trace/
 
 #########################################################
 # cpu emulator library
-obj-y += exec.o
+obj-y += exec.o exec-vary.o
 obj-y += accel/
 obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/tcg-op-vec.o tcg/tcg-op-gvec.o
 obj-$(CONFIG_TCG) += tcg/tcg-common.o tcg/optimize.o
diff --git a/include/qemu-common.h b/include/qemu-common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/qemu-common.h
+++ b/include/qemu-common.h
@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu);
  */
 bool set_preferred_target_page_bits(int bits);
 
+/**
+ * finalize_target_page_bits:
+ * Commit the final value set by set_preferred_target_page_bits.
+ */
+void finalize_target_page_bits(void);
+
 /**
  * Sends a (part of) iovec down a socket, yielding when the socket is full, or
  * Receives data into a (part of) iovec from a socket,
diff --git a/exec-vary.c b/exec-vary.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/exec-vary.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Variable page size handling
+ *
+ *  Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "exec/exec-all.h"
+
+#ifdef TARGET_PAGE_BITS_VARY
+int target_page_bits;
+bool target_page_bits_decided;
+#endif
+
+bool set_preferred_target_page_bits(int bits)
+{
+    /*
+     * The target page size is the lowest common denominator for all
+     * the CPUs in the system, so we can only make it smaller, never
+     * larger. And we can't make it smaller once we've committed to
+     * a particular size.
+     */
+#ifdef TARGET_PAGE_BITS_VARY
+    assert(bits >= TARGET_PAGE_BITS_MIN);
+    if (target_page_bits == 0 || target_page_bits > bits) {
+        if (target_page_bits_decided) {
+            return false;
+        }
+        target_page_bits = bits;
+    }
+#endif
+    return true;
+}
+
+void finalize_target_page_bits(void)
+{
+#ifdef TARGET_PAGE_BITS_VARY
+    if (target_page_bits == 0) {
+        target_page_bits = TARGET_PAGE_BITS_MIN;
+    }
+    target_page_bits_decided = true;
+#endif
+}
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ AddressSpace address_space_memory;
 static MemoryRegion io_mem_unassigned;
 #endif
 
-#ifdef TARGET_PAGE_BITS_VARY
-int target_page_bits;
-bool target_page_bits_decided;
-#endif
-
 CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
 
 /* current CPU in the current thread. It is only valid inside
@@ -XXX,XX +XXX,XX @@ int use_icount;
 uintptr_t qemu_host_page_size;
 intptr_t qemu_host_page_mask;
 
-bool set_preferred_target_page_bits(int bits)
-{
-    /* The target page size is the lowest common denominator for all
-     * the CPUs in the system, so we can only make it smaller, never
-     * larger. And we can't make it smaller once we've committed to
-     * a particular size.
-     */
-#ifdef TARGET_PAGE_BITS_VARY
-    assert(bits >= TARGET_PAGE_BITS_MIN);
-    if (target_page_bits == 0 || target_page_bits > bits) {
-        if (target_page_bits_decided) {
-            return false;
-        }
-        target_page_bits = bits;
-    }
-#endif
-    return true;
-}
-
 #if !defined(CONFIG_USER_ONLY)
 
-static void finalize_target_page_bits(void)
-{
-#ifdef TARGET_PAGE_BITS_VARY
-    if (target_page_bits == 0) {
-        target_page_bits = TARGET_PAGE_BITS_MIN;
-    }
-    target_page_bits_decided = true;
-#endif
-}
-
 typedef struct PhysPageEntry PhysPageEntry;
 
 struct PhysPageEntry {
-- 
2.17.1

Such support is present almost everywhere, except for Xcode 9.
It is added in Xcode 10, but travis uses xcode9 by default,
so we should support it for a while yet.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 configure | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/configure b/configure
index XXXXXXX..XXXXXXX 100755
--- a/configure
+++ b/configure
@@ -XXX,XX +XXX,XX @@ if compile_prog "" "" ; then
   vector16=yes
 fi
 
+########################################
+# See if __attribute__((alias)) is supported.
+# This false for Xcode 9, but has been remedied for Xcode 10.
+# Unfortunately, travis uses Xcode 9 by default.
+
+attralias=no
+cat > $TMPC << EOF
+int x = 1;
+extern const int y __attribute__((alias("x")));
+int main(void) { return 0; }
+EOF
+if compile_prog "" "" ; then
+    attralias=yes
+fi
+
 ########################################
 # check if getauxval is available.
 
@@ -XXX,XX +XXX,XX @@ if test "$vector16" = "yes" ; then
   echo "CONFIG_VECTOR16=y" >> $config_host_mak
 fi
 
+if test "$attralias" = "yes" ; then
+  echo "CONFIG_ATTRIBUTE_ALIAS=y" >> $config_host_mak
+fi
+
 if test "$getauxval" = "yes" ; then
   echo "CONFIG_GETAUXVAL=y" >> $config_host_mak
 fi
-- 
2.17.1

Using a variable that is declared "const" for this tells the
compiler that it may read the value once and assume that it
does not change across function calls.

For target_page_size, this means we have only one assert per
function, and one read of the variable.

This reduces the size of qemu-system-aarch64 by 8k.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu-all.h | 14 ++++++---
 exec-vary.c            | 66 +++++++++++++++++++++++++++++++++++++-----
 2 files changed, 68 insertions(+), 12 deletions(-)

diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -XXX,XX +XXX,XX @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val
 /* page related stuff */
 
 #ifdef TARGET_PAGE_BITS_VARY
-extern bool target_page_bits_decided;
-extern int target_page_bits;
-#define TARGET_PAGE_BITS ({ assert(target_page_bits_decided); \
-                            target_page_bits; })
+typedef struct {
+    bool decided;
+    int bits;
+} TargetPageBits;
+#if defined(CONFIG_ATTRIBUTE_ALIAS) || !defined(IN_EXEC_VARY)
+extern const TargetPageBits target_page;
+#else
+extern TargetPageBits target_page;
+#endif
+#define TARGET_PAGE_BITS   ({ assert(target_page.decided); target_page.bits; })
 #else
 #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
 #endif
diff --git a/exec-vary.c b/exec-vary.c
index XXXXXXX..XXXXXXX 100644
--- a/exec-vary.c
+++ b/exec-vary.c
@@ -XXX,XX +XXX,XX @@
 
 #include "qemu/osdep.h"
 #include "qemu-common.h"
+
+#define IN_EXEC_VARY 1
+
 #include "exec/exec-all.h"
 
 #ifdef TARGET_PAGE_BITS_VARY
-int target_page_bits;
-bool target_page_bits_decided;
+# ifdef CONFIG_ATTRIBUTE_ALIAS
+/*
+ * We want to declare the "target_page" variable as const, which tells
+ * the compiler that it can cache any value that it reads across calls.
+ * This avoids multiple assertions and multiple reads within any one user.
+ *
+ * This works because we finish initializing the data before we ever read
+ * from the "target_page" symbol.
+ *
+ * This also requires that we have a non-constant symbol by which we can
+ * perform the actual initialization, and which forces the data to be
+ * allocated within writable memory.  Thus "init_target_page", and we use
+ * that symbol exclusively in the two functions that initialize this value.
+ *
+ * The "target_page" symbol is created as an alias of "init_target_page".
+ */
+static TargetPageBits init_target_page;
+
+/*
+ * Note that this is *not* a redundant decl, this is the definition of
+ * the "target_page" symbol.  The syntax for this definition requires
+ * the use of the extern keyword.  This seems to be a GCC bug in
+ * either the syntax for the alias attribute or in -Wredundant-decls.
+ *
+ * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91765
+ */
+#  pragma GCC diagnostic push
+#  pragma GCC diagnostic ignored "-Wredundant-decls"
+
+extern const TargetPageBits target_page
+    __attribute__((alias("init_target_page")));
+
+#  pragma GCC diagnostic pop
+# else
+/*
+ * When aliases are not supported then we force two different declarations,
+ * by way of suppressing the header declaration with IN_EXEC_VARY.
+ * We assume that on such an old compiler, LTO cannot be used, and so the
+ * compiler cannot not detect the mismatched declarations, and all is well.
+ */
+TargetPageBits target_page;
+#  define init_target_page target_page
+# endif
 #endif
 
 bool set_preferred_target_page_bits(int bits)
@@ -XXX,XX +XXX,XX @@ bool set_preferred_target_page_bits(int bits)
      */
 #ifdef TARGET_PAGE_BITS_VARY
     assert(bits >= TARGET_PAGE_BITS_MIN);
-    if (target_page_bits == 0 || target_page_bits > bits) {
-        if (target_page_bits_decided) {
+    if (init_target_page.bits == 0 || init_target_page.bits > bits) {
+        if (init_target_page.decided) {
             return false;
         }
-        target_page_bits = bits;
+        init_target_page.bits = bits;
     }
 #endif
     return true;
@@ -XXX,XX +XXX,XX @@ bool set_preferred_target_page_bits(int bits)
 void finalize_target_page_bits(void)
 {
 #ifdef TARGET_PAGE_BITS_VARY
-    if (target_page_bits == 0) {
-        target_page_bits = TARGET_PAGE_BITS_MIN;
+    if (init_target_page.bits == 0) {
+        init_target_page.bits = TARGET_PAGE_BITS_MIN;
     }
-    target_page_bits_decided = true;
+    init_target_page.decided = true;
+
+    /*
+     * For the benefit of an -flto build, prevent the compiler from
+     * hoisting a read from target_page before we finish initializing.
+     */
+    barrier();
 #endif
 }
-- 
2.17.1

There are some uint64_t uses that expect TARGET_PAGE_MASK to
extend for a 32-bit, so this must continue to be a signed type.
Define based on TARGET_PAGE_BITS not TARGET_PAGE_SIZE; this
will make a following patch more clear.

This should not have a functional effect so far.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu-all.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -XXX,XX +XXX,XX @@ extern TargetPageBits target_page;
 #endif
 
 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
-#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
+#define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS)
 #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
 
 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even
-- 
2.17.1

This eliminates a set of runtime shifts.  It turns out that we
require TARGET_PAGE_MASK more often than TARGET_PAGE_SIZE, so
redefine TARGET_PAGE_SIZE based on TARGET_PAGE_MASK instead of
the other way around.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu-all.h | 8 ++++++--
 exec-vary.c            | 1 +
 2 files changed, 7 insertions(+), 2 deletions(-)

From: Clement Deschamps <clement.deschamps@greensocs.com>

This fixes a segmentation fault in icount mode when executing
from an IO region.

TB is marked as CF_NOCACHE but tb->orig_tb is not initialized
(equals previous value in code_gen_buffer).

The issue happens in cpu_io_recompile() when it tries to invalidate orig_tb.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Clement Deschamps <clement.deschamps@greensocs.com>
Message-Id: <20191022140016.918371-1-clement.deschamps@greensocs.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/translate-all.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
     tb->cs_base = cs_base;
     tb->flags = flags;
     tb->cflags = cflags;
+    tb->orig_tb = NULL;
     tb->trace_vcpu_dstate = *cpu->trace_dstate;
     tcg_ctx->tb_cflags = cflags;
  tb_overflow:
-- 
2.17.1

Since 2ac01d6dafab, this function does only two things: assert a
lock is held, and call tcg_tb_alloc.  It is used exactly once,
and its user has already done the assert.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Clement Deschamps <clement.deschamps@greensocs.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/translate-all.c | 20 ++------------------
 1 file changed, 2 insertions(+), 18 deletions(-)

diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ void tcg_exec_init(unsigned long tb_size)
 #endif
 }
 
-/*
- * Allocate a new translation block. Flush the translation buffer if
- * too many translation blocks or too much generated code.
- */
-static TranslationBlock *tb_alloc(target_ulong pc)
-{
-    TranslationBlock *tb;
-
-    assert_memory_lock();
-
-    tb = tcg_tb_alloc(tcg_ctx);
-    if (unlikely(tb == NULL)) {
-        return NULL;
-    }
-    return tb;
-}
-
 /* call with @p->lock held */
 static inline void invalidate_page_bitmap(PageDesc *p)
 {
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
     TCGProfile *prof = &tcg_ctx->prof;
     int64_t ti;
 #endif
+
     assert_memory_lock();
 
     phys_pc = get_page_addr_code(env, pc);
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
     }
 
  buffer_overflow:
-    tb = tb_alloc(pc);
+    tb = tcg_tb_alloc(tcg_ctx);
     if (unlikely(!tb)) {
         /* flush must be done */
         tb_flush(cpu);
-- 
2.17.1

v2: Fix FreeBSD build error in patch 18.

The following changes since commit 0d239e513e0117e66fa739fb71a43b9383a108ff:

Merge tag 'pull-lu-20231018' of https://gitlab.com/rth7680/qemu into staging (2023-10-19 10:20:57 -0700)

are available in the Git repository at:

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20231018-2

for you to fetch changes up to a75f704d972b9408f5e2843784b3add48c724c52:

target/i386: Use i128 for 128 and 256-bit loads and stores (2023-10-19 21:11:44 -0700)

----------------------------------------------------------------
tcg: Drop unused tcg_temp_free define
tcg: Introduce tcg_use_softmmu
tcg: Optimize past conditional branches
tcg: Use constant zero when expanding with divu2
tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TB
tcg/ppc: Use ADDPCIS for power9
tcg/ppc: Use prefixed instructions for power10
tcg/ppc: Disable TCG_REG_TB for Power9/Power10

----------------------------------------------------------------
Jordan Niethe (1):
      tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TB

Mike Frysinger (1):
      tcg: drop unused tcg_temp_free define

Richard Henderson (27):
      tcg/ppc: Untabify tcg-target.c.inc
      tcg/ppc: Reinterpret tb-relative to TB+4
      tcg/ppc: Use ADDPCIS in tcg_out_tb_start
      tcg/ppc: Use ADDPCIS in tcg_out_movi_int
      tcg/ppc: Use ADDPCIS for the constant pool
      tcg/ppc: Use ADDPCIS in tcg_out_goto_tb
      tcg/ppc: Use PADDI in tcg_out_movi
      tcg/ppc: Use prefixed instructions in tcg_out_mem_long
      tcg/ppc: Use PLD in tcg_out_movi for constant pool
      tcg/ppc: Use prefixed instructions in tcg_out_dupi_vec
      tcg/ppc: Use PLD in tcg_out_goto_tb
      tcg/ppc: Disable TCG_REG_TB for Power9/Power10
      tcg: Introduce tcg_use_softmmu
      tcg: Provide guest_base fallback for system mode
      tcg/arm: Use tcg_use_softmmu
      tcg/aarch64: Use tcg_use_softmmu
      tcg/i386: Use tcg_use_softmmu
      tcg/loongarch64: Use tcg_use_softmmu
      tcg/mips: Use tcg_use_softmmu
      tcg/ppc: Use tcg_use_softmmu
      tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zero
      tcg/riscv: Use tcg_use_softmmu
      tcg/s390x: Use tcg_use_softmmu
      tcg: Use constant zero when expanding with divu2
      tcg: Optimize past conditional branches
      tcg: Add tcg_gen_{ld,st}_i128
      target/i386: Use i128 for 128 and 256-bit loads and stores

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.c.inc | 198 +++++++++++++++++++-------------------
 1 file changed, 98 insertions(+), 100 deletions(-)

diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
 # define ALL_VECTOR_REGS       0x00ff0000u
 # define ALL_BYTEL_REGS        0x0000000fu
 #endif
-#ifdef CONFIG_SOFTMMU
-# define SOFTMMU_RESERVE_REGS  ((1 << TCG_REG_L0) | (1 << TCG_REG_L1))
-#else
-# define SOFTMMU_RESERVE_REGS  0
-#endif
+#define SOFTMMU_RESERVE_REGS \
+    (tcg_use_softmmu ? (1 << TCG_REG_L0) | (1 << TCG_REG_L1) : 0)
 
 /* For 64-bit, we always know that CMOV is available.  */
 #if TCG_TARGET_REG_BITS == 64
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
     return true;
 }
 
-#ifndef CONFIG_SOFTMMU
+#ifdef CONFIG_USER_ONLY
 static HostAddress x86_guest_base = {
     .index = -1
 };
@@ -XXX,XX +XXX,XX @@ static inline int setup_guest_base_seg(void)
     }
     return 0;
 }
+#define setup_guest_base_seg  setup_guest_base_seg
 #elif defined(__x86_64__) && \
       (defined (__FreeBSD__) || defined (__FreeBSD_kernel__))
 # include <machine/sysarch.h>
@@ -XXX,XX +XXX,XX @@ static inline int setup_guest_base_seg(void)
     }
     return 0;
 }
+#define setup_guest_base_seg  setup_guest_base_seg
+#endif
 #else
-static inline int setup_guest_base_seg(void)
-{
-    return 0;
-}
-#endif /* setup_guest_base_seg */
-#endif /* !SOFTMMU */
+# define x86_guest_base (*(HostAddress *)({ qemu_build_not_reached(); NULL; }))
+#endif /* CONFIG_USER_ONLY */
+#ifndef setup_guest_base_seg
+# define setup_guest_base_seg()  0
+#endif
 
 #define MIN_TLB_MASK_TABLE_OFS  INT_MIN
 
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
     MemOp s_bits = opc & MO_SIZE;
     unsigned a_mask;
 
-#ifdef CONFIG_SOFTMMU
-    h->index = TCG_REG_L0;
-    h->ofs = 0;
-    h->seg = 0;
-#else
-    *h = x86_guest_base;
-#endif
+    if (tcg_use_softmmu) {
+        h->index = TCG_REG_L0;
+        h->ofs = 0;
+        h->seg = 0;
+    } else {
+        *h = x86_guest_base;
+    }
     h->base = addrlo;
     h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128);
     a_mask = (1 << h->aa.align) - 1;
 
-#ifdef CONFIG_SOFTMMU
-    int cmp_ofs = is_ld ? offsetof(CPUTLBEntry, addr_read)
-                        : offsetof(CPUTLBEntry, addr_write);
-    TCGType ttype = TCG_TYPE_I32;
-    TCGType tlbtype = TCG_TYPE_I32;
-    int trexw = 0, hrexw = 0, tlbrexw = 0;
-    unsigned mem_index = get_mmuidx(oi);
-    unsigned s_mask = (1 << s_bits) - 1;
-    int fast_ofs = tlb_mask_table_ofs(s, mem_index);
-    int tlb_mask;
+    if (tcg_use_softmmu) {
+        int cmp_ofs = is_ld ? offsetof(CPUTLBEntry, addr_read)
+                            : offsetof(CPUTLBEntry, addr_write);
+        TCGType ttype = TCG_TYPE_I32;
+        TCGType tlbtype = TCG_TYPE_I32;
+        int trexw = 0, hrexw = 0, tlbrexw = 0;
+        unsigned mem_index = get_mmuidx(oi);
+        unsigned s_mask = (1 << s_bits) - 1;
+        int fast_ofs = tlb_mask_table_ofs(s, mem_index);
+        int tlb_mask;
 
-    ldst = new_ldst_label(s);
-    ldst->is_ld = is_ld;
-    ldst->oi = oi;
-    ldst->addrlo_reg = addrlo;
-    ldst->addrhi_reg = addrhi;
+        ldst = new_ldst_label(s);
+        ldst->is_ld = is_ld;
+        ldst->oi = oi;
+        ldst->addrlo_reg = addrlo;
+        ldst->addrhi_reg = addrhi;
 
-    if (TCG_TARGET_REG_BITS == 64) {
-        ttype = s->addr_type;
-        trexw = (ttype == TCG_TYPE_I32 ? 0 : P_REXW);
-        if (TCG_TYPE_PTR == TCG_TYPE_I64) {
-            hrexw = P_REXW;
-            if (s->page_bits + s->tlb_dyn_max_bits > 32) {
-                tlbtype = TCG_TYPE_I64;
-                tlbrexw = P_REXW;
+        if (TCG_TARGET_REG_BITS == 64) {
+            ttype = s->addr_type;
+            trexw = (ttype == TCG_TYPE_I32 ? 0 : P_REXW);
+            if (TCG_TYPE_PTR == TCG_TYPE_I64) {
+                hrexw = P_REXW;
+                if (s->page_bits + s->tlb_dyn_max_bits > 32) {
+                    tlbtype = TCG_TYPE_I64;
+                    tlbrexw = P_REXW;
+                }
             }
         }
-    }
 
-    tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo);
-    tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0,
-                   s->page_bits - CPU_TLB_ENTRY_BITS);
+        tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo);
+        tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0,
+                       s->page_bits - CPU_TLB_ENTRY_BITS);
 
-    tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0,
-                         fast_ofs + offsetof(CPUTLBDescFast, mask));
+        tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0,
+                             fast_ofs + offsetof(CPUTLBDescFast, mask));
 
-    tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0,
-                         fast_ofs + offsetof(CPUTLBDescFast, table));
+        tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0,
+                             fast_ofs + offsetof(CPUTLBDescFast, table));
 
-    /*
-     * If the required alignment is at least as large as the access, simply
-     * copy the address and mask.  For lesser alignments, check that we don't
-     * cross pages for the complete access.
-     */
-    if (a_mask >= s_mask) {
-        tcg_out_mov(s, ttype, TCG_REG_L1, addrlo);
-    } else {
-        tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1,
-                             addrlo, s_mask - a_mask);
-    }
-    tlb_mask = s->page_mask | a_mask;
-    tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0);
+        /*
+         * If the required alignment is at least as large as the access,
+         * simply copy the address and mask.  For lesser alignments,
+         * check that we don't cross pages for the complete access.
+         */
+        if (a_mask >= s_mask) {
+            tcg_out_mov(s, ttype, TCG_REG_L1, addrlo);
+        } else {
+            tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1,
+                                 addrlo, s_mask - a_mask);
+        }
+        tlb_mask = s->page_mask | a_mask;
+        tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0);
 
-    /* cmp 0(TCG_REG_L0), TCG_REG_L1 */
-    tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw,
-                         TCG_REG_L1, TCG_REG_L0, cmp_ofs);
-
-    /* jne slow_path */
-    tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
-    ldst->label_ptr[0] = s->code_ptr;
-    s->code_ptr += 4;
-
-    if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I64) {
-        /* cmp 4(TCG_REG_L0), addrhi */
-        tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, TCG_REG_L0, cmp_ofs + 4);
+        /* cmp 0(TCG_REG_L0), TCG_REG_L1 */
+        tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw,
+                             TCG_REG_L1, TCG_REG_L0, cmp_ofs);
 
         /* jne slow_path */
         tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
-        ldst->label_ptr[1] = s->code_ptr;
+        ldst->label_ptr[0] = s->code_ptr;
         s->code_ptr += 4;
-    }
 
-    /* TLB Hit.  */
-    tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0,
-               offsetof(CPUTLBEntry, addend));
-#else
-    if (a_mask) {
+        if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I64) {
+            /* cmp 4(TCG_REG_L0), addrhi */
+            tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi,
+                                 TCG_REG_L0, cmp_ofs + 4);
+
+            /* jne slow_path */
+            tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
+            ldst->label_ptr[1] = s->code_ptr;
+            s->code_ptr += 4;
+        }
+
+        /* TLB Hit.  */
+        tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0,
+                   offsetof(CPUTLBEntry, addend));
+    } else if (a_mask) {
         ldst = new_ldst_label(s);
 
         ldst->is_ld = is_ld;
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
         ldst->label_ptr[0] = s->code_ptr;
         s->code_ptr += 4;
     }
-#endif
 
     return ldst;
 }
@@ -XXX,XX +XXX,XX @@ static void tcg_target_qemu_prologue(TCGContext *s)
         tcg_out_push(s, tcg_target_callee_save_regs[i]);
     }
 
-#if TCG_TARGET_REG_BITS == 32
-    tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP,
-               (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4);
-    tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
-    /* jmp *tb.  */
-    tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP,
-                         (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4
-                         + stack_addend);
-#else
-# if !defined(CONFIG_SOFTMMU)
-    if (guest_base) {
+    if (!tcg_use_softmmu && guest_base) {
         int seg = setup_guest_base_seg();
         if (seg != 0) {
             x86_guest_base.seg = seg;
         } else if (guest_base == (int32_t)guest_base) {
             x86_guest_base.ofs = guest_base;
         } else {
+            assert(TCG_TARGET_REG_BITS == 64);
             /* Choose R12 because, as a base, it requires a SIB byte. */
             x86_guest_base.index = TCG_REG_R12;
             tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base.index, guest_base);
             tcg_regset_set_reg(s->reserved_regs, x86_guest_base.index);
         }
     }
-# endif
-    tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
-    tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
-    /* jmp *tb.  */
-    tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]);
-#endif
+
+    if (TCG_TARGET_REG_BITS == 32) {
+        tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP,
+                   (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4);
+        tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
+        /* jmp *tb.  */
+        tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP,
+                             (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4
+                             + stack_addend);
+    } else {
+        tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
+        tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
+        /* jmp *tb.  */
+        tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]);
+    }
 
     /*
      * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
-- 
2.34.1