1
The following changes since commit bad76ac319556dab2497429d473b49a237672e1c:
1
The following changes since commit 6587b0c1331d427b0939c37e763842550ed581db:
2
2
3
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-request' into staging (2019-10-25 14:17:08 +0100)
3
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2021-10-15' into staging (2021-10-15 14:16:28 -0700)
4
4
5
are available in the Git repository at:
5
are available in the Git repository at:
6
6
7
https://github.com/rth7680/qemu.git tags/pull-tcg-20191025
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211016
8
8
9
for you to fetch changes up to 0ed1bfb046b740b70eed2cf3581e01768703b185:
9
for you to fetch changes up to 995b87dedc78b0467f5f18bbc3546072ba97516a:
10
10
11
translate-all: Remove tb_alloc (2019-10-25 10:15:25 -0400)
11
Revert "cpu: Move cpu_common_props to hw/core/cpu.c" (2021-10-15 16:39:15 -0700)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
Improvements for TARGET_PAGE_BITS_VARY
14
Move gdb singlestep to generic code
15
Fix for TCI ld16u_i64.
15
Fix cpu_common_props
16
Fix for segv on icount execute from i/o memory.
17
Two misc cleanups.
18
16
19
----------------------------------------------------------------
17
----------------------------------------------------------------
20
Alex Bennée (1):
18
Richard Henderson (24):
21
cputlb: ensure _cmmu helper functions follow the naming standard
19
accel/tcg: Handle gdb singlestep in cpu_tb_exec
20
target/alpha: Drop checks for singlestep_enabled
21
target/avr: Drop checks for singlestep_enabled
22
target/cris: Drop checks for singlestep_enabled
23
target/hexagon: Drop checks for singlestep_enabled
24
target/arm: Drop checks for singlestep_enabled
25
target/hppa: Drop checks for singlestep_enabled
26
target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt
27
target/i386: Drop check for singlestep_enabled
28
target/m68k: Drop checks for singlestep_enabled
29
target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP
30
target/microblaze: Drop checks for singlestep_enabled
31
target/mips: Fix single stepping
32
target/mips: Drop exit checks for singlestep_enabled
33
target/openrisc: Drop checks for singlestep_enabled
34
target/ppc: Drop exit checks for singlestep_enabled
35
target/riscv: Remove dead code after exception
36
target/riscv: Remove exit_tb and lookup_and_goto_ptr
37
target/rx: Drop checks for singlestep_enabled
38
target/s390x: Drop check for singlestep_enabled
39
target/sh4: Drop check for singlestep_enabled
40
target/tricore: Drop check for singlestep_enabled
41
target/xtensa: Drop check for singlestep_enabled
42
Revert "cpu: Move cpu_common_props to hw/core/cpu.c"
22
43
23
Clement Deschamps (1):
44
include/hw/core/cpu.h | 1 +
24
translate-all: fix uninitialized tb->orig_tb
45
target/i386/helper.h | 1 -
46
target/rx/helper.h | 1 -
47
target/sh4/helper.h | 1 -
48
target/tricore/helper.h | 1 -
49
accel/tcg/cpu-exec.c | 11 ++++
50
cpu.c | 21 ++++++++
51
hw/core/cpu-common.c | 17 +-----
52
target/alpha/translate.c | 13 ++---
53
target/arm/translate-a64.c | 10 +---
54
target/arm/translate.c | 36 +++----------
55
target/avr/translate.c | 19 ++-----
56
target/cris/translate.c | 16 ------
57
target/hexagon/translate.c | 12 +----
58
target/hppa/translate.c | 17 ++----
59
target/i386/tcg/misc_helper.c | 8 ---
60
target/i386/tcg/translate.c | 9 ++--
61
target/m68k/translate.c | 44 ++++-----------
62
target/microblaze/translate.c | 18 ++-----
63
target/mips/tcg/translate.c | 75 ++++++++++++--------------
64
target/openrisc/translate.c | 18 ++-----
65
target/ppc/translate.c | 38 +++----------
66
target/riscv/translate.c | 27 +---------
67
target/rx/op_helper.c | 8 ---
68
target/rx/translate.c | 12 +----
69
target/s390x/tcg/translate.c | 8 +--
70
target/sh4/op_helper.c | 5 --
71
target/sh4/translate.c | 14 ++---
72
target/tricore/op_helper.c | 7 ---
73
target/tricore/translate.c | 14 +----
74
target/xtensa/translate.c | 25 +++------
75
target/riscv/insn_trans/trans_privileged.c.inc | 10 ++--
76
target/riscv/insn_trans/trans_rvi.c.inc | 8 ++-
77
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
78
34 files changed, 141 insertions(+), 386 deletions(-)
25
79
26
Richard Henderson (8):
27
exec: Split out variable page size support to exec-vary.c
28
configure: Detect compiler support for __attribute__((alias))
29
exec: Use const alias for TARGET_PAGE_BITS_VARY
30
exec: Restrict TARGET_PAGE_BITS_VARY assert to CONFIG_DEBUG_TCG
31
exec: Promote TARGET_PAGE_MASK to target_long
32
exec: Cache TARGET_PAGE_MASK for TARGET_PAGE_BITS_VARY
33
cputlb: Fix tlb_vaddr_to_host
34
translate-all: Remove tb_alloc
35
36
Stefan Weil (1):
37
tci: Add implementation for INDEX_op_ld16u_i64
38
39
Wei Yang (1):
40
cpu: use ROUND_UP() to define xxx_PAGE_ALIGN
41
42
Makefile.target | 2 +-
43
include/exec/cpu-all.h | 33 +++++++++----
44
include/exec/cpu_ldst_template.h | 4 +-
45
include/qemu-common.h | 6 +++
46
tcg/tcg.h | 20 +++++---
47
accel/tcg/cputlb.c | 26 ++++++++--
48
accel/tcg/translate-all.c | 21 ++------
49
exec-vary.c | 102 +++++++++++++++++++++++++++++++++++++++
50
exec.c | 34 -------------
51
target/cris/translate_v10.inc.c | 3 +-
52
tcg/tci.c | 15 ++++++
53
configure | 19 ++++++++
54
12 files changed, 208 insertions(+), 77 deletions(-)
55
create mode 100644 exec-vary.c
56
diff view generated by jsdifflib
New patch
1
Currently the change in cpu_tb_exec is masked by the debug exception
2
being raised by the translators. But this allows us to remove that code.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
accel/tcg/cpu-exec.c | 11 +++++++++++
7
1 file changed, 11 insertions(+)
8
9
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/accel/tcg/cpu-exec.c
12
+++ b/accel/tcg/cpu-exec.c
13
@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
14
cc->set_pc(cpu, last_tb->pc);
15
}
16
}
17
+
18
+ /*
19
+ * If gdb single-step, and we haven't raised another exception,
20
+ * raise a debug exception. Single-step with another exception
21
+ * is handled in cpu_handle_exception.
22
+ */
23
+ if (unlikely(cpu->singlestep_enabled) && cpu->exception_index == -1) {
24
+ cpu->exception_index = EXCP_DEBUG;
25
+ cpu_loop_exit(cpu);
26
+ }
27
+
28
return last_tb;
29
}
30
31
--
32
2.25.1
33
34
diff view generated by jsdifflib
New patch
1
GDB single-stepping is now handled generically.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/alpha/translate.c | 13 +++----------
7
1 file changed, 3 insertions(+), 10 deletions(-)
8
9
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/alpha/translate.c
12
+++ b/target/alpha/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void alpha_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
14
tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next);
15
/* FALLTHRU */
16
case DISAS_PC_UPDATED:
17
- if (!ctx->base.singlestep_enabled) {
18
- tcg_gen_lookup_and_goto_ptr();
19
- break;
20
- }
21
- /* FALLTHRU */
22
+ tcg_gen_lookup_and_goto_ptr();
23
+ break;
24
case DISAS_PC_UPDATED_NOCHAIN:
25
- if (ctx->base.singlestep_enabled) {
26
- gen_excp_1(EXCP_DEBUG, 0);
27
- } else {
28
- tcg_gen_exit_tb(NULL, 0);
29
- }
30
+ tcg_gen_exit_tb(NULL, 0);
31
break;
32
default:
33
g_assert_not_reached();
34
--
35
2.25.1
36
37
diff view generated by jsdifflib
New patch
1
GDB single-stepping is now handled generically.
1
2
3
Tested-by: Michael Rolnik <mrolnik@gmail.com>
4
Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
target/avr/translate.c | 19 ++++---------------
9
1 file changed, 4 insertions(+), 15 deletions(-)
10
11
diff --git a/target/avr/translate.c b/target/avr/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/avr/translate.c
14
+++ b/target/avr/translate.c
15
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
16
tcg_gen_exit_tb(tb, n);
17
} else {
18
tcg_gen_movi_i32(cpu_pc, dest);
19
- if (ctx->base.singlestep_enabled) {
20
- gen_helper_debug(cpu_env);
21
- } else {
22
- tcg_gen_lookup_and_goto_ptr();
23
- }
24
+ tcg_gen_lookup_and_goto_ptr();
25
}
26
ctx->base.is_jmp = DISAS_NORETURN;
27
}
28
@@ -XXX,XX +XXX,XX @@ static void avr_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
29
tcg_gen_movi_tl(cpu_pc, ctx->npc);
30
/* fall through */
31
case DISAS_LOOKUP:
32
- if (!ctx->base.singlestep_enabled) {
33
- tcg_gen_lookup_and_goto_ptr();
34
- break;
35
- }
36
- /* fall through */
37
+ tcg_gen_lookup_and_goto_ptr();
38
+ break;
39
case DISAS_EXIT:
40
- if (ctx->base.singlestep_enabled) {
41
- gen_helper_debug(cpu_env);
42
- } else {
43
- tcg_gen_exit_tb(NULL, 0);
44
- }
45
+ tcg_gen_exit_tb(NULL, 0);
46
break;
47
default:
48
g_assert_not_reached();
49
--
50
2.25.1
51
52
diff view generated by jsdifflib
New patch
1
GDB single-stepping is now handled generically.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/cris/translate.c | 16 ----------------
6
1 file changed, 16 deletions(-)
7
8
diff --git a/target/cris/translate.c b/target/cris/translate.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/target/cris/translate.c
11
+++ b/target/cris/translate.c
12
@@ -XXX,XX +XXX,XX @@ static void cris_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
13
}
14
}
15
16
- if (unlikely(dc->base.singlestep_enabled)) {
17
- switch (is_jmp) {
18
- case DISAS_TOO_MANY:
19
- case DISAS_UPDATE_NEXT:
20
- tcg_gen_movi_tl(env_pc, npc);
21
- /* fall through */
22
- case DISAS_JUMP:
23
- case DISAS_UPDATE:
24
- t_gen_raise_exception(EXCP_DEBUG);
25
- return;
26
- default:
27
- break;
28
- }
29
- g_assert_not_reached();
30
- }
31
-
32
switch (is_jmp) {
33
case DISAS_TOO_MANY:
34
gen_goto_tb(dc, 0, npc);
35
--
36
2.25.1
37
38
diff view generated by jsdifflib
New patch
1
GDB single-stepping is now handled generically.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/hexagon/translate.c | 12 ++----------
7
1 file changed, 2 insertions(+), 10 deletions(-)
8
9
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/hexagon/translate.c
12
+++ b/target/hexagon/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void gen_end_tb(DisasContext *ctx)
14
{
15
gen_exec_counters(ctx);
16
tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
17
- if (ctx->base.singlestep_enabled) {
18
- gen_exception_raw(EXCP_DEBUG);
19
- } else {
20
- tcg_gen_exit_tb(NULL, 0);
21
- }
22
+ tcg_gen_exit_tb(NULL, 0);
23
ctx->base.is_jmp = DISAS_NORETURN;
24
}
25
26
@@ -XXX,XX +XXX,XX @@ static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
27
case DISAS_TOO_MANY:
28
gen_exec_counters(ctx);
29
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
30
- if (ctx->base.singlestep_enabled) {
31
- gen_exception_raw(EXCP_DEBUG);
32
- } else {
33
- tcg_gen_exit_tb(NULL, 0);
34
- }
35
+ tcg_gen_exit_tb(NULL, 0);
36
break;
37
case DISAS_NORETURN:
38
break;
39
--
40
2.25.1
41
42
diff view generated by jsdifflib
1
Since 2ac01d6dafab, this function does only two things: assert a
1
GDB single-stepping is now handled generically.
2
lock is held, and call tcg_tb_alloc. It is used exactly once,
3
and its user has already done the assert.
4
2
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Clement Deschamps <clement.deschamps@greensocs.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
4
---
9
accel/tcg/translate-all.c | 20 ++------------------
5
target/arm/translate-a64.c | 10 ++--------
10
1 file changed, 2 insertions(+), 18 deletions(-)
6
target/arm/translate.c | 36 ++++++------------------------------
7
2 files changed, 8 insertions(+), 38 deletions(-)
11
8
12
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
9
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
13
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
14
--- a/accel/tcg/translate-all.c
11
--- a/target/arm/translate-a64.c
15
+++ b/accel/tcg/translate-all.c
12
+++ b/target/arm/translate-a64.c
16
@@ -XXX,XX +XXX,XX @@ void tcg_exec_init(unsigned long tb_size)
13
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
17
#endif
14
gen_a64_set_pc_im(dest);
15
if (s->ss_active) {
16
gen_step_complete_exception(s);
17
- } else if (s->base.singlestep_enabled) {
18
- gen_exception_internal(EXCP_DEBUG);
19
} else {
20
tcg_gen_lookup_and_goto_ptr();
21
s->base.is_jmp = DISAS_NORETURN;
22
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
23
{
24
DisasContext *dc = container_of(dcbase, DisasContext, base);
25
26
- if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) {
27
+ if (unlikely(dc->ss_active)) {
28
/* Note that this means single stepping WFI doesn't halt the CPU.
29
* For conditional branch insns this is harmless unreachable code as
30
* gen_goto_tb() has already handled emitting the debug exception
31
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
32
/* fall through */
33
case DISAS_EXIT:
34
case DISAS_JUMP:
35
- if (dc->base.singlestep_enabled) {
36
- gen_exception_internal(EXCP_DEBUG);
37
- } else {
38
- gen_step_complete_exception(dc);
39
- }
40
+ gen_step_complete_exception(dc);
41
break;
42
case DISAS_NORETURN:
43
break;
44
diff --git a/target/arm/translate.c b/target/arm/translate.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/translate.c
47
+++ b/target/arm/translate.c
48
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
49
tcg_temp_free_i32(tcg_excp);
18
}
50
}
19
51
20
-/*
52
-static void gen_step_complete_exception(DisasContext *s)
21
- * Allocate a new translation block. Flush the translation buffer if
53
+static void gen_singlestep_exception(DisasContext *s)
22
- * too many translation blocks or too much generated code.
54
{
23
- */
55
/* We just completed step of an insn. Move from Active-not-pending
24
-static TranslationBlock *tb_alloc(target_ulong pc)
56
* to Active-pending, and then also take the swstep exception.
57
@@ -XXX,XX +XXX,XX @@ static void gen_step_complete_exception(DisasContext *s)
58
s->base.is_jmp = DISAS_NORETURN;
59
}
60
61
-static void gen_singlestep_exception(DisasContext *s)
25
-{
62
-{
26
- TranslationBlock *tb;
63
- /* Generate the right kind of exception for singlestep, which is
27
-
64
- * either the architectural singlestep or EXCP_DEBUG for QEMU's
28
- assert_memory_lock();
65
- * gdb singlestepping.
29
-
66
- */
30
- tb = tcg_tb_alloc(tcg_ctx);
67
- if (s->ss_active) {
31
- if (unlikely(tb == NULL)) {
68
- gen_step_complete_exception(s);
32
- return NULL;
69
- } else {
70
- gen_exception_internal(EXCP_DEBUG);
33
- }
71
- }
34
- return tb;
35
-}
72
-}
36
-
73
-
37
/* call with @p->lock held */
74
-static inline bool is_singlestepping(DisasContext *s)
38
static inline void invalidate_page_bitmap(PageDesc *p)
75
-{
76
- /* Return true if we are singlestepping either because of
77
- * architectural singlestep or QEMU gdbstub singlestep. This does
78
- * not include the command line '-singlestep' mode which is rather
79
- * misnamed as it only means "one instruction per TB" and doesn't
80
- * affect the code we generate.
81
- */
82
- return s->base.singlestep_enabled || s->ss_active;
83
-}
84
-
85
void clear_eci_state(DisasContext *s)
39
{
86
{
40
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
87
/*
41
TCGProfile *prof = &tcg_ctx->prof;
88
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret_final_code(DisasContext *s)
42
int64_t ti;
89
/* Is the new PC value in the magic range indicating exception return? */
43
#endif
90
tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label);
44
+
91
/* No: end the TB as we would for a DISAS_JMP */
45
assert_memory_lock();
92
- if (is_singlestepping(s)) {
46
93
+ if (s->ss_active) {
47
phys_pc = get_page_addr_code(env, pc);
94
gen_singlestep_exception(s);
48
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
95
} else {
96
tcg_gen_exit_tb(NULL, 0);
97
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
98
/* Jump, specifying which TB number to use if we gen_goto_tb() */
99
static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
100
{
101
- if (unlikely(is_singlestepping(s))) {
102
+ if (unlikely(s->ss_active)) {
103
/* An indirect jump so that we still trigger the debug exception. */
104
gen_set_pc_im(s, dest);
105
s->base.is_jmp = DISAS_JUMP;
106
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
107
dc->page_start = dc->base.pc_first & TARGET_PAGE_MASK;
108
109
/* If architectural single step active, limit to 1. */
110
- if (is_singlestepping(dc)) {
111
+ if (dc->ss_active) {
112
dc->base.max_insns = 1;
49
}
113
}
50
114
51
buffer_overflow:
115
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
52
- tb = tb_alloc(pc);
116
* insn codepath itself.
53
+ tb = tcg_tb_alloc(tcg_ctx);
117
*/
54
if (unlikely(!tb)) {
118
gen_bx_excret_final_code(dc);
55
/* flush must be done */
119
- } else if (unlikely(is_singlestepping(dc))) {
56
tb_flush(cpu);
120
+ } else if (unlikely(dc->ss_active)) {
121
/* Unconditional and "condition passed" instruction codepath. */
122
switch (dc->base.is_jmp) {
123
case DISAS_SWI:
124
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
125
/* "Condition failed" instruction codepath for the branch/trap insn */
126
gen_set_label(dc->condlabel);
127
gen_set_condexec(dc);
128
- if (unlikely(is_singlestepping(dc))) {
129
+ if (unlikely(dc->ss_active)) {
130
gen_set_pc_im(dc, dc->base.pc_next);
131
gen_singlestep_exception(dc);
132
} else {
57
--
133
--
58
2.17.1
134
2.25.1
59
135
60
136
diff view generated by jsdifflib
New patch
1
GDB single-stepping is now handled generically.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/hppa/translate.c | 17 ++++-------------
7
1 file changed, 4 insertions(+), 13 deletions(-)
8
9
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/hppa/translate.c
12
+++ b/target/hppa/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int which,
14
} else {
15
copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b);
16
copy_iaoq_entry(cpu_iaoq_b, b, ctx->iaoq_n_var);
17
- if (ctx->base.singlestep_enabled) {
18
- gen_excp_1(EXCP_DEBUG);
19
- } else {
20
- tcg_gen_lookup_and_goto_ptr();
21
- }
22
+ tcg_gen_lookup_and_goto_ptr();
23
}
24
}
25
26
@@ -XXX,XX +XXX,XX @@ static bool do_rfi(DisasContext *ctx, bool rfi_r)
27
gen_helper_rfi(cpu_env);
28
}
29
/* Exit the TB to recognize new interrupts. */
30
- if (ctx->base.singlestep_enabled) {
31
- gen_excp_1(EXCP_DEBUG);
32
- } else {
33
- tcg_gen_exit_tb(NULL, 0);
34
- }
35
+ tcg_gen_exit_tb(NULL, 0);
36
ctx->base.is_jmp = DISAS_NORETURN;
37
38
return nullify_end(ctx);
39
@@ -XXX,XX +XXX,XX @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
40
nullify_save(ctx);
41
/* FALLTHRU */
42
case DISAS_IAQ_N_UPDATED:
43
- if (ctx->base.singlestep_enabled) {
44
- gen_excp_1(EXCP_DEBUG);
45
- } else if (is_jmp != DISAS_IAQ_N_STALE_EXIT) {
46
+ if (is_jmp != DISAS_IAQ_N_STALE_EXIT) {
47
tcg_gen_lookup_and_goto_ptr();
48
+ break;
49
}
50
/* FALLTHRU */
51
case DISAS_EXIT:
52
--
53
2.25.1
54
55
diff view generated by jsdifflib
New patch
1
We were using singlestep_enabled as a proxy for whether
2
translator_use_goto_tb would always return false.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/i386/tcg/translate.c | 5 +++--
7
1 file changed, 3 insertions(+), 2 deletions(-)
8
9
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/i386/tcg/translate.c
12
+++ b/target/i386/tcg/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
14
DisasContext *dc = container_of(dcbase, DisasContext, base);
15
CPUX86State *env = cpu->env_ptr;
16
uint32_t flags = dc->base.tb->flags;
17
+ uint32_t cflags = tb_cflags(dc->base.tb);
18
int cpl = (flags >> HF_CPL_SHIFT) & 3;
19
int iopl = (flags >> IOPL_SHIFT) & 3;
20
21
@@ -XXX,XX +XXX,XX @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
22
dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX];
23
dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX];
24
dc->cpuid_xsave_features = env->features[FEAT_XSAVE];
25
- dc->jmp_opt = !(dc->base.singlestep_enabled ||
26
+ dc->jmp_opt = !((cflags & CF_NO_GOTO_TB) ||
27
(flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)));
28
/*
29
* If jmp_opt, we want to handle each string instruction individually.
30
* For icount also disable repz optimization so that each iteration
31
* is accounted separately.
32
*/
33
- dc->repz_opt = !dc->jmp_opt && !(tb_cflags(dc->base.tb) & CF_USE_ICOUNT);
34
+ dc->repz_opt = !dc->jmp_opt && !(cflags & CF_USE_ICOUNT);
35
36
dc->T0 = tcg_temp_new();
37
dc->T1 = tcg_temp_new();
38
--
39
2.25.1
40
41
diff view generated by jsdifflib
New patch
1
GDB single-stepping is now handled generically.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/i386/helper.h | 1 -
6
target/i386/tcg/misc_helper.c | 8 --------
7
target/i386/tcg/translate.c | 4 +---
8
3 files changed, 1 insertion(+), 12 deletions(-)
9
10
diff --git a/target/i386/helper.h b/target/i386/helper.h
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/i386/helper.h
13
+++ b/target/i386/helper.h
14
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(syscall, void, env, int)
15
DEF_HELPER_2(sysret, void, env, int)
16
#endif
17
DEF_HELPER_FLAGS_2(pause, TCG_CALL_NO_WG, noreturn, env, int)
18
-DEF_HELPER_FLAGS_1(debug, TCG_CALL_NO_WG, noreturn, env)
19
DEF_HELPER_1(reset_rf, void, env)
20
DEF_HELPER_FLAGS_3(raise_interrupt, TCG_CALL_NO_WG, noreturn, env, int, int)
21
DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, int)
22
diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/i386/tcg/misc_helper.c
25
+++ b/target/i386/tcg/misc_helper.c
26
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN helper_pause(CPUX86State *env, int next_eip_addend)
27
do_pause(env);
28
}
29
30
-void QEMU_NORETURN helper_debug(CPUX86State *env)
31
-{
32
- CPUState *cs = env_cpu(env);
33
-
34
- cs->exception_index = EXCP_DEBUG;
35
- cpu_loop_exit(cs);
36
-}
37
-
38
uint64_t helper_rdpkru(CPUX86State *env, uint32_t ecx)
39
{
40
if ((env->cr[4] & CR4_PKE_MASK) == 0) {
41
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/i386/tcg/translate.c
44
+++ b/target/i386/tcg/translate.c
45
@@ -XXX,XX +XXX,XX @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr)
46
if (s->base.tb->flags & HF_RF_MASK) {
47
gen_helper_reset_rf(cpu_env);
48
}
49
- if (s->base.singlestep_enabled) {
50
- gen_helper_debug(cpu_env);
51
- } else if (recheck_tf) {
52
+ if (recheck_tf) {
53
gen_helper_rechecking_single_step(cpu_env);
54
tcg_gen_exit_tb(NULL, 0);
55
} else if (s->flags & HF_TF_MASK) {
56
--
57
2.25.1
58
59
diff view generated by jsdifflib
New patch
1
GDB single-stepping is now handled generically.
1
2
3
Acked-by: Laurent Vivier <laurent@vivier.eu>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/m68k/translate.c | 44 +++++++++--------------------------------
7
1 file changed, 9 insertions(+), 35 deletions(-)
8
9
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/m68k/translate.c
12
+++ b/target/m68k/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void do_writebacks(DisasContext *s)
14
}
15
}
16
17
-static bool is_singlestepping(DisasContext *s)
18
-{
19
- /*
20
- * Return true if we are singlestepping either because of
21
- * architectural singlestep or QEMU gdbstub singlestep. This does
22
- * not include the command line '-singlestep' mode which is rather
23
- * misnamed as it only means "one instruction per TB" and doesn't
24
- * affect the code we generate.
25
- */
26
- return s->base.singlestep_enabled || s->ss_active;
27
-}
28
-
29
/* is_jmp field values */
30
#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
31
#define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */
32
@@ -XXX,XX +XXX,XX @@ static void gen_exception(DisasContext *s, uint32_t dest, int nr)
33
s->base.is_jmp = DISAS_NORETURN;
34
}
35
36
-static void gen_singlestep_exception(DisasContext *s)
37
-{
38
- /*
39
- * Generate the right kind of exception for singlestep, which is
40
- * either the architectural singlestep or EXCP_DEBUG for QEMU's
41
- * gdb singlestepping.
42
- */
43
- if (s->ss_active) {
44
- gen_raise_exception(EXCP_TRACE);
45
- } else {
46
- gen_raise_exception(EXCP_DEBUG);
47
- }
48
-}
49
-
50
static inline void gen_addr_fault(DisasContext *s)
51
{
52
gen_exception(s, s->base.pc_next, EXCP_ADDRESS);
53
@@ -XXX,XX +XXX,XX @@ static void gen_exit_tb(DisasContext *s)
54
/* Generate a jump to an immediate address. */
55
static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
56
{
57
- if (unlikely(is_singlestepping(s))) {
58
+ if (unlikely(s->ss_active)) {
59
update_cc_op(s);
60
tcg_gen_movi_i32(QREG_PC, dest);
61
- gen_singlestep_exception(s);
62
+ gen_raise_exception(EXCP_TRACE);
63
} else if (translator_use_goto_tb(&s->base, dest)) {
64
tcg_gen_goto_tb(n);
65
tcg_gen_movi_i32(QREG_PC, dest);
66
@@ -XXX,XX +XXX,XX @@ static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
67
68
dc->ss_active = (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS);
69
/* If architectural single step active, limit to 1 */
70
- if (is_singlestepping(dc)) {
71
+ if (dc->ss_active) {
72
dc->base.max_insns = 1;
73
}
74
}
75
@@ -XXX,XX +XXX,XX @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
76
break;
77
case DISAS_TOO_MANY:
78
update_cc_op(dc);
79
- if (is_singlestepping(dc)) {
80
+ if (dc->ss_active) {
81
tcg_gen_movi_i32(QREG_PC, dc->pc);
82
- gen_singlestep_exception(dc);
83
+ gen_raise_exception(EXCP_TRACE);
84
} else {
85
gen_jmp_tb(dc, 0, dc->pc);
86
}
87
break;
88
case DISAS_JUMP:
89
/* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
90
- if (is_singlestepping(dc)) {
91
- gen_singlestep_exception(dc);
92
+ if (dc->ss_active) {
93
+ gen_raise_exception(EXCP_TRACE);
94
} else {
95
tcg_gen_lookup_and_goto_ptr();
96
}
97
@@ -XXX,XX +XXX,XX @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
98
* We updated CC_OP and PC in gen_exit_tb, but also modified
99
* other state that may require returning to the main loop.
100
*/
101
- if (is_singlestepping(dc)) {
102
- gen_singlestep_exception(dc);
103
+ if (dc->ss_active) {
104
+ gen_raise_exception(EXCP_TRACE);
105
} else {
106
tcg_gen_exit_tb(NULL, 0);
107
}
108
--
109
2.25.1
110
111
diff view generated by jsdifflib
New patch
1
We were using singlestep_enabled as a proxy for whether
2
translator_use_goto_tb would always return false.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/microblaze/translate.c | 4 ++--
7
1 file changed, 2 insertions(+), 2 deletions(-)
8
9
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/microblaze/translate.c
12
+++ b/target/microblaze/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
14
break;
15
16
case DISAS_JUMP:
17
- if (dc->jmp_dest != -1 && !cs->singlestep_enabled) {
18
+ if (dc->jmp_dest != -1 && !(tb_cflags(dc->base.tb) & CF_NO_GOTO_TB)) {
19
/* Direct jump. */
20
tcg_gen_discard_i32(cpu_btarget);
21
22
@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
23
return;
24
}
25
26
- /* Indirect jump (or direct jump w/ singlestep) */
27
+ /* Indirect jump (or direct jump w/ goto_tb disabled) */
28
tcg_gen_mov_i32(cpu_pc, cpu_btarget);
29
tcg_gen_discard_i32(cpu_btarget);
30
31
--
32
2.25.1
33
34
diff view generated by jsdifflib
New patch
1
GDB single-stepping is now handled generically.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/microblaze/translate.c | 14 ++------------
6
1 file changed, 2 insertions(+), 12 deletions(-)
7
8
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/target/microblaze/translate.c
11
+++ b/target/microblaze/translate.c
12
@@ -XXX,XX +XXX,XX @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
13
14
static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
15
{
16
- if (dc->base.singlestep_enabled) {
17
- TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
18
- tcg_gen_movi_i32(cpu_pc, dest);
19
- gen_helper_raise_exception(cpu_env, tmp);
20
- tcg_temp_free_i32(tmp);
21
- } else if (translator_use_goto_tb(&dc->base, dest)) {
22
+ if (translator_use_goto_tb(&dc->base, dest)) {
23
tcg_gen_goto_tb(n);
24
tcg_gen_movi_i32(cpu_pc, dest);
25
tcg_gen_exit_tb(dc->base.tb, n);
26
@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
27
/* Indirect jump (or direct jump w/ goto_tb disabled) */
28
tcg_gen_mov_i32(cpu_pc, cpu_btarget);
29
tcg_gen_discard_i32(cpu_btarget);
30
-
31
- if (unlikely(cs->singlestep_enabled)) {
32
- gen_raise_exception(dc, EXCP_DEBUG);
33
- } else {
34
- tcg_gen_lookup_and_goto_ptr();
35
- }
36
+ tcg_gen_lookup_and_goto_ptr();
37
return;
38
39
default:
40
--
41
2.25.1
42
43
diff view generated by jsdifflib
New patch
1
As per an ancient comment in mips_tr_translate_insn about the
2
expectations of gdb, when restarting the insn in a delay slot
3
we also re-execute the branch. Which means that we are
4
expected to execute two insns in this case.
1
5
6
This has been broken since 8b86d6d2580, where we forced max_insns
7
to 1 while single-stepping. This resulted in an exit from the
8
translator loop after the branch but before the delay slot is
9
translated.
10
11
Increase the max_insns to 2 for this case. In addition, bypass
12
the end-of-page check, for when the branch itself ends the page.
13
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
---
17
target/mips/tcg/translate.c | 25 ++++++++++++++++---------
18
1 file changed, 16 insertions(+), 9 deletions(-)
19
20
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/mips/tcg/translate.c
23
+++ b/target/mips/tcg/translate.c
24
@@ -XXX,XX +XXX,XX @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
25
ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS_R6 |
26
INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
27
28
+ /*
29
+ * Execute a branch and its delay slot as a single instruction.
30
+ * This is what GDB expects and is consistent with what the
31
+ * hardware does (e.g. if a delay slot instruction faults, the
32
+ * reported PC is the PC of the branch).
33
+ */
34
+ if (ctx->base.singlestep_enabled && (ctx->hflags & MIPS_HFLAG_BMASK)) {
35
+ ctx->base.max_insns = 2;
36
+ }
37
+
38
LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,
39
ctx->hflags);
40
}
41
@@ -XXX,XX +XXX,XX @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
42
if (ctx->base.is_jmp != DISAS_NEXT) {
43
return;
44
}
45
+
46
/*
47
- * Execute a branch and its delay slot as a single instruction.
48
- * This is what GDB expects and is consistent with what the
49
- * hardware does (e.g. if a delay slot instruction faults, the
50
- * reported PC is the PC of the branch).
51
+ * End the TB on (most) page crossings.
52
+ * See mips_tr_init_disas_context about single-stepping a branch
53
+ * together with its delay slot.
54
*/
55
- if (ctx->base.singlestep_enabled &&
56
- (ctx->hflags & MIPS_HFLAG_BMASK) == 0) {
57
- ctx->base.is_jmp = DISAS_TOO_MANY;
58
- }
59
- if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE) {
60
+ if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE
61
+ && !ctx->base.singlestep_enabled) {
62
ctx->base.is_jmp = DISAS_TOO_MANY;
63
}
64
}
65
--
66
2.25.1
67
68
diff view generated by jsdifflib
1
From: Clement Deschamps <clement.deschamps@greensocs.com>
1
GDB single-stepping is now handled generically.
2
2
3
This fixes a segmentation fault in icount mode when executing
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
from an IO region.
5
6
TB is marked as CF_NOCACHE but tb->orig_tb is not initialized
7
(equals previous value in code_gen_buffer).
8
9
The issue happens in cpu_io_recompile() when it tries to invalidate orig_tb.
10
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Clement Deschamps <clement.deschamps@greensocs.com>
13
Message-Id: <20191022140016.918371-1-clement.deschamps@greensocs.com>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
---
5
---
16
accel/tcg/translate-all.c | 1 +
6
target/mips/tcg/translate.c | 50 +++++++++++++------------------------
17
1 file changed, 1 insertion(+)
7
1 file changed, 18 insertions(+), 32 deletions(-)
18
8
19
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
9
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
20
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
21
--- a/accel/tcg/translate-all.c
11
--- a/target/mips/tcg/translate.c
22
+++ b/accel/tcg/translate-all.c
12
+++ b/target/mips/tcg/translate.c
23
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
13
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
24
tb->cs_base = cs_base;
14
tcg_gen_exit_tb(ctx->base.tb, n);
25
tb->flags = flags;
15
} else {
26
tb->cflags = cflags;
16
gen_save_pc(dest);
27
+ tb->orig_tb = NULL;
17
- if (ctx->base.singlestep_enabled) {
28
tb->trace_vcpu_dstate = *cpu->trace_dstate;
18
- save_cpu_state(ctx, 0);
29
tcg_ctx->tb_cflags = cflags;
19
- gen_helper_raise_exception_debug(cpu_env);
30
tb_overflow:
20
- } else {
21
- tcg_gen_lookup_and_goto_ptr();
22
- }
23
+ tcg_gen_lookup_and_goto_ptr();
24
}
25
}
26
27
@@ -XXX,XX +XXX,XX @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
28
} else {
29
tcg_gen_mov_tl(cpu_PC, btarget);
30
}
31
- if (ctx->base.singlestep_enabled) {
32
- save_cpu_state(ctx, 0);
33
- gen_helper_raise_exception_debug(cpu_env);
34
- }
35
tcg_gen_lookup_and_goto_ptr();
36
break;
37
default:
38
@@ -XXX,XX +XXX,XX @@ static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
39
{
40
DisasContext *ctx = container_of(dcbase, DisasContext, base);
41
42
- if (ctx->base.singlestep_enabled && ctx->base.is_jmp != DISAS_NORETURN) {
43
- save_cpu_state(ctx, ctx->base.is_jmp != DISAS_EXIT);
44
- gen_helper_raise_exception_debug(cpu_env);
45
- } else {
46
- switch (ctx->base.is_jmp) {
47
- case DISAS_STOP:
48
- gen_save_pc(ctx->base.pc_next);
49
- tcg_gen_lookup_and_goto_ptr();
50
- break;
51
- case DISAS_NEXT:
52
- case DISAS_TOO_MANY:
53
- save_cpu_state(ctx, 0);
54
- gen_goto_tb(ctx, 0, ctx->base.pc_next);
55
- break;
56
- case DISAS_EXIT:
57
- tcg_gen_exit_tb(NULL, 0);
58
- break;
59
- case DISAS_NORETURN:
60
- break;
61
- default:
62
- g_assert_not_reached();
63
- }
64
+ switch (ctx->base.is_jmp) {
65
+ case DISAS_STOP:
66
+ gen_save_pc(ctx->base.pc_next);
67
+ tcg_gen_lookup_and_goto_ptr();
68
+ break;
69
+ case DISAS_NEXT:
70
+ case DISAS_TOO_MANY:
71
+ save_cpu_state(ctx, 0);
72
+ gen_goto_tb(ctx, 0, ctx->base.pc_next);
73
+ break;
74
+ case DISAS_EXIT:
75
+ tcg_gen_exit_tb(NULL, 0);
76
+ break;
77
+ case DISAS_NORETURN:
78
+ break;
79
+ default:
80
+ g_assert_not_reached();
81
}
82
}
83
31
--
84
--
32
2.17.1
85
2.25.1
33
86
34
87
diff view generated by jsdifflib
1
Using uintptr_t instead of target_ulong meant that, for 64-bit guest
1
GDB single-stepping is now handled generically.
2
and 32-bit host, we truncated the guest address comparator and so may
3
not hit the tlb when we should.
4
2
5
Fixes: 4811e9095c0
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: David Hildenbrand <david@redhat.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
5
---
9
accel/tcg/cputlb.c | 2 +-
6
target/openrisc/translate.c | 18 +++---------------
10
1 file changed, 1 insertion(+), 1 deletion(-)
7
1 file changed, 3 insertions(+), 15 deletions(-)
11
8
12
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
9
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
13
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
14
--- a/accel/tcg/cputlb.c
11
--- a/target/openrisc/translate.c
15
+++ b/accel/tcg/cputlb.c
12
+++ b/target/openrisc/translate.c
16
@@ -XXX,XX +XXX,XX @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
13
@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
17
MMUAccessType access_type, int mmu_idx)
14
/* The jump destination is indirect/computed; use jmp_pc. */
18
{
15
tcg_gen_mov_tl(cpu_pc, jmp_pc);
19
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
16
tcg_gen_discard_tl(jmp_pc);
20
- uintptr_t tlb_addr, page;
17
- if (unlikely(dc->base.singlestep_enabled)) {
21
+ target_ulong tlb_addr, page;
18
- gen_exception(dc, EXCP_DEBUG);
22
size_t elt_ofs;
19
- } else {
23
20
- tcg_gen_lookup_and_goto_ptr();
24
switch (access_type) {
21
- }
22
+ tcg_gen_lookup_and_goto_ptr();
23
break;
24
}
25
/* The jump destination is direct; use jmp_pc_imm.
26
@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
27
break;
28
}
29
tcg_gen_movi_tl(cpu_pc, jmp_dest);
30
- if (unlikely(dc->base.singlestep_enabled)) {
31
- gen_exception(dc, EXCP_DEBUG);
32
- } else {
33
- tcg_gen_lookup_and_goto_ptr();
34
- }
35
+ tcg_gen_lookup_and_goto_ptr();
36
break;
37
38
case DISAS_EXIT:
39
- if (unlikely(dc->base.singlestep_enabled)) {
40
- gen_exception(dc, EXCP_DEBUG);
41
- } else {
42
- tcg_gen_exit_tb(NULL, 0);
43
- }
44
+ tcg_gen_exit_tb(NULL, 0);
45
break;
46
default:
47
g_assert_not_reached();
25
--
48
--
26
2.17.1
49
2.25.1
27
50
28
51
diff view generated by jsdifflib
1
Using a variable that is declared "const" for this tells the
1
GDB single-stepping is now handled generically.
2
compiler that it may read the value once and assume that it
2
Reuse gen_debug_exception to handle architectural debug exceptions.
3
does not change across function calls.
4
3
5
For target_page_size, this means we have only one assert per
6
function, and one read of the variable.
7
8
This reduces the size of qemu-system-aarch64 by 8k.
9
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
5
---
14
include/exec/cpu-all.h | 14 +++++++---
6
target/ppc/translate.c | 38 ++++++++------------------------------
15
exec-vary.c | 60 ++++++++++++++++++++++++++++++++++++------
7
1 file changed, 8 insertions(+), 30 deletions(-)
16
2 files changed, 62 insertions(+), 12 deletions(-)
17
8
18
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
9
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
19
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
20
--- a/include/exec/cpu-all.h
11
--- a/target/ppc/translate.c
21
+++ b/include/exec/cpu-all.h
12
+++ b/target/ppc/translate.c
22
@@ -XXX,XX +XXX,XX @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val
23
/* page related stuff */
24
25
#ifdef TARGET_PAGE_BITS_VARY
26
-extern bool target_page_bits_decided;
27
-extern int target_page_bits;
28
-#define TARGET_PAGE_BITS ({ assert(target_page_bits_decided); \
29
- target_page_bits; })
30
+typedef struct {
31
+ bool decided;
32
+ int bits;
33
+} TargetPageBits;
34
+# if defined(CONFIG_ATTRIBUTE_ALIAS) || !defined(IN_EXEC_VARY)
35
+extern const TargetPageBits target_page;
36
+#else
37
+extern TargetPageBits target_page;
38
+# endif
39
+#define TARGET_PAGE_BITS (assert(target_page.decided), target_page.bits)
40
#else
41
#define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
42
#endif
43
diff --git a/exec-vary.c b/exec-vary.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/exec-vary.c
46
+++ b/exec-vary.c
47
@@ -XXX,XX +XXX,XX @@
13
@@ -XXX,XX +XXX,XX @@
48
14
49
#include "qemu/osdep.h"
15
#define CPU_SINGLE_STEP 0x1
50
#include "qemu-common.h"
16
#define CPU_BRANCH_STEP 0x2
51
+
17
-#define GDBSTUB_SINGLE_STEP 0x4
52
+#define IN_EXEC_VARY 1
18
53
+
19
/* Include definitions for instructions classes and implementations flags */
54
#include "exec/exec-all.h"
20
/* #define PPC_DEBUG_DISAS */
55
21
@@ -XXX,XX +XXX,XX @@ static uint32_t gen_prep_dbgex(DisasContext *ctx)
56
#ifdef TARGET_PAGE_BITS_VARY
22
57
-int target_page_bits;
23
static void gen_debug_exception(DisasContext *ctx)
58
-bool target_page_bits_decided;
24
{
59
+# ifdef CONFIG_ATTRIBUTE_ALIAS
25
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
60
+/*
26
+ gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
61
+ * We want to declare the "target_page" variable as const, which tells
27
ctx->base.is_jmp = DISAS_NORETURN;
62
+ * the compiler that it can cache any value that it reads across calls.
28
}
63
+ * This avoids multiple assertions and multiple reads within any one user.
29
64
+ *
30
@@ -XXX,XX +XXX,XX @@ static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
65
+ * This works because we initialize the target_page data very early, in a
31
66
+ * location far removed from the functions that require the final results.
32
static void gen_lookup_and_goto_ptr(DisasContext *ctx)
67
+ *
33
{
68
+ * This also requires that we have a non-constant symbol by which we can
34
- int sse = ctx->singlestep_enabled;
69
+ * perform the actual initialization, and which forces the data to be
35
- if (unlikely(sse)) {
70
+ * allocated within writable memory. Thus "init_target_page", and we use
36
- if (sse & GDBSTUB_SINGLE_STEP) {
71
+ * that symbol exclusively in the two functions that initialize this value.
37
- gen_debug_exception(ctx);
72
+ *
38
- } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
73
+ * The "target_page" symbol is created as an alias of "init_target_page".
39
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
74
+ */
40
- } else {
75
+static TargetPageBits init_target_page;
41
- tcg_gen_exit_tb(NULL, 0);
76
+
42
- }
77
+/*
43
+ if (unlikely(ctx->singlestep_enabled)) {
78
+ * Note that this is *not* a redundant decl, this is the definition of
44
+ gen_debug_exception(ctx);
79
+ * the "target_page" symbol. The syntax for this definition requires
45
} else {
80
+ * the use of the extern keyword. This seems to be a GCC bug in
46
tcg_gen_lookup_and_goto_ptr();
81
+ * either the syntax for the alias attribute or in -Wredundant-decls.
47
}
82
+ *
48
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
83
+ * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91765
49
ctx->singlestep_enabled = 0;
84
+ */
50
if ((hflags >> HFLAGS_SE) & 1) {
85
+# pragma GCC diagnostic push
51
ctx->singlestep_enabled |= CPU_SINGLE_STEP;
86
+# pragma GCC diagnostic ignored "-Wredundant-decls"
52
+ ctx->base.max_insns = 1;
87
+
53
}
88
+extern const TargetPageBits target_page
54
if ((hflags >> HFLAGS_BE) & 1) {
89
+ __attribute__((alias("init_target_page")));
55
ctx->singlestep_enabled |= CPU_BRANCH_STEP;
90
+
56
}
91
+# pragma GCC diagnostic pop
57
- if (unlikely(ctx->base.singlestep_enabled)) {
92
+# else
58
- ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
93
+/*
59
- }
94
+ * When aliases are not supported then we force two different declarations,
60
-
95
+ * by way of suppressing the header declaration with IN_EXEC_VARY.
61
- if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) {
96
+ * We assume that on such an old compiler, LTO cannot be used, and so the
62
- ctx->base.max_insns = 1;
97
+ * compiler cannot not detect the mismatched declarations, and all is well.
63
- }
98
+ */
64
}
99
+TargetPageBits target_page;
65
100
+# define init_target_page target_page
66
static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
101
+# endif
67
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
102
#endif
68
DisasContext *ctx = container_of(dcbase, DisasContext, base);
103
69
DisasJumpType is_jmp = ctx->base.is_jmp;
104
bool set_preferred_target_page_bits(int bits)
70
target_ulong nip = ctx->base.pc_next;
105
@@ -XXX,XX +XXX,XX @@ bool set_preferred_target_page_bits(int bits)
71
- int sse;
106
*/
72
107
#ifdef TARGET_PAGE_BITS_VARY
73
if (is_jmp == DISAS_NORETURN) {
108
assert(bits >= TARGET_PAGE_BITS_MIN);
74
/* We have already exited the TB. */
109
- if (target_page_bits == 0 || target_page_bits > bits) {
75
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
110
- if (target_page_bits_decided) {
76
}
111
+ if (init_target_page.bits == 0 || init_target_page.bits > bits) {
77
112
+ if (init_target_page.decided) {
78
/* Honor single stepping. */
113
return false;
79
- sse = ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP);
80
- if (unlikely(sse)) {
81
+ if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)
82
+ && (nip <= 0x100 || nip > 0xf00)) {
83
switch (is_jmp) {
84
case DISAS_TOO_MANY:
85
case DISAS_EXIT_UPDATE:
86
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
87
g_assert_not_reached();
114
}
88
}
115
- target_page_bits = bits;
89
116
+ init_target_page.bits = bits;
90
- if (sse & GDBSTUB_SINGLE_STEP) {
91
- gen_debug_exception(ctx);
92
- return;
93
- }
94
- /* else CPU_SINGLE_STEP... */
95
- if (nip <= 0x100 || nip > 0xf00) {
96
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
97
- return;
98
- }
99
+ gen_debug_exception(ctx);
100
+ return;
117
}
101
}
118
#endif
102
119
return true;
103
switch (is_jmp) {
120
@@ -XXX,XX +XXX,XX @@ bool set_preferred_target_page_bits(int bits)
121
void finalize_target_page_bits(void)
122
{
123
#ifdef TARGET_PAGE_BITS_VARY
124
- if (target_page_bits == 0) {
125
- target_page_bits = TARGET_PAGE_BITS_MIN;
126
+ if (init_target_page.bits == 0) {
127
+ init_target_page.bits = TARGET_PAGE_BITS_MIN;
128
}
129
- target_page_bits_decided = true;
130
+ init_target_page.decided = true;
131
#endif
132
}
133
--
104
--
134
2.17.1
105
2.25.1
135
106
136
107
diff view generated by jsdifflib
1
There are some uint64_t uses that expect TARGET_PAGE_MASK to
1
We have already set DISAS_NORETURN in generate_exception,
2
extend for a 32-bit, so this must continue to be a signed type.
2
which makes the exit_tb unreachable.
3
Define based on TARGET_PAGE_BITS not TARGET_PAGE_SIZE; this
4
will make a following patch more clear.
5
3
6
This should not have a functional effect so far.
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
6
---
12
include/exec/cpu-all.h | 2 +-
7
target/riscv/insn_trans/trans_privileged.c.inc | 6 +-----
13
1 file changed, 1 insertion(+), 1 deletion(-)
8
1 file changed, 1 insertion(+), 5 deletions(-)
14
9
15
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
10
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
16
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
17
--- a/include/exec/cpu-all.h
12
--- a/target/riscv/insn_trans/trans_privileged.c.inc
18
+++ b/include/exec/cpu-all.h
13
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
19
@@ -XXX,XX +XXX,XX @@ extern TargetPageBits target_page;
14
@@ -XXX,XX +XXX,XX @@ static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
20
#endif
15
{
21
16
/* always generates U-level ECALL, fixed in do_interrupt handler */
22
#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
17
generate_exception(ctx, RISCV_EXCP_U_ECALL);
23
-#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
18
- exit_tb(ctx); /* no chaining */
24
+#define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS)
19
- ctx->base.is_jmp = DISAS_NORETURN;
25
#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
20
return true;
26
21
}
27
/* Using intptr_t ensures that qemu_*_page_mask is sign-extended even
22
23
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
24
post = opcode_at(&ctx->base, post_addr);
25
}
26
27
- if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
28
+ if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
29
generate_exception(ctx, RISCV_EXCP_SEMIHOST);
30
} else {
31
generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
32
}
33
- exit_tb(ctx); /* no chaining */
34
- ctx->base.is_jmp = DISAS_NORETURN;
35
return true;
36
}
37
28
--
38
--
29
2.17.1
39
2.25.1
30
40
31
41
diff view generated by jsdifflib
1
This eliminates a set of runtime shifts. It turns out that we
1
GDB single-stepping is now handled generically, which means
2
require TARGET_PAGE_MASK more often than TARGET_PAGE_SIZE, so
2
we don't need to do anything in the wrappers.
3
redefine TARGET_PAGE_SIZE based on TARGET_PAGE_MASK instead of
4
the other way around.
5
3
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: David Hildenbrand <david@redhat.com>
8
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
6
---
11
include/exec/cpu-all.h | 8 ++++++--
7
target/riscv/translate.c | 27 +------------------
12
exec-vary.c | 1 +
8
.../riscv/insn_trans/trans_privileged.c.inc | 4 +--
13
2 files changed, 7 insertions(+), 2 deletions(-)
9
target/riscv/insn_trans/trans_rvi.c.inc | 8 +++---
10
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
11
4 files changed, 7 insertions(+), 34 deletions(-)
14
12
15
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
13
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
16
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
17
--- a/include/exec/cpu-all.h
15
--- a/target/riscv/translate.c
18
+++ b/include/exec/cpu-all.h
16
+++ b/target/riscv/translate.c
19
@@ -XXX,XX +XXX,XX @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val
17
@@ -XXX,XX +XXX,XX @@ static void generate_exception_mtval(DisasContext *ctx, int excp)
20
typedef struct {
18
ctx->base.is_jmp = DISAS_NORETURN;
21
bool decided;
19
}
22
int bits;
20
23
+ target_long mask;
21
-static void gen_exception_debug(void)
24
} TargetPageBits;
22
-{
25
# if defined(CONFIG_ATTRIBUTE_ALIAS) || !defined(IN_EXEC_VARY)
23
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
26
extern const TargetPageBits target_page;
24
-}
27
@@ -XXX,XX +XXX,XX @@ extern TargetPageBits target_page;
25
-
28
# endif
26
-/* Wrapper around tcg_gen_exit_tb that handles single stepping */
29
# ifdef CONFIG_DEBUG_TCG
27
-static void exit_tb(DisasContext *ctx)
30
# define TARGET_PAGE_BITS (assert(target_page.decided), target_page.bits)
28
-{
31
+# define TARGET_PAGE_MASK (assert(target_page.decided), target_page.mask)
29
- if (ctx->base.singlestep_enabled) {
32
# else
30
- gen_exception_debug();
33
# define TARGET_PAGE_BITS target_page.bits
31
- } else {
34
+# define TARGET_PAGE_MASK target_page.mask
32
- tcg_gen_exit_tb(NULL, 0);
35
# endif
33
- }
36
+# define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK)
34
-}
35
-
36
-/* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
37
-static void lookup_and_goto_ptr(DisasContext *ctx)
38
-{
39
- if (ctx->base.singlestep_enabled) {
40
- gen_exception_debug();
41
- } else {
42
- tcg_gen_lookup_and_goto_ptr();
43
- }
44
-}
45
-
46
static void gen_exception_illegal(DisasContext *ctx)
47
{
48
generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
49
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
50
tcg_gen_exit_tb(ctx->base.tb, n);
51
} else {
52
tcg_gen_movi_tl(cpu_pc, dest);
53
- lookup_and_goto_ptr(ctx);
54
+ tcg_gen_lookup_and_goto_ptr();
55
}
56
}
57
58
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/riscv/insn_trans/trans_privileged.c.inc
61
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
62
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
63
64
if (has_ext(ctx, RVS)) {
65
gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
66
- exit_tb(ctx); /* no chaining */
67
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
68
ctx->base.is_jmp = DISAS_NORETURN;
69
} else {
70
return false;
71
@@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
72
#ifndef CONFIG_USER_ONLY
73
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
74
gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
75
- exit_tb(ctx); /* no chaining */
76
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
77
ctx->base.is_jmp = DISAS_NORETURN;
78
return true;
37
#else
79
#else
38
#define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
80
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
39
+#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
40
+#define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS)
41
#endif
42
43
-#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
44
-#define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS)
45
#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
46
47
/* Using intptr_t ensures that qemu_*_page_mask is sign-extended even
48
diff --git a/exec-vary.c b/exec-vary.c
49
index XXXXXXX..XXXXXXX 100644
81
index XXXXXXX..XXXXXXX 100644
50
--- a/exec-vary.c
82
--- a/target/riscv/insn_trans/trans_rvi.c.inc
51
+++ b/exec-vary.c
83
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
52
@@ -XXX,XX +XXX,XX @@ void finalize_target_page_bits(void)
84
@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
53
init_target_page.bits = TARGET_PAGE_BITS_MIN;
85
if (a->rd != 0) {
86
tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
54
}
87
}
55
init_target_page.decided = true;
88
-
56
+ init_target_page.mask = (target_long)-1 << init_target_page.bits;
89
- /* No chaining with JALR. */
57
#endif
90
- lookup_and_goto_ptr(ctx);
91
+ tcg_gen_lookup_and_goto_ptr();
92
93
if (misaligned) {
94
gen_set_label(misaligned);
95
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
96
* however we need to end the translation block
97
*/
98
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
99
- exit_tb(ctx);
100
+ tcg_gen_exit_tb(NULL, 0);
101
ctx->base.is_jmp = DISAS_NORETURN;
102
return true;
103
}
104
@@ -XXX,XX +XXX,XX @@ static bool do_csr_post(DisasContext *ctx)
105
{
106
/* We may have changed important cpu state -- exit to main loop. */
107
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
108
- exit_tb(ctx);
109
+ tcg_gen_exit_tb(NULL, 0);
110
ctx->base.is_jmp = DISAS_NORETURN;
111
return true;
112
}
113
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
114
index XXXXXXX..XXXXXXX 100644
115
--- a/target/riscv/insn_trans/trans_rvv.c.inc
116
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
117
@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
118
gen_set_gpr(ctx, a->rd, dst);
119
120
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
121
- lookup_and_goto_ptr(ctx);
122
+ tcg_gen_lookup_and_goto_ptr();
123
ctx->base.is_jmp = DISAS_NORETURN;
124
return true;
58
}
125
}
59
--
126
--
60
2.17.1
127
2.25.1
61
128
62
129
diff view generated by jsdifflib
1
This reduces the size of a release build by about 10k.
1
GDB single-stepping is now handled generically.
2
Noticably, within the tlb miss helpers.
3
2
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
5
---
9
include/exec/cpu-all.h | 6 +++++-
6
target/rx/helper.h | 1 -
10
1 file changed, 5 insertions(+), 1 deletion(-)
7
target/rx/op_helper.c | 8 --------
8
target/rx/translate.c | 12 ++----------
9
3 files changed, 2 insertions(+), 19 deletions(-)
11
10
12
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
11
diff --git a/target/rx/helper.h b/target/rx/helper.h
13
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
14
--- a/include/exec/cpu-all.h
13
--- a/target/rx/helper.h
15
+++ b/include/exec/cpu-all.h
14
+++ b/target/rx/helper.h
16
@@ -XXX,XX +XXX,XX @@ extern const TargetPageBits target_page;
15
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_illegal_instruction, noreturn, env)
17
#else
16
DEF_HELPER_1(raise_access_fault, noreturn, env)
18
extern TargetPageBits target_page;
17
DEF_HELPER_1(raise_privilege_violation, noreturn, env)
19
# endif
18
DEF_HELPER_1(wait, noreturn, env)
20
-#define TARGET_PAGE_BITS (assert(target_page.decided), target_page.bits)
19
-DEF_HELPER_1(debug, noreturn, env)
21
+# ifdef CONFIG_DEBUG_TCG
20
DEF_HELPER_2(rxint, noreturn, env, i32)
22
+# define TARGET_PAGE_BITS (assert(target_page.decided), target_page.bits)
21
DEF_HELPER_1(rxbrk, noreturn, env)
23
+# else
22
DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, f32, env, f32, f32)
24
+# define TARGET_PAGE_BITS target_page.bits
23
diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
25
+# endif
24
index XXXXXXX..XXXXXXX 100644
26
#else
25
--- a/target/rx/op_helper.c
27
#define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
26
+++ b/target/rx/op_helper.c
28
#endif
27
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN helper_wait(CPURXState *env)
28
raise_exception(env, EXCP_HLT, 0);
29
}
30
31
-void QEMU_NORETURN helper_debug(CPURXState *env)
32
-{
33
- CPUState *cs = env_cpu(env);
34
-
35
- cs->exception_index = EXCP_DEBUG;
36
- cpu_loop_exit(cs);
37
-}
38
-
39
void QEMU_NORETURN helper_rxint(CPURXState *env, uint32_t vec)
40
{
41
raise_exception(env, 0x100 + vec, 0);
42
diff --git a/target/rx/translate.c b/target/rx/translate.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/rx/translate.c
45
+++ b/target/rx/translate.c
46
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
47
tcg_gen_exit_tb(dc->base.tb, n);
48
} else {
49
tcg_gen_movi_i32(cpu_pc, dest);
50
- if (dc->base.singlestep_enabled) {
51
- gen_helper_debug(cpu_env);
52
- } else {
53
- tcg_gen_lookup_and_goto_ptr();
54
- }
55
+ tcg_gen_lookup_and_goto_ptr();
56
}
57
dc->base.is_jmp = DISAS_NORETURN;
58
}
59
@@ -XXX,XX +XXX,XX @@ static void rx_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
60
gen_goto_tb(ctx, 0, dcbase->pc_next);
61
break;
62
case DISAS_JUMP:
63
- if (ctx->base.singlestep_enabled) {
64
- gen_helper_debug(cpu_env);
65
- } else {
66
- tcg_gen_lookup_and_goto_ptr();
67
- }
68
+ tcg_gen_lookup_and_goto_ptr();
69
break;
70
case DISAS_UPDATE:
71
tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
29
--
72
--
30
2.17.1
73
2.25.1
31
74
32
75
diff view generated by jsdifflib
1
Such support is present almost everywhere, except for Xcode 9.
1
GDB single-stepping is now handled generically.
2
It is added in Xcode 10, but travis uses xcode9 by default,
3
so we should support it for a while yet.
4
2
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
4
---
8
configure | 19 +++++++++++++++++++
5
target/s390x/tcg/translate.c | 8 ++------
9
1 file changed, 19 insertions(+)
6
1 file changed, 2 insertions(+), 6 deletions(-)
10
7
11
diff --git a/configure b/configure
8
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
12
index XXXXXXX..XXXXXXX 100755
9
index XXXXXXX..XXXXXXX 100644
13
--- a/configure
10
--- a/target/s390x/tcg/translate.c
14
+++ b/configure
11
+++ b/target/s390x/tcg/translate.c
15
@@ -XXX,XX +XXX,XX @@ if compile_prog "" "" ; then
12
@@ -XXX,XX +XXX,XX @@ struct DisasContext {
16
vector16=yes
13
uint64_t pc_tmp;
17
fi
14
uint32_t ilen;
18
15
enum cc_op cc_op;
19
+########################################
16
- bool do_debug;
20
+# See if __attribute__((alias)) is supported.
17
};
21
+# This false for Xcode 9, but has been remedied for Xcode 10.
18
22
+# Unfortunately, travis uses Xcode 9 by default.
19
/* Information carried about a condition to be evaluated. */
23
+
20
@@ -XXX,XX +XXX,XX @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
24
+attralias=no
21
25
+cat > $TMPC << EOF
22
dc->cc_op = CC_OP_DYNAMIC;
26
+int x = 1;
23
dc->ex_value = dc->base.tb->cs_base;
27
+extern const int y __attribute__((alias("x")));
24
- dc->do_debug = dc->base.singlestep_enabled;
28
+int main(void) { return 0; }
25
}
29
+EOF
26
30
+if compile_prog "" "" ; then
27
static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs)
31
+ attralias=yes
28
@@ -XXX,XX +XXX,XX @@ static void s390x_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
32
+fi
29
/* FALLTHRU */
33
+
30
case DISAS_PC_CC_UPDATED:
34
########################################
31
/* Exit the TB, either by raising a debug exception or by return. */
35
# check if getauxval is available.
32
- if (dc->do_debug) {
36
33
- gen_exception(EXCP_DEBUG);
37
@@ -XXX,XX +XXX,XX @@ if test "$vector16" = "yes" ; then
34
- } else if ((dc->base.tb->flags & FLAG_MASK_PER) ||
38
echo "CONFIG_VECTOR16=y" >> $config_host_mak
35
- dc->base.is_jmp == DISAS_PC_STALE_NOCHAIN) {
39
fi
36
+ if ((dc->base.tb->flags & FLAG_MASK_PER) ||
40
37
+ dc->base.is_jmp == DISAS_PC_STALE_NOCHAIN) {
41
+if test "$attralias" = "yes" ; then
38
tcg_gen_exit_tb(NULL, 0);
42
+ echo "CONFIG_ATTRIBUTE_ALIAS=y" >> $config_host_mak
39
} else {
43
+fi
40
tcg_gen_lookup_and_goto_ptr();
44
+
45
if test "$getauxval" = "yes" ; then
46
echo "CONFIG_GETAUXVAL=y" >> $config_host_mak
47
fi
48
--
41
--
49
2.17.1
42
2.25.1
50
43
51
44
diff view generated by jsdifflib
1
From: Stefan Weil <sw@weilnetz.de>
1
GDB single-stepping is now handled generically.
2
2
3
This fixes "make check-tcg" on a Debian x86_64 host.
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
5
Signed-off-by: Stefan Weil <sw@weilnetz.de>
6
Tested-by: Thomas Huth <thuth@redhat.com>
7
Message-Id: <20190410194838.10123-1-sw@weilnetz.de>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
5
---
10
tcg/tci.c | 15 +++++++++++++++
6
target/sh4/helper.h | 1 -
11
1 file changed, 15 insertions(+)
7
target/sh4/op_helper.c | 5 -----
8
target/sh4/translate.c | 14 +++-----------
9
3 files changed, 3 insertions(+), 17 deletions(-)
12
10
13
diff --git a/tcg/tci.c b/tcg/tci.c
11
diff --git a/target/sh4/helper.h b/target/sh4/helper.h
14
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
15
--- a/tcg/tci.c
13
--- a/target/sh4/helper.h
16
+++ b/tcg/tci.c
14
+++ b/target/sh4/helper.h
17
@@ -XXX,XX +XXX,XX @@ static void tci_write_reg8(tcg_target_ulong *regs, TCGReg index, uint8_t value)
15
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_illegal_instruction, noreturn, env)
18
tci_write_reg(regs, index, value);
16
DEF_HELPER_1(raise_slot_illegal_instruction, noreturn, env)
17
DEF_HELPER_1(raise_fpu_disable, noreturn, env)
18
DEF_HELPER_1(raise_slot_fpu_disable, noreturn, env)
19
-DEF_HELPER_1(debug, noreturn, env)
20
DEF_HELPER_1(sleep, noreturn, env)
21
DEF_HELPER_2(trapa, noreturn, env, i32)
22
DEF_HELPER_1(exclusive, noreturn, env)
23
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/sh4/op_helper.c
26
+++ b/target/sh4/op_helper.c
27
@@ -XXX,XX +XXX,XX @@ void helper_raise_slot_fpu_disable(CPUSH4State *env)
28
raise_exception(env, 0x820, 0);
19
}
29
}
20
30
21
+static void
31
-void helper_debug(CPUSH4State *env)
22
+tci_write_reg16(tcg_target_ulong *regs, TCGReg index, uint16_t value)
32
-{
23
+{
33
- raise_exception(env, EXCP_DEBUG, 0);
24
+ tci_write_reg(regs, index, value);
34
-}
25
+}
35
-
26
+
36
void helper_sleep(CPUSH4State *env)
27
static void
28
tci_write_reg32(tcg_target_ulong *regs, TCGReg index, uint32_t value)
29
{
37
{
30
@@ -XXX,XX +XXX,XX @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
38
CPUState *cs = env_cpu(env);
31
tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2));
39
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
32
break;
40
index XXXXXXX..XXXXXXX 100644
33
case INDEX_op_ld8s_i32:
41
--- a/target/sh4/translate.c
34
+ TODO();
42
+++ b/target/sh4/translate.c
35
+ break;
43
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
36
case INDEX_op_ld16u_i32:
44
tcg_gen_exit_tb(ctx->base.tb, n);
37
TODO();
45
} else {
38
break;
46
tcg_gen_movi_i32(cpu_pc, dest);
39
@@ -XXX,XX +XXX,XX @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
47
- if (ctx->base.singlestep_enabled) {
40
tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2));
48
- gen_helper_debug(cpu_env);
41
break;
49
- } else if (use_exit_tb(ctx)) {
42
case INDEX_op_ld8s_i64:
50
+ if (use_exit_tb(ctx)) {
43
+ TODO();
51
tcg_gen_exit_tb(NULL, 0);
44
+ break;
52
} else {
45
case INDEX_op_ld16u_i64:
53
tcg_gen_lookup_and_goto_ptr();
46
+ t0 = *tb_ptr++;
54
@@ -XXX,XX +XXX,XX @@ static void gen_jump(DisasContext * ctx)
47
+ t1 = tci_read_r(regs, &tb_ptr);
55
     delayed jump as immediate jump are conditinal jumps */
48
+ t2 = tci_read_s32(&tb_ptr);
56
    tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);
49
+ tci_write_reg16(regs, t0, *(uint16_t *)(t1 + t2));
57
tcg_gen_discard_i32(cpu_delayed_pc);
50
+ break;
58
- if (ctx->base.singlestep_enabled) {
51
case INDEX_op_ld16s_i64:
59
- gen_helper_debug(cpu_env);
52
TODO();
60
- } else if (use_exit_tb(ctx)) {
53
break;
61
+ if (use_exit_tb(ctx)) {
62
tcg_gen_exit_tb(NULL, 0);
63
} else {
64
tcg_gen_lookup_and_goto_ptr();
65
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
66
switch (ctx->base.is_jmp) {
67
case DISAS_STOP:
68
gen_save_cpu_state(ctx, true);
69
- if (ctx->base.singlestep_enabled) {
70
- gen_helper_debug(cpu_env);
71
- } else {
72
- tcg_gen_exit_tb(NULL, 0);
73
- }
74
+ tcg_gen_exit_tb(NULL, 0);
75
break;
76
case DISAS_NEXT:
77
case DISAS_TOO_MANY:
54
--
78
--
55
2.17.1
79
2.25.1
56
80
57
81
diff view generated by jsdifflib
1
The next patch will play a trick with "const" that will
1
GDB single-stepping is now handled generically.
2
confuse the compiler about the uses of target_page_bits
3
within exec.c. Moving everything to a new file prevents
4
this confusion.
5
2
6
No functional change so far.
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
---
5
---
13
Makefile.target | 2 +-
6
target/tricore/helper.h | 1 -
14
include/qemu-common.h | 6 +++++
7
target/tricore/op_helper.c | 7 -------
15
exec-vary.c | 57 +++++++++++++++++++++++++++++++++++++++++++
8
target/tricore/translate.c | 14 +-------------
16
exec.c | 34 --------------------------
9
3 files changed, 1 insertion(+), 21 deletions(-)
17
4 files changed, 64 insertions(+), 35 deletions(-)
18
create mode 100644 exec-vary.c
19
10
20
diff --git a/Makefile.target b/Makefile.target
11
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
21
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
22
--- a/Makefile.target
13
--- a/target/tricore/helper.h
23
+++ b/Makefile.target
14
+++ b/target/tricore/helper.h
24
@@ -XXX,XX +XXX,XX @@ obj-y += trace/
15
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(psw_write, void, env, i32)
25
16
DEF_HELPER_1(psw_read, i32, env)
26
#########################################################
17
/* Exceptions */
27
# cpu emulator library
18
DEF_HELPER_3(raise_exception_sync, noreturn, env, i32, i32)
28
-obj-y += exec.o
19
-DEF_HELPER_2(qemu_excp, noreturn, env, i32)
29
+obj-y += exec.o exec-vary.o
20
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
30
obj-y += accel/
31
obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/tcg-op-vec.o tcg/tcg-op-gvec.o
32
obj-$(CONFIG_TCG) += tcg/tcg-common.o tcg/optimize.o
33
diff --git a/include/qemu-common.h b/include/qemu-common.h
34
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
35
--- a/include/qemu-common.h
22
--- a/target/tricore/op_helper.c
36
+++ b/include/qemu-common.h
23
+++ b/target/tricore/op_helper.c
37
@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu);
24
@@ -XXX,XX +XXX,XX @@ static void raise_exception_sync_helper(CPUTriCoreState *env, uint32_t class,
38
*/
25
raise_exception_sync_internal(env, class, tin, pc, 0);
39
bool set_preferred_target_page_bits(int bits);
26
}
40
27
41
+/**
28
-void helper_qemu_excp(CPUTriCoreState *env, uint32_t excp)
42
+ * finalize_target_page_bits:
43
+ * Commit the final value set by set_preferred_target_page_bits.
44
+ */
45
+void finalize_target_page_bits(void);
46
+
47
/**
48
* Sends a (part of) iovec down a socket, yielding when the socket is full, or
49
* Receives data into a (part of) iovec from a socket,
50
diff --git a/exec-vary.c b/exec-vary.c
51
new file mode 100644
52
index XXXXXXX..XXXXXXX
53
--- /dev/null
54
+++ b/exec-vary.c
55
@@ -XXX,XX +XXX,XX @@
56
+/*
57
+ * Variable page size handling
58
+ *
59
+ * Copyright (c) 2003 Fabrice Bellard
60
+ *
61
+ * This library is free software; you can redistribute it and/or
62
+ * modify it under the terms of the GNU Lesser General Public
63
+ * License as published by the Free Software Foundation; either
64
+ * version 2 of the License, or (at your option) any later version.
65
+ *
66
+ * This library is distributed in the hope that it will be useful,
67
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
68
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
69
+ * Lesser General Public License for more details.
70
+ *
71
+ * You should have received a copy of the GNU Lesser General Public
72
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
73
+ */
74
+
75
+#include "qemu/osdep.h"
76
+#include "qemu-common.h"
77
+#include "exec/exec-all.h"
78
+
79
+#ifdef TARGET_PAGE_BITS_VARY
80
+int target_page_bits;
81
+bool target_page_bits_decided;
82
+#endif
83
+
84
+bool set_preferred_target_page_bits(int bits)
85
+{
86
+ /*
87
+ * The target page size is the lowest common denominator for all
88
+ * the CPUs in the system, so we can only make it smaller, never
89
+ * larger. And we can't make it smaller once we've committed to
90
+ * a particular size.
91
+ */
92
+#ifdef TARGET_PAGE_BITS_VARY
93
+ assert(bits >= TARGET_PAGE_BITS_MIN);
94
+ if (target_page_bits == 0 || target_page_bits > bits) {
95
+ if (target_page_bits_decided) {
96
+ return false;
97
+ }
98
+ target_page_bits = bits;
99
+ }
100
+#endif
101
+ return true;
102
+}
103
+
104
+void finalize_target_page_bits(void)
105
+{
106
+#ifdef TARGET_PAGE_BITS_VARY
107
+ if (target_page_bits == 0) {
108
+ target_page_bits = TARGET_PAGE_BITS_MIN;
109
+ }
110
+ target_page_bits_decided = true;
111
+#endif
112
+}
113
diff --git a/exec.c b/exec.c
114
index XXXXXXX..XXXXXXX 100644
115
--- a/exec.c
116
+++ b/exec.c
117
@@ -XXX,XX +XXX,XX @@ AddressSpace address_space_memory;
118
static MemoryRegion io_mem_unassigned;
119
#endif
120
121
-#ifdef TARGET_PAGE_BITS_VARY
122
-int target_page_bits;
123
-bool target_page_bits_decided;
124
-#endif
125
-
126
CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
127
128
/* current CPU in the current thread. It is only valid inside
129
@@ -XXX,XX +XXX,XX @@ int use_icount;
130
uintptr_t qemu_host_page_size;
131
intptr_t qemu_host_page_mask;
132
133
-bool set_preferred_target_page_bits(int bits)
134
-{
29
-{
135
- /* The target page size is the lowest common denominator for all
30
- CPUState *cs = env_cpu(env);
136
- * the CPUs in the system, so we can only make it smaller, never
31
- cs->exception_index = excp;
137
- * larger. And we can't make it smaller once we've committed to
32
- cpu_loop_exit(cs);
138
- * a particular size.
139
- */
140
-#ifdef TARGET_PAGE_BITS_VARY
141
- assert(bits >= TARGET_PAGE_BITS_MIN);
142
- if (target_page_bits == 0 || target_page_bits > bits) {
143
- if (target_page_bits_decided) {
144
- return false;
145
- }
146
- target_page_bits = bits;
147
- }
148
-#endif
149
- return true;
150
-}
33
-}
151
-
34
-
152
#if !defined(CONFIG_USER_ONLY)
35
/* Addressing mode helper */
153
36
154
-static void finalize_target_page_bits(void)
37
static uint16_t reverse16(uint16_t val)
38
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/tricore/translate.c
41
+++ b/target/tricore/translate.c
42
@@ -XXX,XX +XXX,XX @@ static inline void gen_save_pc(target_ulong pc)
43
tcg_gen_movi_tl(cpu_PC, pc);
44
}
45
46
-static void generate_qemu_excp(DisasContext *ctx, int excp)
155
-{
47
-{
156
-#ifdef TARGET_PAGE_BITS_VARY
48
- TCGv_i32 tmp = tcg_const_i32(excp);
157
- if (target_page_bits == 0) {
49
- gen_helper_qemu_excp(cpu_env, tmp);
158
- target_page_bits = TARGET_PAGE_BITS_MIN;
50
- ctx->base.is_jmp = DISAS_NORETURN;
159
- }
51
- tcg_temp_free(tmp);
160
- target_page_bits_decided = true;
161
-#endif
162
-}
52
-}
163
-
53
-
164
typedef struct PhysPageEntry PhysPageEntry;
54
static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
165
55
{
166
struct PhysPageEntry {
56
if (translator_use_goto_tb(&ctx->base, dest)) {
57
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
58
tcg_gen_exit_tb(ctx->base.tb, n);
59
} else {
60
gen_save_pc(dest);
61
- if (ctx->base.singlestep_enabled) {
62
- generate_qemu_excp(ctx, EXCP_DEBUG);
63
- } else {
64
- tcg_gen_lookup_and_goto_ptr();
65
- }
66
+ tcg_gen_lookup_and_goto_ptr();
67
}
68
}
69
167
--
70
--
168
2.17.1
71
2.25.1
169
72
170
73
diff view generated by jsdifflib
1
From: Wei Yang <richardw.yang@linux.intel.com>
1
GDB single-stepping is now handled generically.
2
2
3
Use ROUND_UP() to define, which is a little bit easy to read.
4
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
7
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
8
Reviewed-by: Juan Quintela <quintela@redhat.com>
9
Signed-off-by: Wei Yang <richardw.yang@linux.intel.com>
10
Message-Id: <20191013021145.16011-2-richardw.yang@linux.intel.com>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
---
4
---
13
include/exec/cpu-all.h | 7 +++----
5
target/xtensa/translate.c | 25 ++++++++-----------------
14
1 file changed, 3 insertions(+), 4 deletions(-)
6
1 file changed, 8 insertions(+), 17 deletions(-)
15
7
16
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
8
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
17
index XXXXXXX..XXXXXXX 100644
9
index XXXXXXX..XXXXXXX 100644
18
--- a/include/exec/cpu-all.h
10
--- a/target/xtensa/translate.c
19
+++ b/include/exec/cpu-all.h
11
+++ b/target/xtensa/translate.c
20
@@ -XXX,XX +XXX,XX @@ extern int target_page_bits;
12
@@ -XXX,XX +XXX,XX @@ static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
21
13
if (dc->icount) {
22
#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
14
tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
23
#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
15
}
24
-#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
16
- if (dc->base.singlestep_enabled) {
25
+#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
17
- gen_exception(dc, EXCP_DEBUG);
26
18
+ if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
27
/* Using intptr_t ensures that qemu_*_page_mask is sign-extended even
19
+ slot = gen_postprocess(dc, slot);
28
* when intptr_t is 32-bit and we are aligning a long long.
20
+ }
29
@@ -XXX,XX +XXX,XX @@ extern int target_page_bits;
21
+ if (slot >= 0) {
30
extern uintptr_t qemu_host_page_size;
22
+ tcg_gen_goto_tb(slot);
31
extern intptr_t qemu_host_page_mask;
23
+ tcg_gen_exit_tb(dc->base.tb, slot);
32
24
} else {
33
-#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
25
- if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
34
-#define REAL_HOST_PAGE_ALIGN(addr) (((addr) + qemu_real_host_page_size - 1) & \
26
- slot = gen_postprocess(dc, slot);
35
- qemu_real_host_page_mask)
27
- }
36
+#define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size)
28
- if (slot >= 0) {
37
+#define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size)
29
- tcg_gen_goto_tb(slot);
38
30
- tcg_gen_exit_tb(dc->base.tb, slot);
39
/* same as PROT_xxx */
31
- } else {
40
#define PAGE_READ 0x0001
32
- tcg_gen_exit_tb(NULL, 0);
33
- }
34
+ tcg_gen_exit_tb(NULL, 0);
35
}
36
dc->base.is_jmp = DISAS_NORETURN;
37
}
38
@@ -XXX,XX +XXX,XX @@ static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
39
case DISAS_NORETURN:
40
break;
41
case DISAS_TOO_MANY:
42
- if (dc->base.singlestep_enabled) {
43
- tcg_gen_movi_i32(cpu_pc, dc->pc);
44
- gen_exception(dc, EXCP_DEBUG);
45
- } else {
46
- gen_jumpi(dc, dc->pc, 0);
47
- }
48
+ gen_jumpi(dc, dc->pc, 0);
49
break;
50
default:
51
g_assert_not_reached();
41
--
52
--
42
2.17.1
53
2.25.1
43
54
44
55
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f.
2
2
3
We document this in docs/devel/load-stores.rst so lets follow it. The
3
Despite a comment saying why cpu_common_props cannot be placed in
4
32 bit and 64 bit access functions have historically not included the
4
a file that is compiled once, it was moved anyway. Revert that.
5
sign so we leave those as is. We also introduce some signed helpers
6
which are used for loading immediate values in the translator.
7
5
8
Fixes: 282dffc8
6
Since then, Property is not defined in hw/core/cpu.h, so it is now
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
easier to declare a function to install the properties rather than
10
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
the Property array itself.
11
Message-Id: <20191021150910.23216-1-alex.bennee@linaro.org>
9
10
Cc: Eduardo Habkost <ehabkost@redhat.com>
11
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
13
---
14
include/exec/cpu_ldst_template.h | 4 ++--
14
include/hw/core/cpu.h | 1 +
15
tcg/tcg.h | 20 ++++++++++++++------
15
cpu.c | 21 +++++++++++++++++++++
16
accel/tcg/cputlb.c | 24 +++++++++++++++++++++---
16
hw/core/cpu-common.c | 17 +----------------
17
target/cris/translate_v10.inc.c | 3 +--
17
3 files changed, 23 insertions(+), 16 deletions(-)
18
4 files changed, 38 insertions(+), 13 deletions(-)
19
18
20
diff --git a/include/exec/cpu_ldst_template.h b/include/exec/cpu_ldst_template.h
19
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
21
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
22
--- a/include/exec/cpu_ldst_template.h
21
--- a/include/hw/core/cpu.h
23
+++ b/include/exec/cpu_ldst_template.h
22
+++ b/include/hw/core/cpu.h
24
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
25
#ifdef SOFTMMU_CODE_ACCESS
24
GCC_FMT_ATTR(2, 3);
26
#define ADDR_READ addr_code
25
27
#define MMUSUFFIX _cmmu
26
/* $(top_srcdir)/cpu.c */
28
-#define URETSUFFIX SUFFIX
27
+void cpu_class_init_props(DeviceClass *dc);
29
-#define SRETSUFFIX SUFFIX
28
void cpu_exec_initfn(CPUState *cpu);
30
+#define URETSUFFIX USUFFIX
29
void cpu_exec_realizefn(CPUState *cpu, Error **errp);
31
+#define SRETSUFFIX glue(s, SUFFIX)
30
void cpu_exec_unrealizefn(CPUState *cpu);
32
#else
31
diff --git a/cpu.c b/cpu.c
33
#define ADDR_READ addr_read
34
#define MMUSUFFIX _mmu
35
diff --git a/tcg/tcg.h b/tcg/tcg.h
36
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
37
--- a/tcg/tcg.h
33
--- a/cpu.c
38
+++ b/tcg/tcg.h
34
+++ b/cpu.c
39
@@ -XXX,XX +XXX,XX @@ void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
35
@@ -XXX,XX +XXX,XX @@ void cpu_exec_unrealizefn(CPUState *cpu)
40
void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
36
cpu_list_remove(cpu);
41
TCGMemOpIdx oi, uintptr_t retaddr);
42
43
-uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
44
+uint8_t helper_ret_ldub_cmmu(CPUArchState *env, target_ulong addr,
45
TCGMemOpIdx oi, uintptr_t retaddr);
46
-uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
47
+int8_t helper_ret_ldsb_cmmu(CPUArchState *env, target_ulong addr,
48
TCGMemOpIdx oi, uintptr_t retaddr);
49
+uint16_t helper_le_lduw_cmmu(CPUArchState *env, target_ulong addr,
50
+ TCGMemOpIdx oi, uintptr_t retaddr);
51
+int16_t helper_le_ldsw_cmmu(CPUArchState *env, target_ulong addr,
52
+ TCGMemOpIdx oi, uintptr_t retaddr);
53
uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
54
TCGMemOpIdx oi, uintptr_t retaddr);
55
uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
56
TCGMemOpIdx oi, uintptr_t retaddr);
57
-uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
58
- TCGMemOpIdx oi, uintptr_t retaddr);
59
+uint16_t helper_be_lduw_cmmu(CPUArchState *env, target_ulong addr,
60
+ TCGMemOpIdx oi, uintptr_t retaddr);
61
+int16_t helper_be_ldsw_cmmu(CPUArchState *env, target_ulong addr,
62
+ TCGMemOpIdx oi, uintptr_t retaddr);
63
uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
64
TCGMemOpIdx oi, uintptr_t retaddr);
65
uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
66
@@ -XXX,XX +XXX,XX @@ uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
67
# define helper_ret_stw_mmu helper_be_stw_mmu
68
# define helper_ret_stl_mmu helper_be_stl_mmu
69
# define helper_ret_stq_mmu helper_be_stq_mmu
70
-# define helper_ret_ldw_cmmu helper_be_ldw_cmmu
71
+# define helper_ret_lduw_cmmu helper_be_lduw_cmmu
72
+# define helper_ret_ldsw_cmmu helper_be_ldsw_cmmu
73
# define helper_ret_ldl_cmmu helper_be_ldl_cmmu
74
# define helper_ret_ldq_cmmu helper_be_ldq_cmmu
75
#else
76
@@ -XXX,XX +XXX,XX @@ uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
77
# define helper_ret_stw_mmu helper_le_stw_mmu
78
# define helper_ret_stl_mmu helper_le_stl_mmu
79
# define helper_ret_stq_mmu helper_le_stq_mmu
80
-# define helper_ret_ldw_cmmu helper_le_ldw_cmmu
81
+# define helper_ret_lduw_cmmu helper_le_lduw_cmmu
82
+# define helper_ret_ldsw_cmmu helper_le_ldsw_cmmu
83
# define helper_ret_ldl_cmmu helper_le_ldl_cmmu
84
# define helper_ret_ldq_cmmu helper_le_ldq_cmmu
85
#endif
86
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/accel/tcg/cputlb.c
89
+++ b/accel/tcg/cputlb.c
90
@@ -XXX,XX +XXX,XX @@ static uint64_t full_ldub_cmmu(CPUArchState *env, target_ulong addr,
91
return load_helper(env, addr, oi, retaddr, MO_8, true, full_ldub_cmmu);
92
}
37
}
93
38
94
-uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
39
+static Property cpu_common_props[] = {
95
+uint8_t helper_ret_ldub_cmmu(CPUArchState *env, target_ulong addr,
40
+#ifndef CONFIG_USER_ONLY
96
TCGMemOpIdx oi, uintptr_t retaddr)
41
+ /*
97
{
42
+ * Create a memory property for softmmu CPU object,
98
return full_ldub_cmmu(env, addr, oi, retaddr);
43
+ * so users can wire up its memory. (This can't go in hw/core/cpu.c
99
}
44
+ * because that file is compiled only once for both user-mode
100
45
+ * and system builds.) The default if no link is set up is to use
101
+int8_t helper_ret_ldsb_cmmu(CPUArchState *env, target_ulong addr,
46
+ * the system address space.
102
+ TCGMemOpIdx oi, uintptr_t retaddr)
47
+ */
48
+ DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
49
+ MemoryRegion *),
50
+#endif
51
+ DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
52
+ DEFINE_PROP_END_OF_LIST(),
53
+};
54
+
55
+void cpu_class_init_props(DeviceClass *dc)
103
+{
56
+{
104
+ return (int8_t) full_ldub_cmmu(env, addr, oi, retaddr);
57
+ device_class_set_props(dc, cpu_common_props);
105
+}
58
+}
106
+
59
+
107
static uint64_t full_le_lduw_cmmu(CPUArchState *env, target_ulong addr,
60
void cpu_exec_initfn(CPUState *cpu)
108
TCGMemOpIdx oi, uintptr_t retaddr)
109
{
61
{
110
@@ -XXX,XX +XXX,XX @@ static uint64_t full_le_lduw_cmmu(CPUArchState *env, target_ulong addr,
62
cpu->as = NULL;
111
full_le_lduw_cmmu);
63
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/core/cpu-common.c
66
+++ b/hw/core/cpu-common.c
67
@@ -XXX,XX +XXX,XX @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
68
return cpu->cpu_index;
112
}
69
}
113
70
114
-uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
71
-static Property cpu_common_props[] = {
115
+uint16_t helper_le_lduw_cmmu(CPUArchState *env, target_ulong addr,
72
-#ifndef CONFIG_USER_ONLY
116
TCGMemOpIdx oi, uintptr_t retaddr)
73
- /* Create a memory property for softmmu CPU object,
74
- * so users can wire up its memory. (This can't go in hw/core/cpu.c
75
- * because that file is compiled only once for both user-mode
76
- * and system builds.) The default if no link is set up is to use
77
- * the system address space.
78
- */
79
- DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
80
- MemoryRegion *),
81
-#endif
82
- DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
83
- DEFINE_PROP_END_OF_LIST(),
84
-};
85
-
86
static void cpu_class_init(ObjectClass *klass, void *data)
117
{
87
{
118
return full_le_lduw_cmmu(env, addr, oi, retaddr);
88
DeviceClass *dc = DEVICE_CLASS(klass);
119
}
89
@@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data)
120
90
dc->realize = cpu_common_realizefn;
121
+int16_t helper_le_ldsw_cmmu(CPUArchState *env, target_ulong addr,
91
dc->unrealize = cpu_common_unrealizefn;
122
+ TCGMemOpIdx oi, uintptr_t retaddr)
92
dc->reset = cpu_common_reset;
123
+{
93
- device_class_set_props(dc, cpu_common_props);
124
+ return (int16_t) full_le_lduw_cmmu(env, addr, oi, retaddr);
94
+ cpu_class_init_props(dc);
125
+}
95
/*
126
+
96
* Reason: CPUs still need special care by board code: wiring up
127
static uint64_t full_be_lduw_cmmu(CPUArchState *env, target_ulong addr,
97
* IRQs, adding reset handlers, halting non-first CPUs, ...
128
TCGMemOpIdx oi, uintptr_t retaddr)
129
{
130
@@ -XXX,XX +XXX,XX @@ static uint64_t full_be_lduw_cmmu(CPUArchState *env, target_ulong addr,
131
full_be_lduw_cmmu);
132
}
133
134
-uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
135
+uint16_t helper_be_lduw_cmmu(CPUArchState *env, target_ulong addr,
136
TCGMemOpIdx oi, uintptr_t retaddr)
137
{
138
return full_be_lduw_cmmu(env, addr, oi, retaddr);
139
}
140
141
+int16_t helper_be_ldsw_cmmu(CPUArchState *env, target_ulong addr,
142
+ TCGMemOpIdx oi, uintptr_t retaddr)
143
+{
144
+ return (int16_t) full_be_lduw_cmmu(env, addr, oi, retaddr);
145
+}
146
+
147
static uint64_t full_le_ldul_cmmu(CPUArchState *env, target_ulong addr,
148
TCGMemOpIdx oi, uintptr_t retaddr)
149
{
150
diff --git a/target/cris/translate_v10.inc.c b/target/cris/translate_v10.inc.c
151
index XXXXXXX..XXXXXXX 100644
152
--- a/target/cris/translate_v10.inc.c
153
+++ b/target/cris/translate_v10.inc.c
154
@@ -XXX,XX +XXX,XX @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
155
case CRISV10_IND_BCC_M:
156
157
cris_cc_mask(dc, 0);
158
- imm = cpu_ldsw_code(env, dc->pc + 2);
159
- simm = (int16_t)imm;
160
+ simm = cpu_ldsw_code(env, dc->pc + 2);
161
simm += 4;
162
163
LOG_DIS("bcc_m: b%s %x\n", cc_name(dc->cond), dc->pc + simm);
164
--
98
--
165
2.17.1
99
2.25.1
166
100
167
101
diff view generated by jsdifflib