| 1 | Changes from v1: dropped SVE patchset. | 1 | This bug seemed worth fixing for 8.0 since we need an rc4 anyway: |
|---|---|---|---|
| 2 | we were using uninitialized data for the guarded bit when | ||
| 3 | combining stage 1 and stage 2 attrs. | ||
| 2 | 4 | ||
| 3 | The following changes since commit 58560ad254fbda71d4daa6622d71683190070ee2: | 5 | thanks |
| 6 | -- PMM | ||
| 4 | 7 | ||
| 5 | Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.2-20191024' into staging (2019-10-24 16:22:58 +0100) | 8 | The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6: |
| 9 | |||
| 10 | Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100) | ||
| 6 | 11 | ||
| 7 | are available in the Git repository at: | 12 | are available in the Git repository at: |
| 8 | 13 | ||
| 9 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191025 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410 |
| 10 | 15 | ||
| 11 | for you to fetch changes up to f9469c1a01c333c08980e083e0ad3417256c8b9c: | 16 | for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308: |
| 12 | 17 | ||
| 13 | hw/arm/highbank: Use AddressSpace when using write_secondary_boot() (2019-10-25 13:09:27 +0100) | 18 | target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100) |
| 14 | 19 | ||
| 15 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
| 16 | target-arm queue: | 21 | target-arm: Fix bug where we weren't initializing |
| 17 | * raspi boards: some cleanup | 22 | guarded bit state when combining S1/S2 attrs |
| 18 | * raspi: implement the bcm2835 system timer device | ||
| 19 | * raspi: implement a dummy thermal sensor | ||
| 20 | * misc devices: switch to ptimer transaction API | ||
| 21 | * cache TB flag state to improve performance of cpu_get_tb_cpu_state | ||
| 22 | * aspeed: Add an AST2600 eval board | ||
| 23 | 23 | ||
| 24 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
| 25 | Cédric Le Goater (2): | 25 | Richard Henderson (2): |
| 26 | hw/gpio: Fix property accessors of the AST2600 GPIO 1.8V model | 26 | target/arm: PTE bit GP only applies to stage1 |
| 27 | aspeed: Add an AST2600 eval board | 27 | target/arm: Copy guarded bit in combine_cacheattrs |
| 28 | 28 | ||
| 29 | Peter Maydell (8): | 29 | target/arm/ptw.c | 11 ++++++----- |
| 30 | hw/net/fsl_etsec/etsec.c: Switch to transaction-based ptimer API | 30 | 1 file changed, 6 insertions(+), 5 deletions(-) |
| 31 | hw/timer/xilinx_timer.c: Switch to transaction-based ptimer API | ||
| 32 | hw/dma/xilinx_axidma.c: Switch to transaction-based ptimer API | ||
| 33 | hw/timer/slavio_timer: Remove useless check for NULL t->timer | ||
| 34 | hw/timer/slavio_timer.c: Switch to transaction-based ptimer API | ||
| 35 | hw/timer/grlib_gptimer.c: Switch to transaction-based ptimer API | ||
| 36 | hw/m68k/mcf5206.c: Switch to transaction-based ptimer API | ||
| 37 | hw/watchdog/milkymist-sysctl.c: Switch to transaction-based ptimer API | ||
| 38 | |||
| 39 | Philippe Mathieu-Daudé (8): | ||
| 40 | hw/misc/bcm2835_thermal: Add a dummy BCM2835 thermal sensor | ||
| 41 | hw/arm/bcm2835_peripherals: Use the thermal sensor block | ||
| 42 | hw/timer/bcm2835: Add the BCM2835 SYS_timer | ||
| 43 | hw/arm/bcm2835_peripherals: Use the SYS_timer | ||
| 44 | hw/arm/bcm2836: Make the SoC code modular | ||
| 45 | hw/arm/bcm2836: Rename cpus[] as cpu[].core | ||
| 46 | hw/arm/raspi: Use AddressSpace when using arm_boot::write_secondary_boot | ||
| 47 | hw/arm/highbank: Use AddressSpace when using write_secondary_boot() | ||
| 48 | |||
| 49 | Richard Henderson (24): | ||
| 50 | target/arm: Split out rebuild_hflags_common | ||
| 51 | target/arm: Split out rebuild_hflags_a64 | ||
| 52 | target/arm: Split out rebuild_hflags_common_32 | ||
| 53 | target/arm: Split arm_cpu_data_is_big_endian | ||
| 54 | target/arm: Split out rebuild_hflags_m32 | ||
| 55 | target/arm: Reduce tests vs M-profile in cpu_get_tb_cpu_state | ||
| 56 | target/arm: Split out rebuild_hflags_a32 | ||
| 57 | target/arm: Split out rebuild_hflags_aprofile | ||
| 58 | target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state | ||
| 59 | target/arm: Simplify set of PSTATE_SS in cpu_get_tb_cpu_state | ||
| 60 | target/arm: Hoist computation of TBFLAG_A32.VFPEN | ||
| 61 | target/arm: Add arm_rebuild_hflags | ||
| 62 | target/arm: Split out arm_mmu_idx_el | ||
| 63 | target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state | ||
| 64 | target/arm: Add HELPER(rebuild_hflags_{a32, a64, m32}) | ||
| 65 | target/arm: Rebuild hflags at EL changes | ||
| 66 | target/arm: Rebuild hflags at MSR writes | ||
| 67 | target/arm: Rebuild hflags at CPSR writes | ||
| 68 | target/arm: Rebuild hflags at Xscale SCTLR writes | ||
| 69 | target/arm: Rebuild hflags for M-profile | ||
| 70 | target/arm: Rebuild hflags for M-profile NVIC | ||
| 71 | linux-user/aarch64: Rebuild hflags for TARGET_WORDS_BIGENDIAN | ||
| 72 | linux-user/arm: Rebuild hflags for TARGET_WORDS_BIGENDIAN | ||
| 73 | target/arm: Rely on hflags correct in cpu_get_tb_cpu_state | ||
| 74 | |||
| 75 | hw/misc/Makefile.objs | 1 + | ||
| 76 | hw/timer/Makefile.objs | 1 + | ||
| 77 | hw/net/fsl_etsec/etsec.h | 1 - | ||
| 78 | include/hw/arm/aspeed.h | 1 + | ||
| 79 | include/hw/arm/bcm2835_peripherals.h | 5 +- | ||
| 80 | include/hw/arm/bcm2836.h | 4 +- | ||
| 81 | include/hw/arm/raspi_platform.h | 1 + | ||
| 82 | include/hw/misc/bcm2835_thermal.h | 27 +++ | ||
| 83 | include/hw/timer/bcm2835_systmr.h | 33 +++ | ||
| 84 | target/arm/cpu.h | 84 +++++--- | ||
| 85 | target/arm/helper.h | 4 + | ||
| 86 | target/arm/internals.h | 9 + | ||
| 87 | hw/arm/aspeed.c | 23 ++ | ||
| 88 | hw/arm/bcm2835_peripherals.c | 30 ++- | ||
| 89 | hw/arm/bcm2836.c | 44 ++-- | ||
| 90 | hw/arm/highbank.c | 3 +- | ||
| 91 | hw/arm/raspi.c | 14 +- | ||
| 92 | hw/dma/xilinx_axidma.c | 9 +- | ||
| 93 | hw/gpio/aspeed_gpio.c | 8 +- | ||
| 94 | hw/intc/armv7m_nvic.c | 22 +- | ||
| 95 | hw/m68k/mcf5206.c | 15 +- | ||
| 96 | hw/misc/bcm2835_thermal.c | 135 ++++++++++++ | ||
| 97 | hw/net/fsl_etsec/etsec.c | 9 +- | ||
| 98 | hw/timer/bcm2835_systmr.c | 163 +++++++++++++++ | ||
| 99 | hw/timer/grlib_gptimer.c | 28 ++- | ||
| 100 | hw/timer/milkymist-sysctl.c | 25 ++- | ||
| 101 | hw/timer/slavio_timer.c | 32 ++- | ||
| 102 | hw/timer/xilinx_timer.c | 13 +- | ||
| 103 | linux-user/aarch64/cpu_loop.c | 1 + | ||
| 104 | linux-user/arm/cpu_loop.c | 1 + | ||
| 105 | linux-user/syscall.c | 1 + | ||
| 106 | target/arm/cpu.c | 1 + | ||
| 107 | target/arm/helper-a64.c | 3 + | ||
| 108 | target/arm/helper.c | 393 +++++++++++++++++++++++------------ | ||
| 109 | target/arm/m_helper.c | 6 + | ||
| 110 | target/arm/machine.c | 1 + | ||
| 111 | target/arm/op_helper.c | 4 + | ||
| 112 | target/arm/translate-a64.c | 13 +- | ||
| 113 | target/arm/translate.c | 33 ++- | ||
| 114 | hw/timer/trace-events | 5 + | ||
| 115 | 40 files changed, 945 insertions(+), 261 deletions(-) | ||
| 116 | create mode 100644 include/hw/misc/bcm2835_thermal.h | ||
| 117 | create mode 100644 include/hw/timer/bcm2835_systmr.h | ||
| 118 | create mode 100644 hw/misc/bcm2835_thermal.c | ||
| 119 | create mode 100644 hw/timer/bcm2835_systmr.c | ||
| 120 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 1 | 2 | ||
| 3 | Only perform the extract of GP during the stage1 walk. | ||
| 4 | |||
| 5 | Reported-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/ptw.c | 10 +++++----- | ||
| 12 | 1 file changed, 5 insertions(+), 5 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/ptw.c | ||
| 17 | +++ b/target/arm/ptw.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
| 19 | result->f.attrs.secure = false; | ||
| 20 | } | ||
| 21 | |||
| 22 | - /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
| 23 | - if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
| 24 | - result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
| 25 | - } | ||
| 26 | - | ||
| 27 | if (regime_is_stage2(mmu_idx)) { | ||
| 28 | result->cacheattrs.is_s2_format = true; | ||
| 29 | result->cacheattrs.attrs = extract32(attrs, 2, 4); | ||
| 30 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
| 31 | assert(attrindx <= 7); | ||
| 32 | result->cacheattrs.is_s2_format = false; | ||
| 33 | result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); | ||
| 34 | + | ||
| 35 | + /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
| 36 | + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
| 37 | + result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
| 38 | + } | ||
| 39 | } | ||
| 40 | |||
| 41 | /* | ||
| 42 | -- | ||
| 43 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 1 | 2 | ||
| 3 | The guarded bit comes from the stage1 walk. | ||
| 4 | |||
| 5 | Fixes: Coverity CID 1507929 | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/ptw.c | 1 + | ||
| 12 | 1 file changed, 1 insertion(+) | ||
| 13 | |||
| 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/ptw.c | ||
| 17 | +++ b/target/arm/ptw.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, | ||
| 19 | |||
| 20 | assert(!s1.is_s2_format); | ||
| 21 | ret.is_s2_format = false; | ||
| 22 | + ret.guarded = s1.guarded; | ||
| 23 | |||
| 24 | if (s1.attrs == 0xf0) { | ||
| 25 | tagged = true; | ||
| 26 | -- | ||
| 27 | 2.34.1 | diff view generated by jsdifflib |