[PULL 00/42] target-arm queue
[PULL 0/3] target-arm queue
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Changes from v1: dropped SVE patchset.
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Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code.
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The following changes since commit 58560ad254fbda71d4daa6622d71683190070ee2:
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-- PMM
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Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.2-20191024' into staging (2019-10-24 16:22:58 +0100)
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The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236:
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Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191025
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801
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for you to fetch changes up to f9469c1a01c333c08980e083e0ad3417256c8b9c:
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for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc:
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hw/arm/highbank: Use AddressSpace when using write_secondary_boot() (2019-10-25 13:09:27 +0100)
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target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* raspi boards: some cleanup
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* Fix KVM SVE ID register probe code
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* raspi: implement the bcm2835 system timer device
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* raspi: implement a dummy thermal sensor
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* misc devices: switch to ptimer transaction API
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* cache TB flag state to improve performance of cpu_get_tb_cpu_state
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* aspeed: Add an AST2600 eval board
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----------------------------------------------------------------
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----------------------------------------------------------------
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Cédric Le Goater (2):
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Richard Henderson (3):
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hw/gpio: Fix property accessors of the AST2600 GPIO 1.8V model
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target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
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aspeed: Add an AST2600 eval board
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target/arm: Set KVM_ARM_VCPU_SVE while probing the host
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target/arm: Move sve probe inside kvm >= 4.15 branch
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Peter Maydell (8):
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target/arm/kvm64.c | 45 ++++++++++++++++++++++-----------------------
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hw/net/fsl_etsec/etsec.c: Switch to transaction-based ptimer API
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1 file changed, 22 insertions(+), 23 deletions(-)
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hw/timer/xilinx_timer.c: Switch to transaction-based ptimer API
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hw/dma/xilinx_axidma.c: Switch to transaction-based ptimer API
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hw/timer/slavio_timer: Remove useless check for NULL t->timer
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hw/timer/slavio_timer.c: Switch to transaction-based ptimer API
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hw/timer/grlib_gptimer.c: Switch to transaction-based ptimer API
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hw/m68k/mcf5206.c: Switch to transaction-based ptimer API
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hw/watchdog/milkymist-sysctl.c: Switch to transaction-based ptimer API
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Philippe Mathieu-Daudé (8):
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hw/misc/bcm2835_thermal: Add a dummy BCM2835 thermal sensor
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hw/arm/bcm2835_peripherals: Use the thermal sensor block
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hw/timer/bcm2835: Add the BCM2835 SYS_timer
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hw/arm/bcm2835_peripherals: Use the SYS_timer
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hw/arm/bcm2836: Make the SoC code modular
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hw/arm/bcm2836: Rename cpus[] as cpu[].core
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hw/arm/raspi: Use AddressSpace when using arm_boot::write_secondary_boot
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hw/arm/highbank: Use AddressSpace when using write_secondary_boot()
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Richard Henderson (24):
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target/arm: Split out rebuild_hflags_common
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target/arm: Split out rebuild_hflags_a64
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target/arm: Split out rebuild_hflags_common_32
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target/arm: Split arm_cpu_data_is_big_endian
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target/arm: Split out rebuild_hflags_m32
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target/arm: Reduce tests vs M-profile in cpu_get_tb_cpu_state
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target/arm: Split out rebuild_hflags_a32
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target/arm: Split out rebuild_hflags_aprofile
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target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state
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target/arm: Simplify set of PSTATE_SS in cpu_get_tb_cpu_state
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target/arm: Hoist computation of TBFLAG_A32.VFPEN
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target/arm: Add arm_rebuild_hflags
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target/arm: Split out arm_mmu_idx_el
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target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state
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target/arm: Add HELPER(rebuild_hflags_{a32, a64, m32})
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target/arm: Rebuild hflags at EL changes
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target/arm: Rebuild hflags at MSR writes
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target/arm: Rebuild hflags at CPSR writes
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target/arm: Rebuild hflags at Xscale SCTLR writes
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target/arm: Rebuild hflags for M-profile
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target/arm: Rebuild hflags for M-profile NVIC
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linux-user/aarch64: Rebuild hflags for TARGET_WORDS_BIGENDIAN
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linux-user/arm: Rebuild hflags for TARGET_WORDS_BIGENDIAN
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target/arm: Rely on hflags correct in cpu_get_tb_cpu_state
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hw/misc/Makefile.objs | 1 +
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hw/timer/Makefile.objs | 1 +
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hw/net/fsl_etsec/etsec.h | 1 -
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include/hw/arm/aspeed.h | 1 +
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include/hw/arm/bcm2835_peripherals.h | 5 +-
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include/hw/arm/bcm2836.h | 4 +-
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include/hw/arm/raspi_platform.h | 1 +
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include/hw/misc/bcm2835_thermal.h | 27 +++
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include/hw/timer/bcm2835_systmr.h | 33 +++
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target/arm/cpu.h | 84 +++++---
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target/arm/helper.h | 4 +
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target/arm/internals.h | 9 +
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hw/arm/aspeed.c | 23 ++
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hw/arm/bcm2835_peripherals.c | 30 ++-
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hw/arm/bcm2836.c | 44 ++--
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hw/arm/highbank.c | 3 +-
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hw/arm/raspi.c | 14 +-
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hw/dma/xilinx_axidma.c | 9 +-
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hw/gpio/aspeed_gpio.c | 8 +-
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hw/intc/armv7m_nvic.c | 22 +-
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hw/m68k/mcf5206.c | 15 +-
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hw/misc/bcm2835_thermal.c | 135 ++++++++++++
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hw/net/fsl_etsec/etsec.c | 9 +-
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hw/timer/bcm2835_systmr.c | 163 +++++++++++++++
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hw/timer/grlib_gptimer.c | 28 ++-
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hw/timer/milkymist-sysctl.c | 25 ++-
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hw/timer/slavio_timer.c | 32 ++-
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hw/timer/xilinx_timer.c | 13 +-
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linux-user/aarch64/cpu_loop.c | 1 +
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linux-user/arm/cpu_loop.c | 1 +
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linux-user/syscall.c | 1 +
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target/arm/cpu.c | 1 +
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target/arm/helper-a64.c | 3 +
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target/arm/helper.c | 393 +++++++++++++++++++++++------------
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target/arm/m_helper.c | 6 +
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target/arm/machine.c | 1 +
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target/arm/op_helper.c | 4 +
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target/arm/translate-a64.c | 13 +-
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target/arm/translate.c | 33 ++-
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hw/timer/trace-events | 5 +
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40 files changed, 945 insertions(+), 261 deletions(-)
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create mode 100644 include/hw/misc/bcm2835_thermal.h
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create mode 100644 include/hw/timer/bcm2835_systmr.h
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create mode 100644 hw/misc/bcm2835_thermal.c
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create mode 100644 hw/timer/bcm2835_systmr.c
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diff view generated by jsdifflib
New patch
[PULL 1/3] target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
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From: Richard Henderson <richard.henderson@linaro.org>
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Indication for support for SVE will not depend on whether we
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perform the query on the main kvm_state or the temp vcpu.
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-2-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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}
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}
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- sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
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+ sve_supported = kvm_arm_sve_supported();
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/* Add feature bits that can't appear until after VCPU init. */
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if (sve_supported) {
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--
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2.25.1
diff view generated by jsdifflib
New patch
[PULL 2/3] target/arm: Set KVM_ARM_VCPU_SVE while probing the host
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From: Richard Henderson <richard.henderson@linaro.org>
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Because we weren't setting this flag, our probe of ID_AA64ZFR0
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was always returning zero. This also obviates the adjustment
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of ID_AA64PFR0, which had sanitized the SVE field.
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The effects of the bug are not visible, because the only thing that
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ID_AA64ZFR0 is used for within qemu at present is tcg translation.
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The other tests for SVE within KVM are via ID_AA64PFR0.SVE.
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Reported-by: Zenghui Yu <yuzenghui@huawei.com>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-3-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 27 +++++++++++++--------------
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1 file changed, 13 insertions(+), 14 deletions(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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bool sve_supported;
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bool pmu_supported = false;
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uint64_t features = 0;
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- uint64_t t;
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int err;
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/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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struct kvm_vcpu_init init = { .target = -1, };
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/*
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- * Ask for Pointer Authentication if supported. We can't play the
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- * SVE trick of synthesising the ID reg as KVM won't tell us
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- * whether we have the architected or IMPDEF version of PAuth, so
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- * we have to use the actual ID regs.
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+ * Ask for SVE if supported, so that we can query ID_AA64ZFR0,
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+ * which is otherwise RAZ.
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+ */
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+ sve_supported = kvm_arm_sve_supported();
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+ if (sve_supported) {
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+ init.features[0] |= 1 << KVM_ARM_VCPU_SVE;
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+ }
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+
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+ /*
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+ * Ask for Pointer Authentication if supported, so that we get
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+ * the unsanitized field values for AA64ISAR1_EL1.
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*/
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if (kvm_arm_pauth_supported()) {
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init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS |
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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}
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}
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- sve_supported = kvm_arm_sve_supported();
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-
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- /* Add feature bits that can't appear until after VCPU init. */
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if (sve_supported) {
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- t = ahcf->isar.id_aa64pfr0;
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- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
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- ahcf->isar.id_aa64pfr0 = t;
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-
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/*
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* There is a range of kernels between kernel commit 73433762fcae
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* and f81cb2c3ad41 which have a bug where the kernel doesn't expose
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* SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
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- * SVE support, so we only read it here, rather than together with all
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- * the other ID registers earlier.
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+ * SVE support, which resulted in an error rather than RAZ.
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+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
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*/
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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ARM64_SYS_REG(3, 0, 0, 4, 4));
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--
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2.25.1
diff view generated by jsdifflib
New patch
[PULL 3/3] target/arm: Move sve probe inside kvm >= 4.15 branch
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From: Richard Henderson <richard.henderson@linaro.org>
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The test for the IF block indicates no ID registers are exposed, much
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less host support for SVE. Move the SVE probe into the ELSE block.
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-4-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 22 +++++++++++-----------
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1 file changed, 11 insertions(+), 11 deletions(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
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ARM64_SYS_REG(3, 3, 9, 12, 0));
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}
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- }
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- if (sve_supported) {
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- /*
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- * There is a range of kernels between kernel commit 73433762fcae
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- * and f81cb2c3ad41 which have a bug where the kernel doesn't expose
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- * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
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- * SVE support, which resulted in an error rather than RAZ.
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- * So only read the register if we set KVM_ARM_VCPU_SVE above.
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- */
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- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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- ARM64_SYS_REG(3, 0, 0, 4, 4));
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+ if (sve_supported) {
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+ /*
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+ * There is a range of kernels between kernel commit 73433762fcae
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+ * and f81cb2c3ad41 which have a bug where the kernel doesn't
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+ * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
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+ * enabled SVE support, which resulted in an error rather than RAZ.
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+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
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+ */
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+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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+ ARM64_SYS_REG(3, 0, 0, 4, 4));
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+ }
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}
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kvm_arm_destroy_scratch_host_vcpu(fdarray);
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--
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2.25.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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