[PULL 00/41] target-arm queue
[PULL v2 00/11] target-arm queue
1
The big thing in here is RTH's caching-of-tb-flags patchset
1
Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx
2
which should improve TCG performance.
2
ethernet device failed 'make check' on big-endian hosts.
3
3
4
thanks
5
-- PMM
4
-- PMM
6
5
7
The following changes since commit 2152e740a8938b3bad73bfe1a01f8b94dab02d41:
6
The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf:
8
7
9
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-request' into staging (2019-10-22 12:03:03 +0100)
8
Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000)
10
9
11
are available in the Git repository at:
10
are available in the Git repository at:
12
11
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191022
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1
14
13
15
for you to fetch changes up to 833043a060f7d0e95ded88e61e992466305c0345:
14
for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621:
16
15
17
hw/arm/digic4: Inline digic4_board_setup_ram() function (2019-10-22 14:21:57 +0100)
16
target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000)
18
17
19
----------------------------------------------------------------
18
----------------------------------------------------------------
20
target-arm queue:
19
target-arm queue:
21
* Fix sign-extension for SMLAL* instructions
20
* Correctly initialize MDCR_EL2.HPMN
22
* aspeed: Add an AST2600 eval board
21
* versal: Use nr_apu_cpus in favor of hard coding 2
23
* Various ptimer device conversions to new transaction API
22
* accel/tcg: Add URL of clang bug to comment about our workaround
24
* Cache TB flags to avoid expensively recomputing them every time
23
* Add support for FEAT_DIT, Data Independent Timing
25
* Add a dummy Samsung SDHCI controller model to exynos4 boards
24
* Remove GPIO from unimplemented NPCM7XX
26
* Minor refactorings of RAM creation for some arm boards
25
* Fix SCR RES1 handling
26
* Don't migrate CPUARMState.features
27
27
28
----------------------------------------------------------------
28
----------------------------------------------------------------
29
Cédric Le Goater (1):
29
Aaron Lindsay (1):
30
aspeed: Add an AST2600 eval board
30
target/arm: Don't migrate CPUARMState.features
31
31
32
Guenter Roeck (1):
32
Daniel Müller (1):
33
hw/timer/exynos4210_mct: Initialize ptimer before starting it
33
target/arm: Correctly initialize MDCR_EL2.HPMN
34
34
35
Peter Maydell (7):
35
Edgar E. Iglesias (1):
36
hw/timer/arm_mptimer.c: Undo accidental rename of arm_mptimer_init()
36
hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
37
hw/timer/puv3_ost.c: Switch to transaction-based ptimer API
38
hw/timer/sh_timer: Switch to transaction-based ptimer API
39
hw/timer/lm32_timer: Switch to transaction-based ptimer API
40
hw/timer/altera_timer.c: Switch to transaction-based ptimer API
41
hw/watchdog/etraxfs_timer.c: Switch to transaction-based ptimer API
42
hw/m68k/mcf5208.c: Switch to transaction-based ptimer API
43
37
44
Philippe Mathieu-Daudé (9):
38
Hao Wu (1):
45
hw/sd/sdhci: Add a comment to distinct the i.MX eSDHC functions
39
hw/arm: Remove GPIO from unimplemented NPCM7XX
46
hw/sd/sdhci: Add dummy Samsung SDHCI controller
47
hw/arm/exynos4210: Use the Samsung s3c SDHCI controller
48
hw/arm/xilinx_zynq: Use the IEC binary prefix definitions
49
hw/arm/mps2: Use the IEC binary prefix definitions
50
hw/arm/collie: Create the RAM in the board
51
hw/arm/omap2: Create the RAM in the board
52
hw/arm/omap1: Create the RAM in the board
53
hw/arm/digic4: Inline digic4_board_setup_ram() function
54
40
55
Richard Henderson (23):
41
Mike Nawrocki (1):
56
target/arm: Fix sign-extension for SMLAL*
42
target/arm: Fix SCR RES1 handling
57
target/arm: Split out rebuild_hflags_common
58
target/arm: Split out rebuild_hflags_a64
59
target/arm: Split out rebuild_hflags_common_32
60
target/arm: Split arm_cpu_data_is_big_endian
61
target/arm: Split out rebuild_hflags_m32
62
target/arm: Reduce tests vs M-profile in cpu_get_tb_cpu_state
63
target/arm: Split out rebuild_hflags_a32
64
target/arm: Split out rebuild_hflags_aprofile
65
target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state
66
target/arm: Simplify set of PSTATE_SS in cpu_get_tb_cpu_state
67
target/arm: Hoist computation of TBFLAG_A32.VFPEN
68
target/arm: Add arm_rebuild_hflags
69
target/arm: Split out arm_mmu_idx_el
70
target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state
71
target/arm: Add HELPER(rebuild_hflags_{a32, a64, m32})
72
target/arm: Rebuild hflags at EL changes
73
target/arm: Rebuild hflags at MSR writes
74
target/arm: Rebuild hflags at CPSR writes
75
target/arm: Rebuild hflags at Xscale SCTLR writes
76
target/arm: Rebuild hflags for M-profile
77
target/arm: Rebuild hflags for M-profile NVIC
78
target/arm: Rely on hflags correct in cpu_get_tb_cpu_state
79
43
80
hw/arm/strongarm.h | 4 +-
44
Peter Maydell (2):
81
include/hw/arm/aspeed.h | 1 +
45
arm: Update infocenter.arm.com URLs
82
include/hw/arm/omap.h | 10 +-
46
accel/tcg: Add URL of clang bug to comment about our workaround
83
include/hw/sd/sdhci.h | 2 +
84
target/arm/cpu.h | 84 ++++++----
85
target/arm/helper.h | 4 +
86
target/arm/internals.h | 9 ++
87
hw/arm/aspeed.c | 23 +++
88
hw/arm/collie.c | 8 +-
89
hw/arm/digic_boards.c | 9 +-
90
hw/arm/exynos4210.c | 2 +-
91
hw/arm/mps2-tz.c | 3 +-
92
hw/arm/mps2.c | 3 +-
93
hw/arm/nseries.c | 10 +-
94
hw/arm/omap1.c | 12 +-
95
hw/arm/omap2.c | 13 +-
96
hw/arm/omap_sx1.c | 8 +-
97
hw/arm/palm.c | 8 +-
98
hw/arm/strongarm.c | 7 +-
99
hw/arm/xilinx_zynq.c | 3 +-
100
hw/intc/armv7m_nvic.c | 22 +--
101
hw/m68k/mcf5208.c | 9 +-
102
hw/sd/sdhci.c | 68 +++++++-
103
hw/timer/altera_timer.c | 13 +-
104
hw/timer/arm_mptimer.c | 4 +-
105
hw/timer/etraxfs_timer.c | 23 +--
106
hw/timer/exynos4210_mct.c | 2 +-
107
hw/timer/lm32_timer.c | 13 +-
108
hw/timer/puv3_ost.c | 9 +-
109
hw/timer/sh_timer.c | 13 +-
110
linux-user/syscall.c | 1 +
111
target/arm/cpu.c | 1 +
112
target/arm/helper-a64.c | 3 +
113
target/arm/helper.c | 393 +++++++++++++++++++++++++++++----------------
114
target/arm/m_helper.c | 6 +
115
target/arm/machine.c | 1 +
116
target/arm/op_helper.c | 4 +
117
target/arm/translate-a64.c | 13 +-
118
target/arm/translate.c | 37 ++++-
119
39 files changed, 588 insertions(+), 270 deletions(-)
120
47
48
Rebecca Cran (4):
49
target/arm: Add support for FEAT_DIT, Data Independent Timing
50
target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
51
target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
52
target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU
53
54
include/hw/dma/pl080.h | 7 ++--
55
include/hw/misc/arm_integrator_debug.h | 2 +-
56
include/hw/ssi/pl022.h | 5 ++-
57
target/arm/cpu.h | 17 ++++++++
58
target/arm/internals.h | 6 +++
59
accel/tcg/cpu-exec.c | 25 +++++++++---
60
hw/arm/aspeed_ast2600.c | 2 +-
61
hw/arm/musca.c | 4 +-
62
hw/arm/npcm7xx.c | 8 ----
63
hw/arm/xlnx-versal.c | 4 +-
64
hw/misc/arm_integrator_debug.c | 2 +-
65
hw/timer/arm_timer.c | 7 ++--
66
target/arm/cpu.c | 4 ++
67
target/arm/cpu64.c | 5 +++
68
target/arm/helper-a64.c | 27 +++++++++++--
69
target/arm/helper.c | 71 +++++++++++++++++++++++++++-------
70
target/arm/machine.c | 2 +-
71
target/arm/op_helper.c | 9 +----
72
target/arm/translate-a64.c | 12 ++++++
73
19 files changed, 164 insertions(+), 55 deletions(-)
74
diff view generated by jsdifflib
[PULL 01/41] target/arm: Fix sign-extension for SMLAL*
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
The 32-bit product should be sign-extended, not zero-extended.
4
5
Fixes: ea96b374641b
6
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
Message-id: 20190912183058.17947-1-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/translate.c | 4 +++-
14
1 file changed, 3 insertions(+), 1 deletion(-)
15
16
diff --git a/target/arm/translate.c b/target/arm/translate.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate.c
19
+++ b/target/arm/translate.c
20
@@ -XXX,XX +XXX,XX @@ static bool op_smlaxxx(DisasContext *s, arg_rrrr *a,
21
case 2:
22
tl = load_reg(s, a->ra);
23
th = load_reg(s, a->rd);
24
- t1 = tcg_const_i32(0);
25
+ /* Sign-extend the 32-bit product to 64 bits. */
26
+ t1 = tcg_temp_new_i32();
27
+ tcg_gen_sari_i32(t1, t0, 31);
28
tcg_gen_add2_i32(tl, th, tl, th, t0, t1);
29
tcg_temp_free_i32(t0);
30
tcg_temp_free_i32(t1);
31
--
32
2.20.1
33
34
diff view generated by jsdifflib
[PULL 02/41] aspeed: Add an AST2600 eval board
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
Define the board with 1 GiB of RAM but some boards can have up to 2
4
GiB.
5
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7
Reviewed-by: Joel Stanley <joel@jms.id.au>
8
Message-id: 20191016090745.15334-1-clg@kaod.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/aspeed.h | 1 +
12
hw/arm/aspeed.c | 23 +++++++++++++++++++++++
13
2 files changed, 24 insertions(+)
14
15
diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/aspeed.h
18
+++ b/include/hw/arm/aspeed.h
19
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedBoardConfig {
20
const char *desc;
21
const char *soc_name;
22
uint32_t hw_strap1;
23
+ uint32_t hw_strap2;
24
const char *fmc_model;
25
const char *spi_model;
26
uint32_t num_cs;
27
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/arm/aspeed.c
30
+++ b/hw/arm/aspeed.c
31
@@ -XXX,XX +XXX,XX @@ struct AspeedBoardState {
32
/* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
33
#define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
34
35
+/* AST2600 evb hardware value */
36
+#define AST2600_EVB_HW_STRAP1 0x000000C0
37
+#define AST2600_EVB_HW_STRAP2 0x00000003
38
+
39
/*
40
* The max ram region is for firmwares that scan the address space
41
* with load/store to guess how much RAM the SoC has.
42
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
43
&error_abort);
44
object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1",
45
&error_abort);
46
+ object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap2, "hw-strap2",
47
+ &error_abort);
48
object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs",
49
&error_abort);
50
object_property_set_int(OBJECT(&bmc->soc), machine->smp.cpus, "num-cpus",
51
@@ -XXX,XX +XXX,XX @@ static void ast2500_evb_i2c_init(AspeedBoardState *bmc)
52
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
53
}
54
55
+static void ast2600_evb_i2c_init(AspeedBoardState *bmc)
56
+{
57
+ /* Start with some devices on our I2C busses */
58
+ ast2500_evb_i2c_init(bmc);
59
+}
60
+
61
static void romulus_bmc_i2c_init(AspeedBoardState *bmc)
62
{
63
AspeedSoCState *soc = &bmc->soc;
64
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
65
.num_cs = 2,
66
.i2c_init = witherspoon_bmc_i2c_init,
67
.ram = 512 * MiB,
68
+ }, {
69
+ .name = MACHINE_TYPE_NAME("ast2600-evb"),
70
+ .desc = "Aspeed AST2600 EVB (Cortex A7)",
71
+ .soc_name = "ast2600-a0",
72
+ .hw_strap1 = AST2600_EVB_HW_STRAP1,
73
+ .hw_strap2 = AST2600_EVB_HW_STRAP2,
74
+ .fmc_model = "w25q512jv",
75
+ .spi_model = "mx66u51235f",
76
+ .num_cs = 1,
77
+ .i2c_init = ast2600_evb_i2c_init,
78
+ .ram = 1 * GiB,
79
},
80
};
81
82
--
83
2.20.1
84
85
diff view generated by jsdifflib
[PULL 03/41] hw/timer/exynos4210_mct: Initialize ptimer before starting it
Deleted patch
1
From: Guenter Roeck <linux@roeck-us.net>
2
1
3
When booting a recent Linux kernel, the qemu message "Timer with delta
4
zero, disabling" is seen, apparently because a ptimer is started before
5
being initialized. Fix the problem by initializing the offending ptimer
6
before starting it.
7
8
The bug is effectively harmless in the old QEMUBH setup
9
because the sequence of events is:
10
* the delta zero means the timer expires immediately
11
* ptimer_reload() arranges for exynos4210_gfrc_event() to be called
12
* ptimer_reload() notices the zero delta and disables the timer
13
* later, the QEMUBH runs, and exynos4210_gfrc_event() correctly
14
configures the timer and restarts it
15
16
In the new transaction based API the bug is still harmless,
17
but differences of when the callback function runs mean the
18
message is not printed any more:
19
* ptimer_run() does nothing as it's inside a transaction block
20
* ptimer_transaction_commit() sees it has work to do and
21
calls ptimer_reload()
22
* the zero delta means the timer expires immediately
23
* ptimer_reload() calls exynos4210_gfrc_event() directly
24
* exynos4210_gfrc_event() configures the timer
25
* the delta is no longer zero so ptimer_reload() doesn't complain
26
(the zero-delta test is after the trigger-callback in
27
the ptimer_reload() function)
28
29
Regardless, the behaviour here was not intentional, and we should
30
just program the ptimer correctly to start with.
31
32
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
33
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
34
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
36
Message-id: 20191018143149.9216-1-peter.maydell@linaro.org
37
[PMM: Expansion/clarification of the commit message:
38
the message is about a zero delta, not a zero period;
39
added detail to the commit message of the analysis of what
40
is happening and why the kernel boots even with the message;
41
added note that the message goes away with the new ptimer API]
42
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
43
---
44
hw/timer/exynos4210_mct.c | 2 +-
45
1 file changed, 1 insertion(+), 1 deletion(-)
46
47
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/hw/timer/exynos4210_mct.c
50
+++ b/hw/timer/exynos4210_mct.c
51
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
52
/* Start FRC if transition from disabled to enabled */
53
if ((value & G_TCON_TIMER_ENABLE) > (old_val &
54
G_TCON_TIMER_ENABLE)) {
55
- exynos4210_gfrc_start(&s->g_timer);
56
+ exynos4210_gfrc_restart(s);
57
}
58
if ((value & G_TCON_TIMER_ENABLE) < (old_val &
59
G_TCON_TIMER_ENABLE)) {
60
--
61
2.20.1
62
63
diff view generated by jsdifflib
[PULL 04/41] hw/timer/arm_mptimer.c: Undo accidental rename of arm_mptimer_init()
Deleted patch
1
In commit b01422622b we did an automated rename of the ptimer_init()
2
function to ptimer_init_with_bh(). Unfortunately this caught the
3
unrelated arm_mptimer_init() function. Undo that accidental
4
renaming.
5
1
6
Fixes: b01422622b7c7293196fdaf1dbb4f495af44ecf9
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 20191017133331.5901-1-peter.maydell@linaro.org
11
---
12
hw/timer/arm_mptimer.c | 4 ++--
13
1 file changed, 2 insertions(+), 2 deletions(-)
14
15
diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/timer/arm_mptimer.c
18
+++ b/hw/timer/arm_mptimer.c
19
@@ -XXX,XX +XXX,XX @@ static void arm_mptimer_reset(DeviceState *dev)
20
}
21
}
22
23
-static void arm_mptimer_init_with_bh(Object *obj)
24
+static void arm_mptimer_init(Object *obj)
25
{
26
ARMMPTimerState *s = ARM_MPTIMER(obj);
27
28
@@ -XXX,XX +XXX,XX @@ static const TypeInfo arm_mptimer_info = {
29
.name = TYPE_ARM_MPTIMER,
30
.parent = TYPE_SYS_BUS_DEVICE,
31
.instance_size = sizeof(ARMMPTimerState),
32
- .instance_init = arm_mptimer_init_with_bh,
33
+ .instance_init = arm_mptimer_init,
34
.class_init = arm_mptimer_class_init,
35
};
36
37
--
38
2.20.1
39
40
diff view generated by jsdifflib
[PULL 05/41] hw/timer/puv3_ost.c: Switch to transaction-based ptimer API
Deleted patch
1
Switch the puv3_ost code away from bottom-half based ptimers to the
2
new transaction-based ptimer API. This just requires adding
3
begin/commit calls around the various places that modify the ptimer
4
state, and using the new ptimer_init() function to create the timer.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20191017132905.5604-2-peter.maydell@linaro.org
10
---
11
hw/timer/puv3_ost.c | 9 +++++----
12
1 file changed, 5 insertions(+), 4 deletions(-)
13
14
diff --git a/hw/timer/puv3_ost.c b/hw/timer/puv3_ost.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/timer/puv3_ost.c
17
+++ b/hw/timer/puv3_ost.c
18
@@ -XXX,XX +XXX,XX @@
19
#include "hw/sysbus.h"
20
#include "hw/irq.h"
21
#include "hw/ptimer.h"
22
-#include "qemu/main-loop.h"
23
#include "qemu/module.h"
24
25
#undef DEBUG_PUV3
26
@@ -XXX,XX +XXX,XX @@ typedef struct PUV3OSTState {
27
SysBusDevice parent_obj;
28
29
MemoryRegion iomem;
30
- QEMUBH *bh;
31
qemu_irq irq;
32
ptimer_state *ptimer;
33
34
@@ -XXX,XX +XXX,XX @@ static void puv3_ost_write(void *opaque, hwaddr offset,
35
DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
36
switch (offset) {
37
case 0x00: /* Match Register 0 */
38
+ ptimer_transaction_begin(s->ptimer);
39
s->reg_OSMR0 = value;
40
if (s->reg_OSMR0 > s->reg_OSCR) {
41
ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR);
42
@@ -XXX,XX +XXX,XX @@ static void puv3_ost_write(void *opaque, hwaddr offset,
43
(0xffffffff - s->reg_OSCR));
44
}
45
ptimer_run(s->ptimer, 2);
46
+ ptimer_transaction_commit(s->ptimer);
47
break;
48
case 0x14: /* Status Register */
49
assert(value == 0);
50
@@ -XXX,XX +XXX,XX @@ static void puv3_ost_realize(DeviceState *dev, Error **errp)
51
52
sysbus_init_irq(sbd, &s->irq);
53
54
- s->bh = qemu_bh_new(puv3_ost_tick, s);
55
- s->ptimer = ptimer_init_with_bh(s->bh, PTIMER_POLICY_DEFAULT);
56
+ s->ptimer = ptimer_init(puv3_ost_tick, s, PTIMER_POLICY_DEFAULT);
57
+ ptimer_transaction_begin(s->ptimer);
58
ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
59
+ ptimer_transaction_commit(s->ptimer);
60
61
memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost",
62
PUV3_REGS_OFFSET);
63
--
64
2.20.1
65
66
diff view generated by jsdifflib
[PULL 06/41] hw/timer/sh_timer: Switch to transaction-based ptimer API
Deleted patch
1
Switch the sh_timer code away from bottom-half based ptimers to the
2
new transaction-based ptimer API. This just requires adding
3
begin/commit calls around the various places that modify the ptimer
4
state, and using the new ptimer_init() function to create the timer.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20191017132905.5604-3-peter.maydell@linaro.org
10
---
11
hw/timer/sh_timer.c | 13 +++++++++----
12
1 file changed, 9 insertions(+), 4 deletions(-)
13
14
diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/timer/sh_timer.c
17
+++ b/hw/timer/sh_timer.c
18
@@ -XXX,XX +XXX,XX @@
19
#include "hw/irq.h"
20
#include "hw/sh4/sh.h"
21
#include "qemu/timer.h"
22
-#include "qemu/main-loop.h"
23
#include "hw/ptimer.h"
24
25
//#define DEBUG_TIMER
26
@@ -XXX,XX +XXX,XX @@ static void sh_timer_write(void *opaque, hwaddr offset,
27
switch (offset >> 2) {
28
case OFFSET_TCOR:
29
s->tcor = value;
30
+ ptimer_transaction_begin(s->timer);
31
ptimer_set_limit(s->timer, s->tcor, 0);
32
+ ptimer_transaction_commit(s->timer);
33
break;
34
case OFFSET_TCNT:
35
s->tcnt = value;
36
+ ptimer_transaction_begin(s->timer);
37
ptimer_set_count(s->timer, s->tcnt);
38
+ ptimer_transaction_commit(s->timer);
39
break;
40
case OFFSET_TCR:
41
+ ptimer_transaction_begin(s->timer);
42
if (s->enabled) {
43
/* Pause the timer if it is running. This may cause some
44
inaccuracy dure to rounding, but avoids a whole lot of other
45
@@ -XXX,XX +XXX,XX @@ static void sh_timer_write(void *opaque, hwaddr offset,
46
/* Restart the timer if still enabled. */
47
ptimer_run(s->timer, 0);
48
}
49
+ ptimer_transaction_commit(s->timer);
50
break;
51
case OFFSET_TCPR:
52
if (s->feat & TIMER_FEAT_CAPT) {
53
@@ -XXX,XX +XXX,XX @@ static void sh_timer_start_stop(void *opaque, int enable)
54
printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
55
#endif
56
57
+ ptimer_transaction_begin(s->timer);
58
if (s->enabled && !enable) {
59
ptimer_stop(s->timer);
60
}
61
if (!s->enabled && enable) {
62
ptimer_run(s->timer, 0);
63
}
64
+ ptimer_transaction_commit(s->timer);
65
s->enabled = !!enable;
66
67
#ifdef DEBUG_TIMER
68
@@ -XXX,XX +XXX,XX @@ static void sh_timer_tick(void *opaque)
69
static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
70
{
71
sh_timer_state *s;
72
- QEMUBH *bh;
73
74
s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state));
75
s->freq = freq;
76
@@ -XXX,XX +XXX,XX @@ static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
77
s->enabled = 0;
78
s->irq = irq;
79
80
- bh = qemu_bh_new(sh_timer_tick, s);
81
- s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT);
82
+ s->timer = ptimer_init(sh_timer_tick, s, PTIMER_POLICY_DEFAULT);
83
84
sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
85
sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
86
--
87
2.20.1
88
89
diff view generated by jsdifflib
[PULL 07/41] hw/timer/lm32_timer: Switch to transaction-based ptimer API
Deleted patch
1
Switch the lm32_timer code away from bottom-half based ptimers to the
2
new transaction-based ptimer API. This just requires adding
3
begin/commit calls around the various places that modify the ptimer
4
state, and using the new ptimer_init() function to create the ytimer.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20191017132905.5604-4-peter.maydell@linaro.org
10
---
11
hw/timer/lm32_timer.c | 13 +++++++++----
12
1 file changed, 9 insertions(+), 4 deletions(-)
13
14
diff --git a/hw/timer/lm32_timer.c b/hw/timer/lm32_timer.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/timer/lm32_timer.c
17
+++ b/hw/timer/lm32_timer.c
18
@@ -XXX,XX +XXX,XX @@
19
#include "hw/ptimer.h"
20
#include "hw/qdev-properties.h"
21
#include "qemu/error-report.h"
22
-#include "qemu/main-loop.h"
23
#include "qemu/module.h"
24
25
#define DEFAULT_FREQUENCY (50*1000000)
26
@@ -XXX,XX +XXX,XX @@ struct LM32TimerState {
27
28
MemoryRegion iomem;
29
30
- QEMUBH *bh;
31
ptimer_state *ptimer;
32
33
qemu_irq irq;
34
@@ -XXX,XX +XXX,XX @@ static void timer_write(void *opaque, hwaddr addr,
35
s->regs[R_SR] &= ~SR_TO;
36
break;
37
case R_CR:
38
+ ptimer_transaction_begin(s->ptimer);
39
s->regs[R_CR] = value;
40
if (s->regs[R_CR] & CR_START) {
41
ptimer_run(s->ptimer, 1);
42
@@ -XXX,XX +XXX,XX @@ static void timer_write(void *opaque, hwaddr addr,
43
if (s->regs[R_CR] & CR_STOP) {
44
ptimer_stop(s->ptimer);
45
}
46
+ ptimer_transaction_commit(s->ptimer);
47
break;
48
case R_PERIOD:
49
s->regs[R_PERIOD] = value;
50
+ ptimer_transaction_begin(s->ptimer);
51
ptimer_set_count(s->ptimer, value);
52
+ ptimer_transaction_commit(s->ptimer);
53
break;
54
case R_SNAPSHOT:
55
error_report("lm32_timer: write access to read only register 0x"
56
@@ -XXX,XX +XXX,XX @@ static void timer_reset(DeviceState *d)
57
for (i = 0; i < R_MAX; i++) {
58
s->regs[i] = 0;
59
}
60
+ ptimer_transaction_begin(s->ptimer);
61
ptimer_stop(s->ptimer);
62
+ ptimer_transaction_commit(s->ptimer);
63
}
64
65
static void lm32_timer_init(Object *obj)
66
@@ -XXX,XX +XXX,XX @@ static void lm32_timer_realize(DeviceState *dev, Error **errp)
67
{
68
LM32TimerState *s = LM32_TIMER(dev);
69
70
- s->bh = qemu_bh_new(timer_hit, s);
71
- s->ptimer = ptimer_init_with_bh(s->bh, PTIMER_POLICY_DEFAULT);
72
+ s->ptimer = ptimer_init(timer_hit, s, PTIMER_POLICY_DEFAULT);
73
74
+ ptimer_transaction_begin(s->ptimer);
75
ptimer_set_freq(s->ptimer, s->freq_hz);
76
+ ptimer_transaction_commit(s->ptimer);
77
}
78
79
static const VMStateDescription vmstate_lm32_timer = {
80
--
81
2.20.1
82
83
diff view generated by jsdifflib
[PULL 08/41] hw/timer/altera_timer.c: Switch to transaction-based ptimer API
Deleted patch
1
Switch the altera_timer code away from bottom-half based ptimers to
2
the new transaction-based ptimer API. This just requires adding
3
begin/commit calls around the various places that modify the ptimer
4
state, and using the new ptimer_init() function to create the timer.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20191017132905.5604-6-peter.maydell@linaro.org
10
---
11
hw/timer/altera_timer.c | 13 +++++++++----
12
1 file changed, 9 insertions(+), 4 deletions(-)
13
14
diff --git a/hw/timer/altera_timer.c b/hw/timer/altera_timer.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/timer/altera_timer.c
17
+++ b/hw/timer/altera_timer.c
18
@@ -XXX,XX +XXX,XX @@
19
*/
20
21
#include "qemu/osdep.h"
22
-#include "qemu/main-loop.h"
23
#include "qemu/module.h"
24
#include "qapi/error.h"
25
26
@@ -XXX,XX +XXX,XX @@ typedef struct AlteraTimer {
27
MemoryRegion mmio;
28
qemu_irq irq;
29
uint32_t freq_hz;
30
- QEMUBH *bh;
31
ptimer_state *ptimer;
32
uint32_t regs[R_MAX];
33
} AlteraTimer;
34
@@ -XXX,XX +XXX,XX @@ static void timer_write(void *opaque, hwaddr addr,
35
break;
36
37
case R_CONTROL:
38
+ ptimer_transaction_begin(t->ptimer);
39
t->regs[R_CONTROL] = value & (CONTROL_ITO | CONTROL_CONT);
40
if ((value & CONTROL_START) &&
41
!(t->regs[R_STATUS] & STATUS_RUN)) {
42
@@ -XXX,XX +XXX,XX @@ static void timer_write(void *opaque, hwaddr addr,
43
ptimer_stop(t->ptimer);
44
t->regs[R_STATUS] &= ~STATUS_RUN;
45
}
46
+ ptimer_transaction_commit(t->ptimer);
47
break;
48
49
case R_PERIODL:
50
case R_PERIODH:
51
+ ptimer_transaction_begin(t->ptimer);
52
t->regs[addr] = value & 0xFFFF;
53
if (t->regs[R_STATUS] & STATUS_RUN) {
54
ptimer_stop(t->ptimer);
55
@@ -XXX,XX +XXX,XX @@ static void timer_write(void *opaque, hwaddr addr,
56
}
57
tvalue = (t->regs[R_PERIODH] << 16) | t->regs[R_PERIODL];
58
ptimer_set_limit(t->ptimer, tvalue + 1, 1);
59
+ ptimer_transaction_commit(t->ptimer);
60
break;
61
62
case R_SNAPL:
63
@@ -XXX,XX +XXX,XX @@ static void altera_timer_realize(DeviceState *dev, Error **errp)
64
return;
65
}
66
67
- t->bh = qemu_bh_new(timer_hit, t);
68
- t->ptimer = ptimer_init_with_bh(t->bh, PTIMER_POLICY_DEFAULT);
69
+ t->ptimer = ptimer_init(timer_hit, t, PTIMER_POLICY_DEFAULT);
70
+ ptimer_transaction_begin(t->ptimer);
71
ptimer_set_freq(t->ptimer, t->freq_hz);
72
+ ptimer_transaction_commit(t->ptimer);
73
74
memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
75
TYPE_ALTERA_TIMER, R_MAX * sizeof(uint32_t));
76
@@ -XXX,XX +XXX,XX @@ static void altera_timer_reset(DeviceState *dev)
77
{
78
AlteraTimer *t = ALTERA_TIMER(dev);
79
80
+ ptimer_transaction_begin(t->ptimer);
81
ptimer_stop(t->ptimer);
82
ptimer_set_limit(t->ptimer, 0xffffffff, 1);
83
+ ptimer_transaction_commit(t->ptimer);
84
memset(t->regs, 0, sizeof(t->regs));
85
}
86
87
--
88
2.20.1
89
90
diff view generated by jsdifflib
[PULL 09/41] hw/watchdog/etraxfs_timer.c: Switch to transaction-based ptimer API
Deleted patch
1
Switch the etraxfs_timer code away from bottom-half based ptimers to
2
the new transaction-based ptimer API. This just requires adding
3
begin/commit calls around the various places that modify the ptimer
4
state, and using the new ptimer_init() function to create the timer.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20191017132905.5604-7-peter.maydell@linaro.org
10
---
11
hw/timer/etraxfs_timer.c | 23 +++++++++++++----------
12
1 file changed, 13 insertions(+), 10 deletions(-)
13
14
diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/timer/etraxfs_timer.c
17
+++ b/hw/timer/etraxfs_timer.c
18
@@ -XXX,XX +XXX,XX @@
19
#include "hw/sysbus.h"
20
#include "sysemu/reset.h"
21
#include "sysemu/runstate.h"
22
-#include "qemu/main-loop.h"
23
#include "qemu/module.h"
24
#include "qemu/timer.h"
25
#include "hw/irq.h"
26
@@ -XXX,XX +XXX,XX @@ typedef struct ETRAXTimerState {
27
qemu_irq irq;
28
qemu_irq nmi;
29
30
- QEMUBH *bh_t0;
31
- QEMUBH *bh_t1;
32
- QEMUBH *bh_wd;
33
ptimer_state *ptimer_t0;
34
ptimer_state *ptimer_t1;
35
ptimer_state *ptimer_wd;
36
@@ -XXX,XX +XXX,XX @@ static void update_ctrl(ETRAXTimerState *t, int tnum)
37
}
38
39
D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
40
+ ptimer_transaction_begin(timer);
41
ptimer_set_freq(timer, freq_hz);
42
ptimer_set_limit(timer, div, 0);
43
44
@@ -XXX,XX +XXX,XX @@ static void update_ctrl(ETRAXTimerState *t, int tnum)
45
abort();
46
break;
47
}
48
+ ptimer_transaction_commit(timer);
49
}
50
51
static void timer_update_irq(ETRAXTimerState *t)
52
@@ -XXX,XX +XXX,XX @@ static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value)
53
54
t->wd_hits = 0;
55
56
+ ptimer_transaction_begin(t->ptimer_wd);
57
ptimer_set_freq(t->ptimer_wd, 760);
58
if (wd_cnt == 0)
59
wd_cnt = 256;
60
@@ -XXX,XX +XXX,XX @@ static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value)
61
ptimer_stop(t->ptimer_wd);
62
63
t->rw_wd_ctrl = value;
64
+ ptimer_transaction_commit(t->ptimer_wd);
65
}
66
67
static void
68
@@ -XXX,XX +XXX,XX @@ static void etraxfs_timer_reset(void *opaque)
69
{
70
ETRAXTimerState *t = opaque;
71
72
+ ptimer_transaction_begin(t->ptimer_t0);
73
ptimer_stop(t->ptimer_t0);
74
+ ptimer_transaction_commit(t->ptimer_t0);
75
+ ptimer_transaction_begin(t->ptimer_t1);
76
ptimer_stop(t->ptimer_t1);
77
+ ptimer_transaction_commit(t->ptimer_t1);
78
+ ptimer_transaction_begin(t->ptimer_wd);
79
ptimer_stop(t->ptimer_wd);
80
+ ptimer_transaction_commit(t->ptimer_wd);
81
t->rw_wd_ctrl = 0;
82
t->r_intr = 0;
83
t->rw_intr_mask = 0;
84
@@ -XXX,XX +XXX,XX @@ static void etraxfs_timer_realize(DeviceState *dev, Error **errp)
85
ETRAXTimerState *t = ETRAX_TIMER(dev);
86
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
87
88
- t->bh_t0 = qemu_bh_new(timer0_hit, t);
89
- t->bh_t1 = qemu_bh_new(timer1_hit, t);
90
- t->bh_wd = qemu_bh_new(watchdog_hit, t);
91
- t->ptimer_t0 = ptimer_init_with_bh(t->bh_t0, PTIMER_POLICY_DEFAULT);
92
- t->ptimer_t1 = ptimer_init_with_bh(t->bh_t1, PTIMER_POLICY_DEFAULT);
93
- t->ptimer_wd = ptimer_init_with_bh(t->bh_wd, PTIMER_POLICY_DEFAULT);
94
+ t->ptimer_t0 = ptimer_init(timer0_hit, t, PTIMER_POLICY_DEFAULT);
95
+ t->ptimer_t1 = ptimer_init(timer1_hit, t, PTIMER_POLICY_DEFAULT);
96
+ t->ptimer_wd = ptimer_init(watchdog_hit, t, PTIMER_POLICY_DEFAULT);
97
98
sysbus_init_irq(sbd, &t->irq);
99
sysbus_init_irq(sbd, &t->nmi);
100
--
101
2.20.1
102
103
diff view generated by jsdifflib
[PULL 10/41] hw/m68k/mcf5208.c: Switch to transaction-based ptimer API
Deleted patch
1
Switch the mcf5208 code away from bottom-half based ptimers to
2
the new transaction-based ptimer API. This just requires adding
3
begin/commit calls around the various places that modify the ptimer
4
state, and using the new ptimer_init() function to create the timer.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Tested-by: Thomas Huth <huth@tuxfamily.org>
10
Message-id: 20191017132905.5604-9-peter.maydell@linaro.org
11
---
12
hw/m68k/mcf5208.c | 9 +++++----
13
1 file changed, 5 insertions(+), 4 deletions(-)
14
15
diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/m68k/mcf5208.c
18
+++ b/hw/m68k/mcf5208.c
19
@@ -XXX,XX +XXX,XX @@
20
#include "qemu/osdep.h"
21
#include "qemu/units.h"
22
#include "qemu/error-report.h"
23
-#include "qemu/main-loop.h"
24
#include "qapi/error.h"
25
#include "qemu-common.h"
26
#include "cpu.h"
27
@@ -XXX,XX +XXX,XX @@ static void m5208_timer_write(void *opaque, hwaddr offset,
28
return;
29
}
30
31
+ ptimer_transaction_begin(s->timer);
32
if (s->pcsr & PCSR_EN)
33
ptimer_stop(s->timer);
34
35
@@ -XXX,XX +XXX,XX @@ static void m5208_timer_write(void *opaque, hwaddr offset,
36
37
if (s->pcsr & PCSR_EN)
38
ptimer_run(s->timer, 0);
39
+ ptimer_transaction_commit(s->timer);
40
break;
41
case 2:
42
+ ptimer_transaction_begin(s->timer);
43
s->pmr = value;
44
s->pcsr &= ~PCSR_PIF;
45
if ((s->pcsr & PCSR_RLD) == 0) {
46
@@ -XXX,XX +XXX,XX @@ static void m5208_timer_write(void *opaque, hwaddr offset,
47
} else {
48
ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW);
49
}
50
+ ptimer_transaction_commit(s->timer);
51
break;
52
case 4:
53
break;
54
@@ -XXX,XX +XXX,XX @@ static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic)
55
{
56
MemoryRegion *iomem = g_new(MemoryRegion, 1);
57
m5208_timer_state *s;
58
- QEMUBH *bh;
59
int i;
60
61
/* SDRAMC. */
62
@@ -XXX,XX +XXX,XX @@ static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic)
63
/* Timers. */
64
for (i = 0; i < 2; i++) {
65
s = g_new0(m5208_timer_state, 1);
66
- bh = qemu_bh_new(m5208_timer_trigger, s);
67
- s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT);
68
+ s->timer = ptimer_init(m5208_timer_trigger, s, PTIMER_POLICY_DEFAULT);
69
memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s,
70
"m5208-timer", 0x00004000);
71
memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i,
72
--
73
2.20.1
74
75
diff view generated by jsdifflib
[PULL 11/41] target/arm: Split out rebuild_hflags_common
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Create a function to compute the values of the TBFLAG_ANY bits
4
that will be cached. For now, the env->hflags variable is not
5
used, and the results are fed back to cpu_get_tb_cpu_state.
6
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20191018174431.1784-2-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/cpu.h | 29 ++++++++++++++++++-----------
13
target/arm/helper.c | 26 +++++++++++++++++++-------
14
2 files changed, 37 insertions(+), 18 deletions(-)
15
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
21
uint32_t pstate;
22
uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
23
24
+ /* Cached TBFLAGS state. See below for which bits are included. */
25
+ uint32_t hflags;
26
+
27
/* Frequently accessed CPSR bits are stored separately for efficiency.
28
This contains all the other bits. Use cpsr_{read,write} to access
29
the whole CPSR. */
30
@@ -XXX,XX +XXX,XX @@ typedef ARMCPU ArchCPU;
31
32
#include "exec/cpu-all.h"
33
34
-/* Bit usage in the TB flags field: bit 31 indicates whether we are
35
+/*
36
+ * Bit usage in the TB flags field: bit 31 indicates whether we are
37
* in 32 or 64 bit mode. The meaning of the other bits depends on that.
38
* We put flags which are shared between 32 and 64 bit mode at the top
39
* of the word, and flags which apply to only one mode at the bottom.
40
+ *
41
+ * Unless otherwise noted, these bits are cached in env->hflags.
42
*/
43
FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
44
FIELD(TBFLAG_ANY, MMUIDX, 28, 3)
45
FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1)
46
-FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1)
47
+FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cached. */
48
/* Target EL if we take a floating-point-disabled exception */
49
FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2)
50
FIELD(TBFLAG_ANY, BE_DATA, 23, 1)
51
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, BE_DATA, 23, 1)
52
FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2)
53
54
/* Bit usage when in AArch32 state: */
55
-FIELD(TBFLAG_A32, THUMB, 0, 1)
56
-FIELD(TBFLAG_A32, VECLEN, 1, 3)
57
-FIELD(TBFLAG_A32, VECSTRIDE, 4, 2)
58
+FIELD(TBFLAG_A32, THUMB, 0, 1) /* Not cached. */
59
+FIELD(TBFLAG_A32, VECLEN, 1, 3) /* Not cached. */
60
+FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) /* Not cached. */
61
/*
62
* We store the bottom two bits of the CPAR as TB flags and handle
63
* checks on the other bits at runtime. This shares the same bits as
64
* VECSTRIDE, which is OK as no XScale CPU has VFP.
65
+ * Not cached, because VECLEN+VECSTRIDE are not cached.
66
*/
67
FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2)
68
/*
69
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2)
70
* the same thing as the current security state of the processor!
71
*/
72
FIELD(TBFLAG_A32, NS, 6, 1)
73
-FIELD(TBFLAG_A32, VFPEN, 7, 1)
74
-FIELD(TBFLAG_A32, CONDEXEC, 8, 8)
75
+FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Not cached. */
76
+FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */
77
FIELD(TBFLAG_A32, SCTLR_B, 16, 1)
78
/* For M profile only, set if FPCCR.LSPACT is set */
79
-FIELD(TBFLAG_A32, LSPACT, 18, 1)
80
+FIELD(TBFLAG_A32, LSPACT, 18, 1) /* Not cached. */
81
/* For M profile only, set if we must create a new FP context */
82
-FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1)
83
+FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) /* Not cached. */
84
/* For M profile only, set if FPCCR.S does not match current security state */
85
-FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1)
86
+FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) /* Not cached. */
87
/* For M profile only, Handler (ie not Thread) mode */
88
FIELD(TBFLAG_A32, HANDLER, 21, 1)
89
/* For M profile only, whether we should generate stack-limit checks */
90
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
91
FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
92
FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
93
FIELD(TBFLAG_A64, BT, 9, 1)
94
-FIELD(TBFLAG_A64, BTYPE, 10, 2)
95
+FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */
96
FIELD(TBFLAG_A64, TBID, 12, 2)
97
98
static inline bool bswap_code(bool sctlr_b)
99
diff --git a/target/arm/helper.c b/target/arm/helper.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/target/arm/helper.c
102
+++ b/target/arm/helper.c
103
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
104
}
105
#endif
106
107
+static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el,
108
+ ARMMMUIdx mmu_idx, uint32_t flags)
109
+{
110
+ flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el);
111
+ flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX,
112
+ arm_to_core_mmu_idx(mmu_idx));
113
+
114
+ if (arm_cpu_data_is_big_endian(env)) {
115
+ flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1);
116
+ }
117
+ if (arm_singlestep_active(env)) {
118
+ flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1);
119
+ }
120
+ return flags;
121
+}
122
+
123
void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
124
target_ulong *cs_base, uint32_t *pflags)
125
{
126
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
127
}
128
}
129
130
- flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx));
131
+ flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags);
132
133
/* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
134
* states defined in the ARM ARM for software singlestep:
135
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
136
* 0 x Inactive (the TB flag for SS is always 0)
137
* 1 0 Active-pending
138
* 1 1 Active-not-pending
139
+ * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB.
140
*/
141
- if (arm_singlestep_active(env)) {
142
- flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1);
143
+ if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE)) {
144
if (is_a64(env)) {
145
if (env->pstate & PSTATE_SS) {
146
flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1);
147
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
148
}
149
}
150
}
151
- if (arm_cpu_data_is_big_endian(env)) {
152
- flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1);
153
- }
154
- flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el);
155
156
if (arm_v7m_is_handler_mode(env)) {
157
flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1);
158
--
159
2.20.1
160
161
diff view generated by jsdifflib
[PULL 12/41] target/arm: Split out rebuild_hflags_a64
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Create a function to compute the values of the TBFLAG_A64 bits
4
that will be cached. For now, the env->hflags variable is not
5
used, and the results are fed back to cpu_get_tb_cpu_state.
6
7
Note that not all BTI related flags are cached, so we have to
8
test the BTI feature twice -- once for those bits moved out to
9
rebuild_hflags_a64 and once for those bits that remain in
10
cpu_get_tb_cpu_state.
11
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20191018174431.1784-3-richard.henderson@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/helper.c | 131 +++++++++++++++++++++++---------------------
18
1 file changed, 69 insertions(+), 62 deletions(-)
19
20
diff --git a/target/arm/helper.c b/target/arm/helper.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper.c
23
+++ b/target/arm/helper.c
24
@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el,
25
return flags;
26
}
27
28
+static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
29
+ ARMMMUIdx mmu_idx)
30
+{
31
+ ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
32
+ ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1);
33
+ uint32_t flags = 0;
34
+ uint64_t sctlr;
35
+ int tbii, tbid;
36
+
37
+ flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
38
+
39
+ /* FIXME: ARMv8.1-VHE S2 translation regime. */
40
+ if (regime_el(env, stage1) < 2) {
41
+ ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1);
42
+ tbid = (p1.tbi << 1) | p0.tbi;
43
+ tbii = tbid & ~((p1.tbid << 1) | p0.tbid);
44
+ } else {
45
+ tbid = p0.tbi;
46
+ tbii = tbid & !p0.tbid;
47
+ }
48
+
49
+ flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii);
50
+ flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid);
51
+
52
+ if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
53
+ int sve_el = sve_exception_el(env, el);
54
+ uint32_t zcr_len;
55
+
56
+ /*
57
+ * If SVE is disabled, but FP is enabled,
58
+ * then the effective len is 0.
59
+ */
60
+ if (sve_el != 0 && fp_el == 0) {
61
+ zcr_len = 0;
62
+ } else {
63
+ zcr_len = sve_zcr_len_for_el(env, el);
64
+ }
65
+ flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el);
66
+ flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
67
+ }
68
+
69
+ sctlr = arm_sctlr(env, el);
70
+
71
+ if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) {
72
+ /*
73
+ * In order to save space in flags, we record only whether
74
+ * pauth is "inactive", meaning all insns are implemented as
75
+ * a nop, or "active" when some action must be performed.
76
+ * The decision of which action to take is left to a helper.
77
+ */
78
+ if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
79
+ flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1);
80
+ }
81
+ }
82
+
83
+ if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
84
+ /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
85
+ if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
86
+ flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1);
87
+ }
88
+ }
89
+
90
+ return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
91
+}
92
+
93
void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
94
target_ulong *cs_base, uint32_t *pflags)
95
{
96
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
97
uint32_t flags = 0;
98
99
if (is_a64(env)) {
100
- ARMCPU *cpu = env_archcpu(env);
101
- uint64_t sctlr;
102
-
103
*pc = env->pc;
104
- flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
105
-
106
- /* Get control bits for tagged addresses. */
107
- {
108
- ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
109
- ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1);
110
- int tbii, tbid;
111
-
112
- /* FIXME: ARMv8.1-VHE S2 translation regime. */
113
- if (regime_el(env, stage1) < 2) {
114
- ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1);
115
- tbid = (p1.tbi << 1) | p0.tbi;
116
- tbii = tbid & ~((p1.tbid << 1) | p0.tbid);
117
- } else {
118
- tbid = p0.tbi;
119
- tbii = tbid & !p0.tbid;
120
- }
121
-
122
- flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii);
123
- flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid);
124
- }
125
-
126
- if (cpu_isar_feature(aa64_sve, cpu)) {
127
- int sve_el = sve_exception_el(env, current_el);
128
- uint32_t zcr_len;
129
-
130
- /* If SVE is disabled, but FP is enabled,
131
- * then the effective len is 0.
132
- */
133
- if (sve_el != 0 && fp_el == 0) {
134
- zcr_len = 0;
135
- } else {
136
- zcr_len = sve_zcr_len_for_el(env, current_el);
137
- }
138
- flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el);
139
- flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
140
- }
141
-
142
- sctlr = arm_sctlr(env, current_el);
143
-
144
- if (cpu_isar_feature(aa64_pauth, cpu)) {
145
- /*
146
- * In order to save space in flags, we record only whether
147
- * pauth is "inactive", meaning all insns are implemented as
148
- * a nop, or "active" when some action must be performed.
149
- * The decision of which action to take is left to a helper.
150
- */
151
- if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
152
- flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1);
153
- }
154
- }
155
-
156
- if (cpu_isar_feature(aa64_bti, cpu)) {
157
- /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
158
- if (sctlr & (current_el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
159
- flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1);
160
- }
161
+ flags = rebuild_hflags_a64(env, current_el, fp_el, mmu_idx);
162
+ if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
163
flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);
164
}
165
} else {
166
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
167
flags = FIELD_DP32(flags, TBFLAG_A32,
168
XSCALE_CPAR, env->cp15.c15_cpar);
169
}
170
- }
171
172
- flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags);
173
+ flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags);
174
+ }
175
176
/* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
177
* states defined in the ARM ARM for software singlestep:
178
--
179
2.20.1
180
181
diff view generated by jsdifflib
[PULL 13/41] target/arm: Split out rebuild_hflags_common_32
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Create a function to compute the values of the TBFLAG_A32 bits
4
that will be cached, and are used by all profiles.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20191018174431.1784-4-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/helper.c | 16 +++++++++++-----
12
1 file changed, 11 insertions(+), 5 deletions(-)
13
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
17
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el,
19
return flags;
20
}
21
22
+static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el,
23
+ ARMMMUIdx mmu_idx, uint32_t flags)
24
+{
25
+ flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env));
26
+ flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env));
27
+
28
+ return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
29
+}
30
+
31
static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
32
ARMMMUIdx mmu_idx)
33
{
34
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
35
ARMMMUIdx mmu_idx = arm_mmu_idx(env);
36
int current_el = arm_current_el(env);
37
int fp_el = fp_exception_el(env, current_el);
38
- uint32_t flags = 0;
39
+ uint32_t flags;
40
41
if (is_a64(env)) {
42
*pc = env->pc;
43
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
44
}
45
} else {
46
*pc = env->regs[15];
47
+ flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0);
48
flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb);
49
flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len);
50
flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride);
51
flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits);
52
- flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env));
53
- flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env));
54
if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
55
|| arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) {
56
flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
57
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
58
flags = FIELD_DP32(flags, TBFLAG_A32,
59
XSCALE_CPAR, env->cp15.c15_cpar);
60
}
61
-
62
- flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags);
63
}
64
65
/* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
66
--
67
2.20.1
68
69
diff view generated by jsdifflib
[PULL 14/41] target/arm: Split arm_cpu_data_is_big_endian
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Set TBFLAG_ANY.BE_DATA in rebuild_hflags_common_32 and
4
rebuild_hflags_a64 instead of rebuild_hflags_common, where we do
5
not need to re-test is_a64() nor re-compute the various inputs.
6
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20191018174431.1784-5-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/cpu.h | 49 +++++++++++++++++++++++++++------------------
13
target/arm/helper.c | 16 +++++++++++----
14
2 files changed, 42 insertions(+), 23 deletions(-)
15
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ static inline uint64_t arm_sctlr(CPUARMState *env, int el)
21
}
22
}
23
24
+static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
25
+ bool sctlr_b)
26
+{
27
+#ifdef CONFIG_USER_ONLY
28
+ /*
29
+ * In system mode, BE32 is modelled in line with the
30
+ * architecture (as word-invariant big-endianness), where loads
31
+ * and stores are done little endian but from addresses which
32
+ * are adjusted by XORing with the appropriate constant. So the
33
+ * endianness to use for the raw data access is not affected by
34
+ * SCTLR.B.
35
+ * In user mode, however, we model BE32 as byte-invariant
36
+ * big-endianness (because user-only code cannot tell the
37
+ * difference), and so we need to use a data access endianness
38
+ * that depends on SCTLR.B.
39
+ */
40
+ if (sctlr_b) {
41
+ return true;
42
+ }
43
+#endif
44
+ /* In 32bit endianness is determined by looking at CPSR's E bit */
45
+ return env->uncached_cpsr & CPSR_E;
46
+}
47
+
48
+static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
49
+{
50
+ return sctlr & (el ? SCTLR_EE : SCTLR_E0E);
51
+}
52
53
/* Return true if the processor is in big-endian mode. */
54
static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
55
{
56
- /* In 32bit endianness is determined by looking at CPSR's E bit */
57
if (!is_a64(env)) {
58
- return
59
-#ifdef CONFIG_USER_ONLY
60
- /* In system mode, BE32 is modelled in line with the
61
- * architecture (as word-invariant big-endianness), where loads
62
- * and stores are done little endian but from addresses which
63
- * are adjusted by XORing with the appropriate constant. So the
64
- * endianness to use for the raw data access is not affected by
65
- * SCTLR.B.
66
- * In user mode, however, we model BE32 as byte-invariant
67
- * big-endianness (because user-only code cannot tell the
68
- * difference), and so we need to use a data access endianness
69
- * that depends on SCTLR.B.
70
- */
71
- arm_sctlr_b(env) ||
72
-#endif
73
- ((env->uncached_cpsr & CPSR_E) ? 1 : 0);
74
+ return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
75
} else {
76
int cur_el = arm_current_el(env);
77
uint64_t sctlr = arm_sctlr(env, cur_el);
78
-
79
- return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0;
80
+ return arm_cpu_data_is_big_endian_a64(cur_el, sctlr);
81
}
82
}
83
84
diff --git a/target/arm/helper.c b/target/arm/helper.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/target/arm/helper.c
87
+++ b/target/arm/helper.c
88
@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el,
89
flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX,
90
arm_to_core_mmu_idx(mmu_idx));
91
92
- if (arm_cpu_data_is_big_endian(env)) {
93
- flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1);
94
- }
95
if (arm_singlestep_active(env)) {
96
flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1);
97
}
98
@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el,
99
static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el,
100
ARMMMUIdx mmu_idx, uint32_t flags)
101
{
102
- flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env));
103
+ bool sctlr_b = arm_sctlr_b(env);
104
+
105
+ if (sctlr_b) {
106
+ flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, 1);
107
+ }
108
+ if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) {
109
+ flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1);
110
+ }
111
flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env));
112
113
return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
114
@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
115
116
sctlr = arm_sctlr(env, el);
117
118
+ if (arm_cpu_data_is_big_endian_a64(el, sctlr)) {
119
+ flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1);
120
+ }
121
+
122
if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) {
123
/*
124
* In order to save space in flags, we record only whether
125
--
126
2.20.1
127
128
diff view generated by jsdifflib
[PULL 15/41] target/arm: Split out rebuild_hflags_m32
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Create a function to compute the values of the TBFLAG_A32 bits
4
that will be cached, and are used by M-profile.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20191018174431.1784-6-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/helper.c | 45 ++++++++++++++++++++++++++++++---------------
12
1 file changed, 30 insertions(+), 15 deletions(-)
13
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
17
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el,
19
return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
20
}
21
22
+static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el,
23
+ ARMMMUIdx mmu_idx)
24
+{
25
+ uint32_t flags = 0;
26
+
27
+ if (arm_v7m_is_handler_mode(env)) {
28
+ flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1);
29
+ }
30
+
31
+ /*
32
+ * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
33
+ * is suppressing them because the requested execution priority
34
+ * is less than 0.
35
+ */
36
+ if (arm_feature(env, ARM_FEATURE_V8) &&
37
+ !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
38
+ (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
39
+ flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1);
40
+ }
41
+
42
+ return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
43
+}
44
+
45
static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
46
ARMMMUIdx mmu_idx)
47
{
48
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
49
}
50
} else {
51
*pc = env->regs[15];
52
- flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0);
53
+
54
+ if (arm_feature(env, ARM_FEATURE_M)) {
55
+ flags = rebuild_hflags_m32(env, fp_el, mmu_idx);
56
+ } else {
57
+ flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0);
58
+ }
59
+
60
flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb);
61
flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len);
62
flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride);
63
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
64
}
65
}
66
67
- if (arm_v7m_is_handler_mode(env)) {
68
- flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1);
69
- }
70
-
71
- /* v8M always applies stack limit checks unless CCR.STKOFHFNMIGN is
72
- * suppressing them because the requested execution priority is less than 0.
73
- */
74
- if (arm_feature(env, ARM_FEATURE_V8) &&
75
- arm_feature(env, ARM_FEATURE_M) &&
76
- !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
77
- (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
78
- flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1);
79
- }
80
-
81
if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
82
FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) {
83
flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1);
84
--
85
2.20.1
86
87
diff view generated by jsdifflib
[PULL 16/41] target/arm: Reduce tests vs M-profile in cpu_get_tb_cpu_state
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Hoist the computation of some TBFLAG_A32 bits that only apply to
4
M-profile under a single test for ARM_FEATURE_M.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20191018174431.1784-7-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/helper.c | 49 +++++++++++++++++++++------------------------
12
1 file changed, 23 insertions(+), 26 deletions(-)
13
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
17
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
19
20
if (arm_feature(env, ARM_FEATURE_M)) {
21
flags = rebuild_hflags_m32(env, fp_el, mmu_idx);
22
+
23
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
24
+ FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S)
25
+ != env->v7m.secure) {
26
+ flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1);
27
+ }
28
+
29
+ if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) &&
30
+ (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) ||
31
+ (env->v7m.secure &&
32
+ !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) {
33
+ /*
34
+ * ASPEN is set, but FPCA/SFPA indicate that there is no
35
+ * active FP context; we must create a new FP context before
36
+ * executing any FP insn.
37
+ */
38
+ flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1);
39
+ }
40
+
41
+ bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK;
42
+ if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) {
43
+ flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1);
44
+ }
45
} else {
46
flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0);
47
}
48
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
49
}
50
}
51
52
- if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
53
- FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) {
54
- flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1);
55
- }
56
-
57
- if (arm_feature(env, ARM_FEATURE_M) &&
58
- (env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) &&
59
- (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) ||
60
- (env->v7m.secure &&
61
- !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) {
62
- /*
63
- * ASPEN is set, but FPCA/SFPA indicate that there is no active
64
- * FP context; we must create a new FP context before executing
65
- * any FP insn.
66
- */
67
- flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1);
68
- }
69
-
70
- if (arm_feature(env, ARM_FEATURE_M)) {
71
- bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK;
72
-
73
- if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) {
74
- flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1);
75
- }
76
- }
77
-
78
if (!arm_feature(env, ARM_FEATURE_M)) {
79
int target_el = arm_debug_target_el(env);
80
81
--
82
2.20.1
83
84
diff view generated by jsdifflib
[PULL 17/41] target/arm: Split out rebuild_hflags_a32
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Currently a trivial wrapper for rebuild_hflags_common_32.
4
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20191018174431.1784-8-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/helper.c | 8 +++++++-
11
1 file changed, 7 insertions(+), 1 deletion(-)
12
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
16
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el,
18
return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
19
}
20
21
+static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el,
22
+ ARMMMUIdx mmu_idx)
23
+{
24
+ return rebuild_hflags_common_32(env, fp_el, mmu_idx, 0);
25
+}
26
+
27
static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
28
ARMMMUIdx mmu_idx)
29
{
30
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
31
flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1);
32
}
33
} else {
34
- flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0);
35
+ flags = rebuild_hflags_a32(env, fp_el, mmu_idx);
36
}
37
38
flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb);
39
--
40
2.20.1
41
42
diff view generated by jsdifflib
[PULL 18/41] target/arm: Split out rebuild_hflags_aprofile
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Create a function to compute the values of the TBFLAG_ANY bits
4
that will be cached, and are used by A-profile.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20191018174431.1784-9-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/helper.c | 20 ++++++++++++--------
12
1 file changed, 12 insertions(+), 8 deletions(-)
13
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
17
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el,
19
return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
20
}
21
22
+static uint32_t rebuild_hflags_aprofile(CPUARMState *env)
23
+{
24
+ int flags = 0;
25
+
26
+ flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL,
27
+ arm_debug_target_el(env));
28
+ return flags;
29
+}
30
+
31
static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el,
32
ARMMMUIdx mmu_idx)
33
{
34
- return rebuild_hflags_common_32(env, fp_el, mmu_idx, 0);
35
+ uint32_t flags = rebuild_hflags_aprofile(env);
36
+ return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
37
}
38
39
static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
40
ARMMMUIdx mmu_idx)
41
{
42
+ uint32_t flags = rebuild_hflags_aprofile(env);
43
ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
44
ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1);
45
- uint32_t flags = 0;
46
uint64_t sctlr;
47
int tbii, tbid;
48
49
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
50
}
51
}
52
53
- if (!arm_feature(env, ARM_FEATURE_M)) {
54
- int target_el = arm_debug_target_el(env);
55
-
56
- flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, target_el);
57
- }
58
-
59
*pflags = flags;
60
*cs_base = 0;
61
}
62
--
63
2.20.1
64
65
diff view generated by jsdifflib
[PULL 19/41] target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
We do not need to compute any of these values for M-profile.
4
Further, XSCALE_CPAR overlaps VECSTRIDE so obviously the two
5
sets must be mutually exclusive.
6
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20191018174431.1784-10-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/helper.c | 21 ++++++++++++++-------
13
1 file changed, 14 insertions(+), 7 deletions(-)
14
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.c
18
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
20
}
21
} else {
22
flags = rebuild_hflags_a32(env, fp_el, mmu_idx);
23
+
24
+ /*
25
+ * Note that XSCALE_CPAR shares bits with VECSTRIDE.
26
+ * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
27
+ */
28
+ if (arm_feature(env, ARM_FEATURE_XSCALE)) {
29
+ flags = FIELD_DP32(flags, TBFLAG_A32,
30
+ XSCALE_CPAR, env->cp15.c15_cpar);
31
+ } else {
32
+ flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN,
33
+ env->vfp.vec_len);
34
+ flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE,
35
+ env->vfp.vec_stride);
36
+ }
37
}
38
39
flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb);
40
- flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len);
41
- flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride);
42
flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits);
43
if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
44
|| arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) {
45
flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
46
}
47
- /* Note that XSCALE_CPAR shares bits with VECSTRIDE */
48
- if (arm_feature(env, ARM_FEATURE_XSCALE)) {
49
- flags = FIELD_DP32(flags, TBFLAG_A32,
50
- XSCALE_CPAR, env->cp15.c15_cpar);
51
- }
52
}
53
54
/* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
55
--
56
2.20.1
57
58
diff view generated by jsdifflib
[PULL 20/41] target/arm: Simplify set of PSTATE_SS in cpu_get_tb_cpu_state
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Hoist the variable load for PSTATE into the existing test vs is_a64.
4
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20191018174431.1784-11-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/helper.c | 20 ++++++++------------
11
1 file changed, 8 insertions(+), 12 deletions(-)
12
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
16
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
18
ARMMMUIdx mmu_idx = arm_mmu_idx(env);
19
int current_el = arm_current_el(env);
20
int fp_el = fp_exception_el(env, current_el);
21
- uint32_t flags;
22
+ uint32_t flags, pstate_for_ss;
23
24
if (is_a64(env)) {
25
*pc = env->pc;
26
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
27
if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
28
flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);
29
}
30
+ pstate_for_ss = env->pstate;
31
} else {
32
*pc = env->regs[15];
33
34
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
35
|| arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) {
36
flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
37
}
38
+ pstate_for_ss = env->uncached_cpsr;
39
}
40
41
- /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
42
+ /*
43
+ * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
44
* states defined in the ARM ARM for software singlestep:
45
* SS_ACTIVE PSTATE.SS State
46
* 0 x Inactive (the TB flag for SS is always 0)
47
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
48
* 1 1 Active-not-pending
49
* SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB.
50
*/
51
- if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE)) {
52
- if (is_a64(env)) {
53
- if (env->pstate & PSTATE_SS) {
54
- flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1);
55
- }
56
- } else {
57
- if (env->uncached_cpsr & PSTATE_SS) {
58
- flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1);
59
- }
60
- }
61
+ if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) &&
62
+ (pstate_for_ss & PSTATE_SS)) {
63
+ flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1);
64
}
65
66
*pflags = flags;
67
--
68
2.20.1
69
70
diff view generated by jsdifflib
[PULL 21/41] target/arm: Hoist computation of TBFLAG_A32.VFPEN
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
There are 3 conditions that each enable this flag. M-profile always
4
enables; A-profile with EL1 as AA64 always enables. Both of these
5
conditions can easily be cached. The final condition relies on the
6
FPEXC register which we are not prepared to cache.
7
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20191018174431.1784-12-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/cpu.h | 2 +-
14
target/arm/helper.c | 14 ++++++++++----
15
2 files changed, 11 insertions(+), 5 deletions(-)
16
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2)
22
* the same thing as the current security state of the processor!
23
*/
24
FIELD(TBFLAG_A32, NS, 6, 1)
25
-FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Not cached. */
26
+FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */
27
FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */
28
FIELD(TBFLAG_A32, SCTLR_B, 16, 1)
29
/* For M profile only, set if FPCCR.LSPACT is set */
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/helper.c
33
+++ b/target/arm/helper.c
34
@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el,
35
{
36
uint32_t flags = 0;
37
38
+ /* v8M always enables the fpu. */
39
+ flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
40
+
41
if (arm_v7m_is_handler_mode(env)) {
42
flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1);
43
}
44
@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el,
45
ARMMMUIdx mmu_idx)
46
{
47
uint32_t flags = rebuild_hflags_aprofile(env);
48
+
49
+ if (arm_el_is_aa64(env, 1)) {
50
+ flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
51
+ }
52
return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
53
}
54
55
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
56
flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE,
57
env->vfp.vec_stride);
58
}
59
+ if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
60
+ flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
61
+ }
62
}
63
64
flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb);
65
flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits);
66
- if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
67
- || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) {
68
- flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
69
- }
70
pstate_for_ss = env->uncached_cpsr;
71
}
72
73
--
74
2.20.1
75
76
diff view generated by jsdifflib
[PULL 22/41] target/arm: Add arm_rebuild_hflags
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
This function assumes nothing about the current state of the cpu,
4
and writes the computed value to env->hflags.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20191018174431.1784-13-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/cpu.h | 6 ++++++
12
target/arm/helper.c | 30 ++++++++++++++++++++++--------
13
2 files changed, 28 insertions(+), 8 deletions(-)
14
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.h
18
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
20
void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
21
*opaque);
22
23
+/**
24
+ * arm_rebuild_hflags:
25
+ * Rebuild the cached TBFLAGS for arbitrary changed processor state.
26
+ */
27
+void arm_rebuild_hflags(CPUARMState *env);
28
+
29
/**
30
* aa32_vfp_dreg:
31
* Return a pointer to the Dn register within env in 32-bit mode.
32
diff --git a/target/arm/helper.c b/target/arm/helper.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/helper.c
35
+++ b/target/arm/helper.c
36
@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
37
return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
38
}
39
40
+static uint32_t rebuild_hflags_internal(CPUARMState *env)
41
+{
42
+ int el = arm_current_el(env);
43
+ int fp_el = fp_exception_el(env, el);
44
+ ARMMMUIdx mmu_idx = arm_mmu_idx(env);
45
+
46
+ if (is_a64(env)) {
47
+ return rebuild_hflags_a64(env, el, fp_el, mmu_idx);
48
+ } else if (arm_feature(env, ARM_FEATURE_M)) {
49
+ return rebuild_hflags_m32(env, fp_el, mmu_idx);
50
+ } else {
51
+ return rebuild_hflags_a32(env, fp_el, mmu_idx);
52
+ }
53
+}
54
+
55
+void arm_rebuild_hflags(CPUARMState *env)
56
+{
57
+ env->hflags = rebuild_hflags_internal(env);
58
+}
59
+
60
void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
61
target_ulong *cs_base, uint32_t *pflags)
62
{
63
- ARMMMUIdx mmu_idx = arm_mmu_idx(env);
64
- int current_el = arm_current_el(env);
65
- int fp_el = fp_exception_el(env, current_el);
66
uint32_t flags, pstate_for_ss;
67
68
+ flags = rebuild_hflags_internal(env);
69
+
70
if (is_a64(env)) {
71
*pc = env->pc;
72
- flags = rebuild_hflags_a64(env, current_el, fp_el, mmu_idx);
73
if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
74
flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);
75
}
76
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
77
*pc = env->regs[15];
78
79
if (arm_feature(env, ARM_FEATURE_M)) {
80
- flags = rebuild_hflags_m32(env, fp_el, mmu_idx);
81
-
82
if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
83
FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S)
84
!= env->v7m.secure) {
85
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
86
flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1);
87
}
88
} else {
89
- flags = rebuild_hflags_a32(env, fp_el, mmu_idx);
90
-
91
/*
92
* Note that XSCALE_CPAR shares bits with VECSTRIDE.
93
* Note that VECLEN+VECSTRIDE are RES0 for M-profile.
94
--
95
2.20.1
96
97
diff view generated by jsdifflib
[PULL 23/41] target/arm: Split out arm_mmu_idx_el
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Avoid calling arm_current_el() twice.
4
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20191018174431.1784-14-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/internals.h | 9 +++++++++
12
target/arm/helper.c | 12 +++++++-----
13
2 files changed, 16 insertions(+), 5 deletions(-)
14
15
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/internals.h
18
+++ b/target/arm/internals.h
19
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu);
20
*/
21
void arm_cpu_update_vfiq(ARMCPU *cpu);
22
23
+/**
24
+ * arm_mmu_idx_el:
25
+ * @env: The cpu environment
26
+ * @el: The EL to use.
27
+ *
28
+ * Return the full ARMMMUIdx for the translation regime for EL.
29
+ */
30
+ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el);
31
+
32
/**
33
* arm_mmu_idx:
34
* @env: The cpu environment
35
diff --git a/target/arm/helper.c b/target/arm/helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/helper.c
38
+++ b/target/arm/helper.c
39
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
40
}
41
#endif
42
43
-ARMMMUIdx arm_mmu_idx(CPUARMState *env)
44
+ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
45
{
46
- int el;
47
-
48
if (arm_feature(env, ARM_FEATURE_M)) {
49
return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
50
}
51
52
- el = arm_current_el(env);
53
if (el < 2 && arm_is_secure_below_el3(env)) {
54
return ARMMMUIdx_S1SE0 + el;
55
} else {
56
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env)
57
}
58
}
59
60
+ARMMMUIdx arm_mmu_idx(CPUARMState *env)
61
+{
62
+ return arm_mmu_idx_el(env, arm_current_el(env));
63
+}
64
+
65
int cpu_mmu_index(CPUARMState *env, bool ifetch)
66
{
67
return arm_to_core_mmu_idx(arm_mmu_idx(env));
68
@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_internal(CPUARMState *env)
69
{
70
int el = arm_current_el(env);
71
int fp_el = fp_exception_el(env, el);
72
- ARMMMUIdx mmu_idx = arm_mmu_idx(env);
73
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
74
75
if (is_a64(env)) {
76
return rebuild_hflags_a64(env, el, fp_el, mmu_idx);
77
--
78
2.20.1
79
80
diff view generated by jsdifflib
[PULL 24/41] target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
By performing this store early, we avoid having to save and restore
4
the register holding the address around any function calls.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20191018174431.1784-15-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/helper.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
17
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
19
{
20
uint32_t flags, pstate_for_ss;
21
22
+ *cs_base = 0;
23
flags = rebuild_hflags_internal(env);
24
25
if (is_a64(env)) {
26
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
27
}
28
29
*pflags = flags;
30
- *cs_base = 0;
31
}
32
33
#ifdef TARGET_AARCH64
34
--
35
2.20.1
36
37
diff view generated by jsdifflib
[PULL 25/41] target/arm: Add HELPER(rebuild_hflags_{a32, a64, m32})
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
This functions are given the mode and el state of the cpu
4
and writes the computed value to env->hflags.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20191018174431.1784-16-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/helper.h | 4 ++++
12
target/arm/helper.c | 24 ++++++++++++++++++++++++
13
2 files changed, 28 insertions(+)
14
15
diff --git a/target/arm/helper.h b/target/arm/helper.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.h
18
+++ b/target/arm/helper.h
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(msr_banked, void, env, i32, i32, i32)
20
DEF_HELPER_2(get_user_reg, i32, env, i32)
21
DEF_HELPER_3(set_user_reg, void, env, i32, i32)
22
23
+DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int)
24
+DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int)
25
+DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int)
26
+
27
DEF_HELPER_1(vfp_get_fpscr, i32, env)
28
DEF_HELPER_2(vfp_set_fpscr, void, env, i32)
29
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/helper.c
33
+++ b/target/arm/helper.c
34
@@ -XXX,XX +XXX,XX @@ void arm_rebuild_hflags(CPUARMState *env)
35
env->hflags = rebuild_hflags_internal(env);
36
}
37
38
+void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
39
+{
40
+ int fp_el = fp_exception_el(env, el);
41
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
42
+
43
+ env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
44
+}
45
+
46
+void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el)
47
+{
48
+ int fp_el = fp_exception_el(env, el);
49
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
50
+
51
+ env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
52
+}
53
+
54
+void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el)
55
+{
56
+ int fp_el = fp_exception_el(env, el);
57
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
58
+
59
+ env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx);
60
+}
61
+
62
void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
63
target_ulong *cs_base, uint32_t *pflags)
64
{
65
--
66
2.20.1
67
68
diff view generated by jsdifflib
[PULL 26/41] target/arm: Rebuild hflags at EL changes
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Begin setting, but not relying upon, env->hflags.
4
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20191018174431.1784-17-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
linux-user/syscall.c | 1 +
11
target/arm/cpu.c | 1 +
12
target/arm/helper-a64.c | 3 +++
13
target/arm/helper.c | 2 ++
14
target/arm/machine.c | 1 +
15
target/arm/op_helper.c | 1 +
16
6 files changed, 9 insertions(+)
17
18
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/linux-user/syscall.c
21
+++ b/linux-user/syscall.c
22
@@ -XXX,XX +XXX,XX @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
23
aarch64_sve_narrow_vq(env, vq);
24
}
25
env->vfp.zcr_el[1] = vq - 1;
26
+ arm_rebuild_hflags(env);
27
ret = vq * 16;
28
}
29
return ret;
30
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/cpu.c
33
+++ b/target/arm/cpu.c
34
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
35
36
hw_breakpoint_update_all(cpu);
37
hw_watchpoint_update_all(cpu);
38
+ arm_rebuild_hflags(env);
39
}
40
41
bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
42
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/helper-a64.c
45
+++ b/target/arm/helper-a64.c
46
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
47
} else {
48
env->regs[15] = new_pc & ~0x3;
49
}
50
+ helper_rebuild_hflags_a32(env, new_el);
51
qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to "
52
"AArch32 EL%d PC 0x%" PRIx32 "\n",
53
cur_el, new_el, env->regs[15]);
54
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
55
}
56
aarch64_restore_sp(env, new_el);
57
env->pc = new_pc;
58
+ helper_rebuild_hflags_a64(env, new_el);
59
qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to "
60
"AArch64 EL%d PC 0x%" PRIx64 "\n",
61
cur_el, new_el, env->pc);
62
}
63
+
64
/*
65
* Note that cur_el can never be 0. If new_el is 0, then
66
* el0_a64 is return_to_aa64, else el0_a64 is ignored.
67
diff --git a/target/arm/helper.c b/target/arm/helper.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/target/arm/helper.c
70
+++ b/target/arm/helper.c
71
@@ -XXX,XX +XXX,XX @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
72
env->regs[14] = env->regs[15] + offset;
73
}
74
env->regs[15] = newpc;
75
+ arm_rebuild_hflags(env);
76
}
77
78
static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
79
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
80
pstate_write(env, PSTATE_DAIF | new_mode);
81
env->aarch64 = 1;
82
aarch64_restore_sp(env, new_el);
83
+ helper_rebuild_hflags_a64(env, new_el);
84
85
env->pc = addr;
86
87
diff --git a/target/arm/machine.c b/target/arm/machine.c
88
index XXXXXXX..XXXXXXX 100644
89
--- a/target/arm/machine.c
90
+++ b/target/arm/machine.c
91
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
92
if (!kvm_enabled()) {
93
pmu_op_finish(&cpu->env);
94
}
95
+ arm_rebuild_hflags(&cpu->env);
96
97
return 0;
98
}
99
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/target/arm/op_helper.c
102
+++ b/target/arm/op_helper.c
103
@@ -XXX,XX +XXX,XX @@ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val)
104
* state. Do the masking now.
105
*/
106
env->regs[15] &= (env->thumb ? ~1 : ~3);
107
+ arm_rebuild_hflags(env);
108
109
qemu_mutex_lock_iothread();
110
arm_call_el_change_hook(env_archcpu(env));
111
--
112
2.20.1
113
114
diff view generated by jsdifflib
[PULL 27/41] target/arm: Rebuild hflags at MSR writes
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Continue setting, but not relying upon, env->hflags.
4
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20191018174431.1784-18-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-a64.c | 13 +++++++++++--
11
target/arm/translate.c | 28 +++++++++++++++++++++++-----
12
2 files changed, 34 insertions(+), 7 deletions(-)
13
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
17
+++ b/target/arm/translate-a64.c
18
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
19
if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
20
/* I/O operations must end the TB here (whether read or write) */
21
s->base.is_jmp = DISAS_UPDATE;
22
- } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
23
- /* We default to ending the TB on a coprocessor register write,
24
+ }
25
+ if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
26
+ /*
27
+ * A write to any coprocessor regiser that ends a TB
28
+ * must rebuild the hflags for the next TB.
29
+ */
30
+ TCGv_i32 tcg_el = tcg_const_i32(s->current_el);
31
+ gen_helper_rebuild_hflags_a64(cpu_env, tcg_el);
32
+ tcg_temp_free_i32(tcg_el);
33
+ /*
34
+ * We default to ending the TB on a coprocessor register write,
35
* but allow this to be suppressed by the register definition
36
* (usually only necessary to work around guest bugs).
37
*/
38
diff --git a/target/arm/translate.c b/target/arm/translate.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/translate.c
41
+++ b/target/arm/translate.c
42
@@ -XXX,XX +XXX,XX @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
43
ri = get_arm_cp_reginfo(s->cp_regs,
44
ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2));
45
if (ri) {
46
+ bool need_exit_tb;
47
+
48
/* Check access permissions */
49
if (!cp_access_ok(s->current_el, ri, isread)) {
50
return 1;
51
@@ -XXX,XX +XXX,XX @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
52
}
53
}
54
55
- if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
56
- /* I/O operations must end the TB here (whether read or write) */
57
- gen_lookup_tb(s);
58
- } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
59
- /* We default to ending the TB on a coprocessor register write,
60
+ /* I/O operations must end the TB here (whether read or write) */
61
+ need_exit_tb = ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) &&
62
+ (ri->type & ARM_CP_IO));
63
+
64
+ if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
65
+ /*
66
+ * A write to any coprocessor regiser that ends a TB
67
+ * must rebuild the hflags for the next TB.
68
+ */
69
+ TCGv_i32 tcg_el = tcg_const_i32(s->current_el);
70
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
71
+ gen_helper_rebuild_hflags_m32(cpu_env, tcg_el);
72
+ } else {
73
+ gen_helper_rebuild_hflags_a32(cpu_env, tcg_el);
74
+ }
75
+ tcg_temp_free_i32(tcg_el);
76
+ /*
77
+ * We default to ending the TB on a coprocessor register write,
78
* but allow this to be suppressed by the register definition
79
* (usually only necessary to work around guest bugs).
80
*/
81
+ need_exit_tb = true;
82
+ }
83
+ if (need_exit_tb) {
84
gen_lookup_tb(s);
85
}
86
87
--
88
2.20.1
89
90
diff view generated by jsdifflib
[PULL 28/41] target/arm: Rebuild hflags at CPSR writes
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Continue setting, but not relying upon, env->hflags.
4
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20191018174431.1784-19-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/op_helper.c | 3 +++
11
1 file changed, 3 insertions(+)
12
13
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/op_helper.c
16
+++ b/target/arm/op_helper.c
17
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
18
void HELPER(setend)(CPUARMState *env)
19
{
20
env->uncached_cpsr ^= CPSR_E;
21
+ arm_rebuild_hflags(env);
22
}
23
24
/* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
25
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(cpsr_read)(CPUARMState *env)
26
void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
27
{
28
cpsr_write(env, val, mask, CPSRWriteByInstr);
29
+ /* TODO: Not all cpsr bits are relevant to hflags. */
30
+ arm_rebuild_hflags(env);
31
}
32
33
/* Write the CPSR for a 32-bit exception return */
34
--
35
2.20.1
36
37
diff view generated by jsdifflib
[PULL 29/41] target/arm: Rebuild hflags at Xscale SCTLR writes
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Continue setting, but not relying upon, env->hflags.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20191018174431.1784-20-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/helper.c | 10 ++++++++++
11
1 file changed, 10 insertions(+)
12
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
16
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
18
/* ??? Lots of these bits are not implemented. */
19
/* This may enable/disable the MMU, so do a TLB flush. */
20
tlb_flush(CPU(cpu));
21
+
22
+ if (ri->type & ARM_CP_SUPPRESS_TB_END) {
23
+ /*
24
+ * Normally we would always end the TB on an SCTLR write; see the
25
+ * comment in ARMCPRegInfo sctlr initialization below for why Xscale
26
+ * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
27
+ * of hflags from the translator, so do it here.
28
+ */
29
+ arm_rebuild_hflags(env);
30
+ }
31
}
32
33
static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
34
--
35
2.20.1
36
37
diff view generated by jsdifflib
[PULL 30/41] target/arm: Rebuild hflags for M-profile
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Continue setting, but not relying upon, env->hflags.
4
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20191018174431.1784-21-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/m_helper.c | 6 ++++++
11
target/arm/translate.c | 5 ++++-
12
2 files changed, 10 insertions(+), 1 deletion(-)
13
14
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/m_helper.c
17
+++ b/target/arm/m_helper.c
18
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
19
switch_v7m_security_state(env, dest & 1);
20
env->thumb = 1;
21
env->regs[15] = dest & ~1;
22
+ arm_rebuild_hflags(env);
23
}
24
25
void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
26
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
27
switch_v7m_security_state(env, 0);
28
env->thumb = 1;
29
env->regs[15] = dest;
30
+ arm_rebuild_hflags(env);
31
}
32
33
static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
34
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
35
env->regs[14] = lr;
36
env->regs[15] = addr & 0xfffffffe;
37
env->thumb = addr & 1;
38
+ arm_rebuild_hflags(env);
39
}
40
41
static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr,
42
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
43
44
/* Otherwise, we have a successful exception exit. */
45
arm_clear_exclusive(env);
46
+ arm_rebuild_hflags(env);
47
qemu_log_mask(CPU_LOG_INT, "...successful exception return\n");
48
}
49
50
@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
51
xpsr_write(env, 0, XPSR_IT);
52
env->thumb = newpc & 1;
53
env->regs[15] = newpc & ~1;
54
+ arm_rebuild_hflags(env);
55
56
qemu_log_mask(CPU_LOG_INT, "...function return successful\n");
57
return true;
58
@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
59
switch_v7m_security_state(env, true);
60
xpsr_write(env, 0, XPSR_IT);
61
env->regs[15] += 4;
62
+ arm_rebuild_hflags(env);
63
return true;
64
65
gen_invep:
66
diff --git a/target/arm/translate.c b/target/arm/translate.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/arm/translate.c
69
+++ b/target/arm/translate.c
70
@@ -XXX,XX +XXX,XX @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a)
71
72
static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
73
{
74
- TCGv_i32 addr, reg;
75
+ TCGv_i32 addr, reg, el;
76
77
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
78
return false;
79
@@ -XXX,XX +XXX,XX @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
80
gen_helper_v7m_msr(cpu_env, addr, reg);
81
tcg_temp_free_i32(addr);
82
tcg_temp_free_i32(reg);
83
+ el = tcg_const_i32(s->current_el);
84
+ gen_helper_rebuild_hflags_m32(cpu_env, el);
85
+ tcg_temp_free_i32(el);
86
gen_lookup_tb(s);
87
return true;
88
}
89
--
90
2.20.1
91
92
diff view generated by jsdifflib
[PULL 31/41] target/arm: Rebuild hflags for M-profile NVIC
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Continue setting, but not relying upon, env->hflags.
4
5
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20191018174431.1784-22-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/intc/armv7m_nvic.c | 22 +++++++++++++---------
12
1 file changed, 13 insertions(+), 9 deletions(-)
13
14
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/armv7m_nvic.c
17
+++ b/hw/intc/armv7m_nvic.c
18
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
19
}
20
}
21
nvic_irq_update(s);
22
- return MEMTX_OK;
23
+ goto exit_ok;
24
case 0x200 ... 0x23f: /* NVIC Set pend */
25
/* the special logic in armv7m_nvic_set_pending()
26
* is not needed since IRQs are never escalated
27
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
28
}
29
}
30
nvic_irq_update(s);
31
- return MEMTX_OK;
32
+ goto exit_ok;
33
case 0x300 ... 0x33f: /* NVIC Active */
34
- return MEMTX_OK; /* R/O */
35
+ goto exit_ok; /* R/O */
36
case 0x400 ... 0x5ef: /* NVIC Priority */
37
startvec = (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */
38
39
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
40
}
41
}
42
nvic_irq_update(s);
43
- return MEMTX_OK;
44
+ goto exit_ok;
45
case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */
46
if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {
47
- return MEMTX_OK;
48
+ goto exit_ok;
49
}
50
/* fall through */
51
case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */
52
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
53
set_prio(s, hdlidx, sbank, newprio);
54
}
55
nvic_irq_update(s);
56
- return MEMTX_OK;
57
+ goto exit_ok;
58
case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */
59
if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {
60
- return MEMTX_OK;
61
+ goto exit_ok;
62
}
63
/* All bits are W1C, so construct 32 bit value with 0s in
64
* the parts not written by the access size
65
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
66
*/
67
s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK);
68
}
69
- return MEMTX_OK;
70
+ goto exit_ok;
71
}
72
if (size == 4) {
73
nvic_writel(s, offset, value, attrs);
74
- return MEMTX_OK;
75
+ goto exit_ok;
76
}
77
qemu_log_mask(LOG_GUEST_ERROR,
78
"NVIC: Bad write of size %d at offset 0x%x\n", size, offset);
79
/* This is UNPREDICTABLE; treat as RAZ/WI */
80
+
81
+ exit_ok:
82
+ /* Ensure any changes made are reflected in the cached hflags. */
83
+ arm_rebuild_hflags(&s->cpu->env);
84
return MEMTX_OK;
85
}
86
87
--
88
2.20.1
89
90
diff view generated by jsdifflib
[PULL 32/41] target/arm: Rely on hflags correct in cpu_get_tb_cpu_state
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
This is the payoff.
4
5
From perf record -g data of ubuntu 18 boot and shutdown:
6
7
BEFORE:
8
9
- 23.02% 2.82% qemu-system-aar [.] helper_lookup_tb_ptr
10
- 20.22% helper_lookup_tb_ptr
11
+ 10.05% tb_htable_lookup
12
- 9.13% cpu_get_tb_cpu_state
13
3.20% aa64_va_parameters_both
14
0.55% fp_exception_el
15
16
- 11.66% 4.74% qemu-system-aar [.] cpu_get_tb_cpu_state
17
- 6.96% cpu_get_tb_cpu_state
18
3.63% aa64_va_parameters_both
19
0.60% fp_exception_el
20
0.53% sve_exception_el
21
22
AFTER:
23
24
- 16.40% 3.40% qemu-system-aar [.] helper_lookup_tb_ptr
25
- 13.03% helper_lookup_tb_ptr
26
+ 11.19% tb_htable_lookup
27
0.55% cpu_get_tb_cpu_state
28
29
0.98% 0.71% qemu-system-aar [.] cpu_get_tb_cpu_state
30
31
0.87% 0.24% qemu-system-aar [.] rebuild_hflags_a64
32
33
Before, helper_lookup_tb_ptr is the second hottest function in the
34
application, consuming almost a quarter of the runtime. Within the
35
entire execution, cpu_get_tb_cpu_state consumes about 12%.
36
37
After, helper_lookup_tb_ptr has dropped to the fourth hottest function,
38
with consumption dropping to a sixth of the runtime. Within the
39
entire execution, cpu_get_tb_cpu_state has dropped below 1%, and the
40
supporting function to rebuild hflags also consumes about 1%.
41
42
Assertions are retained for --enable-debug-tcg.
43
44
Tested-by: Alex Bennée <alex.bennee@linaro.org>
45
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
46
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
47
Message-id: 20191018174431.1784-23-richard.henderson@linaro.org
48
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
49
---
50
target/arm/helper.c | 9 ++++++---
51
1 file changed, 6 insertions(+), 3 deletions(-)
52
53
diff --git a/target/arm/helper.c b/target/arm/helper.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/target/arm/helper.c
56
+++ b/target/arm/helper.c
57
@@ -XXX,XX +XXX,XX @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el)
58
void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
59
target_ulong *cs_base, uint32_t *pflags)
60
{
61
- uint32_t flags, pstate_for_ss;
62
+ uint32_t flags = env->hflags;
63
+ uint32_t pstate_for_ss;
64
65
*cs_base = 0;
66
- flags = rebuild_hflags_internal(env);
67
+#ifdef CONFIG_DEBUG_TCG
68
+ assert(flags == rebuild_hflags_internal(env));
69
+#endif
70
71
- if (is_a64(env)) {
72
+ if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) {
73
*pc = env->pc;
74
if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
75
flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);
76
--
77
2.20.1
78
79
diff view generated by jsdifflib
[PULL 33/41] hw/sd/sdhci: Add a comment to distinct the i.MX eSDHC functions
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
This file keeps the various QDev blocks separated by comments.
4
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Cleber Rosa <crosa@redhat.com>
7
Message-id: 20191005154748.21718-3-f4bug@amsat.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/sd/sdhci.c | 3 ++-
11
1 file changed, 2 insertions(+), 1 deletion(-)
12
13
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/sd/sdhci.c
16
+++ b/hw/sd/sdhci.c
17
@@ -XXX,XX +XXX,XX @@ static const TypeInfo sdhci_bus_info = {
18
.class_init = sdhci_bus_class_init,
19
};
20
21
+/* --- qdev i.MX eSDHC --- */
22
+
23
static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
24
{
25
SDHCIState *s = SYSBUS_SDHCI(opaque);
26
@@ -XXX,XX +XXX,XX @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
27
}
28
}
29
30
-
31
static const MemoryRegionOps usdhc_mmio_ops = {
32
.read = usdhc_read,
33
.write = usdhc_write,
34
--
35
2.20.1
36
37
diff view generated by jsdifflib
[PULL 34/41] hw/sd/sdhci: Add dummy Samsung SDHCI controller
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
The Linux kernel access few S3C-specific registers [1] to set some
4
clock. We don't care about this part for device emulation [2]. Add
5
a dummy device to properly ignore these accesses, so we can focus
6
on the important registers missing.
7
8
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/mmc/host/sdhci-s3c-regs.h?h=cc014f3
9
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/mmc/host/sdhci-s3c.c?h=v5.3#n263
10
11
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
13
Message-id: 20191005154748.21718-4-f4bug@amsat.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
include/hw/sd/sdhci.h | 2 ++
17
hw/sd/sdhci.c | 65 +++++++++++++++++++++++++++++++++++++++++++
18
2 files changed, 67 insertions(+)
19
20
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/sd/sdhci.h
23
+++ b/include/hw/sd/sdhci.h
24
@@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState {
25
26
#define TYPE_IMX_USDHC "imx-usdhc"
27
28
+#define TYPE_S3C_SDHCI "s3c-sdhci"
29
+
30
#endif /* SDHCI_H */
31
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/sd/sdhci.c
34
+++ b/hw/sd/sdhci.c
35
@@ -XXX,XX +XXX,XX @@ static const TypeInfo imx_usdhc_info = {
36
.instance_init = imx_usdhc_init,
37
};
38
39
+/* --- qdev Samsung s3c --- */
40
+
41
+#define S3C_SDHCI_CONTROL2 0x80
42
+#define S3C_SDHCI_CONTROL3 0x84
43
+#define S3C_SDHCI_CONTROL4 0x8c
44
+
45
+static uint64_t sdhci_s3c_read(void *opaque, hwaddr offset, unsigned size)
46
+{
47
+ uint64_t ret;
48
+
49
+ switch (offset) {
50
+ case S3C_SDHCI_CONTROL2:
51
+ case S3C_SDHCI_CONTROL3:
52
+ case S3C_SDHCI_CONTROL4:
53
+ /* ignore */
54
+ ret = 0;
55
+ break;
56
+ default:
57
+ ret = sdhci_read(opaque, offset, size);
58
+ break;
59
+ }
60
+
61
+ return ret;
62
+}
63
+
64
+static void sdhci_s3c_write(void *opaque, hwaddr offset, uint64_t val,
65
+ unsigned size)
66
+{
67
+ switch (offset) {
68
+ case S3C_SDHCI_CONTROL2:
69
+ case S3C_SDHCI_CONTROL3:
70
+ case S3C_SDHCI_CONTROL4:
71
+ /* ignore */
72
+ break;
73
+ default:
74
+ sdhci_write(opaque, offset, val, size);
75
+ break;
76
+ }
77
+}
78
+
79
+static const MemoryRegionOps sdhci_s3c_mmio_ops = {
80
+ .read = sdhci_s3c_read,
81
+ .write = sdhci_s3c_write,
82
+ .valid = {
83
+ .min_access_size = 1,
84
+ .max_access_size = 4,
85
+ .unaligned = false
86
+ },
87
+ .endianness = DEVICE_LITTLE_ENDIAN,
88
+};
89
+
90
+static void sdhci_s3c_init(Object *obj)
91
+{
92
+ SDHCIState *s = SYSBUS_SDHCI(obj);
93
+
94
+ s->io_ops = &sdhci_s3c_mmio_ops;
95
+}
96
+
97
+static const TypeInfo sdhci_s3c_info = {
98
+ .name = TYPE_S3C_SDHCI ,
99
+ .parent = TYPE_SYSBUS_SDHCI,
100
+ .instance_init = sdhci_s3c_init,
101
+};
102
+
103
static void sdhci_register_types(void)
104
{
105
type_register_static(&sdhci_sysbus_info);
106
type_register_static(&sdhci_bus_info);
107
type_register_static(&imx_usdhc_info);
108
+ type_register_static(&sdhci_s3c_info);
109
}
110
111
type_init(sdhci_register_types)
112
--
113
2.20.1
114
115
diff view generated by jsdifflib
[PULL 35/41] hw/arm/exynos4210: Use the Samsung s3c SDHCI controller
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
The Exynos SoC has specific SDHCI registers. Use the s3c SDHCI
4
model which handle these specific registers.
5
6
This silents the following "SDHC ... not implemented" warnings so
7
we can focus on the important registers missing:
8
9
$ qemu-system-arm ... -d unimp \
10
-append "... root=/dev/mmcblk0 rootfstype=ext4 rw rootwait" \
11
-drive file=linux-build-test/rootfs/arm/rootfs-armv5.ext2,if=sd,format=raw
12
[...]
13
[ 25.744858] sdhci: Secure Digital Host Controller Interface driver
14
[ 25.745862] sdhci: Copyright(c) Pierre Ossman
15
[ 25.783188] s3c-sdhci 12530000.sdhci: clock source 2: mmc_busclk.2 (12000000 Hz)
16
SDHC rd_4b @0x80 not implemented
17
SDHC wr_4b @0x80 <- 0x00000020 not implemented
18
SDHC wr_4b @0x8c <- 0x00030000 not implemented
19
SDHC rd_4b @0x80 not implemented
20
SDHC wr_4b @0x80 <- 0xc0004100 not implemented
21
SDHC wr_4b @0x84 <- 0x80808080 not implemented
22
[ 26.013318] mmc0: SDHCI controller on samsung-hsmmc [12530000.sdhci] using ADMA
23
[ 26.032318] Synopsys Designware Multimedia Card Interface Driver
24
[ 42.024885] Waiting for root device /dev/mmcblk0...
25
26
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
27
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
28
Message-id: 20191005154748.21718-5-f4bug@amsat.org
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
---
31
hw/arm/exynos4210.c | 2 +-
32
1 file changed, 1 insertion(+), 1 deletion(-)
33
34
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/arm/exynos4210.c
37
+++ b/hw/arm/exynos4210.c
38
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
39
* public datasheet which is very similar (implementing
40
* MMC Specification Version 4.0 being the only difference noted)
41
*/
42
- dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
43
+ dev = qdev_create(NULL, TYPE_S3C_SDHCI);
44
qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES);
45
qdev_init_nofail(dev);
46
47
--
48
2.20.1
49
50
diff view generated by jsdifflib
[PULL 36/41] hw/arm/xilinx_zynq: Use the IEC binary prefix definitions
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
IEC binary prefixes ease code review: the unit is explicit.
4
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20191021190653.9511-2-philmd@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/xilinx_zynq.c | 3 ++-
12
1 file changed, 2 insertions(+), 1 deletion(-)
13
14
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/xilinx_zynq.c
17
+++ b/hw/arm/xilinx_zynq.c
18
@@ -XXX,XX +XXX,XX @@
19
*/
20
21
#include "qemu/osdep.h"
22
+#include "qemu/units.h"
23
#include "qapi/error.h"
24
#include "cpu.h"
25
#include "hw/sysbus.h"
26
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
27
memory_region_add_subregion(address_space_mem, 0, ext_ram);
28
29
/* 256K of on-chip memory */
30
- memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10,
31
+ memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB,
32
&error_fatal);
33
memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
34
35
--
36
2.20.1
37
38
diff view generated by jsdifflib
[PULL 37/41] hw/arm/mps2: Use the IEC binary prefix definitions
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
IEC binary prefixes ease code review: the unit is explicit.
4
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20191021190653.9511-3-philmd@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/mps2-tz.c | 3 ++-
12
hw/arm/mps2.c | 3 ++-
13
2 files changed, 4 insertions(+), 2 deletions(-)
14
15
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/mps2-tz.c
18
+++ b/hw/arm/mps2-tz.c
19
@@ -XXX,XX +XXX,XX @@
20
*/
21
22
#include "qemu/osdep.h"
23
+#include "qemu/units.h"
24
#include "qapi/error.h"
25
#include "qemu/error-report.h"
26
#include "hw/arm/boot.h"
27
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
28
* call the 16MB our "system memory", as it's the largest lump.
29
*/
30
memory_region_allocate_system_memory(&mms->psram,
31
- NULL, "mps.ram", 0x01000000);
32
+ NULL, "mps.ram", 16 * MiB);
33
memory_region_add_subregion(system_memory, 0x80000000, &mms->psram);
34
35
/* The overflow IRQs for all UARTs are ORed together.
36
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/arm/mps2.c
39
+++ b/hw/arm/mps2.c
40
@@ -XXX,XX +XXX,XX @@
41
*/
42
43
#include "qemu/osdep.h"
44
+#include "qemu/units.h"
45
#include "qapi/error.h"
46
#include "qemu/error-report.h"
47
#include "hw/arm/boot.h"
48
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
49
* zbt_boot_ctrl is always zero).
50
*/
51
memory_region_allocate_system_memory(&mms->psram,
52
- NULL, "mps.ram", 0x1000000);
53
+ NULL, "mps.ram", 16 * MiB);
54
memory_region_add_subregion(system_memory, 0x21000000, &mms->psram);
55
56
switch (mmc->fpga_type) {
57
--
58
2.20.1
59
60
diff view generated by jsdifflib
[PULL 38/41] hw/arm/collie: Create the RAM in the board
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
The SDRAM is incorrectly created in the SA1110 SoC.
4
Move its creation in the board code, this will later allow the
5
board to have the QOM ownership of the RAM.
6
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20191021190653.9511-4-philmd@redhat.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/strongarm.h | 4 +---
14
hw/arm/collie.c | 8 ++++++--
15
hw/arm/strongarm.c | 7 +------
16
3 files changed, 8 insertions(+), 11 deletions(-)
17
18
diff --git a/hw/arm/strongarm.h b/hw/arm/strongarm.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/strongarm.h
21
+++ b/hw/arm/strongarm.h
22
@@ -XXX,XX +XXX,XX @@ enum {
23
24
typedef struct {
25
ARMCPU *cpu;
26
- MemoryRegion sdram;
27
DeviceState *pic;
28
DeviceState *gpio;
29
DeviceState *ppc;
30
@@ -XXX,XX +XXX,XX @@ typedef struct {
31
SSIBus *ssp_bus;
32
} StrongARMState;
33
34
-StrongARMState *sa1110_init(MemoryRegion *sysmem,
35
- unsigned int sdram_size, const char *rev);
36
+StrongARMState *sa1110_init(const char *cpu_type);
37
38
#endif
39
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/arm/collie.c
42
+++ b/hw/arm/collie.c
43
@@ -XXX,XX +XXX,XX @@ static void collie_init(MachineState *machine)
44
{
45
StrongARMState *s;
46
DriveInfo *dinfo;
47
- MemoryRegion *sysmem = get_system_memory();
48
+ MemoryRegion *sdram = g_new(MemoryRegion, 1);
49
50
- s = sa1110_init(sysmem, collie_binfo.ram_size, machine->cpu_type);
51
+ s = sa1110_init(machine->cpu_type);
52
+
53
+ memory_region_allocate_system_memory(sdram, NULL, "strongarm.sdram",
54
+ collie_binfo.ram_size);
55
+ memory_region_add_subregion(get_system_memory(), SA_SDCS0, sdram);
56
57
dinfo = drive_get(IF_PFLASH, 0, 0);
58
pflash_cfi01_register(SA_CS0, "collie.fl1", 0x02000000,
59
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/arm/strongarm.c
62
+++ b/hw/arm/strongarm.c
63
@@ -XXX,XX +XXX,XX @@ static const TypeInfo strongarm_ssp_info = {
64
};
65
66
/* Main CPU functions */
67
-StrongARMState *sa1110_init(MemoryRegion *sysmem,
68
- unsigned int sdram_size, const char *cpu_type)
69
+StrongARMState *sa1110_init(const char *cpu_type)
70
{
71
StrongARMState *s;
72
int i;
73
@@ -XXX,XX +XXX,XX @@ StrongARMState *sa1110_init(MemoryRegion *sysmem,
74
75
s->cpu = ARM_CPU(cpu_create(cpu_type));
76
77
- memory_region_allocate_system_memory(&s->sdram, NULL, "strongarm.sdram",
78
- sdram_size);
79
- memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
80
-
81
s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
82
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ),
83
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ),
84
--
85
2.20.1
86
87
diff view generated by jsdifflib
[PULL 39/41] hw/arm/omap2: Create the RAM in the board
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
The SDRAM is incorrectly created in the OMAP2420 SoC.
4
Move its creation in the board code, this will later allow the
5
board to have the QOM ownership of the RAM.
6
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20191021190653.9511-5-philmd@redhat.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/hw/arm/omap.h | 4 +---
14
hw/arm/nseries.c | 10 +++++++---
15
hw/arm/omap2.c | 13 +++++--------
16
3 files changed, 13 insertions(+), 14 deletions(-)
17
18
diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/omap.h
21
+++ b/include/hw/arm/omap.h
22
@@ -XXX,XX +XXX,XX @@ struct omap_mpu_state_s {
23
MemoryRegion tap_iomem;
24
MemoryRegion imif_ram;
25
MemoryRegion emiff_ram;
26
- MemoryRegion sdram;
27
MemoryRegion sram;
28
29
struct omap_dma_port_if_s {
30
@@ -XXX,XX +XXX,XX @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
31
const char *core);
32
33
/* omap2.c */
34
-struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
35
- unsigned long sdram_size,
36
+struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
37
const char *core);
38
39
uint32_t omap_badwidth_read8(void *opaque, hwaddr addr);
40
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/arm/nseries.c
43
+++ b/hw/arm/nseries.c
44
@@ -XXX,XX +XXX,XX @@
45
46
/* Nokia N8x0 support */
47
struct n800_s {
48
+ MemoryRegion sdram;
49
struct omap_mpu_state_s *mpu;
50
51
struct rfbi_chip_s blizzard;
52
@@ -XXX,XX +XXX,XX @@ static int n810_atag_setup(const struct arm_boot_info *info, void *p)
53
static void n8x0_init(MachineState *machine,
54
struct arm_boot_info *binfo, int model)
55
{
56
- MemoryRegion *sysmem = get_system_memory();
57
struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
58
- int sdram_size = binfo->ram_size;
59
+ uint64_t sdram_size = binfo->ram_size;
60
61
- s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_type);
62
+ memory_region_allocate_system_memory(&s->sdram, NULL, "omap2.dram",
63
+ sdram_size);
64
+ memory_region_add_subregion(get_system_memory(), OMAP2_Q2_BASE, &s->sdram);
65
+
66
+ s->mpu = omap2420_mpu_init(&s->sdram, machine->cpu_type);
67
68
/* Setup peripherals
69
*
70
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/arm/omap2.c
73
+++ b/hw/arm/omap2.c
74
@@ -XXX,XX +XXX,XX @@
75
#include "qemu/error-report.h"
76
#include "qapi/error.h"
77
#include "cpu.h"
78
+#include "exec/address-spaces.h"
79
#include "sysemu/blockdev.h"
80
#include "sysemu/qtest.h"
81
#include "sysemu/reset.h"
82
@@ -XXX,XX +XXX,XX @@ static const struct dma_irq_map omap2_dma_irq_map[] = {
83
{ 0, OMAP_INT_24XX_SDMA_IRQ3 },
84
};
85
86
-struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
87
- unsigned long sdram_size,
88
+struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
89
const char *cpu_type)
90
{
91
struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
92
@@ -XXX,XX +XXX,XX @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
93
int i;
94
SysBusDevice *busdev;
95
struct omap_target_agent_s *ta;
96
+ MemoryRegion *sysmem = get_system_memory();
97
98
/* Core */
99
s->mpu_model = omap2420;
100
s->cpu = ARM_CPU(cpu_create(cpu_type));
101
- s->sdram_size = sdram_size;
102
s->sram_size = OMAP242X_SRAM_SIZE;
103
104
s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0);
105
@@ -XXX,XX +XXX,XX @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
106
omap_clk_init(s);
107
108
/* Memory-mapped stuff */
109
- memory_region_allocate_system_memory(&s->sdram, NULL, "omap2.dram",
110
- s->sdram_size);
111
- memory_region_add_subregion(sysmem, OMAP2_Q2_BASE, &s->sdram);
112
memory_region_init_ram(&s->sram, NULL, "omap2.sram", s->sram_size,
113
&error_fatal);
114
memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram);
115
@@ -XXX,XX +XXX,XX @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
116
s->port->addr_valid = omap2_validate_addr;
117
118
/* Register SDRAM and SRAM ports for fast DMA transfers. */
119
- soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sdram),
120
- OMAP2_Q2_BASE, s->sdram_size);
121
+ soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(sdram),
122
+ OMAP2_Q2_BASE, memory_region_size(sdram));
123
soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sram),
124
OMAP2_SRAM_BASE, s->sram_size);
125
126
--
127
2.20.1
128
129
diff view generated by jsdifflib
[PULL 40/41] hw/arm/omap1: Create the RAM in the board
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
The SDRAM is incorrectly created in the OMAP310 SoC.
4
Move its creation in the board code, this will later allow the
5
board to have the QOM ownership of the RAM.
6
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20191021190653.9511-6-philmd@redhat.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/hw/arm/omap.h | 6 ++----
14
hw/arm/omap1.c | 12 +++++-------
15
hw/arm/omap_sx1.c | 8 ++++++--
16
hw/arm/palm.c | 8 ++++++--
17
4 files changed, 19 insertions(+), 15 deletions(-)
18
19
diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/omap.h
22
+++ b/include/hw/arm/omap.h
23
@@ -XXX,XX +XXX,XX @@ struct omap_mpu_state_s {
24
MemoryRegion mpui_io_iomem;
25
MemoryRegion tap_iomem;
26
MemoryRegion imif_ram;
27
- MemoryRegion emiff_ram;
28
MemoryRegion sram;
29
30
struct omap_dma_port_if_s {
31
@@ -XXX,XX +XXX,XX @@ struct omap_mpu_state_s {
32
hwaddr addr);
33
} port[__omap_dma_port_last];
34
35
- unsigned long sdram_size;
36
+ uint64_t sdram_size;
37
unsigned long sram_size;
38
39
/* MPUI-TIPB peripherals */
40
@@ -XXX,XX +XXX,XX @@ struct omap_mpu_state_s {
41
};
42
43
/* omap1.c */
44
-struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
45
- unsigned long sdram_size,
46
+struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram,
47
const char *core);
48
49
/* omap2.c */
50
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/hw/arm/omap1.c
53
+++ b/hw/arm/omap1.c
54
@@ -XXX,XX +XXX,XX @@
55
#include "qapi/error.h"
56
#include "qemu-common.h"
57
#include "cpu.h"
58
+#include "exec/address-spaces.h"
59
#include "hw/boards.h"
60
#include "hw/hw.h"
61
#include "hw/irq.h"
62
@@ -XXX,XX +XXX,XX @@ static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
63
return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr);
64
}
65
66
-struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
67
- unsigned long sdram_size,
68
+struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,
69
const char *cpu_type)
70
{
71
int i;
72
@@ -XXX,XX +XXX,XX @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
73
qemu_irq dma_irqs[6];
74
DriveInfo *dinfo;
75
SysBusDevice *busdev;
76
+ MemoryRegion *system_memory = get_system_memory();
77
78
/* Core */
79
s->mpu_model = omap310;
80
s->cpu = ARM_CPU(cpu_create(cpu_type));
81
- s->sdram_size = sdram_size;
82
+ s->sdram_size = memory_region_size(dram);
83
s->sram_size = OMAP15XX_SRAM_SIZE;
84
85
s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0);
86
@@ -XXX,XX +XXX,XX @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
87
omap_clk_init(s);
88
89
/* Memory-mapped stuff */
90
- memory_region_allocate_system_memory(&s->emiff_ram, NULL, "omap1.dram",
91
- s->sdram_size);
92
- memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram);
93
memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size,
94
&error_fatal);
95
memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram);
96
@@ -XXX,XX +XXX,XX @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
97
s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
98
99
/* Register SDRAM and SRAM DMA ports for fast transfers. */
100
- soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->emiff_ram),
101
+ soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(dram),
102
OMAP_EMIFF_BASE, s->sdram_size);
103
soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram),
104
OMAP_IMIF_BASE, s->sram_size);
105
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
106
index XXXXXXX..XXXXXXX 100644
107
--- a/hw/arm/omap_sx1.c
108
+++ b/hw/arm/omap_sx1.c
109
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
110
{
111
struct omap_mpu_state_s *mpu;
112
MemoryRegion *address_space = get_system_memory();
113
+ MemoryRegion *dram = g_new(MemoryRegion, 1);
114
MemoryRegion *flash = g_new(MemoryRegion, 1);
115
MemoryRegion *cs = g_new(MemoryRegion, 4);
116
static uint32_t cs0val = 0x00213090;
117
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
118
flash_size = flash2_size;
119
}
120
121
- mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size,
122
- machine->cpu_type);
123
+ memory_region_allocate_system_memory(dram, NULL, "omap1.dram",
124
+ sx1_binfo.ram_size);
125
+ memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, dram);
126
+
127
+ mpu = omap310_mpu_init(dram, machine->cpu_type);
128
129
/* External Flash (EMIFS) */
130
memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size,
131
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/hw/arm/palm.c
134
+++ b/hw/arm/palm.c
135
@@ -XXX,XX +XXX,XX @@ static void palmte_init(MachineState *machine)
136
MemoryRegion *address_space_mem = get_system_memory();
137
struct omap_mpu_state_s *mpu;
138
int flash_size = 0x00800000;
139
- int sdram_size = palmte_binfo.ram_size;
140
static uint32_t cs0val = 0xffffffff;
141
static uint32_t cs1val = 0x0000e1a0;
142
static uint32_t cs2val = 0x0000e1a0;
143
static uint32_t cs3val = 0xe1a0e1a0;
144
int rom_size, rom_loaded = 0;
145
+ MemoryRegion *dram = g_new(MemoryRegion, 1);
146
MemoryRegion *flash = g_new(MemoryRegion, 1);
147
MemoryRegion *cs = g_new(MemoryRegion, 4);
148
149
- mpu = omap310_mpu_init(address_space_mem, sdram_size, machine->cpu_type);
150
+ memory_region_allocate_system_memory(dram, NULL, "omap1.dram",
151
+ palmte_binfo.ram_size);
152
+ memory_region_add_subregion(address_space_mem, OMAP_EMIFF_BASE, dram);
153
+
154
+ mpu = omap310_mpu_init(dram, machine->cpu_type);
155
156
/* External Flash (EMIFS) */
157
memory_region_init_ram(flash, NULL, "palmte.flash", flash_size,
158
--
159
2.20.1
160
161
diff view generated by jsdifflib
[PULL 41/41] hw/arm/digic4: Inline digic4_board_setup_ram() function
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
Having the RAM creation code in a separate function is not
4
very helpful. Move this code directly inside the board_init()
5
function, this will later allow the board to have the QOM
6
ownership of the RAM.
7
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 20191021190653.9511-7-philmd@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/digic_boards.c | 9 ++-------
15
1 file changed, 2 insertions(+), 7 deletions(-)
16
17
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/digic_boards.c
20
+++ b/hw/arm/digic_boards.c
21
@@ -XXX,XX +XXX,XX @@ typedef struct DigicBoard {
22
const char *rom1_def_filename;
23
} DigicBoard;
24
25
-static void digic4_board_setup_ram(DigicBoardState *s, hwaddr ram_size)
26
-{
27
- memory_region_allocate_system_memory(&s->ram, NULL, "ram", ram_size);
28
- memory_region_add_subregion(get_system_memory(), 0, &s->ram);
29
-}
30
-
31
static void digic4_board_init(DigicBoard *board)
32
{
33
Error *err = NULL;
34
@@ -XXX,XX +XXX,XX @@ static void digic4_board_init(DigicBoard *board)
35
exit(1);
36
}
37
38
- digic4_board_setup_ram(s, board->ram_size);
39
+ memory_region_allocate_system_memory(&s->ram, NULL, "ram", board->ram_size);
40
+ memory_region_add_subregion(get_system_memory(), 0, &s->ram);
41
42
if (board->add_rom0) {
43
board->add_rom0(s, DIGIC4_ROM0_BASE, board->rom0_def_filename);
44
--
45
2.20.1
46
47
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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