aspeed/i2c: Add support for pool and DMA transfer modes

[PATCH 0/5] aspeed/i2c: Add support for pool and DMA transfer modes

Cédric Le Goater posted 5 patches 4 years, 6 months ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20191016085035.12136-1-clg@kaod.org

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Maintainers: Joel Stanley <joel@jms.id.au>, "Cédric Le Goater" <clg@kaod.org>, Andrew Jeffery <andrew@aj.id.au>, Peter Maydell <peter.maydell@linaro.org>

include/hw/arm/aspeed_soc.h |   1 +
include/hw/i2c/aspeed_i2c.h |  16 ++
hw/arm/aspeed_ast2600.c     |  12 +-
hw/arm/aspeed_soc.c         |  14 +-
hw/i2c/aspeed_i2c.c         | 439 +++++++++++++++++++++++++++++++++---
hw/i2c/trace-events         |   9 +
6 files changed, 459 insertions(+), 32 deletions(-)

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[PATCH 0/5] aspeed/i2c: Add support for pool and DMA transfer modes

Posted by Cédric Le Goater 4 years, 6 months ago

Hello,

The Aspeed I2C controller can operate in three different transfer
modes :

  - Byte Buffer mode, using a dedicated register to transfer a
    byte. This is what the model supports today.

  - Pool Buffer mode, using an internal SRAM to transfer multiple
    bytes in the same command sequence.

  - DMA mode, supporting transfers up to 4K to and from DRAM.

This series adds support for the pool and DMA transfer modes taking
into account the specificities of each SoC.

Last patch adds some traces which proved to be useful to debug the
I2C state machine.

Thanks,

C.

Cédric Le Goater (5):
  aspeed/i2c: Add support for pool buffer transfers
  aspeed/i2c: Check SRAM enablement on A2500
  aspeed: Add a DRAM memory region at the SoC level
  aspeed/i2c: Add support for DMA transfers
  aspeed/i2c: Add trace events

 include/hw/arm/aspeed_soc.h |   1 +
 include/hw/i2c/aspeed_i2c.h |  16 ++
 hw/arm/aspeed_ast2600.c     |  12 +-
 hw/arm/aspeed_soc.c         |  14 +-
 hw/i2c/aspeed_i2c.c         | 439 +++++++++++++++++++++++++++++++++---
 hw/i2c/trace-events         |   9 +
 6 files changed, 459 insertions(+), 32 deletions(-)

-- 
2.21.0