| 1 | A large arm pullreq, mostly because of 3 series: | 1 | First arm pullreq of the cycle; this is mostly my softfloat NaN |
|---|---|---|---|
| 2 | * aspeed 2600 support | 2 | handling series. (Lots more in my to-review queue, but I don't |
| 3 | * semihosting v2.0 support | 3 | like pullreqs growing too close to a hundred patches at a time :-)) |
| 4 | * transaction-based ptimers | ||
| 5 | 4 | ||
| 6 | thanks | 5 | thanks |
| 7 | -- PMM | 6 | -- PMM |
| 8 | 7 | ||
| 9 | The following changes since commit 22dbfdecc3c52228d3489da3fe81da92b21197bf: | 8 | The following changes since commit 97f2796a3736ed37a1b85dc1c76a6c45b829dd17: |
| 10 | 9 | ||
| 11 | Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20191010.0' into staging (2019-10-14 15:09:08 +0100) | 10 | Open 10.0 development tree (2024-12-10 17:41:17 +0000) |
| 12 | 11 | ||
| 13 | are available in the Git repository at: | 12 | are available in the Git repository at: |
| 14 | 13 | ||
| 15 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191014 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241211 |
| 16 | 15 | ||
| 17 | for you to fetch changes up to bca1936f8f66c5f8a111569ffd14969de208bf3b: | 16 | for you to fetch changes up to 1abe28d519239eea5cf9620bb13149423e5665f8: |
| 18 | 17 | ||
| 19 | hw/misc/bcm2835_mbox: Add trace events (2019-10-14 16:48:56 +0100) | 18 | MAINTAINERS: Add correct email address for Vikram Garhwal (2024-12-11 15:31:09 +0000) |
| 20 | 19 | ||
| 21 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
| 22 | target-arm queue: | 21 | target-arm queue: |
| 23 | * Add Aspeed AST2600 SoC and board support | 22 | * hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs |
| 24 | * aspeed/wdt: Check correct register for clock source | 23 | * fpu: Make muladd NaN handling runtime-selected, not compile-time |
| 25 | * bcm2835: code cleanups, better logging, trace events | 24 | * fpu: Make default NaN pattern runtime-selected, not compile-time |
| 26 | * implement v2.0 of the Arm semihosting specification | 25 | * fpu: Minor NaN-related cleanups |
| 27 | * provide new 'transaction-based' ptimer API and use it | 26 | * MAINTAINERS: email address updates |
| 28 | for the Arm devices that use ptimers | ||
| 29 | * ARM: KVM: support more than 256 CPUs | ||
| 30 | 27 | ||
| 31 | ---------------------------------------------------------------- | 28 | ---------------------------------------------------------------- |
| 32 | Amithash Prasad (1): | 29 | Bernhard Beschow (5): |
| 33 | aspeed/wdt: Check correct register for clock source | 30 | hw/net/lan9118: Extract lan9118_phy |
| 31 | hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations | ||
| 32 | hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register | ||
| 33 | hw/net/lan9118_phy: Reuse MII constants | ||
| 34 | hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement | ||
| 34 | 35 | ||
| 35 | Cédric Le Goater (15): | 36 | Leif Lindholm (1): |
| 36 | aspeed/timer: Introduce an object class per SoC | 37 | MAINTAINERS: update email address for Leif Lindholm |
| 37 | aspeed/timer: Add support for control register 3 | ||
| 38 | aspeed/timer: Add AST2600 support | ||
| 39 | aspeed/timer: Add support for IRQ status register on the AST2600 | ||
| 40 | aspeed/sdmc: Introduce an object class per SoC | ||
| 41 | watchdog/aspeed: Introduce an object class per SoC | ||
| 42 | aspeed/smc: Introduce segment operations | ||
| 43 | aspeed/smc: Add AST2600 support | ||
| 44 | aspeed/i2c: Introduce an object class per SoC | ||
| 45 | aspeed/i2c: Add AST2600 support | ||
| 46 | aspeed: Introduce an object class per SoC | ||
| 47 | aspeed/soc: Add AST2600 support | ||
| 48 | m25p80: Add support for w25q512jv | ||
| 49 | aspeed: Add an AST2600 eval board | ||
| 50 | aspeed: add support for the Aspeed MII controller of the AST2600 | ||
| 51 | 38 | ||
| 52 | Eddie James (1): | 39 | Peter Maydell (54): |
| 53 | hw/sd/aspeed_sdhci: New device | 40 | fpu: handle raising Invalid for infzero in pick_nan_muladd |
| 41 | fpu: Check for default_nan_mode before calling pickNaNMulAdd | ||
| 42 | softfloat: Allow runtime choice of inf * 0 + NaN result | ||
| 43 | tests/fp: Explicitly set inf-zero-nan rule | ||
| 44 | target/arm: Set FloatInfZeroNaNRule explicitly | ||
| 45 | target/s390: Set FloatInfZeroNaNRule explicitly | ||
| 46 | target/ppc: Set FloatInfZeroNaNRule explicitly | ||
| 47 | target/mips: Set FloatInfZeroNaNRule explicitly | ||
| 48 | target/sparc: Set FloatInfZeroNaNRule explicitly | ||
| 49 | target/xtensa: Set FloatInfZeroNaNRule explicitly | ||
| 50 | target/x86: Set FloatInfZeroNaNRule explicitly | ||
| 51 | target/loongarch: Set FloatInfZeroNaNRule explicitly | ||
| 52 | target/hppa: Set FloatInfZeroNaNRule explicitly | ||
| 53 | softfloat: Pass have_snan to pickNaNMulAdd | ||
| 54 | softfloat: Allow runtime choice of NaN propagation for muladd | ||
| 55 | tests/fp: Explicitly set 3-NaN propagation rule | ||
| 56 | target/arm: Set Float3NaNPropRule explicitly | ||
| 57 | target/loongarch: Set Float3NaNPropRule explicitly | ||
| 58 | target/ppc: Set Float3NaNPropRule explicitly | ||
| 59 | target/s390x: Set Float3NaNPropRule explicitly | ||
| 60 | target/sparc: Set Float3NaNPropRule explicitly | ||
| 61 | target/mips: Set Float3NaNPropRule explicitly | ||
| 62 | target/xtensa: Set Float3NaNPropRule explicitly | ||
| 63 | target/i386: Set Float3NaNPropRule explicitly | ||
| 64 | target/hppa: Set Float3NaNPropRule explicitly | ||
| 65 | fpu: Remove use_first_nan field from float_status | ||
| 66 | target/m68k: Don't pass NULL float_status to floatx80_default_nan() | ||
| 67 | softfloat: Create floatx80 default NaN from parts64_default_nan | ||
| 68 | target/loongarch: Use normal float_status in fclass_s and fclass_d helpers | ||
| 69 | target/m68k: In frem helper, initialize local float_status from env->fp_status | ||
| 70 | target/m68k: Init local float_status from env fp_status in gdb get/set reg | ||
| 71 | target/sparc: Initialize local scratch float_status from env->fp_status | ||
| 72 | target/ppc: Use env->fp_status in helper_compute_fprf functions | ||
| 73 | fpu: Allow runtime choice of default NaN value | ||
| 74 | tests/fp: Set default NaN pattern explicitly | ||
| 75 | target/microblaze: Set default NaN pattern explicitly | ||
| 76 | target/i386: Set default NaN pattern explicitly | ||
| 77 | target/hppa: Set default NaN pattern explicitly | ||
| 78 | target/alpha: Set default NaN pattern explicitly | ||
| 79 | target/arm: Set default NaN pattern explicitly | ||
| 80 | target/loongarch: Set default NaN pattern explicitly | ||
| 81 | target/m68k: Set default NaN pattern explicitly | ||
| 82 | target/mips: Set default NaN pattern explicitly | ||
| 83 | target/openrisc: Set default NaN pattern explicitly | ||
| 84 | target/ppc: Set default NaN pattern explicitly | ||
| 85 | target/sh4: Set default NaN pattern explicitly | ||
| 86 | target/rx: Set default NaN pattern explicitly | ||
| 87 | target/s390x: Set default NaN pattern explicitly | ||
| 88 | target/sparc: Set default NaN pattern explicitly | ||
| 89 | target/xtensa: Set default NaN pattern explicitly | ||
| 90 | target/hexagon: Set default NaN pattern explicitly | ||
| 91 | target/riscv: Set default NaN pattern explicitly | ||
| 92 | target/tricore: Set default NaN pattern explicitly | ||
| 93 | fpu: Remove default handling for dnan_pattern | ||
| 54 | 94 | ||
| 55 | Eric Auger (3): | 95 | Richard Henderson (11): |
| 56 | linux headers: update against v5.4-rc1 | 96 | target/arm: Copy entire float_status in is_ebf |
| 57 | intc/arm_gic: Support IRQ injection for more than 256 vpus | 97 | softfloat: Inline pickNaNMulAdd |
| 58 | ARM: KVM: Check KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 for smp_cpus > 256 | 98 | softfloat: Use goto for default nan case in pick_nan_muladd |
| 99 | softfloat: Remove which from parts_pick_nan_muladd | ||
| 100 | softfloat: Pad array size in pick_nan_muladd | ||
| 101 | softfloat: Move propagateFloatx80NaN to softfloat.c | ||
| 102 | softfloat: Use parts_pick_nan in propagateFloatx80NaN | ||
| 103 | softfloat: Inline pickNaN | ||
| 104 | softfloat: Share code between parts_pick_nan cases | ||
| 105 | softfloat: Sink frac_cmp in parts_pick_nan until needed | ||
| 106 | softfloat: Replace WHICH with RET in parts_pick_nan | ||
| 59 | 107 | ||
| 60 | Joel Stanley (5): | 108 | Vikram Garhwal (1): |
| 61 | hw: aspeed_scu: Add AST2600 support | 109 | MAINTAINERS: Add correct email address for Vikram Garhwal |
| 62 | aspeed/sdmc: Add AST2600 support | ||
| 63 | hw: wdt_aspeed: Add AST2600 support | ||
| 64 | aspeed: Parameterise number of MACs | ||
| 65 | aspeed/soc: Add ASPEED Video stub | ||
| 66 | 110 | ||
| 67 | Peter Maydell (36): | 111 | MAINTAINERS | 4 +- |
| 68 | ptimer: Rename ptimer_init() to ptimer_init_with_bh() | 112 | include/fpu/softfloat-helpers.h | 38 +++- |
| 69 | ptimer: Provide new transaction-based API | 113 | include/fpu/softfloat-types.h | 89 +++++++- |
| 70 | tests/ptimer-test: Switch to transaction-based ptimer API | 114 | include/hw/net/imx_fec.h | 9 +- |
| 71 | hw/timer/arm_timer.c: Switch to transaction-based ptimer API | 115 | include/hw/net/lan9118_phy.h | 37 ++++ |
| 72 | hw/arm/musicpal.c: Switch to transaction-based ptimer API | 116 | include/hw/net/mii.h | 6 + |
| 73 | hw/timer/allwinner-a10-pit.c: Switch to transaction-based ptimer API | 117 | target/mips/fpu_helper.h | 20 ++ |
| 74 | hw/timer/arm_mptimer.c: Switch to transaction-based ptimer API | 118 | target/sparc/helper.h | 4 +- |
| 75 | hw/timer/cmsdk-apb-dualtimer.c: Switch to transaction-based ptimer API | 119 | fpu/softfloat.c | 19 ++ |
| 76 | hw/timer/cmsdk-apb-timer.c: Switch to transaction-based ptimer API | 120 | hw/net/imx_fec.c | 146 ++------------ |
| 77 | hw/timer/digic-timer.c: Switch to transaction-based ptimer API | 121 | hw/net/lan9118.c | 137 ++----------- |
| 78 | hw/timer/exynos4210_mct.c: Switch GFRC to transaction-based ptimer API | 122 | hw/net/lan9118_phy.c | 222 ++++++++++++++++++++ |
| 79 | hw/timer/exynos4210_mct.c: Switch LFRC to transaction-based ptimer API | 123 | linux-user/arm/nwfpe/fpa11.c | 5 + |
| 80 | hw/timer/exynos4210_mct.c: Switch ltick to transaction-based ptimer API | 124 | target/alpha/cpu.c | 2 + |
| 81 | hw/timer/exynos4210_pwm.c: Switch to transaction-based ptimer API | 125 | target/arm/cpu.c | 10 + |
| 82 | hw/timer/exynos4210_rtc.c: Switch 1Hz ptimer to transaction-based API | 126 | target/arm/tcg/vec_helper.c | 20 +- |
| 83 | hw/timer/exynos4210_rtc.c: Switch main ptimer to transaction-based API | 127 | target/hexagon/cpu.c | 2 + |
| 84 | hw/timer/imx_epit.c: Switch to transaction-based ptimer API | 128 | target/hppa/fpu_helper.c | 12 ++ |
| 85 | hw/timer/imx_gpt.c: Switch to transaction-based ptimer API | 129 | target/i386/tcg/fpu_helper.c | 12 ++ |
| 86 | hw/timer/mss-timerc: Switch to transaction-based ptimer API | 130 | target/loongarch/tcg/fpu_helper.c | 14 +- |
| 87 | hw/watchdog/cmsdk-apb-watchdog.c: Switch to transaction-based ptimer API | 131 | target/m68k/cpu.c | 14 +- |
| 88 | hw/net/lan9118.c: Switch to transaction-based ptimer API | 132 | target/m68k/fpu_helper.c | 6 +- |
| 89 | target/arm/arm-semi: Capture errno in softmmu version of set_swi_errno() | 133 | target/m68k/helper.c | 6 +- |
| 90 | target/arm/arm-semi: Always set some kind of errno for failed calls | 134 | target/microblaze/cpu.c | 2 + |
| 91 | target/arm/arm-semi: Correct comment about gdb syscall races | 135 | target/mips/msa.c | 10 + |
| 92 | target/arm/arm-semi: Make semihosting code hand out its own file descriptors | 136 | target/openrisc/cpu.c | 2 + |
| 93 | target/arm/arm-semi: Restrict use of TaskState* | 137 | target/ppc/cpu_init.c | 19 ++ |
| 94 | target/arm/arm-semi: Use set_swi_errno() in gdbstub callback functions | 138 | target/ppc/fpu_helper.c | 3 +- |
| 95 | target/arm/arm-semi: Factor out implementation of SYS_CLOSE | 139 | target/riscv/cpu.c | 2 + |
| 96 | target/arm/arm-semi: Factor out implementation of SYS_WRITE | 140 | target/rx/cpu.c | 2 + |
| 97 | target/arm/arm-semi: Factor out implementation of SYS_READ | 141 | target/s390x/cpu.c | 5 + |
| 98 | target/arm/arm-semi: Factor out implementation of SYS_ISTTY | 142 | target/sh4/cpu.c | 2 + |
| 99 | target/arm/arm-semi: Factor out implementation of SYS_SEEK | 143 | target/sparc/cpu.c | 6 + |
| 100 | target/arm/arm-semi: Factor out implementation of SYS_FLEN | 144 | target/sparc/fop_helper.c | 8 +- |
| 101 | target/arm/arm-semi: Implement support for semihosting feature detection | 145 | target/sparc/translate.c | 4 +- |
| 102 | target/arm/arm-semi: Implement SH_EXT_EXIT_EXTENDED extension | 146 | target/tricore/helper.c | 2 + |
| 103 | target/arm/arm-semi: Implement SH_EXT_STDOUT_STDERR extension | 147 | target/xtensa/cpu.c | 4 + |
| 104 | 148 | target/xtensa/fpu_helper.c | 3 +- | |
| 105 | Philippe Mathieu-Daudé (6): | 149 | tests/fp/fp-bench.c | 7 + |
| 106 | hw/arm/raspi: Use the IEC binary prefix definitions | 150 | tests/fp/fp-test-log2.c | 1 + |
| 107 | hw/arm/bcm2835_peripherals: Improve logging | 151 | tests/fp/fp-test.c | 7 + |
| 108 | hw/arm/bcm2835_peripherals: Name various address spaces | 152 | fpu/softfloat-parts.c.inc | 152 +++++++++++--- |
| 109 | hw/arm/bcm2835: Rename some definitions | 153 | fpu/softfloat-specialize.c.inc | 412 ++------------------------------------ |
| 110 | hw/arm/bcm2835: Add various unimplemented peripherals | 154 | .mailmap | 5 +- |
| 111 | hw/misc/bcm2835_mbox: Add trace events | 155 | hw/net/Kconfig | 5 + |
| 112 | 156 | hw/net/meson.build | 1 + | |
| 113 | Rashmica Gupta (1): | 157 | hw/net/trace-events | 10 +- |
| 114 | hw/gpio: Add in AST2600 specific implementation | 158 | 47 files changed, 778 insertions(+), 730 deletions(-) |
| 115 | 159 | create mode 100644 include/hw/net/lan9118_phy.h | |
| 116 | hw/arm/Makefile.objs | 2 +- | 160 | create mode 100644 hw/net/lan9118_phy.c |
| 117 | hw/sd/Makefile.objs | 1 + | ||
| 118 | include/hw/arm/aspeed.h | 1 + | ||
| 119 | include/hw/arm/aspeed_soc.h | 29 +- | ||
| 120 | include/hw/arm/bcm2835_peripherals.h | 15 + | ||
| 121 | include/hw/arm/raspi_platform.h | 24 +- | ||
| 122 | include/hw/i2c/aspeed_i2c.h | 20 +- | ||
| 123 | include/hw/misc/aspeed_scu.h | 7 +- | ||
| 124 | include/hw/misc/aspeed_sdmc.h | 20 +- | ||
| 125 | include/hw/net/ftgmac100.h | 17 + | ||
| 126 | include/hw/ptimer.h | 83 ++- | ||
| 127 | include/hw/sd/aspeed_sdhci.h | 34 ++ | ||
| 128 | include/hw/ssi/aspeed_smc.h | 4 + | ||
| 129 | include/hw/timer/aspeed_timer.h | 18 + | ||
| 130 | include/hw/timer/mss-timer.h | 1 - | ||
| 131 | include/hw/watchdog/wdt_aspeed.h | 19 +- | ||
| 132 | include/standard-headers/asm-x86/bootparam.h | 2 + | ||
| 133 | include/standard-headers/asm-x86/kvm_para.h | 1 + | ||
| 134 | include/standard-headers/linux/ethtool.h | 24 + | ||
| 135 | include/standard-headers/linux/pci_regs.h | 19 +- | ||
| 136 | include/standard-headers/linux/virtio_fs.h | 19 + | ||
| 137 | include/standard-headers/linux/virtio_ids.h | 2 + | ||
| 138 | include/standard-headers/linux/virtio_iommu.h | 165 ++++++ | ||
| 139 | include/standard-headers/linux/virtio_pmem.h | 6 +- | ||
| 140 | linux-headers/asm-arm/kvm.h | 16 +- | ||
| 141 | linux-headers/asm-arm/unistd-common.h | 2 + | ||
| 142 | linux-headers/asm-arm64/kvm.h | 21 +- | ||
| 143 | linux-headers/asm-generic/mman-common.h | 18 +- | ||
| 144 | linux-headers/asm-generic/mman.h | 10 +- | ||
| 145 | linux-headers/asm-generic/unistd.h | 10 +- | ||
| 146 | linux-headers/asm-mips/mman.h | 3 + | ||
| 147 | linux-headers/asm-mips/unistd_n32.h | 1 + | ||
| 148 | linux-headers/asm-mips/unistd_n64.h | 1 + | ||
| 149 | linux-headers/asm-mips/unistd_o32.h | 1 + | ||
| 150 | linux-headers/asm-powerpc/mman.h | 6 +- | ||
| 151 | linux-headers/asm-powerpc/unistd_32.h | 2 + | ||
| 152 | linux-headers/asm-powerpc/unistd_64.h | 2 + | ||
| 153 | linux-headers/asm-s390/kvm.h | 6 + | ||
| 154 | linux-headers/asm-s390/unistd_32.h | 2 + | ||
| 155 | linux-headers/asm-s390/unistd_64.h | 2 + | ||
| 156 | linux-headers/asm-x86/kvm.h | 28 +- | ||
| 157 | linux-headers/asm-x86/unistd.h | 2 +- | ||
| 158 | linux-headers/asm-x86/unistd_32.h | 2 + | ||
| 159 | linux-headers/asm-x86/unistd_64.h | 2 + | ||
| 160 | linux-headers/asm-x86/unistd_x32.h | 2 + | ||
| 161 | linux-headers/linux/kvm.h | 12 +- | ||
| 162 | linux-headers/linux/psp-sev.h | 5 +- | ||
| 163 | linux-headers/linux/vfio.h | 71 ++- | ||
| 164 | target/arm/kvm_arm.h | 1 + | ||
| 165 | hw/arm/aspeed.c | 42 +- | ||
| 166 | hw/arm/aspeed_ast2600.c | 523 +++++++++++++++++++ | ||
| 167 | hw/arm/aspeed_soc.c | 199 +++++--- | ||
| 168 | hw/arm/bcm2835_peripherals.c | 38 +- | ||
| 169 | hw/arm/bcm2836.c | 2 +- | ||
| 170 | hw/arm/musicpal.c | 16 +- | ||
| 171 | hw/arm/raspi.c | 4 +- | ||
| 172 | hw/block/m25p80.c | 1 + | ||
| 173 | hw/char/bcm2835_aux.c | 5 +- | ||
| 174 | hw/core/ptimer.c | 154 +++++- | ||
| 175 | hw/display/bcm2835_fb.c | 2 +- | ||
| 176 | hw/dma/bcm2835_dma.c | 10 +- | ||
| 177 | hw/dma/xilinx_axidma.c | 2 +- | ||
| 178 | hw/gpio/aspeed_gpio.c | 142 +++++- | ||
| 179 | hw/i2c/aspeed_i2c.c | 106 +++- | ||
| 180 | hw/intc/arm_gic_kvm.c | 7 +- | ||
| 181 | hw/intc/bcm2836_control.c | 7 +- | ||
| 182 | hw/m68k/mcf5206.c | 2 +- | ||
| 183 | hw/m68k/mcf5208.c | 2 +- | ||
| 184 | hw/misc/aspeed_scu.c | 194 ++++++- | ||
| 185 | hw/misc/aspeed_sdmc.c | 250 ++++++--- | ||
| 186 | hw/misc/bcm2835_mbox.c | 14 +- | ||
| 187 | hw/misc/bcm2835_property.c | 20 +- | ||
| 188 | hw/net/fsl_etsec/etsec.c | 2 +- | ||
| 189 | hw/net/ftgmac100.c | 162 ++++++ | ||
| 190 | hw/net/lan9118.c | 11 +- | ||
| 191 | hw/sd/aspeed_sdhci.c | 198 ++++++++ | ||
| 192 | hw/ssi/aspeed_smc.c | 177 ++++++- | ||
| 193 | hw/timer/allwinner-a10-pit.c | 12 +- | ||
| 194 | hw/timer/altera_timer.c | 2 +- | ||
| 195 | hw/timer/arm_mptimer.c | 18 +- | ||
| 196 | hw/timer/arm_timer.c | 16 +- | ||
| 197 | hw/timer/aspeed_timer.c | 213 +++++++- | ||
| 198 | hw/timer/cmsdk-apb-dualtimer.c | 14 +- | ||
| 199 | hw/timer/cmsdk-apb-timer.c | 15 +- | ||
| 200 | hw/timer/digic-timer.c | 16 +- | ||
| 201 | hw/timer/etraxfs_timer.c | 6 +- | ||
| 202 | hw/timer/exynos4210_mct.c | 107 +++- | ||
| 203 | hw/timer/exynos4210_pwm.c | 17 +- | ||
| 204 | hw/timer/exynos4210_rtc.c | 22 +- | ||
| 205 | hw/timer/grlib_gptimer.c | 2 +- | ||
| 206 | hw/timer/imx_epit.c | 32 +- | ||
| 207 | hw/timer/imx_gpt.c | 21 +- | ||
| 208 | hw/timer/lm32_timer.c | 2 +- | ||
| 209 | hw/timer/milkymist-sysctl.c | 4 +- | ||
| 210 | hw/timer/mss-timer.c | 11 +- | ||
| 211 | hw/timer/puv3_ost.c | 2 +- | ||
| 212 | hw/timer/sh_timer.c | 2 +- | ||
| 213 | hw/timer/slavio_timer.c | 2 +- | ||
| 214 | hw/timer/xilinx_timer.c | 2 +- | ||
| 215 | hw/watchdog/cmsdk-apb-watchdog.c | 13 +- | ||
| 216 | hw/watchdog/wdt_aspeed.c | 153 +++--- | ||
| 217 | target/arm/arm-semi.c | 707 +++++++++++++++++++++----- | ||
| 218 | target/arm/cpu.c | 10 +- | ||
| 219 | target/arm/kvm.c | 22 +- | ||
| 220 | tests/ptimer-test.c | 106 +++- | ||
| 221 | hw/misc/trace-events | 6 + | ||
| 222 | 106 files changed, 3958 insertions(+), 650 deletions(-) | ||
| 223 | create mode 100644 include/hw/sd/aspeed_sdhci.h | ||
| 224 | create mode 100644 include/standard-headers/linux/virtio_fs.h | ||
| 225 | create mode 100644 include/standard-headers/linux/virtio_iommu.h | ||
| 226 | create mode 100644 hw/arm/aspeed_ast2600.c | ||
| 227 | create mode 100644 hw/sd/aspeed_sdhci.c | ||
| 228 | diff view generated by jsdifflib |
| 1 | From: Eddie James <eajames@linux.ibm.com> | 1 | From: Bernhard Beschow <shentey@gmail.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The Aspeed SOCs have two SD/MMC controllers. Add a device that | 3 | A very similar implementation of the same device exists in imx_fec. Prepare for |
| 4 | encapsulates both of these controllers and models the Aspeed-specific | 4 | a common implementation by extracting a device model into its own files. |
| 5 | registers and behavior. | ||
| 6 | 5 | ||
| 7 | Tested by reading from mmcblk0 in Linux: | 6 | Some migration state has been moved into the new device model which breaks |
| 8 | qemu-system-arm -machine romulus-bmc -nographic \ | 7 | migration compatibility for the following machines: |
| 9 | -drive file=flash-romulus,format=raw,if=mtd \ | 8 | * smdkc210 |
| 10 | -device sd-card,drive=sd0 -drive file=_tmp/kernel,format=raw,if=sd,id=sd0 | 9 | * realview-* |
| 10 | * vexpress-* | ||
| 11 | * kzm | ||
| 12 | * mps2-* | ||
| 11 | 13 | ||
| 12 | Signed-off-by: Eddie James <eajames@linux.ibm.com> | 14 | While breaking migration ABI, fix the size of the MII registers to be 16 bit, |
| 13 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 15 | as defined by IEEE 802.3u. |
| 14 | Reviewed-by: Joel Stanley <joel@jms.id.au> | 16 | |
| 15 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 17 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> |
| 16 | Message-id: 20190925143248.10000-3-clg@kaod.org | 18 | Tested-by: Guenter Roeck <linux@roeck-us.net> |
| 17 | [clg: - changed the controller MMIO window size to 0x1000 | 19 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 18 | - moved the MMIO mapping of the SDHCI slots at the SoC level | 20 | Message-id: 20241102125724.532843-2-shentey@gmail.com |
| 19 | - merged code to add SD drives on the SD buses at the machine level ] | ||
| 20 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 22 | --- | 22 | --- |
| 23 | hw/sd/Makefile.objs | 1 + | 23 | include/hw/net/lan9118_phy.h | 37 ++++++++ |
| 24 | include/hw/arm/aspeed_soc.h | 3 + | 24 | hw/net/lan9118.c | 137 +++++----------------------- |
| 25 | include/hw/sd/aspeed_sdhci.h | 34 ++++++ | 25 | hw/net/lan9118_phy.c | 169 +++++++++++++++++++++++++++++++++++ |
| 26 | hw/arm/aspeed.c | 15 ++- | 26 | hw/net/Kconfig | 4 + |
| 27 | hw/arm/aspeed_soc.c | 23 ++++ | 27 | hw/net/meson.build | 1 + |
| 28 | hw/sd/aspeed_sdhci.c | 198 +++++++++++++++++++++++++++++++++++ | 28 | 5 files changed, 233 insertions(+), 115 deletions(-) |
| 29 | 6 files changed, 273 insertions(+), 1 deletion(-) | 29 | create mode 100644 include/hw/net/lan9118_phy.h |
| 30 | create mode 100644 include/hw/sd/aspeed_sdhci.h | 30 | create mode 100644 hw/net/lan9118_phy.c |
| 31 | create mode 100644 hw/sd/aspeed_sdhci.c | ||
| 32 | 31 | ||
| 33 | diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs | 32 | diff --git a/include/hw/net/lan9118_phy.h b/include/hw/net/lan9118_phy.h |
| 34 | index XXXXXXX..XXXXXXX 100644 | ||
| 35 | --- a/hw/sd/Makefile.objs | ||
| 36 | +++ b/hw/sd/Makefile.objs | ||
| 37 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MILKYMIST) += milkymist-memcard.o | ||
| 38 | obj-$(CONFIG_OMAP) += omap_mmc.o | ||
| 39 | obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o | ||
| 40 | obj-$(CONFIG_RASPI) += bcm2835_sdhost.o | ||
| 41 | +obj-$(CONFIG_ASPEED_SOC) += aspeed_sdhci.o | ||
| 42 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | ||
| 43 | index XXXXXXX..XXXXXXX 100644 | ||
| 44 | --- a/include/hw/arm/aspeed_soc.h | ||
| 45 | +++ b/include/hw/arm/aspeed_soc.h | ||
| 46 | @@ -XXX,XX +XXX,XX @@ | ||
| 47 | #include "hw/net/ftgmac100.h" | ||
| 48 | #include "target/arm/cpu.h" | ||
| 49 | #include "hw/gpio/aspeed_gpio.h" | ||
| 50 | +#include "hw/sd/aspeed_sdhci.h" | ||
| 51 | |||
| 52 | #define ASPEED_SPIS_NUM 2 | ||
| 53 | #define ASPEED_WDTS_NUM 3 | ||
| 54 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState { | ||
| 55 | AspeedWDTState wdt[ASPEED_WDTS_NUM]; | ||
| 56 | FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; | ||
| 57 | AspeedGPIOState gpio; | ||
| 58 | + AspeedSDHCIState sdhci; | ||
| 59 | } AspeedSoCState; | ||
| 60 | |||
| 61 | #define TYPE_ASPEED_SOC "aspeed-soc" | ||
| 62 | @@ -XXX,XX +XXX,XX @@ enum { | ||
| 63 | ASPEED_SCU, | ||
| 64 | ASPEED_ADC, | ||
| 65 | ASPEED_SRAM, | ||
| 66 | + ASPEED_SDHCI, | ||
| 67 | ASPEED_GPIO, | ||
| 68 | ASPEED_RTC, | ||
| 69 | ASPEED_TIMER1, | ||
| 70 | diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h | ||
| 71 | new file mode 100644 | 33 | new file mode 100644 |
| 72 | index XXXXXXX..XXXXXXX | 34 | index XXXXXXX..XXXXXXX |
| 73 | --- /dev/null | 35 | --- /dev/null |
| 74 | +++ b/include/hw/sd/aspeed_sdhci.h | 36 | +++ b/include/hw/net/lan9118_phy.h |
| 75 | @@ -XXX,XX +XXX,XX @@ | 37 | @@ -XXX,XX +XXX,XX @@ |
| 76 | +/* | 38 | +/* |
| 77 | + * Aspeed SD Host Controller | 39 | + * SMSC LAN9118 PHY emulation |
| 78 | + * Eddie James <eajames@linux.ibm.com> | ||
| 79 | + * | 40 | + * |
| 80 | + * Copyright (C) 2019 IBM Corp | 41 | + * Copyright (c) 2009 CodeSourcery, LLC. |
| 81 | + * SPDX-License-Identifer: GPL-2.0-or-later | 42 | + * Written by Paul Brook |
| 43 | + * | ||
| 44 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
| 45 | + * See the COPYING file in the top-level directory. | ||
| 82 | + */ | 46 | + */ |
| 83 | + | 47 | + |
| 84 | +#ifndef ASPEED_SDHCI_H | 48 | +#ifndef HW_NET_LAN9118_PHY_H |
| 85 | +#define ASPEED_SDHCI_H | 49 | +#define HW_NET_LAN9118_PHY_H |
| 86 | + | 50 | + |
| 87 | +#include "hw/sd/sdhci.h" | 51 | +#include "qom/object.h" |
| 88 | + | 52 | +#include "hw/sysbus.h" |
| 89 | +#define TYPE_ASPEED_SDHCI "aspeed.sdhci" | 53 | + |
| 90 | +#define ASPEED_SDHCI(obj) OBJECT_CHECK(AspeedSDHCIState, (obj), \ | 54 | +#define TYPE_LAN9118_PHY "lan9118-phy" |
| 91 | + TYPE_ASPEED_SDHCI) | 55 | +OBJECT_DECLARE_SIMPLE_TYPE(Lan9118PhyState, LAN9118_PHY) |
| 92 | + | 56 | + |
| 93 | +#define ASPEED_SDHCI_CAPABILITIES 0x01E80080 | 57 | +typedef struct Lan9118PhyState { |
| 94 | +#define ASPEED_SDHCI_NUM_SLOTS 2 | 58 | + SysBusDevice parent_obj; |
| 95 | +#define ASPEED_SDHCI_NUM_REGS (ASPEED_SDHCI_REG_SIZE / sizeof(uint32_t)) | 59 | + |
| 96 | +#define ASPEED_SDHCI_REG_SIZE 0x100 | 60 | + uint16_t status; |
| 97 | + | 61 | + uint16_t control; |
| 98 | +typedef struct AspeedSDHCIState { | 62 | + uint16_t advertise; |
| 99 | + SysBusDevice parent; | 63 | + uint16_t ints; |
| 100 | + | 64 | + uint16_t int_mask; |
| 101 | + SDHCIState slots[ASPEED_SDHCI_NUM_SLOTS]; | ||
| 102 | + | ||
| 103 | + MemoryRegion iomem; | ||
| 104 | + qemu_irq irq; | 65 | + qemu_irq irq; |
| 105 | + | 66 | + bool link_down; |
| 106 | + uint32_t regs[ASPEED_SDHCI_NUM_REGS]; | 67 | +} Lan9118PhyState; |
| 107 | +} AspeedSDHCIState; | 68 | + |
| 108 | + | 69 | +void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down); |
| 109 | +#endif /* ASPEED_SDHCI_H */ | 70 | +void lan9118_phy_reset(Lan9118PhyState *s); |
| 110 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | 71 | +uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg); |
| 72 | +void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val); | ||
| 73 | + | ||
| 74 | +#endif | ||
| 75 | diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c | ||
| 111 | index XXXXXXX..XXXXXXX 100644 | 76 | index XXXXXXX..XXXXXXX 100644 |
| 112 | --- a/hw/arm/aspeed.c | 77 | --- a/hw/net/lan9118.c |
| 113 | +++ b/hw/arm/aspeed.c | 78 | +++ b/hw/net/lan9118.c |
| 114 | @@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine, | 79 | @@ -XXX,XX +XXX,XX @@ |
| 115 | AspeedSoCClass *sc; | 80 | #include "net/net.h" |
| 116 | DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); | 81 | #include "net/eth.h" |
| 117 | ram_addr_t max_ram_size; | 82 | #include "hw/irq.h" |
| 118 | + int i; | 83 | +#include "hw/net/lan9118_phy.h" |
| 119 | 84 | #include "hw/net/lan9118.h" | |
| 120 | bmc = g_new0(AspeedBoardState, 1); | 85 | #include "hw/ptimer.h" |
| 121 | 86 | #include "hw/qdev-properties.h" | |
| 122 | @@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine, | 87 | @@ -XXX,XX +XXX,XX @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0) |
| 123 | cfg->i2c_init(bmc); | 88 | #define MAC_CR_RXEN 0x00000004 |
| 89 | #define MAC_CR_RESERVED 0x7f404213 | ||
| 90 | |||
| 91 | -#define PHY_INT_ENERGYON 0x80 | ||
| 92 | -#define PHY_INT_AUTONEG_COMPLETE 0x40 | ||
| 93 | -#define PHY_INT_FAULT 0x20 | ||
| 94 | -#define PHY_INT_DOWN 0x10 | ||
| 95 | -#define PHY_INT_AUTONEG_LP 0x08 | ||
| 96 | -#define PHY_INT_PARFAULT 0x04 | ||
| 97 | -#define PHY_INT_AUTONEG_PAGE 0x02 | ||
| 98 | - | ||
| 99 | #define GPT_TIMER_EN 0x20000000 | ||
| 100 | |||
| 101 | /* | ||
| 102 | @@ -XXX,XX +XXX,XX @@ struct lan9118_state { | ||
| 103 | uint32_t mac_mii_data; | ||
| 104 | uint32_t mac_flow; | ||
| 105 | |||
| 106 | - uint32_t phy_status; | ||
| 107 | - uint32_t phy_control; | ||
| 108 | - uint32_t phy_advertise; | ||
| 109 | - uint32_t phy_int; | ||
| 110 | - uint32_t phy_int_mask; | ||
| 111 | + Lan9118PhyState mii; | ||
| 112 | + IRQState mii_irq; | ||
| 113 | |||
| 114 | int32_t eeprom_writable; | ||
| 115 | uint8_t eeprom[128]; | ||
| 116 | @@ -XXX,XX +XXX,XX @@ struct lan9118_state { | ||
| 117 | |||
| 118 | static const VMStateDescription vmstate_lan9118 = { | ||
| 119 | .name = "lan9118", | ||
| 120 | - .version_id = 2, | ||
| 121 | - .minimum_version_id = 1, | ||
| 122 | + .version_id = 3, | ||
| 123 | + .minimum_version_id = 3, | ||
| 124 | .fields = (const VMStateField[]) { | ||
| 125 | VMSTATE_PTIMER(timer, lan9118_state), | ||
| 126 | VMSTATE_UINT32(irq_cfg, lan9118_state), | ||
| 127 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118 = { | ||
| 128 | VMSTATE_UINT32(mac_mii_acc, lan9118_state), | ||
| 129 | VMSTATE_UINT32(mac_mii_data, lan9118_state), | ||
| 130 | VMSTATE_UINT32(mac_flow, lan9118_state), | ||
| 131 | - VMSTATE_UINT32(phy_status, lan9118_state), | ||
| 132 | - VMSTATE_UINT32(phy_control, lan9118_state), | ||
| 133 | - VMSTATE_UINT32(phy_advertise, lan9118_state), | ||
| 134 | - VMSTATE_UINT32(phy_int, lan9118_state), | ||
| 135 | - VMSTATE_UINT32(phy_int_mask, lan9118_state), | ||
| 136 | VMSTATE_INT32(eeprom_writable, lan9118_state), | ||
| 137 | VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128), | ||
| 138 | VMSTATE_INT32(tx_fifo_size, lan9118_state), | ||
| 139 | @@ -XXX,XX +XXX,XX @@ static void lan9118_reload_eeprom(lan9118_state *s) | ||
| 140 | lan9118_mac_changed(s); | ||
| 141 | } | ||
| 142 | |||
| 143 | -static void phy_update_irq(lan9118_state *s) | ||
| 144 | +static void lan9118_update_irq(void *opaque, int n, int level) | ||
| 145 | { | ||
| 146 | - if (s->phy_int & s->phy_int_mask) { | ||
| 147 | + lan9118_state *s = opaque; | ||
| 148 | + | ||
| 149 | + if (level) { | ||
| 150 | s->int_sts |= PHY_INT; | ||
| 151 | } else { | ||
| 152 | s->int_sts &= ~PHY_INT; | ||
| 153 | @@ -XXX,XX +XXX,XX @@ static void phy_update_irq(lan9118_state *s) | ||
| 154 | lan9118_update(s); | ||
| 155 | } | ||
| 156 | |||
| 157 | -static void phy_update_link(lan9118_state *s) | ||
| 158 | -{ | ||
| 159 | - /* Autonegotiation status mirrors link status. */ | ||
| 160 | - if (qemu_get_queue(s->nic)->link_down) { | ||
| 161 | - s->phy_status &= ~0x0024; | ||
| 162 | - s->phy_int |= PHY_INT_DOWN; | ||
| 163 | - } else { | ||
| 164 | - s->phy_status |= 0x0024; | ||
| 165 | - s->phy_int |= PHY_INT_ENERGYON; | ||
| 166 | - s->phy_int |= PHY_INT_AUTONEG_COMPLETE; | ||
| 167 | - } | ||
| 168 | - phy_update_irq(s); | ||
| 169 | -} | ||
| 170 | - | ||
| 171 | static void lan9118_set_link(NetClientState *nc) | ||
| 172 | { | ||
| 173 | - phy_update_link(qemu_get_nic_opaque(nc)); | ||
| 174 | -} | ||
| 175 | - | ||
| 176 | -static void phy_reset(lan9118_state *s) | ||
| 177 | -{ | ||
| 178 | - s->phy_status = 0x7809; | ||
| 179 | - s->phy_control = 0x3000; | ||
| 180 | - s->phy_advertise = 0x01e1; | ||
| 181 | - s->phy_int_mask = 0; | ||
| 182 | - s->phy_int = 0; | ||
| 183 | - phy_update_link(s); | ||
| 184 | + lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii, | ||
| 185 | + nc->link_down); | ||
| 186 | } | ||
| 187 | |||
| 188 | static void lan9118_reset(DeviceState *d) | ||
| 189 | @@ -XXX,XX +XXX,XX @@ static void lan9118_reset(DeviceState *d) | ||
| 190 | s->read_word_n = 0; | ||
| 191 | s->write_word_n = 0; | ||
| 192 | |||
| 193 | - phy_reset(s); | ||
| 194 | - | ||
| 195 | s->eeprom_writable = 0; | ||
| 196 | lan9118_reload_eeprom(s); | ||
| 197 | } | ||
| 198 | @@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s) | ||
| 199 | uint32_t status; | ||
| 200 | |||
| 201 | /* FIXME: Honor TX disable, and allow queueing of packets. */ | ||
| 202 | - if (s->phy_control & 0x4000) { | ||
| 203 | + if (s->mii.control & 0x4000) { | ||
| 204 | /* This assumes the receive routine doesn't touch the VLANClient. */ | ||
| 205 | qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len); | ||
| 206 | } else { | ||
| 207 | @@ -XXX,XX +XXX,XX @@ static void tx_fifo_push(lan9118_state *s, uint32_t val) | ||
| 124 | } | 208 | } |
| 125 | |||
| 126 | + for (i = 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) { | ||
| 127 | + SDHCIState *sdhci = &bmc->soc.sdhci.slots[i]; | ||
| 128 | + DriveInfo *dinfo = drive_get_next(IF_SD); | ||
| 129 | + BlockBackend *blk; | ||
| 130 | + DeviceState *card; | ||
| 131 | + | ||
| 132 | + blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; | ||
| 133 | + card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), | ||
| 134 | + TYPE_SD_CARD); | ||
| 135 | + qdev_prop_set_drive(card, "drive", blk, &error_fatal); | ||
| 136 | + object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); | ||
| 137 | + } | ||
| 138 | + | ||
| 139 | arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); | ||
| 140 | } | 209 | } |
| 141 | 210 | ||
| 142 | @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data) | 211 | -static uint32_t do_phy_read(lan9118_state *s, int reg) |
| 143 | mc->desc = board->desc; | 212 | -{ |
| 144 | mc->init = aspeed_machine_init; | 213 | - uint32_t val; |
| 145 | mc->max_cpus = ASPEED_CPUS_NUM; | 214 | - |
| 146 | - mc->no_sdcard = 1; | 215 | - switch (reg) { |
| 147 | mc->no_floppy = 1; | 216 | - case 0: /* Basic Control */ |
| 148 | mc->no_cdrom = 1; | 217 | - return s->phy_control; |
| 149 | mc->no_parallel = 1; | 218 | - case 1: /* Basic Status */ |
| 150 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | 219 | - return s->phy_status; |
| 151 | index XXXXXXX..XXXXXXX 100644 | 220 | - case 2: /* ID1 */ |
| 152 | --- a/hw/arm/aspeed_soc.c | 221 | - return 0x0007; |
| 153 | +++ b/hw/arm/aspeed_soc.c | 222 | - case 3: /* ID2 */ |
| 154 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2400_memmap[] = { | 223 | - return 0xc0d1; |
| 155 | [ASPEED_XDMA] = 0x1E6E7000, | 224 | - case 4: /* Auto-neg advertisement */ |
| 156 | [ASPEED_ADC] = 0x1E6E9000, | 225 | - return s->phy_advertise; |
| 157 | [ASPEED_SRAM] = 0x1E720000, | 226 | - case 5: /* Auto-neg Link Partner Ability */ |
| 158 | + [ASPEED_SDHCI] = 0x1E740000, | 227 | - return 0x0f71; |
| 159 | [ASPEED_GPIO] = 0x1E780000, | 228 | - case 6: /* Auto-neg Expansion */ |
| 160 | [ASPEED_RTC] = 0x1E781000, | 229 | - return 1; |
| 161 | [ASPEED_TIMER1] = 0x1E782000, | 230 | - /* TODO 17, 18, 27, 29, 30, 31 */ |
| 162 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2500_memmap[] = { | 231 | - case 29: /* Interrupt source. */ |
| 163 | [ASPEED_XDMA] = 0x1E6E7000, | 232 | - val = s->phy_int; |
| 164 | [ASPEED_ADC] = 0x1E6E9000, | 233 | - s->phy_int = 0; |
| 165 | [ASPEED_SRAM] = 0x1E720000, | 234 | - phy_update_irq(s); |
| 166 | + [ASPEED_SDHCI] = 0x1E740000, | 235 | - return val; |
| 167 | [ASPEED_GPIO] = 0x1E780000, | 236 | - case 30: /* Interrupt mask */ |
| 168 | [ASPEED_RTC] = 0x1E781000, | 237 | - return s->phy_int_mask; |
| 169 | [ASPEED_TIMER1] = 0x1E782000, | 238 | - default: |
| 170 | @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2400_irqmap[] = { | 239 | - qemu_log_mask(LOG_GUEST_ERROR, |
| 171 | [ASPEED_ETH1] = 2, | 240 | - "do_phy_read: PHY read reg %d\n", reg); |
| 172 | [ASPEED_ETH2] = 3, | 241 | - return 0; |
| 173 | [ASPEED_XDMA] = 6, | 242 | - } |
| 174 | + [ASPEED_SDHCI] = 26, | 243 | -} |
| 175 | }; | 244 | - |
| 176 | 245 | -static void do_phy_write(lan9118_state *s, int reg, uint32_t val) | |
| 177 | #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap | 246 | -{ |
| 178 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | 247 | - switch (reg) { |
| 179 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); | 248 | - case 0: /* Basic Control */ |
| 180 | sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio), | 249 | - if (val & 0x8000) { |
| 181 | typename); | 250 | - phy_reset(s); |
| 182 | + | 251 | - break; |
| 183 | + sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), | 252 | - } |
| 184 | + TYPE_ASPEED_SDHCI); | 253 | - s->phy_control = val & 0x7980; |
| 185 | + | 254 | - /* Complete autonegotiation immediately. */ |
| 186 | + /* Init sd card slot class here so that they're under the correct parent */ | 255 | - if (val & 0x1000) { |
| 187 | + for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | 256 | - s->phy_status |= 0x0020; |
| 188 | + sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), | 257 | - } |
| 189 | + sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); | 258 | - break; |
| 190 | + } | 259 | - case 4: /* Auto-neg advertisement */ |
| 191 | } | 260 | - s->phy_advertise = (val & 0x2d7f) | 0x80; |
| 192 | 261 | - break; | |
| 193 | static void aspeed_soc_realize(DeviceState *dev, Error **errp) | 262 | - /* TODO 17, 18, 27, 31 */ |
| 194 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | 263 | - case 30: /* Interrupt mask */ |
| 195 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->info->memmap[ASPEED_GPIO]); | 264 | - s->phy_int_mask = val & 0xff; |
| 196 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, | 265 | - phy_update_irq(s); |
| 197 | aspeed_soc_get_irq(s, ASPEED_GPIO)); | 266 | - break; |
| 198 | + | 267 | - default: |
| 199 | + /* SDHCI */ | 268 | - qemu_log_mask(LOG_GUEST_ERROR, |
| 200 | + object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err); | 269 | - "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val); |
| 201 | + if (err) { | 270 | - } |
| 202 | + error_propagate(errp, err); | 271 | -} |
| 272 | - | ||
| 273 | static void do_mac_write(lan9118_state *s, int reg, uint32_t val) | ||
| 274 | { | ||
| 275 | switch (reg) { | ||
| 276 | @@ -XXX,XX +XXX,XX @@ static void do_mac_write(lan9118_state *s, int reg, uint32_t val) | ||
| 277 | if (val & 2) { | ||
| 278 | DPRINTF("PHY write %d = 0x%04x\n", | ||
| 279 | (val >> 6) & 0x1f, s->mac_mii_data); | ||
| 280 | - do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data); | ||
| 281 | + lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data); | ||
| 282 | } else { | ||
| 283 | - s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f); | ||
| 284 | + s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f); | ||
| 285 | DPRINTF("PHY read %d = 0x%04x\n", | ||
| 286 | (val >> 6) & 0x1f, s->mac_mii_data); | ||
| 287 | } | ||
| 288 | @@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset, | ||
| 289 | break; | ||
| 290 | case CSR_PMT_CTRL: | ||
| 291 | if (val & 0x400) { | ||
| 292 | - phy_reset(s); | ||
| 293 | + lan9118_phy_reset(&s->mii); | ||
| 294 | } | ||
| 295 | s->pmt_ctrl &= ~0x34e; | ||
| 296 | s->pmt_ctrl |= (val & 0x34e); | ||
| 297 | @@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp) | ||
| 298 | const MemoryRegionOps *mem_ops = | ||
| 299 | s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops; | ||
| 300 | |||
| 301 | + qemu_init_irq(&s->mii_irq, lan9118_update_irq, s, 0); | ||
| 302 | + object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY); | ||
| 303 | + if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) { | ||
| 203 | + return; | 304 | + return; |
| 204 | + } | 305 | + } |
| 205 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, | 306 | + qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq); |
| 206 | + sc->info->memmap[ASPEED_SDHCI]); | 307 | + |
| 207 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, | 308 | memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s, |
| 208 | + aspeed_soc_get_irq(s, ASPEED_SDHCI)); | 309 | "lan9118-mmio", 0x100); |
| 209 | } | 310 | sysbus_init_mmio(sbd, &s->mmio); |
| 210 | static Property aspeed_soc_properties[] = { | 311 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c |
| 211 | DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0), | ||
| 212 | diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c | ||
| 213 | new file mode 100644 | 312 | new file mode 100644 |
| 214 | index XXXXXXX..XXXXXXX | 313 | index XXXXXXX..XXXXXXX |
| 215 | --- /dev/null | 314 | --- /dev/null |
| 216 | +++ b/hw/sd/aspeed_sdhci.c | 315 | +++ b/hw/net/lan9118_phy.c |
| 217 | @@ -XXX,XX +XXX,XX @@ | 316 | @@ -XXX,XX +XXX,XX @@ |
| 218 | +/* | 317 | +/* |
| 219 | + * Aspeed SD Host Controller | 318 | + * SMSC LAN9118 PHY emulation |
| 220 | + * Eddie James <eajames@linux.ibm.com> | ||
| 221 | + * | 319 | + * |
| 222 | + * Copyright (C) 2019 IBM Corp | 320 | + * Copyright (c) 2009 CodeSourcery, LLC. |
| 223 | + * SPDX-License-Identifer: GPL-2.0-or-later | 321 | + * Written by Paul Brook |
| 322 | + * | ||
| 323 | + * This code is licensed under the GNU GPL v2 | ||
| 324 | + * | ||
| 325 | + * Contributions after 2012-01-13 are licensed under the terms of the | ||
| 326 | + * GNU GPL, version 2 or (at your option) any later version. | ||
| 224 | + */ | 327 | + */ |
| 225 | + | 328 | + |
| 226 | +#include "qemu/osdep.h" | 329 | +#include "qemu/osdep.h" |
| 330 | +#include "hw/net/lan9118_phy.h" | ||
| 331 | +#include "hw/irq.h" | ||
| 332 | +#include "hw/resettable.h" | ||
| 333 | +#include "migration/vmstate.h" | ||
| 227 | +#include "qemu/log.h" | 334 | +#include "qemu/log.h" |
| 228 | +#include "qemu/error-report.h" | 335 | + |
| 229 | +#include "hw/sd/aspeed_sdhci.h" | 336 | +#define PHY_INT_ENERGYON (1 << 7) |
| 230 | +#include "qapi/error.h" | 337 | +#define PHY_INT_AUTONEG_COMPLETE (1 << 6) |
| 231 | +#include "hw/irq.h" | 338 | +#define PHY_INT_FAULT (1 << 5) |
| 232 | +#include "migration/vmstate.h" | 339 | +#define PHY_INT_DOWN (1 << 4) |
| 233 | + | 340 | +#define PHY_INT_AUTONEG_LP (1 << 3) |
| 234 | +#define ASPEED_SDHCI_INFO 0x00 | 341 | +#define PHY_INT_PARFAULT (1 << 2) |
| 235 | +#define ASPEED_SDHCI_INFO_RESET 0x00030000 | 342 | +#define PHY_INT_AUTONEG_PAGE (1 << 1) |
| 236 | +#define ASPEED_SDHCI_DEBOUNCE 0x04 | 343 | + |
| 237 | +#define ASPEED_SDHCI_DEBOUNCE_RESET 0x00000005 | 344 | +static void lan9118_phy_update_irq(Lan9118PhyState *s) |
| 238 | +#define ASPEED_SDHCI_BUS 0x08 | 345 | +{ |
| 239 | +#define ASPEED_SDHCI_SDIO_140 0x10 | 346 | + qemu_set_irq(s->irq, !!(s->ints & s->int_mask)); |
| 240 | +#define ASPEED_SDHCI_SDIO_148 0x18 | 347 | +} |
| 241 | +#define ASPEED_SDHCI_SDIO_240 0x20 | 348 | + |
| 242 | +#define ASPEED_SDHCI_SDIO_248 0x28 | 349 | +uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) |
| 243 | +#define ASPEED_SDHCI_WP_POL 0xec | 350 | +{ |
| 244 | +#define ASPEED_SDHCI_CARD_DET 0xf0 | 351 | + uint16_t val; |
| 245 | +#define ASPEED_SDHCI_IRQ_STAT 0xfc | 352 | + |
| 246 | + | 353 | + switch (reg) { |
| 247 | +#define TO_REG(addr) ((addr) / sizeof(uint32_t)) | 354 | + case 0: /* Basic Control */ |
| 248 | + | 355 | + return s->control; |
| 249 | +static uint64_t aspeed_sdhci_read(void *opaque, hwaddr addr, unsigned int size) | 356 | + case 1: /* Basic Status */ |
| 250 | +{ | 357 | + return s->status; |
| 251 | + uint32_t val = 0; | 358 | + case 2: /* ID1 */ |
| 252 | + AspeedSDHCIState *sdhci = opaque; | 359 | + return 0x0007; |
| 253 | + | 360 | + case 3: /* ID2 */ |
| 254 | + switch (addr) { | 361 | + return 0xc0d1; |
| 255 | + case ASPEED_SDHCI_SDIO_140: | 362 | + case 4: /* Auto-neg advertisement */ |
| 256 | + val = (uint32_t)sdhci->slots[0].capareg; | 363 | + return s->advertise; |
| 364 | + case 5: /* Auto-neg Link Partner Ability */ | ||
| 365 | + return 0x0f71; | ||
| 366 | + case 6: /* Auto-neg Expansion */ | ||
| 367 | + return 1; | ||
| 368 | + /* TODO 17, 18, 27, 29, 30, 31 */ | ||
| 369 | + case 29: /* Interrupt source. */ | ||
| 370 | + val = s->ints; | ||
| 371 | + s->ints = 0; | ||
| 372 | + lan9118_phy_update_irq(s); | ||
| 373 | + return val; | ||
| 374 | + case 30: /* Interrupt mask */ | ||
| 375 | + return s->int_mask; | ||
| 376 | + default: | ||
| 377 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
| 378 | + "lan9118_phy_read: PHY read reg %d\n", reg); | ||
| 379 | + return 0; | ||
| 380 | + } | ||
| 381 | +} | ||
| 382 | + | ||
| 383 | +void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) | ||
| 384 | +{ | ||
| 385 | + switch (reg) { | ||
| 386 | + case 0: /* Basic Control */ | ||
| 387 | + if (val & 0x8000) { | ||
| 388 | + lan9118_phy_reset(s); | ||
| 389 | + break; | ||
| 390 | + } | ||
| 391 | + s->control = val & 0x7980; | ||
| 392 | + /* Complete autonegotiation immediately. */ | ||
| 393 | + if (val & 0x1000) { | ||
| 394 | + s->status |= 0x0020; | ||
| 395 | + } | ||
| 257 | + break; | 396 | + break; |
| 258 | + case ASPEED_SDHCI_SDIO_148: | 397 | + case 4: /* Auto-neg advertisement */ |
| 259 | + val = (uint32_t)sdhci->slots[0].maxcurr; | 398 | + s->advertise = (val & 0x2d7f) | 0x80; |
| 260 | + break; | 399 | + break; |
| 261 | + case ASPEED_SDHCI_SDIO_240: | 400 | + /* TODO 17, 18, 27, 31 */ |
| 262 | + val = (uint32_t)sdhci->slots[1].capareg; | 401 | + case 30: /* Interrupt mask */ |
| 263 | + break; | 402 | + s->int_mask = val & 0xff; |
| 264 | + case ASPEED_SDHCI_SDIO_248: | 403 | + lan9118_phy_update_irq(s); |
| 265 | + val = (uint32_t)sdhci->slots[1].maxcurr; | ||
| 266 | + break; | 404 | + break; |
| 267 | + default: | 405 | + default: |
| 268 | + if (addr < ASPEED_SDHCI_REG_SIZE) { | 406 | + qemu_log_mask(LOG_GUEST_ERROR, |
| 269 | + val = sdhci->regs[TO_REG(addr)]; | 407 | + "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val); |
| 270 | + } else { | ||
| 271 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
| 272 | + "%s: Out-of-bounds read at 0x%" HWADDR_PRIx "\n", | ||
| 273 | + __func__, addr); | ||
| 274 | + } | ||
| 275 | + } | 408 | + } |
| 276 | + | 409 | +} |
| 277 | + return (uint64_t)val; | 410 | + |
| 278 | +} | 411 | +void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) |
| 279 | + | 412 | +{ |
| 280 | +static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val, | 413 | + s->link_down = link_down; |
| 281 | + unsigned int size) | 414 | + |
| 282 | +{ | 415 | + /* Autonegotiation status mirrors link status. */ |
| 283 | + AspeedSDHCIState *sdhci = opaque; | 416 | + if (link_down) { |
| 284 | + | 417 | + s->status &= ~0x0024; |
| 285 | + switch (addr) { | 418 | + s->ints |= PHY_INT_DOWN; |
| 286 | + case ASPEED_SDHCI_SDIO_140: | 419 | + } else { |
| 287 | + sdhci->slots[0].capareg = (uint64_t)(uint32_t)val; | 420 | + s->status |= 0x0024; |
| 288 | + break; | 421 | + s->ints |= PHY_INT_ENERGYON; |
| 289 | + case ASPEED_SDHCI_SDIO_148: | 422 | + s->ints |= PHY_INT_AUTONEG_COMPLETE; |
| 290 | + sdhci->slots[0].maxcurr = (uint64_t)(uint32_t)val; | ||
| 291 | + break; | ||
| 292 | + case ASPEED_SDHCI_SDIO_240: | ||
| 293 | + sdhci->slots[1].capareg = (uint64_t)(uint32_t)val; | ||
| 294 | + break; | ||
| 295 | + case ASPEED_SDHCI_SDIO_248: | ||
| 296 | + sdhci->slots[1].maxcurr = (uint64_t)(uint32_t)val; | ||
| 297 | + break; | ||
| 298 | + default: | ||
| 299 | + if (addr < ASPEED_SDHCI_REG_SIZE) { | ||
| 300 | + sdhci->regs[TO_REG(addr)] = (uint32_t)val; | ||
| 301 | + } else { | ||
| 302 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
| 303 | + "%s: Out-of-bounds write at 0x%" HWADDR_PRIx "\n", | ||
| 304 | + __func__, addr); | ||
| 305 | + } | ||
| 306 | + } | 423 | + } |
| 307 | +} | 424 | + lan9118_phy_update_irq(s); |
| 308 | + | 425 | +} |
| 309 | +static const MemoryRegionOps aspeed_sdhci_ops = { | 426 | + |
| 310 | + .read = aspeed_sdhci_read, | 427 | +void lan9118_phy_reset(Lan9118PhyState *s) |
| 311 | + .write = aspeed_sdhci_write, | 428 | +{ |
| 312 | + .endianness = DEVICE_NATIVE_ENDIAN, | 429 | + s->control = 0x3000; |
| 313 | + .valid.min_access_size = 4, | 430 | + s->status = 0x7809; |
| 314 | + .valid.max_access_size = 4, | 431 | + s->advertise = 0x01e1; |
| 432 | + s->int_mask = 0; | ||
| 433 | + s->ints = 0; | ||
| 434 | + lan9118_phy_update_link(s, s->link_down); | ||
| 435 | +} | ||
| 436 | + | ||
| 437 | +static void lan9118_phy_reset_hold(Object *obj, ResetType type) | ||
| 438 | +{ | ||
| 439 | + Lan9118PhyState *s = LAN9118_PHY(obj); | ||
| 440 | + | ||
| 441 | + lan9118_phy_reset(s); | ||
| 442 | +} | ||
| 443 | + | ||
| 444 | +static void lan9118_phy_init(Object *obj) | ||
| 445 | +{ | ||
| 446 | + Lan9118PhyState *s = LAN9118_PHY(obj); | ||
| 447 | + | ||
| 448 | + qdev_init_gpio_out(DEVICE(s), &s->irq, 1); | ||
| 449 | +} | ||
| 450 | + | ||
| 451 | +static const VMStateDescription vmstate_lan9118_phy = { | ||
| 452 | + .name = "lan9118-phy", | ||
| 453 | + .version_id = 1, | ||
| 454 | + .minimum_version_id = 1, | ||
| 455 | + .fields = (const VMStateField[]) { | ||
| 456 | + VMSTATE_UINT16(control, Lan9118PhyState), | ||
| 457 | + VMSTATE_UINT16(status, Lan9118PhyState), | ||
| 458 | + VMSTATE_UINT16(advertise, Lan9118PhyState), | ||
| 459 | + VMSTATE_UINT16(ints, Lan9118PhyState), | ||
| 460 | + VMSTATE_UINT16(int_mask, Lan9118PhyState), | ||
| 461 | + VMSTATE_BOOL(link_down, Lan9118PhyState), | ||
| 462 | + VMSTATE_END_OF_LIST() | ||
| 463 | + } | ||
| 315 | +}; | 464 | +}; |
| 316 | + | 465 | + |
| 317 | +static void aspeed_sdhci_set_irq(void *opaque, int n, int level) | 466 | +static void lan9118_phy_class_init(ObjectClass *klass, void *data) |
| 318 | +{ | 467 | +{ |
| 319 | + AspeedSDHCIState *sdhci = opaque; | 468 | + ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 320 | + | 469 | + DeviceClass *dc = DEVICE_CLASS(klass); |
| 321 | + if (level) { | 470 | + |
| 322 | + sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] |= BIT(n); | 471 | + rc->phases.hold = lan9118_phy_reset_hold; |
| 323 | + | 472 | + dc->vmsd = &vmstate_lan9118_phy; |
| 324 | + qemu_irq_raise(sdhci->irq); | 473 | +} |
| 325 | + } else { | 474 | + |
| 326 | + sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] &= ~BIT(n); | 475 | +static const TypeInfo types[] = { |
| 327 | + | 476 | + { |
| 328 | + qemu_irq_lower(sdhci->irq); | 477 | + .name = TYPE_LAN9118_PHY, |
| 478 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
| 479 | + .instance_size = sizeof(Lan9118PhyState), | ||
| 480 | + .instance_init = lan9118_phy_init, | ||
| 481 | + .class_init = lan9118_phy_class_init, | ||
| 329 | + } | 482 | + } |
| 330 | +} | ||
| 331 | + | ||
| 332 | +static void aspeed_sdhci_realize(DeviceState *dev, Error **errp) | ||
| 333 | +{ | ||
| 334 | + Error *err = NULL; | ||
| 335 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
| 336 | + AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev); | ||
| 337 | + | ||
| 338 | + /* Create input irqs for the slots */ | ||
| 339 | + qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq, | ||
| 340 | + sdhci, NULL, ASPEED_SDHCI_NUM_SLOTS); | ||
| 341 | + | ||
| 342 | + sysbus_init_irq(sbd, &sdhci->irq); | ||
| 343 | + memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops, | ||
| 344 | + sdhci, TYPE_ASPEED_SDHCI, 0x1000); | ||
| 345 | + sysbus_init_mmio(sbd, &sdhci->iomem); | ||
| 346 | + | ||
| 347 | + for (int i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | ||
| 348 | + Object *sdhci_slot = OBJECT(&sdhci->slots[i]); | ||
| 349 | + SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slots[i]); | ||
| 350 | + | ||
| 351 | + object_property_set_int(sdhci_slot, 2, "sd-spec-version", &err); | ||
| 352 | + if (err) { | ||
| 353 | + error_propagate(errp, err); | ||
| 354 | + return; | ||
| 355 | + } | ||
| 356 | + | ||
| 357 | + object_property_set_uint(sdhci_slot, ASPEED_SDHCI_CAPABILITIES, | ||
| 358 | + "capareg", &err); | ||
| 359 | + if (err) { | ||
| 360 | + error_propagate(errp, err); | ||
| 361 | + return; | ||
| 362 | + } | ||
| 363 | + | ||
| 364 | + object_property_set_bool(sdhci_slot, true, "realized", &err); | ||
| 365 | + if (err) { | ||
| 366 | + error_propagate(errp, err); | ||
| 367 | + return; | ||
| 368 | + } | ||
| 369 | + | ||
| 370 | + sysbus_connect_irq(sbd_slot, 0, qdev_get_gpio_in(DEVICE(sbd), i)); | ||
| 371 | + memory_region_add_subregion(&sdhci->iomem, (i + 1) * 0x100, | ||
| 372 | + &sdhci->slots[i].iomem); | ||
| 373 | + } | ||
| 374 | +} | ||
| 375 | + | ||
| 376 | +static void aspeed_sdhci_reset(DeviceState *dev) | ||
| 377 | +{ | ||
| 378 | + AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev); | ||
| 379 | + | ||
| 380 | + memset(sdhci->regs, 0, ASPEED_SDHCI_REG_SIZE); | ||
| 381 | + sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] = ASPEED_SDHCI_INFO_RESET; | ||
| 382 | + sdhci->regs[TO_REG(ASPEED_SDHCI_DEBOUNCE)] = ASPEED_SDHCI_DEBOUNCE_RESET; | ||
| 383 | +} | ||
| 384 | + | ||
| 385 | +static const VMStateDescription vmstate_aspeed_sdhci = { | ||
| 386 | + .name = TYPE_ASPEED_SDHCI, | ||
| 387 | + .version_id = 1, | ||
| 388 | + .fields = (VMStateField[]) { | ||
| 389 | + VMSTATE_UINT32_ARRAY(regs, AspeedSDHCIState, ASPEED_SDHCI_NUM_REGS), | ||
| 390 | + VMSTATE_END_OF_LIST(), | ||
| 391 | + }, | ||
| 392 | +}; | 483 | +}; |
| 393 | + | 484 | + |
| 394 | +static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) | 485 | +DEFINE_TYPES(types) |
| 395 | +{ | 486 | diff --git a/hw/net/Kconfig b/hw/net/Kconfig |
| 396 | + DeviceClass *dc = DEVICE_CLASS(classp); | 487 | index XXXXXXX..XXXXXXX 100644 |
| 397 | + | 488 | --- a/hw/net/Kconfig |
| 398 | + dc->realize = aspeed_sdhci_realize; | 489 | +++ b/hw/net/Kconfig |
| 399 | + dc->reset = aspeed_sdhci_reset; | 490 | @@ -XXX,XX +XXX,XX @@ config VMXNET3_PCI |
| 400 | + dc->vmsd = &vmstate_aspeed_sdhci; | 491 | config SMC91C111 |
| 401 | +} | 492 | bool |
| 402 | + | 493 | |
| 403 | +static TypeInfo aspeed_sdhci_info = { | 494 | +config LAN9118_PHY |
| 404 | + .name = TYPE_ASPEED_SDHCI, | 495 | + bool |
| 405 | + .parent = TYPE_SYS_BUS_DEVICE, | 496 | + |
| 406 | + .instance_size = sizeof(AspeedSDHCIState), | 497 | config LAN9118 |
| 407 | + .class_init = aspeed_sdhci_class_init, | 498 | bool |
| 408 | +}; | 499 | + select LAN9118_PHY |
| 409 | + | 500 | select PTIMER |
| 410 | +static void aspeed_sdhci_register_types(void) | 501 | |
| 411 | +{ | 502 | config NE2000_ISA |
| 412 | + type_register_static(&aspeed_sdhci_info); | 503 | diff --git a/hw/net/meson.build b/hw/net/meson.build |
| 413 | +} | 504 | index XXXXXXX..XXXXXXX 100644 |
| 414 | + | 505 | --- a/hw/net/meson.build |
| 415 | +type_init(aspeed_sdhci_register_types) | 506 | +++ b/hw/net/meson.build |
| 507 | @@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c')) | ||
| 508 | |||
| 509 | system_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c')) | ||
| 510 | system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c')) | ||
| 511 | +system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c')) | ||
| 512 | system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c')) | ||
| 513 | system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c')) | ||
| 514 | system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c')) | ||
| 416 | -- | 515 | -- |
| 417 | 2.20.1 | 516 | 2.34.1 |
| 418 | |||
| 419 | diff view generated by jsdifflib |
| 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Bernhard Beschow <shentey@gmail.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Add trace events for read/write accesses and IRQ. | 3 | imx_fec models the same PHY as lan9118_phy. The code is almost the same with |
| 4 | imx_fec having more logging and tracing. Merge these improvements into | ||
| 5 | lan9118_phy and reuse in imx_fec to fix the code duplication. | ||
| 4 | 6 | ||
| 5 | Properties are structures used for the ARM particular MBOX. | 7 | Some migration state how resides in the new device model which breaks migration |
| 6 | Since one call in bcm2835_property.c concerns the mbox block, | 8 | compatibility for the following machines: |
| 7 | name this trace event in the same bcm2835_mbox* namespace. | 9 | * imx25-pdk |
| 10 | * sabrelite | ||
| 11 | * mcimx7d-sabre | ||
| 12 | * mcimx6ul-evk | ||
| 8 | 13 | ||
| 9 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 14 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> |
| 10 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 15 | Tested-by: Guenter Roeck <linux@roeck-us.net> |
| 11 | Message-id: 20190926173428.10713-8-f4bug@amsat.org | 16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 17 | Message-id: 20241102125724.532843-3-shentey@gmail.com | ||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 13 | --- | 19 | --- |
| 14 | hw/misc/bcm2835_mbox.c | 5 +++++ | 20 | include/hw/net/imx_fec.h | 9 ++- |
| 15 | hw/misc/bcm2835_property.c | 2 ++ | 21 | hw/net/imx_fec.c | 146 ++++----------------------------------- |
| 16 | hw/misc/trace-events | 6 ++++++ | 22 | hw/net/lan9118_phy.c | 82 ++++++++++++++++------ |
| 17 | 3 files changed, 13 insertions(+) | 23 | hw/net/Kconfig | 1 + |
| 24 | hw/net/trace-events | 10 +-- | ||
| 25 | 5 files changed, 85 insertions(+), 163 deletions(-) | ||
| 18 | 26 | ||
| 19 | diff --git a/hw/misc/bcm2835_mbox.c b/hw/misc/bcm2835_mbox.c | 27 | diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h |
| 20 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
| 21 | --- a/hw/misc/bcm2835_mbox.c | 29 | --- a/include/hw/net/imx_fec.h |
| 22 | +++ b/hw/misc/bcm2835_mbox.c | 30 | +++ b/include/hw/net/imx_fec.h |
| 31 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC) | ||
| 32 | #define TYPE_IMX_ENET "imx.enet" | ||
| 33 | |||
| 34 | #include "hw/sysbus.h" | ||
| 35 | +#include "hw/net/lan9118_phy.h" | ||
| 36 | +#include "hw/irq.h" | ||
| 37 | #include "net/net.h" | ||
| 38 | |||
| 39 | #define ENET_EIR 1 | ||
| 40 | @@ -XXX,XX +XXX,XX @@ struct IMXFECState { | ||
| 41 | uint32_t tx_descriptor[ENET_TX_RING_NUM]; | ||
| 42 | uint32_t tx_ring_num; | ||
| 43 | |||
| 44 | - uint32_t phy_status; | ||
| 45 | - uint32_t phy_control; | ||
| 46 | - uint32_t phy_advertise; | ||
| 47 | - uint32_t phy_int; | ||
| 48 | - uint32_t phy_int_mask; | ||
| 49 | + Lan9118PhyState mii; | ||
| 50 | + IRQState mii_irq; | ||
| 51 | uint32_t phy_num; | ||
| 52 | bool phy_connected; | ||
| 53 | struct IMXFECState *phy_consumer; | ||
| 54 | diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c | ||
| 55 | index XXXXXXX..XXXXXXX 100644 | ||
| 56 | --- a/hw/net/imx_fec.c | ||
| 57 | +++ b/hw/net/imx_fec.c | ||
| 58 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth_txdescs = { | ||
| 59 | |||
| 60 | static const VMStateDescription vmstate_imx_eth = { | ||
| 61 | .name = TYPE_IMX_FEC, | ||
| 62 | - .version_id = 2, | ||
| 63 | - .minimum_version_id = 2, | ||
| 64 | + .version_id = 3, | ||
| 65 | + .minimum_version_id = 3, | ||
| 66 | .fields = (const VMStateField[]) { | ||
| 67 | VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX), | ||
| 68 | VMSTATE_UINT32(rx_descriptor, IMXFECState), | ||
| 69 | VMSTATE_UINT32(tx_descriptor[0], IMXFECState), | ||
| 70 | - VMSTATE_UINT32(phy_status, IMXFECState), | ||
| 71 | - VMSTATE_UINT32(phy_control, IMXFECState), | ||
| 72 | - VMSTATE_UINT32(phy_advertise, IMXFECState), | ||
| 73 | - VMSTATE_UINT32(phy_int, IMXFECState), | ||
| 74 | - VMSTATE_UINT32(phy_int_mask, IMXFECState), | ||
| 75 | VMSTATE_END_OF_LIST() | ||
| 76 | }, | ||
| 77 | .subsections = (const VMStateDescription * const []) { | ||
| 78 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth = { | ||
| 79 | }, | ||
| 80 | }; | ||
| 81 | |||
| 82 | -#define PHY_INT_ENERGYON (1 << 7) | ||
| 83 | -#define PHY_INT_AUTONEG_COMPLETE (1 << 6) | ||
| 84 | -#define PHY_INT_FAULT (1 << 5) | ||
| 85 | -#define PHY_INT_DOWN (1 << 4) | ||
| 86 | -#define PHY_INT_AUTONEG_LP (1 << 3) | ||
| 87 | -#define PHY_INT_PARFAULT (1 << 2) | ||
| 88 | -#define PHY_INT_AUTONEG_PAGE (1 << 1) | ||
| 89 | - | ||
| 90 | static void imx_eth_update(IMXFECState *s); | ||
| 91 | |||
| 92 | /* | ||
| 93 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_update(IMXFECState *s); | ||
| 94 | * For now we don't handle any GPIO/interrupt line, so the OS will | ||
| 95 | * have to poll for the PHY status. | ||
| 96 | */ | ||
| 97 | -static void imx_phy_update_irq(IMXFECState *s) | ||
| 98 | +static void imx_phy_update_irq(void *opaque, int n, int level) | ||
| 99 | { | ||
| 100 | - imx_eth_update(s); | ||
| 101 | -} | ||
| 102 | - | ||
| 103 | -static void imx_phy_update_link(IMXFECState *s) | ||
| 104 | -{ | ||
| 105 | - /* Autonegotiation status mirrors link status. */ | ||
| 106 | - if (qemu_get_queue(s->nic)->link_down) { | ||
| 107 | - trace_imx_phy_update_link("down"); | ||
| 108 | - s->phy_status &= ~0x0024; | ||
| 109 | - s->phy_int |= PHY_INT_DOWN; | ||
| 110 | - } else { | ||
| 111 | - trace_imx_phy_update_link("up"); | ||
| 112 | - s->phy_status |= 0x0024; | ||
| 113 | - s->phy_int |= PHY_INT_ENERGYON; | ||
| 114 | - s->phy_int |= PHY_INT_AUTONEG_COMPLETE; | ||
| 115 | - } | ||
| 116 | - imx_phy_update_irq(s); | ||
| 117 | + imx_eth_update(opaque); | ||
| 118 | } | ||
| 119 | |||
| 120 | static void imx_eth_set_link(NetClientState *nc) | ||
| 121 | { | ||
| 122 | - imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc))); | ||
| 123 | -} | ||
| 124 | - | ||
| 125 | -static void imx_phy_reset(IMXFECState *s) | ||
| 126 | -{ | ||
| 127 | - trace_imx_phy_reset(); | ||
| 128 | - | ||
| 129 | - s->phy_status = 0x7809; | ||
| 130 | - s->phy_control = 0x3000; | ||
| 131 | - s->phy_advertise = 0x01e1; | ||
| 132 | - s->phy_int_mask = 0; | ||
| 133 | - s->phy_int = 0; | ||
| 134 | - imx_phy_update_link(s); | ||
| 135 | + lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii, | ||
| 136 | + nc->link_down); | ||
| 137 | } | ||
| 138 | |||
| 139 | static uint32_t imx_phy_read(IMXFECState *s, int reg) | ||
| 140 | { | ||
| 141 | - uint32_t val; | ||
| 142 | uint32_t phy = reg / 32; | ||
| 143 | |||
| 144 | if (!s->phy_connected) { | ||
| 145 | @@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg) | ||
| 146 | |||
| 147 | reg %= 32; | ||
| 148 | |||
| 149 | - switch (reg) { | ||
| 150 | - case 0: /* Basic Control */ | ||
| 151 | - val = s->phy_control; | ||
| 152 | - break; | ||
| 153 | - case 1: /* Basic Status */ | ||
| 154 | - val = s->phy_status; | ||
| 155 | - break; | ||
| 156 | - case 2: /* ID1 */ | ||
| 157 | - val = 0x0007; | ||
| 158 | - break; | ||
| 159 | - case 3: /* ID2 */ | ||
| 160 | - val = 0xc0d1; | ||
| 161 | - break; | ||
| 162 | - case 4: /* Auto-neg advertisement */ | ||
| 163 | - val = s->phy_advertise; | ||
| 164 | - break; | ||
| 165 | - case 5: /* Auto-neg Link Partner Ability */ | ||
| 166 | - val = 0x0f71; | ||
| 167 | - break; | ||
| 168 | - case 6: /* Auto-neg Expansion */ | ||
| 169 | - val = 1; | ||
| 170 | - break; | ||
| 171 | - case 29: /* Interrupt source. */ | ||
| 172 | - val = s->phy_int; | ||
| 173 | - s->phy_int = 0; | ||
| 174 | - imx_phy_update_irq(s); | ||
| 175 | - break; | ||
| 176 | - case 30: /* Interrupt mask */ | ||
| 177 | - val = s->phy_int_mask; | ||
| 178 | - break; | ||
| 179 | - case 17: | ||
| 180 | - case 18: | ||
| 181 | - case 27: | ||
| 182 | - case 31: | ||
| 183 | - qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n", | ||
| 184 | - TYPE_IMX_FEC, __func__, reg); | ||
| 185 | - val = 0; | ||
| 186 | - break; | ||
| 187 | - default: | ||
| 188 | - qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n", | ||
| 189 | - TYPE_IMX_FEC, __func__, reg); | ||
| 190 | - val = 0; | ||
| 191 | - break; | ||
| 192 | - } | ||
| 193 | - | ||
| 194 | - trace_imx_phy_read(val, phy, reg); | ||
| 195 | - | ||
| 196 | - return val; | ||
| 197 | + return lan9118_phy_read(&s->mii, reg); | ||
| 198 | } | ||
| 199 | |||
| 200 | static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) | ||
| 201 | @@ -XXX,XX +XXX,XX @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) | ||
| 202 | |||
| 203 | reg %= 32; | ||
| 204 | |||
| 205 | - trace_imx_phy_write(val, phy, reg); | ||
| 206 | - | ||
| 207 | - switch (reg) { | ||
| 208 | - case 0: /* Basic Control */ | ||
| 209 | - if (val & 0x8000) { | ||
| 210 | - imx_phy_reset(s); | ||
| 211 | - } else { | ||
| 212 | - s->phy_control = val & 0x7980; | ||
| 213 | - /* Complete autonegotiation immediately. */ | ||
| 214 | - if (val & 0x1000) { | ||
| 215 | - s->phy_status |= 0x0020; | ||
| 216 | - } | ||
| 217 | - } | ||
| 218 | - break; | ||
| 219 | - case 4: /* Auto-neg advertisement */ | ||
| 220 | - s->phy_advertise = (val & 0x2d7f) | 0x80; | ||
| 221 | - break; | ||
| 222 | - case 30: /* Interrupt mask */ | ||
| 223 | - s->phy_int_mask = val & 0xff; | ||
| 224 | - imx_phy_update_irq(s); | ||
| 225 | - break; | ||
| 226 | - case 17: | ||
| 227 | - case 18: | ||
| 228 | - case 27: | ||
| 229 | - case 31: | ||
| 230 | - qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n", | ||
| 231 | - TYPE_IMX_FEC, __func__, reg); | ||
| 232 | - break; | ||
| 233 | - default: | ||
| 234 | - qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n", | ||
| 235 | - TYPE_IMX_FEC, __func__, reg); | ||
| 236 | - break; | ||
| 237 | - } | ||
| 238 | + lan9118_phy_write(&s->mii, reg, val); | ||
| 239 | } | ||
| 240 | |||
| 241 | static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr) | ||
| 242 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_reset(DeviceState *d) | ||
| 243 | |||
| 244 | s->rx_descriptor = 0; | ||
| 245 | memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor)); | ||
| 246 | - | ||
| 247 | - /* We also reset the PHY */ | ||
| 248 | - imx_phy_reset(s); | ||
| 249 | } | ||
| 250 | |||
| 251 | static uint32_t imx_default_read(IMXFECState *s, uint32_t index) | ||
| 252 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp) | ||
| 253 | sysbus_init_irq(sbd, &s->irq[0]); | ||
| 254 | sysbus_init_irq(sbd, &s->irq[1]); | ||
| 255 | |||
| 256 | + qemu_init_irq(&s->mii_irq, imx_phy_update_irq, s, 0); | ||
| 257 | + object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY); | ||
| 258 | + if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) { | ||
| 259 | + return; | ||
| 260 | + } | ||
| 261 | + qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq); | ||
| 262 | + | ||
| 263 | qemu_macaddr_default_if_unset(&s->conf.macaddr); | ||
| 264 | |||
| 265 | s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf, | ||
| 266 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c | ||
| 267 | index XXXXXXX..XXXXXXX 100644 | ||
| 268 | --- a/hw/net/lan9118_phy.c | ||
| 269 | +++ b/hw/net/lan9118_phy.c | ||
| 23 | @@ -XXX,XX +XXX,XX @@ | 270 | @@ -XXX,XX +XXX,XX @@ |
| 271 | * Copyright (c) 2009 CodeSourcery, LLC. | ||
| 272 | * Written by Paul Brook | ||
| 273 | * | ||
| 274 | + * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net> | ||
| 275 | + * | ||
| 276 | * This code is licensed under the GNU GPL v2 | ||
| 277 | * | ||
| 278 | * Contributions after 2012-01-13 are licensed under the terms of the | ||
| 279 | @@ -XXX,XX +XXX,XX @@ | ||
| 280 | #include "hw/resettable.h" | ||
| 24 | #include "migration/vmstate.h" | 281 | #include "migration/vmstate.h" |
| 25 | #include "qemu/log.h" | 282 | #include "qemu/log.h" |
| 26 | #include "qemu/module.h" | ||
| 27 | +#include "trace.h" | 283 | +#include "trace.h" |
| 28 | 284 | ||
| 29 | #define MAIL0_PEEK 0x90 | 285 | #define PHY_INT_ENERGYON (1 << 7) |
| 30 | #define MAIL0_SENDER 0x94 | 286 | #define PHY_INT_AUTONEG_COMPLETE (1 << 6) |
| 31 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_mbox_update(BCM2835MboxState *s) | 287 | @@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) |
| 32 | set = true; | 288 | |
| 289 | switch (reg) { | ||
| 290 | case 0: /* Basic Control */ | ||
| 291 | - return s->control; | ||
| 292 | + val = s->control; | ||
| 293 | + break; | ||
| 294 | case 1: /* Basic Status */ | ||
| 295 | - return s->status; | ||
| 296 | + val = s->status; | ||
| 297 | + break; | ||
| 298 | case 2: /* ID1 */ | ||
| 299 | - return 0x0007; | ||
| 300 | + val = 0x0007; | ||
| 301 | + break; | ||
| 302 | case 3: /* ID2 */ | ||
| 303 | - return 0xc0d1; | ||
| 304 | + val = 0xc0d1; | ||
| 305 | + break; | ||
| 306 | case 4: /* Auto-neg advertisement */ | ||
| 307 | - return s->advertise; | ||
| 308 | + val = s->advertise; | ||
| 309 | + break; | ||
| 310 | case 5: /* Auto-neg Link Partner Ability */ | ||
| 311 | - return 0x0f71; | ||
| 312 | + val = 0x0f71; | ||
| 313 | + break; | ||
| 314 | case 6: /* Auto-neg Expansion */ | ||
| 315 | - return 1; | ||
| 316 | - /* TODO 17, 18, 27, 29, 30, 31 */ | ||
| 317 | + val = 1; | ||
| 318 | + break; | ||
| 319 | case 29: /* Interrupt source. */ | ||
| 320 | val = s->ints; | ||
| 321 | s->ints = 0; | ||
| 322 | lan9118_phy_update_irq(s); | ||
| 323 | - return val; | ||
| 324 | + break; | ||
| 325 | case 30: /* Interrupt mask */ | ||
| 326 | - return s->int_mask; | ||
| 327 | + val = s->int_mask; | ||
| 328 | + break; | ||
| 329 | + case 17: | ||
| 330 | + case 18: | ||
| 331 | + case 27: | ||
| 332 | + case 31: | ||
| 333 | + qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", | ||
| 334 | + __func__, reg); | ||
| 335 | + val = 0; | ||
| 336 | + break; | ||
| 337 | default: | ||
| 338 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
| 339 | - "lan9118_phy_read: PHY read reg %d\n", reg); | ||
| 340 | - return 0; | ||
| 341 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", | ||
| 342 | + __func__, reg); | ||
| 343 | + val = 0; | ||
| 344 | + break; | ||
| 345 | } | ||
| 346 | + | ||
| 347 | + trace_lan9118_phy_read(val, reg); | ||
| 348 | + | ||
| 349 | + return val; | ||
| 350 | } | ||
| 351 | |||
| 352 | void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) | ||
| 353 | { | ||
| 354 | + trace_lan9118_phy_write(val, reg); | ||
| 355 | + | ||
| 356 | switch (reg) { | ||
| 357 | case 0: /* Basic Control */ | ||
| 358 | if (val & 0x8000) { | ||
| 359 | lan9118_phy_reset(s); | ||
| 360 | - break; | ||
| 361 | - } | ||
| 362 | - s->control = val & 0x7980; | ||
| 363 | - /* Complete autonegotiation immediately. */ | ||
| 364 | - if (val & 0x1000) { | ||
| 365 | - s->status |= 0x0020; | ||
| 366 | + } else { | ||
| 367 | + s->control = val & 0x7980; | ||
| 368 | + /* Complete autonegotiation immediately. */ | ||
| 369 | + if (val & 0x1000) { | ||
| 370 | + s->status |= 0x0020; | ||
| 371 | + } | ||
| 33 | } | 372 | } |
| 373 | break; | ||
| 374 | case 4: /* Auto-neg advertisement */ | ||
| 375 | s->advertise = (val & 0x2d7f) | 0x80; | ||
| 376 | break; | ||
| 377 | - /* TODO 17, 18, 27, 31 */ | ||
| 378 | case 30: /* Interrupt mask */ | ||
| 379 | s->int_mask = val & 0xff; | ||
| 380 | lan9118_phy_update_irq(s); | ||
| 381 | break; | ||
| 382 | + case 17: | ||
| 383 | + case 18: | ||
| 384 | + case 27: | ||
| 385 | + case 31: | ||
| 386 | + qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", | ||
| 387 | + __func__, reg); | ||
| 388 | + break; | ||
| 389 | default: | ||
| 390 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
| 391 | - "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val); | ||
| 392 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", | ||
| 393 | + __func__, reg); | ||
| 394 | + break; | ||
| 34 | } | 395 | } |
| 35 | + trace_bcm2835_mbox_irq(set); | 396 | } |
| 36 | qemu_set_irq(s->arm_irq, set); | 397 | |
| 37 | } | 398 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) |
| 38 | 399 | ||
| 39 | @@ -XXX,XX +XXX,XX @@ static uint64_t bcm2835_mbox_read(void *opaque, hwaddr offset, unsigned size) | 400 | /* Autonegotiation status mirrors link status. */ |
| 40 | default: | 401 | if (link_down) { |
| 41 | qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx"\n", | 402 | + trace_lan9118_phy_update_link("down"); |
| 42 | __func__, offset); | 403 | s->status &= ~0x0024; |
| 43 | + trace_bcm2835_mbox_read(size, offset, res); | 404 | s->ints |= PHY_INT_DOWN; |
| 44 | return 0; | 405 | } else { |
| 45 | } | 406 | + trace_lan9118_phy_update_link("up"); |
| 46 | + trace_bcm2835_mbox_read(size, offset, res); | 407 | s->status |= 0x0024; |
| 47 | 408 | s->ints |= PHY_INT_ENERGYON; | |
| 48 | bcm2835_mbox_update(s); | 409 | s->ints |= PHY_INT_AUTONEG_COMPLETE; |
| 49 | 410 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) | |
| 50 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_mbox_write(void *opaque, hwaddr offset, | 411 | |
| 51 | 412 | void lan9118_phy_reset(Lan9118PhyState *s) | |
| 52 | offset &= 0xff; | 413 | { |
| 53 | 414 | + trace_lan9118_phy_reset(); | |
| 54 | + trace_bcm2835_mbox_write(size, offset, value); | 415 | + |
| 55 | switch (offset) { | 416 | s->control = 0x3000; |
| 56 | case MAIL0_SENDER: | 417 | s->status = 0x7809; |
| 57 | break; | 418 | s->advertise = 0x01e1; |
| 58 | diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c | 419 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118_phy = { |
| 420 | .version_id = 1, | ||
| 421 | .minimum_version_id = 1, | ||
| 422 | .fields = (const VMStateField[]) { | ||
| 423 | - VMSTATE_UINT16(control, Lan9118PhyState), | ||
| 424 | VMSTATE_UINT16(status, Lan9118PhyState), | ||
| 425 | + VMSTATE_UINT16(control, Lan9118PhyState), | ||
| 426 | VMSTATE_UINT16(advertise, Lan9118PhyState), | ||
| 427 | VMSTATE_UINT16(ints, Lan9118PhyState), | ||
| 428 | VMSTATE_UINT16(int_mask, Lan9118PhyState), | ||
| 429 | diff --git a/hw/net/Kconfig b/hw/net/Kconfig | ||
| 59 | index XXXXXXX..XXXXXXX 100644 | 430 | index XXXXXXX..XXXXXXX 100644 |
| 60 | --- a/hw/misc/bcm2835_property.c | 431 | --- a/hw/net/Kconfig |
| 61 | +++ b/hw/misc/bcm2835_property.c | 432 | +++ b/hw/net/Kconfig |
| 62 | @@ -XXX,XX +XXX,XX @@ | 433 | @@ -XXX,XX +XXX,XX @@ config ALLWINNER_SUN8I_EMAC |
| 63 | #include "sysemu/dma.h" | 434 | |
| 64 | #include "qemu/log.h" | 435 | config IMX_FEC |
| 65 | #include "qemu/module.h" | 436 | bool |
| 66 | +#include "trace.h" | 437 | + select LAN9118_PHY |
| 67 | 438 | ||
| 68 | /* https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface */ | 439 | config CADENCE |
| 69 | 440 | bool | |
| 70 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) | 441 | diff --git a/hw/net/trace-events b/hw/net/trace-events |
| 71 | break; | ||
| 72 | } | ||
| 73 | |||
| 74 | + trace_bcm2835_mbox_property(tag, bufsize, resplen); | ||
| 75 | if (tag == 0) { | ||
| 76 | break; | ||
| 77 | } | ||
| 78 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
| 79 | index XXXXXXX..XXXXXXX 100644 | 442 | index XXXXXXX..XXXXXXX 100644 |
| 80 | --- a/hw/misc/trace-events | 443 | --- a/hw/net/trace-events |
| 81 | +++ b/hw/misc/trace-events | 444 | +++ b/hw/net/trace-events |
| 82 | @@ -XXX,XX +XXX,XX @@ armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU wri | 445 | @@ -XXX,XX +XXX,XX @@ allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u" |
| 83 | 446 | allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64 | |
| 84 | # aspeed_xdma.c | 447 | allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64 |
| 85 | aspeed_xdma_write(uint64_t offset, uint64_t data) "XDMA write: offset 0x%" PRIx64 " data 0x%" PRIx64 | 448 | |
| 86 | + | 449 | +# lan9118_phy.c |
| 87 | +# bcm2835_mbox.c | 450 | +lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16 |
| 88 | +bcm2835_mbox_write(unsigned int size, uint64_t addr, uint64_t value) "mbox write sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 | 451 | +lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16 |
| 89 | +bcm2835_mbox_read(unsigned int size, uint64_t addr, uint64_t value) "mbox read sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 | 452 | +lan9118_phy_update_link(const char *s) "%s" |
| 90 | +bcm2835_mbox_irq(unsigned level) "mbox irq:ARM level:%u" | 453 | +lan9118_phy_reset(void) "" |
| 91 | +bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbox property tag:0x%08x in_sz:%u out_sz:%zu" | 454 | + |
| 455 | # lance.c | ||
| 456 | lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x" | ||
| 457 | lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x" | ||
| 458 | @@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries" | ||
| 459 | i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION" | ||
| 460 | |||
| 461 | # imx_fec.c | ||
| 462 | -imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]" | ||
| 463 | imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)" | ||
| 464 | -imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]" | ||
| 465 | imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)" | ||
| 466 | -imx_phy_update_link(const char *s) "%s" | ||
| 467 | -imx_phy_reset(void) "" | ||
| 468 | imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x" | ||
| 469 | imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x" | ||
| 470 | imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit" | ||
| 92 | -- | 471 | -- |
| 93 | 2.20.1 | 472 | 2.34.1 |
| 94 | |||
| 95 | diff view generated by jsdifflib |
| 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Bernhard Beschow <shentey@gmail.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Base addresses and sizes taken from the "BCM2835 ARM Peripherals" | 3 | Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and |
| 4 | datasheet from February 06 2012: | 4 | fixes the MSB of selector field to be zero, as specified in the datasheet. |
| 5 | https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf | ||
| 6 | 5 | ||
| 6 | Fixes: 2a424990170b "LAN9118 emulation" | ||
| 7 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> | ||
| 8 | Tested-by: Guenter Roeck <linux@roeck-us.net> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 8 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 10 | Message-id: 20241102125724.532843-4-shentey@gmail.com |
| 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 11 | Message-id: 20190926173428.10713-6-f4bug@amsat.org | ||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 13 | --- | 12 | --- |
| 14 | include/hw/arm/bcm2835_peripherals.h | 15 ++++++++++++++ | 13 | hw/net/lan9118_phy.c | 2 +- |
| 15 | include/hw/arm/raspi_platform.h | 8 +++++++ | 14 | 1 file changed, 1 insertion(+), 1 deletion(-) |
| 16 | hw/arm/bcm2835_peripherals.c | 31 ++++++++++++++++++++++++++++ | ||
| 17 | 3 files changed, 54 insertions(+) | ||
| 18 | 15 | ||
| 19 | diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h | 16 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c |
| 20 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 21 | --- a/include/hw/arm/bcm2835_peripherals.h | 18 | --- a/hw/net/lan9118_phy.c |
| 22 | +++ b/include/hw/arm/bcm2835_peripherals.h | 19 | +++ b/hw/net/lan9118_phy.c |
| 23 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) |
| 24 | #include "hw/sd/sdhci.h" | 21 | val = s->advertise; |
| 25 | #include "hw/sd/bcm2835_sdhost.h" | 22 | break; |
| 26 | #include "hw/gpio/bcm2835_gpio.h" | 23 | case 5: /* Auto-neg Link Partner Ability */ |
| 27 | +#include "hw/misc/unimp.h" | 24 | - val = 0x0f71; |
| 28 | 25 | + val = 0x0fe1; | |
| 29 | #define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals" | 26 | break; |
| 30 | #define BCM2835_PERIPHERALS(obj) \ | 27 | case 6: /* Auto-neg Expansion */ |
| 31 | @@ -XXX,XX +XXX,XX @@ typedef struct BCM2835PeripheralState { | 28 | val = 1; |
| 32 | MemoryRegion ram_alias[4]; | ||
| 33 | qemu_irq irq, fiq; | ||
| 34 | |||
| 35 | + UnimplementedDeviceState systmr; | ||
| 36 | + UnimplementedDeviceState armtmr; | ||
| 37 | + UnimplementedDeviceState cprman; | ||
| 38 | + UnimplementedDeviceState a2w; | ||
| 39 | PL011State uart0; | ||
| 40 | BCM2835AuxState aux; | ||
| 41 | BCM2835FBState fb; | ||
| 42 | @@ -XXX,XX +XXX,XX @@ typedef struct BCM2835PeripheralState { | ||
| 43 | SDHCIState sdhci; | ||
| 44 | BCM2835SDHostState sdhost; | ||
| 45 | BCM2835GpioState gpio; | ||
| 46 | + UnimplementedDeviceState i2s; | ||
| 47 | + UnimplementedDeviceState spi[1]; | ||
| 48 | + UnimplementedDeviceState i2c[3]; | ||
| 49 | + UnimplementedDeviceState otp; | ||
| 50 | + UnimplementedDeviceState dbus; | ||
| 51 | + UnimplementedDeviceState ave0; | ||
| 52 | + UnimplementedDeviceState bscsl; | ||
| 53 | + UnimplementedDeviceState smi; | ||
| 54 | + UnimplementedDeviceState dwc2; | ||
| 55 | + UnimplementedDeviceState sdramc; | ||
| 56 | } BCM2835PeripheralState; | ||
| 57 | |||
| 58 | #endif /* BCM2835_PERIPHERALS_H */ | ||
| 59 | diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h | ||
| 60 | index XXXXXXX..XXXXXXX 100644 | ||
| 61 | --- a/include/hw/arm/raspi_platform.h | ||
| 62 | +++ b/include/hw/arm/raspi_platform.h | ||
| 63 | @@ -XXX,XX +XXX,XX @@ | ||
| 64 | * Doorbells & Mailboxes */ | ||
| 65 | #define CPRMAN_OFFSET 0x100000 /* Power Management, Watchdog */ | ||
| 66 | #define CM_OFFSET 0x101000 /* Clock Management */ | ||
| 67 | +#define A2W_OFFSET 0x102000 /* Reset controller */ | ||
| 68 | +#define AVS_OFFSET 0x103000 /* Audio Video Standard */ | ||
| 69 | #define RNG_OFFSET 0x104000 | ||
| 70 | #define GPIO_OFFSET 0x200000 | ||
| 71 | #define UART0_OFFSET 0x201000 | ||
| 72 | @@ -XXX,XX +XXX,XX @@ | ||
| 73 | #define I2S_OFFSET 0x203000 | ||
| 74 | #define SPI0_OFFSET 0x204000 | ||
| 75 | #define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */ | ||
| 76 | +#define OTP_OFFSET 0x20f000 | ||
| 77 | +#define BSC_SL_OFFSET 0x214000 /* SPI slave */ | ||
| 78 | #define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */ | ||
| 79 | #define EMMC1_OFFSET 0x300000 | ||
| 80 | #define SMI_OFFSET 0x600000 | ||
| 81 | #define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */ | ||
| 82 | +#define BSC2_OFFSET 0x805000 /* BSC2 I2C/TWI */ | ||
| 83 | +#define DBUS_OFFSET 0x900000 | ||
| 84 | +#define AVE0_OFFSET 0x910000 | ||
| 85 | #define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */ | ||
| 86 | +#define SDRAMC_OFFSET 0xe00000 | ||
| 87 | #define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */ | ||
| 88 | |||
| 89 | /* GPU interrupts */ | ||
| 90 | diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c | ||
| 91 | index XXXXXXX..XXXXXXX 100644 | ||
| 92 | --- a/hw/arm/bcm2835_peripherals.c | ||
| 93 | +++ b/hw/arm/bcm2835_peripherals.c | ||
| 94 | @@ -XXX,XX +XXX,XX @@ | ||
| 95 | /* Capabilities for SD controller: no DMA, high-speed, default clocks etc. */ | ||
| 96 | #define BCM2835_SDHC_CAPAREG 0x52134b4 | ||
| 97 | |||
| 98 | +static void create_unimp(BCM2835PeripheralState *ps, | ||
| 99 | + UnimplementedDeviceState *uds, | ||
| 100 | + const char *name, hwaddr ofs, hwaddr size) | ||
| 101 | +{ | ||
| 102 | + sysbus_init_child_obj(OBJECT(ps), name, uds, | ||
| 103 | + sizeof(UnimplementedDeviceState), | ||
| 104 | + TYPE_UNIMPLEMENTED_DEVICE); | ||
| 105 | + qdev_prop_set_string(DEVICE(uds), "name", name); | ||
| 106 | + qdev_prop_set_uint64(DEVICE(uds), "size", size); | ||
| 107 | + object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal); | ||
| 108 | + memory_region_add_subregion_overlap(&ps->peri_mr, ofs, | ||
| 109 | + sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0), -1000); | ||
| 110 | +} | ||
| 111 | + | ||
| 112 | static void bcm2835_peripherals_init(Object *obj) | ||
| 113 | { | ||
| 114 | BCM2835PeripheralState *s = BCM2835_PERIPHERALS(obj); | ||
| 115 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) | ||
| 116 | error_propagate(errp, err); | ||
| 117 | return; | ||
| 118 | } | ||
| 119 | + | ||
| 120 | + create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40); | ||
| 121 | + create_unimp(s, &s->systmr, "bcm2835-systimer", ST_OFFSET, 0x20); | ||
| 122 | + create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000); | ||
| 123 | + create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000); | ||
| 124 | + create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100); | ||
| 125 | + create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100); | ||
| 126 | + create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20); | ||
| 127 | + create_unimp(s, &s->bscsl, "bcm2835-spis", BSC_SL_OFFSET, 0x100); | ||
| 128 | + create_unimp(s, &s->i2c[0], "bcm2835-i2c0", BSC0_OFFSET, 0x20); | ||
| 129 | + create_unimp(s, &s->i2c[1], "bcm2835-i2c1", BSC1_OFFSET, 0x20); | ||
| 130 | + create_unimp(s, &s->i2c[2], "bcm2835-i2c2", BSC2_OFFSET, 0x20); | ||
| 131 | + create_unimp(s, &s->otp, "bcm2835-otp", OTP_OFFSET, 0x80); | ||
| 132 | + create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000); | ||
| 133 | + create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000); | ||
| 134 | + create_unimp(s, &s->dwc2, "dwc-usb2", USB_OTG_OFFSET, 0x1000); | ||
| 135 | + create_unimp(s, &s->sdramc, "bcm2835-sdramc", SDRAMC_OFFSET, 0x100); | ||
| 136 | } | ||
| 137 | |||
| 138 | static void bcm2835_peripherals_class_init(ObjectClass *oc, void *data) | ||
| 139 | -- | 29 | -- |
| 140 | 2.20.1 | 30 | 2.34.1 |
| 141 | |||
| 142 | diff view generated by jsdifflib |
| 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Bernhard Beschow <shentey@gmail.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The UART1 is part of the AUX peripheral, | 3 | Prefer named constants over magic values for better readability. |
| 4 | the PCM_CLOCK (yet unimplemented) is part of the CPRMAN. | ||
| 5 | 4 | ||
| 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 6 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> |
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 7 | Tested-by: Guenter Roeck <linux@roeck-us.net> |
| 9 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 8 | Message-id: 20241102125724.532843-5-shentey@gmail.com |
| 10 | Message-id: 20190926173428.10713-5-f4bug@amsat.org | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 12 | --- | 10 | --- |
| 13 | include/hw/arm/raspi_platform.h | 16 +++++++--------- | 11 | include/hw/net/mii.h | 6 +++++ |
| 14 | hw/arm/bcm2835_peripherals.c | 7 ++++--- | 12 | hw/net/lan9118_phy.c | 63 ++++++++++++++++++++++++++++---------------- |
| 15 | hw/arm/bcm2836.c | 2 +- | 13 | 2 files changed, 46 insertions(+), 23 deletions(-) |
| 16 | 3 files changed, 12 insertions(+), 13 deletions(-) | ||
| 17 | 14 | ||
| 18 | diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h | 15 | diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h |
| 19 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 20 | --- a/include/hw/arm/raspi_platform.h | 17 | --- a/include/hw/net/mii.h |
| 21 | +++ b/include/hw/arm/raspi_platform.h | 18 | +++ b/include/hw/net/mii.h |
| 22 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ |
| 23 | #ifndef HW_ARM_RASPI_PLATFORM_H | 20 | #define MII_BMSR_JABBER (1 << 1) /* Jabber detected */ |
| 24 | #define HW_ARM_RASPI_PLATFORM_H | 21 | #define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */ |
| 25 | 22 | ||
| 26 | -#define MCORE_OFFSET 0x0000 /* Fake frame buffer device | 23 | +#define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */ |
| 27 | - * (the multicore sync block) */ | 24 | #define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymmetric pause */ |
| 28 | +#define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */ | 25 | #define MII_ANAR_PAUSE (1 << 10) /* Try for pause */ |
| 29 | #define IC0_OFFSET 0x2000 | 26 | #define MII_ANAR_TXFD (1 << 8) |
| 30 | #define ST_OFFSET 0x3000 /* System Timer */ | ||
| 31 | #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */ | ||
| 32 | @@ -XXX,XX +XXX,XX @@ | 27 | @@ -XXX,XX +XXX,XX @@ |
| 33 | #define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */ | 28 | #define MII_ANAR_10FD (1 << 6) |
| 34 | #define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores | 29 | #define MII_ANAR_10 (1 << 5) |
| 35 | * Doorbells & Mailboxes */ | 30 | #define MII_ANAR_CSMACD (1 << 0) |
| 36 | -#define PM_OFFSET 0x100000 /* Power Management, Reset controller | 31 | +#define MII_ANAR_SELECT (0x001f) /* Selector bits */ |
| 37 | - * and Watchdog registers */ | 32 | |
| 38 | -#define PCM_CLOCK_OFFSET 0x101098 | 33 | #define MII_ANLPAR_ACK (1 << 14) |
| 39 | +#define CPRMAN_OFFSET 0x100000 /* Power Management, Watchdog */ | 34 | #define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */ |
| 40 | +#define CM_OFFSET 0x101000 /* Clock Management */ | ||
| 41 | #define RNG_OFFSET 0x104000 | ||
| 42 | #define GPIO_OFFSET 0x200000 | ||
| 43 | #define UART0_OFFSET 0x201000 | ||
| 44 | @@ -XXX,XX +XXX,XX @@ | 35 | @@ -XXX,XX +XXX,XX @@ |
| 45 | #define I2S_OFFSET 0x203000 | 36 | #define RTL8201CP_PHYID1 0x0000 |
| 46 | #define SPI0_OFFSET 0x204000 | 37 | #define RTL8201CP_PHYID2 0x8201 |
| 47 | #define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */ | 38 | |
| 48 | -#define UART1_OFFSET 0x215000 | 39 | +/* SMSC LAN9118 */ |
| 49 | -#define EMMC_OFFSET 0x300000 | 40 | +#define SMSCLAN9118_PHYID1 0x0007 |
| 50 | +#define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */ | 41 | +#define SMSCLAN9118_PHYID2 0xc0d1 |
| 51 | +#define EMMC1_OFFSET 0x300000 | 42 | + |
| 52 | #define SMI_OFFSET 0x600000 | 43 | /* RealTek 8211E */ |
| 53 | #define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */ | 44 | #define RTL8211E_PHYID1 0x001c |
| 54 | -#define USB_OFFSET 0x980000 /* DTC_OTG USB controller */ | 45 | #define RTL8211E_PHYID2 0xc915 |
| 55 | +#define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */ | 46 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c |
| 56 | #define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */ | 47 | index XXXXXXX..XXXXXXX 100644 |
| 57 | 48 | --- a/hw/net/lan9118_phy.c | |
| 58 | /* GPU interrupts */ | 49 | +++ b/hw/net/lan9118_phy.c |
| 59 | @@ -XXX,XX +XXX,XX @@ | 50 | @@ -XXX,XX +XXX,XX @@ |
| 60 | #define INTERRUPT_SPI 54 | 51 | |
| 61 | #define INTERRUPT_I2SPCM 55 | 52 | #include "qemu/osdep.h" |
| 62 | #define INTERRUPT_SDIO 56 | 53 | #include "hw/net/lan9118_phy.h" |
| 63 | -#define INTERRUPT_UART 57 | 54 | +#include "hw/net/mii.h" |
| 64 | +#define INTERRUPT_UART0 57 | 55 | #include "hw/irq.h" |
| 65 | #define INTERRUPT_SLIMBUS 58 | 56 | #include "hw/resettable.h" |
| 66 | #define INTERRUPT_VEC 59 | 57 | #include "migration/vmstate.h" |
| 67 | #define INTERRUPT_CPG 60 | 58 | @@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) |
| 68 | diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c | 59 | uint16_t val; |
| 69 | index XXXXXXX..XXXXXXX 100644 | 60 | |
| 70 | --- a/hw/arm/bcm2835_peripherals.c | 61 | switch (reg) { |
| 71 | +++ b/hw/arm/bcm2835_peripherals.c | 62 | - case 0: /* Basic Control */ |
| 72 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) | 63 | + case MII_BMCR: |
| 73 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart0), 0)); | 64 | val = s->control; |
| 74 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart0), 0, | 65 | break; |
| 75 | qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, | 66 | - case 1: /* Basic Status */ |
| 76 | - INTERRUPT_UART)); | 67 | + case MII_BMSR: |
| 77 | + INTERRUPT_UART0)); | 68 | val = s->status; |
| 78 | + | 69 | break; |
| 79 | /* AUX / UART1 */ | 70 | - case 2: /* ID1 */ |
| 80 | qdev_prop_set_chr(DEVICE(&s->aux), "chardev", serial_hd(1)); | 71 | - val = 0x0007; |
| 81 | 72 | + case MII_PHYID1: | |
| 82 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) | 73 | + val = SMSCLAN9118_PHYID1; |
| 83 | return; | 74 | break; |
| 75 | - case 3: /* ID2 */ | ||
| 76 | - val = 0xc0d1; | ||
| 77 | + case MII_PHYID2: | ||
| 78 | + val = SMSCLAN9118_PHYID2; | ||
| 79 | break; | ||
| 80 | - case 4: /* Auto-neg advertisement */ | ||
| 81 | + case MII_ANAR: | ||
| 82 | val = s->advertise; | ||
| 83 | break; | ||
| 84 | - case 5: /* Auto-neg Link Partner Ability */ | ||
| 85 | - val = 0x0fe1; | ||
| 86 | + case MII_ANLPAR: | ||
| 87 | + val = MII_ANLPAR_PAUSEASY | MII_ANLPAR_PAUSE | MII_ANLPAR_T4 | | ||
| 88 | + MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD | | ||
| 89 | + MII_ANLPAR_10 | MII_ANLPAR_CSMACD; | ||
| 90 | break; | ||
| 91 | - case 6: /* Auto-neg Expansion */ | ||
| 92 | - val = 1; | ||
| 93 | + case MII_ANER: | ||
| 94 | + val = MII_ANER_NWAY; | ||
| 95 | break; | ||
| 96 | case 29: /* Interrupt source. */ | ||
| 97 | val = s->ints; | ||
| 98 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) | ||
| 99 | trace_lan9118_phy_write(val, reg); | ||
| 100 | |||
| 101 | switch (reg) { | ||
| 102 | - case 0: /* Basic Control */ | ||
| 103 | - if (val & 0x8000) { | ||
| 104 | + case MII_BMCR: | ||
| 105 | + if (val & MII_BMCR_RESET) { | ||
| 106 | lan9118_phy_reset(s); | ||
| 107 | } else { | ||
| 108 | - s->control = val & 0x7980; | ||
| 109 | + s->control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 | | ||
| 110 | + MII_BMCR_AUTOEN | MII_BMCR_PDOWN | MII_BMCR_FD | | ||
| 111 | + MII_BMCR_CTST); | ||
| 112 | /* Complete autonegotiation immediately. */ | ||
| 113 | - if (val & 0x1000) { | ||
| 114 | - s->status |= 0x0020; | ||
| 115 | + if (val & MII_BMCR_AUTOEN) { | ||
| 116 | + s->status |= MII_BMSR_AN_COMP; | ||
| 117 | } | ||
| 118 | } | ||
| 119 | break; | ||
| 120 | - case 4: /* Auto-neg advertisement */ | ||
| 121 | - s->advertise = (val & 0x2d7f) | 0x80; | ||
| 122 | + case MII_ANAR: | ||
| 123 | + s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM | | ||
| 124 | + MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 | | ||
| 125 | + MII_ANAR_SELECT)) | ||
| 126 | + | MII_ANAR_TX; | ||
| 127 | break; | ||
| 128 | case 30: /* Interrupt mask */ | ||
| 129 | s->int_mask = val & 0xff; | ||
| 130 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) | ||
| 131 | /* Autonegotiation status mirrors link status. */ | ||
| 132 | if (link_down) { | ||
| 133 | trace_lan9118_phy_update_link("down"); | ||
| 134 | - s->status &= ~0x0024; | ||
| 135 | + s->status &= ~(MII_BMSR_AN_COMP | MII_BMSR_LINK_ST); | ||
| 136 | s->ints |= PHY_INT_DOWN; | ||
| 137 | } else { | ||
| 138 | trace_lan9118_phy_update_link("up"); | ||
| 139 | - s->status |= 0x0024; | ||
| 140 | + s->status |= MII_BMSR_AN_COMP | MII_BMSR_LINK_ST; | ||
| 141 | s->ints |= PHY_INT_ENERGYON; | ||
| 142 | s->ints |= PHY_INT_AUTONEG_COMPLETE; | ||
| 84 | } | 143 | } |
| 85 | 144 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_reset(Lan9118PhyState *s) | |
| 86 | - memory_region_add_subregion(&s->peri_mr, UART1_OFFSET, | 145 | { |
| 87 | + memory_region_add_subregion(&s->peri_mr, AUX_OFFSET, | 146 | trace_lan9118_phy_reset(); |
| 88 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->aux), 0)); | 147 | |
| 89 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->aux), 0, | 148 | - s->control = 0x3000; |
| 90 | qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, | 149 | - s->status = 0x7809; |
| 91 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) | 150 | - s->advertise = 0x01e1; |
| 92 | return; | 151 | + s->control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100; |
| 93 | } | 152 | + s->status = MII_BMSR_100TX_FD |
| 94 | 153 | + | MII_BMSR_100TX_HD | |
| 95 | - memory_region_add_subregion(&s->peri_mr, EMMC_OFFSET, | 154 | + | MII_BMSR_10T_FD |
| 96 | + memory_region_add_subregion(&s->peri_mr, EMMC1_OFFSET, | 155 | + | MII_BMSR_10T_HD |
| 97 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhci), 0)); | 156 | + | MII_BMSR_AUTONEG |
| 98 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, | 157 | + | MII_BMSR_EXTCAP; |
| 99 | qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, | 158 | + s->advertise = MII_ANAR_TXFD |
| 100 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c | 159 | + | MII_ANAR_TX |
| 101 | index XXXXXXX..XXXXXXX 100644 | 160 | + | MII_ANAR_10FD |
| 102 | --- a/hw/arm/bcm2836.c | 161 | + | MII_ANAR_10 |
| 103 | +++ b/hw/arm/bcm2836.c | 162 | + | MII_ANAR_CSMACD; |
| 104 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | 163 | s->int_mask = 0; |
| 105 | 164 | s->ints = 0; | |
| 106 | /* set periphbase/CBAR value for CPU-local registers */ | 165 | lan9118_phy_update_link(s, s->link_down); |
| 107 | object_property_set_int(OBJECT(&s->cpus[n]), | ||
| 108 | - BCM2836_PERI_BASE + MCORE_OFFSET, | ||
| 109 | + BCM2836_PERI_BASE + MSYNC_OFFSET, | ||
| 110 | "reset-cbar", &err); | ||
| 111 | if (err) { | ||
| 112 | error_propagate(errp, err); | ||
| 113 | -- | 166 | -- |
| 114 | 2.20.1 | 167 | 2.34.1 |
| 115 | |||
| 116 | diff view generated by jsdifflib |
| 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Bernhard Beschow <shentey@gmail.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | IEC binary prefixes ease code review: the unit is explicit. | 3 | The real device advertises this mode and the device model already advertises |
| 4 | 100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to | ||
| 5 | make the model more realistic. | ||
| 4 | 6 | ||
| 5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 8 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> |
| 7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 9 | Tested-by: Guenter Roeck <linux@roeck-us.net> |
| 8 | Reviewed-by: Cleber Rosa <crosa@redhat.com> | 10 | Message-id: 20241102125724.532843-6-shentey@gmail.com |
| 9 | Message-id: 20190926173428.10713-2-f4bug@amsat.org | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | --- | 12 | --- |
| 12 | hw/arm/raspi.c | 4 ++-- | 13 | hw/net/lan9118_phy.c | 4 ++-- |
| 13 | 1 file changed, 2 insertions(+), 2 deletions(-) | 14 | 1 file changed, 2 insertions(+), 2 deletions(-) |
| 14 | 15 | ||
| 15 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | 16 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c |
| 16 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/hw/arm/raspi.c | 18 | --- a/hw/net/lan9118_phy.c |
| 18 | +++ b/hw/arm/raspi.c | 19 | +++ b/hw/net/lan9118_phy.c |
| 19 | @@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc) | 20 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) |
| 20 | mc->max_cpus = BCM283X_NCPUS; | 21 | break; |
| 21 | mc->min_cpus = BCM283X_NCPUS; | 22 | case MII_ANAR: |
| 22 | mc->default_cpus = BCM283X_NCPUS; | 23 | s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM | |
| 23 | - mc->default_ram_size = 1024 * 1024 * 1024; | 24 | - MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 | |
| 24 | + mc->default_ram_size = 1 * GiB; | 25 | - MII_ANAR_SELECT)) |
| 25 | mc->ignore_memory_transaction_failures = true; | 26 | + MII_ANAR_PAUSE | MII_ANAR_TXFD | MII_ANAR_10FD | |
| 26 | }; | 27 | + MII_ANAR_10 | MII_ANAR_SELECT)) |
| 27 | DEFINE_MACHINE("raspi2", raspi2_machine_init) | 28 | | MII_ANAR_TX; |
| 28 | @@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc) | 29 | break; |
| 29 | mc->max_cpus = BCM283X_NCPUS; | 30 | case 30: /* Interrupt mask */ |
| 30 | mc->min_cpus = BCM283X_NCPUS; | ||
| 31 | mc->default_cpus = BCM283X_NCPUS; | ||
| 32 | - mc->default_ram_size = 1024 * 1024 * 1024; | ||
| 33 | + mc->default_ram_size = 1 * GiB; | ||
| 34 | } | ||
| 35 | DEFINE_MACHINE("raspi3", raspi3_machine_init) | ||
| 36 | #endif | ||
| 37 | -- | 31 | -- |
| 38 | 2.20.1 | 32 | 2.34.1 |
| 39 | |||
| 40 | diff view generated by jsdifflib |
| 1 | From: Cédric Le Goater <clg@kaod.org> | 1 | For IEEE fused multiply-add, the (0 * inf) + NaN case should raise |
|---|---|---|---|
| 2 | Invalid for the multiplication of 0 by infinity. Currently we handle | ||
| 3 | this in the per-architecture ifdef ladder in pickNaNMulAdd(). | ||
| 4 | However, since this isn't really architecture specific we can hoist | ||
| 5 | it up to the generic code. | ||
| 2 | 6 | ||
| 3 | The AST2600 SoC has an extra controller to set the PHY registers. | 7 | For the cases where the infzero test in pickNaNMulAdd was |
| 8 | returning 2, we can delete the check entirely and allow the | ||
| 9 | code to fall into the normal pick-a-NaN handling, because this | ||
| 10 | will return 2 anyway (input 'c' being the only NaN in this case). | ||
| 11 | For the cases where infzero was returning 3 to indicate "return | ||
| 12 | the default NaN", we must retain that "return 3". | ||
| 4 | 13 | ||
| 5 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 14 | For Arm, this looks like it might be a behaviour change because we |
| 6 | Reviewed-by: Joel Stanley <joel@jms.id.au> | 15 | used to set float_flag_invalid | float_flag_invalid_imz only if C is |
| 7 | Message-id: 20190925143248.10000-23-clg@kaod.org | 16 | a quiet NaN. However, it is not, because Arm target code never looks |
| 17 | at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we | ||
| 18 | already raised float_flag_invalid via the "abc_mask & | ||
| 19 | float_cmask_snan" check in pick_nan_muladd. | ||
| 20 | |||
| 21 | For any target architecture using the "default implementation" at the | ||
| 22 | bottom of the ifdef, this is a behaviour change but will be fixing a | ||
| 23 | bug (where we failed to raise the Invalid exception for (0 * inf + | ||
| 24 | QNaN). The architectures using the default case are: | ||
| 25 | * hppa | ||
| 26 | * i386 | ||
| 27 | * sh4 | ||
| 28 | * tricore | ||
| 29 | |||
| 30 | The x86, Tricore and SH4 CPU architecture manuals are clear that this | ||
| 31 | should have raised Invalid; HPPA is a bit vaguer but still seems | ||
| 32 | clear enough. | ||
| 33 | |||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 34 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 35 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 36 | Message-id: 20241202131347.498124-2-peter.maydell@linaro.org | ||
| 9 | --- | 37 | --- |
| 10 | include/hw/arm/aspeed_soc.h | 5 ++ | 38 | fpu/softfloat-parts.c.inc | 13 +++++++------ |
| 11 | include/hw/net/ftgmac100.h | 17 ++++ | 39 | fpu/softfloat-specialize.c.inc | 29 +---------------------------- |
| 12 | hw/arm/aspeed_ast2600.c | 20 +++++ | 40 | 2 files changed, 8 insertions(+), 34 deletions(-) |
| 13 | hw/net/ftgmac100.c | 162 ++++++++++++++++++++++++++++++++++++ | ||
| 14 | 4 files changed, 204 insertions(+) | ||
| 15 | 41 | ||
| 16 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | 42 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
| 17 | index XXXXXXX..XXXXXXX 100644 | 43 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/include/hw/arm/aspeed_soc.h | 44 | --- a/fpu/softfloat-parts.c.inc |
| 19 | +++ b/include/hw/arm/aspeed_soc.h | 45 | +++ b/fpu/softfloat-parts.c.inc |
| 20 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState { | 46 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
| 21 | AspeedSDMCState sdmc; | 47 | int ab_mask, int abc_mask) |
| 22 | AspeedWDTState wdt[ASPEED_WDTS_NUM]; | 48 | { |
| 23 | FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; | 49 | int which; |
| 24 | + AspeedMiiState mii[ASPEED_MACS_NUM]; | 50 | + bool infzero = (ab_mask == float_cmask_infzero); |
| 25 | AspeedGPIOState gpio; | 51 | |
| 26 | AspeedGPIOState gpio_1_8v; | 52 | if (unlikely(abc_mask & float_cmask_snan)) { |
| 27 | AspeedSDHCIState sdhci; | 53 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); |
| 28 | @@ -XXX,XX +XXX,XX @@ enum { | ||
| 29 | ASPEED_ETH2, | ||
| 30 | ASPEED_ETH3, | ||
| 31 | ASPEED_ETH4, | ||
| 32 | + ASPEED_MII1, | ||
| 33 | + ASPEED_MII2, | ||
| 34 | + ASPEED_MII3, | ||
| 35 | + ASPEED_MII4, | ||
| 36 | ASPEED_SDRAM, | ||
| 37 | ASPEED_XDMA, | ||
| 38 | }; | ||
| 39 | diff --git a/include/hw/net/ftgmac100.h b/include/hw/net/ftgmac100.h | ||
| 40 | index XXXXXXX..XXXXXXX 100644 | ||
| 41 | --- a/include/hw/net/ftgmac100.h | ||
| 42 | +++ b/include/hw/net/ftgmac100.h | ||
| 43 | @@ -XXX,XX +XXX,XX @@ typedef struct FTGMAC100State { | ||
| 44 | uint32_t rxdes0_edorr; | ||
| 45 | } FTGMAC100State; | ||
| 46 | |||
| 47 | +#define TYPE_ASPEED_MII "aspeed-mmi" | ||
| 48 | +#define ASPEED_MII(obj) OBJECT_CHECK(AspeedMiiState, (obj), TYPE_ASPEED_MII) | ||
| 49 | + | ||
| 50 | +/* | ||
| 51 | + * AST2600 MII controller | ||
| 52 | + */ | ||
| 53 | +typedef struct AspeedMiiState { | ||
| 54 | + /*< private >*/ | ||
| 55 | + SysBusDevice parent_obj; | ||
| 56 | + | ||
| 57 | + FTGMAC100State *nic; | ||
| 58 | + | ||
| 59 | + MemoryRegion iomem; | ||
| 60 | + uint32_t phycr; | ||
| 61 | + uint32_t phydata; | ||
| 62 | +} AspeedMiiState; | ||
| 63 | + | ||
| 64 | #endif | ||
| 65 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c | ||
| 66 | index XXXXXXX..XXXXXXX 100644 | ||
| 67 | --- a/hw/arm/aspeed_ast2600.c | ||
| 68 | +++ b/hw/arm/aspeed_ast2600.c | ||
| 69 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { | ||
| 70 | [ASPEED_FMC] = 0x1E620000, | ||
| 71 | [ASPEED_SPI1] = 0x1E630000, | ||
| 72 | [ASPEED_SPI2] = 0x1E641000, | ||
| 73 | + [ASPEED_MII1] = 0x1E650000, | ||
| 74 | + [ASPEED_MII2] = 0x1E650008, | ||
| 75 | + [ASPEED_MII3] = 0x1E650010, | ||
| 76 | + [ASPEED_MII4] = 0x1E650018, | ||
| 77 | [ASPEED_ETH1] = 0x1E660000, | ||
| 78 | [ASPEED_ETH3] = 0x1E670000, | ||
| 79 | [ASPEED_ETH2] = 0x1E680000, | ||
| 80 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj) | ||
| 81 | for (i = 0; i < sc->macs_num; i++) { | ||
| 82 | sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]), | ||
| 83 | sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); | ||
| 84 | + | ||
| 85 | + sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]), | ||
| 86 | + TYPE_ASPEED_MII); | ||
| 87 | + object_property_add_const_link(OBJECT(&s->mii[i]), "nic", | ||
| 88 | + OBJECT(&s->ftgmac100[i]), | ||
| 89 | + &error_abort); | ||
| 90 | } | 54 | } |
| 91 | 55 | ||
| 92 | sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma), | 56 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, |
| 93 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | 57 | - ab_mask == float_cmask_infzero, s); |
| 94 | sc->memmap[ASPEED_ETH1 + i]); | 58 | + if (infzero) { |
| 95 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | 59 | + /* This is (0 * inf) + NaN or (inf * 0) + NaN */ |
| 96 | aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); | 60 | + float_raise(float_flag_invalid | float_flag_invalid_imz, s); |
| 97 | + | ||
| 98 | + object_property_set_bool(OBJECT(&s->mii[i]), true, "realized", | ||
| 99 | + &err); | ||
| 100 | + if (err) { | ||
| 101 | + error_propagate(errp, err); | ||
| 102 | + return; | ||
| 103 | + } | ||
| 104 | + | ||
| 105 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, | ||
| 106 | + sc->memmap[ASPEED_MII1 + i]); | ||
| 107 | } | ||
| 108 | |||
| 109 | /* XDMA */ | ||
| 110 | diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c | ||
| 111 | index XXXXXXX..XXXXXXX 100644 | ||
| 112 | --- a/hw/net/ftgmac100.c | ||
| 113 | +++ b/hw/net/ftgmac100.c | ||
| 114 | @@ -XXX,XX +XXX,XX @@ | ||
| 115 | #include "hw/irq.h" | ||
| 116 | #include "hw/net/ftgmac100.h" | ||
| 117 | #include "sysemu/dma.h" | ||
| 118 | +#include "qapi/error.h" | ||
| 119 | #include "qemu/log.h" | ||
| 120 | #include "qemu/module.h" | ||
| 121 | #include "net/checksum.h" | ||
| 122 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo ftgmac100_info = { | ||
| 123 | .class_init = ftgmac100_class_init, | ||
| 124 | }; | ||
| 125 | |||
| 126 | +/* | ||
| 127 | + * AST2600 MII controller | ||
| 128 | + */ | ||
| 129 | +#define ASPEED_MII_PHYCR_FIRE BIT(31) | ||
| 130 | +#define ASPEED_MII_PHYCR_ST_22 BIT(28) | ||
| 131 | +#define ASPEED_MII_PHYCR_OP(x) ((x) & (ASPEED_MII_PHYCR_OP_WRITE | \ | ||
| 132 | + ASPEED_MII_PHYCR_OP_READ)) | ||
| 133 | +#define ASPEED_MII_PHYCR_OP_WRITE BIT(26) | ||
| 134 | +#define ASPEED_MII_PHYCR_OP_READ BIT(27) | ||
| 135 | +#define ASPEED_MII_PHYCR_DATA(x) (x & 0xffff) | ||
| 136 | +#define ASPEED_MII_PHYCR_PHY(x) (((x) >> 21) & 0x1f) | ||
| 137 | +#define ASPEED_MII_PHYCR_REG(x) (((x) >> 16) & 0x1f) | ||
| 138 | + | ||
| 139 | +#define ASPEED_MII_PHYDATA_IDLE BIT(16) | ||
| 140 | + | ||
| 141 | +static void aspeed_mii_transition(AspeedMiiState *s, bool fire) | ||
| 142 | +{ | ||
| 143 | + if (fire) { | ||
| 144 | + s->phycr |= ASPEED_MII_PHYCR_FIRE; | ||
| 145 | + s->phydata &= ~ASPEED_MII_PHYDATA_IDLE; | ||
| 146 | + } else { | ||
| 147 | + s->phycr &= ~ASPEED_MII_PHYCR_FIRE; | ||
| 148 | + s->phydata |= ASPEED_MII_PHYDATA_IDLE; | ||
| 149 | + } | ||
| 150 | +} | ||
| 151 | + | ||
| 152 | +static void aspeed_mii_do_phy_ctl(AspeedMiiState *s) | ||
| 153 | +{ | ||
| 154 | + uint8_t reg; | ||
| 155 | + uint16_t data; | ||
| 156 | + | ||
| 157 | + if (!(s->phycr & ASPEED_MII_PHYCR_ST_22)) { | ||
| 158 | + aspeed_mii_transition(s, !ASPEED_MII_PHYCR_FIRE); | ||
| 159 | + qemu_log_mask(LOG_UNIMP, "%s: unsupported ST code\n", __func__); | ||
| 160 | + return; | ||
| 161 | + } | 61 | + } |
| 162 | + | 62 | + |
| 163 | + /* Nothing to do */ | 63 | + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); |
| 164 | + if (!(s->phycr & ASPEED_MII_PHYCR_FIRE)) { | 64 | |
| 165 | + return; | 65 | if (s->default_nan_mode || which == 3) { |
| 166 | + } | 66 | - /* |
| 67 | - * Note that this check is after pickNaNMulAdd so that function | ||
| 68 | - * has an opportunity to set the Invalid flag for infzero. | ||
| 69 | - */ | ||
| 70 | parts_default_nan(a, s); | ||
| 71 | return a; | ||
| 72 | } | ||
| 73 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 74 | index XXXXXXX..XXXXXXX 100644 | ||
| 75 | --- a/fpu/softfloat-specialize.c.inc | ||
| 76 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 77 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 78 | * the default NaN | ||
| 79 | */ | ||
| 80 | if (infzero && is_qnan(c_cls)) { | ||
| 81 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
| 82 | return 3; | ||
| 83 | } | ||
| 84 | |||
| 85 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 86 | * case sets InvalidOp and returns the default NaN | ||
| 87 | */ | ||
| 88 | if (infzero) { | ||
| 89 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
| 90 | return 3; | ||
| 91 | } | ||
| 92 | /* Prefer sNaN over qNaN, in the a, b, c order. */ | ||
| 93 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 94 | * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 95 | * case sets InvalidOp and returns the input value 'c' | ||
| 96 | */ | ||
| 97 | - if (infzero) { | ||
| 98 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
| 99 | - return 2; | ||
| 100 | - } | ||
| 101 | /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
| 102 | if (is_snan(c_cls)) { | ||
| 103 | return 2; | ||
| 104 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 105 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 106 | * case sets InvalidOp and returns the input value 'c' | ||
| 107 | */ | ||
| 108 | - if (infzero) { | ||
| 109 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
| 110 | - return 2; | ||
| 111 | - } | ||
| 167 | + | 112 | + |
| 168 | + reg = ASPEED_MII_PHYCR_REG(s->phycr); | 113 | /* Prefer sNaN over qNaN, in the c, a, b order. */ |
| 169 | + data = ASPEED_MII_PHYCR_DATA(s->phycr); | 114 | if (is_snan(c_cls)) { |
| 170 | + | 115 | return 2; |
| 171 | + switch (ASPEED_MII_PHYCR_OP(s->phycr)) { | 116 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 172 | + case ASPEED_MII_PHYCR_OP_WRITE: | 117 | * to return an input NaN if we have one (ie c) rather than generating |
| 173 | + do_phy_write(s->nic, reg, data); | 118 | * a default NaN |
| 174 | + break; | 119 | */ |
| 175 | + case ASPEED_MII_PHYCR_OP_READ: | 120 | - if (infzero) { |
| 176 | + s->phydata = (s->phydata & ~0xffff) | do_phy_read(s->nic, reg); | 121 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); |
| 177 | + break; | 122 | - return 2; |
| 178 | + default: | 123 | - } |
| 179 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid OP code %08x\n", | 124 | |
| 180 | + __func__, s->phycr); | 125 | /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; |
| 181 | + } | 126 | * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB |
| 182 | + | 127 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 183 | + aspeed_mii_transition(s, !ASPEED_MII_PHYCR_FIRE); | 128 | return 1; |
| 184 | +} | 129 | } |
| 185 | + | 130 | #elif defined(TARGET_RISCV) |
| 186 | +static uint64_t aspeed_mii_read(void *opaque, hwaddr addr, unsigned size) | 131 | - /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ |
| 187 | +{ | 132 | - if (infzero) { |
| 188 | + AspeedMiiState *s = ASPEED_MII(opaque); | 133 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); |
| 189 | + | 134 | - } |
| 190 | + switch (addr) { | 135 | return 3; /* default NaN */ |
| 191 | + case 0x0: | 136 | #elif defined(TARGET_S390X) |
| 192 | + return s->phycr; | 137 | if (infzero) { |
| 193 | + case 0x4: | 138 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); |
| 194 | + return s->phydata; | 139 | return 3; |
| 195 | + default: | 140 | } |
| 196 | + g_assert_not_reached(); | 141 | |
| 197 | + } | 142 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 198 | +} | 143 | return 2; |
| 199 | + | 144 | } |
| 200 | +static void aspeed_mii_write(void *opaque, hwaddr addr, | 145 | #elif defined(TARGET_SPARC) |
| 201 | + uint64_t value, unsigned size) | 146 | - /* For (inf,0,nan) return c. */ |
| 202 | +{ | 147 | - if (infzero) { |
| 203 | + AspeedMiiState *s = ASPEED_MII(opaque); | 148 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); |
| 204 | + | 149 | - return 2; |
| 205 | + switch (addr) { | 150 | - } |
| 206 | + case 0x0: | 151 | /* Prefer SNaN over QNaN, order C, B, A. */ |
| 207 | + s->phycr = value & ~(s->phycr & ASPEED_MII_PHYCR_FIRE); | 152 | if (is_snan(c_cls)) { |
| 208 | + break; | 153 | return 2; |
| 209 | + case 0x4: | 154 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 210 | + s->phydata = value & ~(0xffff | ASPEED_MII_PHYDATA_IDLE); | 155 | * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns |
| 211 | + break; | 156 | * an input NaN if we have one (ie c). |
| 212 | + default: | 157 | */ |
| 213 | + g_assert_not_reached(); | 158 | - if (infzero) { |
| 214 | + } | 159 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); |
| 215 | + | 160 | - return 2; |
| 216 | + aspeed_mii_transition(s, !!(s->phycr & ASPEED_MII_PHYCR_FIRE)); | 161 | - } |
| 217 | + aspeed_mii_do_phy_ctl(s); | 162 | if (status->use_first_nan) { |
| 218 | +} | 163 | if (is_nan(a_cls)) { |
| 219 | + | 164 | return 0; |
| 220 | +static const MemoryRegionOps aspeed_mii_ops = { | ||
| 221 | + .read = aspeed_mii_read, | ||
| 222 | + .write = aspeed_mii_write, | ||
| 223 | + .valid.min_access_size = 4, | ||
| 224 | + .valid.max_access_size = 4, | ||
| 225 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
| 226 | +}; | ||
| 227 | + | ||
| 228 | +static void aspeed_mii_reset(DeviceState *dev) | ||
| 229 | +{ | ||
| 230 | + AspeedMiiState *s = ASPEED_MII(dev); | ||
| 231 | + | ||
| 232 | + s->phycr = 0; | ||
| 233 | + s->phydata = 0; | ||
| 234 | + | ||
| 235 | + aspeed_mii_transition(s, !!(s->phycr & ASPEED_MII_PHYCR_FIRE)); | ||
| 236 | +}; | ||
| 237 | + | ||
| 238 | +static void aspeed_mii_realize(DeviceState *dev, Error **errp) | ||
| 239 | +{ | ||
| 240 | + AspeedMiiState *s = ASPEED_MII(dev); | ||
| 241 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
| 242 | + Object *obj; | ||
| 243 | + Error *local_err = NULL; | ||
| 244 | + | ||
| 245 | + obj = object_property_get_link(OBJECT(dev), "nic", &local_err); | ||
| 246 | + if (!obj) { | ||
| 247 | + error_propagate(errp, local_err); | ||
| 248 | + error_prepend(errp, "required link 'nic' not found: "); | ||
| 249 | + return; | ||
| 250 | + } | ||
| 251 | + | ||
| 252 | + s->nic = FTGMAC100(obj); | ||
| 253 | + | ||
| 254 | + memory_region_init_io(&s->iomem, OBJECT(dev), &aspeed_mii_ops, s, | ||
| 255 | + TYPE_ASPEED_MII, 0x8); | ||
| 256 | + sysbus_init_mmio(sbd, &s->iomem); | ||
| 257 | +} | ||
| 258 | + | ||
| 259 | +static const VMStateDescription vmstate_aspeed_mii = { | ||
| 260 | + .name = TYPE_ASPEED_MII, | ||
| 261 | + .version_id = 1, | ||
| 262 | + .minimum_version_id = 1, | ||
| 263 | + .fields = (VMStateField[]) { | ||
| 264 | + VMSTATE_UINT32(phycr, FTGMAC100State), | ||
| 265 | + VMSTATE_UINT32(phydata, FTGMAC100State), | ||
| 266 | + VMSTATE_END_OF_LIST() | ||
| 267 | + } | ||
| 268 | +}; | ||
| 269 | +static void aspeed_mii_class_init(ObjectClass *klass, void *data) | ||
| 270 | +{ | ||
| 271 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 272 | + | ||
| 273 | + dc->vmsd = &vmstate_aspeed_mii; | ||
| 274 | + dc->reset = aspeed_mii_reset; | ||
| 275 | + dc->realize = aspeed_mii_realize; | ||
| 276 | + dc->desc = "Aspeed MII controller"; | ||
| 277 | +} | ||
| 278 | + | ||
| 279 | +static const TypeInfo aspeed_mii_info = { | ||
| 280 | + .name = TYPE_ASPEED_MII, | ||
| 281 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
| 282 | + .instance_size = sizeof(AspeedMiiState), | ||
| 283 | + .class_init = aspeed_mii_class_init, | ||
| 284 | +}; | ||
| 285 | + | ||
| 286 | static void ftgmac100_register_types(void) | ||
| 287 | { | ||
| 288 | type_register_static(&ftgmac100_info); | ||
| 289 | + type_register_static(&aspeed_mii_info); | ||
| 290 | } | ||
| 291 | |||
| 292 | type_init(ftgmac100_register_types) | ||
| 293 | -- | 165 | -- |
| 294 | 2.20.1 | 166 | 2.34.1 |
| 295 | |||
| 296 | diff view generated by jsdifflib |
| 1 | Switch the cmsdk-apb-dualtimer code away from bottom-half based | 1 | If the target sets default_nan_mode then we're always going to return |
|---|---|---|---|
| 2 | ptimers to the new transaction-based ptimer API. This just requires | 2 | the default NaN, and pickNaNMulAdd() no longer has any side effects. |
| 3 | adding begin/commit calls around the various places that modify the | 3 | For consistency with pickNaN(), check for default_nan_mode before |
| 4 | ptimer state, and using the new ptimer_init() function to create the | 4 | calling pickNaNMulAdd(). |
| 5 | timer. | 5 | |
| 6 | When we convert pickNaNMulAdd() to allow runtime selection of the NaN | ||
| 7 | propagation rule, this means we won't have to make the targets which | ||
| 8 | use default_nan_mode also set a propagation rule. | ||
| 9 | |||
| 10 | Since RiscV always uses default_nan_mode, this allows us to remove | ||
| 11 | its ifdef case from pickNaNMulAdd(). | ||
| 6 | 12 | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 9 | Message-id: 20191008171740.9679-9-peter.maydell@linaro.org | 15 | Message-id: 20241202131347.498124-3-peter.maydell@linaro.org |
| 10 | --- | 16 | --- |
| 11 | hw/timer/cmsdk-apb-dualtimer.c | 14 +++++++++++--- | 17 | fpu/softfloat-parts.c.inc | 8 ++++++-- |
| 12 | 1 file changed, 11 insertions(+), 3 deletions(-) | 18 | fpu/softfloat-specialize.c.inc | 9 +++++++-- |
| 19 | 2 files changed, 13 insertions(+), 4 deletions(-) | ||
| 13 | 20 | ||
| 14 | diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c | 21 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
| 15 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/hw/timer/cmsdk-apb-dualtimer.c | 23 | --- a/fpu/softfloat-parts.c.inc |
| 17 | +++ b/hw/timer/cmsdk-apb-dualtimer.c | 24 | +++ b/fpu/softfloat-parts.c.inc |
| 18 | @@ -XXX,XX +XXX,XX @@ | 25 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
| 19 | #include "qemu/log.h" | 26 | float_raise(float_flag_invalid | float_flag_invalid_imz, s); |
| 20 | #include "trace.h" | ||
| 21 | #include "qapi/error.h" | ||
| 22 | -#include "qemu/main-loop.h" | ||
| 23 | #include "qemu/module.h" | ||
| 24 | #include "hw/sysbus.h" | ||
| 25 | #include "hw/irq.h" | ||
| 26 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m, | ||
| 27 | /* Handle a write to the CONTROL register */ | ||
| 28 | uint32_t changed; | ||
| 29 | |||
| 30 | + ptimer_transaction_begin(m->timer); | ||
| 31 | + | ||
| 32 | newctrl &= R_CONTROL_VALID_MASK; | ||
| 33 | |||
| 34 | changed = m->control ^ newctrl; | ||
| 35 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m, | ||
| 36 | } | 27 | } |
| 37 | 28 | ||
| 38 | m->control = newctrl; | 29 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); |
| 39 | + | 30 | + if (s->default_nan_mode) { |
| 40 | + ptimer_transaction_commit(m->timer); | 31 | + which = 3; |
| 41 | } | 32 | + } else { |
| 42 | 33 | + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); | |
| 43 | static uint64_t cmsdk_apb_dualtimer_read(void *opaque, hwaddr offset, | 34 | + } |
| 44 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_write(void *opaque, hwaddr offset, | 35 | |
| 45 | if (!(m->control & R_CONTROL_SIZE_MASK)) { | 36 | - if (s->default_nan_mode || which == 3) { |
| 46 | value &= 0xffff; | 37 | + if (which == 3) { |
| 47 | } | 38 | parts_default_nan(a, s); |
| 48 | + ptimer_transaction_begin(m->timer); | 39 | return a; |
| 49 | if (!(m->control & R_CONTROL_MODE_MASK)) { | 40 | } |
| 50 | /* | 41 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 51 | * In free-running mode this won't set the limit but will | 42 | index XXXXXXX..XXXXXXX 100644 |
| 52 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_write(void *opaque, hwaddr offset, | 43 | --- a/fpu/softfloat-specialize.c.inc |
| 53 | ptimer_run(m->timer, 1); | 44 | +++ b/fpu/softfloat-specialize.c.inc |
| 54 | } | 45 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, |
| 55 | } | 46 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 56 | + ptimer_transaction_commit(m->timer); | 47 | bool infzero, float_status *status) |
| 57 | break; | 48 | { |
| 58 | case A_TIMER1BGLOAD: | 49 | + /* |
| 59 | /* Set the limit, but not the current count */ | 50 | + * We guarantee not to require the target to tell us how to |
| 60 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_write(void *opaque, hwaddr offset, | 51 | + * pick a NaN if we're always returning the default NaN. |
| 61 | if (!(m->control & R_CONTROL_SIZE_MASK)) { | 52 | + * But if we're not in default-NaN mode then the target must |
| 62 | value &= 0xffff; | 53 | + * specify. |
| 63 | } | 54 | + */ |
| 64 | + ptimer_transaction_begin(m->timer); | 55 | + assert(!status->default_nan_mode); |
| 65 | ptimer_set_limit(m->timer, value, 0); | 56 | #if defined(TARGET_ARM) |
| 66 | + ptimer_transaction_commit(m->timer); | 57 | /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns |
| 67 | break; | 58 | * the default NaN |
| 68 | case A_TIMER1CONTROL: | 59 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 69 | cmsdk_dualtimermod_write_control(m, value); | 60 | } else { |
| 70 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_dualtimermod_reset(CMSDKAPBDualTimerModule *m) | 61 | return 1; |
| 71 | m->intstatus = 0; | 62 | } |
| 72 | m->load = 0; | 63 | -#elif defined(TARGET_RISCV) |
| 73 | m->value = 0xffffffff; | 64 | - return 3; /* default NaN */ |
| 74 | + ptimer_transaction_begin(m->timer); | 65 | #elif defined(TARGET_S390X) |
| 75 | ptimer_stop(m->timer); | 66 | if (infzero) { |
| 76 | /* | 67 | return 3; |
| 77 | * We start in free-running mode, with VALUE at 0xffffffff, and | ||
| 78 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_dualtimermod_reset(CMSDKAPBDualTimerModule *m) | ||
| 79 | */ | ||
| 80 | ptimer_set_limit(m->timer, 0xffff, 1); | ||
| 81 | ptimer_set_freq(m->timer, m->parent->pclk_frq); | ||
| 82 | + ptimer_transaction_commit(m->timer); | ||
| 83 | } | ||
| 84 | |||
| 85 | static void cmsdk_apb_dualtimer_reset(DeviceState *dev) | ||
| 86 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp) | ||
| 87 | |||
| 88 | for (i = 0; i < ARRAY_SIZE(s->timermod); i++) { | ||
| 89 | CMSDKAPBDualTimerModule *m = &s->timermod[i]; | ||
| 90 | - QEMUBH *bh = qemu_bh_new(cmsdk_dualtimermod_tick, m); | ||
| 91 | |||
| 92 | m->parent = s; | ||
| 93 | - m->timer = ptimer_init_with_bh(bh, | ||
| 94 | + m->timer = ptimer_init(cmsdk_dualtimermod_tick, m, | ||
| 95 | PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | | ||
| 96 | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | | ||
| 97 | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | | ||
| 98 | -- | 68 | -- |
| 99 | 2.20.1 | 69 | 2.34.1 |
| 100 | |||
| 101 | diff view generated by jsdifflib |
| 1 | Factor out the implementation of SYS_ISTTY via the new function | 1 | IEEE 758 does not define a fixed rule for what NaN to return in |
|---|---|---|---|
| 2 | tables. | 2 | the case of a fused multiply-add of inf * 0 + NaN. Different |
| 3 | architectures thus do different things: | ||
| 4 | * some return the default NaN | ||
| 5 | * some return the input NaN | ||
| 6 | * Arm returns the default NaN if the input NaN is quiet, | ||
| 7 | and the input NaN if it is signalling | ||
| 8 | |||
| 9 | We want to make this logic be runtime selected rather than | ||
| 10 | hardcoded into the binary, because: | ||
| 11 | * this will let us have multiple targets in one QEMU binary | ||
| 12 | * the Arm FEAT_AFP architectural feature includes letting | ||
| 13 | the guest select a NaN propagation rule at runtime | ||
| 14 | |||
| 15 | In this commit we add an enum for the propagation rule, the field in | ||
| 16 | float_status, and the corresponding getters and setters. We change | ||
| 17 | pickNaNMulAdd to honour this, but because all targets still leave | ||
| 18 | this field at its default 0 value, the fallback logic will pick the | ||
| 19 | rule type with the old ifdef ladder. | ||
| 20 | |||
| 21 | Note that four architectures both use the muladd softfloat functions | ||
| 22 | and did not have a branch of the ifdef ladder to specify their | ||
| 23 | behaviour (and so were ending up with the "default" case, probably | ||
| 24 | wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set | ||
| 25 | default_nan_mode, and so will never get into pickNaNMulAdd(). For | ||
| 26 | HPPA and i386 we retain the same behaviour as the old default-case, | ||
| 27 | which is to not ever return the default NaN. This might not be | ||
| 28 | correct but it is not a behaviour change. | ||
| 3 | 29 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 31 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 6 | Message-id: 20190916141544.17540-11-peter.maydell@linaro.org | 32 | Message-id: 20241202131347.498124-4-peter.maydell@linaro.org |
| 7 | --- | 33 | --- |
| 8 | target/arm/arm-semi.c | 20 +++++++++++++++----- | 34 | include/fpu/softfloat-helpers.h | 11 ++++ |
| 9 | 1 file changed, 15 insertions(+), 5 deletions(-) | 35 | include/fpu/softfloat-types.h | 23 +++++++++ |
| 10 | 36 | fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++----------- | |
| 11 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 37 | 3 files changed, 95 insertions(+), 30 deletions(-) |
| 38 | |||
| 39 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h | ||
| 12 | index XXXXXXX..XXXXXXX 100644 | 40 | index XXXXXXX..XXXXXXX 100644 |
| 13 | --- a/target/arm/arm-semi.c | 41 | --- a/include/fpu/softfloat-helpers.h |
| 14 | +++ b/target/arm/arm-semi.c | 42 | +++ b/include/fpu/softfloat-helpers.h |
| 15 | @@ -XXX,XX +XXX,XX @@ typedef uint32_t sys_writefn(ARMCPU *cpu, GuestFD *gf, | 43 | @@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, |
| 16 | target_ulong buf, uint32_t len); | 44 | status->float_2nan_prop_rule = rule; |
| 17 | typedef uint32_t sys_readfn(ARMCPU *cpu, GuestFD *gf, | 45 | } |
| 18 | target_ulong buf, uint32_t len); | 46 | |
| 19 | +typedef uint32_t sys_isattyfn(ARMCPU *cpu, GuestFD *gf); | 47 | +static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, |
| 20 | 48 | + float_status *status) | |
| 21 | static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) | 49 | +{ |
| 50 | + status->float_infzeronan_rule = rule; | ||
| 51 | +} | ||
| 52 | + | ||
| 53 | static inline void set_flush_to_zero(bool val, float_status *status) | ||
| 22 | { | 54 | { |
| 23 | @@ -XXX,XX +XXX,XX @@ static uint32_t host_readfn(ARMCPU *cpu, GuestFD *gf, | 55 | status->flush_to_zero = val; |
| 24 | return len - ret; | 56 | @@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) |
| 57 | return status->float_2nan_prop_rule; | ||
| 25 | } | 58 | } |
| 26 | 59 | ||
| 27 | +static uint32_t host_isattyfn(ARMCPU *cpu, GuestFD *gf) | 60 | +static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) |
| 28 | +{ | 61 | +{ |
| 29 | + return isatty(gf->hostfd); | 62 | + return status->float_infzeronan_rule; |
| 30 | +} | 63 | +} |
| 31 | + | 64 | + |
| 32 | static uint32_t gdb_closefn(ARMCPU *cpu, GuestFD *gf) | 65 | static inline bool get_flush_to_zero(float_status *status) |
| 33 | { | 66 | { |
| 34 | return arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); | 67 | return status->flush_to_zero; |
| 35 | @@ -XXX,XX +XXX,XX @@ static uint32_t gdb_readfn(ARMCPU *cpu, GuestFD *gf, | 68 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h |
| 36 | gf->hostfd, buf, len); | 69 | index XXXXXXX..XXXXXXX 100644 |
| 37 | } | 70 | --- a/include/fpu/softfloat-types.h |
| 38 | 71 | +++ b/include/fpu/softfloat-types.h | |
| 39 | +static uint32_t gdb_isattyfn(ARMCPU *cpu, GuestFD *gf) | 72 | @@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) { |
| 40 | +{ | 73 | float_2nan_prop_x87, |
| 41 | + return arm_gdb_syscall(cpu, arm_semi_cb, "isatty,%x", gf->hostfd); | 74 | } Float2NaNPropRule; |
| 42 | +} | 75 | |
| 43 | + | 76 | +/* |
| 44 | typedef struct GuestFDFunctions { | 77 | + * Rule for result of fused multiply-add 0 * Inf + NaN. |
| 45 | sys_closefn *closefn; | 78 | + * This must be a NaN, but implementations differ on whether this |
| 46 | sys_writefn *writefn; | 79 | + * is the input NaN or the default NaN. |
| 47 | sys_readfn *readfn; | 80 | + * |
| 48 | + sys_isattyfn *isattyfn; | 81 | + * You don't need to set this if default_nan_mode is enabled. |
| 49 | } GuestFDFunctions; | 82 | + * When not in default-NaN mode, it is an error for the target |
| 50 | 83 | + * not to set the rule in float_status if it uses muladd, and we | |
| 51 | static const GuestFDFunctions guestfd_fns[] = { | 84 | + * will assert if we need to handle an input NaN and no rule was |
| 52 | @@ -XXX,XX +XXX,XX @@ static const GuestFDFunctions guestfd_fns[] = { | 85 | + * selected. |
| 53 | .closefn = host_closefn, | 86 | + */ |
| 54 | .writefn = host_writefn, | 87 | +typedef enum __attribute__((__packed__)) { |
| 55 | .readfn = host_readfn, | 88 | + /* No propagation rule specified */ |
| 56 | + .isattyfn = host_isattyfn, | 89 | + float_infzeronan_none = 0, |
| 57 | }, | 90 | + /* Result is never the default NaN (so always the input NaN) */ |
| 58 | [GuestFDGDB] = { | 91 | + float_infzeronan_dnan_never, |
| 59 | .closefn = gdb_closefn, | 92 | + /* Result is always the default NaN */ |
| 60 | .writefn = gdb_writefn, | 93 | + float_infzeronan_dnan_always, |
| 61 | .readfn = gdb_readfn, | 94 | + /* Result is the default NaN if the input NaN is quiet */ |
| 62 | + .isattyfn = gdb_isattyfn, | 95 | + float_infzeronan_dnan_if_qnan, |
| 63 | }, | 96 | +} FloatInfZeroNaNRule; |
| 64 | }; | 97 | + |
| 65 | 98 | /* | |
| 66 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | 99 | * Floating Point Status. Individual architectures may maintain |
| 67 | return set_swi_errno(env, -1); | 100 | * several versions of float_status for different functions. The |
| 101 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { | ||
| 102 | FloatRoundMode float_rounding_mode; | ||
| 103 | FloatX80RoundPrec floatx80_rounding_precision; | ||
| 104 | Float2NaNPropRule float_2nan_prop_rule; | ||
| 105 | + FloatInfZeroNaNRule float_infzeronan_rule; | ||
| 106 | bool tininess_before_rounding; | ||
| 107 | /* should denormalised results go to zero and set the inexact flag? */ | ||
| 108 | bool flush_to_zero; | ||
| 109 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 110 | index XXXXXXX..XXXXXXX 100644 | ||
| 111 | --- a/fpu/softfloat-specialize.c.inc | ||
| 112 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 113 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
| 114 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 115 | bool infzero, float_status *status) | ||
| 116 | { | ||
| 117 | + FloatInfZeroNaNRule rule = status->float_infzeronan_rule; | ||
| 118 | + | ||
| 119 | /* | ||
| 120 | * We guarantee not to require the target to tell us how to | ||
| 121 | * pick a NaN if we're always returning the default NaN. | ||
| 122 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 123 | * specify. | ||
| 124 | */ | ||
| 125 | assert(!status->default_nan_mode); | ||
| 126 | + | ||
| 127 | + if (rule == float_infzeronan_none) { | ||
| 128 | + /* | ||
| 129 | + * Temporarily fall back to ifdef ladder | ||
| 130 | + */ | ||
| 131 | #if defined(TARGET_ARM) | ||
| 132 | - /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns | ||
| 133 | - * the default NaN | ||
| 134 | - */ | ||
| 135 | - if (infzero && is_qnan(c_cls)) { | ||
| 136 | - return 3; | ||
| 137 | + /* | ||
| 138 | + * For ARM, the (inf,zero,qnan) case returns the default NaN, | ||
| 139 | + * but (inf,zero,snan) returns the input NaN. | ||
| 140 | + */ | ||
| 141 | + rule = float_infzeronan_dnan_if_qnan; | ||
| 142 | +#elif defined(TARGET_MIPS) | ||
| 143 | + if (snan_bit_is_one(status)) { | ||
| 144 | + /* | ||
| 145 | + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
| 146 | + * case sets InvalidOp and returns the default NaN | ||
| 147 | + */ | ||
| 148 | + rule = float_infzeronan_dnan_always; | ||
| 149 | + } else { | ||
| 150 | + /* | ||
| 151 | + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 152 | + * case sets InvalidOp and returns the input value 'c' | ||
| 153 | + */ | ||
| 154 | + rule = float_infzeronan_dnan_never; | ||
| 155 | + } | ||
| 156 | +#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ | ||
| 157 | + defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
| 158 | + defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
| 159 | + /* | ||
| 160 | + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 161 | + * case sets InvalidOp and returns the input value 'c' | ||
| 162 | + */ | ||
| 163 | + /* | ||
| 164 | + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
| 165 | + * to return an input NaN if we have one (ie c) rather than generating | ||
| 166 | + * a default NaN | ||
| 167 | + */ | ||
| 168 | + rule = float_infzeronan_dnan_never; | ||
| 169 | +#elif defined(TARGET_S390X) | ||
| 170 | + rule = float_infzeronan_dnan_always; | ||
| 171 | +#endif | ||
| 172 | } | ||
| 173 | |||
| 174 | + if (infzero) { | ||
| 175 | + /* | ||
| 176 | + * Inf * 0 + NaN -- some implementations return the default NaN here, | ||
| 177 | + * and some return the input NaN. | ||
| 178 | + */ | ||
| 179 | + switch (rule) { | ||
| 180 | + case float_infzeronan_dnan_never: | ||
| 181 | + return 2; | ||
| 182 | + case float_infzeronan_dnan_always: | ||
| 183 | + return 3; | ||
| 184 | + case float_infzeronan_dnan_if_qnan: | ||
| 185 | + return is_qnan(c_cls) ? 3 : 2; | ||
| 186 | + default: | ||
| 187 | + g_assert_not_reached(); | ||
| 188 | + } | ||
| 189 | + } | ||
| 190 | + | ||
| 191 | +#if defined(TARGET_ARM) | ||
| 192 | + | ||
| 193 | /* This looks different from the ARM ARM pseudocode, because the ARM ARM | ||
| 194 | * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. | ||
| 195 | */ | ||
| 196 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 197 | } | ||
| 198 | #elif defined(TARGET_MIPS) | ||
| 199 | if (snan_bit_is_one(status)) { | ||
| 200 | - /* | ||
| 201 | - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
| 202 | - * case sets InvalidOp and returns the default NaN | ||
| 203 | - */ | ||
| 204 | - if (infzero) { | ||
| 205 | - return 3; | ||
| 206 | - } | ||
| 207 | /* Prefer sNaN over qNaN, in the a, b, c order. */ | ||
| 208 | if (is_snan(a_cls)) { | ||
| 209 | return 0; | ||
| 210 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 211 | return 2; | ||
| 68 | } | 212 | } |
| 69 | 213 | } else { | |
| 70 | - if (use_gdb_syscalls()) { | 214 | - /* |
| 71 | - return arm_gdb_syscall(cpu, arm_semi_cb, "isatty,%x", gf->hostfd); | 215 | - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) |
| 72 | - } else { | 216 | - * case sets InvalidOp and returns the input value 'c' |
| 73 | - return isatty(gf->hostfd); | 217 | - */ |
| 74 | - } | 218 | /* Prefer sNaN over qNaN, in the c, a, b order. */ |
| 75 | + return guestfd_fns[gf->type].isattyfn(cpu, gf); | 219 | if (is_snan(c_cls)) { |
| 76 | case TARGET_SYS_SEEK: | 220 | return 2; |
| 77 | GET_ARG(0); | 221 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 78 | GET_ARG(1); | 222 | } |
| 223 | } | ||
| 224 | #elif defined(TARGET_LOONGARCH64) | ||
| 225 | - /* | ||
| 226 | - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 227 | - * case sets InvalidOp and returns the input value 'c' | ||
| 228 | - */ | ||
| 229 | - | ||
| 230 | /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
| 231 | if (is_snan(c_cls)) { | ||
| 232 | return 2; | ||
| 233 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 234 | return 1; | ||
| 235 | } | ||
| 236 | #elif defined(TARGET_PPC) | ||
| 237 | - /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
| 238 | - * to return an input NaN if we have one (ie c) rather than generating | ||
| 239 | - * a default NaN | ||
| 240 | - */ | ||
| 241 | - | ||
| 242 | /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
| 243 | * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
| 244 | */ | ||
| 245 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 246 | return 1; | ||
| 247 | } | ||
| 248 | #elif defined(TARGET_S390X) | ||
| 249 | - if (infzero) { | ||
| 250 | - return 3; | ||
| 251 | - } | ||
| 252 | - | ||
| 253 | if (is_snan(a_cls)) { | ||
| 254 | return 0; | ||
| 255 | } else if (is_snan(b_cls)) { | ||
| 79 | -- | 256 | -- |
| 80 | 2.20.1 | 257 | 2.34.1 |
| 81 | |||
| 82 | diff view generated by jsdifflib |
| 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | Explicitly set a rule in the softfloat tests for the inf-zero-nan |
|---|---|---|---|
| 2 | muladd special case. In meson.build we put -DTARGET_ARM in fpcflags, | ||
| 3 | and so we should select here the Arm rule of | ||
| 4 | float_infzeronan_dnan_if_qnan. | ||
| 2 | 5 | ||
| 3 | Various logging improvements as once: | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 4 | - Use 0x prefix for hex numbers | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 5 | - Display value written during write accesses | 8 | Message-id: 20241202131347.498124-5-peter.maydell@linaro.org |
| 6 | - Move some logs from GUEST_ERROR to UNIMP | 9 | --- |
| 10 | tests/fp/fp-bench.c | 5 +++++ | ||
| 11 | tests/fp/fp-test.c | 5 +++++ | ||
| 12 | 2 files changed, 10 insertions(+) | ||
| 7 | 13 | ||
| 8 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 14 | diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c |
| 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 11 | Reviewed-by: Cleber Rosa <crosa@redhat.com> | ||
| 12 | Message-id: 20190926173428.10713-3-f4bug@amsat.org | ||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | --- | ||
| 15 | hw/char/bcm2835_aux.c | 5 +++-- | ||
| 16 | hw/dma/bcm2835_dma.c | 8 ++++---- | ||
| 17 | hw/intc/bcm2836_control.c | 7 ++++--- | ||
| 18 | hw/misc/bcm2835_mbox.c | 7 ++++--- | ||
| 19 | hw/misc/bcm2835_property.c | 16 ++++++++++------ | ||
| 20 | 5 files changed, 25 insertions(+), 18 deletions(-) | ||
| 21 | |||
| 22 | diff --git a/hw/char/bcm2835_aux.c b/hw/char/bcm2835_aux.c | ||
| 23 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 24 | --- a/hw/char/bcm2835_aux.c | 16 | --- a/tests/fp/fp-bench.c |
| 25 | +++ b/hw/char/bcm2835_aux.c | 17 | +++ b/tests/fp/fp-bench.c |
| 26 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_aux_write(void *opaque, hwaddr offset, uint64_t value, | 18 | @@ -XXX,XX +XXX,XX @@ static void run_bench(void) |
| 27 | switch (offset) { | 19 | { |
| 28 | case AUX_ENABLES: | 20 | bench_func_t f; |
| 29 | if (value != 1) { | 21 | |
| 30 | - qemu_log_mask(LOG_UNIMP, "%s: unsupported attempt to enable SPI " | 22 | + /* |
| 31 | - "or disable UART\n", __func__); | 23 | + * These implementation-defined choices for various things IEEE |
| 32 | + qemu_log_mask(LOG_UNIMP, "%s: unsupported attempt to enable SPI" | 24 | + * doesn't specify match those used by the Arm architecture. |
| 33 | + " or disable UART: 0x%"PRIx64"\n", | 25 | + */ |
| 34 | + __func__, value); | 26 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); |
| 35 | } | 27 | + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); |
| 36 | break; | 28 | |
| 37 | 29 | f = bench_funcs[operation][precision]; | |
| 38 | diff --git a/hw/dma/bcm2835_dma.c b/hw/dma/bcm2835_dma.c | 30 | g_assert(f); |
| 31 | diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c | ||
| 39 | index XXXXXXX..XXXXXXX 100644 | 32 | index XXXXXXX..XXXXXXX 100644 |
| 40 | --- a/hw/dma/bcm2835_dma.c | 33 | --- a/tests/fp/fp-test.c |
| 41 | +++ b/hw/dma/bcm2835_dma.c | 34 | +++ b/tests/fp/fp-test.c |
| 42 | @@ -XXX,XX +XXX,XX @@ static uint64_t bcm2835_dma_read(BCM2835DMAState *s, hwaddr offset, | 35 | @@ -XXX,XX +XXX,XX @@ void run_test(void) |
| 43 | res = ch->debug; | 36 | { |
| 44 | break; | 37 | unsigned int i; |
| 45 | default: | 38 | |
| 46 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", | 39 | + /* |
| 47 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n", | 40 | + * These implementation-defined choices for various things IEEE |
| 48 | __func__, offset); | 41 | + * doesn't specify match those used by the Arm architecture. |
| 49 | break; | 42 | + */ |
| 50 | } | 43 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); |
| 51 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_dma_write(BCM2835DMAState *s, hwaddr offset, | 44 | + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); |
| 52 | ch->debug = value; | 45 | |
| 53 | break; | 46 | genCases_setLevel(test_level); |
| 54 | default: | 47 | verCases_maxErrorCount = n_max_errors; |
| 55 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", | ||
| 56 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n", | ||
| 57 | __func__, offset); | ||
| 58 | break; | ||
| 59 | } | ||
| 60 | @@ -XXX,XX +XXX,XX @@ static uint64_t bcm2835_dma0_read(void *opaque, hwaddr offset, unsigned size) | ||
| 61 | case BCM2708_DMA_ENABLE: | ||
| 62 | return s->enable; | ||
| 63 | default: | ||
| 64 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", | ||
| 65 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n", | ||
| 66 | __func__, offset); | ||
| 67 | return 0; | ||
| 68 | } | ||
| 69 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_dma0_write(void *opaque, hwaddr offset, uint64_t value, | ||
| 70 | s->enable = (value & 0xffff); | ||
| 71 | break; | ||
| 72 | default: | ||
| 73 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", | ||
| 74 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n", | ||
| 75 | __func__, offset); | ||
| 76 | } | ||
| 77 | } | ||
| 78 | diff --git a/hw/intc/bcm2836_control.c b/hw/intc/bcm2836_control.c | ||
| 79 | index XXXXXXX..XXXXXXX 100644 | ||
| 80 | --- a/hw/intc/bcm2836_control.c | ||
| 81 | +++ b/hw/intc/bcm2836_control.c | ||
| 82 | @@ -XXX,XX +XXX,XX @@ static uint64_t bcm2836_control_read(void *opaque, hwaddr offset, unsigned size) | ||
| 83 | } else if (offset >= REG_MBOX0_RDCLR && offset < REG_LIMIT) { | ||
| 84 | return s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2]; | ||
| 85 | } else { | ||
| 86 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", | ||
| 87 | + qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx"\n", | ||
| 88 | __func__, offset); | ||
| 89 | return 0; | ||
| 90 | } | ||
| 91 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_control_write(void *opaque, hwaddr offset, | ||
| 92 | } else if (offset >= REG_MBOX0_RDCLR && offset < REG_LIMIT) { | ||
| 93 | s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2] &= ~val; | ||
| 94 | } else { | ||
| 95 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", | ||
| 96 | - __func__, offset); | ||
| 97 | + qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx | ||
| 98 | + " value 0x%"PRIx64"\n", | ||
| 99 | + __func__, offset, val); | ||
| 100 | return; | ||
| 101 | } | ||
| 102 | |||
| 103 | diff --git a/hw/misc/bcm2835_mbox.c b/hw/misc/bcm2835_mbox.c | ||
| 104 | index XXXXXXX..XXXXXXX 100644 | ||
| 105 | --- a/hw/misc/bcm2835_mbox.c | ||
| 106 | +++ b/hw/misc/bcm2835_mbox.c | ||
| 107 | @@ -XXX,XX +XXX,XX @@ static uint64_t bcm2835_mbox_read(void *opaque, hwaddr offset, unsigned size) | ||
| 108 | break; | ||
| 109 | |||
| 110 | default: | ||
| 111 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", | ||
| 112 | + qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx"\n", | ||
| 113 | __func__, offset); | ||
| 114 | return 0; | ||
| 115 | } | ||
| 116 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_mbox_write(void *opaque, hwaddr offset, | ||
| 117 | break; | ||
| 118 | |||
| 119 | default: | ||
| 120 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", | ||
| 121 | - __func__, offset); | ||
| 122 | + qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx | ||
| 123 | + " value 0x%"PRIx64"\n", | ||
| 124 | + __func__, offset, value); | ||
| 125 | return; | ||
| 126 | } | ||
| 127 | |||
| 128 | diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c | ||
| 129 | index XXXXXXX..XXXXXXX 100644 | ||
| 130 | --- a/hw/misc/bcm2835_property.c | ||
| 131 | +++ b/hw/misc/bcm2835_property.c | ||
| 132 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) | ||
| 133 | break; | ||
| 134 | case 0x00010001: /* Get board model */ | ||
| 135 | qemu_log_mask(LOG_UNIMP, | ||
| 136 | - "bcm2835_property: %x get board model NYI\n", tag); | ||
| 137 | + "bcm2835_property: 0x%08x get board model NYI\n", | ||
| 138 | + tag); | ||
| 139 | resplen = 4; | ||
| 140 | break; | ||
| 141 | case 0x00010002: /* Get board revision */ | ||
| 142 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) | ||
| 143 | break; | ||
| 144 | case 0x00010004: /* Get board serial */ | ||
| 145 | qemu_log_mask(LOG_UNIMP, | ||
| 146 | - "bcm2835_property: %x get board serial NYI\n", tag); | ||
| 147 | + "bcm2835_property: 0x%08x get board serial NYI\n", | ||
| 148 | + tag); | ||
| 149 | resplen = 8; | ||
| 150 | break; | ||
| 151 | case 0x00010005: /* Get ARM memory */ | ||
| 152 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) | ||
| 153 | |||
| 154 | case 0x00038001: /* Set clock state */ | ||
| 155 | qemu_log_mask(LOG_UNIMP, | ||
| 156 | - "bcm2835_property: %x set clock state NYI\n", tag); | ||
| 157 | + "bcm2835_property: 0x%08x set clock state NYI\n", | ||
| 158 | + tag); | ||
| 159 | resplen = 8; | ||
| 160 | break; | ||
| 161 | |||
| 162 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) | ||
| 163 | case 0x00038004: /* Set max clock rate */ | ||
| 164 | case 0x00038007: /* Set min clock rate */ | ||
| 165 | qemu_log_mask(LOG_UNIMP, | ||
| 166 | - "bcm2835_property: %x set clock rates NYI\n", tag); | ||
| 167 | + "bcm2835_property: 0x%08x set clock rate NYI\n", | ||
| 168 | + tag); | ||
| 169 | resplen = 8; | ||
| 170 | break; | ||
| 171 | |||
| 172 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) | ||
| 173 | break; | ||
| 174 | |||
| 175 | default: | ||
| 176 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
| 177 | - "bcm2835_property: unhandled tag %08x\n", tag); | ||
| 178 | + qemu_log_mask(LOG_UNIMP, | ||
| 179 | + "bcm2835_property: unhandled tag 0x%08x\n", tag); | ||
| 180 | break; | ||
| 181 | } | ||
| 182 | |||
| 183 | -- | 48 | -- |
| 184 | 2.20.1 | 49 | 2.34.1 |
| 185 | |||
| 186 | diff view generated by jsdifflib |
| 1 | From: Cédric Le Goater <clg@kaod.org> | 1 | Set the FloatInfZeroNaNRule explicitly for the Arm target, |
|---|---|---|---|
| 2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
| 2 | 3 | ||
| 3 | The AST2600 SoC SMC controller is a SPI only controller now and has a | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 4 | few extensions which we will need to take into account when SW | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 5 | requires it. This is enough to support u-boot and Linux. | 6 | Message-id: 20241202131347.498124-6-peter.maydell@linaro.org |
| 7 | --- | ||
| 8 | target/arm/cpu.c | 3 +++ | ||
| 9 | fpu/softfloat-specialize.c.inc | 8 +------- | ||
| 10 | 2 files changed, 4 insertions(+), 7 deletions(-) | ||
| 6 | 11 | ||
| 7 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 12 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
| 8 | Acked-by: Joel Stanley <joel@jms.id.au> | ||
| 9 | Message-id: 20190925143248.10000-14-clg@kaod.org | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | hw/ssi/aspeed_smc.c | 132 ++++++++++++++++++++++++++++++++++++++++++-- | ||
| 13 | 1 file changed, 128 insertions(+), 4 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/hw/ssi/aspeed_smc.c | 14 | --- a/target/arm/cpu.c |
| 18 | +++ b/hw/ssi/aspeed_smc.c | 15 | +++ b/target/arm/cpu.c |
| 19 | @@ -XXX,XX +XXX,XX @@ | 16 | @@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
| 20 | #include "qemu/error-report.h" | 17 | * * tininess-before-rounding |
| 21 | #include "qapi/error.h" | 18 | * * 2-input NaN propagation prefers SNaN over QNaN, and then |
| 22 | #include "exec/address-spaces.h" | 19 | * operand A over operand B (see FPProcessNaNs() pseudocode) |
| 23 | +#include "qemu/units.h" | 20 | + * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, |
| 24 | 21 | + * and the input NaN if it is signalling | |
| 25 | #include "hw/irq.h" | 22 | */ |
| 26 | #include "hw/qdev-properties.h" | 23 | static void arm_set_default_fp_behaviours(float_status *s) |
| 27 | @@ -XXX,XX +XXX,XX @@ | 24 | { |
| 28 | #define CONF_FLASH_TYPE0 0 | 25 | set_float_detect_tininess(float_tininess_before_rounding, s); |
| 29 | #define CONF_FLASH_TYPE_NOR 0x0 | 26 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); |
| 30 | #define CONF_FLASH_TYPE_NAND 0x1 | 27 | + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); |
| 31 | -#define CONF_FLASH_TYPE_SPI 0x2 | ||
| 32 | +#define CONF_FLASH_TYPE_SPI 0x2 /* AST2600 is SPI only */ | ||
| 33 | |||
| 34 | /* CE Control Register */ | ||
| 35 | #define R_CE_CTRL (0x04 / 4) | ||
| 36 | @@ -XXX,XX +XXX,XX @@ | ||
| 37 | |||
| 38 | /* CEx Control Register */ | ||
| 39 | #define R_CTRL0 (0x10 / 4) | ||
| 40 | +#define CTRL_IO_QPI (1 << 31) | ||
| 41 | +#define CTRL_IO_QUAD_DATA (1 << 30) | ||
| 42 | #define CTRL_IO_DUAL_DATA (1 << 29) | ||
| 43 | #define CTRL_IO_DUAL_ADDR_DATA (1 << 28) /* Includes dummies */ | ||
| 44 | +#define CTRL_IO_QUAD_ADDR_DATA (1 << 28) /* Includes dummies */ | ||
| 45 | #define CTRL_CMD_SHIFT 16 | ||
| 46 | #define CTRL_CMD_MASK 0xff | ||
| 47 | #define CTRL_DUMMY_HIGH_SHIFT 14 | ||
| 48 | @@ -XXX,XX +XXX,XX @@ | ||
| 49 | /* Misc Control Register #2 */ | ||
| 50 | #define R_TIMINGS (0x94 / 4) | ||
| 51 | |||
| 52 | -/* SPI controller registers and bits */ | ||
| 53 | +/* SPI controller registers and bits (AST2400) */ | ||
| 54 | #define R_SPI_CONF (0x00 / 4) | ||
| 55 | #define SPI_CONF_ENABLE_W0 0 | ||
| 56 | #define R_SPI_CTRL0 (0x4 / 4) | ||
| 57 | @@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s, | ||
| 58 | static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, uint32_t reg, | ||
| 59 | AspeedSegments *seg); | ||
| 60 | |||
| 61 | +/* | ||
| 62 | + * AST2600 definitions | ||
| 63 | + */ | ||
| 64 | +#define ASPEED26_SOC_FMC_FLASH_BASE 0x20000000 | ||
| 65 | +#define ASPEED26_SOC_SPI_FLASH_BASE 0x30000000 | ||
| 66 | +#define ASPEED26_SOC_SPI2_FLASH_BASE 0x50000000 | ||
| 67 | + | ||
| 68 | +static const AspeedSegments aspeed_segments_ast2600_fmc[] = { | ||
| 69 | + { 0x0, 128 * MiB }, /* start address is readonly */ | ||
| 70 | + { 0x0, 0 }, /* disabled */ | ||
| 71 | + { 0x0, 0 }, /* disabled */ | ||
| 72 | +}; | ||
| 73 | + | ||
| 74 | +static const AspeedSegments aspeed_segments_ast2600_spi1[] = { | ||
| 75 | + { 0x0, 128 * MiB }, /* start address is readonly */ | ||
| 76 | + { 0x0, 0 }, /* disabled */ | ||
| 77 | +}; | ||
| 78 | + | ||
| 79 | +static const AspeedSegments aspeed_segments_ast2600_spi2[] = { | ||
| 80 | + { 0x0, 128 * MiB }, /* start address is readonly */ | ||
| 81 | + { 0x0, 0 }, /* disabled */ | ||
| 82 | + { 0x0, 0 }, /* disabled */ | ||
| 83 | +}; | ||
| 84 | + | ||
| 85 | +static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s, | ||
| 86 | + const AspeedSegments *seg); | ||
| 87 | +static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s, | ||
| 88 | + uint32_t reg, AspeedSegments *seg); | ||
| 89 | + | ||
| 90 | static const AspeedSMCController controllers[] = { | ||
| 91 | { | ||
| 92 | .name = "aspeed.smc-ast2400", | ||
| 93 | @@ -XXX,XX +XXX,XX @@ static const AspeedSMCController controllers[] = { | ||
| 94 | .nregs = ASPEED_SMC_R_MAX, | ||
| 95 | .segment_to_reg = aspeed_smc_segment_to_reg, | ||
| 96 | .reg_to_segment = aspeed_smc_reg_to_segment, | ||
| 97 | + }, { | ||
| 98 | + .name = "aspeed.fmc-ast2600", | ||
| 99 | + .r_conf = R_CONF, | ||
| 100 | + .r_ce_ctrl = R_CE_CTRL, | ||
| 101 | + .r_ctrl0 = R_CTRL0, | ||
| 102 | + .r_timings = R_TIMINGS, | ||
| 103 | + .conf_enable_w0 = CONF_ENABLE_W0, | ||
| 104 | + .max_slaves = 3, | ||
| 105 | + .segments = aspeed_segments_ast2600_fmc, | ||
| 106 | + .flash_window_base = ASPEED26_SOC_FMC_FLASH_BASE, | ||
| 107 | + .flash_window_size = 0x10000000, | ||
| 108 | + .has_dma = true, | ||
| 109 | + .nregs = ASPEED_SMC_R_MAX, | ||
| 110 | + .segment_to_reg = aspeed_2600_smc_segment_to_reg, | ||
| 111 | + .reg_to_segment = aspeed_2600_smc_reg_to_segment, | ||
| 112 | + }, { | ||
| 113 | + .name = "aspeed.spi1-ast2600", | ||
| 114 | + .r_conf = R_CONF, | ||
| 115 | + .r_ce_ctrl = R_CE_CTRL, | ||
| 116 | + .r_ctrl0 = R_CTRL0, | ||
| 117 | + .r_timings = R_TIMINGS, | ||
| 118 | + .conf_enable_w0 = CONF_ENABLE_W0, | ||
| 119 | + .max_slaves = 2, | ||
| 120 | + .segments = aspeed_segments_ast2600_spi1, | ||
| 121 | + .flash_window_base = ASPEED26_SOC_SPI_FLASH_BASE, | ||
| 122 | + .flash_window_size = 0x10000000, | ||
| 123 | + .has_dma = false, | ||
| 124 | + .nregs = ASPEED_SMC_R_MAX, | ||
| 125 | + .segment_to_reg = aspeed_2600_smc_segment_to_reg, | ||
| 126 | + .reg_to_segment = aspeed_2600_smc_reg_to_segment, | ||
| 127 | + }, { | ||
| 128 | + .name = "aspeed.spi2-ast2600", | ||
| 129 | + .r_conf = R_CONF, | ||
| 130 | + .r_ce_ctrl = R_CE_CTRL, | ||
| 131 | + .r_ctrl0 = R_CTRL0, | ||
| 132 | + .r_timings = R_TIMINGS, | ||
| 133 | + .conf_enable_w0 = CONF_ENABLE_W0, | ||
| 134 | + .max_slaves = 3, | ||
| 135 | + .segments = aspeed_segments_ast2600_spi2, | ||
| 136 | + .flash_window_base = ASPEED26_SOC_SPI2_FLASH_BASE, | ||
| 137 | + .flash_window_size = 0x10000000, | ||
| 138 | + .has_dma = false, | ||
| 139 | + .nregs = ASPEED_SMC_R_MAX, | ||
| 140 | + .segment_to_reg = aspeed_2600_smc_segment_to_reg, | ||
| 141 | + .reg_to_segment = aspeed_2600_smc_reg_to_segment, | ||
| 142 | }, | ||
| 143 | }; | ||
| 144 | |||
| 145 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, | ||
| 146 | seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr; | ||
| 147 | } | 28 | } |
| 148 | 29 | ||
| 149 | +/* | 30 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
| 150 | + * The Segment Registers of the AST2600 have a 1MB unit. The address | 31 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 151 | + * range of a flash SPI slave is encoded with offsets in the overall | 32 | index XXXXXXX..XXXXXXX 100644 |
| 152 | + * controller window. The previous SoC AST2400 and AST2500 used | 33 | --- a/fpu/softfloat-specialize.c.inc |
| 153 | + * absolute addresses. Only bits [27:20] are relevant and the end | 34 | +++ b/fpu/softfloat-specialize.c.inc |
| 154 | + * address is an upper bound limit. | 35 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 155 | + */ | 36 | /* |
| 156 | +#define AST2600_SEG_ADDR_MASK 0x0ff00000 | 37 | * Temporarily fall back to ifdef ladder |
| 157 | + | 38 | */ |
| 158 | +static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s, | 39 | -#if defined(TARGET_ARM) |
| 159 | + const AspeedSegments *seg) | 40 | - /* |
| 160 | +{ | 41 | - * For ARM, the (inf,zero,qnan) case returns the default NaN, |
| 161 | + uint32_t reg = 0; | 42 | - * but (inf,zero,snan) returns the input NaN. |
| 162 | + | 43 | - */ |
| 163 | + /* Disabled segments have a nil register */ | 44 | - rule = float_infzeronan_dnan_if_qnan; |
| 164 | + if (!seg->size) { | 45 | -#elif defined(TARGET_MIPS) |
| 165 | + return 0; | 46 | +#if defined(TARGET_MIPS) |
| 166 | + } | 47 | if (snan_bit_is_one(status)) { |
| 167 | + | 48 | /* |
| 168 | + reg |= (seg->addr & AST2600_SEG_ADDR_MASK) >> 16; /* start offset */ | 49 | * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) |
| 169 | + reg |= (seg->addr + seg->size - 1) & AST2600_SEG_ADDR_MASK; /* end offset */ | ||
| 170 | + return reg; | ||
| 171 | +} | ||
| 172 | + | ||
| 173 | +static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s, | ||
| 174 | + uint32_t reg, AspeedSegments *seg) | ||
| 175 | +{ | ||
| 176 | + uint32_t start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK; | ||
| 177 | + uint32_t end_offset = reg & AST2600_SEG_ADDR_MASK; | ||
| 178 | + | ||
| 179 | + seg->addr = s->ctrl->flash_window_base + start_offset; | ||
| 180 | + seg->size = end_offset + MiB - start_offset; | ||
| 181 | +} | ||
| 182 | + | ||
| 183 | static bool aspeed_smc_flash_overlap(const AspeedSMCState *s, | ||
| 184 | const AspeedSegments *new, | ||
| 185 | int cs) | ||
| 186 | @@ -XXX,XX +XXX,XX @@ static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl) | ||
| 187 | const AspeedSMCState *s = fl->controller; | ||
| 188 | int cmd = (s->regs[s->r_ctrl0 + fl->id] >> CTRL_CMD_SHIFT) & CTRL_CMD_MASK; | ||
| 189 | |||
| 190 | - /* In read mode, the default SPI command is READ (0x3). In other | ||
| 191 | - * modes, the command should necessarily be defined */ | ||
| 192 | + /* | ||
| 193 | + * In read mode, the default SPI command is READ (0x3). In other | ||
| 194 | + * modes, the command should necessarily be defined | ||
| 195 | + * | ||
| 196 | + * TODO: add support for READ4 (0x13) on AST2600 | ||
| 197 | + */ | ||
| 198 | if (aspeed_smc_flash_mode(fl) == CTRL_READMODE) { | ||
| 199 | cmd = SPI_OP_READ; | ||
| 200 | } | ||
| 201 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_reset(DeviceState *d) | ||
| 202 | s->ctrl->segment_to_reg(s, &s->ctrl->segments[i]); | ||
| 203 | } | ||
| 204 | |||
| 205 | + /* HW strapping flash type for the AST2600 controllers */ | ||
| 206 | + if (s->ctrl->segments == aspeed_segments_ast2600_fmc) { | ||
| 207 | + /* flash type is fixed to SPI for all */ | ||
| 208 | + s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0); | ||
| 209 | + s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1); | ||
| 210 | + s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE2); | ||
| 211 | + } | ||
| 212 | + | ||
| 213 | /* HW strapping flash type for FMC controllers */ | ||
| 214 | if (s->ctrl->segments == aspeed_segments_ast2500_fmc) { | ||
| 215 | /* flash type is fixed to SPI for CE0 and CE1 */ | ||
| 216 | -- | 50 | -- |
| 217 | 2.20.1 | 51 | 2.34.1 |
| 218 | |||
| 219 | diff view generated by jsdifflib |
| 1 | From: Cédric Le Goater <clg@kaod.org> | 1 | Set the FloatInfZeroNaNRule explicitly for s390, so we |
|---|---|---|---|
| 2 | can remove the ifdef from pickNaNMulAdd(). | ||
| 2 | 3 | ||
| 3 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 4 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
| 5 | Message-id: 20190925143248.10000-21-clg@kaod.org | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-7-peter.maydell@linaro.org | ||
| 7 | --- | 7 | --- |
| 8 | include/hw/arm/aspeed.h | 1 + | 8 | target/s390x/cpu.c | 2 ++ |
| 9 | hw/arm/aspeed.c | 23 +++++++++++++++++++++++ | 9 | fpu/softfloat-specialize.c.inc | 2 -- |
| 10 | 2 files changed, 24 insertions(+) | 10 | 2 files changed, 2 insertions(+), 2 deletions(-) |
| 11 | 11 | ||
| 12 | diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h | 12 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c |
| 13 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 14 | --- a/include/hw/arm/aspeed.h | 14 | --- a/target/s390x/cpu.c |
| 15 | +++ b/include/hw/arm/aspeed.h | 15 | +++ b/target/s390x/cpu.c |
| 16 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedBoardConfig { | 16 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) |
| 17 | const char *desc; | 17 | set_float_detect_tininess(float_tininess_before_rounding, |
| 18 | const char *soc_name; | 18 | &env->fpu_status); |
| 19 | uint32_t hw_strap1; | 19 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); |
| 20 | + uint32_t hw_strap2; | 20 | + set_float_infzeronan_rule(float_infzeronan_dnan_always, |
| 21 | const char *fmc_model; | 21 | + &env->fpu_status); |
| 22 | const char *spi_model; | 22 | /* fall through */ |
| 23 | uint32_t num_cs; | 23 | case RESET_TYPE_S390_CPU_NORMAL: |
| 24 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | 24 | env->psw.mask &= ~PSW_MASK_RI; |
| 25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 25 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
| 26 | --- a/hw/arm/aspeed.c | 27 | --- a/fpu/softfloat-specialize.c.inc |
| 27 | +++ b/hw/arm/aspeed.c | 28 | +++ b/fpu/softfloat-specialize.c.inc |
| 28 | @@ -XXX,XX +XXX,XX @@ struct AspeedBoardState { | 29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 29 | /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ | 30 | * a default NaN |
| 30 | #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 | 31 | */ |
| 31 | 32 | rule = float_infzeronan_dnan_never; | |
| 32 | +/* AST2600 evb hardware value */ | 33 | -#elif defined(TARGET_S390X) |
| 33 | +#define AST2600_EVB_HW_STRAP1 0x000000C0 | 34 | - rule = float_infzeronan_dnan_always; |
| 34 | +#define AST2600_EVB_HW_STRAP2 0x00000003 | 35 | #endif |
| 35 | + | 36 | } |
| 36 | /* | ||
| 37 | * The max ram region is for firmwares that scan the address space | ||
| 38 | * with load/store to guess how much RAM the SoC has. | ||
| 39 | @@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine, | ||
| 40 | &error_abort); | ||
| 41 | object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1", | ||
| 42 | &error_abort); | ||
| 43 | + object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap2, "hw-strap2", | ||
| 44 | + &error_abort); | ||
| 45 | object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs", | ||
| 46 | &error_abort); | ||
| 47 | object_property_set_int(OBJECT(&bmc->soc), machine->smp.cpus, "num-cpus", | ||
| 48 | @@ -XXX,XX +XXX,XX @@ static void ast2500_evb_i2c_init(AspeedBoardState *bmc) | ||
| 49 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); | ||
| 50 | } | ||
| 51 | |||
| 52 | +static void ast2600_evb_i2c_init(AspeedBoardState *bmc) | ||
| 53 | +{ | ||
| 54 | + /* Start with some devices on our I2C busses */ | ||
| 55 | + ast2500_evb_i2c_init(bmc); | ||
| 56 | +} | ||
| 57 | + | ||
| 58 | static void romulus_bmc_i2c_init(AspeedBoardState *bmc) | ||
| 59 | { | ||
| 60 | AspeedSoCState *soc = &bmc->soc; | ||
| 61 | @@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = { | ||
| 62 | .num_cs = 2, | ||
| 63 | .i2c_init = witherspoon_bmc_i2c_init, | ||
| 64 | .ram = 512 * MiB, | ||
| 65 | + }, { | ||
| 66 | + .name = MACHINE_TYPE_NAME("ast2600-evb"), | ||
| 67 | + .desc = "Aspeed AST2600 EVB (Cortex A7)", | ||
| 68 | + .soc_name = "ast2600-a0", | ||
| 69 | + .hw_strap1 = AST2600_EVB_HW_STRAP1, | ||
| 70 | + .hw_strap2 = AST2600_EVB_HW_STRAP2, | ||
| 71 | + .fmc_model = "w25q512jv", | ||
| 72 | + .spi_model = "mx66u51235f", | ||
| 73 | + .num_cs = 1, | ||
| 74 | + .i2c_init = ast2600_evb_i2c_init, | ||
| 75 | + .ram = 2 * GiB, | ||
| 76 | }, | ||
| 77 | }; | ||
| 78 | 37 | ||
| 79 | -- | 38 | -- |
| 80 | 2.20.1 | 39 | 2.34.1 |
| 81 | |||
| 82 | diff view generated by jsdifflib |
| 1 | From: Cédric Le Goater <clg@kaod.org> | 1 | Set the FloatInfZeroNaNRule explicitly for the PPC target, |
|---|---|---|---|
| 2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
| 2 | 3 | ||
| 3 | It prepares ground for the AST2600. | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-8-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/ppc/cpu_init.c | 7 +++++++ | ||
| 9 | fpu/softfloat-specialize.c.inc | 7 +------ | ||
| 10 | 2 files changed, 8 insertions(+), 6 deletions(-) | ||
| 4 | 11 | ||
| 5 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 12 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c |
| 6 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
| 7 | Message-id: 20190925143248.10000-18-clg@kaod.org | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | --- | ||
| 10 | include/hw/arm/aspeed_soc.h | 9 +-- | ||
| 11 | hw/arm/aspeed.c | 4 +- | ||
| 12 | hw/arm/aspeed_soc.c | 148 +++++++++++++++++++----------------- | ||
| 13 | 3 files changed, 84 insertions(+), 77 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/include/hw/arm/aspeed_soc.h | 14 | --- a/target/ppc/cpu_init.c |
| 18 | +++ b/include/hw/arm/aspeed_soc.h | 15 | +++ b/target/ppc/cpu_init.c |
| 19 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState { | 16 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) |
| 20 | #define TYPE_ASPEED_SOC "aspeed-soc" | 17 | */ |
| 21 | #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC) | 18 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); |
| 22 | 19 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); | |
| 23 | -typedef struct AspeedSoCInfo { | 20 | + /* |
| 24 | +typedef struct AspeedSoCClass { | 21 | + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer |
| 25 | + DeviceClass parent_class; | 22 | + * to return an input NaN if we have one (ie c) rather than generating |
| 26 | + | 23 | + * a default NaN |
| 27 | const char *name; | 24 | + */ |
| 28 | const char *cpu_type; | 25 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); |
| 29 | uint32_t silicon_rev; | 26 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); |
| 30 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCInfo { | 27 | |
| 31 | const int *irqmap; | 28 | for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { |
| 32 | const hwaddr *memmap; | 29 | ppc_spr_t *spr = &env->spr_cb[i]; |
| 33 | uint32_t num_cpus; | 30 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 34 | -} AspeedSoCInfo; | ||
| 35 | - | ||
| 36 | -typedef struct AspeedSoCClass { | ||
| 37 | - DeviceClass parent_class; | ||
| 38 | - AspeedSoCInfo *info; | ||
| 39 | } AspeedSoCClass; | ||
| 40 | |||
| 41 | #define ASPEED_SOC_CLASS(klass) \ | ||
| 42 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | ||
| 43 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
| 44 | --- a/hw/arm/aspeed.c | 32 | --- a/fpu/softfloat-specialize.c.inc |
| 45 | +++ b/hw/arm/aspeed.c | 33 | +++ b/fpu/softfloat-specialize.c.inc |
| 46 | @@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine, | 34 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 47 | memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size); | 35 | */ |
| 48 | memory_region_add_subregion(&bmc->ram_container, 0, &bmc->ram); | 36 | rule = float_infzeronan_dnan_never; |
| 49 | memory_region_add_subregion(get_system_memory(), | 37 | } |
| 50 | - sc->info->memmap[ASPEED_SDRAM], | 38 | -#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ |
| 51 | + sc->memmap[ASPEED_SDRAM], | 39 | +#elif defined(TARGET_SPARC) || \ |
| 52 | &bmc->ram_container); | 40 | defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ |
| 53 | 41 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) | |
| 54 | max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", | 42 | /* |
| 55 | @@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine, | 43 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) |
| 44 | * case sets InvalidOp and returns the input value 'c' | ||
| 45 | */ | ||
| 46 | - /* | ||
| 47 | - * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
| 48 | - * to return an input NaN if we have one (ie c) rather than generating | ||
| 49 | - * a default NaN | ||
| 50 | - */ | ||
| 51 | rule = float_infzeronan_dnan_never; | ||
| 52 | #endif | ||
| 56 | } | 53 | } |
| 57 | |||
| 58 | aspeed_board_binfo.ram_size = ram_size; | ||
| 59 | - aspeed_board_binfo.loader_start = sc->info->memmap[ASPEED_SDRAM]; | ||
| 60 | + aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM]; | ||
| 61 | aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus; | ||
| 62 | |||
| 63 | if (cfg->i2c_init) { | ||
| 64 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
| 65 | index XXXXXXX..XXXXXXX 100644 | ||
| 66 | --- a/hw/arm/aspeed_soc.c | ||
| 67 | +++ b/hw/arm/aspeed_soc.c | ||
| 68 | @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2400_irqmap[] = { | ||
| 69 | |||
| 70 | #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap | ||
| 71 | |||
| 72 | -static const AspeedSoCInfo aspeed_socs[] = { | ||
| 73 | - { | ||
| 74 | - .name = "ast2400-a1", | ||
| 75 | - .cpu_type = ARM_CPU_TYPE_NAME("arm926"), | ||
| 76 | - .silicon_rev = AST2400_A1_SILICON_REV, | ||
| 77 | - .sram_size = 0x8000, | ||
| 78 | - .spis_num = 1, | ||
| 79 | - .wdts_num = 2, | ||
| 80 | - .irqmap = aspeed_soc_ast2400_irqmap, | ||
| 81 | - .memmap = aspeed_soc_ast2400_memmap, | ||
| 82 | - .num_cpus = 1, | ||
| 83 | - }, { | ||
| 84 | - .name = "ast2500-a1", | ||
| 85 | - .cpu_type = ARM_CPU_TYPE_NAME("arm1176"), | ||
| 86 | - .silicon_rev = AST2500_A1_SILICON_REV, | ||
| 87 | - .sram_size = 0x9000, | ||
| 88 | - .spis_num = 2, | ||
| 89 | - .wdts_num = 3, | ||
| 90 | - .irqmap = aspeed_soc_ast2500_irqmap, | ||
| 91 | - .memmap = aspeed_soc_ast2500_memmap, | ||
| 92 | - .num_cpus = 1, | ||
| 93 | - }, | ||
| 94 | -}; | ||
| 95 | - | ||
| 96 | static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) | ||
| 97 | { | ||
| 98 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
| 99 | |||
| 100 | - return qdev_get_gpio_in(DEVICE(&s->vic), sc->info->irqmap[ctrl]); | ||
| 101 | + return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[ctrl]); | ||
| 102 | } | ||
| 103 | |||
| 104 | static void aspeed_soc_init(Object *obj) | ||
| 105 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | ||
| 106 | char socname[8]; | ||
| 107 | char typename[64]; | ||
| 108 | |||
| 109 | - if (sscanf(sc->info->name, "%7s", socname) != 1) { | ||
| 110 | + if (sscanf(sc->name, "%7s", socname) != 1) { | ||
| 111 | g_assert_not_reached(); | ||
| 112 | } | ||
| 113 | |||
| 114 | - for (i = 0; i < sc->info->num_cpus; i++) { | ||
| 115 | + for (i = 0; i < sc->num_cpus; i++) { | ||
| 116 | object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), | ||
| 117 | - sizeof(s->cpu[i]), sc->info->cpu_type, | ||
| 118 | + sizeof(s->cpu[i]), sc->cpu_type, | ||
| 119 | &error_abort, NULL); | ||
| 120 | } | ||
| 121 | |||
| 122 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | ||
| 123 | sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu), | ||
| 124 | typename); | ||
| 125 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", | ||
| 126 | - sc->info->silicon_rev); | ||
| 127 | + sc->silicon_rev); | ||
| 128 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), | ||
| 129 | "hw-strap1", &error_abort); | ||
| 130 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), | ||
| 131 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | ||
| 132 | object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram", | ||
| 133 | &error_abort); | ||
| 134 | |||
| 135 | - for (i = 0; i < sc->info->spis_num; i++) { | ||
| 136 | + for (i = 0; i < sc->spis_num; i++) { | ||
| 137 | snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); | ||
| 138 | sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]), | ||
| 139 | sizeof(s->spi[i]), typename); | ||
| 140 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | ||
| 141 | object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), | ||
| 142 | "max-ram-size", &error_abort); | ||
| 143 | |||
| 144 | - for (i = 0; i < sc->info->wdts_num; i++) { | ||
| 145 | + for (i = 0; i < sc->wdts_num; i++) { | ||
| 146 | snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); | ||
| 147 | sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]), | ||
| 148 | sizeof(s->wdt[i]), typename); | ||
| 149 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
| 150 | Error *err = NULL, *local_err = NULL; | ||
| 151 | |||
| 152 | /* IO space */ | ||
| 153 | - create_unimplemented_device("aspeed_soc.io", sc->info->memmap[ASPEED_IOMEM], | ||
| 154 | + create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], | ||
| 155 | ASPEED_SOC_IOMEM_SIZE); | ||
| 156 | |||
| 157 | - if (s->num_cpus > sc->info->num_cpus) { | ||
| 158 | + if (s->num_cpus > sc->num_cpus) { | ||
| 159 | warn_report("%s: invalid number of CPUs %d, using default %d", | ||
| 160 | - sc->info->name, s->num_cpus, sc->info->num_cpus); | ||
| 161 | - s->num_cpus = sc->info->num_cpus; | ||
| 162 | + sc->name, s->num_cpus, sc->num_cpus); | ||
| 163 | + s->num_cpus = sc->num_cpus; | ||
| 164 | } | ||
| 165 | |||
| 166 | /* CPU */ | ||
| 167 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
| 168 | |||
| 169 | /* SRAM */ | ||
| 170 | memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", | ||
| 171 | - sc->info->sram_size, &err); | ||
| 172 | + sc->sram_size, &err); | ||
| 173 | if (err) { | ||
| 174 | error_propagate(errp, err); | ||
| 175 | return; | ||
| 176 | } | ||
| 177 | memory_region_add_subregion(get_system_memory(), | ||
| 178 | - sc->info->memmap[ASPEED_SRAM], &s->sram); | ||
| 179 | + sc->memmap[ASPEED_SRAM], &s->sram); | ||
| 180 | |||
| 181 | /* SCU */ | ||
| 182 | object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); | ||
| 183 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
| 184 | error_propagate(errp, err); | ||
| 185 | return; | ||
| 186 | } | ||
| 187 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->info->memmap[ASPEED_SCU]); | ||
| 188 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]); | ||
| 189 | |||
| 190 | /* VIC */ | ||
| 191 | object_property_set_bool(OBJECT(&s->vic), true, "realized", &err); | ||
| 192 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
| 193 | error_propagate(errp, err); | ||
| 194 | return; | ||
| 195 | } | ||
| 196 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->info->memmap[ASPEED_VIC]); | ||
| 197 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_VIC]); | ||
| 198 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0, | ||
| 199 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); | ||
| 200 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1, | ||
| 201 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
| 202 | error_propagate(errp, err); | ||
| 203 | return; | ||
| 204 | } | ||
| 205 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->info->memmap[ASPEED_RTC]); | ||
| 206 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]); | ||
| 207 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, | ||
| 208 | aspeed_soc_get_irq(s, ASPEED_RTC)); | ||
| 209 | |||
| 210 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
| 211 | return; | ||
| 212 | } | ||
| 213 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, | ||
| 214 | - sc->info->memmap[ASPEED_TIMER1]); | ||
| 215 | + sc->memmap[ASPEED_TIMER1]); | ||
| 216 | for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { | ||
| 217 | qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); | ||
| 218 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); | ||
| 219 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
| 220 | /* UART - attach an 8250 to the IO space as our UART5 */ | ||
| 221 | if (serial_hd(0)) { | ||
| 222 | qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5); | ||
| 223 | - serial_mm_init(get_system_memory(), sc->info->memmap[ASPEED_UART5], 2, | ||
| 224 | + serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2, | ||
| 225 | uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); | ||
| 226 | } | ||
| 227 | |||
| 228 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
| 229 | error_propagate(errp, err); | ||
| 230 | return; | ||
| 231 | } | ||
| 232 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->info->memmap[ASPEED_I2C]); | ||
| 233 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]); | ||
| 234 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, | ||
| 235 | aspeed_soc_get_irq(s, ASPEED_I2C)); | ||
| 236 | |||
| 237 | /* FMC, The number of CS is set at the board level */ | ||
| 238 | - object_property_set_int(OBJECT(&s->fmc), sc->info->memmap[ASPEED_SDRAM], | ||
| 239 | + object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], | ||
| 240 | "sdram-base", &err); | ||
| 241 | if (err) { | ||
| 242 | error_propagate(errp, err); | ||
| 243 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
| 244 | error_propagate(errp, err); | ||
| 245 | return; | ||
| 246 | } | ||
| 247 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->info->memmap[ASPEED_FMC]); | ||
| 248 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]); | ||
| 249 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, | ||
| 250 | s->fmc.ctrl->flash_window_base); | ||
| 251 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, | ||
| 252 | aspeed_soc_get_irq(s, ASPEED_FMC)); | ||
| 253 | |||
| 254 | /* SPI */ | ||
| 255 | - for (i = 0; i < sc->info->spis_num; i++) { | ||
| 256 | + for (i = 0; i < sc->spis_num; i++) { | ||
| 257 | object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err); | ||
| 258 | object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", | ||
| 259 | &local_err); | ||
| 260 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
| 261 | return; | ||
| 262 | } | ||
| 263 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, | ||
| 264 | - sc->info->memmap[ASPEED_SPI1 + i]); | ||
| 265 | + sc->memmap[ASPEED_SPI1 + i]); | ||
| 266 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, | ||
| 267 | s->spi[i].ctrl->flash_window_base); | ||
| 268 | } | ||
| 269 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
| 270 | error_propagate(errp, err); | ||
| 271 | return; | ||
| 272 | } | ||
| 273 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->info->memmap[ASPEED_SDMC]); | ||
| 274 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]); | ||
| 275 | |||
| 276 | /* Watch dog */ | ||
| 277 | - for (i = 0; i < sc->info->wdts_num; i++) { | ||
| 278 | + for (i = 0; i < sc->wdts_num; i++) { | ||
| 279 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); | ||
| 280 | |||
| 281 | object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); | ||
| 282 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
| 283 | return; | ||
| 284 | } | ||
| 285 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | ||
| 286 | - sc->info->memmap[ASPEED_WDT] + i * awc->offset); | ||
| 287 | + sc->memmap[ASPEED_WDT] + i * awc->offset); | ||
| 288 | } | ||
| 289 | |||
| 290 | /* Net */ | ||
| 291 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
| 292 | return; | ||
| 293 | } | ||
| 294 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | ||
| 295 | - sc->info->memmap[ASPEED_ETH1 + i]); | ||
| 296 | + sc->memmap[ASPEED_ETH1 + i]); | ||
| 297 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | ||
| 298 | aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); | ||
| 299 | } | ||
| 300 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
| 301 | return; | ||
| 302 | } | ||
| 303 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, | ||
| 304 | - sc->info->memmap[ASPEED_XDMA]); | ||
| 305 | + sc->memmap[ASPEED_XDMA]); | ||
| 306 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, | ||
| 307 | aspeed_soc_get_irq(s, ASPEED_XDMA)); | ||
| 308 | |||
| 309 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
| 310 | error_propagate(errp, err); | ||
| 311 | return; | ||
| 312 | } | ||
| 313 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->info->memmap[ASPEED_GPIO]); | ||
| 314 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]); | ||
| 315 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, | ||
| 316 | aspeed_soc_get_irq(s, ASPEED_GPIO)); | ||
| 317 | |||
| 318 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
| 319 | return; | ||
| 320 | } | ||
| 321 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, | ||
| 322 | - sc->info->memmap[ASPEED_SDHCI]); | ||
| 323 | + sc->memmap[ASPEED_SDHCI]); | ||
| 324 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, | ||
| 325 | aspeed_soc_get_irq(s, ASPEED_SDHCI)); | ||
| 326 | } | ||
| 327 | @@ -XXX,XX +XXX,XX @@ static Property aspeed_soc_properties[] = { | ||
| 328 | static void aspeed_soc_class_init(ObjectClass *oc, void *data) | ||
| 329 | { | ||
| 330 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 331 | - AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | ||
| 332 | |||
| 333 | - sc->info = (AspeedSoCInfo *) data; | ||
| 334 | dc->realize = aspeed_soc_realize; | ||
| 335 | /* Reason: Uses serial_hds and nd_table in realize() directly */ | ||
| 336 | dc->user_creatable = false; | ||
| 337 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data) | ||
| 338 | static const TypeInfo aspeed_soc_type_info = { | ||
| 339 | .name = TYPE_ASPEED_SOC, | ||
| 340 | .parent = TYPE_DEVICE, | ||
| 341 | - .instance_init = aspeed_soc_init, | ||
| 342 | .instance_size = sizeof(AspeedSoCState), | ||
| 343 | .class_size = sizeof(AspeedSoCClass), | ||
| 344 | + .class_init = aspeed_soc_class_init, | ||
| 345 | .abstract = true, | ||
| 346 | }; | ||
| 347 | |||
| 348 | -static void aspeed_soc_register_types(void) | ||
| 349 | +static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) | ||
| 350 | { | ||
| 351 | - int i; | ||
| 352 | + AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | ||
| 353 | |||
| 354 | - type_register_static(&aspeed_soc_type_info); | ||
| 355 | - for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) { | ||
| 356 | - TypeInfo ti = { | ||
| 357 | - .name = aspeed_socs[i].name, | ||
| 358 | - .parent = TYPE_ASPEED_SOC, | ||
| 359 | - .class_init = aspeed_soc_class_init, | ||
| 360 | - .class_data = (void *) &aspeed_socs[i], | ||
| 361 | - }; | ||
| 362 | - type_register(&ti); | ||
| 363 | - } | ||
| 364 | + sc->name = "ast2400-a1"; | ||
| 365 | + sc->cpu_type = ARM_CPU_TYPE_NAME("arm926"); | ||
| 366 | + sc->silicon_rev = AST2400_A1_SILICON_REV; | ||
| 367 | + sc->sram_size = 0x8000; | ||
| 368 | + sc->spis_num = 1; | ||
| 369 | + sc->wdts_num = 2; | ||
| 370 | + sc->irqmap = aspeed_soc_ast2400_irqmap; | ||
| 371 | + sc->memmap = aspeed_soc_ast2400_memmap; | ||
| 372 | + sc->num_cpus = 1; | ||
| 373 | } | ||
| 374 | |||
| 375 | +static const TypeInfo aspeed_soc_ast2400_type_info = { | ||
| 376 | + .name = "ast2400-a1", | ||
| 377 | + .parent = TYPE_ASPEED_SOC, | ||
| 378 | + .instance_init = aspeed_soc_init, | ||
| 379 | + .instance_size = sizeof(AspeedSoCState), | ||
| 380 | + .class_init = aspeed_soc_ast2400_class_init, | ||
| 381 | +}; | ||
| 382 | + | ||
| 383 | +static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) | ||
| 384 | +{ | ||
| 385 | + AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | ||
| 386 | + | ||
| 387 | + sc->name = "ast2500-a1"; | ||
| 388 | + sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); | ||
| 389 | + sc->silicon_rev = AST2500_A1_SILICON_REV; | ||
| 390 | + sc->sram_size = 0x9000; | ||
| 391 | + sc->spis_num = 2; | ||
| 392 | + sc->wdts_num = 3; | ||
| 393 | + sc->irqmap = aspeed_soc_ast2500_irqmap; | ||
| 394 | + sc->memmap = aspeed_soc_ast2500_memmap; | ||
| 395 | + sc->num_cpus = 1; | ||
| 396 | +} | ||
| 397 | + | ||
| 398 | +static const TypeInfo aspeed_soc_ast2500_type_info = { | ||
| 399 | + .name = "ast2500-a1", | ||
| 400 | + .parent = TYPE_ASPEED_SOC, | ||
| 401 | + .instance_init = aspeed_soc_init, | ||
| 402 | + .instance_size = sizeof(AspeedSoCState), | ||
| 403 | + .class_init = aspeed_soc_ast2500_class_init, | ||
| 404 | +}; | ||
| 405 | +static void aspeed_soc_register_types(void) | ||
| 406 | +{ | ||
| 407 | + type_register_static(&aspeed_soc_type_info); | ||
| 408 | + type_register_static(&aspeed_soc_ast2400_type_info); | ||
| 409 | + type_register_static(&aspeed_soc_ast2500_type_info); | ||
| 410 | +}; | ||
| 411 | + | ||
| 412 | type_init(aspeed_soc_register_types) | ||
| 413 | -- | 54 | -- |
| 414 | 2.20.1 | 55 | 2.34.1 |
| 415 | |||
| 416 | diff view generated by jsdifflib |
| 1 | Version 2.0 of the semihosting specification added support for | 1 | Set the FloatInfZeroNaNRule explicitly for the MIPS target, |
|---|---|---|---|
| 2 | allowing a guest to detect whether the implementation supported | 2 | so we can remove the ifdef from pickNaNMulAdd(). |
| 3 | particular features. This works by the guest opening a magic | ||
| 4 | file ":semihosting-features", which contains a fixed set of | ||
| 5 | data with some magic numbers followed by a sequence of bytes | ||
| 6 | with feature flags. The file is expected to behave sensibly | ||
| 7 | for the various semihosting calls which operate on files | ||
| 8 | (SYS_FLEN, SYS_SEEK, etc). | ||
| 9 | |||
| 10 | Implement this as another kind of guest FD using our function | ||
| 11 | table dispatch mechanism. Initially we report no extended | ||
| 12 | features, so we have just one feature flag byte which is zero. | ||
| 13 | 3 | ||
| 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 15 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 16 | Message-id: 20190916141544.17540-14-peter.maydell@linaro.org | 6 | Message-id: 20241202131347.498124-9-peter.maydell@linaro.org |
| 17 | --- | 7 | --- |
| 18 | target/arm/arm-semi.c | 109 +++++++++++++++++++++++++++++++++++++++++- | 8 | target/mips/fpu_helper.h | 9 +++++++++ |
| 19 | 1 file changed, 108 insertions(+), 1 deletion(-) | 9 | target/mips/msa.c | 4 ++++ |
| 10 | fpu/softfloat-specialize.c.inc | 16 +--------------- | ||
| 11 | 3 files changed, 14 insertions(+), 15 deletions(-) | ||
| 20 | 12 | ||
| 21 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 13 | diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h |
| 22 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
| 23 | --- a/target/arm/arm-semi.c | 15 | --- a/target/mips/fpu_helper.h |
| 24 | +++ b/target/arm/arm-semi.c | 16 | +++ b/target/mips/fpu_helper.h |
| 25 | @@ -XXX,XX +XXX,XX @@ typedef enum GuestFDType { | 17 | @@ -XXX,XX +XXX,XX @@ static inline void restore_flush_mode(CPUMIPSState *env) |
| 26 | GuestFDUnused = 0, | 18 | static inline void restore_snan_bit_mode(CPUMIPSState *env) |
| 27 | GuestFDHost = 1, | 19 | { |
| 28 | GuestFDGDB = 2, | 20 | bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); |
| 29 | + GuestFDFeatureFile = 3, | 21 | + FloatInfZeroNaNRule izn_rule; |
| 30 | } GuestFDType; | 22 | |
| 31 | 23 | /* | |
| 32 | /* | 24 | * With nan2008, SNaNs are silenced in the usual way. |
| 33 | @@ -XXX,XX +XXX,XX @@ typedef enum GuestFDType { | 25 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) |
| 34 | */ | 26 | */ |
| 35 | typedef struct GuestFD { | 27 | set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status); |
| 36 | GuestFDType type; | 28 | set_default_nan_mode(!nan2008, &env->active_fpu.fp_status); |
| 37 | - int hostfd; | 29 | + /* |
| 38 | + union { | 30 | + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) |
| 39 | + int hostfd; | 31 | + * case sets InvalidOp and returns the default NaN. |
| 40 | + target_ulong featurefile_offset; | 32 | + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) |
| 41 | + }; | 33 | + * case sets InvalidOp and returns the input value 'c'. |
| 42 | } GuestFD; | 34 | + */ |
| 43 | 35 | + izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; | |
| 44 | static GArray *guestfd_array; | 36 | + set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); |
| 45 | @@ -XXX,XX +XXX,XX @@ static uint32_t gdb_flenfn(ARMCPU *cpu, GuestFD *gf) | ||
| 46 | gf->hostfd, arm_flen_buf(cpu)); | ||
| 47 | } | 37 | } |
| 48 | 38 | ||
| 49 | +#define SHFB_MAGIC_0 0x53 | 39 | static inline void restore_fp_status(CPUMIPSState *env) |
| 50 | +#define SHFB_MAGIC_1 0x48 | 40 | diff --git a/target/mips/msa.c b/target/mips/msa.c |
| 51 | +#define SHFB_MAGIC_2 0x46 | 41 | index XXXXXXX..XXXXXXX 100644 |
| 52 | +#define SHFB_MAGIC_3 0x42 | 42 | --- a/target/mips/msa.c |
| 43 | +++ b/target/mips/msa.c | ||
| 44 | @@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env) | ||
| 45 | |||
| 46 | /* set proper signanling bit meaning ("1" means "quiet") */ | ||
| 47 | set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); | ||
| 53 | + | 48 | + |
| 54 | +static const uint8_t featurefile_data[] = { | 49 | + /* Inf * 0 + NaN returns the input NaN */ |
| 55 | + SHFB_MAGIC_0, | 50 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, |
| 56 | + SHFB_MAGIC_1, | 51 | + &env->active_tc.msa_fp_status); |
| 57 | + SHFB_MAGIC_2, | 52 | } |
| 58 | + SHFB_MAGIC_3, | 53 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 59 | + 0, /* Feature byte 0 */ | 54 | index XXXXXXX..XXXXXXX 100644 |
| 60 | +}; | 55 | --- a/fpu/softfloat-specialize.c.inc |
| 61 | + | 56 | +++ b/fpu/softfloat-specialize.c.inc |
| 62 | +static void init_featurefile_guestfd(int guestfd) | 57 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 63 | +{ | 58 | /* |
| 64 | + GuestFD *gf = do_get_guestfd(guestfd); | 59 | * Temporarily fall back to ifdef ladder |
| 65 | + | 60 | */ |
| 66 | + assert(gf); | 61 | -#if defined(TARGET_MIPS) |
| 67 | + gf->type = GuestFDFeatureFile; | 62 | - if (snan_bit_is_one(status)) { |
| 68 | + gf->featurefile_offset = 0; | 63 | - /* |
| 69 | +} | 64 | - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) |
| 70 | + | 65 | - * case sets InvalidOp and returns the default NaN |
| 71 | +static uint32_t featurefile_closefn(ARMCPU *cpu, GuestFD *gf) | 66 | - */ |
| 72 | +{ | 67 | - rule = float_infzeronan_dnan_always; |
| 73 | + /* Nothing to do */ | 68 | - } else { |
| 74 | + return 0; | 69 | - /* |
| 75 | +} | 70 | - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) |
| 76 | + | 71 | - * case sets InvalidOp and returns the input value 'c' |
| 77 | +static uint32_t featurefile_writefn(ARMCPU *cpu, GuestFD *gf, | 72 | - */ |
| 78 | + target_ulong buf, uint32_t len) | 73 | - rule = float_infzeronan_dnan_never; |
| 79 | +{ | 74 | - } |
| 80 | + /* This fd can never be open for writing */ | 75 | -#elif defined(TARGET_SPARC) || \ |
| 81 | + CPUARMState *env = &cpu->env; | 76 | +#if defined(TARGET_SPARC) || \ |
| 82 | + | 77 | defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ |
| 83 | + errno = EBADF; | 78 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) |
| 84 | + return set_swi_errno(env, -1); | 79 | /* |
| 85 | +} | ||
| 86 | + | ||
| 87 | +static uint32_t featurefile_readfn(ARMCPU *cpu, GuestFD *gf, | ||
| 88 | + target_ulong buf, uint32_t len) | ||
| 89 | +{ | ||
| 90 | + uint32_t i; | ||
| 91 | +#ifndef CONFIG_USER_ONLY | ||
| 92 | + CPUARMState *env = &cpu->env; | ||
| 93 | +#endif | ||
| 94 | + char *s; | ||
| 95 | + | ||
| 96 | + s = lock_user(VERIFY_WRITE, buf, len, 0); | ||
| 97 | + if (!s) { | ||
| 98 | + return len; | ||
| 99 | + } | ||
| 100 | + | ||
| 101 | + for (i = 0; i < len; i++) { | ||
| 102 | + if (gf->featurefile_offset >= sizeof(featurefile_data)) { | ||
| 103 | + break; | ||
| 104 | + } | ||
| 105 | + s[i] = featurefile_data[gf->featurefile_offset]; | ||
| 106 | + gf->featurefile_offset++; | ||
| 107 | + } | ||
| 108 | + | ||
| 109 | + unlock_user(s, buf, len); | ||
| 110 | + | ||
| 111 | + /* Return number of bytes not read */ | ||
| 112 | + return len - i; | ||
| 113 | +} | ||
| 114 | + | ||
| 115 | +static uint32_t featurefile_isattyfn(ARMCPU *cpu, GuestFD *gf) | ||
| 116 | +{ | ||
| 117 | + return 0; | ||
| 118 | +} | ||
| 119 | + | ||
| 120 | +static uint32_t featurefile_seekfn(ARMCPU *cpu, GuestFD *gf, | ||
| 121 | + target_ulong offset) | ||
| 122 | +{ | ||
| 123 | + gf->featurefile_offset = offset; | ||
| 124 | + return 0; | ||
| 125 | +} | ||
| 126 | + | ||
| 127 | +static uint32_t featurefile_flenfn(ARMCPU *cpu, GuestFD *gf) | ||
| 128 | +{ | ||
| 129 | + return sizeof(featurefile_data); | ||
| 130 | +} | ||
| 131 | + | ||
| 132 | typedef struct GuestFDFunctions { | ||
| 133 | sys_closefn *closefn; | ||
| 134 | sys_writefn *writefn; | ||
| 135 | @@ -XXX,XX +XXX,XX @@ static const GuestFDFunctions guestfd_fns[] = { | ||
| 136 | .seekfn = gdb_seekfn, | ||
| 137 | .flenfn = gdb_flenfn, | ||
| 138 | }, | ||
| 139 | + [GuestFDFeatureFile] = { | ||
| 140 | + .closefn = featurefile_closefn, | ||
| 141 | + .writefn = featurefile_writefn, | ||
| 142 | + .readfn = featurefile_readfn, | ||
| 143 | + .isattyfn = featurefile_isattyfn, | ||
| 144 | + .seekfn = featurefile_seekfn, | ||
| 145 | + .flenfn = featurefile_flenfn, | ||
| 146 | + }, | ||
| 147 | }; | ||
| 148 | |||
| 149 | /* Read the input value from the argument block; fail the semihosting | ||
| 150 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 151 | unlock_user(s, arg0, 0); | ||
| 152 | return guestfd; | ||
| 153 | } | ||
| 154 | + if (strcmp(s, ":semihosting-features") == 0) { | ||
| 155 | + unlock_user(s, arg0, 0); | ||
| 156 | + /* We must fail opens for modes other than 0 ('r') or 1 ('rb') */ | ||
| 157 | + if (arg1 != 0 && arg1 != 1) { | ||
| 158 | + dealloc_guestfd(guestfd); | ||
| 159 | + errno = EACCES; | ||
| 160 | + return set_swi_errno(env, -1); | ||
| 161 | + } | ||
| 162 | + init_featurefile_guestfd(guestfd); | ||
| 163 | + return guestfd; | ||
| 164 | + } | ||
| 165 | + | ||
| 166 | if (use_gdb_syscalls()) { | ||
| 167 | arm_semi_open_guestfd = guestfd; | ||
| 168 | ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0, | ||
| 169 | -- | 80 | -- |
| 170 | 2.20.1 | 81 | 2.34.1 |
| 171 | |||
| 172 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the FloatInfZeroNaNRule explicitly for the SPARC target, | ||
| 2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-10-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/sparc/cpu.c | 2 ++ | ||
| 9 | fpu/softfloat-specialize.c.inc | 3 +-- | ||
| 10 | 2 files changed, 3 insertions(+), 2 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/sparc/cpu.c | ||
| 15 | +++ b/target/sparc/cpu.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) | ||
| 17 | * the CPU state struct so it won't get zeroed on reset. | ||
| 18 | */ | ||
| 19 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); | ||
| 20 | + /* For inf * 0 + NaN, return the input NaN */ | ||
| 21 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
| 22 | |||
| 23 | cpu_exec_realizefn(cs, &local_err); | ||
| 24 | if (local_err != NULL) { | ||
| 25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | ||
| 27 | --- a/fpu/softfloat-specialize.c.inc | ||
| 28 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 30 | /* | ||
| 31 | * Temporarily fall back to ifdef ladder | ||
| 32 | */ | ||
| 33 | -#if defined(TARGET_SPARC) || \ | ||
| 34 | - defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
| 35 | +#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
| 36 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
| 37 | /* | ||
| 38 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 39 | -- | ||
| 40 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the FloatInfZeroNaNRule explicitly for the xtensa target, | ||
| 2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-11-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/xtensa/cpu.c | 2 ++ | ||
| 9 | fpu/softfloat-specialize.c.inc | 2 +- | ||
| 10 | 2 files changed, 3 insertions(+), 1 deletion(-) | ||
| 11 | |||
| 12 | diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/xtensa/cpu.c | ||
| 15 | +++ b/target/xtensa/cpu.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) | ||
| 17 | reset_mmu(env); | ||
| 18 | cs->halted = env->runstall; | ||
| 19 | #endif | ||
| 20 | + /* For inf * 0 + NaN, return the input NaN */ | ||
| 21 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
| 22 | set_no_signaling_nans(!dfpu, &env->fp_status); | ||
| 23 | xtensa_use_first_nan(env, !dfpu); | ||
| 24 | } | ||
| 25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | ||
| 27 | --- a/fpu/softfloat-specialize.c.inc | ||
| 28 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 30 | /* | ||
| 31 | * Temporarily fall back to ifdef ladder | ||
| 32 | */ | ||
| 33 | -#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
| 34 | +#if defined(TARGET_HPPA) || \ | ||
| 35 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
| 36 | /* | ||
| 37 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 38 | -- | ||
| 39 | 2.34.1 | diff view generated by jsdifflib |
| 1 | Factor out the implementation of SYS_FLEN via the new | 1 | Set the FloatInfZeroNaNRule explicitly for the x86 target. |
|---|---|---|---|
| 2 | function tables. | ||
| 3 | 2 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 6 | Message-id: 20190916141544.17540-13-peter.maydell@linaro.org | 5 | Message-id: 20241202131347.498124-12-peter.maydell@linaro.org |
| 7 | --- | 6 | --- |
| 8 | target/arm/arm-semi.c | 32 ++++++++++++++++++++++---------- | 7 | target/i386/tcg/fpu_helper.c | 7 +++++++ |
| 9 | 1 file changed, 22 insertions(+), 10 deletions(-) | 8 | fpu/softfloat-specialize.c.inc | 2 +- |
| 9 | 2 files changed, 8 insertions(+), 1 deletion(-) | ||
| 10 | 10 | ||
| 11 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 11 | diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c |
| 12 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
| 13 | --- a/target/arm/arm-semi.c | 13 | --- a/target/i386/tcg/fpu_helper.c |
| 14 | +++ b/target/arm/arm-semi.c | 14 | +++ b/target/i386/tcg/fpu_helper.c |
| 15 | @@ -XXX,XX +XXX,XX @@ typedef uint32_t sys_readfn(ARMCPU *cpu, GuestFD *gf, | 15 | @@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env) |
| 16 | typedef uint32_t sys_isattyfn(ARMCPU *cpu, GuestFD *gf); | 16 | */ |
| 17 | typedef uint32_t sys_seekfn(ARMCPU *cpu, GuestFD *gf, | 17 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status); |
| 18 | target_ulong offset); | 18 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status); |
| 19 | +typedef uint32_t sys_flenfn(ARMCPU *cpu, GuestFD *gf); | 19 | + /* |
| 20 | 20 | + * Only SSE has multiply-add instructions. In the SDM Section 14.5.2 | |
| 21 | static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) | 21 | + * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is |
| 22 | { | 22 | + * specified -- for 0 * inf + NaN the input NaN is selected, and if |
| 23 | @@ -XXX,XX +XXX,XX @@ static uint32_t host_seekfn(ARMCPU *cpu, GuestFD *gf, target_ulong offset) | 23 | + * there are multiple input NaNs they are selected in the order a, b, c. |
| 24 | return 0; | 24 | + */ |
| 25 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); | ||
| 25 | } | 26 | } |
| 26 | 27 | ||
| 27 | +static uint32_t host_flenfn(ARMCPU *cpu, GuestFD *gf) | 28 | static inline uint8_t save_exception_flags(CPUX86State *env) |
| 28 | +{ | 29 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 29 | + CPUARMState *env = &cpu->env; | 30 | index XXXXXXX..XXXXXXX 100644 |
| 30 | + struct stat buf; | 31 | --- a/fpu/softfloat-specialize.c.inc |
| 31 | + uint32_t ret = set_swi_errno(env, fstat(gf->hostfd, &buf)); | 32 | +++ b/fpu/softfloat-specialize.c.inc |
| 32 | + if (ret == (uint32_t)-1) { | 33 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 33 | + return -1; | 34 | * Temporarily fall back to ifdef ladder |
| 34 | + } | 35 | */ |
| 35 | + return buf.st_size; | 36 | #if defined(TARGET_HPPA) || \ |
| 36 | +} | 37 | - defined(TARGET_I386) || defined(TARGET_LOONGARCH) |
| 37 | + | 38 | + defined(TARGET_LOONGARCH) |
| 38 | static uint32_t gdb_closefn(ARMCPU *cpu, GuestFD *gf) | 39 | /* |
| 39 | { | 40 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) |
| 40 | return arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); | 41 | * case sets InvalidOp and returns the input value 'c' |
| 41 | @@ -XXX,XX +XXX,XX @@ static uint32_t gdb_seekfn(ARMCPU *cpu, GuestFD *gf, target_ulong offset) | ||
| 42 | gf->hostfd, offset); | ||
| 43 | } | ||
| 44 | |||
| 45 | +static uint32_t gdb_flenfn(ARMCPU *cpu, GuestFD *gf) | ||
| 46 | +{ | ||
| 47 | + return arm_gdb_syscall(cpu, arm_semi_flen_cb, "fstat,%x,%x", | ||
| 48 | + gf->hostfd, arm_flen_buf(cpu)); | ||
| 49 | +} | ||
| 50 | + | ||
| 51 | typedef struct GuestFDFunctions { | ||
| 52 | sys_closefn *closefn; | ||
| 53 | sys_writefn *writefn; | ||
| 54 | sys_readfn *readfn; | ||
| 55 | sys_isattyfn *isattyfn; | ||
| 56 | sys_seekfn *seekfn; | ||
| 57 | + sys_flenfn *flenfn; | ||
| 58 | } GuestFDFunctions; | ||
| 59 | |||
| 60 | static const GuestFDFunctions guestfd_fns[] = { | ||
| 61 | @@ -XXX,XX +XXX,XX @@ static const GuestFDFunctions guestfd_fns[] = { | ||
| 62 | .readfn = host_readfn, | ||
| 63 | .isattyfn = host_isattyfn, | ||
| 64 | .seekfn = host_seekfn, | ||
| 65 | + .flenfn = host_flenfn, | ||
| 66 | }, | ||
| 67 | [GuestFDGDB] = { | ||
| 68 | .closefn = gdb_closefn, | ||
| 69 | @@ -XXX,XX +XXX,XX @@ static const GuestFDFunctions guestfd_fns[] = { | ||
| 70 | .readfn = gdb_readfn, | ||
| 71 | .isattyfn = gdb_isattyfn, | ||
| 72 | .seekfn = gdb_seekfn, | ||
| 73 | + .flenfn = gdb_flenfn, | ||
| 74 | }, | ||
| 75 | }; | ||
| 76 | |||
| 77 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 78 | return set_swi_errno(env, -1); | ||
| 79 | } | ||
| 80 | |||
| 81 | - if (use_gdb_syscalls()) { | ||
| 82 | - return arm_gdb_syscall(cpu, arm_semi_flen_cb, "fstat,%x,%x", | ||
| 83 | - gf->hostfd, arm_flen_buf(cpu)); | ||
| 84 | - } else { | ||
| 85 | - struct stat buf; | ||
| 86 | - ret = set_swi_errno(env, fstat(gf->hostfd, &buf)); | ||
| 87 | - if (ret == (uint32_t)-1) | ||
| 88 | - return -1; | ||
| 89 | - return buf.st_size; | ||
| 90 | - } | ||
| 91 | + return guestfd_fns[gf->type].flenfn(cpu, gf); | ||
| 92 | case TARGET_SYS_TMPNAM: | ||
| 93 | qemu_log_mask(LOG_UNIMP, "%s: SYS_TMPNAM not implemented", __func__); | ||
| 94 | return -1; | ||
| 95 | -- | 42 | -- |
| 96 | 2.20.1 | 43 | 2.34.1 |
| 97 | |||
| 98 | diff view generated by jsdifflib |
| 1 | Factor out the implementation of SYS_SEEK via the new function | 1 | Set the FloatInfZeroNaNRule explicitly for the loongarch target. |
|---|---|---|---|
| 2 | tables. | ||
| 3 | 2 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 6 | Message-id: 20190916141544.17540-12-peter.maydell@linaro.org | 5 | Message-id: 20241202131347.498124-13-peter.maydell@linaro.org |
| 7 | --- | 6 | --- |
| 8 | target/arm/arm-semi.c | 31 ++++++++++++++++++++++--------- | 7 | target/loongarch/tcg/fpu_helper.c | 5 +++++ |
| 9 | 1 file changed, 22 insertions(+), 9 deletions(-) | 8 | fpu/softfloat-specialize.c.inc | 7 +------ |
| 9 | 2 files changed, 6 insertions(+), 6 deletions(-) | ||
| 10 | 10 | ||
| 11 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 11 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c |
| 12 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
| 13 | --- a/target/arm/arm-semi.c | 13 | --- a/target/loongarch/tcg/fpu_helper.c |
| 14 | +++ b/target/arm/arm-semi.c | 14 | +++ b/target/loongarch/tcg/fpu_helper.c |
| 15 | @@ -XXX,XX +XXX,XX @@ typedef uint32_t sys_writefn(ARMCPU *cpu, GuestFD *gf, | 15 | @@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env) |
| 16 | typedef uint32_t sys_readfn(ARMCPU *cpu, GuestFD *gf, | 16 | &env->fp_status); |
| 17 | target_ulong buf, uint32_t len); | 17 | set_flush_to_zero(0, &env->fp_status); |
| 18 | typedef uint32_t sys_isattyfn(ARMCPU *cpu, GuestFD *gf); | 18 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); |
| 19 | +typedef uint32_t sys_seekfn(ARMCPU *cpu, GuestFD *gf, | 19 | + /* |
| 20 | + target_ulong offset); | 20 | + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) |
| 21 | 21 | + * case sets InvalidOp and returns the input value 'c' | |
| 22 | static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) | 22 | + */ |
| 23 | { | 23 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); |
| 24 | @@ -XXX,XX +XXX,XX @@ static uint32_t host_isattyfn(ARMCPU *cpu, GuestFD *gf) | ||
| 25 | return isatty(gf->hostfd); | ||
| 26 | } | 24 | } |
| 27 | 25 | ||
| 28 | +static uint32_t host_seekfn(ARMCPU *cpu, GuestFD *gf, target_ulong offset) | 26 | int ieee_ex_to_loongarch(int xcpt) |
| 29 | +{ | 27 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 30 | + CPUARMState *env = &cpu->env; | 28 | index XXXXXXX..XXXXXXX 100644 |
| 31 | + uint32_t ret = set_swi_errno(env, lseek(gf->hostfd, offset, SEEK_SET)); | 29 | --- a/fpu/softfloat-specialize.c.inc |
| 32 | + if (ret == (uint32_t)-1) { | 30 | +++ b/fpu/softfloat-specialize.c.inc |
| 33 | + return -1; | 31 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 34 | + } | 32 | /* |
| 35 | + return 0; | 33 | * Temporarily fall back to ifdef ladder |
| 36 | +} | 34 | */ |
| 37 | + | 35 | -#if defined(TARGET_HPPA) || \ |
| 38 | static uint32_t gdb_closefn(ARMCPU *cpu, GuestFD *gf) | 36 | - defined(TARGET_LOONGARCH) |
| 39 | { | 37 | - /* |
| 40 | return arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); | 38 | - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) |
| 41 | @@ -XXX,XX +XXX,XX @@ static uint32_t gdb_isattyfn(ARMCPU *cpu, GuestFD *gf) | 39 | - * case sets InvalidOp and returns the input value 'c' |
| 42 | return arm_gdb_syscall(cpu, arm_semi_cb, "isatty,%x", gf->hostfd); | 40 | - */ |
| 43 | } | 41 | +#if defined(TARGET_HPPA) |
| 44 | 42 | rule = float_infzeronan_dnan_never; | |
| 45 | +static uint32_t gdb_seekfn(ARMCPU *cpu, GuestFD *gf, target_ulong offset) | 43 | #endif |
| 46 | +{ | 44 | } |
| 47 | + return arm_gdb_syscall(cpu, arm_semi_cb, "lseek,%x,%x,0", | ||
| 48 | + gf->hostfd, offset); | ||
| 49 | +} | ||
| 50 | + | ||
| 51 | typedef struct GuestFDFunctions { | ||
| 52 | sys_closefn *closefn; | ||
| 53 | sys_writefn *writefn; | ||
| 54 | sys_readfn *readfn; | ||
| 55 | sys_isattyfn *isattyfn; | ||
| 56 | + sys_seekfn *seekfn; | ||
| 57 | } GuestFDFunctions; | ||
| 58 | |||
| 59 | static const GuestFDFunctions guestfd_fns[] = { | ||
| 60 | @@ -XXX,XX +XXX,XX @@ static const GuestFDFunctions guestfd_fns[] = { | ||
| 61 | .writefn = host_writefn, | ||
| 62 | .readfn = host_readfn, | ||
| 63 | .isattyfn = host_isattyfn, | ||
| 64 | + .seekfn = host_seekfn, | ||
| 65 | }, | ||
| 66 | [GuestFDGDB] = { | ||
| 67 | .closefn = gdb_closefn, | ||
| 68 | .writefn = gdb_writefn, | ||
| 69 | .readfn = gdb_readfn, | ||
| 70 | .isattyfn = gdb_isattyfn, | ||
| 71 | + .seekfn = gdb_seekfn, | ||
| 72 | }, | ||
| 73 | }; | ||
| 74 | |||
| 75 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 76 | return set_swi_errno(env, -1); | ||
| 77 | } | ||
| 78 | |||
| 79 | - if (use_gdb_syscalls()) { | ||
| 80 | - return arm_gdb_syscall(cpu, arm_semi_cb, "lseek,%x,%x,0", | ||
| 81 | - gf->hostfd, arg1); | ||
| 82 | - } else { | ||
| 83 | - ret = set_swi_errno(env, lseek(gf->hostfd, arg1, SEEK_SET)); | ||
| 84 | - if (ret == (uint32_t)-1) | ||
| 85 | - return -1; | ||
| 86 | - return 0; | ||
| 87 | - } | ||
| 88 | + return guestfd_fns[gf->type].seekfn(cpu, gf, arg1); | ||
| 89 | case TARGET_SYS_FLEN: | ||
| 90 | GET_ARG(0); | ||
| 91 | |||
| 92 | -- | 45 | -- |
| 93 | 2.20.1 | 46 | 2.34.1 |
| 94 | |||
| 95 | diff view generated by jsdifflib |
| 1 | The semihosting code needs accuss to the linux-user only | 1 | Set the FloatInfZeroNaNRule explicitly for the HPPA target, |
|---|---|---|---|
| 2 | TaskState pointer so it can set the semihosting errno per-thread | 2 | so we can remove the ifdef from pickNaNMulAdd(). |
| 3 | for linux-user mode. At the moment we do this by having some | ||
| 4 | ifdefs so that we define a 'ts' local in do_arm_semihosting() | ||
| 5 | which is either a real TaskState * or just a CPUARMState *, | ||
| 6 | depending on which mode we're compiling for. | ||
| 7 | 3 | ||
| 8 | This is awkward if we want to refactor do_arm_semihosting() | 4 | As this is the last target to be converted to explicitly setting |
| 9 | into other functions which might need to be passed the TaskState. | 5 | the rule, we can remove the fallback code in pickNaNMulAdd() |
| 10 | Restrict usage of the TaskState local by: | 6 | entirely. |
| 11 | * making set_swi_errno() always take the CPUARMState pointer | ||
| 12 | and (for the linux-user version) get TaskState from that | ||
| 13 | * creating a new get_swi_errno() which reads the errno | ||
| 14 | * having the two semihosting calls which need the TaskState | ||
| 15 | for other purposes (SYS_GET_CMDLINE and SYS_HEAPINFO) | ||
| 16 | define a variable with scope restricted to just that code | ||
| 17 | 7 | ||
| 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 20 | Message-id: 20190916141544.17540-6-peter.maydell@linaro.org | 10 | Message-id: 20241202131347.498124-14-peter.maydell@linaro.org |
| 21 | --- | 11 | --- |
| 22 | target/arm/arm-semi.c | 111 ++++++++++++++++++++++++------------------ | 12 | target/hppa/fpu_helper.c | 2 ++ |
| 23 | 1 file changed, 63 insertions(+), 48 deletions(-) | 13 | fpu/softfloat-specialize.c.inc | 13 +------------ |
| 14 | 2 files changed, 3 insertions(+), 12 deletions(-) | ||
| 24 | 15 | ||
| 25 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 16 | diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c |
| 26 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 27 | --- a/target/arm/arm-semi.c | 18 | --- a/target/hppa/fpu_helper.c |
| 28 | +++ b/target/arm/arm-semi.c | 19 | +++ b/target/hppa/fpu_helper.c |
| 29 | @@ -XXX,XX +XXX,XX @@ static GuestFD *get_guestfd(int guestfd) | 20 | @@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env) |
| 30 | return gf; | 21 | * HPPA does note implement a CPU reset method at all... |
| 22 | */ | ||
| 23 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); | ||
| 24 | + /* For inf * 0 + NaN, return the input NaN */ | ||
| 25 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
| 31 | } | 26 | } |
| 32 | 27 | ||
| 33 | -#ifdef CONFIG_USER_ONLY | 28 | void cpu_hppa_loaded_fr0(CPUHPPAState *env) |
| 34 | -static inline uint32_t set_swi_errno(TaskState *ts, uint32_t code) | 29 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 35 | -{ | 30 | index XXXXXXX..XXXXXXX 100644 |
| 36 | - if (code == (uint32_t)-1) | 31 | --- a/fpu/softfloat-specialize.c.inc |
| 37 | - ts->swi_errno = errno; | 32 | +++ b/fpu/softfloat-specialize.c.inc |
| 38 | - return code; | 33 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, |
| 39 | -} | 34 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 40 | -#else | 35 | bool infzero, float_status *status) |
| 41 | +/* | ||
| 42 | + * The semihosting API has no concept of its errno being thread-safe, | ||
| 43 | + * as the API design predates SMP CPUs and was intended as a simple | ||
| 44 | + * real-hardware set of debug functionality. For QEMU, we make the | ||
| 45 | + * errno be per-thread in linux-user mode; in softmmu it is a simple | ||
| 46 | + * global, and we assume that the guest takes care of avoiding any races. | ||
| 47 | + */ | ||
| 48 | +#ifndef CONFIG_USER_ONLY | ||
| 49 | static target_ulong syscall_err; | ||
| 50 | |||
| 51 | +#include "exec/softmmu-semi.h" | ||
| 52 | +#endif | ||
| 53 | + | ||
| 54 | static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code) | ||
| 55 | { | 36 | { |
| 56 | if (code == (uint32_t)-1) { | 37 | - FloatInfZeroNaNRule rule = status->float_infzeronan_rule; |
| 57 | +#ifdef CONFIG_USER_ONLY | 38 | - |
| 58 | + CPUState *cs = env_cpu(env); | 39 | /* |
| 59 | + TaskState *ts = cs->opaque; | 40 | * We guarantee not to require the target to tell us how to |
| 60 | + | 41 | * pick a NaN if we're always returning the default NaN. |
| 61 | + ts->swi_errno = errno; | 42 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 62 | +#else | 43 | */ |
| 63 | syscall_err = errno; | 44 | assert(!status->default_nan_mode); |
| 64 | +#endif | 45 | |
| 65 | } | 46 | - if (rule == float_infzeronan_none) { |
| 66 | return code; | 47 | - /* |
| 67 | } | 48 | - * Temporarily fall back to ifdef ladder |
| 68 | 49 | - */ | |
| 69 | -#include "exec/softmmu-semi.h" | 50 | -#if defined(TARGET_HPPA) |
| 70 | +static inline uint32_t get_swi_errno(CPUARMState *env) | 51 | - rule = float_infzeronan_dnan_never; |
| 71 | +{ | ||
| 72 | +#ifdef CONFIG_USER_ONLY | ||
| 73 | + CPUState *cs = env_cpu(env); | ||
| 74 | + TaskState *ts = cs->opaque; | ||
| 75 | + | ||
| 76 | + return ts->swi_errno; | ||
| 77 | +#else | ||
| 78 | + return syscall_err; | ||
| 79 | #endif | ||
| 80 | +} | ||
| 81 | |||
| 82 | static target_ulong arm_semi_syscall_len; | ||
| 83 | |||
| 84 | @@ -XXX,XX +XXX,XX @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, | ||
| 85 | if (is_a64(env)) { \ | ||
| 86 | if (get_user_u64(arg ## n, args + (n) * 8)) { \ | ||
| 87 | errno = EFAULT; \ | ||
| 88 | - return set_swi_errno(ts, -1); \ | ||
| 89 | + return set_swi_errno(env, -1); \ | ||
| 90 | } \ | ||
| 91 | } else { \ | ||
| 92 | if (get_user_u32(arg ## n, args + (n) * 4)) { \ | ||
| 93 | errno = EFAULT; \ | ||
| 94 | - return set_swi_errno(ts, -1); \ | ||
| 95 | + return set_swi_errno(env, -1); \ | ||
| 96 | } \ | ||
| 97 | } \ | ||
| 98 | } while (0) | ||
| 99 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 100 | int nr; | ||
| 101 | uint32_t ret; | ||
| 102 | uint32_t len; | ||
| 103 | -#ifdef CONFIG_USER_ONLY | ||
| 104 | - TaskState *ts = cs->opaque; | ||
| 105 | -#else | ||
| 106 | - CPUARMState *ts = env; | ||
| 107 | -#endif | 52 | -#endif |
| 108 | GuestFD *gf; | 53 | - } |
| 109 | 54 | - | |
| 110 | if (is_a64(env)) { | 55 | if (infzero) { |
| 111 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | 56 | /* |
| 112 | s = lock_user_string(arg0); | 57 | * Inf * 0 + NaN -- some implementations return the default NaN here, |
| 113 | if (!s) { | 58 | * and some return the input NaN. |
| 114 | errno = EFAULT; | 59 | */ |
| 115 | - return set_swi_errno(ts, -1); | 60 | - switch (rule) { |
| 116 | + return set_swi_errno(env, -1); | 61 | + switch (status->float_infzeronan_rule) { |
| 117 | } | 62 | case float_infzeronan_dnan_never: |
| 118 | if (arg1 >= 12) { | 63 | return 2; |
| 119 | unlock_user(s, arg0, 0); | 64 | case float_infzeronan_dnan_always: |
| 120 | errno = EINVAL; | ||
| 121 | - return set_swi_errno(ts, -1); | ||
| 122 | + return set_swi_errno(env, -1); | ||
| 123 | } | ||
| 124 | |||
| 125 | guestfd = alloc_guestfd(); | ||
| 126 | if (guestfd < 0) { | ||
| 127 | unlock_user(s, arg0, 0); | ||
| 128 | errno = EMFILE; | ||
| 129 | - return set_swi_errno(ts, -1); | ||
| 130 | + return set_swi_errno(env, -1); | ||
| 131 | } | ||
| 132 | |||
| 133 | if (strcmp(s, ":tt") == 0) { | ||
| 134 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 135 | ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0, | ||
| 136 | (int)arg2+1, gdb_open_modeflags[arg1]); | ||
| 137 | } else { | ||
| 138 | - ret = set_swi_errno(ts, open(s, open_modeflags[arg1], 0644)); | ||
| 139 | + ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644)); | ||
| 140 | if (ret == (uint32_t)-1) { | ||
| 141 | dealloc_guestfd(guestfd); | ||
| 142 | } else { | ||
| 143 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 144 | gf = get_guestfd(arg0); | ||
| 145 | if (!gf) { | ||
| 146 | errno = EBADF; | ||
| 147 | - return set_swi_errno(ts, -1); | ||
| 148 | + return set_swi_errno(env, -1); | ||
| 149 | } | ||
| 150 | |||
| 151 | if (use_gdb_syscalls()) { | ||
| 152 | ret = arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); | ||
| 153 | } else { | ||
| 154 | - ret = set_swi_errno(ts, close(gf->hostfd)); | ||
| 155 | + ret = set_swi_errno(env, close(gf->hostfd)); | ||
| 156 | } | ||
| 157 | dealloc_guestfd(arg0); | ||
| 158 | return ret; | ||
| 159 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 160 | gf = get_guestfd(arg0); | ||
| 161 | if (!gf) { | ||
| 162 | errno = EBADF; | ||
| 163 | - return set_swi_errno(ts, -1); | ||
| 164 | + return set_swi_errno(env, -1); | ||
| 165 | } | ||
| 166 | |||
| 167 | if (use_gdb_syscalls()) { | ||
| 168 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 169 | /* Return bytes not written on error */ | ||
| 170 | return len; | ||
| 171 | } | ||
| 172 | - ret = set_swi_errno(ts, write(gf->hostfd, s, len)); | ||
| 173 | + ret = set_swi_errno(env, write(gf->hostfd, s, len)); | ||
| 174 | unlock_user(s, arg1, 0); | ||
| 175 | if (ret == (uint32_t)-1) { | ||
| 176 | ret = 0; | ||
| 177 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 178 | gf = get_guestfd(arg0); | ||
| 179 | if (!gf) { | ||
| 180 | errno = EBADF; | ||
| 181 | - return set_swi_errno(ts, -1); | ||
| 182 | + return set_swi_errno(env, -1); | ||
| 183 | } | ||
| 184 | |||
| 185 | if (use_gdb_syscalls()) { | ||
| 186 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 187 | return len; | ||
| 188 | } | ||
| 189 | do { | ||
| 190 | - ret = set_swi_errno(ts, read(gf->hostfd, s, len)); | ||
| 191 | + ret = set_swi_errno(env, read(gf->hostfd, s, len)); | ||
| 192 | } while (ret == -1 && errno == EINTR); | ||
| 193 | unlock_user(s, arg1, len); | ||
| 194 | if (ret == (uint32_t)-1) { | ||
| 195 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 196 | gf = get_guestfd(arg0); | ||
| 197 | if (!gf) { | ||
| 198 | errno = EBADF; | ||
| 199 | - return set_swi_errno(ts, -1); | ||
| 200 | + return set_swi_errno(env, -1); | ||
| 201 | } | ||
| 202 | |||
| 203 | if (use_gdb_syscalls()) { | ||
| 204 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 205 | gf = get_guestfd(arg0); | ||
| 206 | if (!gf) { | ||
| 207 | errno = EBADF; | ||
| 208 | - return set_swi_errno(ts, -1); | ||
| 209 | + return set_swi_errno(env, -1); | ||
| 210 | } | ||
| 211 | |||
| 212 | if (use_gdb_syscalls()) { | ||
| 213 | return arm_gdb_syscall(cpu, arm_semi_cb, "lseek,%x,%x,0", | ||
| 214 | gf->hostfd, arg1); | ||
| 215 | } else { | ||
| 216 | - ret = set_swi_errno(ts, lseek(gf->hostfd, arg1, SEEK_SET)); | ||
| 217 | + ret = set_swi_errno(env, lseek(gf->hostfd, arg1, SEEK_SET)); | ||
| 218 | if (ret == (uint32_t)-1) | ||
| 219 | return -1; | ||
| 220 | return 0; | ||
| 221 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 222 | gf = get_guestfd(arg0); | ||
| 223 | if (!gf) { | ||
| 224 | errno = EBADF; | ||
| 225 | - return set_swi_errno(ts, -1); | ||
| 226 | + return set_swi_errno(env, -1); | ||
| 227 | } | ||
| 228 | |||
| 229 | if (use_gdb_syscalls()) { | ||
| 230 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 231 | gf->hostfd, arm_flen_buf(cpu)); | ||
| 232 | } else { | ||
| 233 | struct stat buf; | ||
| 234 | - ret = set_swi_errno(ts, fstat(gf->hostfd, &buf)); | ||
| 235 | + ret = set_swi_errno(env, fstat(gf->hostfd, &buf)); | ||
| 236 | if (ret == (uint32_t)-1) | ||
| 237 | return -1; | ||
| 238 | return buf.st_size; | ||
| 239 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 240 | s = lock_user_string(arg0); | ||
| 241 | if (!s) { | ||
| 242 | errno = EFAULT; | ||
| 243 | - return set_swi_errno(ts, -1); | ||
| 244 | + return set_swi_errno(env, -1); | ||
| 245 | } | ||
| 246 | - ret = set_swi_errno(ts, remove(s)); | ||
| 247 | + ret = set_swi_errno(env, remove(s)); | ||
| 248 | unlock_user(s, arg0, 0); | ||
| 249 | } | ||
| 250 | return ret; | ||
| 251 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 252 | s2 = lock_user_string(arg2); | ||
| 253 | if (!s || !s2) { | ||
| 254 | errno = EFAULT; | ||
| 255 | - ret = set_swi_errno(ts, -1); | ||
| 256 | + ret = set_swi_errno(env, -1); | ||
| 257 | } else { | ||
| 258 | - ret = set_swi_errno(ts, rename(s, s2)); | ||
| 259 | + ret = set_swi_errno(env, rename(s, s2)); | ||
| 260 | } | ||
| 261 | if (s2) | ||
| 262 | unlock_user(s2, arg2, 0); | ||
| 263 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 264 | case TARGET_SYS_CLOCK: | ||
| 265 | return clock() / (CLOCKS_PER_SEC / 100); | ||
| 266 | case TARGET_SYS_TIME: | ||
| 267 | - return set_swi_errno(ts, time(NULL)); | ||
| 268 | + return set_swi_errno(env, time(NULL)); | ||
| 269 | case TARGET_SYS_SYSTEM: | ||
| 270 | GET_ARG(0); | ||
| 271 | GET_ARG(1); | ||
| 272 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 273 | s = lock_user_string(arg0); | ||
| 274 | if (!s) { | ||
| 275 | errno = EFAULT; | ||
| 276 | - return set_swi_errno(ts, -1); | ||
| 277 | + return set_swi_errno(env, -1); | ||
| 278 | } | ||
| 279 | - ret = set_swi_errno(ts, system(s)); | ||
| 280 | + ret = set_swi_errno(env, system(s)); | ||
| 281 | unlock_user(s, arg0, 0); | ||
| 282 | return ret; | ||
| 283 | } | ||
| 284 | case TARGET_SYS_ERRNO: | ||
| 285 | -#ifdef CONFIG_USER_ONLY | ||
| 286 | - return ts->swi_errno; | ||
| 287 | -#else | ||
| 288 | - return syscall_err; | ||
| 289 | -#endif | ||
| 290 | + return get_swi_errno(env); | ||
| 291 | case TARGET_SYS_GET_CMDLINE: | ||
| 292 | { | ||
| 293 | /* Build a command-line from the original argv. | ||
| 294 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 295 | int status = 0; | ||
| 296 | #if !defined(CONFIG_USER_ONLY) | ||
| 297 | const char *cmdline; | ||
| 298 | +#else | ||
| 299 | + TaskState *ts = cs->opaque; | ||
| 300 | #endif | ||
| 301 | GET_ARG(0); | ||
| 302 | GET_ARG(1); | ||
| 303 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 304 | if (output_size > input_size) { | ||
| 305 | /* Not enough space to store command-line arguments. */ | ||
| 306 | errno = E2BIG; | ||
| 307 | - return set_swi_errno(ts, -1); | ||
| 308 | + return set_swi_errno(env, -1); | ||
| 309 | } | ||
| 310 | |||
| 311 | /* Adjust the command-line length. */ | ||
| 312 | if (SET_ARG(1, output_size - 1)) { | ||
| 313 | /* Couldn't write back to argument block */ | ||
| 314 | errno = EFAULT; | ||
| 315 | - return set_swi_errno(ts, -1); | ||
| 316 | + return set_swi_errno(env, -1); | ||
| 317 | } | ||
| 318 | |||
| 319 | /* Lock the buffer on the ARM side. */ | ||
| 320 | output_buffer = lock_user(VERIFY_WRITE, arg0, output_size, 0); | ||
| 321 | if (!output_buffer) { | ||
| 322 | errno = EFAULT; | ||
| 323 | - return set_swi_errno(ts, -1); | ||
| 324 | + return set_swi_errno(env, -1); | ||
| 325 | } | ||
| 326 | |||
| 327 | /* Copy the command-line arguments. */ | ||
| 328 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 329 | if (copy_from_user(output_buffer, ts->info->arg_start, | ||
| 330 | output_size)) { | ||
| 331 | errno = EFAULT; | ||
| 332 | - status = set_swi_errno(ts, -1); | ||
| 333 | + status = set_swi_errno(env, -1); | ||
| 334 | goto out; | ||
| 335 | } | ||
| 336 | |||
| 337 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 338 | target_ulong retvals[4]; | ||
| 339 | target_ulong limit; | ||
| 340 | int i; | ||
| 341 | +#ifdef CONFIG_USER_ONLY | ||
| 342 | + TaskState *ts = cs->opaque; | ||
| 343 | +#endif | ||
| 344 | |||
| 345 | GET_ARG(0); | ||
| 346 | |||
| 347 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 348 | if (fail) { | ||
| 349 | /* Couldn't write back to argument block */ | ||
| 350 | errno = EFAULT; | ||
| 351 | - return set_swi_errno(ts, -1); | ||
| 352 | + return set_swi_errno(env, -1); | ||
| 353 | } | ||
| 354 | } | ||
| 355 | return 0; | ||
| 356 | -- | 65 | -- |
| 357 | 2.20.1 | 66 | 2.34.1 |
| 358 | |||
| 359 | diff view generated by jsdifflib |
| 1 | Switch the cmsdk-apb-timer code away from bottom-half based ptimers | 1 | The new implementation of pickNaNMulAdd() will find it convenient |
|---|---|---|---|
| 2 | to the new transaction-based ptimer API. This just requires adding | 2 | to know whether at least one of the three arguments to the muladd |
| 3 | begin/commit calls around the various places that modify the ptimer | 3 | was a signaling NaN. We already calculate that in the caller, |
| 4 | state, and using the new ptimer_init() function to create the timer. | 4 | so pass it in as a new bool have_snan. |
| 5 | 5 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Message-id: 20191008171740.9679-10-peter.maydell@linaro.org | 8 | Message-id: 20241202131347.498124-15-peter.maydell@linaro.org |
| 9 | --- | 9 | --- |
| 10 | hw/timer/cmsdk-apb-timer.c | 15 +++++++++++---- | 10 | fpu/softfloat-parts.c.inc | 5 +++-- |
| 11 | 1 file changed, 11 insertions(+), 4 deletions(-) | 11 | fpu/softfloat-specialize.c.inc | 2 +- |
| 12 | 2 files changed, 4 insertions(+), 3 deletions(-) | ||
| 12 | 13 | ||
| 13 | diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c | 14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
| 14 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/hw/timer/cmsdk-apb-timer.c | 16 | --- a/fpu/softfloat-parts.c.inc |
| 16 | +++ b/hw/timer/cmsdk-apb-timer.c | 17 | +++ b/fpu/softfloat-parts.c.inc |
| 17 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
| 18 | |||
| 19 | #include "qemu/osdep.h" | ||
| 20 | #include "qemu/log.h" | ||
| 21 | -#include "qemu/main-loop.h" | ||
| 22 | #include "qemu/module.h" | ||
| 23 | #include "qapi/error.h" | ||
| 24 | #include "trace.h" | ||
| 25 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value, | ||
| 26 | "CMSDK APB timer: EXTIN input not supported\n"); | ||
| 27 | } | ||
| 28 | s->ctrl = value & 0xf; | ||
| 29 | + ptimer_transaction_begin(s->timer); | ||
| 30 | if (s->ctrl & R_CTRL_EN_MASK) { | ||
| 31 | ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0); | ||
| 32 | } else { | ||
| 33 | ptimer_stop(s->timer); | ||
| 34 | } | ||
| 35 | + ptimer_transaction_commit(s->timer); | ||
| 36 | break; | ||
| 37 | case A_RELOAD: | ||
| 38 | /* Writing to reload also sets the current timer value */ | ||
| 39 | + ptimer_transaction_begin(s->timer); | ||
| 40 | if (!value) { | ||
| 41 | ptimer_stop(s->timer); | ||
| 42 | } | ||
| 43 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value, | ||
| 44 | */ | ||
| 45 | ptimer_run(s->timer, 0); | ||
| 46 | } | ||
| 47 | + ptimer_transaction_commit(s->timer); | ||
| 48 | break; | ||
| 49 | case A_VALUE: | ||
| 50 | + ptimer_transaction_begin(s->timer); | ||
| 51 | if (!value && !ptimer_get_limit(s->timer)) { | ||
| 52 | ptimer_stop(s->timer); | ||
| 53 | } | ||
| 54 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value, | ||
| 55 | if (value && (s->ctrl & R_CTRL_EN_MASK)) { | ||
| 56 | ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0); | ||
| 57 | } | ||
| 58 | + ptimer_transaction_commit(s->timer); | ||
| 59 | break; | ||
| 60 | case A_INTSTATUS: | ||
| 61 | /* Just one bit, which is W1C. */ | ||
| 62 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_reset(DeviceState *dev) | ||
| 63 | trace_cmsdk_apb_timer_reset(); | ||
| 64 | s->ctrl = 0; | ||
| 65 | s->intstatus = 0; | ||
| 66 | + ptimer_transaction_begin(s->timer); | ||
| 67 | ptimer_stop(s->timer); | ||
| 68 | /* Set the limit and the count */ | ||
| 69 | ptimer_set_limit(s->timer, 0, 1); | ||
| 70 | + ptimer_transaction_commit(s->timer); | ||
| 71 | } | ||
| 72 | |||
| 73 | static void cmsdk_apb_timer_init(Object *obj) | ||
| 74 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_init(Object *obj) | ||
| 75 | static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) | ||
| 76 | { | 19 | { |
| 77 | CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev); | 20 | int which; |
| 78 | - QEMUBH *bh; | 21 | bool infzero = (ab_mask == float_cmask_infzero); |
| 79 | 22 | + bool have_snan = (abc_mask & float_cmask_snan); | |
| 80 | if (s->pclk_frq == 0) { | 23 | |
| 81 | error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); | 24 | - if (unlikely(abc_mask & float_cmask_snan)) { |
| 82 | return; | 25 | + if (unlikely(have_snan)) { |
| 26 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); | ||
| 83 | } | 27 | } |
| 84 | 28 | ||
| 85 | - bh = qemu_bh_new(cmsdk_apb_timer_tick, s); | 29 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
| 86 | - s->timer = ptimer_init_with_bh(bh, | 30 | if (s->default_nan_mode) { |
| 87 | + s->timer = ptimer_init(cmsdk_apb_timer_tick, s, | 31 | which = 3; |
| 88 | PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | | 32 | } else { |
| 89 | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | | 33 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); |
| 90 | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | | 34 | + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s); |
| 91 | PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | 35 | } |
| 92 | 36 | ||
| 93 | + ptimer_transaction_begin(s->timer); | 37 | if (which == 3) { |
| 94 | ptimer_set_freq(s->timer, s->pclk_frq); | 38 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 95 | + ptimer_transaction_commit(s->timer); | 39 | index XXXXXXX..XXXXXXX 100644 |
| 96 | } | 40 | --- a/fpu/softfloat-specialize.c.inc |
| 97 | 41 | +++ b/fpu/softfloat-specialize.c.inc | |
| 98 | static const VMStateDescription cmsdk_apb_timer_vmstate = { | 42 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, |
| 43 | | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN | ||
| 44 | *----------------------------------------------------------------------------*/ | ||
| 45 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 46 | - bool infzero, float_status *status) | ||
| 47 | + bool infzero, bool have_snan, float_status *status) | ||
| 48 | { | ||
| 49 | /* | ||
| 50 | * We guarantee not to require the target to tell us how to | ||
| 99 | -- | 51 | -- |
| 100 | 2.20.1 | 52 | 2.34.1 |
| 101 | |||
| 102 | diff view generated by jsdifflib |
| 1 | Switch the arm_mptimer.c code away from bottom-half based ptimers to | 1 | IEEE 758 does not define a fixed rule for which NaN to pick as the |
|---|---|---|---|
| 2 | the new transaction-based ptimer API. This just requires adding | 2 | result if both operands of a 3-operand fused multiply-add operation |
| 3 | begin/commit calls around the various places that modify the ptimer | 3 | are NaNs. As a result different architectures have ended up with |
| 4 | state, and using the new ptimer_init() function to create the timer. | 4 | different rules for propagating NaNs. |
| 5 | |||
| 6 | QEMU currently hardcodes the NaN propagation logic into the binary | ||
| 7 | because pickNaNMulAdd() has an ifdef ladder for different targets. | ||
| 8 | We want to make the propagation rule instead be selectable at | ||
| 9 | runtime, because: | ||
| 10 | * this will let us have multiple targets in one QEMU binary | ||
| 11 | * the Arm FEAT_AFP architectural feature includes letting | ||
| 12 | the guest select a NaN propagation rule at runtime | ||
| 13 | |||
| 14 | In this commit we add an enum for the propagation rule, the field in | ||
| 15 | float_status, and the corresponding getters and setters. We change | ||
| 16 | pickNaNMulAdd to honour this, but because all targets still leave | ||
| 17 | this field at its default 0 value, the fallback logic will pick the | ||
| 18 | rule type with the old ifdef ladder. | ||
| 19 | |||
| 20 | It's valid not to set a propagation rule if default_nan_mode is | ||
| 21 | enabled, because in that case there's no need to pick a NaN; all the | ||
| 22 | callers of pickNaNMulAdd() catch this case and skip calling it. | ||
| 5 | 23 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 25 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Message-id: 20191008171740.9679-8-peter.maydell@linaro.org | 26 | Message-id: 20241202131347.498124-16-peter.maydell@linaro.org |
| 9 | --- | 27 | --- |
| 10 | hw/timer/arm_mptimer.c | 14 +++++++++++--- | 28 | include/fpu/softfloat-helpers.h | 11 +++ |
| 11 | 1 file changed, 11 insertions(+), 3 deletions(-) | 29 | include/fpu/softfloat-types.h | 55 +++++++++++ |
| 12 | 30 | fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------ | |
| 13 | diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c | 31 | 3 files changed, 107 insertions(+), 126 deletions(-) |
| 32 | |||
| 33 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/hw/timer/arm_mptimer.c | 35 | --- a/include/fpu/softfloat-helpers.h |
| 16 | +++ b/hw/timer/arm_mptimer.c | 36 | +++ b/include/fpu/softfloat-helpers.h |
| 17 | @@ -XXX,XX +XXX,XX @@ | 37 | @@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, |
| 18 | #include "hw/timer/arm_mptimer.h" | 38 | status->float_2nan_prop_rule = rule; |
| 19 | #include "migration/vmstate.h" | ||
| 20 | #include "qapi/error.h" | ||
| 21 | -#include "qemu/main-loop.h" | ||
| 22 | #include "qemu/module.h" | ||
| 23 | #include "hw/core/cpu.h" | ||
| 24 | |||
| 25 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t timerblock_scale(uint32_t control) | ||
| 26 | return (((control >> 8) & 0xff) + 1) * 10; | ||
| 27 | } | 39 | } |
| 28 | 40 | ||
| 29 | +/* Must be called within a ptimer transaction block */ | 41 | +static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule, |
| 30 | static inline void timerblock_set_count(struct ptimer_state *timer, | 42 | + float_status *status) |
| 31 | uint32_t control, uint64_t *count) | 43 | +{ |
| 44 | + status->float_3nan_prop_rule = rule; | ||
| 45 | +} | ||
| 46 | + | ||
| 47 | static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, | ||
| 48 | float_status *status) | ||
| 32 | { | 49 | { |
| 33 | @@ -XXX,XX +XXX,XX @@ static inline void timerblock_set_count(struct ptimer_state *timer, | 50 | @@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) |
| 34 | ptimer_set_count(timer, *count); | 51 | return status->float_2nan_prop_rule; |
| 35 | } | 52 | } |
| 36 | 53 | ||
| 37 | +/* Must be called within a ptimer transaction block */ | 54 | +static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status) |
| 38 | static inline void timerblock_run(struct ptimer_state *timer, | 55 | +{ |
| 39 | uint32_t control, uint32_t load) | 56 | + return status->float_3nan_prop_rule; |
| 57 | +} | ||
| 58 | + | ||
| 59 | static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) | ||
| 40 | { | 60 | { |
| 41 | @@ -XXX,XX +XXX,XX @@ static void timerblock_write(void *opaque, hwaddr addr, | 61 | return status->float_infzeronan_rule; |
| 42 | uint32_t control = tb->control; | 62 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h |
| 43 | switch (addr) { | 63 | index XXXXXXX..XXXXXXX 100644 |
| 44 | case 0: /* Load */ | 64 | --- a/include/fpu/softfloat-types.h |
| 45 | + ptimer_transaction_begin(tb->timer); | 65 | +++ b/include/fpu/softfloat-types.h |
| 46 | /* Setting load to 0 stops the timer without doing the tick if | 66 | @@ -XXX,XX +XXX,XX @@ this code that are retained. |
| 47 | * prescaler = 0. | 67 | #ifndef SOFTFLOAT_TYPES_H |
| 48 | */ | 68 | #define SOFTFLOAT_TYPES_H |
| 49 | @@ -XXX,XX +XXX,XX @@ static void timerblock_write(void *opaque, hwaddr addr, | 69 | |
| 70 | +#include "hw/registerfields.h" | ||
| 71 | + | ||
| 72 | /* | ||
| 73 | * Software IEC/IEEE floating-point types. | ||
| 74 | */ | ||
| 75 | @@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) { | ||
| 76 | float_2nan_prop_x87, | ||
| 77 | } Float2NaNPropRule; | ||
| 78 | |||
| 79 | +/* | ||
| 80 | + * 3-input NaN propagation rule, for fused multiply-add. Individual | ||
| 81 | + * architectures have different rules for which input NaN is | ||
| 82 | + * propagated to the output when there is more than one NaN on the | ||
| 83 | + * input. | ||
| 84 | + * | ||
| 85 | + * If default_nan_mode is enabled then it is valid not to set a NaN | ||
| 86 | + * propagation rule, because the softfloat code guarantees not to try | ||
| 87 | + * to pick a NaN to propagate in default NaN mode. When not in | ||
| 88 | + * default-NaN mode, it is an error for the target not to set the rule | ||
| 89 | + * in float_status if it uses a muladd, and we will assert if we need | ||
| 90 | + * to handle an input NaN and no rule was selected. | ||
| 91 | + * | ||
| 92 | + * The naming scheme for Float3NaNPropRule values is: | ||
| 93 | + * float_3nan_prop_s_abc: | ||
| 94 | + * = "Prefer SNaN over QNaN, then operand A over B over C" | ||
| 95 | + * float_3nan_prop_abc: | ||
| 96 | + * = "Prefer A over B over C regardless of SNaN vs QNAN" | ||
| 97 | + * | ||
| 98 | + * For QEMU, the multiply-add operation is A * B + C. | ||
| 99 | + */ | ||
| 100 | + | ||
| 101 | +/* | ||
| 102 | + * We set the Float3NaNPropRule enum values up so we can select the | ||
| 103 | + * right value in pickNaNMulAdd in a data driven way. | ||
| 104 | + */ | ||
| 105 | +FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */ | ||
| 106 | +FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */ | ||
| 107 | +FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */ | ||
| 108 | +FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */ | ||
| 109 | + | ||
| 110 | +#define PROPRULE(X, Y, Z) \ | ||
| 111 | + ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT)) | ||
| 112 | + | ||
| 113 | +typedef enum __attribute__((__packed__)) { | ||
| 114 | + float_3nan_prop_none = 0, /* No propagation rule specified */ | ||
| 115 | + float_3nan_prop_abc = PROPRULE(0, 1, 2), | ||
| 116 | + float_3nan_prop_acb = PROPRULE(0, 2, 1), | ||
| 117 | + float_3nan_prop_bac = PROPRULE(1, 0, 2), | ||
| 118 | + float_3nan_prop_bca = PROPRULE(1, 2, 0), | ||
| 119 | + float_3nan_prop_cab = PROPRULE(2, 0, 1), | ||
| 120 | + float_3nan_prop_cba = PROPRULE(2, 1, 0), | ||
| 121 | + float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK, | ||
| 122 | + float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK, | ||
| 123 | + float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK, | ||
| 124 | + float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK, | ||
| 125 | + float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK, | ||
| 126 | + float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK, | ||
| 127 | +} Float3NaNPropRule; | ||
| 128 | + | ||
| 129 | +#undef PROPRULE | ||
| 130 | + | ||
| 131 | /* | ||
| 132 | * Rule for result of fused multiply-add 0 * Inf + NaN. | ||
| 133 | * This must be a NaN, but implementations differ on whether this | ||
| 134 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { | ||
| 135 | FloatRoundMode float_rounding_mode; | ||
| 136 | FloatX80RoundPrec floatx80_rounding_precision; | ||
| 137 | Float2NaNPropRule float_2nan_prop_rule; | ||
| 138 | + Float3NaNPropRule float_3nan_prop_rule; | ||
| 139 | FloatInfZeroNaNRule float_infzeronan_rule; | ||
| 140 | bool tininess_before_rounding; | ||
| 141 | /* should denormalised results go to zero and set the inexact flag? */ | ||
| 142 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 143 | index XXXXXXX..XXXXXXX 100644 | ||
| 144 | --- a/fpu/softfloat-specialize.c.inc | ||
| 145 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 146 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
| 147 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 148 | bool infzero, bool have_snan, float_status *status) | ||
| 149 | { | ||
| 150 | + FloatClass cls[3] = { a_cls, b_cls, c_cls }; | ||
| 151 | + Float3NaNPropRule rule = status->float_3nan_prop_rule; | ||
| 152 | + int which; | ||
| 153 | + | ||
| 154 | /* | ||
| 155 | * We guarantee not to require the target to tell us how to | ||
| 156 | * pick a NaN if we're always returning the default NaN. | ||
| 157 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 50 | } | 158 | } |
| 51 | ptimer_set_limit(tb->timer, value, 1); | 159 | } |
| 52 | timerblock_run(tb->timer, control, value); | 160 | |
| 53 | + ptimer_transaction_commit(tb->timer); | 161 | + if (rule == float_3nan_prop_none) { |
| 54 | break; | 162 | #if defined(TARGET_ARM) |
| 55 | case 4: /* Counter. */ | 163 | - |
| 56 | + ptimer_transaction_begin(tb->timer); | 164 | - /* This looks different from the ARM ARM pseudocode, because the ARM ARM |
| 57 | /* Setting counter to 0 stops the one-shot timer, or periodic with | 165 | - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. |
| 58 | * load = 0, without doing the tick if prescaler = 0. | 166 | - */ |
| 59 | */ | 167 | - if (is_snan(c_cls)) { |
| 60 | @@ -XXX,XX +XXX,XX @@ static void timerblock_write(void *opaque, hwaddr addr, | 168 | - return 2; |
| 169 | - } else if (is_snan(a_cls)) { | ||
| 170 | - return 0; | ||
| 171 | - } else if (is_snan(b_cls)) { | ||
| 172 | - return 1; | ||
| 173 | - } else if (is_qnan(c_cls)) { | ||
| 174 | - return 2; | ||
| 175 | - } else if (is_qnan(a_cls)) { | ||
| 176 | - return 0; | ||
| 177 | - } else { | ||
| 178 | - return 1; | ||
| 179 | - } | ||
| 180 | + /* | ||
| 181 | + * This looks different from the ARM ARM pseudocode, because the ARM ARM | ||
| 182 | + * puts the operands to a fused mac operation (a*b)+c in the order c,a,b | ||
| 183 | + */ | ||
| 184 | + rule = float_3nan_prop_s_cab; | ||
| 185 | #elif defined(TARGET_MIPS) | ||
| 186 | - if (snan_bit_is_one(status)) { | ||
| 187 | - /* Prefer sNaN over qNaN, in the a, b, c order. */ | ||
| 188 | - if (is_snan(a_cls)) { | ||
| 189 | - return 0; | ||
| 190 | - } else if (is_snan(b_cls)) { | ||
| 191 | - return 1; | ||
| 192 | - } else if (is_snan(c_cls)) { | ||
| 193 | - return 2; | ||
| 194 | - } else if (is_qnan(a_cls)) { | ||
| 195 | - return 0; | ||
| 196 | - } else if (is_qnan(b_cls)) { | ||
| 197 | - return 1; | ||
| 198 | + if (snan_bit_is_one(status)) { | ||
| 199 | + rule = float_3nan_prop_s_abc; | ||
| 200 | } else { | ||
| 201 | - return 2; | ||
| 202 | + rule = float_3nan_prop_s_cab; | ||
| 61 | } | 203 | } |
| 62 | timerblock_set_count(tb->timer, control, &value); | 204 | - } else { |
| 63 | timerblock_run(tb->timer, control, value); | 205 | - /* Prefer sNaN over qNaN, in the c, a, b order. */ |
| 64 | + ptimer_transaction_commit(tb->timer); | 206 | - if (is_snan(c_cls)) { |
| 65 | break; | 207 | - return 2; |
| 66 | case 8: /* Control. */ | 208 | - } else if (is_snan(a_cls)) { |
| 67 | + ptimer_transaction_begin(tb->timer); | 209 | - return 0; |
| 68 | if ((control & 3) != (value & 3)) { | 210 | - } else if (is_snan(b_cls)) { |
| 69 | ptimer_stop(tb->timer); | 211 | - return 1; |
| 212 | - } else if (is_qnan(c_cls)) { | ||
| 213 | - return 2; | ||
| 214 | - } else if (is_qnan(a_cls)) { | ||
| 215 | - return 0; | ||
| 216 | - } else { | ||
| 217 | - return 1; | ||
| 218 | - } | ||
| 219 | - } | ||
| 220 | #elif defined(TARGET_LOONGARCH64) | ||
| 221 | - /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
| 222 | - if (is_snan(c_cls)) { | ||
| 223 | - return 2; | ||
| 224 | - } else if (is_snan(a_cls)) { | ||
| 225 | - return 0; | ||
| 226 | - } else if (is_snan(b_cls)) { | ||
| 227 | - return 1; | ||
| 228 | - } else if (is_qnan(c_cls)) { | ||
| 229 | - return 2; | ||
| 230 | - } else if (is_qnan(a_cls)) { | ||
| 231 | - return 0; | ||
| 232 | - } else { | ||
| 233 | - return 1; | ||
| 234 | - } | ||
| 235 | + rule = float_3nan_prop_s_cab; | ||
| 236 | #elif defined(TARGET_PPC) | ||
| 237 | - /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
| 238 | - * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
| 239 | - */ | ||
| 240 | - if (is_nan(a_cls)) { | ||
| 241 | - return 0; | ||
| 242 | - } else if (is_nan(c_cls)) { | ||
| 243 | - return 2; | ||
| 244 | - } else { | ||
| 245 | - return 1; | ||
| 246 | - } | ||
| 247 | + /* | ||
| 248 | + * If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
| 249 | + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
| 250 | + */ | ||
| 251 | + rule = float_3nan_prop_acb; | ||
| 252 | #elif defined(TARGET_S390X) | ||
| 253 | - if (is_snan(a_cls)) { | ||
| 254 | - return 0; | ||
| 255 | - } else if (is_snan(b_cls)) { | ||
| 256 | - return 1; | ||
| 257 | - } else if (is_snan(c_cls)) { | ||
| 258 | - return 2; | ||
| 259 | - } else if (is_qnan(a_cls)) { | ||
| 260 | - return 0; | ||
| 261 | - } else if (is_qnan(b_cls)) { | ||
| 262 | - return 1; | ||
| 263 | - } else { | ||
| 264 | - return 2; | ||
| 265 | - } | ||
| 266 | + rule = float_3nan_prop_s_abc; | ||
| 267 | #elif defined(TARGET_SPARC) | ||
| 268 | - /* Prefer SNaN over QNaN, order C, B, A. */ | ||
| 269 | - if (is_snan(c_cls)) { | ||
| 270 | - return 2; | ||
| 271 | - } else if (is_snan(b_cls)) { | ||
| 272 | - return 1; | ||
| 273 | - } else if (is_snan(a_cls)) { | ||
| 274 | - return 0; | ||
| 275 | - } else if (is_qnan(c_cls)) { | ||
| 276 | - return 2; | ||
| 277 | - } else if (is_qnan(b_cls)) { | ||
| 278 | - return 1; | ||
| 279 | - } else { | ||
| 280 | - return 0; | ||
| 281 | - } | ||
| 282 | + rule = float_3nan_prop_s_cba; | ||
| 283 | #elif defined(TARGET_XTENSA) | ||
| 284 | - /* | ||
| 285 | - * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns | ||
| 286 | - * an input NaN if we have one (ie c). | ||
| 287 | - */ | ||
| 288 | - if (status->use_first_nan) { | ||
| 289 | - if (is_nan(a_cls)) { | ||
| 290 | - return 0; | ||
| 291 | - } else if (is_nan(b_cls)) { | ||
| 292 | - return 1; | ||
| 293 | + if (status->use_first_nan) { | ||
| 294 | + rule = float_3nan_prop_abc; | ||
| 295 | } else { | ||
| 296 | - return 2; | ||
| 297 | + rule = float_3nan_prop_cba; | ||
| 70 | } | 298 | } |
| 71 | @@ -XXX,XX +XXX,XX @@ static void timerblock_write(void *opaque, hwaddr addr, | 299 | - } else { |
| 72 | timerblock_run(tb->timer, value, count); | 300 | - if (is_nan(c_cls)) { |
| 73 | } | 301 | - return 2; |
| 74 | tb->control = value; | 302 | - } else if (is_nan(b_cls)) { |
| 75 | + ptimer_transaction_commit(tb->timer); | 303 | - return 1; |
| 76 | break; | 304 | - } else { |
| 77 | case 12: /* Interrupt status. */ | 305 | - return 0; |
| 78 | tb->status &= ~value; | 306 | - } |
| 79 | @@ -XXX,XX +XXX,XX @@ static void timerblock_reset(TimerBlock *tb) | 307 | - } |
| 80 | tb->control = 0; | 308 | #else |
| 81 | tb->status = 0; | 309 | - /* A default implementation: prefer a to b to c. |
| 82 | if (tb->timer) { | 310 | - * This is unlikely to actually match any real implementation. |
| 83 | + ptimer_transaction_begin(tb->timer); | 311 | - */ |
| 84 | ptimer_stop(tb->timer); | 312 | - if (is_nan(a_cls)) { |
| 85 | ptimer_set_limit(tb->timer, 0, 1); | 313 | - return 0; |
| 86 | ptimer_set_period(tb->timer, timerblock_scale(0)); | 314 | - } else if (is_nan(b_cls)) { |
| 87 | + ptimer_transaction_commit(tb->timer); | 315 | - return 1; |
| 88 | } | 316 | - } else { |
| 317 | - return 2; | ||
| 318 | - } | ||
| 319 | + rule = float_3nan_prop_abc; | ||
| 320 | #endif | ||
| 321 | + } | ||
| 322 | + | ||
| 323 | + assert(rule != float_3nan_prop_none); | ||
| 324 | + if (have_snan && (rule & R_3NAN_SNAN_MASK)) { | ||
| 325 | + /* We have at least one SNaN input and should prefer it */ | ||
| 326 | + do { | ||
| 327 | + which = rule & R_3NAN_1ST_MASK; | ||
| 328 | + rule >>= R_3NAN_1ST_LENGTH; | ||
| 329 | + } while (!is_snan(cls[which])); | ||
| 330 | + } else { | ||
| 331 | + do { | ||
| 332 | + which = rule & R_3NAN_1ST_MASK; | ||
| 333 | + rule >>= R_3NAN_1ST_LENGTH; | ||
| 334 | + } while (!is_nan(cls[which])); | ||
| 335 | + } | ||
| 336 | + return which; | ||
| 89 | } | 337 | } |
| 90 | 338 | ||
| 91 | @@ -XXX,XX +XXX,XX @@ static void arm_mptimer_realize(DeviceState *dev, Error **errp) | 339 | /*---------------------------------------------------------------------------- |
| 92 | */ | ||
| 93 | for (i = 0; i < s->num_cpu; i++) { | ||
| 94 | TimerBlock *tb = &s->timerblock[i]; | ||
| 95 | - QEMUBH *bh = qemu_bh_new(timerblock_tick, tb); | ||
| 96 | - tb->timer = ptimer_init_with_bh(bh, PTIMER_POLICY); | ||
| 97 | + tb->timer = ptimer_init(timerblock_tick, tb, PTIMER_POLICY); | ||
| 98 | sysbus_init_irq(sbd, &tb->irq); | ||
| 99 | memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, | ||
| 100 | "arm_mptimer_timerblock", 0x20); | ||
| 101 | -- | 340 | -- |
| 102 | 2.20.1 | 341 | 2.34.1 |
| 103 | |||
| 104 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Explicitly set a rule in the softfloat tests for propagating NaNs in | ||
| 2 | the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and | ||
| 3 | so we should select here the Arm rule of float_3nan_prop_s_cab. | ||
| 1 | 4 | ||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20241202131347.498124-17-peter.maydell@linaro.org | ||
| 8 | --- | ||
| 9 | tests/fp/fp-bench.c | 1 + | ||
| 10 | tests/fp/fp-test.c | 1 + | ||
| 11 | 2 files changed, 2 insertions(+) | ||
| 12 | |||
| 13 | diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/tests/fp/fp-bench.c | ||
| 16 | +++ b/tests/fp/fp-bench.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ static void run_bench(void) | ||
| 18 | * doesn't specify match those used by the Arm architecture. | ||
| 19 | */ | ||
| 20 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); | ||
| 21 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status); | ||
| 22 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); | ||
| 23 | |||
| 24 | f = bench_funcs[operation][precision]; | ||
| 25 | diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | ||
| 27 | --- a/tests/fp/fp-test.c | ||
| 28 | +++ b/tests/fp/fp-test.c | ||
| 29 | @@ -XXX,XX +XXX,XX @@ void run_test(void) | ||
| 30 | * doesn't specify match those used by the Arm architecture. | ||
| 31 | */ | ||
| 32 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); | ||
| 33 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf); | ||
| 34 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); | ||
| 35 | |||
| 36 | genCases_setLevel(test_level); | ||
| 37 | -- | ||
| 38 | 2.34.1 | diff view generated by jsdifflib |
| 1 | From: Cédric Le Goater <clg@kaod.org> | 1 | Set the Float3NaNPropRule explicitly for Arm, and remove the |
|---|---|---|---|
| 2 | ifdef from pickNaNMulAdd(). | ||
| 2 | 3 | ||
| 3 | AST2600 will use a different encoding for the addresses defined in the | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 4 | Segment Register. | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 6 | Message-id: 20241202131347.498124-18-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/arm/cpu.c | 5 +++++ | ||
| 9 | fpu/softfloat-specialize.c.inc | 8 +------- | ||
| 10 | 2 files changed, 6 insertions(+), 7 deletions(-) | ||
| 5 | 11 | ||
| 6 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 12 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
| 7 | Acked-by: Joel Stanley <joel@jms.id.au> | ||
| 8 | Message-id: 20190925143248.10000-13-clg@kaod.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | include/hw/ssi/aspeed_smc.h | 4 ++++ | ||
| 12 | hw/ssi/aspeed_smc.c | 45 ++++++++++++++++++++++++------------- | ||
| 13 | 2 files changed, 34 insertions(+), 15 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/include/hw/ssi/aspeed_smc.h | 14 | --- a/target/arm/cpu.c |
| 18 | +++ b/include/hw/ssi/aspeed_smc.h | 15 | +++ b/target/arm/cpu.c |
| 19 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSMCController { | 16 | @@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
| 20 | hwaddr dma_flash_mask; | 17 | * * tininess-before-rounding |
| 21 | hwaddr dma_dram_mask; | 18 | * * 2-input NaN propagation prefers SNaN over QNaN, and then |
| 22 | uint32_t nregs; | 19 | * operand A over operand B (see FPProcessNaNs() pseudocode) |
| 23 | + uint32_t (*segment_to_reg)(const struct AspeedSMCState *s, | 20 | + * * 3-input NaN propagation prefers SNaN over QNaN, and then |
| 24 | + const AspeedSegments *seg); | 21 | + * operand C over A over B (see FPProcessNaNs3() pseudocode, |
| 25 | + void (*reg_to_segment)(const struct AspeedSMCState *s, uint32_t reg, | 22 | + * but note that for QEMU muladd is a * b + c, whereas for |
| 26 | + AspeedSegments *seg); | 23 | + * the pseudocode function the arguments are in the order c, a, b. |
| 27 | } AspeedSMCController; | 24 | * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, |
| 28 | 25 | * and the input NaN if it is signalling | |
| 29 | typedef struct AspeedSMCFlash { | 26 | */ |
| 30 | diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c | 27 | @@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s) |
| 28 | { | ||
| 29 | set_float_detect_tininess(float_tininess_before_rounding, s); | ||
| 30 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); | ||
| 31 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); | ||
| 32 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); | ||
| 33 | } | ||
| 34 | |||
| 35 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 31 | index XXXXXXX..XXXXXXX 100644 | 36 | index XXXXXXX..XXXXXXX 100644 |
| 32 | --- a/hw/ssi/aspeed_smc.c | 37 | --- a/fpu/softfloat-specialize.c.inc |
| 33 | +++ b/hw/ssi/aspeed_smc.c | 38 | +++ b/fpu/softfloat-specialize.c.inc |
| 34 | @@ -XXX,XX +XXX,XX @@ static const AspeedSegments aspeed_segments_ast2500_spi2[] = { | 39 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 35 | { 0x38000000, 32 * 1024 * 1024 }, /* start address is readonly */ | ||
| 36 | { 0x3A000000, 96 * 1024 * 1024 }, /* end address is readonly */ | ||
| 37 | }; | ||
| 38 | +static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s, | ||
| 39 | + const AspeedSegments *seg); | ||
| 40 | +static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, uint32_t reg, | ||
| 41 | + AspeedSegments *seg); | ||
| 42 | |||
| 43 | static const AspeedSMCController controllers[] = { | ||
| 44 | { | ||
| 45 | @@ -XXX,XX +XXX,XX @@ static const AspeedSMCController controllers[] = { | ||
| 46 | .flash_window_size = 0x6000000, | ||
| 47 | .has_dma = false, | ||
| 48 | .nregs = ASPEED_SMC_R_SMC_MAX, | ||
| 49 | + .segment_to_reg = aspeed_smc_segment_to_reg, | ||
| 50 | + .reg_to_segment = aspeed_smc_reg_to_segment, | ||
| 51 | }, { | ||
| 52 | .name = "aspeed.fmc-ast2400", | ||
| 53 | .r_conf = R_CONF, | ||
| 54 | @@ -XXX,XX +XXX,XX @@ static const AspeedSMCController controllers[] = { | ||
| 55 | .dma_flash_mask = 0x0FFFFFFC, | ||
| 56 | .dma_dram_mask = 0x1FFFFFFC, | ||
| 57 | .nregs = ASPEED_SMC_R_MAX, | ||
| 58 | + .segment_to_reg = aspeed_smc_segment_to_reg, | ||
| 59 | + .reg_to_segment = aspeed_smc_reg_to_segment, | ||
| 60 | }, { | ||
| 61 | .name = "aspeed.spi1-ast2400", | ||
| 62 | .r_conf = R_SPI_CONF, | ||
| 63 | @@ -XXX,XX +XXX,XX @@ static const AspeedSMCController controllers[] = { | ||
| 64 | .flash_window_size = 0x10000000, | ||
| 65 | .has_dma = false, | ||
| 66 | .nregs = ASPEED_SMC_R_SPI_MAX, | ||
| 67 | + .segment_to_reg = aspeed_smc_segment_to_reg, | ||
| 68 | + .reg_to_segment = aspeed_smc_reg_to_segment, | ||
| 69 | }, { | ||
| 70 | .name = "aspeed.fmc-ast2500", | ||
| 71 | .r_conf = R_CONF, | ||
| 72 | @@ -XXX,XX +XXX,XX @@ static const AspeedSMCController controllers[] = { | ||
| 73 | .dma_flash_mask = 0x0FFFFFFC, | ||
| 74 | .dma_dram_mask = 0x3FFFFFFC, | ||
| 75 | .nregs = ASPEED_SMC_R_MAX, | ||
| 76 | + .segment_to_reg = aspeed_smc_segment_to_reg, | ||
| 77 | + .reg_to_segment = aspeed_smc_reg_to_segment, | ||
| 78 | }, { | ||
| 79 | .name = "aspeed.spi1-ast2500", | ||
| 80 | .r_conf = R_CONF, | ||
| 81 | @@ -XXX,XX +XXX,XX @@ static const AspeedSMCController controllers[] = { | ||
| 82 | .flash_window_size = 0x8000000, | ||
| 83 | .has_dma = false, | ||
| 84 | .nregs = ASPEED_SMC_R_MAX, | ||
| 85 | + .segment_to_reg = aspeed_smc_segment_to_reg, | ||
| 86 | + .reg_to_segment = aspeed_smc_reg_to_segment, | ||
| 87 | }, { | ||
| 88 | .name = "aspeed.spi2-ast2500", | ||
| 89 | .r_conf = R_CONF, | ||
| 90 | @@ -XXX,XX +XXX,XX @@ static const AspeedSMCController controllers[] = { | ||
| 91 | .flash_window_size = 0x8000000, | ||
| 92 | .has_dma = false, | ||
| 93 | .nregs = ASPEED_SMC_R_MAX, | ||
| 94 | + .segment_to_reg = aspeed_smc_segment_to_reg, | ||
| 95 | + .reg_to_segment = aspeed_smc_reg_to_segment, | ||
| 96 | }, | ||
| 97 | }; | ||
| 98 | |||
| 99 | /* | ||
| 100 | - * The Segment Register uses a 8MB unit to encode the start address | ||
| 101 | - * and the end address of the mapping window of a flash SPI slave : | ||
| 102 | - * | ||
| 103 | - * | byte 1 | byte 2 | byte 3 | byte 4 | | ||
| 104 | - * +--------+--------+--------+--------+ | ||
| 105 | - * | end | start | 0 | 0 | | ||
| 106 | - * | ||
| 107 | + * The Segment Registers of the AST2400 and AST2500 have a 8MB | ||
| 108 | + * unit. The address range of a flash SPI slave is encoded with | ||
| 109 | + * absolute addresses which should be part of the overall controller | ||
| 110 | + * window. | ||
| 111 | */ | ||
| 112 | -static inline uint32_t aspeed_smc_segment_to_reg(const AspeedSegments *seg) | ||
| 113 | +static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s, | ||
| 114 | + const AspeedSegments *seg) | ||
| 115 | { | ||
| 116 | uint32_t reg = 0; | ||
| 117 | reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT; | ||
| 118 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t aspeed_smc_segment_to_reg(const AspeedSegments *seg) | ||
| 119 | return reg; | ||
| 120 | } | ||
| 121 | |||
| 122 | -static inline void aspeed_smc_reg_to_segment(uint32_t reg, AspeedSegments *seg) | ||
| 123 | +static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, | ||
| 124 | + uint32_t reg, AspeedSegments *seg) | ||
| 125 | { | ||
| 126 | seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23; | ||
| 127 | seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr; | ||
| 128 | @@ -XXX,XX +XXX,XX @@ static bool aspeed_smc_flash_overlap(const AspeedSMCState *s, | ||
| 129 | continue; | ||
| 130 | } | ||
| 131 | |||
| 132 | - aspeed_smc_reg_to_segment(s->regs[R_SEG_ADDR0 + i], &seg); | ||
| 133 | + s->ctrl->reg_to_segment(s, s->regs[R_SEG_ADDR0 + i], &seg); | ||
| 134 | |||
| 135 | if (new->addr + new->size > seg.addr && | ||
| 136 | new->addr < seg.addr + seg.size) { | ||
| 137 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, | ||
| 138 | AspeedSMCFlash *fl = &s->flashes[cs]; | ||
| 139 | AspeedSegments seg; | ||
| 140 | |||
| 141 | - aspeed_smc_reg_to_segment(new, &seg); | ||
| 142 | + s->ctrl->reg_to_segment(s, new, &seg); | ||
| 143 | |||
| 144 | /* The start address of CS0 is read-only */ | ||
| 145 | if (cs == 0 && seg.addr != s->ctrl->flash_window_base) { | ||
| 146 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, | ||
| 147 | "%s: Tried to change CS0 start address to 0x%" | ||
| 148 | HWADDR_PRIx "\n", s->ctrl->name, seg.addr); | ||
| 149 | seg.addr = s->ctrl->flash_window_base; | ||
| 150 | - new = aspeed_smc_segment_to_reg(&seg); | ||
| 151 | + new = s->ctrl->segment_to_reg(s, &seg); | ||
| 152 | } | 40 | } |
| 153 | 41 | ||
| 154 | /* | 42 | if (rule == float_3nan_prop_none) { |
| 155 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, | 43 | -#if defined(TARGET_ARM) |
| 156 | HWADDR_PRIx "\n", s->ctrl->name, cs, seg.addr + seg.size); | 44 | - /* |
| 157 | seg.size = s->ctrl->segments[cs].addr + s->ctrl->segments[cs].size - | 45 | - * This looks different from the ARM ARM pseudocode, because the ARM ARM |
| 158 | seg.addr; | 46 | - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b |
| 159 | - new = aspeed_smc_segment_to_reg(&seg); | 47 | - */ |
| 160 | + new = s->ctrl->segment_to_reg(s, &seg); | 48 | - rule = float_3nan_prop_s_cab; |
| 161 | } | 49 | -#elif defined(TARGET_MIPS) |
| 162 | 50 | +#if defined(TARGET_MIPS) | |
| 163 | /* Keep the segment in the overall flash window */ | 51 | if (snan_bit_is_one(status)) { |
| 164 | @@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl, | 52 | rule = float_3nan_prop_s_abc; |
| 165 | const AspeedSMCState *s = fl->controller; | 53 | } else { |
| 166 | AspeedSegments seg; | ||
| 167 | |||
| 168 | - aspeed_smc_reg_to_segment(s->regs[R_SEG_ADDR0 + fl->id], &seg); | ||
| 169 | + s->ctrl->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->id], &seg); | ||
| 170 | if ((addr % seg.size) != addr) { | ||
| 171 | qemu_log_mask(LOG_GUEST_ERROR, | ||
| 172 | "%s: invalid address 0x%08x for CS%d segment : " | ||
| 173 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_reset(DeviceState *d) | ||
| 174 | /* setup default segment register values for all */ | ||
| 175 | for (i = 0; i < s->ctrl->max_slaves; ++i) { | ||
| 176 | s->regs[R_SEG_ADDR0 + i] = | ||
| 177 | - aspeed_smc_segment_to_reg(&s->ctrl->segments[i]); | ||
| 178 | + s->ctrl->segment_to_reg(s, &s->ctrl->segments[i]); | ||
| 179 | } | ||
| 180 | |||
| 181 | /* HW strapping flash type for FMC controllers */ | ||
| 182 | -- | 54 | -- |
| 183 | 2.20.1 | 55 | 2.34.1 |
| 184 | |||
| 185 | diff view generated by jsdifflib |
| 1 | Factor out the implementation of SYS_READ via the | 1 | Set the Float3NaNPropRule explicitly for loongarch, and remove the |
|---|---|---|---|
| 2 | new function tables. | 2 | ifdef from pickNaNMulAdd(). |
| 3 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 6 | Message-id: 20190916141544.17540-10-peter.maydell@linaro.org | 6 | Message-id: 20241202131347.498124-19-peter.maydell@linaro.org |
| 7 | --- | 7 | --- |
| 8 | target/arm/arm-semi.c | 55 +++++++++++++++++++++++++++---------------- | 8 | target/loongarch/tcg/fpu_helper.c | 1 + |
| 9 | 1 file changed, 35 insertions(+), 20 deletions(-) | 9 | fpu/softfloat-specialize.c.inc | 2 -- |
| 10 | 2 files changed, 1 insertion(+), 2 deletions(-) | ||
| 10 | 11 | ||
| 11 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 12 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c |
| 12 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 13 | --- a/target/arm/arm-semi.c | 14 | --- a/target/loongarch/tcg/fpu_helper.c |
| 14 | +++ b/target/arm/arm-semi.c | 15 | +++ b/target/loongarch/tcg/fpu_helper.c |
| 15 | @@ -XXX,XX +XXX,XX @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, | 16 | @@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env) |
| 16 | typedef uint32_t sys_closefn(ARMCPU *cpu, GuestFD *gf); | 17 | * case sets InvalidOp and returns the input value 'c' |
| 17 | typedef uint32_t sys_writefn(ARMCPU *cpu, GuestFD *gf, | 18 | */ |
| 18 | target_ulong buf, uint32_t len); | 19 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); |
| 19 | +typedef uint32_t sys_readfn(ARMCPU *cpu, GuestFD *gf, | 20 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); |
| 20 | + target_ulong buf, uint32_t len); | ||
| 21 | |||
| 22 | static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) | ||
| 23 | { | ||
| 24 | @@ -XXX,XX +XXX,XX @@ static uint32_t host_writefn(ARMCPU *cpu, GuestFD *gf, | ||
| 25 | return len - ret; | ||
| 26 | } | 21 | } |
| 27 | 22 | ||
| 28 | +static uint32_t host_readfn(ARMCPU *cpu, GuestFD *gf, | 23 | int ieee_ex_to_loongarch(int xcpt) |
| 29 | + target_ulong buf, uint32_t len) | 24 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 30 | +{ | 25 | index XXXXXXX..XXXXXXX 100644 |
| 31 | + uint32_t ret; | 26 | --- a/fpu/softfloat-specialize.c.inc |
| 32 | + CPUARMState *env = &cpu->env; | 27 | +++ b/fpu/softfloat-specialize.c.inc |
| 33 | + char *s = lock_user(VERIFY_WRITE, buf, len, 0); | 28 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 34 | + if (!s) { | 29 | } else { |
| 35 | + /* return bytes not read */ | 30 | rule = float_3nan_prop_s_cab; |
| 36 | + return len; | ||
| 37 | + } | ||
| 38 | + do { | ||
| 39 | + ret = set_swi_errno(env, read(gf->hostfd, s, len)); | ||
| 40 | + } while (ret == -1 && errno == EINTR); | ||
| 41 | + unlock_user(s, buf, len); | ||
| 42 | + if (ret == (uint32_t)-1) { | ||
| 43 | + ret = 0; | ||
| 44 | + } | ||
| 45 | + /* Return bytes not read */ | ||
| 46 | + return len - ret; | ||
| 47 | +} | ||
| 48 | + | ||
| 49 | static uint32_t gdb_closefn(ARMCPU *cpu, GuestFD *gf) | ||
| 50 | { | ||
| 51 | return arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); | ||
| 52 | @@ -XXX,XX +XXX,XX @@ static uint32_t gdb_writefn(ARMCPU *cpu, GuestFD *gf, | ||
| 53 | gf->hostfd, buf, len); | ||
| 54 | } | ||
| 55 | |||
| 56 | +static uint32_t gdb_readfn(ARMCPU *cpu, GuestFD *gf, | ||
| 57 | + target_ulong buf, uint32_t len) | ||
| 58 | +{ | ||
| 59 | + arm_semi_syscall_len = len; | ||
| 60 | + return arm_gdb_syscall(cpu, arm_semi_cb, "read,%x,%x,%x", | ||
| 61 | + gf->hostfd, buf, len); | ||
| 62 | +} | ||
| 63 | + | ||
| 64 | typedef struct GuestFDFunctions { | ||
| 65 | sys_closefn *closefn; | ||
| 66 | sys_writefn *writefn; | ||
| 67 | + sys_readfn *readfn; | ||
| 68 | } GuestFDFunctions; | ||
| 69 | |||
| 70 | static const GuestFDFunctions guestfd_fns[] = { | ||
| 71 | [GuestFDHost] = { | ||
| 72 | .closefn = host_closefn, | ||
| 73 | .writefn = host_writefn, | ||
| 74 | + .readfn = host_readfn, | ||
| 75 | }, | ||
| 76 | [GuestFDGDB] = { | ||
| 77 | .closefn = gdb_closefn, | ||
| 78 | .writefn = gdb_writefn, | ||
| 79 | + .readfn = gdb_readfn, | ||
| 80 | }, | ||
| 81 | }; | ||
| 82 | |||
| 83 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 84 | return set_swi_errno(env, -1); | ||
| 85 | } | 31 | } |
| 86 | 32 | -#elif defined(TARGET_LOONGARCH64) | |
| 87 | - if (use_gdb_syscalls()) { | 33 | - rule = float_3nan_prop_s_cab; |
| 88 | - arm_semi_syscall_len = len; | 34 | #elif defined(TARGET_PPC) |
| 89 | - return arm_gdb_syscall(cpu, arm_semi_cb, "read,%x,%x,%x", | 35 | /* |
| 90 | - gf->hostfd, arg1, len); | 36 | * If fRA is a NaN return it; otherwise if fRB is a NaN return it; |
| 91 | - } else { | ||
| 92 | - s = lock_user(VERIFY_WRITE, arg1, len, 0); | ||
| 93 | - if (!s) { | ||
| 94 | - /* return bytes not read */ | ||
| 95 | - return len; | ||
| 96 | - } | ||
| 97 | - do { | ||
| 98 | - ret = set_swi_errno(env, read(gf->hostfd, s, len)); | ||
| 99 | - } while (ret == -1 && errno == EINTR); | ||
| 100 | - unlock_user(s, arg1, len); | ||
| 101 | - if (ret == (uint32_t)-1) { | ||
| 102 | - ret = 0; | ||
| 103 | - } | ||
| 104 | - /* Return bytes not read */ | ||
| 105 | - return len - ret; | ||
| 106 | - } | ||
| 107 | + return guestfd_fns[gf->type].readfn(cpu, gf, arg1, len); | ||
| 108 | case TARGET_SYS_READC: | ||
| 109 | qemu_log_mask(LOG_UNIMP, "%s: SYS_READC not implemented", __func__); | ||
| 110 | return 0; | ||
| 111 | -- | 37 | -- |
| 112 | 2.20.1 | 38 | 2.34.1 |
| 113 | |||
| 114 | diff view generated by jsdifflib |
| 1 | From: Joel Stanley <joel@jms.id.au> | 1 | Set the Float3NaNPropRule explicitly for PPC, and remove the |
|---|---|---|---|
| 2 | ifdef from pickNaNMulAdd(). | ||
| 2 | 3 | ||
| 3 | The AST2600 has four watchdogs, and they each have a 0x40 of registers. | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-20-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/ppc/cpu_init.c | 8 ++++++++ | ||
| 9 | fpu/softfloat-specialize.c.inc | 6 ------ | ||
| 10 | 2 files changed, 8 insertions(+), 6 deletions(-) | ||
| 4 | 11 | ||
| 5 | When running as part of an ast2600 system we must check a different | 12 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c |
| 6 | offset for the system reset control register in the SCU. | ||
| 7 | |||
| 8 | Signed-off-by: Joel Stanley <joel@jms.id.au> | ||
| 9 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 10 | Message-id: 20190925143248.10000-12-clg@kaod.org | ||
| 11 | [clg: - reworked model integration into new object class ] | ||
| 12 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | --- | ||
| 15 | include/hw/arm/aspeed_soc.h | 2 +- | ||
| 16 | include/hw/watchdog/wdt_aspeed.h | 1 + | ||
| 17 | hw/watchdog/wdt_aspeed.c | 29 +++++++++++++++++++++++++++++ | ||
| 18 | 3 files changed, 31 insertions(+), 1 deletion(-) | ||
| 19 | |||
| 20 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 22 | --- a/include/hw/arm/aspeed_soc.h | 14 | --- a/target/ppc/cpu_init.c |
| 23 | +++ b/include/hw/arm/aspeed_soc.h | 15 | +++ b/target/ppc/cpu_init.c |
| 24 | @@ -XXX,XX +XXX,XX @@ | 16 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) |
| 25 | #include "hw/sd/aspeed_sdhci.h" | 17 | */ |
| 26 | 18 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); | |
| 27 | #define ASPEED_SPIS_NUM 2 | 19 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); |
| 28 | -#define ASPEED_WDTS_NUM 3 | 20 | + /* |
| 29 | +#define ASPEED_WDTS_NUM 4 | 21 | + * NaN propagation for fused multiply-add: |
| 30 | #define ASPEED_CPUS_NUM 2 | 22 | + * if fRA is a NaN return it; otherwise if fRB is a NaN return it; |
| 31 | #define ASPEED_MACS_NUM 2 | 23 | + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB |
| 32 | 24 | + * whereas QEMU labels the operands as (a * b) + c. | |
| 33 | diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h | 25 | + */ |
| 26 | + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status); | ||
| 27 | + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status); | ||
| 28 | /* | ||
| 29 | * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
| 30 | * to return an input NaN if we have one (ie c) rather than generating | ||
| 31 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 34 | index XXXXXXX..XXXXXXX 100644 | 32 | index XXXXXXX..XXXXXXX 100644 |
| 35 | --- a/include/hw/watchdog/wdt_aspeed.h | 33 | --- a/fpu/softfloat-specialize.c.inc |
| 36 | +++ b/include/hw/watchdog/wdt_aspeed.h | 34 | +++ b/fpu/softfloat-specialize.c.inc |
| 37 | @@ -XXX,XX +XXX,XX @@ | 35 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 38 | OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT) | 36 | } else { |
| 39 | #define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400" | 37 | rule = float_3nan_prop_s_cab; |
| 40 | #define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500" | 38 | } |
| 41 | +#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600" | 39 | -#elif defined(TARGET_PPC) |
| 42 | 40 | - /* | |
| 43 | #define ASPEED_WDT_REGS_MAX (0x20 / 4) | 41 | - * If fRA is a NaN return it; otherwise if fRB is a NaN return it; |
| 44 | 42 | - * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | |
| 45 | diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c | 43 | - */ |
| 46 | index XXXXXXX..XXXXXXX 100644 | 44 | - rule = float_3nan_prop_acb; |
| 47 | --- a/hw/watchdog/wdt_aspeed.c | 45 | #elif defined(TARGET_S390X) |
| 48 | +++ b/hw/watchdog/wdt_aspeed.c | 46 | rule = float_3nan_prop_s_abc; |
| 49 | @@ -XXX,XX +XXX,XX @@ | 47 | #elif defined(TARGET_SPARC) |
| 50 | #define WDT_DRIVE_TYPE_MASK (0xFF << 24) | ||
| 51 | #define WDT_PUSH_PULL_MAGIC (0xA8 << 24) | ||
| 52 | #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) | ||
| 53 | +#define WDT_RESET_MASK1 (0x1c / 4) | ||
| 54 | |||
| 55 | #define WDT_TIMEOUT_STATUS (0x10 / 4) | ||
| 56 | #define WDT_TIMEOUT_CLEAR (0x14 / 4) | ||
| 57 | |||
| 58 | #define WDT_RESTART_MAGIC 0x4755 | ||
| 59 | |||
| 60 | +#define AST2600_SCU_RESET_CONTROL1 (0x40 / 4) | ||
| 61 | #define SCU_RESET_CONTROL1 (0x04 / 4) | ||
| 62 | #define SCU_RESET_SDRAM BIT(0) | ||
| 63 | |||
| 64 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) | ||
| 65 | return s->regs[WDT_CTRL]; | ||
| 66 | case WDT_RESET_WIDTH: | ||
| 67 | return s->regs[WDT_RESET_WIDTH]; | ||
| 68 | + case WDT_RESET_MASK1: | ||
| 69 | + return s->regs[WDT_RESET_MASK1]; | ||
| 70 | case WDT_TIMEOUT_STATUS: | ||
| 71 | case WDT_TIMEOUT_CLEAR: | ||
| 72 | qemu_log_mask(LOG_UNIMP, | ||
| 73 | @@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, | ||
| 74 | s->regs[WDT_RESET_WIDTH] |= data & awc->ext_pulse_width_mask; | ||
| 75 | break; | ||
| 76 | |||
| 77 | + case WDT_RESET_MASK1: | ||
| 78 | + /* TODO: implement */ | ||
| 79 | + s->regs[WDT_RESET_MASK1] = data; | ||
| 80 | + break; | ||
| 81 | + | ||
| 82 | case WDT_TIMEOUT_STATUS: | ||
| 83 | case WDT_TIMEOUT_CLEAR: | ||
| 84 | qemu_log_mask(LOG_UNIMP, | ||
| 85 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_2500_wdt_info = { | ||
| 86 | .class_init = aspeed_2500_wdt_class_init, | ||
| 87 | }; | ||
| 88 | |||
| 89 | +static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data) | ||
| 90 | +{ | ||
| 91 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 92 | + AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); | ||
| 93 | + | ||
| 94 | + dc->desc = "ASPEED 2600 Watchdog Controller"; | ||
| 95 | + awc->offset = 0x40; | ||
| 96 | + awc->ext_pulse_width_mask = 0xfffff; /* TODO */ | ||
| 97 | + awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1; | ||
| 98 | + awc->reset_pulse = aspeed_2500_wdt_reset_pulse; | ||
| 99 | +} | ||
| 100 | + | ||
| 101 | +static const TypeInfo aspeed_2600_wdt_info = { | ||
| 102 | + .name = TYPE_ASPEED_2600_WDT, | ||
| 103 | + .parent = TYPE_ASPEED_WDT, | ||
| 104 | + .instance_size = sizeof(AspeedWDTState), | ||
| 105 | + .class_init = aspeed_2600_wdt_class_init, | ||
| 106 | +}; | ||
| 107 | + | ||
| 108 | static void wdt_aspeed_register_types(void) | ||
| 109 | { | ||
| 110 | watchdog_add_model(&model); | ||
| 111 | type_register_static(&aspeed_wdt_info); | ||
| 112 | type_register_static(&aspeed_2400_wdt_info); | ||
| 113 | type_register_static(&aspeed_2500_wdt_info); | ||
| 114 | + type_register_static(&aspeed_2600_wdt_info); | ||
| 115 | } | ||
| 116 | |||
| 117 | type_init(wdt_aspeed_register_types) | ||
| 118 | -- | 48 | -- |
| 119 | 2.20.1 | 49 | 2.34.1 |
| 120 | |||
| 121 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the Float3NaNPropRule explicitly for s390x, and remove the | ||
| 2 | ifdef from pickNaNMulAdd(). | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-21-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/s390x/cpu.c | 1 + | ||
| 9 | fpu/softfloat-specialize.c.inc | 2 -- | ||
| 10 | 2 files changed, 1 insertion(+), 2 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/s390x/cpu.c | ||
| 15 | +++ b/target/s390x/cpu.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) | ||
| 17 | set_float_detect_tininess(float_tininess_before_rounding, | ||
| 18 | &env->fpu_status); | ||
| 19 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); | ||
| 20 | + set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status); | ||
| 21 | set_float_infzeronan_rule(float_infzeronan_dnan_always, | ||
| 22 | &env->fpu_status); | ||
| 23 | /* fall through */ | ||
| 24 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 25 | index XXXXXXX..XXXXXXX 100644 | ||
| 26 | --- a/fpu/softfloat-specialize.c.inc | ||
| 27 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 28 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 29 | } else { | ||
| 30 | rule = float_3nan_prop_s_cab; | ||
| 31 | } | ||
| 32 | -#elif defined(TARGET_S390X) | ||
| 33 | - rule = float_3nan_prop_s_abc; | ||
| 34 | #elif defined(TARGET_SPARC) | ||
| 35 | rule = float_3nan_prop_s_cba; | ||
| 36 | #elif defined(TARGET_XTENSA) | ||
| 37 | -- | ||
| 38 | 2.34.1 | diff view generated by jsdifflib |
| 1 | From: Joel Stanley <joel@jms.id.au> | 1 | Set the Float3NaNPropRule explicitly for SPARC, and remove the |
|---|---|---|---|
| 2 | ifdef from pickNaNMulAdd(). | ||
| 2 | 3 | ||
| 3 | Signed-off-by: Joel Stanley <joel@jms.id.au> | ||
| 4 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 5 | Message-id: 20190925143248.10000-24-clg@kaod.org | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-22-peter.maydell@linaro.org | ||
| 7 | --- | 7 | --- |
| 8 | include/hw/arm/aspeed_soc.h | 1 + | 8 | target/sparc/cpu.c | 2 ++ |
| 9 | hw/arm/aspeed_ast2600.c | 5 +++++ | 9 | fpu/softfloat-specialize.c.inc | 2 -- |
| 10 | hw/arm/aspeed_soc.c | 6 ++++++ | 10 | 2 files changed, 2 insertions(+), 2 deletions(-) |
| 11 | 3 files changed, 12 insertions(+) | ||
| 12 | 11 | ||
| 13 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | 12 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c |
| 14 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/include/hw/arm/aspeed_soc.h | 14 | --- a/target/sparc/cpu.c |
| 16 | +++ b/include/hw/arm/aspeed_soc.h | 15 | +++ b/target/sparc/cpu.c |
| 17 | @@ -XXX,XX +XXX,XX @@ enum { | 16 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) |
| 18 | ASPEED_SDMC, | 17 | * the CPU state struct so it won't get zeroed on reset. |
| 19 | ASPEED_SCU, | 18 | */ |
| 20 | ASPEED_ADC, | 19 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); |
| 21 | + ASPEED_VIDEO, | 20 | + /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */ |
| 22 | ASPEED_SRAM, | 21 | + set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); |
| 23 | ASPEED_SDHCI, | 22 | /* For inf * 0 + NaN, return the input NaN */ |
| 24 | ASPEED_GPIO, | 23 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); |
| 25 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c | 24 | |
| 25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
| 27 | --- a/hw/arm/aspeed_ast2600.c | 27 | --- a/fpu/softfloat-specialize.c.inc |
| 28 | +++ b/hw/arm/aspeed_ast2600.c | 28 | +++ b/fpu/softfloat-specialize.c.inc |
| 29 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { | 29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 30 | [ASPEED_SCU] = 0x1E6E2000, | 30 | } else { |
| 31 | [ASPEED_XDMA] = 0x1E6E7000, | 31 | rule = float_3nan_prop_s_cab; |
| 32 | [ASPEED_ADC] = 0x1E6E9000, | 32 | } |
| 33 | + [ASPEED_VIDEO] = 0x1E700000, | 33 | -#elif defined(TARGET_SPARC) |
| 34 | [ASPEED_SDHCI] = 0x1E740000, | 34 | - rule = float_3nan_prop_s_cba; |
| 35 | [ASPEED_GPIO] = 0x1E780000, | 35 | #elif defined(TARGET_XTENSA) |
| 36 | [ASPEED_GPIO_1_8V] = 0x1E780800, | 36 | if (status->use_first_nan) { |
| 37 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | 37 | rule = float_3nan_prop_abc; |
| 38 | create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], | ||
| 39 | ASPEED_SOC_IOMEM_SIZE); | ||
| 40 | |||
| 41 | + /* Video engine stub */ | ||
| 42 | + create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO], | ||
| 43 | + 0x1000); | ||
| 44 | + | ||
| 45 | if (s->num_cpus > sc->num_cpus) { | ||
| 46 | warn_report("%s: invalid number of CPUs %d, using default %d", | ||
| 47 | sc->name, s->num_cpus, sc->num_cpus); | ||
| 48 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
| 49 | index XXXXXXX..XXXXXXX 100644 | ||
| 50 | --- a/hw/arm/aspeed_soc.c | ||
| 51 | +++ b/hw/arm/aspeed_soc.c | ||
| 52 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2400_memmap[] = { | ||
| 53 | [ASPEED_SDMC] = 0x1E6E0000, | ||
| 54 | [ASPEED_SCU] = 0x1E6E2000, | ||
| 55 | [ASPEED_XDMA] = 0x1E6E7000, | ||
| 56 | + [ASPEED_VIDEO] = 0x1E700000, | ||
| 57 | [ASPEED_ADC] = 0x1E6E9000, | ||
| 58 | [ASPEED_SRAM] = 0x1E720000, | ||
| 59 | [ASPEED_SDHCI] = 0x1E740000, | ||
| 60 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2500_memmap[] = { | ||
| 61 | [ASPEED_SCU] = 0x1E6E2000, | ||
| 62 | [ASPEED_XDMA] = 0x1E6E7000, | ||
| 63 | [ASPEED_ADC] = 0x1E6E9000, | ||
| 64 | + [ASPEED_VIDEO] = 0x1E700000, | ||
| 65 | [ASPEED_SRAM] = 0x1E720000, | ||
| 66 | [ASPEED_SDHCI] = 0x1E740000, | ||
| 67 | [ASPEED_GPIO] = 0x1E780000, | ||
| 68 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
| 69 | create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], | ||
| 70 | ASPEED_SOC_IOMEM_SIZE); | ||
| 71 | |||
| 72 | + /* Video engine stub */ | ||
| 73 | + create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO], | ||
| 74 | + 0x1000); | ||
| 75 | + | ||
| 76 | if (s->num_cpus > sc->num_cpus) { | ||
| 77 | warn_report("%s: invalid number of CPUs %d, using default %d", | ||
| 78 | sc->name, s->num_cpus, sc->num_cpus); | ||
| 79 | -- | 38 | -- |
| 80 | 2.20.1 | 39 | 2.34.1 |
| 81 | |||
| 82 | diff view generated by jsdifflib |
| 1 | Switch the cmsdk-apb-watchdog code away from bottom-half based | 1 | Set the Float3NaNPropRule explicitly for Arm, and remove the |
|---|---|---|---|
| 2 | ptimers to the new transaction-based ptimer API. This just requires | 2 | ifdef from pickNaNMulAdd(). |
| 3 | adding begin/commit calls around the various places that modify the | ||
| 4 | ptimer state, and using the new ptimer_init() function to create the | ||
| 5 | timer. | ||
| 6 | 3 | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 9 | Message-id: 20191008171740.9679-21-peter.maydell@linaro.org | 6 | Message-id: 20241202131347.498124-23-peter.maydell@linaro.org |
| 10 | --- | 7 | --- |
| 11 | hw/watchdog/cmsdk-apb-watchdog.c | 13 +++++++++---- | 8 | target/mips/fpu_helper.h | 4 ++++ |
| 12 | 1 file changed, 9 insertions(+), 4 deletions(-) | 9 | target/mips/msa.c | 3 +++ |
| 10 | fpu/softfloat-specialize.c.inc | 8 +------- | ||
| 11 | 3 files changed, 8 insertions(+), 7 deletions(-) | ||
| 13 | 12 | ||
| 14 | diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c | 13 | diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h |
| 15 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/hw/watchdog/cmsdk-apb-watchdog.c | 15 | --- a/target/mips/fpu_helper.h |
| 17 | +++ b/hw/watchdog/cmsdk-apb-watchdog.c | 16 | +++ b/target/mips/fpu_helper.h |
| 18 | @@ -XXX,XX +XXX,XX @@ | 17 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) |
| 19 | #include "qemu/log.h" | 18 | { |
| 20 | #include "trace.h" | 19 | bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); |
| 21 | #include "qapi/error.h" | 20 | FloatInfZeroNaNRule izn_rule; |
| 22 | -#include "qemu/main-loop.h" | 21 | + Float3NaNPropRule nan3_rule; |
| 23 | #include "qemu/module.h" | 22 | |
| 24 | #include "sysemu/watchdog.h" | 23 | /* |
| 25 | #include "hw/sysbus.h" | 24 | * With nan2008, SNaNs are silenced in the usual way. |
| 26 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset, | 25 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) |
| 27 | * Reset the load value and the current count, and make sure | 26 | */ |
| 28 | * we're counting. | 27 | izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; |
| 29 | */ | 28 | set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); |
| 30 | + ptimer_transaction_begin(s->timer); | 29 | + nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; |
| 31 | ptimer_set_limit(s->timer, value, 1); | 30 | + set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); |
| 32 | ptimer_run(s->timer, 0); | 31 | + |
| 33 | + ptimer_transaction_commit(s->timer); | ||
| 34 | break; | ||
| 35 | case A_WDOGCONTROL: | ||
| 36 | if (s->is_luminary && 0 != (R_WDOGCONTROL_INTEN_MASK & s->control)) { | ||
| 37 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset, | ||
| 38 | break; | ||
| 39 | case A_WDOGINTCLR: | ||
| 40 | s->intstatus = 0; | ||
| 41 | + ptimer_transaction_begin(s->timer); | ||
| 42 | ptimer_set_count(s->timer, ptimer_get_limit(s->timer)); | ||
| 43 | + ptimer_transaction_commit(s->timer); | ||
| 44 | cmsdk_apb_watchdog_update(s); | ||
| 45 | break; | ||
| 46 | case A_WDOGLOCK: | ||
| 47 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_reset(DeviceState *dev) | ||
| 48 | s->itop = 0; | ||
| 49 | s->resetstatus = 0; | ||
| 50 | /* Set the limit and the count */ | ||
| 51 | + ptimer_transaction_begin(s->timer); | ||
| 52 | ptimer_set_limit(s->timer, 0xffffffff, 1); | ||
| 53 | ptimer_run(s->timer, 0); | ||
| 54 | + ptimer_transaction_commit(s->timer); | ||
| 55 | } | 32 | } |
| 56 | 33 | ||
| 57 | static void cmsdk_apb_watchdog_init(Object *obj) | 34 | static inline void restore_fp_status(CPUMIPSState *env) |
| 58 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_init(Object *obj) | 35 | diff --git a/target/mips/msa.c b/target/mips/msa.c |
| 59 | static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) | 36 | index XXXXXXX..XXXXXXX 100644 |
| 60 | { | 37 | --- a/target/mips/msa.c |
| 61 | CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev); | 38 | +++ b/target/mips/msa.c |
| 62 | - QEMUBH *bh; | 39 | @@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env) |
| 63 | 40 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, | |
| 64 | if (s->wdogclk_frq == 0) { | 41 | &env->active_tc.msa_fp_status); |
| 65 | error_setg(errp, | 42 | |
| 66 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) | 43 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, |
| 67 | return; | 44 | + &env->active_tc.msa_fp_status); |
| 45 | + | ||
| 46 | /* clear float_status exception flags */ | ||
| 47 | set_float_exception_flags(0, &env->active_tc.msa_fp_status); | ||
| 48 | |||
| 49 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 50 | index XXXXXXX..XXXXXXX 100644 | ||
| 51 | --- a/fpu/softfloat-specialize.c.inc | ||
| 52 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 53 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 68 | } | 54 | } |
| 69 | 55 | ||
| 70 | - bh = qemu_bh_new(cmsdk_apb_watchdog_tick, s); | 56 | if (rule == float_3nan_prop_none) { |
| 71 | - s->timer = ptimer_init_with_bh(bh, | 57 | -#if defined(TARGET_MIPS) |
| 72 | + s->timer = ptimer_init(cmsdk_apb_watchdog_tick, s, | 58 | - if (snan_bit_is_one(status)) { |
| 73 | PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | | 59 | - rule = float_3nan_prop_s_abc; |
| 74 | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | | 60 | - } else { |
| 75 | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | | 61 | - rule = float_3nan_prop_s_cab; |
| 76 | PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | 62 | - } |
| 77 | 63 | -#elif defined(TARGET_XTENSA) | |
| 78 | + ptimer_transaction_begin(s->timer); | 64 | +#if defined(TARGET_XTENSA) |
| 79 | ptimer_set_freq(s->timer, s->wdogclk_frq); | 65 | if (status->use_first_nan) { |
| 80 | + ptimer_transaction_commit(s->timer); | 66 | rule = float_3nan_prop_abc; |
| 81 | } | 67 | } else { |
| 82 | |||
| 83 | static const VMStateDescription cmsdk_apb_watchdog_vmstate = { | ||
| 84 | -- | 68 | -- |
| 85 | 2.20.1 | 69 | 2.34.1 |
| 86 | |||
| 87 | diff view generated by jsdifflib |
| 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | Set the Float3NaNPropRule explicitly for xtensa, and remove the |
|---|---|---|---|
| 2 | ifdef from pickNaNMulAdd(). | ||
| 2 | 3 | ||
| 3 | Various address spaces from the BCM2835 are reported as | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 4 | 'anonymous' in memory tree: | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 6 | Message-id: 20241202131347.498124-24-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/xtensa/fpu_helper.c | 2 ++ | ||
| 9 | fpu/softfloat-specialize.c.inc | 8 -------- | ||
| 10 | 2 files changed, 2 insertions(+), 8 deletions(-) | ||
| 5 | 11 | ||
| 6 | (qemu) info mtree | 12 | diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c |
| 7 | |||
| 8 | address-space: anonymous | ||
| 9 | 0000000000000000-000000000000008f (prio 0, i/o): bcm2835-mbox | ||
| 10 | 0000000000000010-000000000000001f (prio 0, i/o): bcm2835-fb | ||
| 11 | 0000000000000080-000000000000008f (prio 0, i/o): bcm2835-property | ||
| 12 | |||
| 13 | address-space: anonymous | ||
| 14 | 0000000000000000-00000000ffffffff (prio 0, i/o): bcm2835-gpu | ||
| 15 | 0000000000000000-000000003fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
| 16 | 0000000040000000-000000007fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
| 17 | 000000007e000000-000000007effffff (prio 1, i/o): alias bcm2835-peripherals @bcm2835-peripherals 0000000000000000-0000000000ffffff | ||
| 18 | 0000000080000000-00000000bfffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
| 19 | 00000000c0000000-00000000ffffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
| 20 | |||
| 21 | [...] | ||
| 22 | |||
| 23 | Since the address_space_init() function takes a 'name' argument, | ||
| 24 | set it to correctly describe each address space: | ||
| 25 | |||
| 26 | (qemu) info mtree | ||
| 27 | |||
| 28 | address-space: bcm2835-mbox-memory | ||
| 29 | 0000000000000000-000000000000008f (prio 0, i/o): bcm2835-mbox | ||
| 30 | 0000000000000010-000000000000001f (prio 0, i/o): bcm2835-fb | ||
| 31 | 0000000000000080-000000000000008f (prio 0, i/o): bcm2835-property | ||
| 32 | |||
| 33 | address-space: bcm2835-fb-memory | ||
| 34 | 0000000000000000-00000000ffffffff (prio 0, i/o): bcm2835-gpu | ||
| 35 | 0000000000000000-000000003fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
| 36 | 0000000040000000-000000007fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
| 37 | 000000007e000000-000000007effffff (prio 1, i/o): alias bcm2835-peripherals @bcm2835-peripherals 0000000000000000-0000000000ffffff | ||
| 38 | 0000000080000000-00000000bfffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
| 39 | 00000000c0000000-00000000ffffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
| 40 | |||
| 41 | address-space: bcm2835-property-memory | ||
| 42 | 0000000000000000-00000000ffffffff (prio 0, i/o): bcm2835-gpu | ||
| 43 | 0000000000000000-000000003fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
| 44 | 0000000040000000-000000007fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
| 45 | 000000007e000000-000000007effffff (prio 1, i/o): alias bcm2835-peripherals @bcm2835-peripherals 0000000000000000-0000000000ffffff | ||
| 46 | 0000000080000000-00000000bfffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
| 47 | 00000000c0000000-00000000ffffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
| 48 | |||
| 49 | address-space: bcm2835-dma-memory | ||
| 50 | 0000000000000000-00000000ffffffff (prio 0, i/o): bcm2835-gpu | ||
| 51 | 0000000000000000-000000003fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
| 52 | 0000000040000000-000000007fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
| 53 | 000000007e000000-000000007effffff (prio 1, i/o): alias bcm2835-peripherals @bcm2835-peripherals 0000000000000000-0000000000ffffff | ||
| 54 | 0000000080000000-00000000bfffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
| 55 | 00000000c0000000-00000000ffffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
| 56 | |||
| 57 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 58 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 59 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 60 | Reviewed-by: Cleber Rosa <crosa@redhat.com> | ||
| 61 | Message-id: 20190926173428.10713-4-f4bug@amsat.org | ||
| 62 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 63 | --- | ||
| 64 | hw/display/bcm2835_fb.c | 2 +- | ||
| 65 | hw/dma/bcm2835_dma.c | 2 +- | ||
| 66 | hw/misc/bcm2835_mbox.c | 2 +- | ||
| 67 | hw/misc/bcm2835_property.c | 2 +- | ||
| 68 | 4 files changed, 4 insertions(+), 4 deletions(-) | ||
| 69 | |||
| 70 | diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c | ||
| 71 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 72 | --- a/hw/display/bcm2835_fb.c | 14 | --- a/target/xtensa/fpu_helper.c |
| 73 | +++ b/hw/display/bcm2835_fb.c | 15 | +++ b/target/xtensa/fpu_helper.c |
| 74 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_fb_realize(DeviceState *dev, Error **errp) | 16 | @@ -XXX,XX +XXX,XX @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) |
| 75 | s->initial_config.base = s->vcram_base + BCM2835_FB_OFFSET; | 17 | set_use_first_nan(use_first, &env->fp_status); |
| 76 | 18 | set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, | |
| 77 | s->dma_mr = MEMORY_REGION(obj); | 19 | &env->fp_status); |
| 78 | - address_space_init(&s->dma_as, s->dma_mr, NULL); | 20 | + set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba, |
| 79 | + address_space_init(&s->dma_as, s->dma_mr, TYPE_BCM2835_FB "-memory"); | 21 | + &env->fp_status); |
| 80 | 22 | } | |
| 81 | bcm2835_fb_reset(dev); | 23 | |
| 82 | 24 | void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v) | |
| 83 | diff --git a/hw/dma/bcm2835_dma.c b/hw/dma/bcm2835_dma.c | 25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 84 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
| 85 | --- a/hw/dma/bcm2835_dma.c | 27 | --- a/fpu/softfloat-specialize.c.inc |
| 86 | +++ b/hw/dma/bcm2835_dma.c | 28 | +++ b/fpu/softfloat-specialize.c.inc |
| 87 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_dma_realize(DeviceState *dev, Error **errp) | 29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 88 | } | 30 | } |
| 89 | 31 | ||
| 90 | s->dma_mr = MEMORY_REGION(obj); | 32 | if (rule == float_3nan_prop_none) { |
| 91 | - address_space_init(&s->dma_as, s->dma_mr, NULL); | 33 | -#if defined(TARGET_XTENSA) |
| 92 | + address_space_init(&s->dma_as, s->dma_mr, TYPE_BCM2835_DMA "-memory"); | 34 | - if (status->use_first_nan) { |
| 93 | 35 | - rule = float_3nan_prop_abc; | |
| 94 | bcm2835_dma_reset(dev); | 36 | - } else { |
| 95 | } | 37 | - rule = float_3nan_prop_cba; |
| 96 | diff --git a/hw/misc/bcm2835_mbox.c b/hw/misc/bcm2835_mbox.c | 38 | - } |
| 97 | index XXXXXXX..XXXXXXX 100644 | 39 | -#else |
| 98 | --- a/hw/misc/bcm2835_mbox.c | 40 | rule = float_3nan_prop_abc; |
| 99 | +++ b/hw/misc/bcm2835_mbox.c | 41 | -#endif |
| 100 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_mbox_realize(DeviceState *dev, Error **errp) | ||
| 101 | } | 42 | } |
| 102 | 43 | ||
| 103 | s->mbox_mr = MEMORY_REGION(obj); | 44 | assert(rule != float_3nan_prop_none); |
| 104 | - address_space_init(&s->mbox_as, s->mbox_mr, NULL); | ||
| 105 | + address_space_init(&s->mbox_as, s->mbox_mr, TYPE_BCM2835_MBOX "-memory"); | ||
| 106 | bcm2835_mbox_reset(dev); | ||
| 107 | } | ||
| 108 | |||
| 109 | diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c | ||
| 110 | index XXXXXXX..XXXXXXX 100644 | ||
| 111 | --- a/hw/misc/bcm2835_property.c | ||
| 112 | +++ b/hw/misc/bcm2835_property.c | ||
| 113 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_realize(DeviceState *dev, Error **errp) | ||
| 114 | } | ||
| 115 | |||
| 116 | s->dma_mr = MEMORY_REGION(obj); | ||
| 117 | - address_space_init(&s->dma_as, s->dma_mr, NULL); | ||
| 118 | + address_space_init(&s->dma_as, s->dma_mr, TYPE_BCM2835_PROPERTY "-memory"); | ||
| 119 | |||
| 120 | /* TODO: connect to MAC address of USB NIC device, once we emulate it */ | ||
| 121 | qemu_macaddr_default_if_unset(&s->macaddr); | ||
| 122 | -- | 45 | -- |
| 123 | 2.20.1 | 46 | 2.34.1 |
| 124 | |||
| 125 | diff view generated by jsdifflib |
| 1 | From: Cédric Le Goater <clg@kaod.org> | 1 | Set the Float3NaNPropRule explicitly for i386. We had no |
|---|---|---|---|
| 2 | i386-specific behaviour in the old ifdef ladder, so we were using the | ||
| 3 | default "prefer a then b then c" fallback; this is actually the | ||
| 4 | correct per-the-spec handling for i386. | ||
| 2 | 5 | ||
| 3 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 4 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
| 5 | Message-id: 20190925143248.10000-20-clg@kaod.org | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20241202131347.498124-25-peter.maydell@linaro.org | ||
| 7 | --- | 9 | --- |
| 8 | hw/block/m25p80.c | 1 + | 10 | target/i386/tcg/fpu_helper.c | 1 + |
| 9 | 1 file changed, 1 insertion(+) | 11 | 1 file changed, 1 insertion(+) |
| 10 | 12 | ||
| 11 | diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c | 13 | diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c |
| 12 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
| 13 | --- a/hw/block/m25p80.c | 15 | --- a/target/i386/tcg/fpu_helper.c |
| 14 | +++ b/hw/block/m25p80.c | 16 | +++ b/target/i386/tcg/fpu_helper.c |
| 15 | @@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = { | 17 | @@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env) |
| 16 | { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) }, | 18 | * there are multiple input NaNs they are selected in the order a, b, c. |
| 17 | { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) }, | 19 | */ |
| 18 | { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) }, | 20 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); |
| 19 | + { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K) }, | 21 | + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); |
| 20 | }; | 22 | } |
| 21 | 23 | ||
| 22 | typedef enum { | 24 | static inline uint8_t save_exception_flags(CPUX86State *env) |
| 23 | -- | 25 | -- |
| 24 | 2.20.1 | 26 | 2.34.1 |
| 25 | |||
| 26 | diff view generated by jsdifflib |
| 1 | Switch the mss-timer code away from bottom-half based ptimers to | 1 | Set the Float3NaNPropRule explicitly for HPPA, and remove the |
|---|---|---|---|
| 2 | the new transaction-based ptimer API. This just requires adding | 2 | ifdef from pickNaNMulAdd(). |
| 3 | begin/commit calls around the various places that modify the ptimer | 3 | |
| 4 | state, and using the new ptimer_init() function to create the timer. | 4 | HPPA is the only target that was using the default branch of the |
| 5 | ifdef ladder (other targets either do not use muladd or set | ||
| 6 | default_nan_mode), so we can remove the ifdef fallback entirely now | ||
| 7 | (allowing the "rule not set" case to fall into the default of the | ||
| 8 | switch statement and assert). | ||
| 9 | |||
| 10 | We add a TODO note that the HPPA rule is probably wrong; this is | ||
| 11 | not a behavioural change for this refactoring. | ||
| 5 | 12 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Message-id: 20191008171740.9679-20-peter.maydell@linaro.org | 15 | Message-id: 20241202131347.498124-26-peter.maydell@linaro.org |
| 9 | --- | 16 | --- |
| 10 | include/hw/timer/mss-timer.h | 1 - | 17 | target/hppa/fpu_helper.c | 8 ++++++++ |
| 11 | hw/timer/mss-timer.c | 11 ++++++++--- | 18 | fpu/softfloat-specialize.c.inc | 4 ---- |
| 12 | 2 files changed, 8 insertions(+), 4 deletions(-) | 19 | 2 files changed, 8 insertions(+), 4 deletions(-) |
| 13 | 20 | ||
| 14 | diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h | 21 | diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c |
| 15 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/include/hw/timer/mss-timer.h | 23 | --- a/target/hppa/fpu_helper.c |
| 17 | +++ b/include/hw/timer/mss-timer.h | 24 | +++ b/target/hppa/fpu_helper.c |
| 18 | @@ -XXX,XX +XXX,XX @@ | 25 | @@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env) |
| 19 | #define R_TIM1_MAX 6 | 26 | * HPPA does note implement a CPU reset method at all... |
| 20 | 27 | */ | |
| 21 | struct Msf2Timer { | 28 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); |
| 22 | - QEMUBH *bh; | 29 | + /* |
| 23 | ptimer_state *ptimer; | 30 | + * TODO: The HPPA architecture reference only documents its NaN |
| 24 | 31 | + * propagation rule for 2-operand operations. Testing on real hardware | |
| 25 | uint32_t regs[R_TIM1_MAX]; | 32 | + * might be necessary to confirm whether this order for muladd is correct. |
| 26 | diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c | 33 | + * Not preferring the SNaN is almost certainly incorrect as it diverges |
| 34 | + * from the documented rules for 2-operand operations. | ||
| 35 | + */ | ||
| 36 | + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status); | ||
| 37 | /* For inf * 0 + NaN, return the input NaN */ | ||
| 38 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
| 39 | } | ||
| 40 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 27 | index XXXXXXX..XXXXXXX 100644 | 41 | index XXXXXXX..XXXXXXX 100644 |
| 28 | --- a/hw/timer/mss-timer.c | 42 | --- a/fpu/softfloat-specialize.c.inc |
| 29 | +++ b/hw/timer/mss-timer.c | 43 | +++ b/fpu/softfloat-specialize.c.inc |
| 30 | @@ -XXX,XX +XXX,XX @@ | 44 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 31 | */ | ||
| 32 | |||
| 33 | #include "qemu/osdep.h" | ||
| 34 | -#include "qemu/main-loop.h" | ||
| 35 | #include "qemu/module.h" | ||
| 36 | #include "qemu/log.h" | ||
| 37 | #include "hw/irq.h" | ||
| 38 | @@ -XXX,XX +XXX,XX @@ static void timer_update_irq(struct Msf2Timer *st) | ||
| 39 | qemu_set_irq(st->irq, (ier && isr)); | ||
| 40 | } | ||
| 41 | |||
| 42 | +/* Must be called from within a ptimer_transaction_begin/commit block */ | ||
| 43 | static void timer_update(struct Msf2Timer *st) | ||
| 44 | { | ||
| 45 | uint64_t count; | ||
| 46 | @@ -XXX,XX +XXX,XX @@ timer_write(void *opaque, hwaddr offset, | ||
| 47 | switch (addr) { | ||
| 48 | case R_TIM_CTRL: | ||
| 49 | st->regs[R_TIM_CTRL] = value; | ||
| 50 | + ptimer_transaction_begin(st->ptimer); | ||
| 51 | timer_update(st); | ||
| 52 | + ptimer_transaction_commit(st->ptimer); | ||
| 53 | break; | ||
| 54 | |||
| 55 | case R_TIM_RIS: | ||
| 56 | @@ -XXX,XX +XXX,XX @@ timer_write(void *opaque, hwaddr offset, | ||
| 57 | case R_TIM_LOADVAL: | ||
| 58 | st->regs[R_TIM_LOADVAL] = value; | ||
| 59 | if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) { | ||
| 60 | + ptimer_transaction_begin(st->ptimer); | ||
| 61 | timer_update(st); | ||
| 62 | + ptimer_transaction_commit(st->ptimer); | ||
| 63 | } | 45 | } |
| 64 | break; | ||
| 65 | |||
| 66 | @@ -XXX,XX +XXX,XX @@ static void mss_timer_init(Object *obj) | ||
| 67 | for (i = 0; i < NUM_TIMERS; i++) { | ||
| 68 | struct Msf2Timer *st = &t->timers[i]; | ||
| 69 | |||
| 70 | - st->bh = qemu_bh_new(timer_hit, st); | ||
| 71 | - st->ptimer = ptimer_init_with_bh(st->bh, PTIMER_POLICY_DEFAULT); | ||
| 72 | + st->ptimer = ptimer_init(timer_hit, st, PTIMER_POLICY_DEFAULT); | ||
| 73 | + ptimer_transaction_begin(st->ptimer); | ||
| 74 | ptimer_set_freq(st->ptimer, t->freq_hz); | ||
| 75 | + ptimer_transaction_commit(st->ptimer); | ||
| 76 | sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq); | ||
| 77 | } | 46 | } |
| 78 | 47 | ||
| 48 | - if (rule == float_3nan_prop_none) { | ||
| 49 | - rule = float_3nan_prop_abc; | ||
| 50 | - } | ||
| 51 | - | ||
| 52 | assert(rule != float_3nan_prop_none); | ||
| 53 | if (have_snan && (rule & R_3NAN_SNAN_MASK)) { | ||
| 54 | /* We have at least one SNaN input and should prefer it */ | ||
| 79 | -- | 55 | -- |
| 80 | 2.20.1 | 56 | 2.34.1 |
| 81 | |||
| 82 | diff view generated by jsdifflib |
| 1 | Switch the imx_epit.c code away from bottom-half based ptimers to | 1 | The use_first_nan field in float_status was an xtensa-specific way to |
|---|---|---|---|
| 2 | the new transaction-based ptimer API. This just requires adding | 2 | select at runtime from two different NaN propagation rules. Now that |
| 3 | begin/commit calls around the various places that modify the ptimer | 3 | xtensa is using the target-agnostic NaN propagation rule selection |
| 4 | state, and using the new ptimer_init() function to create the timer. | 4 | that we've just added, we can remove use_first_nan, because there is |
| 5 | no longer any code that reads it. | ||
| 5 | 6 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Message-id: 20191008171740.9679-18-peter.maydell@linaro.org | 9 | Message-id: 20241202131347.498124-27-peter.maydell@linaro.org |
| 9 | --- | 10 | --- |
| 10 | hw/timer/imx_epit.c | 32 +++++++++++++++++++++++++++----- | 11 | include/fpu/softfloat-helpers.h | 5 ----- |
| 11 | 1 file changed, 27 insertions(+), 5 deletions(-) | 12 | include/fpu/softfloat-types.h | 1 - |
| 13 | target/xtensa/fpu_helper.c | 1 - | ||
| 14 | 3 files changed, 7 deletions(-) | ||
| 12 | 15 | ||
| 13 | diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c | 16 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h |
| 14 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/hw/timer/imx_epit.c | 18 | --- a/include/fpu/softfloat-helpers.h |
| 16 | +++ b/hw/timer/imx_epit.c | 19 | +++ b/include/fpu/softfloat-helpers.h |
| 17 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ static inline void set_snan_bit_is_one(bool val, float_status *status) |
| 18 | #include "migration/vmstate.h" | 21 | status->snan_bit_is_one = val; |
| 19 | #include "hw/irq.h" | ||
| 20 | #include "hw/misc/imx_ccm.h" | ||
| 21 | -#include "qemu/main-loop.h" | ||
| 22 | #include "qemu/module.h" | ||
| 23 | #include "qemu/log.h" | ||
| 24 | |||
| 25 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_update_int(IMXEPITState *s) | ||
| 26 | } | ||
| 27 | } | 22 | } |
| 28 | 23 | ||
| 29 | +/* | 24 | -static inline void set_use_first_nan(bool val, float_status *status) |
| 30 | + * Must be called from within a ptimer_transaction_begin/commit block | 25 | -{ |
| 31 | + * for both s->timer_cmp and s->timer_reload. | 26 | - status->use_first_nan = val; |
| 32 | + */ | 27 | -} |
| 33 | static void imx_epit_set_freq(IMXEPITState *s) | 28 | - |
| 29 | static inline void set_no_signaling_nans(bool val, float_status *status) | ||
| 34 | { | 30 | { |
| 35 | uint32_t clksrc; | 31 | status->no_signaling_nans = val; |
| 36 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_reset(DeviceState *dev) | 32 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h |
| 37 | s->lr = EPIT_TIMER_MAX; | 33 | index XXXXXXX..XXXXXXX 100644 |
| 38 | s->cmp = 0; | 34 | --- a/include/fpu/softfloat-types.h |
| 39 | s->cnt = 0; | 35 | +++ b/include/fpu/softfloat-types.h |
| 40 | + ptimer_transaction_begin(s->timer_cmp); | 36 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { |
| 41 | + ptimer_transaction_begin(s->timer_reload); | 37 | * softfloat-specialize.inc.c) |
| 42 | /* stop both timers */ | 38 | */ |
| 43 | ptimer_stop(s->timer_cmp); | 39 | bool snan_bit_is_one; |
| 44 | ptimer_stop(s->timer_reload); | 40 | - bool use_first_nan; |
| 45 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_reset(DeviceState *dev) | 41 | bool no_signaling_nans; |
| 46 | /* if the timer is still enabled, restart it */ | 42 | /* should overflowed results subtract re_bias to its exponent? */ |
| 47 | ptimer_run(s->timer_reload, 0); | 43 | bool rebias_overflow; |
| 48 | } | 44 | diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c |
| 49 | + ptimer_transaction_commit(s->timer_cmp); | 45 | index XXXXXXX..XXXXXXX 100644 |
| 50 | + ptimer_transaction_commit(s->timer_reload); | 46 | --- a/target/xtensa/fpu_helper.c |
| 51 | } | 47 | +++ b/target/xtensa/fpu_helper.c |
| 52 | 48 | @@ -XXX,XX +XXX,XX @@ static const struct { | |
| 53 | static uint32_t imx_epit_update_count(IMXEPITState *s) | 49 | |
| 54 | @@ -XXX,XX +XXX,XX @@ static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size) | 50 | void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) |
| 55 | return reg_value; | ||
| 56 | } | ||
| 57 | |||
| 58 | +/* Must be called from ptimer_transaction_begin/commit block for s->timer_cmp */ | ||
| 59 | static void imx_epit_reload_compare_timer(IMXEPITState *s) | ||
| 60 | { | 51 | { |
| 61 | if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) { | 52 | - set_use_first_nan(use_first, &env->fp_status); |
| 62 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, | 53 | set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, |
| 63 | 54 | &env->fp_status); | |
| 64 | switch (offset >> 2) { | 55 | set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba, |
| 65 | case 0: /* CR */ | ||
| 66 | + ptimer_transaction_begin(s->timer_cmp); | ||
| 67 | + ptimer_transaction_begin(s->timer_reload); | ||
| 68 | |||
| 69 | oldcr = s->cr; | ||
| 70 | s->cr = value & 0x03ffffff; | ||
| 71 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, | ||
| 72 | } else { | ||
| 73 | ptimer_stop(s->timer_cmp); | ||
| 74 | } | ||
| 75 | + | ||
| 76 | + ptimer_transaction_commit(s->timer_cmp); | ||
| 77 | + ptimer_transaction_commit(s->timer_reload); | ||
| 78 | break; | ||
| 79 | |||
| 80 | case 1: /* SR - ACK*/ | ||
| 81 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, | ||
| 82 | case 2: /* LR - set ticks */ | ||
| 83 | s->lr = value; | ||
| 84 | |||
| 85 | + ptimer_transaction_begin(s->timer_cmp); | ||
| 86 | + ptimer_transaction_begin(s->timer_reload); | ||
| 87 | if (s->cr & CR_RLD) { | ||
| 88 | /* Also set the limit if the LRD bit is set */ | ||
| 89 | /* If IOVW bit is set then set the timer value */ | ||
| 90 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, | ||
| 91 | } | ||
| 92 | |||
| 93 | imx_epit_reload_compare_timer(s); | ||
| 94 | + ptimer_transaction_commit(s->timer_cmp); | ||
| 95 | + ptimer_transaction_commit(s->timer_reload); | ||
| 96 | break; | ||
| 97 | |||
| 98 | case 3: /* CMP */ | ||
| 99 | s->cmp = value; | ||
| 100 | |||
| 101 | + ptimer_transaction_begin(s->timer_cmp); | ||
| 102 | imx_epit_reload_compare_timer(s); | ||
| 103 | + ptimer_transaction_commit(s->timer_cmp); | ||
| 104 | |||
| 105 | break; | ||
| 106 | |||
| 107 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_cmp(void *opaque) | ||
| 108 | imx_epit_update_int(s); | ||
| 109 | } | ||
| 110 | |||
| 111 | +static void imx_epit_reload(void *opaque) | ||
| 112 | +{ | ||
| 113 | + /* No action required on rollover of timer_reload */ | ||
| 114 | +} | ||
| 115 | + | ||
| 116 | static const MemoryRegionOps imx_epit_ops = { | ||
| 117 | .read = imx_epit_read, | ||
| 118 | .write = imx_epit_write, | ||
| 119 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_realize(DeviceState *dev, Error **errp) | ||
| 120 | { | ||
| 121 | IMXEPITState *s = IMX_EPIT(dev); | ||
| 122 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
| 123 | - QEMUBH *bh; | ||
| 124 | |||
| 125 | DPRINTF("\n"); | ||
| 126 | |||
| 127 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_realize(DeviceState *dev, Error **errp) | ||
| 128 | 0x00001000); | ||
| 129 | sysbus_init_mmio(sbd, &s->iomem); | ||
| 130 | |||
| 131 | - s->timer_reload = ptimer_init_with_bh(NULL, PTIMER_POLICY_DEFAULT); | ||
| 132 | + s->timer_reload = ptimer_init(imx_epit_reload, s, PTIMER_POLICY_DEFAULT); | ||
| 133 | |||
| 134 | - bh = qemu_bh_new(imx_epit_cmp, s); | ||
| 135 | - s->timer_cmp = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
| 136 | + s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_DEFAULT); | ||
| 137 | } | ||
| 138 | |||
| 139 | static void imx_epit_class_init(ObjectClass *klass, void *data) | ||
| 140 | -- | 56 | -- |
| 141 | 2.20.1 | 57 | 2.34.1 |
| 142 | |||
| 143 | diff view generated by jsdifflib |
| 1 | From: Joel Stanley <joel@jms.id.au> | 1 | Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL) |
|---|---|---|---|
| 2 | to get the NaN bit pattern to reset the FPU registers. This | ||
| 3 | works because it happens that our implementation of | ||
| 4 | floatx80_default_nan() doesn't actually look at the float_status | ||
| 5 | pointer except for TARGET_MIPS. However, this isn't guaranteed, | ||
| 6 | and to be able to remove the ifdef in floatx80_default_nan() | ||
| 7 | we're going to need a real float_status here. | ||
| 2 | 8 | ||
| 3 | The AST2600 SDMC controller is slightly different from its predecessor | 9 | Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status |
| 4 | (DRAM training). Max memory is now 2G on the AST2600. | 10 | earlier, and thus can pass it to floatx80_default_nan(). |
| 5 | 11 | ||
| 6 | Signed-off-by: Joel Stanley <joel@jms.id.au> | ||
| 7 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 8 | Message-id: 20190925143248.10000-10-clg@kaod.org | ||
| 9 | [clg: - improved commit log | ||
| 10 | - reworked model integration into new object class ] | ||
| 11 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 14 | Message-id: 20241202131347.498124-28-peter.maydell@linaro.org | ||
| 13 | --- | 15 | --- |
| 14 | include/hw/misc/aspeed_sdmc.h | 1 + | 16 | target/m68k/cpu.c | 12 +++++++----- |
| 15 | hw/misc/aspeed_scu.c | 2 + | 17 | 1 file changed, 7 insertions(+), 5 deletions(-) |
| 16 | hw/misc/aspeed_sdmc.c | 82 +++++++++++++++++++++++++++++++++++ | ||
| 17 | 3 files changed, 85 insertions(+) | ||
| 18 | 18 | ||
| 19 | diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h | 19 | diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c |
| 20 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
| 21 | --- a/include/hw/misc/aspeed_sdmc.h | 21 | --- a/target/m68k/cpu.c |
| 22 | +++ b/include/hw/misc/aspeed_sdmc.h | 22 | +++ b/target/m68k/cpu.c |
| 23 | @@ -XXX,XX +XXX,XX @@ | 23 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) |
| 24 | #define ASPEED_SDMC(obj) OBJECT_CHECK(AspeedSDMCState, (obj), TYPE_ASPEED_SDMC) | 24 | CPUState *cs = CPU(obj); |
| 25 | #define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400" | 25 | M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj); |
| 26 | #define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500" | 26 | CPUM68KState *env = cpu_env(cs); |
| 27 | +#define TYPE_ASPEED_2600_SDMC TYPE_ASPEED_SDMC "-ast2600" | 27 | - floatx80 nan = floatx80_default_nan(NULL); |
| 28 | 28 | + floatx80 nan; | |
| 29 | #define ASPEED_SDMC_NR_REGS (0x174 >> 2) | 29 | int i; |
| 30 | 30 | ||
| 31 | diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c | 31 | if (mcc->parent_phases.hold) { |
| 32 | index XXXXXXX..XXXXXXX 100644 | 32 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) |
| 33 | --- a/hw/misc/aspeed_scu.c | 33 | #else |
| 34 | +++ b/hw/misc/aspeed_scu.c | 34 | cpu_m68k_set_sr(env, SR_S | SR_I); |
| 35 | @@ -XXX,XX +XXX,XX @@ | 35 | #endif |
| 36 | #define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84) | 36 | - for (i = 0; i < 8; i++) { |
| 37 | #define AST2600_CLK_STOP_CTRL2 TO_REG(0x90) | 37 | - env->fregs[i].d = nan; |
| 38 | #define AST2600_CLK_STOP_CTR2L_CLR TO_REG(0x94) | 38 | - } |
| 39 | +#define AST2600_SDRAM_HANDSHAKE TO_REG(0x100) | 39 | - cpu_m68k_set_fpcr(env, 0); |
| 40 | #define AST2600_HPLL_PARAM TO_REG(0x200) | 40 | /* |
| 41 | #define AST2600_HPLL_EXT TO_REG(0x204) | 41 | * M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL |
| 42 | #define AST2600_MPLL_EXT TO_REG(0x224) | 42 | * 3.4 FLOATING-POINT INSTRUCTION DETAILS |
| 43 | @@ -XXX,XX +XXX,XX @@ static const uint32_t ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = { | 43 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) |
| 44 | [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC, | 44 | * preceding paragraph for nonsignaling NaNs. |
| 45 | [AST2600_CLK_STOP_CTRL] = 0xEFF43E8B, | 45 | */ |
| 46 | [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0, | 46 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); |
| 47 | + [AST2600_SDRAM_HANDSHAKE] = 0x00000040, /* SoC completed DRAM init */ | ||
| 48 | [AST2600_HPLL_PARAM] = 0x1000405F, | ||
| 49 | }; | ||
| 50 | |||
| 51 | diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c | ||
| 52 | index XXXXXXX..XXXXXXX 100644 | ||
| 53 | --- a/hw/misc/aspeed_sdmc.c | ||
| 54 | +++ b/hw/misc/aspeed_sdmc.c | ||
| 55 | @@ -XXX,XX +XXX,XX @@ | ||
| 56 | /* Control/Status Register #1 (ast2500) */ | ||
| 57 | #define R_STATUS1 (0x60 / 4) | ||
| 58 | #define PHY_BUSY_STATE BIT(0) | ||
| 59 | +#define PHY_PLL_LOCK_STATUS BIT(4) | ||
| 60 | |||
| 61 | #define R_ECC_TEST_CTRL (0x70 / 4) | ||
| 62 | #define ECC_TEST_FINISHED BIT(12) | ||
| 63 | @@ -XXX,XX +XXX,XX @@ | ||
| 64 | #define ASPEED_SDMC_AST2500_512MB 0x2 | ||
| 65 | #define ASPEED_SDMC_AST2500_1024MB 0x3 | ||
| 66 | |||
| 67 | +#define ASPEED_SDMC_AST2600_256MB 0x0 | ||
| 68 | +#define ASPEED_SDMC_AST2600_512MB 0x1 | ||
| 69 | +#define ASPEED_SDMC_AST2600_1024MB 0x2 | ||
| 70 | +#define ASPEED_SDMC_AST2600_2048MB 0x3 | ||
| 71 | + | 47 | + |
| 72 | #define ASPEED_SDMC_AST2500_READONLY_MASK \ | 48 | + nan = floatx80_default_nan(&env->fp_status); |
| 73 | (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \ | 49 | + for (i = 0; i < 8; i++) { |
| 74 | ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT | \ | 50 | + env->fregs[i].d = nan; |
| 75 | @@ -XXX,XX +XXX,XX @@ static int ast2500_rambits(AspeedSDMCState *s) | ||
| 76 | return ASPEED_SDMC_AST2500_512MB; | ||
| 77 | } | ||
| 78 | |||
| 79 | +static int ast2600_rambits(AspeedSDMCState *s) | ||
| 80 | +{ | ||
| 81 | + switch (s->ram_size >> 20) { | ||
| 82 | + case 256: | ||
| 83 | + return ASPEED_SDMC_AST2600_256MB; | ||
| 84 | + case 512: | ||
| 85 | + return ASPEED_SDMC_AST2600_512MB; | ||
| 86 | + case 1024: | ||
| 87 | + return ASPEED_SDMC_AST2600_1024MB; | ||
| 88 | + case 2048: | ||
| 89 | + return ASPEED_SDMC_AST2600_2048MB; | ||
| 90 | + default: | ||
| 91 | + break; | ||
| 92 | + } | 51 | + } |
| 93 | + | 52 | + cpu_m68k_set_fpcr(env, 0); |
| 94 | + /* use a common default */ | 53 | env->fpsr = 0; |
| 95 | + warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 512M", | 54 | |
| 96 | + s->ram_size); | 55 | /* TODO: We should set PC from the interrupt vector. */ |
| 97 | + s->ram_size = 512 << 20; | ||
| 98 | + return ASPEED_SDMC_AST2600_512MB; | ||
| 99 | +} | ||
| 100 | + | ||
| 101 | static void aspeed_sdmc_reset(DeviceState *dev) | ||
| 102 | { | ||
| 103 | AspeedSDMCState *s = ASPEED_SDMC(dev); | ||
| 104 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_2500_sdmc_info = { | ||
| 105 | .class_init = aspeed_2500_sdmc_class_init, | ||
| 106 | }; | ||
| 107 | |||
| 108 | +static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) | ||
| 109 | +{ | ||
| 110 | + uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(3) | | ||
| 111 | + ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | | ||
| 112 | + ASPEED_SDMC_DRAM_SIZE(ast2600_rambits(s)); | ||
| 113 | + | ||
| 114 | + /* Make sure readonly bits are kept (use ast2500 mask) */ | ||
| 115 | + data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; | ||
| 116 | + | ||
| 117 | + return data | fixed_conf; | ||
| 118 | +} | ||
| 119 | + | ||
| 120 | +static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg, | ||
| 121 | + uint32_t data) | ||
| 122 | +{ | ||
| 123 | + switch (reg) { | ||
| 124 | + case R_CONF: | ||
| 125 | + data = aspeed_2600_sdmc_compute_conf(s, data); | ||
| 126 | + break; | ||
| 127 | + case R_STATUS1: | ||
| 128 | + /* Will never return 'busy'. 'lock status' is always set */ | ||
| 129 | + data &= ~PHY_BUSY_STATE; | ||
| 130 | + data |= PHY_PLL_LOCK_STATUS; | ||
| 131 | + break; | ||
| 132 | + case R_ECC_TEST_CTRL: | ||
| 133 | + /* Always done, always happy */ | ||
| 134 | + data |= ECC_TEST_FINISHED; | ||
| 135 | + data &= ~ECC_TEST_FAIL; | ||
| 136 | + break; | ||
| 137 | + default: | ||
| 138 | + break; | ||
| 139 | + } | ||
| 140 | + | ||
| 141 | + s->regs[reg] = data; | ||
| 142 | +} | ||
| 143 | + | ||
| 144 | +static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data) | ||
| 145 | +{ | ||
| 146 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 147 | + AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); | ||
| 148 | + | ||
| 149 | + dc->desc = "ASPEED 2600 SDRAM Memory Controller"; | ||
| 150 | + asc->max_ram_size = 2048 << 20; | ||
| 151 | + asc->compute_conf = aspeed_2600_sdmc_compute_conf; | ||
| 152 | + asc->write = aspeed_2600_sdmc_write; | ||
| 153 | +} | ||
| 154 | + | ||
| 155 | +static const TypeInfo aspeed_2600_sdmc_info = { | ||
| 156 | + .name = TYPE_ASPEED_2600_SDMC, | ||
| 157 | + .parent = TYPE_ASPEED_SDMC, | ||
| 158 | + .class_init = aspeed_2600_sdmc_class_init, | ||
| 159 | +}; | ||
| 160 | + | ||
| 161 | static void aspeed_sdmc_register_types(void) | ||
| 162 | { | ||
| 163 | type_register_static(&aspeed_sdmc_info); | ||
| 164 | type_register_static(&aspeed_2400_sdmc_info); | ||
| 165 | type_register_static(&aspeed_2500_sdmc_info); | ||
| 166 | + type_register_static(&aspeed_2600_sdmc_info); | ||
| 167 | } | ||
| 168 | |||
| 169 | type_init(aspeed_sdmc_register_types); | ||
| 170 | -- | 56 | -- |
| 171 | 2.20.1 | 57 | 2.34.1 |
| 172 | |||
| 173 | diff view generated by jsdifflib |
| 1 | Currently for the semihosting calls which take a file descriptor | 1 | We create our 128-bit default NaN by calling parts64_default_nan() |
|---|---|---|---|
| 2 | (SYS_CLOSE, SYS_WRITE, SYS_READ, SYS_ISTTY, SYS_SEEK, SYS_FLEN) | 2 | and then adjusting the result. We can do the same trick for creating |
| 3 | we have effectively two implementations, one for real host files | 3 | the floatx80 default NaN, which lets us drop a target ifdef. |
| 4 | and one for when we indirect via the gdbstub. We want to add a | ||
| 5 | third one to deal with the magic :semihosting-features file. | ||
| 6 | 4 | ||
| 7 | Instead of having a three-way if statement in each of these | 5 | floatx80 is used only by: |
| 8 | cases, factor out the implementation of the calls to separate | 6 | i386 |
| 9 | functions which we dispatch to via function pointers selected | 7 | m68k |
| 10 | via the GuestFDType for the guest fd. | 8 | arm nwfpe old floating-point emulation emulation support |
| 9 | (which is essentially dead, especially the parts involving floatx80) | ||
| 10 | PPC (only in the xsrqpxp instruction, which just rounds an input | ||
| 11 | value by converting to floatx80 and back, so will never generate | ||
| 12 | the default NaN) | ||
| 11 | 13 | ||
| 12 | In this commit, we set up the framework for the dispatch, | 14 | The floatx80 default NaN as currently implemented is: |
| 13 | and convert the SYS_CLOSE call to use it. | 15 | m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1 |
| 16 | i386: sign = 1, exp = 1...1, int = 1, frac = 10...0 | ||
| 17 | |||
| 18 | These are the same as the parts64_default_nan for these architectures. | ||
| 19 | |||
| 20 | This is technically a possible behaviour change for arm linux-user | ||
| 21 | nwfpe emulation emulation, because the default NaN will now have the | ||
| 22 | sign bit clear. But we were already generating a different floatx80 | ||
| 23 | default NaN from the real kernel emulation we are supposedly | ||
| 24 | following, which appears to use an all-bits-1 value: | ||
| 25 | https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267 | ||
| 26 | |||
| 27 | This won't affect the only "real" use of the nwfpe emulation, which | ||
| 28 | is ancient binaries that used it as part of the old floating point | ||
| 29 | calling convention; that only uses loads and stores of 32 and 64 bit | ||
| 30 | floats, not any of the floatx80 behaviour the original hardware had. | ||
| 31 | We also get the nwfpe float64 default NaN value wrong: | ||
| 32 | https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166 | ||
| 33 | so if we ever cared about this obscure corner the right fix would be | ||
| 34 | to correct that so nwfpe used its own default-NaN setting rather | ||
| 35 | than the Arm VFP one. | ||
| 14 | 36 | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 37 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 16 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 38 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 18 | Message-id: 20190916141544.17540-8-peter.maydell@linaro.org | 39 | Message-id: 20241202131347.498124-29-peter.maydell@linaro.org |
| 19 | --- | 40 | --- |
| 20 | target/arm/arm-semi.c | 44 ++++++++++++++++++++++++++++++++++++------- | 41 | fpu/softfloat-specialize.c.inc | 20 ++++++++++---------- |
| 21 | 1 file changed, 37 insertions(+), 7 deletions(-) | 42 | 1 file changed, 10 insertions(+), 10 deletions(-) |
| 22 | 43 | ||
| 23 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 44 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 24 | index XXXXXXX..XXXXXXX 100644 | 45 | index XXXXXXX..XXXXXXX 100644 |
| 25 | --- a/target/arm/arm-semi.c | 46 | --- a/fpu/softfloat-specialize.c.inc |
| 26 | +++ b/target/arm/arm-semi.c | 47 | +++ b/fpu/softfloat-specialize.c.inc |
| 27 | @@ -XXX,XX +XXX,XX @@ static int open_modeflags[12] = { | 48 | @@ -XXX,XX +XXX,XX @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status) |
| 28 | typedef enum GuestFDType { | 49 | floatx80 floatx80_default_nan(float_status *status) |
| 29 | GuestFDUnused = 0, | ||
| 30 | GuestFDHost = 1, | ||
| 31 | + GuestFDGDB = 2, | ||
| 32 | } GuestFDType; | ||
| 33 | |||
| 34 | /* | ||
| 35 | @@ -XXX,XX +XXX,XX @@ static GuestFD *do_get_guestfd(int guestfd) | ||
| 36 | /* | ||
| 37 | * Associate the specified guest fd (which must have been | ||
| 38 | * allocated via alloc_fd() and not previously used) with | ||
| 39 | - * the specified host fd. | ||
| 40 | + * the specified host/gdb fd. | ||
| 41 | */ | ||
| 42 | static void associate_guestfd(int guestfd, int hostfd) | ||
| 43 | { | 50 | { |
| 44 | GuestFD *gf = do_get_guestfd(guestfd); | 51 | floatx80 r; |
| 45 | 52 | + /* | |
| 46 | assert(gf); | 53 | + * Extrapolate from the choices made by parts64_default_nan to fill |
| 47 | - gf->type = GuestFDHost; | 54 | + * in the floatx80 format. We assume that floatx80's explicit |
| 48 | + gf->type = use_gdb_syscalls() ? GuestFDGDB : GuestFDHost; | 55 | + * integer bit is always set (this is true for i386 and m68k, |
| 49 | gf->hostfd = hostfd; | 56 | + * which are the only real users of this format). |
| 57 | + */ | ||
| 58 | + FloatParts64 p64; | ||
| 59 | + parts64_default_nan(&p64, status); | ||
| 60 | |||
| 61 | - /* None of the targets that have snan_bit_is_one use floatx80. */ | ||
| 62 | - assert(!snan_bit_is_one(status)); | ||
| 63 | -#if defined(TARGET_M68K) | ||
| 64 | - r.low = UINT64_C(0xFFFFFFFFFFFFFFFF); | ||
| 65 | - r.high = 0x7FFF; | ||
| 66 | -#else | ||
| 67 | - /* X86 */ | ||
| 68 | - r.low = UINT64_C(0xC000000000000000); | ||
| 69 | - r.high = 0xFFFF; | ||
| 70 | -#endif | ||
| 71 | + r.high = 0x7FFF | (p64.sign << 15); | ||
| 72 | + r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac; | ||
| 73 | return r; | ||
| 50 | } | 74 | } |
| 51 | 75 | ||
| 52 | @@ -XXX,XX +XXX,XX @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, | ||
| 53 | return is_a64(env) ? env->xregs[0] : env->regs[0]; | ||
| 54 | } | ||
| 55 | |||
| 56 | +/* | ||
| 57 | + * Types for functions implementing various semihosting calls | ||
| 58 | + * for specific types of guest file descriptor. These must all | ||
| 59 | + * do the work and return the required return value for the guest, | ||
| 60 | + * setting the guest errno if appropriate. | ||
| 61 | + */ | ||
| 62 | +typedef uint32_t sys_closefn(ARMCPU *cpu, GuestFD *gf); | ||
| 63 | + | ||
| 64 | +static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) | ||
| 65 | +{ | ||
| 66 | + CPUARMState *env = &cpu->env; | ||
| 67 | + | ||
| 68 | + return set_swi_errno(env, close(gf->hostfd)); | ||
| 69 | +} | ||
| 70 | + | ||
| 71 | +static uint32_t gdb_closefn(ARMCPU *cpu, GuestFD *gf) | ||
| 72 | +{ | ||
| 73 | + return arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); | ||
| 74 | +} | ||
| 75 | + | ||
| 76 | +typedef struct GuestFDFunctions { | ||
| 77 | + sys_closefn *closefn; | ||
| 78 | +} GuestFDFunctions; | ||
| 79 | + | ||
| 80 | +static const GuestFDFunctions guestfd_fns[] = { | ||
| 81 | + [GuestFDHost] = { | ||
| 82 | + .closefn = host_closefn, | ||
| 83 | + }, | ||
| 84 | + [GuestFDGDB] = { | ||
| 85 | + .closefn = gdb_closefn, | ||
| 86 | + }, | ||
| 87 | +}; | ||
| 88 | + | ||
| 89 | /* Read the input value from the argument block; fail the semihosting | ||
| 90 | * call if the memory read fails. | ||
| 91 | */ | ||
| 92 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 93 | return set_swi_errno(env, -1); | ||
| 94 | } | ||
| 95 | |||
| 96 | - if (use_gdb_syscalls()) { | ||
| 97 | - ret = arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); | ||
| 98 | - } else { | ||
| 99 | - ret = set_swi_errno(env, close(gf->hostfd)); | ||
| 100 | - } | ||
| 101 | + ret = guestfd_fns[gf->type].closefn(cpu, gf); | ||
| 102 | dealloc_guestfd(arg0); | ||
| 103 | return ret; | ||
| 104 | case TARGET_SYS_WRITEC: | ||
| 105 | -- | 76 | -- |
| 106 | 2.20.1 | 77 | 2.34.1 |
| 107 | |||
| 108 | diff view generated by jsdifflib |
| 1 | When we are routing semihosting operations through the gdbstub, the | 1 | In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass |
|---|---|---|---|
| 2 | work of sorting out the return value and setting errno if necessary | 2 | a zero-initialized float_status struct to float32_is_quiet_nan() and |
| 3 | is done by callback functions which are invoked by the gdbstub code. | 3 | float64_is_quiet_nan(), with the cryptic comment "for |
| 4 | Clean up some ifdeffery in those functions by having them call | 4 | snan_bit_is_one". |
| 5 | set_swi_errno() to set the semihosting errno. | 5 | |
| 6 | This pattern appears to have been copied from target/riscv, where it | ||
| 7 | is used because the functions there do not have ready access to the | ||
| 8 | CPU state struct. The comment presumably refers to the fact that the | ||
| 9 | main reason the is_quiet_nan() functions want the float_state is | ||
| 10 | because they want to know about the snan_bit_is_one config. | ||
| 11 | |||
| 12 | In the loongarch helpers, though, we have the CPU state struct | ||
| 13 | to hand. Use the usual env->fp_status here. This avoids our needing | ||
| 14 | to track that we need to update the initializer of the local | ||
| 15 | float_status structs when the core softfloat code adds new | ||
| 16 | options for targets to configure their behaviour. | ||
| 6 | 17 | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 10 | Message-id: 20190916141544.17540-7-peter.maydell@linaro.org | 20 | Message-id: 20241202131347.498124-30-peter.maydell@linaro.org |
| 11 | --- | 21 | --- |
| 12 | target/arm/arm-semi.c | 27 ++++++--------------------- | 22 | target/loongarch/tcg/fpu_helper.c | 6 ++---- |
| 13 | 1 file changed, 6 insertions(+), 21 deletions(-) | 23 | 1 file changed, 2 insertions(+), 4 deletions(-) |
| 14 | 24 | ||
| 15 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 25 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c |
| 16 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/target/arm/arm-semi.c | 27 | --- a/target/loongarch/tcg/fpu_helper.c |
| 18 | +++ b/target/arm/arm-semi.c | 28 | +++ b/target/loongarch/tcg/fpu_helper.c |
| 19 | @@ -XXX,XX +XXX,XX @@ static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) | 29 | @@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj) |
| 20 | { | 30 | } else if (float32_is_zero_or_denormal(f)) { |
| 21 | ARMCPU *cpu = ARM_CPU(cs); | 31 | return sign ? 1 << 4 : 1 << 8; |
| 22 | CPUARMState *env = &cpu->env; | 32 | } else if (float32_is_any_nan(f)) { |
| 23 | -#ifdef CONFIG_USER_ONLY | 33 | - float_status s = { }; /* for snan_bit_is_one */ |
| 24 | - TaskState *ts = cs->opaque; | 34 | - return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0; |
| 25 | -#endif | 35 | + return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0; |
| 26 | target_ulong reg0 = is_a64(env) ? env->xregs[0] : env->regs[0]; | ||
| 27 | |||
| 28 | if (ret == (target_ulong)-1) { | ||
| 29 | -#ifdef CONFIG_USER_ONLY | ||
| 30 | - ts->swi_errno = err; | ||
| 31 | -#else | ||
| 32 | - syscall_err = err; | ||
| 33 | -#endif | ||
| 34 | + errno = err; | ||
| 35 | + set_swi_errno(env, -1); | ||
| 36 | reg0 = ret; | ||
| 37 | } else { | 36 | } else { |
| 38 | /* Fixup syscalls that use nonstardard return conventions. */ | 37 | return sign ? 1 << 3 : 1 << 7; |
| 39 | @@ -XXX,XX +XXX,XX @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) | 38 | } |
| 39 | @@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj) | ||
| 40 | } else if (float64_is_zero_or_denormal(f)) { | ||
| 41 | return sign ? 1 << 4 : 1 << 8; | ||
| 42 | } else if (float64_is_any_nan(f)) { | ||
| 43 | - float_status s = { }; /* for snan_bit_is_one */ | ||
| 44 | - return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0; | ||
| 45 | + return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0; | ||
| 40 | } else { | 46 | } else { |
| 41 | env->regs[0] = size; | 47 | return sign ? 1 << 3 : 1 << 7; |
| 42 | } | 48 | } |
| 43 | -#ifdef CONFIG_USER_ONLY | ||
| 44 | - ((TaskState *)cs->opaque)->swi_errno = err; | ||
| 45 | -#else | ||
| 46 | - syscall_err = err; | ||
| 47 | -#endif | ||
| 48 | + errno = err; | ||
| 49 | + set_swi_errno(env, -1); | ||
| 50 | } | ||
| 51 | |||
| 52 | static int arm_semi_open_guestfd; | ||
| 53 | @@ -XXX,XX +XXX,XX @@ static void arm_semi_open_cb(CPUState *cs, target_ulong ret, target_ulong err) | ||
| 54 | { | ||
| 55 | ARMCPU *cpu = ARM_CPU(cs); | ||
| 56 | CPUARMState *env = &cpu->env; | ||
| 57 | -#ifdef CONFIG_USER_ONLY | ||
| 58 | - TaskState *ts = cs->opaque; | ||
| 59 | -#endif | ||
| 60 | if (ret == (target_ulong)-1) { | ||
| 61 | -#ifdef CONFIG_USER_ONLY | ||
| 62 | - ts->swi_errno = err; | ||
| 63 | -#else | ||
| 64 | - syscall_err = err; | ||
| 65 | -#endif | ||
| 66 | + errno = err; | ||
| 67 | + set_swi_errno(env, -1); | ||
| 68 | dealloc_guestfd(arm_semi_open_guestfd); | ||
| 69 | } else { | ||
| 70 | associate_guestfd(arm_semi_open_guestfd, ret); | ||
| 71 | -- | 49 | -- |
| 72 | 2.20.1 | 50 | 2.34.1 |
| 73 | |||
| 74 | diff view generated by jsdifflib |
| 1 | From: Joel Stanley <joel@jms.id.au> | 1 | In the frem helper, we have a local float_status because we want to |
|---|---|---|---|
| 2 | execute the floatx80_div() with a custom rounding mode. Instead of | ||
| 3 | zero-initializing the local float_status and then having to set it up | ||
| 4 | with the m68k standard behaviour (including the NaN propagation rule | ||
| 5 | and copying the rounding precision from env->fp_status), initialize | ||
| 6 | it as a complete copy of env->fp_status. This will avoid our having | ||
| 7 | to add new code in this function for every new config knob we add | ||
| 8 | to fp_status. | ||
| 2 | 9 | ||
| 3 | To support the ast2600's four MACs allow SoCs to specify the number | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 4 | they have, and create that many. | 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 12 | Message-id: 20241202131347.498124-31-peter.maydell@linaro.org | ||
| 13 | --- | ||
| 14 | target/m68k/fpu_helper.c | 6 ++---- | ||
| 15 | 1 file changed, 2 insertions(+), 4 deletions(-) | ||
| 5 | 16 | ||
| 6 | Signed-off-by: Joel Stanley <joel@jms.id.au> | 17 | diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c |
| 7 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 8 | Message-id: 20190925143248.10000-22-clg@kaod.org | ||
| 9 | [clg: - included a check on sc->macs_num when realizing the macs | ||
| 10 | - included interrupt definitions for the AST2600 ] | ||
| 11 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 13 | --- | ||
| 14 | include/hw/arm/aspeed_soc.h | 5 ++++- | ||
| 15 | hw/arm/aspeed_ast2600.c | 10 ++++++++-- | ||
| 16 | hw/arm/aspeed_soc.c | 6 ++++-- | ||
| 17 | 3 files changed, 16 insertions(+), 5 deletions(-) | ||
| 18 | |||
| 19 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | ||
| 20 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
| 21 | --- a/include/hw/arm/aspeed_soc.h | 19 | --- a/target/m68k/fpu_helper.c |
| 22 | +++ b/include/hw/arm/aspeed_soc.h | 20 | +++ b/target/m68k/fpu_helper.c |
| 23 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) |
| 24 | #define ASPEED_SPIS_NUM 2 | 22 | |
| 25 | #define ASPEED_WDTS_NUM 4 | 23 | fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status); |
| 26 | #define ASPEED_CPUS_NUM 2 | 24 | if (!floatx80_is_any_nan(fp_rem)) { |
| 27 | -#define ASPEED_MACS_NUM 2 | 25 | - float_status fp_status = { }; |
| 28 | +#define ASPEED_MACS_NUM 4 | 26 | + /* Use local temporary fp_status to set different rounding mode */ |
| 29 | 27 | + float_status fp_status = env->fp_status; | |
| 30 | typedef struct AspeedSoCState { | 28 | uint32_t quotient; |
| 31 | /*< private >*/ | 29 | int sign; |
| 32 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCClass { | 30 | |
| 33 | uint64_t sram_size; | 31 | /* Calculate quotient directly using round to nearest mode */ |
| 34 | int spis_num; | 32 | - set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status); |
| 35 | int wdts_num; | 33 | set_float_rounding_mode(float_round_nearest_even, &fp_status); |
| 36 | + int macs_num; | 34 | - set_floatx80_rounding_precision( |
| 37 | const int *irqmap; | 35 | - get_floatx80_rounding_precision(&env->fp_status), &fp_status); |
| 38 | const hwaddr *memmap; | 36 | fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status); |
| 39 | uint32_t num_cpus; | 37 | |
| 40 | @@ -XXX,XX +XXX,XX @@ enum { | 38 | sign = extractFloatx80Sign(fp_quot.d); |
| 41 | ASPEED_I2C, | ||
| 42 | ASPEED_ETH1, | ||
| 43 | ASPEED_ETH2, | ||
| 44 | + ASPEED_ETH3, | ||
| 45 | + ASPEED_ETH4, | ||
| 46 | ASPEED_SDRAM, | ||
| 47 | ASPEED_XDMA, | ||
| 48 | }; | ||
| 49 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c | ||
| 50 | index XXXXXXX..XXXXXXX 100644 | ||
| 51 | --- a/hw/arm/aspeed_ast2600.c | ||
| 52 | +++ b/hw/arm/aspeed_ast2600.c | ||
| 53 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { | ||
| 54 | [ASPEED_SPI1] = 0x1E630000, | ||
| 55 | [ASPEED_SPI2] = 0x1E641000, | ||
| 56 | [ASPEED_ETH1] = 0x1E660000, | ||
| 57 | + [ASPEED_ETH3] = 0x1E670000, | ||
| 58 | [ASPEED_ETH2] = 0x1E680000, | ||
| 59 | + [ASPEED_ETH4] = 0x1E690000, | ||
| 60 | [ASPEED_VIC] = 0x1E6C0000, | ||
| 61 | [ASPEED_SDMC] = 0x1E6E0000, | ||
| 62 | [ASPEED_SCU] = 0x1E6E2000, | ||
| 63 | @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = { | ||
| 64 | [ASPEED_I2C] = 110, /* 110 -> 125 */ | ||
| 65 | [ASPEED_ETH1] = 2, | ||
| 66 | [ASPEED_ETH2] = 3, | ||
| 67 | + [ASPEED_ETH3] = 32, | ||
| 68 | + [ASPEED_ETH4] = 33, | ||
| 69 | + | ||
| 70 | }; | ||
| 71 | |||
| 72 | static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) | ||
| 73 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj) | ||
| 74 | OBJECT(&s->scu), &error_abort); | ||
| 75 | } | ||
| 76 | |||
| 77 | - for (i = 0; i < ASPEED_MACS_NUM; i++) { | ||
| 78 | + for (i = 0; i < sc->macs_num; i++) { | ||
| 79 | sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]), | ||
| 80 | sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); | ||
| 81 | } | ||
| 82 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | ||
| 83 | } | ||
| 84 | |||
| 85 | /* Net */ | ||
| 86 | - for (i = 0; i < nb_nics; i++) { | ||
| 87 | + for (i = 0; i < nb_nics && i < sc->macs_num; i++) { | ||
| 88 | qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]); | ||
| 89 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", | ||
| 90 | &err); | ||
| 91 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) | ||
| 92 | sc->sram_size = 0x10000; | ||
| 93 | sc->spis_num = 2; | ||
| 94 | sc->wdts_num = 4; | ||
| 95 | + sc->macs_num = 4; | ||
| 96 | sc->irqmap = aspeed_soc_ast2600_irqmap; | ||
| 97 | sc->memmap = aspeed_soc_ast2600_memmap; | ||
| 98 | sc->num_cpus = 2; | ||
| 99 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
| 100 | index XXXXXXX..XXXXXXX 100644 | ||
| 101 | --- a/hw/arm/aspeed_soc.c | ||
| 102 | +++ b/hw/arm/aspeed_soc.c | ||
| 103 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | ||
| 104 | OBJECT(&s->scu), &error_abort); | ||
| 105 | } | ||
| 106 | |||
| 107 | - for (i = 0; i < ASPEED_MACS_NUM; i++) { | ||
| 108 | + for (i = 0; i < sc->macs_num; i++) { | ||
| 109 | sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]), | ||
| 110 | sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); | ||
| 111 | } | ||
| 112 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
| 113 | } | ||
| 114 | |||
| 115 | /* Net */ | ||
| 116 | - for (i = 0; i < nb_nics; i++) { | ||
| 117 | + for (i = 0; i < nb_nics && i < sc->macs_num; i++) { | ||
| 118 | qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]); | ||
| 119 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", | ||
| 120 | &err); | ||
| 121 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) | ||
| 122 | sc->sram_size = 0x8000; | ||
| 123 | sc->spis_num = 1; | ||
| 124 | sc->wdts_num = 2; | ||
| 125 | + sc->macs_num = 2; | ||
| 126 | sc->irqmap = aspeed_soc_ast2400_irqmap; | ||
| 127 | sc->memmap = aspeed_soc_ast2400_memmap; | ||
| 128 | sc->num_cpus = 1; | ||
| 129 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) | ||
| 130 | sc->sram_size = 0x9000; | ||
| 131 | sc->spis_num = 2; | ||
| 132 | sc->wdts_num = 3; | ||
| 133 | + sc->macs_num = 2; | ||
| 134 | sc->irqmap = aspeed_soc_ast2500_irqmap; | ||
| 135 | sc->memmap = aspeed_soc_ast2500_memmap; | ||
| 136 | sc->num_cpus = 1; | ||
| 137 | -- | 39 | -- |
| 138 | 2.20.1 | 40 | 2.34.1 |
| 139 | |||
| 140 | diff view generated by jsdifflib |
| 1 | Switch the exynos4210_pwm code away from bottom-half based ptimers to | 1 | In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion |
|---|---|---|---|
| 2 | the new transaction-based ptimer API. This just requires adding | 2 | from float64 to floatx80 using a scratch float_status, because we |
| 3 | begin/commit calls around the various places that modify the ptimer | 3 | don't want the conversion to affect the CPU's floating point exception |
| 4 | state, and using the new ptimer_init() function to create the timer. | 4 | status. Currently we use a zero-initialized float_status. This will |
| 5 | get steadily more awkward as we add config knobs to float_status | ||
| 6 | that the target must initialize. Avoid having to add any of that | ||
| 7 | configuration here by instead initializing our local float_status | ||
| 8 | from the env->fp_status. | ||
| 5 | 9 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Message-id: 20191008171740.9679-15-peter.maydell@linaro.org | 12 | Message-id: 20241202131347.498124-32-peter.maydell@linaro.org |
| 9 | --- | 13 | --- |
| 10 | hw/timer/exynos4210_pwm.c | 17 ++++++++++++----- | 14 | target/m68k/helper.c | 6 ++++-- |
| 11 | 1 file changed, 12 insertions(+), 5 deletions(-) | 15 | 1 file changed, 4 insertions(+), 2 deletions(-) |
| 12 | 16 | ||
| 13 | diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c | 17 | diff --git a/target/m68k/helper.c b/target/m68k/helper.c |
| 14 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/hw/timer/exynos4210_pwm.c | 19 | --- a/target/m68k/helper.c |
| 16 | +++ b/hw/timer/exynos4210_pwm.c | 20 | +++ b/target/m68k/helper.c |
| 17 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n) |
| 18 | #include "hw/sysbus.h" | 22 | CPUM68KState *env = &cpu->env; |
| 19 | #include "migration/vmstate.h" | 23 | |
| 20 | #include "qemu/timer.h" | 24 | if (n < 8) { |
| 21 | -#include "qemu/main-loop.h" | 25 | - float_status s = {}; |
| 22 | #include "qemu/module.h" | 26 | + /* Use scratch float_status so any exceptions don't change CPU state */ |
| 23 | #include "hw/ptimer.h" | 27 | + float_status s = env->fp_status; |
| 24 | 28 | return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s)); | |
| 25 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_exynos4210_pwm_state = { | ||
| 26 | }; | ||
| 27 | |||
| 28 | /* | ||
| 29 | - * PWM update frequency | ||
| 30 | + * PWM update frequency. | ||
| 31 | + * Must be called within a ptimer_transaction_begin/commit block | ||
| 32 | + * for s->timer[id].ptimer. | ||
| 33 | */ | ||
| 34 | static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id) | ||
| 35 | { | ||
| 36 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_write(void *opaque, hwaddr offset, | ||
| 37 | |||
| 38 | /* update timers frequencies */ | ||
| 39 | for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { | ||
| 40 | + ptimer_transaction_begin(s->timer[i].ptimer); | ||
| 41 | exynos4210_pwm_update_freq(s, s->timer[i].id); | ||
| 42 | + ptimer_transaction_commit(s->timer[i].ptimer); | ||
| 43 | } | ||
| 44 | break; | ||
| 45 | |||
| 46 | case TCON: | ||
| 47 | for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { | ||
| 48 | + ptimer_transaction_begin(s->timer[i].ptimer); | ||
| 49 | if ((value & TCON_TIMER_MANUAL_UPD(i)) > | ||
| 50 | (s->reg_tcon & TCON_TIMER_MANUAL_UPD(i))) { | ||
| 51 | /* | ||
| 52 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_write(void *opaque, hwaddr offset, | ||
| 53 | ptimer_stop(s->timer[i].ptimer); | ||
| 54 | DPRINTF("stop timer %d\n", i); | ||
| 55 | } | ||
| 56 | + ptimer_transaction_commit(s->timer[i].ptimer); | ||
| 57 | } | ||
| 58 | s->reg_tcon = value; | ||
| 59 | break; | ||
| 60 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_reset(DeviceState *d) | ||
| 61 | s->timer[i].reg_tcmpb = 0; | ||
| 62 | s->timer[i].reg_tcntb = 0; | ||
| 63 | |||
| 64 | + ptimer_transaction_begin(s->timer[i].ptimer); | ||
| 65 | exynos4210_pwm_update_freq(s, s->timer[i].id); | ||
| 66 | ptimer_stop(s->timer[i].ptimer); | ||
| 67 | + ptimer_transaction_commit(s->timer[i].ptimer); | ||
| 68 | } | 29 | } |
| 69 | } | 30 | switch (n) { |
| 70 | 31 | @@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n) | |
| 71 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_init(Object *obj) | 32 | CPUM68KState *env = &cpu->env; |
| 72 | Exynos4210PWMState *s = EXYNOS4210_PWM(obj); | 33 | |
| 73 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | 34 | if (n < 8) { |
| 74 | int i; | 35 | - float_status s = {}; |
| 75 | - QEMUBH *bh; | 36 | + /* Use scratch float_status so any exceptions don't change CPU state */ |
| 76 | 37 | + float_status s = env->fp_status; | |
| 77 | for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { | 38 | env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s); |
| 78 | - bh = qemu_bh_new(exynos4210_pwm_tick, &s->timer[i]); | 39 | return 8; |
| 79 | sysbus_init_irq(dev, &s->timer[i].irq); | ||
| 80 | - s->timer[i].ptimer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
| 81 | + s->timer[i].ptimer = ptimer_init(exynos4210_pwm_tick, | ||
| 82 | + &s->timer[i], | ||
| 83 | + PTIMER_POLICY_DEFAULT); | ||
| 84 | s->timer[i].id = i; | ||
| 85 | s->timer[i].parent = s; | ||
| 86 | } | 40 | } |
| 87 | -- | 41 | -- |
| 88 | 2.20.1 | 42 | 2.34.1 |
| 89 | |||
| 90 | diff view generated by jsdifflib |
| 1 | Provide the new transaction-based API. If a ptimer is created | 1 | In the helper functions flcmps and flcmpd we use a scratch float_status |
|---|---|---|---|
| 2 | using ptimer_init() rather than ptimer_init_with_bh(), then | 2 | so that we don't change the CPU state if the comparison raises any |
| 3 | instead of providing a QEMUBH, it provides a pointer to the | 3 | floating point exception flags. Instead of zero-initializing this |
| 4 | callback function directly, and has opted into the transaction | 4 | scratch float_status, initialize it as a copy of env->fp_status. This |
| 5 | API. All calls to functions which modify ptimer state: | 5 | avoids the need to explicitly initialize settings like the NaN |
| 6 | - ptimer_set_period() | 6 | propagation rule or others we might add to softfloat in future. |
| 7 | - ptimer_set_freq() | ||
| 8 | - ptimer_set_limit() | ||
| 9 | - ptimer_set_count() | ||
| 10 | - ptimer_run() | ||
| 11 | - ptimer_stop() | ||
| 12 | must be between matched calls to ptimer_transaction_begin() | ||
| 13 | and ptimer_transaction_commit(). When ptimer_transaction_commit() | ||
| 14 | is called it will evaluate the state of the timer after all the | ||
| 15 | changes in the transaction, and call the callback if necessary. | ||
| 16 | 7 | ||
| 17 | In the old API the individual update functions generally would | 8 | To do this we need to pass the CPU env pointer in to the helper. |
| 18 | call ptimer_trigger() immediately, which would schedule the QEMUBH. | ||
| 19 | In the new API the update functions will instead defer the | ||
| 20 | "set s->next_event and call ptimer_reload()" work to | ||
| 21 | ptimer_transaction_commit(). | ||
| 22 | |||
| 23 | Because ptimer_trigger() can now immediately call into the | ||
| 24 | device code which may then call other ptimer functions that | ||
| 25 | update ptimer_state fields, we must be more careful in | ||
| 26 | ptimer_reload() not to cache fields from ptimer_state across | ||
| 27 | the ptimer_trigger() call. (This was harmless with the QEMUBH | ||
| 28 | mechanism as the BH would not be invoked until much later.) | ||
| 29 | |||
| 30 | We use assertions to check that: | ||
| 31 | * the functions modifying ptimer state are not called outside | ||
| 32 | a transaction block | ||
| 33 | * ptimer_transaction_begin() and _commit() calls are paired | ||
| 34 | * the transaction API is not used with a QEMUBH ptimer | ||
| 35 | |||
| 36 | There is some slight repetition of code: | ||
| 37 | * most of the set functions have similar looking "if s->bh | ||
| 38 | call ptimer_reload, otherwise set s->need_reload" code | ||
| 39 | * ptimer_init() and ptimer_init_with_bh() have similar code | ||
| 40 | We deliberately don't try to avoid this repetition, because | ||
| 41 | it will all be deleted when the QEMUBH version of the API | ||
| 42 | is removed. | ||
| 43 | 9 | ||
| 44 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 45 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 46 | Message-id: 20191008171740.9679-3-peter.maydell@linaro.org | 12 | Message-id: 20241202131347.498124-33-peter.maydell@linaro.org |
| 47 | --- | 13 | --- |
| 48 | include/hw/ptimer.h | 72 +++++++++++++++++++++ | 14 | target/sparc/helper.h | 4 ++-- |
| 49 | hw/core/ptimer.c | 152 +++++++++++++++++++++++++++++++++++++++----- | 15 | target/sparc/fop_helper.c | 8 ++++---- |
| 50 | 2 files changed, 209 insertions(+), 15 deletions(-) | 16 | target/sparc/translate.c | 4 ++-- |
| 17 | 3 files changed, 8 insertions(+), 8 deletions(-) | ||
| 51 | 18 | ||
| 52 | diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h | 19 | diff --git a/target/sparc/helper.h b/target/sparc/helper.h |
| 53 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
| 54 | --- a/include/hw/ptimer.h | 21 | --- a/target/sparc/helper.h |
| 55 | +++ b/include/hw/ptimer.h | 22 | +++ b/target/sparc/helper.h |
| 56 | @@ -XXX,XX +XXX,XX @@ typedef void (*ptimer_cb)(void *opaque); | 23 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64) |
| 57 | */ | 24 | DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64) |
| 58 | ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask); | 25 | DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128) |
| 59 | 26 | DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128) | |
| 60 | +/** | 27 | -DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32) |
| 61 | + * ptimer_init - Allocate and return a new ptimer | 28 | -DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64) |
| 62 | + * @callback: function to call on ptimer expiry | 29 | +DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32) |
| 63 | + * @callback_opaque: opaque pointer passed to @callback | 30 | +DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64) |
| 64 | + * @policy: PTIMER_POLICY_* bits specifying behaviour | 31 | DEF_HELPER_2(raise_exception, noreturn, env, int) |
| 65 | + * | 32 | |
| 66 | + * The ptimer returned must be freed using ptimer_free(). | 33 | DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64) |
| 67 | + * | 34 | diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c |
| 68 | + * If a ptimer is created using this API then will use the | ||
| 69 | + * transaction-based API for modifying ptimer state: all calls | ||
| 70 | + * to functions which modify ptimer state: | ||
| 71 | + * - ptimer_set_period() | ||
| 72 | + * - ptimer_set_freq() | ||
| 73 | + * - ptimer_set_limit() | ||
| 74 | + * - ptimer_set_count() | ||
| 75 | + * - ptimer_run() | ||
| 76 | + * - ptimer_stop() | ||
| 77 | + * must be between matched calls to ptimer_transaction_begin() | ||
| 78 | + * and ptimer_transaction_commit(). When ptimer_transaction_commit() | ||
| 79 | + * is called it will evaluate the state of the timer after all the | ||
| 80 | + * changes in the transaction, and call the callback if necessary. | ||
| 81 | + * | ||
| 82 | + * The callback function is always called from within a transaction | ||
| 83 | + * begin/commit block, so the callback should not call the | ||
| 84 | + * ptimer_transaction_begin() function itself. If the callback changes | ||
| 85 | + * the ptimer state such that another ptimer expiry is triggered, then | ||
| 86 | + * the callback will be called a second time after the first call returns. | ||
| 87 | + */ | ||
| 88 | +ptimer_state *ptimer_init(ptimer_cb callback, | ||
| 89 | + void *callback_opaque, | ||
| 90 | + uint8_t policy_mask); | ||
| 91 | + | ||
| 92 | /** | ||
| 93 | * ptimer_free - Free a ptimer | ||
| 94 | * @s: timer to free | ||
| 95 | @@ -XXX,XX +XXX,XX @@ ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask); | ||
| 96 | */ | ||
| 97 | void ptimer_free(ptimer_state *s); | ||
| 98 | |||
| 99 | +/** | ||
| 100 | + * ptimer_transaction_begin() - Start a ptimer modification transaction | ||
| 101 | + * | ||
| 102 | + * This function must be called before making any calls to functions | ||
| 103 | + * which modify the ptimer's state (see the ptimer_init() documentation | ||
| 104 | + * for a list of these), and must always have a matched call to | ||
| 105 | + * ptimer_transaction_commit(). | ||
| 106 | + * It is an error to call this function for a BH-based ptimer; | ||
| 107 | + * attempting to do this will trigger an assert. | ||
| 108 | + */ | ||
| 109 | +void ptimer_transaction_begin(ptimer_state *s); | ||
| 110 | + | ||
| 111 | +/** | ||
| 112 | + * ptimer_transaction_commit() - Commit a ptimer modification transaction | ||
| 113 | + * | ||
| 114 | + * This function must be called after calls to functions which modify | ||
| 115 | + * the ptimer's state, and completes the update of the ptimer. If the | ||
| 116 | + * ptimer state now means that we should trigger the timer expiry | ||
| 117 | + * callback, it will be called directly. | ||
| 118 | + */ | ||
| 119 | +void ptimer_transaction_commit(ptimer_state *s); | ||
| 120 | + | ||
| 121 | /** | ||
| 122 | * ptimer_set_period - Set counter increment interval in nanoseconds | ||
| 123 | * @s: ptimer to configure | ||
| 124 | @@ -XXX,XX +XXX,XX @@ void ptimer_free(ptimer_state *s); | ||
| 125 | * Note that if your counter behaviour is specified as having a | ||
| 126 | * particular frequency rather than a period then ptimer_set_freq() | ||
| 127 | * may be more appropriate. | ||
| 128 | + * | ||
| 129 | + * This function will assert if it is called outside a | ||
| 130 | + * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. | ||
| 131 | */ | ||
| 132 | void ptimer_set_period(ptimer_state *s, int64_t period); | ||
| 133 | |||
| 134 | @@ -XXX,XX +XXX,XX @@ void ptimer_set_period(ptimer_state *s, int64_t period); | ||
| 135 | * as setting the frequency then this function is more appropriate, | ||
| 136 | * because it allows specifying an effective period which is | ||
| 137 | * precise to fractions of a nanosecond, avoiding rounding errors. | ||
| 138 | + * | ||
| 139 | + * This function will assert if it is called outside a | ||
| 140 | + * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. | ||
| 141 | */ | ||
| 142 | void ptimer_set_freq(ptimer_state *s, uint32_t freq); | ||
| 143 | |||
| 144 | @@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_limit(ptimer_state *s); | ||
| 145 | * Set the limit value of the down-counter. The @reload flag can | ||
| 146 | * be used to emulate the behaviour of timers which immediately | ||
| 147 | * reload the counter when their reload register is written to. | ||
| 148 | + * | ||
| 149 | + * This function will assert if it is called outside a | ||
| 150 | + * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. | ||
| 151 | */ | ||
| 152 | void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload); | ||
| 153 | |||
| 154 | @@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_count(ptimer_state *s); | ||
| 155 | * Set the value of the down-counter. If the counter is currently | ||
| 156 | * enabled this will arrange for a timer callback at the appropriate | ||
| 157 | * point in the future. | ||
| 158 | + * | ||
| 159 | + * This function will assert if it is called outside a | ||
| 160 | + * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. | ||
| 161 | */ | ||
| 162 | void ptimer_set_count(ptimer_state *s, uint64_t count); | ||
| 163 | |||
| 164 | @@ -XXX,XX +XXX,XX @@ void ptimer_set_count(ptimer_state *s, uint64_t count); | ||
| 165 | * the counter value will then be reloaded from the limit and it will | ||
| 166 | * start counting down again. If @oneshot is non-zero, then the counter | ||
| 167 | * will disable itself when it reaches zero. | ||
| 168 | + * | ||
| 169 | + * This function will assert if it is called outside a | ||
| 170 | + * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. | ||
| 171 | */ | ||
| 172 | void ptimer_run(ptimer_state *s, int oneshot); | ||
| 173 | |||
| 174 | @@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot); | ||
| 175 | * | ||
| 176 | * Note that this can cause it to "lose" time, even if it is immediately | ||
| 177 | * restarted. | ||
| 178 | + * | ||
| 179 | + * This function will assert if it is called outside a | ||
| 180 | + * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. | ||
| 181 | */ | ||
| 182 | void ptimer_stop(ptimer_state *s); | ||
| 183 | |||
| 184 | diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c | ||
| 185 | index XXXXXXX..XXXXXXX 100644 | 35 | index XXXXXXX..XXXXXXX 100644 |
| 186 | --- a/hw/core/ptimer.c | 36 | --- a/target/sparc/fop_helper.c |
| 187 | +++ b/hw/core/ptimer.c | 37 | +++ b/target/sparc/fop_helper.c |
| 188 | @@ -XXX,XX +XXX,XX @@ struct ptimer_state | 38 | @@ -XXX,XX +XXX,XX @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2) |
| 189 | uint8_t policy_mask; | 39 | return finish_fcmp(env, r, GETPC()); |
| 190 | QEMUBH *bh; | ||
| 191 | QEMUTimer *timer; | ||
| 192 | + ptimer_cb callback; | ||
| 193 | + void *callback_opaque; | ||
| 194 | + /* | ||
| 195 | + * These track whether we're in a transaction block, and if we | ||
| 196 | + * need to do a timer reload when the block finishes. They don't | ||
| 197 | + * need to be migrated because migration can never happen in the | ||
| 198 | + * middle of a transaction block. | ||
| 199 | + */ | ||
| 200 | + bool in_transaction; | ||
| 201 | + bool need_reload; | ||
| 202 | }; | ||
| 203 | |||
| 204 | /* Use a bottom-half routine to avoid reentrancy issues. */ | ||
| 205 | @@ -XXX,XX +XXX,XX @@ static void ptimer_trigger(ptimer_state *s) | ||
| 206 | if (s->bh) { | ||
| 207 | replay_bh_schedule_event(s->bh); | ||
| 208 | } | ||
| 209 | + if (s->callback) { | ||
| 210 | + s->callback(s->callback_opaque); | ||
| 211 | + } | ||
| 212 | } | 40 | } |
| 213 | 41 | ||
| 214 | static void ptimer_reload(ptimer_state *s, int delta_adjust) | 42 | -uint32_t helper_flcmps(float32 src1, float32 src2) |
| 43 | +uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2) | ||
| 215 | { | 44 | { |
| 216 | - uint32_t period_frac = s->period_frac; | ||
| 217 | - uint64_t period = s->period; | ||
| 218 | - uint64_t delta = s->delta; | ||
| 219 | + uint32_t period_frac; | ||
| 220 | + uint64_t period; | ||
| 221 | + uint64_t delta; | ||
| 222 | bool suppress_trigger = false; | ||
| 223 | |||
| 224 | /* | 45 | /* |
| 225 | @@ -XXX,XX +XXX,XX @@ static void ptimer_reload(ptimer_state *s, int delta_adjust) | 46 | * FLCMP never raises an exception nor modifies any FSR fields. |
| 226 | (s->policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT)) { | 47 | * Perform the comparison with a dummy fp environment. |
| 227 | suppress_trigger = true; | 48 | */ |
| 228 | } | 49 | - float_status discard = { }; |
| 229 | - if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER) | 50 | + float_status discard = env->fp_status; |
| 230 | + if (s->delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER) | 51 | FloatRelation r; |
| 231 | && !suppress_trigger) { | 52 | |
| 232 | ptimer_trigger(s); | 53 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); |
| 233 | } | 54 | @@ -XXX,XX +XXX,XX @@ uint32_t helper_flcmps(float32 src1, float32 src2) |
| 234 | 55 | g_assert_not_reached(); | |
| 235 | + /* | ||
| 236 | + * Note that ptimer_trigger() might call the device callback function, | ||
| 237 | + * which can then modify timer state, so we must not cache any fields | ||
| 238 | + * from ptimer_state until after we have called it. | ||
| 239 | + */ | ||
| 240 | + delta = s->delta; | ||
| 241 | + period = s->period; | ||
| 242 | + period_frac = s->period_frac; | ||
| 243 | + | ||
| 244 | if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_RELOAD)) { | ||
| 245 | delta = s->delta = s->limit; | ||
| 246 | } | ||
| 247 | @@ -XXX,XX +XXX,XX @@ static void ptimer_tick(void *opaque) | ||
| 248 | ptimer_state *s = (ptimer_state *)opaque; | ||
| 249 | bool trigger = true; | ||
| 250 | |||
| 251 | + /* | ||
| 252 | + * We perform all the tick actions within a begin/commit block | ||
| 253 | + * because the callback function that ptimer_trigger() calls | ||
| 254 | + * might make calls into the ptimer APIs that provoke another | ||
| 255 | + * trigger, and we want that to cause the callback function | ||
| 256 | + * to be called iteratively, not recursively. | ||
| 257 | + */ | ||
| 258 | + ptimer_transaction_begin(s); | ||
| 259 | + | ||
| 260 | if (s->enabled == 2) { | ||
| 261 | s->delta = 0; | ||
| 262 | s->enabled = 0; | ||
| 263 | @@ -XXX,XX +XXX,XX @@ static void ptimer_tick(void *opaque) | ||
| 264 | if (trigger) { | ||
| 265 | ptimer_trigger(s); | ||
| 266 | } | ||
| 267 | + | ||
| 268 | + ptimer_transaction_commit(s); | ||
| 269 | } | 56 | } |
| 270 | 57 | ||
| 271 | uint64_t ptimer_get_count(ptimer_state *s) | 58 | -uint32_t helper_flcmpd(float64 src1, float64 src2) |
| 272 | @@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_count(ptimer_state *s) | 59 | +uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2) |
| 273 | |||
| 274 | void ptimer_set_count(ptimer_state *s, uint64_t count) | ||
| 275 | { | 60 | { |
| 276 | + assert(s->in_transaction || !s->callback); | 61 | - float_status discard = { }; |
| 277 | s->delta = count; | 62 | + float_status discard = env->fp_status; |
| 278 | if (s->enabled) { | 63 | FloatRelation r; |
| 279 | - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | 64 | |
| 280 | - ptimer_reload(s, 0); | 65 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); |
| 281 | + if (!s->callback) { | 66 | diff --git a/target/sparc/translate.c b/target/sparc/translate.c |
| 282 | + s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | 67 | index XXXXXXX..XXXXXXX 100644 |
| 283 | + ptimer_reload(s, 0); | 68 | --- a/target/sparc/translate.c |
| 284 | + } else { | 69 | +++ b/target/sparc/translate.c |
| 285 | + s->need_reload = true; | 70 | @@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a) |
| 286 | + } | 71 | |
| 287 | } | 72 | src1 = gen_load_fpr_F(dc, a->rs1); |
| 73 | src2 = gen_load_fpr_F(dc, a->rs2); | ||
| 74 | - gen_helper_flcmps(cpu_fcc[a->cc], src1, src2); | ||
| 75 | + gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2); | ||
| 76 | return advance_pc(dc); | ||
| 288 | } | 77 | } |
| 289 | 78 | ||
| 290 | @@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot) | 79 | @@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a) |
| 291 | { | 80 | |
| 292 | bool was_disabled = !s->enabled; | 81 | src1 = gen_load_fpr_D(dc, a->rs1); |
| 293 | 82 | src2 = gen_load_fpr_D(dc, a->rs2); | |
| 294 | + assert(s->in_transaction || !s->callback); | 83 | - gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2); |
| 295 | + | 84 | + gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2); |
| 296 | if (was_disabled && s->period == 0) { | 85 | return advance_pc(dc); |
| 297 | if (!qtest_enabled()) { | ||
| 298 | fprintf(stderr, "Timer with period zero, disabling\n"); | ||
| 299 | @@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot) | ||
| 300 | } | ||
| 301 | s->enabled = oneshot ? 2 : 1; | ||
| 302 | if (was_disabled) { | ||
| 303 | - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
| 304 | - ptimer_reload(s, 0); | ||
| 305 | + if (!s->callback) { | ||
| 306 | + s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
| 307 | + ptimer_reload(s, 0); | ||
| 308 | + } else { | ||
| 309 | + s->need_reload = true; | ||
| 310 | + } | ||
| 311 | } | ||
| 312 | } | 86 | } |
| 313 | 87 | ||
| 314 | @@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot) | ||
| 315 | is immediately restarted. */ | ||
| 316 | void ptimer_stop(ptimer_state *s) | ||
| 317 | { | ||
| 318 | + assert(s->in_transaction || !s->callback); | ||
| 319 | + | ||
| 320 | if (!s->enabled) | ||
| 321 | return; | ||
| 322 | |||
| 323 | s->delta = ptimer_get_count(s); | ||
| 324 | timer_del(s->timer); | ||
| 325 | s->enabled = 0; | ||
| 326 | + if (s->callback) { | ||
| 327 | + s->need_reload = false; | ||
| 328 | + } | ||
| 329 | } | ||
| 330 | |||
| 331 | /* Set counter increment interval in nanoseconds. */ | ||
| 332 | void ptimer_set_period(ptimer_state *s, int64_t period) | ||
| 333 | { | ||
| 334 | + assert(s->in_transaction || !s->callback); | ||
| 335 | s->delta = ptimer_get_count(s); | ||
| 336 | s->period = period; | ||
| 337 | s->period_frac = 0; | ||
| 338 | if (s->enabled) { | ||
| 339 | - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
| 340 | - ptimer_reload(s, 0); | ||
| 341 | + if (!s->callback) { | ||
| 342 | + s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
| 343 | + ptimer_reload(s, 0); | ||
| 344 | + } else { | ||
| 345 | + s->need_reload = true; | ||
| 346 | + } | ||
| 347 | } | ||
| 348 | } | ||
| 349 | |||
| 350 | /* Set counter frequency in Hz. */ | ||
| 351 | void ptimer_set_freq(ptimer_state *s, uint32_t freq) | ||
| 352 | { | ||
| 353 | + assert(s->in_transaction || !s->callback); | ||
| 354 | s->delta = ptimer_get_count(s); | ||
| 355 | s->period = 1000000000ll / freq; | ||
| 356 | s->period_frac = (1000000000ll << 32) / freq; | ||
| 357 | if (s->enabled) { | ||
| 358 | - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
| 359 | - ptimer_reload(s, 0); | ||
| 360 | + if (!s->callback) { | ||
| 361 | + s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
| 362 | + ptimer_reload(s, 0); | ||
| 363 | + } else { | ||
| 364 | + s->need_reload = true; | ||
| 365 | + } | ||
| 366 | } | ||
| 367 | } | ||
| 368 | |||
| 369 | @@ -XXX,XX +XXX,XX @@ void ptimer_set_freq(ptimer_state *s, uint32_t freq) | ||
| 370 | count = limit. */ | ||
| 371 | void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload) | ||
| 372 | { | ||
| 373 | + assert(s->in_transaction || !s->callback); | ||
| 374 | s->limit = limit; | ||
| 375 | if (reload) | ||
| 376 | s->delta = limit; | ||
| 377 | if (s->enabled && reload) { | ||
| 378 | - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
| 379 | - ptimer_reload(s, 0); | ||
| 380 | + if (!s->callback) { | ||
| 381 | + s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
| 382 | + ptimer_reload(s, 0); | ||
| 383 | + } else { | ||
| 384 | + s->need_reload = true; | ||
| 385 | + } | ||
| 386 | } | ||
| 387 | } | ||
| 388 | |||
| 389 | @@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_limit(ptimer_state *s) | ||
| 390 | return s->limit; | ||
| 391 | } | ||
| 392 | |||
| 393 | +void ptimer_transaction_begin(ptimer_state *s) | ||
| 394 | +{ | ||
| 395 | + assert(!s->in_transaction || !s->callback); | ||
| 396 | + s->in_transaction = true; | ||
| 397 | + s->need_reload = false; | ||
| 398 | +} | ||
| 399 | + | ||
| 400 | +void ptimer_transaction_commit(ptimer_state *s) | ||
| 401 | +{ | ||
| 402 | + assert(s->in_transaction); | ||
| 403 | + /* | ||
| 404 | + * We must loop here because ptimer_reload() can call the callback | ||
| 405 | + * function, which might then update ptimer state in a way that | ||
| 406 | + * means we need to do another reload and possibly another callback. | ||
| 407 | + * A disabled timer never needs reloading (and if we don't check | ||
| 408 | + * this then we loop forever if ptimer_reload() disables the timer). | ||
| 409 | + */ | ||
| 410 | + while (s->need_reload && s->enabled) { | ||
| 411 | + s->need_reload = false; | ||
| 412 | + s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
| 413 | + ptimer_reload(s, 0); | ||
| 414 | + } | ||
| 415 | + /* Now we've finished reload we can leave the transaction block. */ | ||
| 416 | + s->in_transaction = false; | ||
| 417 | +} | ||
| 418 | + | ||
| 419 | const VMStateDescription vmstate_ptimer = { | ||
| 420 | .name = "ptimer", | ||
| 421 | .version_id = 1, | ||
| 422 | @@ -XXX,XX +XXX,XX @@ ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask) | ||
| 423 | return s; | ||
| 424 | } | ||
| 425 | |||
| 426 | +ptimer_state *ptimer_init(ptimer_cb callback, void *callback_opaque, | ||
| 427 | + uint8_t policy_mask) | ||
| 428 | +{ | ||
| 429 | + ptimer_state *s; | ||
| 430 | + | ||
| 431 | + /* | ||
| 432 | + * The callback function is mandatory; so we use it to distinguish | ||
| 433 | + * old-style QEMUBH ptimers from new transaction API ptimers. | ||
| 434 | + * (ptimer_init_with_bh() allows a NULL bh pointer and at least | ||
| 435 | + * one device (digic-timer) passes NULL, so it's not the case | ||
| 436 | + * that either s->bh != NULL or s->callback != NULL.) | ||
| 437 | + */ | ||
| 438 | + assert(callback); | ||
| 439 | + | ||
| 440 | + s = g_new0(ptimer_state, 1); | ||
| 441 | + s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s); | ||
| 442 | + s->policy_mask = policy_mask; | ||
| 443 | + s->callback = callback; | ||
| 444 | + s->callback_opaque = callback_opaque; | ||
| 445 | + | ||
| 446 | + /* | ||
| 447 | + * These two policies are incompatible -- trigger-on-decrement implies | ||
| 448 | + * a timer trigger when the count becomes 0, but no-immediate-trigger | ||
| 449 | + * implies a trigger when the count stops being 0. | ||
| 450 | + */ | ||
| 451 | + assert(!((policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) && | ||
| 452 | + (policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER))); | ||
| 453 | + return s; | ||
| 454 | +} | ||
| 455 | + | ||
| 456 | void ptimer_free(ptimer_state *s) | ||
| 457 | { | ||
| 458 | - qemu_bh_delete(s->bh); | ||
| 459 | + if (s->bh) { | ||
| 460 | + qemu_bh_delete(s->bh); | ||
| 461 | + } | ||
| 462 | timer_free(s->timer); | ||
| 463 | g_free(s); | ||
| 464 | } | ||
| 465 | -- | 88 | -- |
| 466 | 2.20.1 | 89 | 2.34.1 |
| 467 | |||
| 468 | diff view generated by jsdifflib |
| 1 | From: Rashmica Gupta <rashmica.g@gmail.com> | 1 | In the helper_compute_fprf functions, we pass a dummy float_status |
|---|---|---|---|
| 2 | in to the is_signaling_nan() function. This is unnecessary, because | ||
| 3 | we have convenient access to the CPU env pointer here and that | ||
| 4 | is already set up with the correct values for the snan_bit_is_one | ||
| 5 | and no_signaling_nans config settings. is_signaling_nan() doesn't | ||
| 6 | ever update the fp_status with any exception flags, so there is | ||
| 7 | no reason not to use env->fp_status here. | ||
| 2 | 8 | ||
| 3 | The AST2600 has the same sets of 3.6v gpios as the AST2400 plus an | 9 | Use env->fp_status instead of the dummy fp_status. |
| 4 | addtional two sets of 1.8V gpios. | ||
| 5 | 10 | ||
| 6 | Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com> | ||
| 7 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
| 8 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 9 | Acked-by: Joel Stanley <joel@jms.id.au> | ||
| 10 | Message-id: 20190925143248.10000-15-clg@kaod.org | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 13 | Message-id: 20241202131347.498124-34-peter.maydell@linaro.org | ||
| 12 | --- | 14 | --- |
| 13 | hw/gpio/aspeed_gpio.c | 142 ++++++++++++++++++++++++++++++++++++++++-- | 15 | target/ppc/fpu_helper.c | 3 +-- |
| 14 | 1 file changed, 137 insertions(+), 5 deletions(-) | 16 | 1 file changed, 1 insertion(+), 2 deletions(-) |
| 15 | 17 | ||
| 16 | diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c | 18 | diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c |
| 17 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/hw/gpio/aspeed_gpio.c | 20 | --- a/target/ppc/fpu_helper.c |
| 19 | +++ b/hw/gpio/aspeed_gpio.c | 21 | +++ b/target/ppc/fpu_helper.c |
| 20 | @@ -XXX,XX +XXX,XX @@ | 22 | @@ -XXX,XX +XXX,XX @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \ |
| 21 | #define GPIO_3_6V_MEM_SIZE 0x1F0 | 23 | } else if (tp##_is_infinity(arg)) { \ |
| 22 | #define GPIO_3_6V_REG_ARRAY_SIZE (GPIO_3_6V_MEM_SIZE >> 2) | 24 | fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \ |
| 23 | 25 | } else { \ | |
| 24 | +/* AST2600 only - 1.8V gpios */ | 26 | - float_status dummy = { }; /* snan_bit_is_one = 0 */ \ |
| 25 | +/* | 27 | - if (tp##_is_signaling_nan(arg, &dummy)) { \ |
| 26 | + * The AST2600 has same 3.6V gpios as the AST2400 (memory offsets 0x0-0x198) | 28 | + if (tp##_is_signaling_nan(arg, &env->fp_status)) { \ |
| 27 | + * and addtional 1.8V gpios (memory offsets 0x800-0x9D4). | 29 | fprf = 0x00 << FPSCR_FPRF; \ |
| 28 | + */ | 30 | } else { \ |
| 29 | +#define GPIO_1_8V_REG_OFFSET 0x800 | 31 | fprf = 0x11 << FPSCR_FPRF; \ |
| 30 | +#define GPIO_1_8V_ABCD_DATA_VALUE ((0x800 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 31 | +#define GPIO_1_8V_ABCD_DIRECTION ((0x804 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 32 | +#define GPIO_1_8V_ABCD_INT_ENABLE ((0x808 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 33 | +#define GPIO_1_8V_ABCD_INT_SENS_0 ((0x80C - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 34 | +#define GPIO_1_8V_ABCD_INT_SENS_1 ((0x810 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 35 | +#define GPIO_1_8V_ABCD_INT_SENS_2 ((0x814 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 36 | +#define GPIO_1_8V_ABCD_INT_STATUS ((0x818 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 37 | +#define GPIO_1_8V_ABCD_RESET_TOLERANT ((0x81C - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 38 | +#define GPIO_1_8V_E_DATA_VALUE ((0x820 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 39 | +#define GPIO_1_8V_E_DIRECTION ((0x824 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 40 | +#define GPIO_1_8V_E_INT_ENABLE ((0x828 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 41 | +#define GPIO_1_8V_E_INT_SENS_0 ((0x82C - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 42 | +#define GPIO_1_8V_E_INT_SENS_1 ((0x830 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 43 | +#define GPIO_1_8V_E_INT_SENS_2 ((0x834 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 44 | +#define GPIO_1_8V_E_INT_STATUS ((0x838 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 45 | +#define GPIO_1_8V_E_RESET_TOLERANT ((0x83C - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 46 | +#define GPIO_1_8V_ABCD_DEBOUNCE_1 ((0x840 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 47 | +#define GPIO_1_8V_ABCD_DEBOUNCE_2 ((0x844 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 48 | +#define GPIO_1_8V_E_DEBOUNCE_1 ((0x848 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 49 | +#define GPIO_1_8V_E_DEBOUNCE_2 ((0x84C - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 50 | +#define GPIO_1_8V_DEBOUNCE_TIME_1 ((0x850 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 51 | +#define GPIO_1_8V_DEBOUNCE_TIME_2 ((0x854 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 52 | +#define GPIO_1_8V_DEBOUNCE_TIME_3 ((0x858 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 53 | +#define GPIO_1_8V_ABCD_COMMAND_SRC_0 ((0x860 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 54 | +#define GPIO_1_8V_ABCD_COMMAND_SRC_1 ((0x864 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 55 | +#define GPIO_1_8V_E_COMMAND_SRC_0 ((0x868 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 56 | +#define GPIO_1_8V_E_COMMAND_SRC_1 ((0x86C - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 57 | +#define GPIO_1_8V_ABCD_DATA_READ ((0x8C0 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 58 | +#define GPIO_1_8V_E_DATA_READ ((0x8C4 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 59 | +#define GPIO_1_8V_ABCD_INPUT_MASK ((0x9D0 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 60 | +#define GPIO_1_8V_E_INPUT_MASK ((0x9D4 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 61 | +#define GPIO_1_8V_MEM_SIZE 0x9D8 | ||
| 62 | +#define GPIO_1_8V_REG_ARRAY_SIZE ((GPIO_1_8V_MEM_SIZE - \ | ||
| 63 | + GPIO_1_8V_REG_OFFSET) >> 2) | ||
| 64 | +#define GPIO_MAX_MEM_SIZE MAX(GPIO_3_6V_MEM_SIZE, GPIO_1_8V_MEM_SIZE) | ||
| 65 | + | ||
| 66 | static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio) | ||
| 67 | { | ||
| 68 | uint32_t falling_edge = 0, rising_edge = 0; | ||
| 69 | @@ -XXX,XX +XXX,XX @@ static const AspeedGPIOReg aspeed_3_6v_gpios[GPIO_3_6V_REG_ARRAY_SIZE] = { | ||
| 70 | [GPIO_AC_INPUT_MASK] = { 7, gpio_reg_input_mask }, | ||
| 71 | }; | ||
| 72 | |||
| 73 | +static const AspeedGPIOReg aspeed_1_8v_gpios[GPIO_1_8V_REG_ARRAY_SIZE] = { | ||
| 74 | + /* 1.8V Set ABCD */ | ||
| 75 | + [GPIO_1_8V_ABCD_DATA_VALUE] = {0, gpio_reg_data_value}, | ||
| 76 | + [GPIO_1_8V_ABCD_DIRECTION] = {0, gpio_reg_direction}, | ||
| 77 | + [GPIO_1_8V_ABCD_INT_ENABLE] = {0, gpio_reg_int_enable}, | ||
| 78 | + [GPIO_1_8V_ABCD_INT_SENS_0] = {0, gpio_reg_int_sens_0}, | ||
| 79 | + [GPIO_1_8V_ABCD_INT_SENS_1] = {0, gpio_reg_int_sens_1}, | ||
| 80 | + [GPIO_1_8V_ABCD_INT_SENS_2] = {0, gpio_reg_int_sens_2}, | ||
| 81 | + [GPIO_1_8V_ABCD_INT_STATUS] = {0, gpio_reg_int_status}, | ||
| 82 | + [GPIO_1_8V_ABCD_RESET_TOLERANT] = {0, gpio_reg_reset_tolerant}, | ||
| 83 | + [GPIO_1_8V_ABCD_DEBOUNCE_1] = {0, gpio_reg_debounce_1}, | ||
| 84 | + [GPIO_1_8V_ABCD_DEBOUNCE_2] = {0, gpio_reg_debounce_2}, | ||
| 85 | + [GPIO_1_8V_ABCD_COMMAND_SRC_0] = {0, gpio_reg_cmd_source_0}, | ||
| 86 | + [GPIO_1_8V_ABCD_COMMAND_SRC_1] = {0, gpio_reg_cmd_source_1}, | ||
| 87 | + [GPIO_1_8V_ABCD_DATA_READ] = {0, gpio_reg_data_read}, | ||
| 88 | + [GPIO_1_8V_ABCD_INPUT_MASK] = {0, gpio_reg_input_mask}, | ||
| 89 | + /* 1.8V Set E */ | ||
| 90 | + [GPIO_1_8V_E_DATA_VALUE] = {1, gpio_reg_data_value}, | ||
| 91 | + [GPIO_1_8V_E_DIRECTION] = {1, gpio_reg_direction}, | ||
| 92 | + [GPIO_1_8V_E_INT_ENABLE] = {1, gpio_reg_int_enable}, | ||
| 93 | + [GPIO_1_8V_E_INT_SENS_0] = {1, gpio_reg_int_sens_0}, | ||
| 94 | + [GPIO_1_8V_E_INT_SENS_1] = {1, gpio_reg_int_sens_1}, | ||
| 95 | + [GPIO_1_8V_E_INT_SENS_2] = {1, gpio_reg_int_sens_2}, | ||
| 96 | + [GPIO_1_8V_E_INT_STATUS] = {1, gpio_reg_int_status}, | ||
| 97 | + [GPIO_1_8V_E_RESET_TOLERANT] = {1, gpio_reg_reset_tolerant}, | ||
| 98 | + [GPIO_1_8V_E_DEBOUNCE_1] = {1, gpio_reg_debounce_1}, | ||
| 99 | + [GPIO_1_8V_E_DEBOUNCE_2] = {1, gpio_reg_debounce_2}, | ||
| 100 | + [GPIO_1_8V_E_COMMAND_SRC_0] = {1, gpio_reg_cmd_source_0}, | ||
| 101 | + [GPIO_1_8V_E_COMMAND_SRC_1] = {1, gpio_reg_cmd_source_1}, | ||
| 102 | + [GPIO_1_8V_E_DATA_READ] = {1, gpio_reg_data_read}, | ||
| 103 | + [GPIO_1_8V_E_INPUT_MASK] = {1, gpio_reg_input_mask}, | ||
| 104 | +}; | ||
| 105 | + | ||
| 106 | static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size) | ||
| 107 | { | ||
| 108 | AspeedGPIOState *s = ASPEED_GPIO(opaque); | ||
| 109 | @@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_get_pin(Object *obj, Visitor *v, const char *name, | ||
| 110 | int set_idx, group_idx = 0; | ||
| 111 | |||
| 112 | if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { | ||
| 113 | - error_setg(errp, "%s: error reading %s", __func__, name); | ||
| 114 | - return; | ||
| 115 | + /* 1.8V gpio */ | ||
| 116 | + if (sscanf(name, "gpio%3s%1d", group, &pin) != 2) { | ||
| 117 | + error_setg(errp, "%s: error reading %s", __func__, name); | ||
| 118 | + return; | ||
| 119 | + } | ||
| 120 | } | ||
| 121 | set_idx = get_set_idx(s, group, &group_idx); | ||
| 122 | if (set_idx == -1) { | ||
| 123 | @@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_set_pin(Object *obj, Visitor *v, const char *name, | ||
| 124 | return; | ||
| 125 | } | ||
| 126 | if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { | ||
| 127 | - error_setg(errp, "%s: error reading %s", __func__, name); | ||
| 128 | - return; | ||
| 129 | + /* 1.8V gpio */ | ||
| 130 | + if (sscanf(name, "gpio%3s%1d", group, &pin) != 2) { | ||
| 131 | + error_setg(errp, "%s: error reading %s", __func__, name); | ||
| 132 | + return; | ||
| 133 | + } | ||
| 134 | } | ||
| 135 | set_idx = get_set_idx(s, group, &group_idx); | ||
| 136 | if (set_idx == -1) { | ||
| 137 | @@ -XXX,XX +XXX,XX @@ static const GPIOSetProperties ast2500_set_props[] = { | ||
| 138 | [7] = {0x000000ff, 0x000000ff, {"AC"} }, | ||
| 139 | }; | ||
| 140 | |||
| 141 | +static GPIOSetProperties ast2600_3_6v_set_props[] = { | ||
| 142 | + [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, | ||
| 143 | + [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, | ||
| 144 | + [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, | ||
| 145 | + [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, | ||
| 146 | + [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} }, | ||
| 147 | + [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} }, | ||
| 148 | + [6] = {0xffff0000, 0x0fff0000, {"Y", "Z", "", ""} }, | ||
| 149 | +}; | ||
| 150 | + | ||
| 151 | +static GPIOSetProperties ast2600_1_8v_set_props[] = { | ||
| 152 | + [0] = {0xffffffff, 0xffffffff, {"18A", "18B", "18C", "18D"} }, | ||
| 153 | + [1] = {0x0000000f, 0x0000000f, {"18E"} }, | ||
| 154 | +}; | ||
| 155 | + | ||
| 156 | static const MemoryRegionOps aspeed_gpio_ops = { | ||
| 157 | .read = aspeed_gpio_read, | ||
| 158 | .write = aspeed_gpio_write, | ||
| 159 | @@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_realize(DeviceState *dev, Error **errp) | ||
| 160 | } | ||
| 161 | |||
| 162 | memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s, | ||
| 163 | - TYPE_ASPEED_GPIO, GPIO_3_6V_MEM_SIZE); | ||
| 164 | + TYPE_ASPEED_GPIO, GPIO_MAX_MEM_SIZE); | ||
| 165 | |||
| 166 | sysbus_init_mmio(sbd, &s->iomem); | ||
| 167 | } | ||
| 168 | @@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data) | ||
| 169 | agc->reg_table = aspeed_3_6v_gpios; | ||
| 170 | } | ||
| 171 | |||
| 172 | +static void aspeed_gpio_ast2600_3_6v_class_init(ObjectClass *klass, void *data) | ||
| 173 | +{ | ||
| 174 | + AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); | ||
| 175 | + | ||
| 176 | + agc->props = ast2600_3_6v_set_props; | ||
| 177 | + agc->nr_gpio_pins = 208; | ||
| 178 | + agc->nr_gpio_sets = 7; | ||
| 179 | + agc->reg_table = aspeed_3_6v_gpios; | ||
| 180 | +} | ||
| 181 | + | ||
| 182 | +static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *data) | ||
| 183 | +{ | ||
| 184 | + AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); | ||
| 185 | + | ||
| 186 | + agc->props = ast2600_1_8v_set_props; | ||
| 187 | + agc->nr_gpio_pins = 36; | ||
| 188 | + agc->nr_gpio_sets = 2; | ||
| 189 | + agc->reg_table = aspeed_1_8v_gpios; | ||
| 190 | +} | ||
| 191 | + | ||
| 192 | static const TypeInfo aspeed_gpio_info = { | ||
| 193 | .name = TYPE_ASPEED_GPIO, | ||
| 194 | .parent = TYPE_SYS_BUS_DEVICE, | ||
| 195 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_gpio_ast2500_info = { | ||
| 196 | .instance_init = aspeed_gpio_init, | ||
| 197 | }; | ||
| 198 | |||
| 199 | +static const TypeInfo aspeed_gpio_ast2600_3_6v_info = { | ||
| 200 | + .name = TYPE_ASPEED_GPIO "-ast2600", | ||
| 201 | + .parent = TYPE_ASPEED_GPIO, | ||
| 202 | + .class_init = aspeed_gpio_ast2600_3_6v_class_init, | ||
| 203 | + .instance_init = aspeed_gpio_init, | ||
| 204 | +}; | ||
| 205 | + | ||
| 206 | +static const TypeInfo aspeed_gpio_ast2600_1_8v_info = { | ||
| 207 | + .name = TYPE_ASPEED_GPIO "-ast2600-1_8v", | ||
| 208 | + .parent = TYPE_ASPEED_GPIO, | ||
| 209 | + .class_init = aspeed_gpio_ast2600_1_8v_class_init, | ||
| 210 | + .instance_init = aspeed_gpio_init, | ||
| 211 | +}; | ||
| 212 | + | ||
| 213 | static void aspeed_gpio_register_types(void) | ||
| 214 | { | ||
| 215 | type_register_static(&aspeed_gpio_info); | ||
| 216 | type_register_static(&aspeed_gpio_ast2400_info); | ||
| 217 | type_register_static(&aspeed_gpio_ast2500_info); | ||
| 218 | + type_register_static(&aspeed_gpio_ast2600_3_6v_info); | ||
| 219 | + type_register_static(&aspeed_gpio_ast2600_1_8v_info); | ||
| 220 | } | ||
| 221 | |||
| 222 | type_init(aspeed_gpio_register_types); | ||
| 223 | -- | 32 | -- |
| 224 | 2.20.1 | 33 | 2.34.1 |
| 225 | |||
| 226 | diff view generated by jsdifflib |
| 1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The AST2500 timer has a third control register that is used to | 3 | Now that float_status has a bunch of fp parameters, |
| 4 | implement a set-to-clear feature for the main control register. | 4 | it is easier to copy an existing structure than create |
| 5 | one from scratch. Begin by copying the structure that | ||
| 6 | corresponds to the FPSR and make only the adjustments | ||
| 7 | required for BFloat16 semantics. | ||
| 5 | 8 | ||
| 6 | This models the behaviour expected by the AST2500 while maintaining | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 7 | the same behaviour for the AST2400. | 10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 8 | 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | |
| 9 | The vmstate version is not increased yet because the structure is | 12 | Message-id: 20241203203949.483774-2-richard.henderson@linaro.org |
| 10 | modified again in the following patches. | ||
| 11 | |||
| 12 | Based on previous work from Joel Stanley. | ||
| 13 | |||
| 14 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 15 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
| 16 | Message-id: 20190925143248.10000-6-clg@kaod.org | ||
| 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 18 | --- | 14 | --- |
| 19 | include/hw/timer/aspeed_timer.h | 1 + | 15 | target/arm/tcg/vec_helper.c | 20 +++++++------------- |
| 20 | hw/timer/aspeed_timer.c | 19 +++++++++++++++++++ | 16 | 1 file changed, 7 insertions(+), 13 deletions(-) |
| 21 | 2 files changed, 20 insertions(+) | ||
| 22 | 17 | ||
| 23 | diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h | 18 | diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c |
| 24 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
| 25 | --- a/include/hw/timer/aspeed_timer.h | 20 | --- a/target/arm/tcg/vec_helper.c |
| 26 | +++ b/include/hw/timer/aspeed_timer.h | 21 | +++ b/target/arm/tcg/vec_helper.c |
| 27 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedTimerCtrlState { | 22 | @@ -XXX,XX +XXX,XX @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp) |
| 28 | 23 | * no effect on AArch32 instructions. | |
| 29 | uint32_t ctrl; | 24 | */ |
| 30 | uint32_t ctrl2; | 25 | bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF; |
| 31 | + uint32_t ctrl3; | 26 | - *statusp = (float_status){ |
| 32 | AspeedTimer timers[ASPEED_TIMER_NR_TIMERS]; | 27 | - .tininess_before_rounding = float_tininess_before_rounding, |
| 33 | 28 | - .float_rounding_mode = float_round_to_odd_inf, | |
| 34 | AspeedSCUState *scu; | 29 | - .flush_to_zero = true, |
| 35 | diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c | 30 | - .flush_inputs_to_zero = true, |
| 36 | index XXXXXXX..XXXXXXX 100644 | 31 | - .default_nan_mode = true, |
| 37 | --- a/hw/timer/aspeed_timer.c | 32 | - }; |
| 38 | +++ b/hw/timer/aspeed_timer.c | ||
| 39 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_2500_timer_read(AspeedTimerCtrlState *s, hwaddr offset) | ||
| 40 | |||
| 41 | switch (offset) { | ||
| 42 | case 0x38: | ||
| 43 | + value = s->ctrl3 & BIT(0); | ||
| 44 | + break; | ||
| 45 | case 0x3C: | ||
| 46 | default: | ||
| 47 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | ||
| 48 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_2500_timer_read(AspeedTimerCtrlState *s, hwaddr offset) | ||
| 49 | static void aspeed_2500_timer_write(AspeedTimerCtrlState *s, hwaddr offset, | ||
| 50 | uint64_t value) | ||
| 51 | { | ||
| 52 | + const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF); | ||
| 53 | + uint8_t command; | ||
| 54 | + | 33 | + |
| 55 | switch (offset) { | 34 | + *statusp = env->vfp.fp_status; |
| 56 | case 0x38: | 35 | + set_default_nan_mode(true, statusp); |
| 57 | + command = (value >> 1) & 0xFF; | 36 | |
| 58 | + if (command == 0xAE) { | 37 | if (ebf) { |
| 59 | + s->ctrl3 = 0x1; | 38 | - float_status *fpst = &env->vfp.fp_status; |
| 60 | + } else if (command == 0xEA) { | 39 | - set_flush_to_zero(get_flush_to_zero(fpst), statusp); |
| 61 | + s->ctrl3 = 0x0; | 40 | - set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp); |
| 62 | + } | 41 | - set_float_rounding_mode(get_float_rounding_mode(fpst), statusp); |
| 63 | + break; | 42 | - |
| 64 | case 0x3C: | 43 | /* EBF=1 needs to do a step with round-to-odd semantics */ |
| 65 | + if (s->ctrl3 & BIT(0)) { | 44 | *oddstatusp = *statusp; |
| 66 | + aspeed_timer_set_ctrl(s, s->ctrl & ~tv); | 45 | set_float_rounding_mode(float_round_to_odd, oddstatusp); |
| 67 | + } | 46 | + } else { |
| 68 | + break; | 47 | + set_flush_to_zero(true, statusp); |
| 69 | + | 48 | + set_flush_inputs_to_zero(true, statusp); |
| 70 | default: | 49 | + set_float_rounding_mode(float_round_to_odd_inf, statusp); |
| 71 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | ||
| 72 | __func__, offset); | ||
| 73 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_reset(DeviceState *dev) | ||
| 74 | } | 50 | } |
| 75 | s->ctrl = 0; | 51 | - |
| 76 | s->ctrl2 = 0; | 52 | return ebf; |
| 77 | + s->ctrl3 = 0; | ||
| 78 | } | 53 | } |
| 79 | 54 | ||
| 80 | static const VMStateDescription vmstate_aspeed_timer = { | ||
| 81 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_timer_state = { | ||
| 82 | .fields = (VMStateField[]) { | ||
| 83 | VMSTATE_UINT32(ctrl, AspeedTimerCtrlState), | ||
| 84 | VMSTATE_UINT32(ctrl2, AspeedTimerCtrlState), | ||
| 85 | + VMSTATE_UINT32(ctrl3, AspeedTimerCtrlState), | ||
| 86 | VMSTATE_STRUCT_ARRAY(timers, AspeedTimerCtrlState, | ||
| 87 | ASPEED_TIMER_NR_TIMERS, 1, vmstate_aspeed_timer, | ||
| 88 | AspeedTimer), | ||
| 89 | -- | 55 | -- |
| 90 | 2.20.1 | 56 | 2.34.1 |
| 91 | 57 | ||
| 92 | 58 | diff view generated by jsdifflib |
| 1 | Factor out the implementation of SYS_WRITE via the | 1 | Currently we hardcode the default NaN value in parts64_default_nan() |
|---|---|---|---|
| 2 | new function tables. | 2 | using a compile-time ifdef ladder. This is awkward for two cases: |
| 3 | * for single-QEMU-binary we can't hard-code target-specifics like this | ||
| 4 | * for Arm FEAT_AFP the default NaN value depends on FPCR.AH | ||
| 5 | (specifically the sign bit is different) | ||
| 6 | |||
| 7 | Add a field to float_status to specify the default NaN value; fall | ||
| 8 | back to the old ifdef behaviour if these are not set. | ||
| 9 | |||
| 10 | The default NaN value is specified by setting a uint8_t to a | ||
| 11 | pattern corresponding to the sign and upper fraction parts of | ||
| 12 | the NaN; the lower bits of the fraction are set from bit 0 of | ||
| 13 | the pattern. | ||
| 3 | 14 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 7 | Message-id: 20190916141544.17540-9-peter.maydell@linaro.org | 17 | Message-id: 20241202131347.498124-35-peter.maydell@linaro.org |
| 8 | --- | 18 | --- |
| 9 | target/arm/arm-semi.c | 51 ++++++++++++++++++++++++++++--------------- | 19 | include/fpu/softfloat-helpers.h | 11 +++++++ |
| 10 | 1 file changed, 33 insertions(+), 18 deletions(-) | 20 | include/fpu/softfloat-types.h | 10 ++++++ |
| 21 | fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++------------- | ||
| 22 | 3 files changed, 54 insertions(+), 22 deletions(-) | ||
| 11 | 23 | ||
| 12 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 24 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h |
| 13 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
| 14 | --- a/target/arm/arm-semi.c | 26 | --- a/include/fpu/softfloat-helpers.h |
| 15 | +++ b/target/arm/arm-semi.c | 27 | +++ b/include/fpu/softfloat-helpers.h |
| 16 | @@ -XXX,XX +XXX,XX @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, | 28 | @@ -XXX,XX +XXX,XX @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, |
| 17 | * setting the guest errno if appropriate. | 29 | status->float_infzeronan_rule = rule; |
| 18 | */ | ||
| 19 | typedef uint32_t sys_closefn(ARMCPU *cpu, GuestFD *gf); | ||
| 20 | +typedef uint32_t sys_writefn(ARMCPU *cpu, GuestFD *gf, | ||
| 21 | + target_ulong buf, uint32_t len); | ||
| 22 | |||
| 23 | static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) | ||
| 24 | { | ||
| 25 | @@ -XXX,XX +XXX,XX @@ static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) | ||
| 26 | return set_swi_errno(env, close(gf->hostfd)); | ||
| 27 | } | 30 | } |
| 28 | 31 | ||
| 29 | +static uint32_t host_writefn(ARMCPU *cpu, GuestFD *gf, | 32 | +static inline void set_float_default_nan_pattern(uint8_t dnan_pattern, |
| 30 | + target_ulong buf, uint32_t len) | 33 | + float_status *status) |
| 31 | +{ | 34 | +{ |
| 32 | + uint32_t ret; | 35 | + status->default_nan_pattern = dnan_pattern; |
| 33 | + CPUARMState *env = &cpu->env; | ||
| 34 | + char *s = lock_user(VERIFY_READ, buf, len, 1); | ||
| 35 | + if (!s) { | ||
| 36 | + /* Return bytes not written on error */ | ||
| 37 | + return len; | ||
| 38 | + } | ||
| 39 | + ret = set_swi_errno(env, write(gf->hostfd, s, len)); | ||
| 40 | + unlock_user(s, buf, 0); | ||
| 41 | + if (ret == (uint32_t)-1) { | ||
| 42 | + ret = 0; | ||
| 43 | + } | ||
| 44 | + /* Return bytes not written */ | ||
| 45 | + return len - ret; | ||
| 46 | +} | 36 | +} |
| 47 | + | 37 | + |
| 48 | static uint32_t gdb_closefn(ARMCPU *cpu, GuestFD *gf) | 38 | static inline void set_flush_to_zero(bool val, float_status *status) |
| 49 | { | 39 | { |
| 50 | return arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); | 40 | status->flush_to_zero = val; |
| 41 | @@ -XXX,XX +XXX,XX @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status | ||
| 42 | return status->float_infzeronan_rule; | ||
| 51 | } | 43 | } |
| 52 | 44 | ||
| 53 | +static uint32_t gdb_writefn(ARMCPU *cpu, GuestFD *gf, | 45 | +static inline uint8_t get_float_default_nan_pattern(float_status *status) |
| 54 | + target_ulong buf, uint32_t len) | ||
| 55 | +{ | 46 | +{ |
| 56 | + arm_semi_syscall_len = len; | 47 | + return status->default_nan_pattern; |
| 57 | + return arm_gdb_syscall(cpu, arm_semi_cb, "write,%x,%x,%x", | ||
| 58 | + gf->hostfd, buf, len); | ||
| 59 | +} | 48 | +} |
| 60 | + | 49 | + |
| 61 | typedef struct GuestFDFunctions { | 50 | static inline bool get_flush_to_zero(float_status *status) |
| 62 | sys_closefn *closefn; | 51 | { |
| 63 | + sys_writefn *writefn; | 52 | return status->flush_to_zero; |
| 64 | } GuestFDFunctions; | 53 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h |
| 65 | 54 | index XXXXXXX..XXXXXXX 100644 | |
| 66 | static const GuestFDFunctions guestfd_fns[] = { | 55 | --- a/include/fpu/softfloat-types.h |
| 67 | [GuestFDHost] = { | 56 | +++ b/include/fpu/softfloat-types.h |
| 68 | .closefn = host_closefn, | 57 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { |
| 69 | + .writefn = host_writefn, | 58 | /* should denormalised inputs go to zero and set the input_denormal flag? */ |
| 70 | }, | 59 | bool flush_inputs_to_zero; |
| 71 | [GuestFDGDB] = { | 60 | bool default_nan_mode; |
| 72 | .closefn = gdb_closefn, | 61 | + /* |
| 73 | + .writefn = gdb_writefn, | 62 | + * The pattern to use for the default NaN. Here the high bit specifies |
| 74 | }, | 63 | + * the default NaN's sign bit, and bits 6..0 specify the high bits of the |
| 75 | }; | 64 | + * fractional part. The low bits of the fractional part are copies of bit 0. |
| 76 | 65 | + * The exponent of the default NaN is (as for any NaN) always all 1s. | |
| 77 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | 66 | + * Note that a value of 0 here is not a valid NaN. The target must set |
| 78 | return set_swi_errno(env, -1); | 67 | + * this to the correct non-zero value, or we will assert when trying to |
| 79 | } | 68 | + * create a default NaN. |
| 80 | 69 | + */ | |
| 81 | - if (use_gdb_syscalls()) { | 70 | + uint8_t default_nan_pattern; |
| 82 | - arm_semi_syscall_len = len; | 71 | /* |
| 83 | - return arm_gdb_syscall(cpu, arm_semi_cb, "write,%x,%x,%x", | 72 | * The flags below are not used on all specializations and may |
| 84 | - gf->hostfd, arg1, len); | 73 | * constant fold away (see snan_bit_is_one()/no_signalling_nans() in |
| 85 | - } else { | 74 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 86 | - s = lock_user(VERIFY_READ, arg1, len, 1); | 75 | index XXXXXXX..XXXXXXX 100644 |
| 87 | - if (!s) { | 76 | --- a/fpu/softfloat-specialize.c.inc |
| 88 | - /* Return bytes not written on error */ | 77 | +++ b/fpu/softfloat-specialize.c.inc |
| 89 | - return len; | 78 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) |
| 90 | - } | 79 | { |
| 91 | - ret = set_swi_errno(env, write(gf->hostfd, s, len)); | 80 | bool sign = 0; |
| 92 | - unlock_user(s, arg1, 0); | 81 | uint64_t frac; |
| 93 | - if (ret == (uint32_t)-1) { | 82 | + uint8_t dnan_pattern = status->default_nan_pattern; |
| 94 | - ret = 0; | 83 | |
| 95 | - } | 84 | + if (dnan_pattern == 0) { |
| 96 | - /* Return bytes not written */ | 85 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) |
| 97 | - return len - ret; | 86 | - /* !snan_bit_is_one, set all bits */ |
| 98 | - } | 87 | - frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; |
| 99 | + return guestfd_fns[gf->type].writefn(cpu, gf, arg1, len); | 88 | -#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ |
| 100 | case TARGET_SYS_READ: | 89 | + /* Sign bit clear, all frac bits set */ |
| 101 | GET_ARG(0); | 90 | + dnan_pattern = 0b01111111; |
| 102 | GET_ARG(1); | 91 | +#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ |
| 92 | || defined(TARGET_MICROBLAZE) | ||
| 93 | - /* !snan_bit_is_one, set sign and msb */ | ||
| 94 | - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); | ||
| 95 | - sign = 1; | ||
| 96 | + /* Sign bit set, most significant frac bit set */ | ||
| 97 | + dnan_pattern = 0b11000000; | ||
| 98 | #elif defined(TARGET_HPPA) | ||
| 99 | - /* snan_bit_is_one, set msb-1. */ | ||
| 100 | - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); | ||
| 101 | + /* Sign bit clear, msb-1 frac bit set */ | ||
| 102 | + dnan_pattern = 0b00100000; | ||
| 103 | #elif defined(TARGET_HEXAGON) | ||
| 104 | - sign = 1; | ||
| 105 | - frac = ~0ULL; | ||
| 106 | + /* Sign bit set, all frac bits set. */ | ||
| 107 | + dnan_pattern = 0b11111111; | ||
| 108 | #else | ||
| 109 | - /* | ||
| 110 | - * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, | ||
| 111 | - * S390, SH4, TriCore, and Xtensa. Our other supported targets | ||
| 112 | - * do not have floating-point. | ||
| 113 | - */ | ||
| 114 | - if (snan_bit_is_one(status)) { | ||
| 115 | - /* set all bits other than msb */ | ||
| 116 | - frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; | ||
| 117 | - } else { | ||
| 118 | - /* set msb */ | ||
| 119 | - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); | ||
| 120 | - } | ||
| 121 | + /* | ||
| 122 | + * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, | ||
| 123 | + * S390, SH4, TriCore, and Xtensa. Our other supported targets | ||
| 124 | + * do not have floating-point. | ||
| 125 | + */ | ||
| 126 | + if (snan_bit_is_one(status)) { | ||
| 127 | + /* sign bit clear, set all frac bits other than msb */ | ||
| 128 | + dnan_pattern = 0b00111111; | ||
| 129 | + } else { | ||
| 130 | + /* sign bit clear, set frac msb */ | ||
| 131 | + dnan_pattern = 0b01000000; | ||
| 132 | + } | ||
| 133 | #endif | ||
| 134 | + } | ||
| 135 | + assert(dnan_pattern != 0); | ||
| 136 | + | ||
| 137 | + sign = dnan_pattern >> 7; | ||
| 138 | + /* | ||
| 139 | + * Place default_nan_pattern [6:0] into bits [62:56], | ||
| 140 | + * and replecate bit [0] down into [55:0] | ||
| 141 | + */ | ||
| 142 | + frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern); | ||
| 143 | + frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1)); | ||
| 144 | |||
| 145 | *p = (FloatParts64) { | ||
| 146 | .cls = float_class_qnan, | ||
| 103 | -- | 147 | -- |
| 104 | 2.20.1 | 148 | 2.34.1 |
| 105 | |||
| 106 | diff view generated by jsdifflib |
| 1 | Switch the musicpal code away from bottom-half based ptimers to | 1 | Set the default NaN pattern explicitly for the tests/fp code. |
|---|---|---|---|
| 2 | the new transaction-based ptimer API. This just requires adding | ||
| 3 | begin/commit calls around the various places that modify the ptimer | ||
| 4 | state, and using the new ptimer_init() function to create the timer. | ||
| 5 | 2 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Message-id: 20191008171740.9679-6-peter.maydell@linaro.org | 5 | Message-id: 20241202131347.498124-36-peter.maydell@linaro.org |
| 9 | --- | 6 | --- |
| 10 | hw/arm/musicpal.c | 16 ++++++++++------ | 7 | tests/fp/fp-bench.c | 1 + |
| 11 | 1 file changed, 10 insertions(+), 6 deletions(-) | 8 | tests/fp/fp-test-log2.c | 1 + |
| 9 | tests/fp/fp-test.c | 1 + | ||
| 10 | 3 files changed, 3 insertions(+) | ||
| 12 | 11 | ||
| 13 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c | 12 | diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c |
| 14 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/hw/arm/musicpal.c | 14 | --- a/tests/fp/fp-bench.c |
| 16 | +++ b/hw/arm/musicpal.c | 15 | +++ b/tests/fp/fp-bench.c |
| 17 | @@ -XXX,XX +XXX,XX @@ static void mv88w8618_timer_tick(void *opaque) | 16 | @@ -XXX,XX +XXX,XX @@ static void run_bench(void) |
| 18 | static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, | 17 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); |
| 19 | uint32_t freq) | 18 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status); |
| 20 | { | 19 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); |
| 21 | - QEMUBH *bh; | 20 | + set_float_default_nan_pattern(0b01000000, &soft_status); |
| 22 | - | 21 | |
| 23 | sysbus_init_irq(dev, &s->irq); | 22 | f = bench_funcs[operation][precision]; |
| 24 | s->freq = freq; | 23 | g_assert(f); |
| 25 | 24 | diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c | |
| 26 | - bh = qemu_bh_new(mv88w8618_timer_tick, s); | 25 | index XXXXXXX..XXXXXXX 100644 |
| 27 | - s->ptimer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | 26 | --- a/tests/fp/fp-test-log2.c |
| 28 | + s->ptimer = ptimer_init(mv88w8618_timer_tick, s, PTIMER_POLICY_DEFAULT); | 27 | +++ b/tests/fp/fp-test-log2.c |
| 29 | } | 28 | @@ -XXX,XX +XXX,XX @@ int main(int ac, char **av) |
| 30 | |||
| 31 | static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset, | ||
| 32 | @@ -XXX,XX +XXX,XX @@ static void mv88w8618_pit_write(void *opaque, hwaddr offset, | ||
| 33 | case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH: | ||
| 34 | t = &s->timer[offset >> 2]; | ||
| 35 | t->limit = value; | ||
| 36 | + ptimer_transaction_begin(t->ptimer); | ||
| 37 | if (t->limit > 0) { | ||
| 38 | ptimer_set_limit(t->ptimer, t->limit, 1); | ||
| 39 | } else { | ||
| 40 | ptimer_stop(t->ptimer); | ||
| 41 | } | ||
| 42 | + ptimer_transaction_commit(t->ptimer); | ||
| 43 | break; | ||
| 44 | |||
| 45 | case MP_PIT_CONTROL: | ||
| 46 | for (i = 0; i < 4; i++) { | ||
| 47 | t = &s->timer[i]; | ||
| 48 | + ptimer_transaction_begin(t->ptimer); | ||
| 49 | if (value & 0xf && t->limit > 0) { | ||
| 50 | ptimer_set_limit(t->ptimer, t->limit, 0); | ||
| 51 | ptimer_set_freq(t->ptimer, t->freq); | ||
| 52 | @@ -XXX,XX +XXX,XX @@ static void mv88w8618_pit_write(void *opaque, hwaddr offset, | ||
| 53 | } else { | ||
| 54 | ptimer_stop(t->ptimer); | ||
| 55 | } | ||
| 56 | + ptimer_transaction_commit(t->ptimer); | ||
| 57 | value >>= 4; | ||
| 58 | } | ||
| 59 | break; | ||
| 60 | @@ -XXX,XX +XXX,XX @@ static void mv88w8618_pit_reset(DeviceState *d) | ||
| 61 | int i; | 29 | int i; |
| 62 | 30 | ||
| 63 | for (i = 0; i < 4; i++) { | 31 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); |
| 64 | - ptimer_stop(s->timer[i].ptimer); | 32 | + set_float_default_nan_pattern(0b01000000, &qsf); |
| 65 | - s->timer[i].limit = 0; | 33 | set_float_rounding_mode(float_round_nearest_even, &qsf); |
| 66 | + mv88w8618_timer_state *t = &s->timer[i]; | 34 | |
| 67 | + ptimer_transaction_begin(t->ptimer); | 35 | test.d = 0.0; |
| 68 | + ptimer_stop(t->ptimer); | 36 | diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c |
| 69 | + ptimer_transaction_commit(t->ptimer); | 37 | index XXXXXXX..XXXXXXX 100644 |
| 70 | + t->limit = 0; | 38 | --- a/tests/fp/fp-test.c |
| 71 | } | 39 | +++ b/tests/fp/fp-test.c |
| 72 | } | 40 | @@ -XXX,XX +XXX,XX @@ void run_test(void) |
| 73 | 41 | */ | |
| 42 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); | ||
| 43 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf); | ||
| 44 | + set_float_default_nan_pattern(0b01000000, &qsf); | ||
| 45 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); | ||
| 46 | |||
| 47 | genCases_setLevel(test_level); | ||
| 74 | -- | 48 | -- |
| 75 | 2.20.1 | 49 | 2.34.1 |
| 76 | |||
| 77 | diff view generated by jsdifflib |
| 1 | SH_EXT_STDOUT_STDERR is a v2.0 semihosting extension: the guest | 1 | Set the default NaN pattern explicitly, and remove the ifdef from |
|---|---|---|---|
| 2 | can open ":tt" with a file mode requesting append access in | 2 | parts64_default_nan(). |
| 3 | order to open stderr, in addition to the existing "open for | ||
| 4 | read for stdin or write for stdout". Implement this and | ||
| 5 | report it via the :semihosting-features data. | ||
| 6 | 3 | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 8 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 9 | Message-id: 20190916141544.17540-16-peter.maydell@linaro.org | 6 | Message-id: 20241202131347.498124-37-peter.maydell@linaro.org |
| 10 | --- | 7 | --- |
| 11 | target/arm/arm-semi.c | 19 +++++++++++++++++-- | 8 | target/microblaze/cpu.c | 2 ++ |
| 12 | 1 file changed, 17 insertions(+), 2 deletions(-) | 9 | fpu/softfloat-specialize.c.inc | 3 +-- |
| 10 | 2 files changed, 3 insertions(+), 2 deletions(-) | ||
| 13 | 11 | ||
| 14 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 12 | diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c |
| 15 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/target/arm/arm-semi.c | 14 | --- a/target/microblaze/cpu.c |
| 17 | +++ b/target/arm/arm-semi.c | 15 | +++ b/target/microblaze/cpu.c |
| 18 | @@ -XXX,XX +XXX,XX @@ static uint32_t gdb_flenfn(ARMCPU *cpu, GuestFD *gf) | 16 | @@ -XXX,XX +XXX,XX @@ static void mb_cpu_reset_hold(Object *obj, ResetType type) |
| 19 | 17 | * this architecture. | |
| 20 | /* Feature bits reportable in feature byte 0 */ | 18 | */ |
| 21 | #define SH_EXT_EXIT_EXTENDED (1 << 0) | 19 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); |
| 22 | +#define SH_EXT_STDOUT_STDERR (1 << 1) | 20 | + /* Default NaN: sign bit set, most significant frac bit set */ |
| 23 | 21 | + set_float_default_nan_pattern(0b11000000, &env->fp_status); | |
| 24 | static const uint8_t featurefile_data[] = { | 22 | |
| 25 | SHFB_MAGIC_0, | 23 | #if defined(CONFIG_USER_ONLY) |
| 26 | SHFB_MAGIC_1, | 24 | /* start in user mode with interrupts enabled. */ |
| 27 | SHFB_MAGIC_2, | 25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 28 | SHFB_MAGIC_3, | 26 | index XXXXXXX..XXXXXXX 100644 |
| 29 | - SH_EXT_EXIT_EXTENDED, /* Feature byte 0 */ | 27 | --- a/fpu/softfloat-specialize.c.inc |
| 30 | + SH_EXT_EXIT_EXTENDED | SH_EXT_STDOUT_STDERR, /* Feature byte 0 */ | 28 | +++ b/fpu/softfloat-specialize.c.inc |
| 31 | }; | 29 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) |
| 32 | 30 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | |
| 33 | static void init_featurefile_guestfd(int guestfd) | 31 | /* Sign bit clear, all frac bits set */ |
| 34 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | 32 | dnan_pattern = 0b01111111; |
| 35 | } | 33 | -#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ |
| 36 | 34 | - || defined(TARGET_MICROBLAZE) | |
| 37 | if (strcmp(s, ":tt") == 0) { | 35 | +#elif defined(TARGET_I386) || defined(TARGET_X86_64) |
| 38 | - int result_fileno = arg1 < 4 ? STDIN_FILENO : STDOUT_FILENO; | 36 | /* Sign bit set, most significant frac bit set */ |
| 39 | + int result_fileno; | 37 | dnan_pattern = 0b11000000; |
| 40 | + | 38 | #elif defined(TARGET_HPPA) |
| 41 | + /* | ||
| 42 | + * We implement SH_EXT_STDOUT_STDERR, so: | ||
| 43 | + * open for read == stdin | ||
| 44 | + * open for write == stdout | ||
| 45 | + * open for append == stderr | ||
| 46 | + */ | ||
| 47 | + if (arg1 < 4) { | ||
| 48 | + result_fileno = STDIN_FILENO; | ||
| 49 | + } else if (arg1 < 8) { | ||
| 50 | + result_fileno = STDOUT_FILENO; | ||
| 51 | + } else { | ||
| 52 | + result_fileno = STDERR_FILENO; | ||
| 53 | + } | ||
| 54 | associate_guestfd(guestfd, result_fileno); | ||
| 55 | unlock_user(s, arg0, 0); | ||
| 56 | return guestfd; | ||
| 57 | -- | 39 | -- |
| 58 | 2.20.1 | 40 | 2.34.1 |
| 59 | |||
| 60 | diff view generated by jsdifflib |
| 1 | Currently the Arm semihosting code returns the guest file descriptors | 1 | Set the default NaN pattern explicitly, and remove the ifdef from |
|---|---|---|---|
| 2 | (handles) which are simply the fd values from the host OS or the | 2 | parts64_default_nan(). |
| 3 | remote gdbstub. Part of the semihosting 2.0 specification requires | ||
| 4 | that we implement special handling of opening a ":semihosting-features" | ||
| 5 | filename. Guest fds which result from opening the special file | ||
| 6 | won't correspond to host fds, so to ensure that we don't end up | ||
| 7 | with duplicate fds we need to have QEMU code control the allocation | ||
| 8 | of the fd values we give the guest. | ||
| 9 | |||
| 10 | Add in an abstraction layer which lets us allocate new guest FD | ||
| 11 | values, and translate from a guest FD value back to the host one. | ||
| 12 | This also fixes an odd hole where a semihosting guest could | ||
| 13 | use the semihosting API to read, write or close file descriptors | ||
| 14 | that it had never allocated but which were being used by QEMU itself. | ||
| 15 | (This isn't a security hole, because enabling semihosting permits | ||
| 16 | the guest to do arbitrary file access to the whole host filesystem, | ||
| 17 | and so should only be done if the guest is completely trusted.) | ||
| 18 | |||
| 19 | Currently the only kind of guest fd is one which maps to a | ||
| 20 | host fd, but in a following commit we will add one which maps | ||
| 21 | to the :semihosting-features magic data. | ||
| 22 | |||
| 23 | If the guest is migrated with an open semihosting file descriptor | ||
| 24 | then subsequent attempts to use the fd will all fail; this is | ||
| 25 | not a change from the previous situation (where the host fd | ||
| 26 | being used on the source end would not be re-opened on the | ||
| 27 | destination end). | ||
| 28 | 3 | ||
| 29 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 30 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 31 | Message-id: 20190916141544.17540-5-peter.maydell@linaro.org | 6 | Message-id: 20241202131347.498124-38-peter.maydell@linaro.org |
| 32 | --- | 7 | --- |
| 33 | target/arm/arm-semi.c | 232 +++++++++++++++++++++++++++++++++++++++--- | 8 | target/i386/tcg/fpu_helper.c | 4 ++++ |
| 34 | 1 file changed, 216 insertions(+), 16 deletions(-) | 9 | fpu/softfloat-specialize.c.inc | 3 --- |
| 10 | 2 files changed, 4 insertions(+), 3 deletions(-) | ||
| 35 | 11 | ||
| 36 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 12 | diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c |
| 37 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 38 | --- a/target/arm/arm-semi.c | 14 | --- a/target/i386/tcg/fpu_helper.c |
| 39 | +++ b/target/arm/arm-semi.c | 15 | +++ b/target/i386/tcg/fpu_helper.c |
| 40 | @@ -XXX,XX +XXX,XX @@ static int open_modeflags[12] = { | 16 | @@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env) |
| 41 | O_RDWR | O_CREAT | O_APPEND | O_BINARY | 17 | */ |
| 42 | }; | 18 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); |
| 43 | 19 | set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); | |
| 44 | +typedef enum GuestFDType { | 20 | + /* Default NaN: sign bit set, most significant frac bit set */ |
| 45 | + GuestFDUnused = 0, | 21 | + set_float_default_nan_pattern(0b11000000, &env->fp_status); |
| 46 | + GuestFDHost = 1, | 22 | + set_float_default_nan_pattern(0b11000000, &env->mmx_status); |
| 47 | +} GuestFDType; | 23 | + set_float_default_nan_pattern(0b11000000, &env->sse_status); |
| 48 | + | ||
| 49 | +/* | ||
| 50 | + * Guest file descriptors are integer indexes into an array of | ||
| 51 | + * these structures (we will dynamically resize as necessary). | ||
| 52 | + */ | ||
| 53 | +typedef struct GuestFD { | ||
| 54 | + GuestFDType type; | ||
| 55 | + int hostfd; | ||
| 56 | +} GuestFD; | ||
| 57 | + | ||
| 58 | +static GArray *guestfd_array; | ||
| 59 | + | ||
| 60 | +/* | ||
| 61 | + * Allocate a new guest file descriptor and return it; if we | ||
| 62 | + * couldn't allocate a new fd then return -1. | ||
| 63 | + * This is a fairly simplistic implementation because we don't | ||
| 64 | + * expect that most semihosting guest programs will make very | ||
| 65 | + * heavy use of opening and closing fds. | ||
| 66 | + */ | ||
| 67 | +static int alloc_guestfd(void) | ||
| 68 | +{ | ||
| 69 | + guint i; | ||
| 70 | + | ||
| 71 | + if (!guestfd_array) { | ||
| 72 | + /* New entries zero-initialized, i.e. type GuestFDUnused */ | ||
| 73 | + guestfd_array = g_array_new(FALSE, TRUE, sizeof(GuestFD)); | ||
| 74 | + } | ||
| 75 | + | ||
| 76 | + for (i = 0; i < guestfd_array->len; i++) { | ||
| 77 | + GuestFD *gf = &g_array_index(guestfd_array, GuestFD, i); | ||
| 78 | + | ||
| 79 | + if (gf->type == GuestFDUnused) { | ||
| 80 | + return i; | ||
| 81 | + } | ||
| 82 | + } | ||
| 83 | + | ||
| 84 | + /* All elements already in use: expand the array */ | ||
| 85 | + g_array_set_size(guestfd_array, i + 1); | ||
| 86 | + return i; | ||
| 87 | +} | ||
| 88 | + | ||
| 89 | +/* | ||
| 90 | + * Look up the guestfd in the data structure; return NULL | ||
| 91 | + * for out of bounds, but don't check whether the slot is unused. | ||
| 92 | + * This is used internally by the other guestfd functions. | ||
| 93 | + */ | ||
| 94 | +static GuestFD *do_get_guestfd(int guestfd) | ||
| 95 | +{ | ||
| 96 | + if (!guestfd_array) { | ||
| 97 | + return NULL; | ||
| 98 | + } | ||
| 99 | + | ||
| 100 | + if (guestfd < 0 || guestfd >= guestfd_array->len) { | ||
| 101 | + return NULL; | ||
| 102 | + } | ||
| 103 | + | ||
| 104 | + return &g_array_index(guestfd_array, GuestFD, guestfd); | ||
| 105 | +} | ||
| 106 | + | ||
| 107 | +/* | ||
| 108 | + * Associate the specified guest fd (which must have been | ||
| 109 | + * allocated via alloc_fd() and not previously used) with | ||
| 110 | + * the specified host fd. | ||
| 111 | + */ | ||
| 112 | +static void associate_guestfd(int guestfd, int hostfd) | ||
| 113 | +{ | ||
| 114 | + GuestFD *gf = do_get_guestfd(guestfd); | ||
| 115 | + | ||
| 116 | + assert(gf); | ||
| 117 | + gf->type = GuestFDHost; | ||
| 118 | + gf->hostfd = hostfd; | ||
| 119 | +} | ||
| 120 | + | ||
| 121 | +/* | ||
| 122 | + * Deallocate the specified guest file descriptor. This doesn't | ||
| 123 | + * close the host fd, it merely undoes the work of alloc_fd(). | ||
| 124 | + */ | ||
| 125 | +static void dealloc_guestfd(int guestfd) | ||
| 126 | +{ | ||
| 127 | + GuestFD *gf = do_get_guestfd(guestfd); | ||
| 128 | + | ||
| 129 | + assert(gf); | ||
| 130 | + gf->type = GuestFDUnused; | ||
| 131 | +} | ||
| 132 | + | ||
| 133 | +/* | ||
| 134 | + * Given a guest file descriptor, get the associated struct. | ||
| 135 | + * If the fd is not valid, return NULL. This is the function | ||
| 136 | + * used by the various semihosting calls to validate a handle | ||
| 137 | + * from the guest. | ||
| 138 | + * Note: calling alloc_guestfd() or dealloc_guestfd() will | ||
| 139 | + * invalidate any GuestFD* obtained by calling this function. | ||
| 140 | + */ | ||
| 141 | +static GuestFD *get_guestfd(int guestfd) | ||
| 142 | +{ | ||
| 143 | + GuestFD *gf = do_get_guestfd(guestfd); | ||
| 144 | + | ||
| 145 | + if (!gf || gf->type == GuestFDUnused) { | ||
| 146 | + return NULL; | ||
| 147 | + } | ||
| 148 | + return gf; | ||
| 149 | +} | ||
| 150 | + | ||
| 151 | #ifdef CONFIG_USER_ONLY | ||
| 152 | static inline uint32_t set_swi_errno(TaskState *ts, uint32_t code) | ||
| 153 | { | ||
| 154 | @@ -XXX,XX +XXX,XX @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) | ||
| 155 | #endif | ||
| 156 | } | 24 | } |
| 157 | 25 | ||
| 158 | +static int arm_semi_open_guestfd; | 26 | static inline uint8_t save_exception_flags(CPUX86State *env) |
| 159 | + | 27 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 160 | +static void arm_semi_open_cb(CPUState *cs, target_ulong ret, target_ulong err) | 28 | index XXXXXXX..XXXXXXX 100644 |
| 161 | +{ | 29 | --- a/fpu/softfloat-specialize.c.inc |
| 162 | + ARMCPU *cpu = ARM_CPU(cs); | 30 | +++ b/fpu/softfloat-specialize.c.inc |
| 163 | + CPUARMState *env = &cpu->env; | 31 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) |
| 164 | +#ifdef CONFIG_USER_ONLY | 32 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) |
| 165 | + TaskState *ts = cs->opaque; | 33 | /* Sign bit clear, all frac bits set */ |
| 166 | +#endif | 34 | dnan_pattern = 0b01111111; |
| 167 | + if (ret == (target_ulong)-1) { | 35 | -#elif defined(TARGET_I386) || defined(TARGET_X86_64) |
| 168 | +#ifdef CONFIG_USER_ONLY | 36 | - /* Sign bit set, most significant frac bit set */ |
| 169 | + ts->swi_errno = err; | 37 | - dnan_pattern = 0b11000000; |
| 170 | +#else | 38 | #elif defined(TARGET_HPPA) |
| 171 | + syscall_err = err; | 39 | /* Sign bit clear, msb-1 frac bit set */ |
| 172 | +#endif | 40 | dnan_pattern = 0b00100000; |
| 173 | + dealloc_guestfd(arm_semi_open_guestfd); | ||
| 174 | + } else { | ||
| 175 | + associate_guestfd(arm_semi_open_guestfd, ret); | ||
| 176 | + ret = arm_semi_open_guestfd; | ||
| 177 | + } | ||
| 178 | + | ||
| 179 | + if (is_a64(env)) { | ||
| 180 | + env->xregs[0] = ret; | ||
| 181 | + } else { | ||
| 182 | + env->regs[0] = ret; | ||
| 183 | + } | ||
| 184 | +} | ||
| 185 | + | ||
| 186 | static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, | ||
| 187 | const char *fmt, ...) | ||
| 188 | { | ||
| 189 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 190 | #else | ||
| 191 | CPUARMState *ts = env; | ||
| 192 | #endif | ||
| 193 | + GuestFD *gf; | ||
| 194 | |||
| 195 | if (is_a64(env)) { | ||
| 196 | /* Note that the syscall number is in W0, not X0 */ | ||
| 197 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 198 | |||
| 199 | switch (nr) { | ||
| 200 | case TARGET_SYS_OPEN: | ||
| 201 | + { | ||
| 202 | + int guestfd; | ||
| 203 | + | ||
| 204 | GET_ARG(0); | ||
| 205 | GET_ARG(1); | ||
| 206 | GET_ARG(2); | ||
| 207 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 208 | errno = EINVAL; | ||
| 209 | return set_swi_errno(ts, -1); | ||
| 210 | } | ||
| 211 | + | ||
| 212 | + guestfd = alloc_guestfd(); | ||
| 213 | + if (guestfd < 0) { | ||
| 214 | + unlock_user(s, arg0, 0); | ||
| 215 | + errno = EMFILE; | ||
| 216 | + return set_swi_errno(ts, -1); | ||
| 217 | + } | ||
| 218 | + | ||
| 219 | if (strcmp(s, ":tt") == 0) { | ||
| 220 | int result_fileno = arg1 < 4 ? STDIN_FILENO : STDOUT_FILENO; | ||
| 221 | + associate_guestfd(guestfd, result_fileno); | ||
| 222 | unlock_user(s, arg0, 0); | ||
| 223 | - return result_fileno; | ||
| 224 | + return guestfd; | ||
| 225 | } | ||
| 226 | if (use_gdb_syscalls()) { | ||
| 227 | - ret = arm_gdb_syscall(cpu, arm_semi_cb, "open,%s,%x,1a4", arg0, | ||
| 228 | + arm_semi_open_guestfd = guestfd; | ||
| 229 | + ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0, | ||
| 230 | (int)arg2+1, gdb_open_modeflags[arg1]); | ||
| 231 | } else { | ||
| 232 | ret = set_swi_errno(ts, open(s, open_modeflags[arg1], 0644)); | ||
| 233 | + if (ret == (uint32_t)-1) { | ||
| 234 | + dealloc_guestfd(guestfd); | ||
| 235 | + } else { | ||
| 236 | + associate_guestfd(guestfd, ret); | ||
| 237 | + ret = guestfd; | ||
| 238 | + } | ||
| 239 | } | ||
| 240 | unlock_user(s, arg0, 0); | ||
| 241 | return ret; | ||
| 242 | + } | ||
| 243 | case TARGET_SYS_CLOSE: | ||
| 244 | GET_ARG(0); | ||
| 245 | - if (use_gdb_syscalls()) { | ||
| 246 | - return arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", arg0); | ||
| 247 | - } else { | ||
| 248 | - return set_swi_errno(ts, close(arg0)); | ||
| 249 | + | ||
| 250 | + gf = get_guestfd(arg0); | ||
| 251 | + if (!gf) { | ||
| 252 | + errno = EBADF; | ||
| 253 | + return set_swi_errno(ts, -1); | ||
| 254 | } | ||
| 255 | + | ||
| 256 | + if (use_gdb_syscalls()) { | ||
| 257 | + ret = arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); | ||
| 258 | + } else { | ||
| 259 | + ret = set_swi_errno(ts, close(gf->hostfd)); | ||
| 260 | + } | ||
| 261 | + dealloc_guestfd(arg0); | ||
| 262 | + return ret; | ||
| 263 | case TARGET_SYS_WRITEC: | ||
| 264 | qemu_semihosting_console_outc(env, args); | ||
| 265 | return 0xdeadbeef; | ||
| 266 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 267 | GET_ARG(1); | ||
| 268 | GET_ARG(2); | ||
| 269 | len = arg2; | ||
| 270 | + | ||
| 271 | + gf = get_guestfd(arg0); | ||
| 272 | + if (!gf) { | ||
| 273 | + errno = EBADF; | ||
| 274 | + return set_swi_errno(ts, -1); | ||
| 275 | + } | ||
| 276 | + | ||
| 277 | if (use_gdb_syscalls()) { | ||
| 278 | arm_semi_syscall_len = len; | ||
| 279 | return arm_gdb_syscall(cpu, arm_semi_cb, "write,%x,%x,%x", | ||
| 280 | - arg0, arg1, len); | ||
| 281 | + gf->hostfd, arg1, len); | ||
| 282 | } else { | ||
| 283 | s = lock_user(VERIFY_READ, arg1, len, 1); | ||
| 284 | if (!s) { | ||
| 285 | /* Return bytes not written on error */ | ||
| 286 | return len; | ||
| 287 | } | ||
| 288 | - ret = set_swi_errno(ts, write(arg0, s, len)); | ||
| 289 | + ret = set_swi_errno(ts, write(gf->hostfd, s, len)); | ||
| 290 | unlock_user(s, arg1, 0); | ||
| 291 | if (ret == (uint32_t)-1) { | ||
| 292 | ret = 0; | ||
| 293 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 294 | GET_ARG(1); | ||
| 295 | GET_ARG(2); | ||
| 296 | len = arg2; | ||
| 297 | + | ||
| 298 | + gf = get_guestfd(arg0); | ||
| 299 | + if (!gf) { | ||
| 300 | + errno = EBADF; | ||
| 301 | + return set_swi_errno(ts, -1); | ||
| 302 | + } | ||
| 303 | + | ||
| 304 | if (use_gdb_syscalls()) { | ||
| 305 | arm_semi_syscall_len = len; | ||
| 306 | return arm_gdb_syscall(cpu, arm_semi_cb, "read,%x,%x,%x", | ||
| 307 | - arg0, arg1, len); | ||
| 308 | + gf->hostfd, arg1, len); | ||
| 309 | } else { | ||
| 310 | s = lock_user(VERIFY_WRITE, arg1, len, 0); | ||
| 311 | if (!s) { | ||
| 312 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 313 | return len; | ||
| 314 | } | ||
| 315 | do { | ||
| 316 | - ret = set_swi_errno(ts, read(arg0, s, len)); | ||
| 317 | + ret = set_swi_errno(ts, read(gf->hostfd, s, len)); | ||
| 318 | } while (ret == -1 && errno == EINTR); | ||
| 319 | unlock_user(s, arg1, len); | ||
| 320 | if (ret == (uint32_t)-1) { | ||
| 321 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 322 | return 0; | ||
| 323 | case TARGET_SYS_ISTTY: | ||
| 324 | GET_ARG(0); | ||
| 325 | + | ||
| 326 | + gf = get_guestfd(arg0); | ||
| 327 | + if (!gf) { | ||
| 328 | + errno = EBADF; | ||
| 329 | + return set_swi_errno(ts, -1); | ||
| 330 | + } | ||
| 331 | + | ||
| 332 | if (use_gdb_syscalls()) { | ||
| 333 | - return arm_gdb_syscall(cpu, arm_semi_cb, "isatty,%x", arg0); | ||
| 334 | + return arm_gdb_syscall(cpu, arm_semi_cb, "isatty,%x", gf->hostfd); | ||
| 335 | } else { | ||
| 336 | - return isatty(arg0); | ||
| 337 | + return isatty(gf->hostfd); | ||
| 338 | } | ||
| 339 | case TARGET_SYS_SEEK: | ||
| 340 | GET_ARG(0); | ||
| 341 | GET_ARG(1); | ||
| 342 | + | ||
| 343 | + gf = get_guestfd(arg0); | ||
| 344 | + if (!gf) { | ||
| 345 | + errno = EBADF; | ||
| 346 | + return set_swi_errno(ts, -1); | ||
| 347 | + } | ||
| 348 | + | ||
| 349 | if (use_gdb_syscalls()) { | ||
| 350 | return arm_gdb_syscall(cpu, arm_semi_cb, "lseek,%x,%x,0", | ||
| 351 | - arg0, arg1); | ||
| 352 | + gf->hostfd, arg1); | ||
| 353 | } else { | ||
| 354 | - ret = set_swi_errno(ts, lseek(arg0, arg1, SEEK_SET)); | ||
| 355 | + ret = set_swi_errno(ts, lseek(gf->hostfd, arg1, SEEK_SET)); | ||
| 356 | if (ret == (uint32_t)-1) | ||
| 357 | return -1; | ||
| 358 | return 0; | ||
| 359 | } | ||
| 360 | case TARGET_SYS_FLEN: | ||
| 361 | GET_ARG(0); | ||
| 362 | + | ||
| 363 | + gf = get_guestfd(arg0); | ||
| 364 | + if (!gf) { | ||
| 365 | + errno = EBADF; | ||
| 366 | + return set_swi_errno(ts, -1); | ||
| 367 | + } | ||
| 368 | + | ||
| 369 | if (use_gdb_syscalls()) { | ||
| 370 | return arm_gdb_syscall(cpu, arm_semi_flen_cb, "fstat,%x,%x", | ||
| 371 | - arg0, arm_flen_buf(cpu)); | ||
| 372 | + gf->hostfd, arm_flen_buf(cpu)); | ||
| 373 | } else { | ||
| 374 | struct stat buf; | ||
| 375 | - ret = set_swi_errno(ts, fstat(arg0, &buf)); | ||
| 376 | + ret = set_swi_errno(ts, fstat(gf->hostfd, &buf)); | ||
| 377 | if (ret == (uint32_t)-1) | ||
| 378 | return -1; | ||
| 379 | return buf.st_size; | ||
| 380 | -- | 41 | -- |
| 381 | 2.20.1 | 42 | 2.34.1 |
| 382 | |||
| 383 | diff view generated by jsdifflib |
| 1 | Switch the cmsdk-apb-watchdog code away from bottom-half based | 1 | Set the default NaN pattern explicitly, and remove the ifdef from |
|---|---|---|---|
| 2 | ptimers to the new transaction-based ptimer API. This just requires | 2 | parts64_default_nan(). |
| 3 | adding begin/commit calls around the various places that modify the | ||
| 4 | ptimer state, and using the new ptimer_init() function to create the | ||
| 5 | timer. | ||
| 6 | 3 | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 9 | Message-id: 20191008171740.9679-22-peter.maydell@linaro.org | 6 | Message-id: 20241202131347.498124-39-peter.maydell@linaro.org |
| 10 | --- | 7 | --- |
| 11 | hw/net/lan9118.c | 11 +++++++---- | 8 | target/hppa/fpu_helper.c | 2 ++ |
| 12 | 1 file changed, 7 insertions(+), 4 deletions(-) | 9 | fpu/softfloat-specialize.c.inc | 3 --- |
| 10 | 2 files changed, 2 insertions(+), 3 deletions(-) | ||
| 13 | 11 | ||
| 14 | diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c | 12 | diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c |
| 15 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/hw/net/lan9118.c | 14 | --- a/target/hppa/fpu_helper.c |
| 17 | +++ b/hw/net/lan9118.c | 15 | +++ b/target/hppa/fpu_helper.c |
| 18 | @@ -XXX,XX +XXX,XX @@ | 16 | @@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env) |
| 19 | #include "hw/ptimer.h" | 17 | set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status); |
| 20 | #include "hw/qdev-properties.h" | 18 | /* For inf * 0 + NaN, return the input NaN */ |
| 21 | #include "qemu/log.h" | 19 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); |
| 22 | -#include "qemu/main-loop.h" | 20 | + /* Default NaN: sign bit clear, msb-1 frac bit set */ |
| 23 | #include "qemu/module.h" | 21 | + set_float_default_nan_pattern(0b00100000, &env->fp_status); |
| 24 | /* For crc32 */ | ||
| 25 | #include <zlib.h> | ||
| 26 | @@ -XXX,XX +XXX,XX @@ static void lan9118_reset(DeviceState *d) | ||
| 27 | s->e2p_data = 0; | ||
| 28 | s->free_timer_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 40; | ||
| 29 | |||
| 30 | + ptimer_transaction_begin(s->timer); | ||
| 31 | ptimer_stop(s->timer); | ||
| 32 | ptimer_set_count(s->timer, 0xffff); | ||
| 33 | + ptimer_transaction_commit(s->timer); | ||
| 34 | s->gpt_cfg = 0xffff; | ||
| 35 | |||
| 36 | s->mac_cr = MAC_CR_PRMS; | ||
| 37 | @@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset, | ||
| 38 | break; | ||
| 39 | case CSR_GPT_CFG: | ||
| 40 | if ((s->gpt_cfg ^ val) & GPT_TIMER_EN) { | ||
| 41 | + ptimer_transaction_begin(s->timer); | ||
| 42 | if (val & GPT_TIMER_EN) { | ||
| 43 | ptimer_set_count(s->timer, val & 0xffff); | ||
| 44 | ptimer_run(s->timer, 0); | ||
| 45 | @@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset, | ||
| 46 | ptimer_stop(s->timer); | ||
| 47 | ptimer_set_count(s->timer, 0xffff); | ||
| 48 | } | ||
| 49 | + ptimer_transaction_commit(s->timer); | ||
| 50 | } | ||
| 51 | s->gpt_cfg = val & (GPT_TIMER_EN | 0xffff); | ||
| 52 | break; | ||
| 53 | @@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp) | ||
| 54 | { | ||
| 55 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
| 56 | lan9118_state *s = LAN9118(dev); | ||
| 57 | - QEMUBH *bh; | ||
| 58 | int i; | ||
| 59 | const MemoryRegionOps *mem_ops = | ||
| 60 | s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops; | ||
| 61 | @@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp) | ||
| 62 | s->pmt_ctrl = 1; | ||
| 63 | s->txp = &s->tx_packet; | ||
| 64 | |||
| 65 | - bh = qemu_bh_new(lan9118_tick, s); | ||
| 66 | - s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
| 67 | + s->timer = ptimer_init(lan9118_tick, s, PTIMER_POLICY_DEFAULT); | ||
| 68 | + ptimer_transaction_begin(s->timer); | ||
| 69 | ptimer_set_freq(s->timer, 10000); | ||
| 70 | ptimer_set_limit(s->timer, 0xffff, 1); | ||
| 71 | + ptimer_transaction_commit(s->timer); | ||
| 72 | } | 22 | } |
| 73 | 23 | ||
| 74 | static Property lan9118_properties[] = { | 24 | void cpu_hppa_loaded_fr0(CPUHPPAState *env) |
| 25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | ||
| 27 | --- a/fpu/softfloat-specialize.c.inc | ||
| 28 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 29 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
| 30 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
| 31 | /* Sign bit clear, all frac bits set */ | ||
| 32 | dnan_pattern = 0b01111111; | ||
| 33 | -#elif defined(TARGET_HPPA) | ||
| 34 | - /* Sign bit clear, msb-1 frac bit set */ | ||
| 35 | - dnan_pattern = 0b00100000; | ||
| 36 | #elif defined(TARGET_HEXAGON) | ||
| 37 | /* Sign bit set, all frac bits set. */ | ||
| 38 | dnan_pattern = 0b11111111; | ||
| 75 | -- | 39 | -- |
| 76 | 2.20.1 | 40 | 2.34.1 |
| 77 | |||
| 78 | diff view generated by jsdifflib |
| 1 | SH_EXT_EXIT_EXTENDED is a v2.0 semihosting extension: it | 1 | Set the default NaN pattern explicitly for the alpha target. |
|---|---|---|---|
| 2 | indicates that the implementation supports the SYS_EXIT_EXTENDED | ||
| 3 | function. This function allows both A64 and A32/T32 guests to | ||
| 4 | exit with a specified exit status, unlike the older SYS_EXIT | ||
| 5 | function which only allowed this for A64 guests. Implement | ||
| 6 | this extension. | ||
| 7 | 2 | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 9 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 10 | Message-id: 20190916141544.17540-15-peter.maydell@linaro.org | 5 | Message-id: 20241202131347.498124-40-peter.maydell@linaro.org |
| 11 | --- | 6 | --- |
| 12 | target/arm/arm-semi.c | 19 ++++++++++++++----- | 7 | target/alpha/cpu.c | 2 ++ |
| 13 | 1 file changed, 14 insertions(+), 5 deletions(-) | 8 | 1 file changed, 2 insertions(+) |
| 14 | 9 | ||
| 15 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 10 | diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c |
| 16 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/target/arm/arm-semi.c | 12 | --- a/target/alpha/cpu.c |
| 18 | +++ b/target/arm/arm-semi.c | 13 | +++ b/target/alpha/cpu.c |
| 19 | @@ -XXX,XX +XXX,XX @@ | 14 | @@ -XXX,XX +XXX,XX @@ static void alpha_cpu_initfn(Object *obj) |
| 20 | #define TARGET_SYS_HEAPINFO 0x16 | 15 | * operand in Fa. That is float_2nan_prop_ba. |
| 21 | #define TARGET_SYS_EXIT 0x18 | 16 | */ |
| 22 | #define TARGET_SYS_SYNCCACHE 0x19 | 17 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); |
| 23 | +#define TARGET_SYS_EXIT_EXTENDED 0x20 | 18 | + /* Default NaN: sign bit clear, msb frac bit set */ |
| 24 | 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); | |
| 25 | /* ADP_Stopped_ApplicationExit is used for exit(0), | 20 | #if defined(CONFIG_USER_ONLY) |
| 26 | * anything else is implemented as exit(1) */ | 21 | env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN; |
| 27 | @@ -XXX,XX +XXX,XX @@ static uint32_t gdb_flenfn(ARMCPU *cpu, GuestFD *gf) | 22 | cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD |
| 28 | #define SHFB_MAGIC_2 0x46 | ||
| 29 | #define SHFB_MAGIC_3 0x42 | ||
| 30 | |||
| 31 | +/* Feature bits reportable in feature byte 0 */ | ||
| 32 | +#define SH_EXT_EXIT_EXTENDED (1 << 0) | ||
| 33 | + | ||
| 34 | static const uint8_t featurefile_data[] = { | ||
| 35 | SHFB_MAGIC_0, | ||
| 36 | SHFB_MAGIC_1, | ||
| 37 | SHFB_MAGIC_2, | ||
| 38 | SHFB_MAGIC_3, | ||
| 39 | - 0, /* Feature byte 0 */ | ||
| 40 | + SH_EXT_EXIT_EXTENDED, /* Feature byte 0 */ | ||
| 41 | }; | ||
| 42 | |||
| 43 | static void init_featurefile_guestfd(int guestfd) | ||
| 44 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 45 | return 0; | ||
| 46 | } | ||
| 47 | case TARGET_SYS_EXIT: | ||
| 48 | - if (is_a64(env)) { | ||
| 49 | + case TARGET_SYS_EXIT_EXTENDED: | ||
| 50 | + if (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(env)) { | ||
| 51 | /* | ||
| 52 | - * The A64 version of this call takes a parameter block, | ||
| 53 | + * The A64 version of SYS_EXIT takes a parameter block, | ||
| 54 | * so the application-exit type can return a subcode which | ||
| 55 | * is the exit status code from the application. | ||
| 56 | + * SYS_EXIT_EXTENDED is an a new-in-v2.0 optional function | ||
| 57 | + * which allows A32/T32 guests to also provide a status code. | ||
| 58 | */ | ||
| 59 | GET_ARG(0); | ||
| 60 | GET_ARG(1); | ||
| 61 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 62 | } | ||
| 63 | } else { | ||
| 64 | /* | ||
| 65 | - * ARM specifies only Stopped_ApplicationExit as normal | ||
| 66 | - * exit, everything else is considered an error | ||
| 67 | + * The A32/T32 version of SYS_EXIT specifies only | ||
| 68 | + * Stopped_ApplicationExit as normal exit, but does not | ||
| 69 | + * allow the guest to specify the exit status code. | ||
| 70 | + * Everything else is considered an error. | ||
| 71 | */ | ||
| 72 | ret = (args == ADP_Stopped_ApplicationExit) ? 0 : 1; | ||
| 73 | } | ||
| 74 | -- | 23 | -- |
| 75 | 2.20.1 | 24 | 2.34.1 |
| 76 | |||
| 77 | diff view generated by jsdifflib |
| 1 | From: Eric Auger <eric.auger@redhat.com> | 1 | Set the default NaN pattern explicitly for the arm target. |
|---|---|---|---|
| 2 | This includes setting it for the old linux-user nwfpe emulation. | ||
| 3 | For nwfpe, our default doesn't match the real kernel, but we | ||
| 4 | avoid making a behaviour change in this commit. | ||
| 2 | 5 | ||
| 3 | Host kernels that expose the KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 capability | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 4 | allow injection of interrupts along with vcpu ids larger than 255. | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 5 | Let's encode the vpcu id on 12 bits according to the upgraded KVM_IRQ_LINE | 8 | Message-id: 20241202131347.498124-41-peter.maydell@linaro.org |
| 6 | ABI when needed. | 9 | --- |
| 10 | linux-user/arm/nwfpe/fpa11.c | 5 +++++ | ||
| 11 | target/arm/cpu.c | 2 ++ | ||
| 12 | 2 files changed, 7 insertions(+) | ||
| 7 | 13 | ||
| 8 | Given that we have two callsites that need to assemble | 14 | diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c |
| 9 | the value for kvm_set_irq(), a new helper routine, kvm_arm_set_irq | ||
| 10 | is introduced. | ||
| 11 | |||
| 12 | Without that patch qemu exits with "kvm_set_irq: Invalid argument" | ||
| 13 | message. | ||
| 14 | |||
| 15 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
| 16 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> | ||
| 17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 18 | Reviewed-by: Andrew Jones <drjones@redhat.com> | ||
| 19 | Acked-by: Marc Zyngier <maz@kernel.org> | ||
| 20 | Message-id: 20191003154640.22451-3-eric.auger@redhat.com | ||
| 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 22 | --- | ||
| 23 | target/arm/kvm_arm.h | 1 + | ||
| 24 | hw/intc/arm_gic_kvm.c | 7 ++----- | ||
| 25 | target/arm/cpu.c | 10 ++++------ | ||
| 26 | target/arm/kvm.c | 12 ++++++++++++ | ||
| 27 | 4 files changed, 19 insertions(+), 11 deletions(-) | ||
| 28 | |||
| 29 | diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h | ||
| 30 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 31 | --- a/target/arm/kvm_arm.h | 16 | --- a/linux-user/arm/nwfpe/fpa11.c |
| 32 | +++ b/target/arm/kvm_arm.h | 17 | +++ b/linux-user/arm/nwfpe/fpa11.c |
| 33 | @@ -XXX,XX +XXX,XX @@ int kvm_arm_vgic_probe(void); | 18 | @@ -XXX,XX +XXX,XX @@ void resetFPA11(void) |
| 34 | 19 | * this late date. | |
| 35 | void kvm_arm_pmu_set_irq(CPUState *cs, int irq); | 20 | */ |
| 36 | void kvm_arm_pmu_init(CPUState *cs); | 21 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status); |
| 37 | +int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); | 22 | + /* |
| 38 | 23 | + * Use the same default NaN value as Arm VFP. This doesn't match | |
| 39 | #else | 24 | + * the Linux kernel's nwfpe emulation, which uses an all-1s value. |
| 40 | 25 | + */ | |
| 41 | diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c | 26 | + set_float_default_nan_pattern(0b01000000, &fpa11->fp_status); |
| 42 | index XXXXXXX..XXXXXXX 100644 | ||
| 43 | --- a/hw/intc/arm_gic_kvm.c | ||
| 44 | +++ b/hw/intc/arm_gic_kvm.c | ||
| 45 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_gic_set_irq(uint32_t num_irq, int irq, int level) | ||
| 46 | * has separate fields in the irq number for type, | ||
| 47 | * CPU number and interrupt number. | ||
| 48 | */ | ||
| 49 | - int kvm_irq, irqtype, cpu; | ||
| 50 | + int irqtype, cpu; | ||
| 51 | |||
| 52 | if (irq < (num_irq - GIC_INTERNAL)) { | ||
| 53 | /* External interrupt. The kernel numbers these like the GIC | ||
| 54 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_gic_set_irq(uint32_t num_irq, int irq, int level) | ||
| 55 | cpu = irq / GIC_INTERNAL; | ||
| 56 | irq %= GIC_INTERNAL; | ||
| 57 | } | ||
| 58 | - kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT) | ||
| 59 | - | (cpu << KVM_ARM_IRQ_VCPU_SHIFT) | irq; | ||
| 60 | - | ||
| 61 | - kvm_set_irq(kvm_state, kvm_irq, !!level); | ||
| 62 | + kvm_arm_set_irq(cpu, irqtype, irq, !!level); | ||
| 63 | } | 27 | } |
| 64 | 28 | ||
| 65 | static void kvm_arm_gicv2_set_irq(void *opaque, int irq, int level) | 29 | void SetRoundingMode(const unsigned int opcode) |
| 66 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 30 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
| 67 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
| 68 | --- a/target/arm/cpu.c | 32 | --- a/target/arm/cpu.c |
| 69 | +++ b/target/arm/cpu.c | 33 | +++ b/target/arm/cpu.c |
| 70 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) | 34 | @@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
| 71 | ARMCPU *cpu = opaque; | 35 | * the pseudocode function the arguments are in the order c, a, b. |
| 72 | CPUARMState *env = &cpu->env; | 36 | * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, |
| 73 | CPUState *cs = CPU(cpu); | 37 | * and the input NaN if it is signalling |
| 74 | - int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; | 38 | + * * Default NaN has sign bit clear, msb frac bit set |
| 75 | uint32_t linestate_bit; | 39 | */ |
| 76 | + int irq_id; | 40 | static void arm_set_default_fp_behaviours(float_status *s) |
| 77 | 41 | { | |
| 78 | switch (irq) { | 42 | @@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s) |
| 79 | case ARM_CPU_IRQ: | 43 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); |
| 80 | - kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; | 44 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); |
| 81 | + irq_id = KVM_ARM_IRQ_CPU_IRQ; | 45 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); |
| 82 | linestate_bit = CPU_INTERRUPT_HARD; | 46 | + set_float_default_nan_pattern(0b01000000, s); |
| 83 | break; | ||
| 84 | case ARM_CPU_FIQ: | ||
| 85 | - kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; | ||
| 86 | + irq_id = KVM_ARM_IRQ_CPU_FIQ; | ||
| 87 | linestate_bit = CPU_INTERRUPT_FIQ; | ||
| 88 | break; | ||
| 89 | default: | ||
| 90 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) | ||
| 91 | } else { | ||
| 92 | env->irq_line_state &= ~linestate_bit; | ||
| 93 | } | ||
| 94 | - | ||
| 95 | - kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; | ||
| 96 | - kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); | ||
| 97 | + kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); | ||
| 98 | #endif | ||
| 99 | } | 47 | } |
| 100 | 48 | ||
| 101 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c | 49 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
| 102 | index XXXXXXX..XXXXXXX 100644 | ||
| 103 | --- a/target/arm/kvm.c | ||
| 104 | +++ b/target/arm/kvm.c | ||
| 105 | @@ -XXX,XX +XXX,XX @@ int kvm_arm_vgic_probe(void) | ||
| 106 | } | ||
| 107 | } | ||
| 108 | |||
| 109 | +int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level) | ||
| 110 | +{ | ||
| 111 | + int kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT) | irq; | ||
| 112 | + int cpu_idx1 = cpu % 256; | ||
| 113 | + int cpu_idx2 = cpu / 256; | ||
| 114 | + | ||
| 115 | + kvm_irq |= (cpu_idx1 << KVM_ARM_IRQ_VCPU_SHIFT) | | ||
| 116 | + (cpu_idx2 << KVM_ARM_IRQ_VCPU2_SHIFT); | ||
| 117 | + | ||
| 118 | + return kvm_set_irq(kvm_state, kvm_irq, !!level); | ||
| 119 | +} | ||
| 120 | + | ||
| 121 | int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, | ||
| 122 | uint64_t address, uint32_t data, PCIDevice *dev) | ||
| 123 | { | ||
| 124 | -- | 50 | -- |
| 125 | 2.20.1 | 51 | 2.34.1 |
| 126 | |||
| 127 | diff view generated by jsdifflib |
| 1 | Switch the imx_epit.c code away from bottom-half based ptimers to | 1 | Set the default NaN pattern explicitly for loongarch. |
|---|---|---|---|
| 2 | the new transaction-based ptimer API. This just requires adding | ||
| 3 | begin/commit calls around the various places that modify the ptimer | ||
| 4 | state, and using the new ptimer_init() function to create the timer. | ||
| 5 | 2 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Message-id: 20191008171740.9679-19-peter.maydell@linaro.org | 5 | Message-id: 20241202131347.498124-42-peter.maydell@linaro.org |
| 9 | --- | 6 | --- |
| 10 | hw/timer/imx_gpt.c | 21 +++++++++++++++++---- | 7 | target/loongarch/tcg/fpu_helper.c | 2 ++ |
| 11 | 1 file changed, 17 insertions(+), 4 deletions(-) | 8 | 1 file changed, 2 insertions(+) |
| 12 | 9 | ||
| 13 | diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c | 10 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c |
| 14 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/hw/timer/imx_gpt.c | 12 | --- a/target/loongarch/tcg/fpu_helper.c |
| 16 | +++ b/hw/timer/imx_gpt.c | 13 | +++ b/target/loongarch/tcg/fpu_helper.c |
| 17 | @@ -XXX,XX +XXX,XX @@ | 14 | @@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env) |
| 18 | #include "hw/irq.h" | 15 | */ |
| 19 | #include "hw/timer/imx_gpt.h" | 16 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); |
| 20 | #include "migration/vmstate.h" | 17 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); |
| 21 | -#include "qemu/main-loop.h" | 18 | + /* Default NaN: sign bit clear, msb frac bit set */ |
| 22 | #include "qemu/module.h" | 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); |
| 23 | #include "qemu/log.h" | ||
| 24 | |||
| 25 | @@ -XXX,XX +XXX,XX @@ static const IMXClk imx7_gpt_clocks[] = { | ||
| 26 | CLK_NONE, /* 111 not defined */ | ||
| 27 | }; | ||
| 28 | |||
| 29 | +/* Must be called from within ptimer_transaction_begin/commit block */ | ||
| 30 | static void imx_gpt_set_freq(IMXGPTState *s) | ||
| 31 | { | ||
| 32 | uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3); | ||
| 33 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg, | ||
| 34 | return timeout; | ||
| 35 | } | 20 | } |
| 36 | 21 | ||
| 37 | +/* Must be called from within ptimer_transaction_begin/commit block */ | 22 | int ieee_ex_to_loongarch(int xcpt) |
| 38 | static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event) | ||
| 39 | { | ||
| 40 | uint32_t timeout = GPT_TIMER_MAX; | ||
| 41 | @@ -XXX,XX +XXX,XX @@ static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size) | ||
| 42 | |||
| 43 | static void imx_gpt_reset_common(IMXGPTState *s, bool is_soft_reset) | ||
| 44 | { | ||
| 45 | + ptimer_transaction_begin(s->timer); | ||
| 46 | /* stop timer */ | ||
| 47 | ptimer_stop(s->timer); | ||
| 48 | |||
| 49 | @@ -XXX,XX +XXX,XX @@ static void imx_gpt_reset_common(IMXGPTState *s, bool is_soft_reset) | ||
| 50 | if (s->freq && (s->cr & GPT_CR_EN)) { | ||
| 51 | ptimer_run(s->timer, 1); | ||
| 52 | } | ||
| 53 | + ptimer_transaction_commit(s->timer); | ||
| 54 | } | ||
| 55 | |||
| 56 | static void imx_gpt_soft_reset(DeviceState *dev) | ||
| 57 | @@ -XXX,XX +XXX,XX @@ static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, | ||
| 58 | imx_gpt_soft_reset(DEVICE(s)); | ||
| 59 | } else { | ||
| 60 | /* set our freq, as the source might have changed */ | ||
| 61 | + ptimer_transaction_begin(s->timer); | ||
| 62 | imx_gpt_set_freq(s); | ||
| 63 | |||
| 64 | if ((oldreg ^ s->cr) & GPT_CR_EN) { | ||
| 65 | @@ -XXX,XX +XXX,XX @@ static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, | ||
| 66 | ptimer_stop(s->timer); | ||
| 67 | } | ||
| 68 | } | ||
| 69 | + ptimer_transaction_commit(s->timer); | ||
| 70 | } | ||
| 71 | break; | ||
| 72 | |||
| 73 | case 1: /* Prescaler */ | ||
| 74 | s->pr = value & 0xfff; | ||
| 75 | + ptimer_transaction_begin(s->timer); | ||
| 76 | imx_gpt_set_freq(s); | ||
| 77 | + ptimer_transaction_commit(s->timer); | ||
| 78 | break; | ||
| 79 | |||
| 80 | case 2: /* SR */ | ||
| 81 | @@ -XXX,XX +XXX,XX @@ static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, | ||
| 82 | s->ir = value & 0x3f; | ||
| 83 | imx_gpt_update_int(s); | ||
| 84 | |||
| 85 | + ptimer_transaction_begin(s->timer); | ||
| 86 | imx_gpt_compute_next_timeout(s, false); | ||
| 87 | + ptimer_transaction_commit(s->timer); | ||
| 88 | |||
| 89 | break; | ||
| 90 | |||
| 91 | case 4: /* OCR1 -- output compare register */ | ||
| 92 | s->ocr1 = value; | ||
| 93 | |||
| 94 | + ptimer_transaction_begin(s->timer); | ||
| 95 | /* In non-freerun mode, reset count when this register is written */ | ||
| 96 | if (!(s->cr & GPT_CR_FRR)) { | ||
| 97 | s->next_timeout = GPT_TIMER_MAX; | ||
| 98 | @@ -XXX,XX +XXX,XX @@ static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, | ||
| 99 | |||
| 100 | /* compute the new timeout */ | ||
| 101 | imx_gpt_compute_next_timeout(s, false); | ||
| 102 | + ptimer_transaction_commit(s->timer); | ||
| 103 | |||
| 104 | break; | ||
| 105 | |||
| 106 | @@ -XXX,XX +XXX,XX @@ static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, | ||
| 107 | s->ocr2 = value; | ||
| 108 | |||
| 109 | /* compute the new timeout */ | ||
| 110 | + ptimer_transaction_begin(s->timer); | ||
| 111 | imx_gpt_compute_next_timeout(s, false); | ||
| 112 | + ptimer_transaction_commit(s->timer); | ||
| 113 | |||
| 114 | break; | ||
| 115 | |||
| 116 | @@ -XXX,XX +XXX,XX @@ static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, | ||
| 117 | s->ocr3 = value; | ||
| 118 | |||
| 119 | /* compute the new timeout */ | ||
| 120 | + ptimer_transaction_begin(s->timer); | ||
| 121 | imx_gpt_compute_next_timeout(s, false); | ||
| 122 | + ptimer_transaction_commit(s->timer); | ||
| 123 | |||
| 124 | break; | ||
| 125 | |||
| 126 | @@ -XXX,XX +XXX,XX @@ static void imx_gpt_realize(DeviceState *dev, Error **errp) | ||
| 127 | { | ||
| 128 | IMXGPTState *s = IMX_GPT(dev); | ||
| 129 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
| 130 | - QEMUBH *bh; | ||
| 131 | |||
| 132 | sysbus_init_irq(sbd, &s->irq); | ||
| 133 | memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT, | ||
| 134 | 0x00001000); | ||
| 135 | sysbus_init_mmio(sbd, &s->iomem); | ||
| 136 | |||
| 137 | - bh = qemu_bh_new(imx_gpt_timeout, s); | ||
| 138 | - s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
| 139 | + s->timer = ptimer_init(imx_gpt_timeout, s, PTIMER_POLICY_DEFAULT); | ||
| 140 | } | ||
| 141 | |||
| 142 | static void imx_gpt_class_init(ObjectClass *klass, void *data) | ||
| 143 | -- | 23 | -- |
| 144 | 2.20.1 | 24 | 2.34.1 |
| 145 | |||
| 146 | diff view generated by jsdifflib |
| 1 | In arm_gdb_syscall() we have a comment suggesting a race | 1 | Set the default NaN pattern explicitly for m68k. |
|---|---|---|---|
| 2 | because the syscall completion callback might not happen | ||
| 3 | before the gdb_do_syscallv() call returns. The comment is | ||
| 4 | correct that the callback may not happen but incorrect about | ||
| 5 | the effects. Correct it and note the important caveat that | ||
| 6 | callers must never do any work of any kind after return from | ||
| 7 | arm_gdb_syscall() that depends on its return value. | ||
| 8 | 2 | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 11 | Message-id: 20190916141544.17540-4-peter.maydell@linaro.org | 5 | Message-id: 20241202131347.498124-43-peter.maydell@linaro.org |
| 12 | --- | 6 | --- |
| 13 | target/arm/arm-semi.c | 19 +++++++++++++++---- | 7 | target/m68k/cpu.c | 2 ++ |
| 14 | 1 file changed, 15 insertions(+), 4 deletions(-) | 8 | fpu/softfloat-specialize.c.inc | 2 +- |
| 9 | 2 files changed, 3 insertions(+), 1 deletion(-) | ||
| 15 | 10 | ||
| 16 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 11 | diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c |
| 17 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/target/arm/arm-semi.c | 13 | --- a/target/m68k/cpu.c |
| 19 | +++ b/target/arm/arm-semi.c | 14 | +++ b/target/m68k/cpu.c |
| 20 | @@ -XXX,XX +XXX,XX @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, | 15 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) |
| 21 | gdb_do_syscallv(cb, fmt, va); | 16 | * preceding paragraph for nonsignaling NaNs. |
| 22 | va_end(va); | ||
| 23 | |||
| 24 | - /* FIXME: we are implicitly relying on the syscall completing | ||
| 25 | - * before this point, which is not guaranteed. We should | ||
| 26 | - * put in an explicit synchronization between this and | ||
| 27 | - * the callback function. | ||
| 28 | + /* | ||
| 29 | + * FIXME: in softmmu mode, the gdbstub will schedule our callback | ||
| 30 | + * to occur, but will not actually call it to complete the syscall | ||
| 31 | + * until after this function has returned and we are back in the | ||
| 32 | + * CPU main loop. Therefore callers to this function must not | ||
| 33 | + * do anything with its return value, because it is not necessarily | ||
| 34 | + * the result of the syscall, but could just be the old value of X0. | ||
| 35 | + * The only thing safe to do with this is that the callers of | ||
| 36 | + * do_arm_semihosting() will write it straight back into X0. | ||
| 37 | + * (In linux-user mode, the callback will have happened before | ||
| 38 | + * gdb_do_syscallv() returns.) | ||
| 39 | + * | ||
| 40 | + * We should tidy this up so neither this function nor | ||
| 41 | + * do_arm_semihosting() return a value, so the mistake of | ||
| 42 | + * doing something with the return value is not possible to make. | ||
| 43 | */ | 17 | */ |
| 44 | 18 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); | |
| 45 | return is_a64(env) ? env->xregs[0] : env->regs[0]; | 19 | + /* Default NaN: sign bit clear, all frac bits set */ |
| 20 | + set_float_default_nan_pattern(0b01111111, &env->fp_status); | ||
| 21 | |||
| 22 | nan = floatx80_default_nan(&env->fp_status); | ||
| 23 | for (i = 0; i < 8; i++) { | ||
| 24 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 25 | index XXXXXXX..XXXXXXX 100644 | ||
| 26 | --- a/fpu/softfloat-specialize.c.inc | ||
| 27 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 28 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
| 29 | uint8_t dnan_pattern = status->default_nan_pattern; | ||
| 30 | |||
| 31 | if (dnan_pattern == 0) { | ||
| 32 | -#if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
| 33 | +#if defined(TARGET_SPARC) | ||
| 34 | /* Sign bit clear, all frac bits set */ | ||
| 35 | dnan_pattern = 0b01111111; | ||
| 36 | #elif defined(TARGET_HEXAGON) | ||
| 46 | -- | 37 | -- |
| 47 | 2.20.1 | 38 | 2.34.1 |
| 48 | |||
| 49 | diff view generated by jsdifflib |
| 1 | Switch the arm_timer.c code away from bottom-half based ptimers | 1 | Set the default NaN pattern explicitly for MIPS. Note that this |
|---|---|---|---|
| 2 | to the new transaction-based ptimer API. This just requires | 2 | is our only target which currently changes the default NaN |
| 3 | adding begin/commit calls around the various arms of | 3 | at runtime (which it was previously doing indirectly when it |
| 4 | arm_timer_write() that modify the ptimer state, and using the | 4 | changed the snan_bit_is_one setting). |
| 5 | new ptimer_init() function to create the timer. | ||
| 6 | 5 | ||
| 7 | Fixes: https://bugs.launchpad.net/qemu/+bug/1777777 | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 10 | Message-id: 20191008171740.9679-5-peter.maydell@linaro.org | 8 | Message-id: 20241202131347.498124-44-peter.maydell@linaro.org |
| 11 | --- | 9 | --- |
| 12 | hw/timer/arm_timer.c | 16 +++++++++++----- | 10 | target/mips/fpu_helper.h | 7 +++++++ |
| 13 | 1 file changed, 11 insertions(+), 5 deletions(-) | 11 | target/mips/msa.c | 3 +++ |
| 12 | 2 files changed, 10 insertions(+) | ||
| 14 | 13 | ||
| 15 | diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c | 14 | diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h |
| 16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/hw/timer/arm_timer.c | 16 | --- a/target/mips/fpu_helper.h |
| 18 | +++ b/hw/timer/arm_timer.c | 17 | +++ b/target/mips/fpu_helper.h |
| 19 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) |
| 20 | #include "hw/irq.h" | 19 | set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); |
| 21 | #include "hw/ptimer.h" | 20 | nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; |
| 22 | #include "hw/qdev-properties.h" | 21 | set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); |
| 23 | -#include "qemu/main-loop.h" | 22 | + /* |
| 24 | #include "qemu/module.h" | 23 | + * With nan2008, the default NaN value has the sign bit clear and the |
| 25 | #include "qemu/log.h" | 24 | + * frac msb set; with the older mode, the sign bit is clear, and all |
| 26 | 25 | + * frac bits except the msb are set. | |
| 27 | @@ -XXX,XX +XXX,XX @@ static uint32_t arm_timer_read(void *opaque, hwaddr offset) | 26 | + */ |
| 28 | } | 27 | + set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111, |
| 28 | + &env->active_fpu.fp_status); | ||
| 29 | |||
| 29 | } | 30 | } |
| 30 | 31 | ||
| 31 | -/* Reset the timer limit after settings have changed. */ | 32 | diff --git a/target/mips/msa.c b/target/mips/msa.c |
| 32 | +/* | 33 | index XXXXXXX..XXXXXXX 100644 |
| 33 | + * Reset the timer limit after settings have changed. | 34 | --- a/target/mips/msa.c |
| 34 | + * May only be called from inside a ptimer transaction block. | 35 | +++ b/target/mips/msa.c |
| 35 | + */ | 36 | @@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env) |
| 36 | static void arm_timer_recalibrate(arm_timer_state *s, int reload) | 37 | /* Inf * 0 + NaN returns the input NaN */ |
| 37 | { | 38 | set_float_infzeronan_rule(float_infzeronan_dnan_never, |
| 38 | uint32_t limit; | 39 | &env->active_tc.msa_fp_status); |
| 39 | @@ -XXX,XX +XXX,XX @@ static void arm_timer_write(void *opaque, hwaddr offset, | 40 | + /* Default NaN: sign bit clear, frac msb set */ |
| 40 | switch (offset >> 2) { | 41 | + set_float_default_nan_pattern(0b01000000, |
| 41 | case 0: /* TimerLoad */ | 42 | + &env->active_tc.msa_fp_status); |
| 42 | s->limit = value; | ||
| 43 | + ptimer_transaction_begin(s->timer); | ||
| 44 | arm_timer_recalibrate(s, 1); | ||
| 45 | + ptimer_transaction_commit(s->timer); | ||
| 46 | break; | ||
| 47 | case 1: /* TimerValue */ | ||
| 48 | /* ??? Linux seems to want to write to this readonly register. | ||
| 49 | Ignore it. */ | ||
| 50 | break; | ||
| 51 | case 2: /* TimerControl */ | ||
| 52 | + ptimer_transaction_begin(s->timer); | ||
| 53 | if (s->control & TIMER_CTRL_ENABLE) { | ||
| 54 | /* Pause the timer if it is running. This may cause some | ||
| 55 | inaccuracy dure to rounding, but avoids a whole lot of other | ||
| 56 | @@ -XXX,XX +XXX,XX @@ static void arm_timer_write(void *opaque, hwaddr offset, | ||
| 57 | /* Restart the timer if still enabled. */ | ||
| 58 | ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0); | ||
| 59 | } | ||
| 60 | + ptimer_transaction_commit(s->timer); | ||
| 61 | break; | ||
| 62 | case 3: /* TimerIntClr */ | ||
| 63 | s->int_level = 0; | ||
| 64 | break; | ||
| 65 | case 6: /* TimerBGLoad */ | ||
| 66 | s->limit = value; | ||
| 67 | + ptimer_transaction_begin(s->timer); | ||
| 68 | arm_timer_recalibrate(s, 0); | ||
| 69 | + ptimer_transaction_commit(s->timer); | ||
| 70 | break; | ||
| 71 | default: | ||
| 72 | qemu_log_mask(LOG_GUEST_ERROR, | ||
| 73 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_arm_timer = { | ||
| 74 | static arm_timer_state *arm_timer_init(uint32_t freq) | ||
| 75 | { | ||
| 76 | arm_timer_state *s; | ||
| 77 | - QEMUBH *bh; | ||
| 78 | |||
| 79 | s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state)); | ||
| 80 | s->freq = freq; | ||
| 81 | s->control = TIMER_CTRL_IE; | ||
| 82 | |||
| 83 | - bh = qemu_bh_new(arm_timer_tick, s); | ||
| 84 | - s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
| 85 | + s->timer = ptimer_init(arm_timer_tick, s, PTIMER_POLICY_DEFAULT); | ||
| 86 | vmstate_register(NULL, -1, &vmstate_arm_timer, s); | ||
| 87 | return s; | ||
| 88 | } | 43 | } |
| 89 | -- | 44 | -- |
| 90 | 2.20.1 | 45 | 2.34.1 |
| 91 | |||
| 92 | diff view generated by jsdifflib |
| 1 | If we fail a semihosting call we should always set the | 1 | Set the default NaN pattern explicitly for openrisc. |
|---|---|---|---|
| 2 | semihosting errno to something; we were failing to do | ||
| 3 | this for some of the "check inputs for sanity" cases. | ||
| 4 | 2 | ||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 9 | Message-id: 20190916141544.17540-3-peter.maydell@linaro.org | 5 | Message-id: 20241202131347.498124-45-peter.maydell@linaro.org |
| 10 | --- | 6 | --- |
| 11 | target/arm/arm-semi.c | 45 ++++++++++++++++++++++++++----------------- | 7 | target/openrisc/cpu.c | 2 ++ |
| 12 | 1 file changed, 27 insertions(+), 18 deletions(-) | 8 | 1 file changed, 2 insertions(+) |
| 13 | 9 | ||
| 14 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 10 | diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c |
| 15 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/target/arm/arm-semi.c | 12 | --- a/target/openrisc/cpu.c |
| 17 | +++ b/target/arm/arm-semi.c | 13 | +++ b/target/openrisc/cpu.c |
| 18 | @@ -XXX,XX +XXX,XX @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, | 14 | @@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type) |
| 19 | #define GET_ARG(n) do { \ | 15 | */ |
| 20 | if (is_a64(env)) { \ | 16 | set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status); |
| 21 | if (get_user_u64(arg ## n, args + (n) * 8)) { \ | 17 | |
| 22 | - return -1; \ | 18 | + /* Default NaN: sign bit clear, frac msb set */ |
| 23 | + errno = EFAULT; \ | 19 | + set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status); |
| 24 | + return set_swi_errno(ts, -1); \ | 20 | |
| 25 | } \ | 21 | #ifndef CONFIG_USER_ONLY |
| 26 | } else { \ | 22 | cpu->env.picmr = 0x00000000; |
| 27 | if (get_user_u32(arg ## n, args + (n) * 4)) { \ | ||
| 28 | - return -1; \ | ||
| 29 | + errno = EFAULT; \ | ||
| 30 | + return set_swi_errno(ts, -1); \ | ||
| 31 | } \ | ||
| 32 | } \ | ||
| 33 | } while (0) | ||
| 34 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 35 | GET_ARG(2); | ||
| 36 | s = lock_user_string(arg0); | ||
| 37 | if (!s) { | ||
| 38 | - /* FIXME - should this error code be -TARGET_EFAULT ? */ | ||
| 39 | - return (uint32_t)-1; | ||
| 40 | + errno = EFAULT; | ||
| 41 | + return set_swi_errno(ts, -1); | ||
| 42 | } | ||
| 43 | if (arg1 >= 12) { | ||
| 44 | unlock_user(s, arg0, 0); | ||
| 45 | - return (uint32_t)-1; | ||
| 46 | + errno = EINVAL; | ||
| 47 | + return set_swi_errno(ts, -1); | ||
| 48 | } | ||
| 49 | if (strcmp(s, ":tt") == 0) { | ||
| 50 | int result_fileno = arg1 < 4 ? STDIN_FILENO : STDOUT_FILENO; | ||
| 51 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 52 | } else { | ||
| 53 | s = lock_user_string(arg0); | ||
| 54 | if (!s) { | ||
| 55 | - /* FIXME - should this error code be -TARGET_EFAULT ? */ | ||
| 56 | - return (uint32_t)-1; | ||
| 57 | + errno = EFAULT; | ||
| 58 | + return set_swi_errno(ts, -1); | ||
| 59 | } | ||
| 60 | ret = set_swi_errno(ts, remove(s)); | ||
| 61 | unlock_user(s, arg0, 0); | ||
| 62 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 63 | char *s2; | ||
| 64 | s = lock_user_string(arg0); | ||
| 65 | s2 = lock_user_string(arg2); | ||
| 66 | - if (!s || !s2) | ||
| 67 | - /* FIXME - should this error code be -TARGET_EFAULT ? */ | ||
| 68 | - ret = (uint32_t)-1; | ||
| 69 | - else | ||
| 70 | + if (!s || !s2) { | ||
| 71 | + errno = EFAULT; | ||
| 72 | + ret = set_swi_errno(ts, -1); | ||
| 73 | + } else { | ||
| 74 | ret = set_swi_errno(ts, rename(s, s2)); | ||
| 75 | + } | ||
| 76 | if (s2) | ||
| 77 | unlock_user(s2, arg2, 0); | ||
| 78 | if (s) | ||
| 79 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 80 | } else { | ||
| 81 | s = lock_user_string(arg0); | ||
| 82 | if (!s) { | ||
| 83 | - /* FIXME - should this error code be -TARGET_EFAULT ? */ | ||
| 84 | - return (uint32_t)-1; | ||
| 85 | + errno = EFAULT; | ||
| 86 | + return set_swi_errno(ts, -1); | ||
| 87 | } | ||
| 88 | ret = set_swi_errno(ts, system(s)); | ||
| 89 | unlock_user(s, arg0, 0); | ||
| 90 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 91 | |||
| 92 | if (output_size > input_size) { | ||
| 93 | /* Not enough space to store command-line arguments. */ | ||
| 94 | - return -1; | ||
| 95 | + errno = E2BIG; | ||
| 96 | + return set_swi_errno(ts, -1); | ||
| 97 | } | ||
| 98 | |||
| 99 | /* Adjust the command-line length. */ | ||
| 100 | if (SET_ARG(1, output_size - 1)) { | ||
| 101 | /* Couldn't write back to argument block */ | ||
| 102 | - return -1; | ||
| 103 | + errno = EFAULT; | ||
| 104 | + return set_swi_errno(ts, -1); | ||
| 105 | } | ||
| 106 | |||
| 107 | /* Lock the buffer on the ARM side. */ | ||
| 108 | output_buffer = lock_user(VERIFY_WRITE, arg0, output_size, 0); | ||
| 109 | if (!output_buffer) { | ||
| 110 | - return -1; | ||
| 111 | + errno = EFAULT; | ||
| 112 | + return set_swi_errno(ts, -1); | ||
| 113 | } | ||
| 114 | |||
| 115 | /* Copy the command-line arguments. */ | ||
| 116 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 117 | |||
| 118 | if (copy_from_user(output_buffer, ts->info->arg_start, | ||
| 119 | output_size)) { | ||
| 120 | - status = -1; | ||
| 121 | + errno = EFAULT; | ||
| 122 | + status = set_swi_errno(ts, -1); | ||
| 123 | goto out; | ||
| 124 | } | ||
| 125 | |||
| 126 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 127 | |||
| 128 | if (fail) { | ||
| 129 | /* Couldn't write back to argument block */ | ||
| 130 | - return -1; | ||
| 131 | + errno = EFAULT; | ||
| 132 | + return set_swi_errno(ts, -1); | ||
| 133 | } | ||
| 134 | } | ||
| 135 | return 0; | ||
| 136 | -- | 23 | -- |
| 137 | 2.20.1 | 24 | 2.34.1 |
| 138 | |||
| 139 | diff view generated by jsdifflib |
| 1 | Switch the exynos MCT LFRC timers over to the ptimer transaction API. | 1 | Set the default NaN pattern explicitly for ppc. |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 5 | Message-id: 20191008171740.9679-13-peter.maydell@linaro.org | 5 | Message-id: 20241202131347.498124-46-peter.maydell@linaro.org |
| 6 | --- | 6 | --- |
| 7 | hw/timer/exynos4210_mct.c | 27 +++++++++++++++++++++++---- | 7 | target/ppc/cpu_init.c | 4 ++++ |
| 8 | 1 file changed, 23 insertions(+), 4 deletions(-) | 8 | 1 file changed, 4 insertions(+) |
| 9 | 9 | ||
| 10 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | 10 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c |
| 11 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
| 12 | --- a/hw/timer/exynos4210_mct.c | 12 | --- a/target/ppc/cpu_init.c |
| 13 | +++ b/hw/timer/exynos4210_mct.c | 13 | +++ b/target/ppc/cpu_init.c |
| 14 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_lfrc_get_count(Exynos4210MCTLT *s) | 14 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) |
| 15 | 15 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | |
| 16 | /* | 16 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); |
| 17 | * Set counter of FRC local timer. | 17 | |
| 18 | + * Must be called from within exynos4210_lfrc_tx_begin/commit block. | 18 | + /* Default NaN: sign bit clear, set frac msb */ |
| 19 | */ | 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); |
| 20 | static void exynos4210_lfrc_update_count(Exynos4210MCTLT *s) | 20 | + set_float_default_nan_pattern(0b01000000, &env->vec_status); |
| 21 | { | ||
| 22 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_lfrc_update_count(Exynos4210MCTLT *s) | ||
| 23 | |||
| 24 | /* | ||
| 25 | * Start local FRC timer | ||
| 26 | + * Must be called from within exynos4210_lfrc_tx_begin/commit block. | ||
| 27 | */ | ||
| 28 | static void exynos4210_lfrc_start(Exynos4210MCTLT *s) | ||
| 29 | { | ||
| 30 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_lfrc_start(Exynos4210MCTLT *s) | ||
| 31 | |||
| 32 | /* | ||
| 33 | * Stop local FRC timer | ||
| 34 | + * Must be called from within exynos4210_lfrc_tx_begin/commit block. | ||
| 35 | */ | ||
| 36 | static void exynos4210_lfrc_stop(Exynos4210MCTLT *s) | ||
| 37 | { | ||
| 38 | ptimer_stop(s->ptimer_frc); | ||
| 39 | } | ||
| 40 | |||
| 41 | +/* Start ptimer transaction for local FRC timer */ | ||
| 42 | +static void exynos4210_lfrc_tx_begin(Exynos4210MCTLT *s) | ||
| 43 | +{ | ||
| 44 | + ptimer_transaction_begin(s->ptimer_frc); | ||
| 45 | +} | ||
| 46 | + | 21 | + |
| 47 | +/* Commit ptimer transaction for local FRC timer */ | 22 | for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { |
| 48 | +static void exynos4210_lfrc_tx_commit(Exynos4210MCTLT *s) | 23 | ppc_spr_t *spr = &env->spr_cb[i]; |
| 49 | +{ | ||
| 50 | + ptimer_transaction_commit(s->ptimer_frc); | ||
| 51 | +} | ||
| 52 | + | ||
| 53 | /* | ||
| 54 | * Local timer free running counter tick handler | ||
| 55 | */ | ||
| 56 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s) | ||
| 57 | |||
| 58 | /* local timer */ | ||
| 59 | ptimer_set_freq(s->l_timer[0].tick_timer.ptimer_tick, s->freq); | ||
| 60 | - ptimer_set_freq(s->l_timer[0].ptimer_frc, s->freq); | ||
| 61 | + tx_ptimer_set_freq(s->l_timer[0].ptimer_frc, s->freq); | ||
| 62 | ptimer_set_freq(s->l_timer[1].tick_timer.ptimer_tick, s->freq); | ||
| 63 | - ptimer_set_freq(s->l_timer[1].ptimer_frc, s->freq); | ||
| 64 | + tx_ptimer_set_freq(s->l_timer[1].ptimer_frc, s->freq); | ||
| 65 | } | ||
| 66 | } | ||
| 67 | |||
| 68 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_reset(DeviceState *d) | ||
| 69 | s->l_timer[i].tick_timer.count = 0; | ||
| 70 | s->l_timer[i].tick_timer.distance = 0; | ||
| 71 | s->l_timer[i].tick_timer.progress = 0; | ||
| 72 | + exynos4210_lfrc_tx_begin(&s->l_timer[i]); | ||
| 73 | ptimer_stop(s->l_timer[i].ptimer_frc); | ||
| 74 | + exynos4210_lfrc_tx_commit(&s->l_timer[i]); | ||
| 75 | |||
| 76 | exynos4210_ltick_timer_init(&s->l_timer[i].tick_timer); | ||
| 77 | } | ||
| 78 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
| 79 | } | ||
| 80 | |||
| 81 | /* Start or Stop local FRC if TCON changed */ | ||
| 82 | + exynos4210_lfrc_tx_begin(&s->l_timer[lt_i]); | ||
| 83 | if ((value & L_TCON_FRC_START) > | ||
| 84 | (s->l_timer[lt_i].reg.tcon & L_TCON_FRC_START)) { | ||
| 85 | DPRINTF("local timer[%d] start frc\n", lt_i); | ||
| 86 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
| 87 | DPRINTF("local timer[%d] stop frc\n", lt_i); | ||
| 88 | exynos4210_lfrc_stop(&s->l_timer[lt_i]); | ||
| 89 | } | ||
| 90 | + exynos4210_lfrc_tx_commit(&s->l_timer[lt_i]); | ||
| 91 | break; | ||
| 92 | |||
| 93 | case L0_TCNTB: case L1_TCNTB: | ||
| 94 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_init(Object *obj) | ||
| 95 | /* Local timers */ | ||
| 96 | for (i = 0; i < 2; i++) { | ||
| 97 | bh[0] = qemu_bh_new(exynos4210_ltick_event, &s->l_timer[i]); | ||
| 98 | - bh[1] = qemu_bh_new(exynos4210_lfrc_event, &s->l_timer[i]); | ||
| 99 | s->l_timer[i].tick_timer.ptimer_tick = | ||
| 100 | ptimer_init_with_bh(bh[0], PTIMER_POLICY_DEFAULT); | ||
| 101 | s->l_timer[i].ptimer_frc = | ||
| 102 | - ptimer_init_with_bh(bh[1], PTIMER_POLICY_DEFAULT); | ||
| 103 | + ptimer_init(exynos4210_lfrc_event, &s->l_timer[i], | ||
| 104 | + PTIMER_POLICY_DEFAULT); | ||
| 105 | s->l_timer[i].id = i; | ||
| 106 | } | ||
| 107 | 24 | ||
| 108 | -- | 25 | -- |
| 109 | 2.20.1 | 26 | 2.34.1 |
| 110 | |||
| 111 | diff view generated by jsdifflib |
| 1 | Switch the exynos41210_rtc 1Hz ptimer over to the transaction-based | 1 | Set the default NaN pattern explicitly for sh4. Note that sh4 |
|---|---|---|---|
| 2 | API. (We will switch the other ptimer used by this device in a | 2 | is one of the only three targets (the others being HPPA and |
| 3 | separate commit.) | 3 | sometimes MIPS) that has snan_bit_is_one set. |
| 4 | 4 | ||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 7 | Message-id: 20191008171740.9679-16-peter.maydell@linaro.org | 7 | Message-id: 20241202131347.498124-47-peter.maydell@linaro.org |
| 8 | --- | 8 | --- |
| 9 | hw/timer/exynos4210_rtc.c | 10 ++++++++-- | 9 | target/sh4/cpu.c | 2 ++ |
| 10 | 1 file changed, 8 insertions(+), 2 deletions(-) | 10 | 1 file changed, 2 insertions(+) |
| 11 | 11 | ||
| 12 | diff --git a/hw/timer/exynos4210_rtc.c b/hw/timer/exynos4210_rtc.c | 12 | diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c |
| 13 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 14 | --- a/hw/timer/exynos4210_rtc.c | 14 | --- a/target/sh4/cpu.c |
| 15 | +++ b/hw/timer/exynos4210_rtc.c | 15 | +++ b/target/sh4/cpu.c |
| 16 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset, | 16 | @@ -XXX,XX +XXX,XX @@ static void superh_cpu_reset_hold(Object *obj, ResetType type) |
| 17 | } | 17 | set_flush_to_zero(1, &env->fp_status); |
| 18 | break; | 18 | #endif |
| 19 | case RTCCON: | 19 | set_default_nan_mode(1, &env->fp_status); |
| 20 | + ptimer_transaction_begin(s->ptimer_1Hz); | 20 | + /* sign bit clear, set all frac bits other than msb */ |
| 21 | if (value & RTC_ENABLE) { | 21 | + set_float_default_nan_pattern(0b00111111, &env->fp_status); |
| 22 | exynos4210_rtc_update_freq(s, value); | ||
| 23 | } | ||
| 24 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset, | ||
| 25 | ptimer_stop(s->ptimer); | ||
| 26 | } | ||
| 27 | } | ||
| 28 | + ptimer_transaction_commit(s->ptimer_1Hz); | ||
| 29 | s->reg_rtccon = value; | ||
| 30 | break; | ||
| 31 | case TICCNT: | ||
| 32 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_reset(DeviceState *d) | ||
| 33 | |||
| 34 | exynos4210_rtc_update_freq(s, s->reg_rtccon); | ||
| 35 | ptimer_stop(s->ptimer); | ||
| 36 | + ptimer_transaction_begin(s->ptimer_1Hz); | ||
| 37 | ptimer_stop(s->ptimer_1Hz); | ||
| 38 | + ptimer_transaction_commit(s->ptimer_1Hz); | ||
| 39 | } | 22 | } |
| 40 | 23 | ||
| 41 | static const MemoryRegionOps exynos4210_rtc_ops = { | 24 | static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) |
| 42 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_init(Object *obj) | ||
| 43 | ptimer_set_freq(s->ptimer, RTC_BASE_FREQ); | ||
| 44 | exynos4210_rtc_update_freq(s, 0); | ||
| 45 | |||
| 46 | - bh = qemu_bh_new(exynos4210_rtc_1Hz_tick, s); | ||
| 47 | - s->ptimer_1Hz = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
| 48 | + s->ptimer_1Hz = ptimer_init(exynos4210_rtc_1Hz_tick, | ||
| 49 | + s, PTIMER_POLICY_DEFAULT); | ||
| 50 | + ptimer_transaction_begin(s->ptimer_1Hz); | ||
| 51 | ptimer_set_freq(s->ptimer_1Hz, RTC_BASE_FREQ); | ||
| 52 | + ptimer_transaction_commit(s->ptimer_1Hz); | ||
| 53 | |||
| 54 | sysbus_init_irq(dev, &s->alm_irq); | ||
| 55 | sysbus_init_irq(dev, &s->tick_irq); | ||
| 56 | -- | 25 | -- |
| 57 | 2.20.1 | 26 | 2.34.1 |
| 58 | |||
| 59 | diff view generated by jsdifflib |
| 1 | Switch the ltick ptimer over to the ptimer transaction API. | 1 | Set the default NaN pattern explicitly for rx. |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 5 | Message-id: 20191008171740.9679-14-peter.maydell@linaro.org | 5 | Message-id: 20241202131347.498124-48-peter.maydell@linaro.org |
| 6 | --- | 6 | --- |
| 7 | hw/timer/exynos4210_mct.c | 31 +++++++++++++++++++++++++------ | 7 | target/rx/cpu.c | 2 ++ |
| 8 | 1 file changed, 25 insertions(+), 6 deletions(-) | 8 | 1 file changed, 2 insertions(+) |
| 9 | 9 | ||
| 10 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | 10 | diff --git a/target/rx/cpu.c b/target/rx/cpu.c |
| 11 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
| 12 | --- a/hw/timer/exynos4210_mct.c | 12 | --- a/target/rx/cpu.c |
| 13 | +++ b/hw/timer/exynos4210_mct.c | 13 | +++ b/target/rx/cpu.c |
| 14 | @@ -XXX,XX +XXX,XX @@ | 14 | @@ -XXX,XX +XXX,XX @@ static void rx_cpu_reset_hold(Object *obj, ResetType type) |
| 15 | #include "hw/sysbus.h" | 15 | * then prefer dest over source", which is float_2nan_prop_s_ab. |
| 16 | #include "migration/vmstate.h" | 16 | */ |
| 17 | #include "qemu/timer.h" | 17 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); |
| 18 | -#include "qemu/main-loop.h" | 18 | + /* Default NaN value: sign bit clear, set frac msb */ |
| 19 | #include "qemu/module.h" | 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); |
| 20 | #include "hw/ptimer.h" | ||
| 21 | |||
| 22 | @@ -XXX,XX +XXX,XX @@ static uint32_t exynos4210_ltick_int_get_cnto(struct tick_timer *s) | ||
| 23 | |||
| 24 | /* | ||
| 25 | * Start local tick cnt timer. | ||
| 26 | + * Must be called within exynos4210_ltick_tx_begin/commit block. | ||
| 27 | */ | ||
| 28 | static void exynos4210_ltick_cnt_start(struct tick_timer *s) | ||
| 29 | { | ||
| 30 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_ltick_cnt_start(struct tick_timer *s) | ||
| 31 | |||
| 32 | /* | ||
| 33 | * Stop local tick cnt timer. | ||
| 34 | + * Must be called within exynos4210_ltick_tx_begin/commit block. | ||
| 35 | */ | ||
| 36 | static void exynos4210_ltick_cnt_stop(struct tick_timer *s) | ||
| 37 | { | ||
| 38 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_ltick_cnt_stop(struct tick_timer *s) | ||
| 39 | } | ||
| 40 | } | 20 | } |
| 41 | 21 | ||
| 42 | +/* Start ptimer transaction for local tick timer */ | 22 | static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) |
| 43 | +static void exynos4210_ltick_tx_begin(struct tick_timer *s) | ||
| 44 | +{ | ||
| 45 | + ptimer_transaction_begin(s->ptimer_tick); | ||
| 46 | +} | ||
| 47 | + | ||
| 48 | +/* Commit ptimer transaction for local tick timer */ | ||
| 49 | +static void exynos4210_ltick_tx_commit(struct tick_timer *s) | ||
| 50 | +{ | ||
| 51 | + ptimer_transaction_commit(s->ptimer_tick); | ||
| 52 | +} | ||
| 53 | + | ||
| 54 | /* | ||
| 55 | * Get counter for CNT timer | ||
| 56 | */ | ||
| 57 | @@ -XXX,XX +XXX,XX @@ static uint32_t exynos4210_ltick_cnt_get_cnto(struct tick_timer *s) | ||
| 58 | |||
| 59 | /* | ||
| 60 | * Set new values of counters for CNT and INT timers | ||
| 61 | + * Must be called within exynos4210_ltick_tx_begin/commit block. | ||
| 62 | */ | ||
| 63 | static void exynos4210_ltick_set_cntb(struct tick_timer *s, uint32_t new_cnt, | ||
| 64 | uint32_t new_int) | ||
| 65 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_ltick_recalc_count(struct tick_timer *s) | ||
| 66 | static void exynos4210_ltick_timer_init(struct tick_timer *s) | ||
| 67 | { | ||
| 68 | exynos4210_ltick_int_stop(s); | ||
| 69 | + exynos4210_ltick_tx_begin(s); | ||
| 70 | exynos4210_ltick_cnt_stop(s); | ||
| 71 | + exynos4210_ltick_tx_commit(s); | ||
| 72 | |||
| 73 | s->count = 0; | ||
| 74 | s->distance = 0; | ||
| 75 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s) | ||
| 76 | tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq); | ||
| 77 | |||
| 78 | /* local timer */ | ||
| 79 | - ptimer_set_freq(s->l_timer[0].tick_timer.ptimer_tick, s->freq); | ||
| 80 | + tx_ptimer_set_freq(s->l_timer[0].tick_timer.ptimer_tick, s->freq); | ||
| 81 | tx_ptimer_set_freq(s->l_timer[0].ptimer_frc, s->freq); | ||
| 82 | - ptimer_set_freq(s->l_timer[1].tick_timer.ptimer_tick, s->freq); | ||
| 83 | + tx_ptimer_set_freq(s->l_timer[1].tick_timer.ptimer_tick, s->freq); | ||
| 84 | tx_ptimer_set_freq(s->l_timer[1].ptimer_frc, s->freq); | ||
| 85 | } | ||
| 86 | } | ||
| 87 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
| 88 | s->l_timer[lt_i].reg.wstat |= L_WSTAT_TCON_WRITE; | ||
| 89 | s->l_timer[lt_i].reg.tcon = value; | ||
| 90 | |||
| 91 | + exynos4210_ltick_tx_begin(&s->l_timer[lt_i].tick_timer); | ||
| 92 | /* Stop local CNT */ | ||
| 93 | if ((value & L_TCON_TICK_START) < | ||
| 94 | (old_val & L_TCON_TICK_START)) { | ||
| 95 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
| 96 | DPRINTF("local timer[%d] start int\n", lt_i); | ||
| 97 | exynos4210_ltick_int_start(&s->l_timer[lt_i].tick_timer); | ||
| 98 | } | ||
| 99 | + exynos4210_ltick_tx_commit(&s->l_timer[lt_i].tick_timer); | ||
| 100 | |||
| 101 | /* Start or Stop local FRC if TCON changed */ | ||
| 102 | exynos4210_lfrc_tx_begin(&s->l_timer[lt_i]); | ||
| 103 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
| 104 | * Due to this we should reload timer to nearest moment when CNT is | ||
| 105 | * expired and then in event handler update tcntb to new TCNTB value. | ||
| 106 | */ | ||
| 107 | + exynos4210_ltick_tx_begin(&s->l_timer[lt_i].tick_timer); | ||
| 108 | exynos4210_ltick_set_cntb(&s->l_timer[lt_i].tick_timer, value, | ||
| 109 | s->l_timer[lt_i].tick_timer.icntb); | ||
| 110 | + exynos4210_ltick_tx_commit(&s->l_timer[lt_i].tick_timer); | ||
| 111 | |||
| 112 | s->l_timer[lt_i].reg.wstat |= L_WSTAT_TCNTB_WRITE; | ||
| 113 | s->l_timer[lt_i].reg.cnt[L_REG_CNT_TCNTB] = value; | ||
| 114 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_init(Object *obj) | ||
| 115 | int i; | ||
| 116 | Exynos4210MCTState *s = EXYNOS4210_MCT(obj); | ||
| 117 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | ||
| 118 | - QEMUBH *bh[2]; | ||
| 119 | |||
| 120 | /* Global timer */ | ||
| 121 | s->g_timer.ptimer_frc = ptimer_init(exynos4210_gfrc_event, s, | ||
| 122 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_init(Object *obj) | ||
| 123 | |||
| 124 | /* Local timers */ | ||
| 125 | for (i = 0; i < 2; i++) { | ||
| 126 | - bh[0] = qemu_bh_new(exynos4210_ltick_event, &s->l_timer[i]); | ||
| 127 | s->l_timer[i].tick_timer.ptimer_tick = | ||
| 128 | - ptimer_init_with_bh(bh[0], PTIMER_POLICY_DEFAULT); | ||
| 129 | + ptimer_init(exynos4210_ltick_event, &s->l_timer[i], | ||
| 130 | + PTIMER_POLICY_DEFAULT); | ||
| 131 | s->l_timer[i].ptimer_frc = | ||
| 132 | ptimer_init(exynos4210_lfrc_event, &s->l_timer[i], | ||
| 133 | PTIMER_POLICY_DEFAULT); | ||
| 134 | -- | 23 | -- |
| 135 | 2.20.1 | 24 | 2.34.1 |
| 136 | |||
| 137 | diff view generated by jsdifflib |
| 1 | Switch the exynos41210_rtc main ptimer over to the transaction-based | 1 | Set the default NaN pattern explicitly for s390x. |
|---|---|---|---|
| 2 | API, completing the transition for this device. | ||
| 3 | 2 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 6 | Message-id: 20191008171740.9679-17-peter.maydell@linaro.org | 5 | Message-id: 20241202131347.498124-49-peter.maydell@linaro.org |
| 7 | --- | 6 | --- |
| 8 | hw/timer/exynos4210_rtc.c | 12 ++++++++---- | 7 | target/s390x/cpu.c | 2 ++ |
| 9 | 1 file changed, 8 insertions(+), 4 deletions(-) | 8 | 1 file changed, 2 insertions(+) |
| 10 | 9 | ||
| 11 | diff --git a/hw/timer/exynos4210_rtc.c b/hw/timer/exynos4210_rtc.c | 10 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c |
| 12 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
| 13 | --- a/hw/timer/exynos4210_rtc.c | 12 | --- a/target/s390x/cpu.c |
| 14 | +++ b/hw/timer/exynos4210_rtc.c | 13 | +++ b/target/s390x/cpu.c |
| 15 | @@ -XXX,XX +XXX,XX @@ | 14 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) |
| 16 | #include "qemu/osdep.h" | 15 | set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status); |
| 17 | #include "qemu-common.h" | 16 | set_float_infzeronan_rule(float_infzeronan_dnan_always, |
| 18 | #include "qemu/log.h" | 17 | &env->fpu_status); |
| 19 | -#include "qemu/main-loop.h" | 18 | + /* Default NaN value: sign bit clear, frac msb set */ |
| 20 | #include "qemu/module.h" | 19 | + set_float_default_nan_pattern(0b01000000, &env->fpu_status); |
| 21 | #include "hw/sysbus.h" | 20 | /* fall through */ |
| 22 | #include "migration/vmstate.h" | 21 | case RESET_TYPE_S390_CPU_NORMAL: |
| 23 | @@ -XXX,XX +XXX,XX @@ static void check_alarm_raise(Exynos4210RTCState *s) | 22 | env->psw.mask &= ~PSW_MASK_RI; |
| 24 | * RTC update frequency | ||
| 25 | * Parameters: | ||
| 26 | * reg_value - current RTCCON register or his new value | ||
| 27 | + * Must be called within a ptimer_transaction_begin/commit block for s->ptimer. | ||
| 28 | */ | ||
| 29 | static void exynos4210_rtc_update_freq(Exynos4210RTCState *s, | ||
| 30 | uint32_t reg_value) | ||
| 31 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset, | ||
| 32 | break; | ||
| 33 | case RTCCON: | ||
| 34 | ptimer_transaction_begin(s->ptimer_1Hz); | ||
| 35 | + ptimer_transaction_begin(s->ptimer); | ||
| 36 | if (value & RTC_ENABLE) { | ||
| 37 | exynos4210_rtc_update_freq(s, value); | ||
| 38 | } | ||
| 39 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset, | ||
| 40 | } | ||
| 41 | } | ||
| 42 | ptimer_transaction_commit(s->ptimer_1Hz); | ||
| 43 | + ptimer_transaction_commit(s->ptimer); | ||
| 44 | s->reg_rtccon = value; | ||
| 45 | break; | ||
| 46 | case TICCNT: | ||
| 47 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_reset(DeviceState *d) | ||
| 48 | |||
| 49 | s->reg_curticcnt = 0; | ||
| 50 | |||
| 51 | + ptimer_transaction_begin(s->ptimer); | ||
| 52 | exynos4210_rtc_update_freq(s, s->reg_rtccon); | ||
| 53 | ptimer_stop(s->ptimer); | ||
| 54 | + ptimer_transaction_commit(s->ptimer); | ||
| 55 | ptimer_transaction_begin(s->ptimer_1Hz); | ||
| 56 | ptimer_stop(s->ptimer_1Hz); | ||
| 57 | ptimer_transaction_commit(s->ptimer_1Hz); | ||
| 58 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_init(Object *obj) | ||
| 59 | { | ||
| 60 | Exynos4210RTCState *s = EXYNOS4210_RTC(obj); | ||
| 61 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | ||
| 62 | - QEMUBH *bh; | ||
| 63 | |||
| 64 | - bh = qemu_bh_new(exynos4210_rtc_tick, s); | ||
| 65 | - s->ptimer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
| 66 | + s->ptimer = ptimer_init(exynos4210_rtc_tick, s, PTIMER_POLICY_DEFAULT); | ||
| 67 | + ptimer_transaction_begin(s->ptimer); | ||
| 68 | ptimer_set_freq(s->ptimer, RTC_BASE_FREQ); | ||
| 69 | exynos4210_rtc_update_freq(s, 0); | ||
| 70 | + ptimer_transaction_commit(s->ptimer); | ||
| 71 | |||
| 72 | s->ptimer_1Hz = ptimer_init(exynos4210_rtc_1Hz_tick, | ||
| 73 | s, PTIMER_POLICY_DEFAULT); | ||
| 74 | -- | 23 | -- |
| 75 | 2.20.1 | 24 | 2.34.1 |
| 76 | |||
| 77 | diff view generated by jsdifflib |
| 1 | We want to switch the exynos MCT code away from bottom-half based ptimers to | 1 | Set the default NaN pattern explicitly for SPARC, and remove |
|---|---|---|---|
| 2 | the new transaction-based ptimer API. The MCT is complicated | 2 | the ifdef from parts64_default_nan. |
| 3 | and uses multiple different ptimers, so it's clearer to switch | ||
| 4 | it a piece at a time. Here we change over only the GFRC. | ||
| 5 | 3 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Message-id: 20191008171740.9679-12-peter.maydell@linaro.org | 6 | Message-id: 20241202131347.498124-50-peter.maydell@linaro.org |
| 9 | --- | 7 | --- |
| 10 | hw/timer/exynos4210_mct.c | 48 ++++++++++++++++++++++++++++++++++++--- | 8 | target/sparc/cpu.c | 2 ++ |
| 11 | 1 file changed, 45 insertions(+), 3 deletions(-) | 9 | fpu/softfloat-specialize.c.inc | 5 +---- |
| 10 | 2 files changed, 3 insertions(+), 4 deletions(-) | ||
| 12 | 11 | ||
| 13 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | 12 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c |
| 14 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/hw/timer/exynos4210_mct.c | 14 | --- a/target/sparc/cpu.c |
| 16 | +++ b/hw/timer/exynos4210_mct.c | 15 | +++ b/target/sparc/cpu.c |
| 17 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s); | 16 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) |
| 18 | 17 | set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); | |
| 19 | /* | 18 | /* For inf * 0 + NaN, return the input NaN */ |
| 20 | * Set counter of FRC global timer. | 19 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); |
| 21 | + * Must be called within exynos4210_gfrc_tx_begin/commit block. | 20 | + /* Default NaN value: sign bit clear, all frac bits set */ |
| 22 | */ | 21 | + set_float_default_nan_pattern(0b01111111, &env->fp_status); |
| 23 | static void exynos4210_gfrc_set_count(Exynos4210MCTGT *s, uint64_t count) | 22 | |
| 24 | { | 23 | cpu_exec_realizefn(cs, &local_err); |
| 25 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_gfrc_get_count(Exynos4210MCTGT *s) | 24 | if (local_err != NULL) { |
| 26 | 25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | |
| 27 | /* | 26 | index XXXXXXX..XXXXXXX 100644 |
| 28 | * Stop global FRC timer | 27 | --- a/fpu/softfloat-specialize.c.inc |
| 29 | + * Must be called within exynos4210_gfrc_tx_begin/commit block. | 28 | +++ b/fpu/softfloat-specialize.c.inc |
| 30 | */ | 29 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) |
| 31 | static void exynos4210_gfrc_stop(Exynos4210MCTGT *s) | 30 | uint8_t dnan_pattern = status->default_nan_pattern; |
| 32 | { | 31 | |
| 33 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gfrc_stop(Exynos4210MCTGT *s) | 32 | if (dnan_pattern == 0) { |
| 34 | 33 | -#if defined(TARGET_SPARC) | |
| 35 | /* | 34 | - /* Sign bit clear, all frac bits set */ |
| 36 | * Start global FRC timer | 35 | - dnan_pattern = 0b01111111; |
| 37 | + * Must be called within exynos4210_gfrc_tx_begin/commit block. | 36 | -#elif defined(TARGET_HEXAGON) |
| 38 | */ | 37 | +#if defined(TARGET_HEXAGON) |
| 39 | static void exynos4210_gfrc_start(Exynos4210MCTGT *s) | 38 | /* Sign bit set, all frac bits set. */ |
| 40 | { | 39 | dnan_pattern = 0b11111111; |
| 41 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gfrc_start(Exynos4210MCTGT *s) | 40 | #else |
| 42 | ptimer_run(s->ptimer_frc, 1); | ||
| 43 | } | ||
| 44 | |||
| 45 | +/* | ||
| 46 | + * Start ptimer transaction for global FRC timer; this is just for | ||
| 47 | + * consistency with the way we wrap operations like stop and run. | ||
| 48 | + */ | ||
| 49 | +static void exynos4210_gfrc_tx_begin(Exynos4210MCTGT *s) | ||
| 50 | +{ | ||
| 51 | + ptimer_transaction_begin(s->ptimer_frc); | ||
| 52 | +} | ||
| 53 | + | ||
| 54 | +/* Commit ptimer transaction for global FRC timer. */ | ||
| 55 | +static void exynos4210_gfrc_tx_commit(Exynos4210MCTGT *s) | ||
| 56 | +{ | ||
| 57 | + ptimer_transaction_commit(s->ptimer_frc); | ||
| 58 | +} | ||
| 59 | + | ||
| 60 | /* | ||
| 61 | * Find next nearest Comparator. If current Comparator value equals to other | ||
| 62 | * Comparator value, skip them both | ||
| 63 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_gcomp_get_distance(Exynos4210MCTState *s, int32_t id) | ||
| 64 | |||
| 65 | /* | ||
| 66 | * Restart global FRC timer | ||
| 67 | + * Must be called within exynos4210_gfrc_tx_begin/commit block. | ||
| 68 | */ | ||
| 69 | static void exynos4210_gfrc_restart(Exynos4210MCTState *s) | ||
| 70 | { | ||
| 71 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_ltick_event(void *opaque) | ||
| 72 | exynos4210_ltick_int_start(&s->tick_timer); | ||
| 73 | } | ||
| 74 | |||
| 75 | +static void tx_ptimer_set_freq(ptimer_state *s, uint32_t freq) | ||
| 76 | +{ | ||
| 77 | + /* | ||
| 78 | + * callers of exynos4210_mct_update_freq() never do anything | ||
| 79 | + * else that needs to be in the same ptimer transaction, so | ||
| 80 | + * to avoid a lot of repetition we have a convenience function | ||
| 81 | + * for begin/set_freq/commit. | ||
| 82 | + */ | ||
| 83 | + ptimer_transaction_begin(s); | ||
| 84 | + ptimer_set_freq(s, freq); | ||
| 85 | + ptimer_transaction_commit(s); | ||
| 86 | +} | ||
| 87 | + | ||
| 88 | /* update timer frequency */ | ||
| 89 | static void exynos4210_mct_update_freq(Exynos4210MCTState *s) | ||
| 90 | { | ||
| 91 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s) | ||
| 92 | DPRINTF("freq=%dHz\n", s->freq); | ||
| 93 | |||
| 94 | /* global timer */ | ||
| 95 | - ptimer_set_freq(s->g_timer.ptimer_frc, s->freq); | ||
| 96 | + tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq); | ||
| 97 | |||
| 98 | /* local timer */ | ||
| 99 | ptimer_set_freq(s->l_timer[0].tick_timer.ptimer_tick, s->freq); | ||
| 100 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_reset(DeviceState *d) | ||
| 101 | |||
| 102 | /* global timer */ | ||
| 103 | memset(&s->g_timer.reg, 0, sizeof(s->g_timer.reg)); | ||
| 104 | + exynos4210_gfrc_tx_begin(&s->g_timer); | ||
| 105 | exynos4210_gfrc_stop(&s->g_timer); | ||
| 106 | + exynos4210_gfrc_tx_commit(&s->g_timer); | ||
| 107 | |||
| 108 | /* local timer */ | ||
| 109 | memset(s->l_timer[0].reg.cnt, 0, sizeof(s->l_timer[0].reg.cnt)); | ||
| 110 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
| 111 | } | ||
| 112 | |||
| 113 | s->g_timer.reg.cnt = new_frc; | ||
| 114 | + exynos4210_gfrc_tx_begin(&s->g_timer); | ||
| 115 | exynos4210_gfrc_restart(s); | ||
| 116 | + exynos4210_gfrc_tx_commit(&s->g_timer); | ||
| 117 | break; | ||
| 118 | |||
| 119 | case G_CNT_WSTAT: | ||
| 120 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
| 121 | s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index); | ||
| 122 | } | ||
| 123 | |||
| 124 | + exynos4210_gfrc_tx_begin(&s->g_timer); | ||
| 125 | exynos4210_gfrc_restart(s); | ||
| 126 | + exynos4210_gfrc_tx_commit(&s->g_timer); | ||
| 127 | break; | ||
| 128 | |||
| 129 | case G_TCON: | ||
| 130 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
| 131 | |||
| 132 | DPRINTF("global timer write to reg.g_tcon %llx\n", value); | ||
| 133 | |||
| 134 | + exynos4210_gfrc_tx_begin(&s->g_timer); | ||
| 135 | + | ||
| 136 | /* Start FRC if transition from disabled to enabled */ | ||
| 137 | if ((value & G_TCON_TIMER_ENABLE) > (old_val & | ||
| 138 | G_TCON_TIMER_ENABLE)) { | ||
| 139 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
| 140 | exynos4210_gfrc_restart(s); | ||
| 141 | } | ||
| 142 | } | ||
| 143 | + | ||
| 144 | + exynos4210_gfrc_tx_commit(&s->g_timer); | ||
| 145 | break; | ||
| 146 | |||
| 147 | case G_INT_CSTAT: | ||
| 148 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_init(Object *obj) | ||
| 149 | QEMUBH *bh[2]; | ||
| 150 | |||
| 151 | /* Global timer */ | ||
| 152 | - bh[0] = qemu_bh_new(exynos4210_gfrc_event, s); | ||
| 153 | - s->g_timer.ptimer_frc = ptimer_init_with_bh(bh[0], PTIMER_POLICY_DEFAULT); | ||
| 154 | + s->g_timer.ptimer_frc = ptimer_init(exynos4210_gfrc_event, s, | ||
| 155 | + PTIMER_POLICY_DEFAULT); | ||
| 156 | memset(&s->g_timer.reg, 0, sizeof(struct gregs)); | ||
| 157 | |||
| 158 | /* Local timers */ | ||
| 159 | -- | 41 | -- |
| 160 | 2.20.1 | 42 | 2.34.1 |
| 161 | |||
| 162 | diff view generated by jsdifflib |
| 1 | Currently the ptimer design uses a QEMU bottom-half as its | 1 | Set the default NaN pattern explicitly for xtensa. |
|---|---|---|---|
| 2 | mechanism for calling back into the device model using the | ||
| 3 | ptimer when the timer has expired. Unfortunately this design | ||
| 4 | is fatally flawed, because it means that there is a lag | ||
| 5 | between the ptimer updating its own state and the device | ||
| 6 | callback function updating device state, and guest accesses | ||
| 7 | to device registers between the two can return inconsistent | ||
| 8 | device state. | ||
| 9 | |||
| 10 | We want to replace the bottom-half design with one where | ||
| 11 | the guest device's callback is called either immediately | ||
| 12 | (when the ptimer triggers by timeout) or when the device | ||
| 13 | model code closes a transaction-begin/end section (when the | ||
| 14 | ptimer triggers because the device model changed the | ||
| 15 | ptimer's count value or other state). As the first step, | ||
| 16 | rename ptimer_init() to ptimer_init_with_bh(), to free up | ||
| 17 | the ptimer_init() name for the new API. We can then convert | ||
| 18 | all the ptimer users away from ptimer_init_with_bh() before | ||
| 19 | removing it entirely. | ||
| 20 | |||
| 21 | (Commit created with | ||
| 22 | git grep -l ptimer_init | xargs sed -i -e 's/ptimer_init/ptimer_init_with_bh/' | ||
| 23 | and three overlong lines folded by hand.) | ||
| 24 | 2 | ||
| 25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 26 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 27 | Message-id: 20191008171740.9679-2-peter.maydell@linaro.org | 5 | Message-id: 20241202131347.498124-51-peter.maydell@linaro.org |
| 28 | --- | 6 | --- |
| 29 | include/hw/ptimer.h | 11 ++++++----- | 7 | target/xtensa/cpu.c | 2 ++ |
| 30 | hw/arm/musicpal.c | 2 +- | 8 | 1 file changed, 2 insertions(+) |
| 31 | hw/core/ptimer.c | 2 +- | ||
| 32 | hw/dma/xilinx_axidma.c | 2 +- | ||
| 33 | hw/m68k/mcf5206.c | 2 +- | ||
| 34 | hw/m68k/mcf5208.c | 2 +- | ||
| 35 | hw/net/fsl_etsec/etsec.c | 2 +- | ||
| 36 | hw/net/lan9118.c | 2 +- | ||
| 37 | hw/timer/allwinner-a10-pit.c | 2 +- | ||
| 38 | hw/timer/altera_timer.c | 2 +- | ||
| 39 | hw/timer/arm_mptimer.c | 6 +++--- | ||
| 40 | hw/timer/arm_timer.c | 2 +- | ||
| 41 | hw/timer/cmsdk-apb-dualtimer.c | 2 +- | ||
| 42 | hw/timer/cmsdk-apb-timer.c | 2 +- | ||
| 43 | hw/timer/digic-timer.c | 2 +- | ||
| 44 | hw/timer/etraxfs_timer.c | 6 +++--- | ||
| 45 | hw/timer/exynos4210_mct.c | 7 ++++--- | ||
| 46 | hw/timer/exynos4210_pwm.c | 2 +- | ||
| 47 | hw/timer/exynos4210_rtc.c | 4 ++-- | ||
| 48 | hw/timer/grlib_gptimer.c | 2 +- | ||
| 49 | hw/timer/imx_epit.c | 4 ++-- | ||
| 50 | hw/timer/imx_gpt.c | 2 +- | ||
| 51 | hw/timer/lm32_timer.c | 2 +- | ||
| 52 | hw/timer/milkymist-sysctl.c | 4 ++-- | ||
| 53 | hw/timer/mss-timer.c | 2 +- | ||
| 54 | hw/timer/puv3_ost.c | 2 +- | ||
| 55 | hw/timer/sh_timer.c | 2 +- | ||
| 56 | hw/timer/slavio_timer.c | 2 +- | ||
| 57 | hw/timer/xilinx_timer.c | 2 +- | ||
| 58 | hw/watchdog/cmsdk-apb-watchdog.c | 2 +- | ||
| 59 | tests/ptimer-test.c | 22 +++++++++++----------- | ||
| 60 | 31 files changed, 56 insertions(+), 54 deletions(-) | ||
| 61 | 9 | ||
| 62 | diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h | 10 | diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c |
| 63 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
| 64 | --- a/include/hw/ptimer.h | 12 | --- a/target/xtensa/cpu.c |
| 65 | +++ b/include/hw/ptimer.h | 13 | +++ b/target/xtensa/cpu.c |
| 66 | @@ -XXX,XX +XXX,XX @@ | 14 | @@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) |
| 67 | * ptimer_set_count() or ptimer_set_limit() will not trigger the timer | 15 | /* For inf * 0 + NaN, return the input NaN */ |
| 68 | * (though it will cause a reload). Only a counter decrement to "0" | 16 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); |
| 69 | * will cause a trigger. Not compatible with NO_IMMEDIATE_TRIGGER; | 17 | set_no_signaling_nans(!dfpu, &env->fp_status); |
| 70 | - * ptimer_init() will assert() that you don't set both. | 18 | + /* Default NaN value: sign bit clear, set frac msb */ |
| 71 | + * ptimer_init_with_bh() will assert() that you don't set both. | 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); |
| 72 | */ | 20 | xtensa_use_first_nan(env, !dfpu); |
| 73 | #define PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT (1 << 5) | ||
| 74 | |||
| 75 | @@ -XXX,XX +XXX,XX @@ typedef struct ptimer_state ptimer_state; | ||
| 76 | typedef void (*ptimer_cb)(void *opaque); | ||
| 77 | |||
| 78 | /** | ||
| 79 | - * ptimer_init - Allocate and return a new ptimer | ||
| 80 | + * ptimer_init_with_bh - Allocate and return a new ptimer | ||
| 81 | * @bh: QEMU bottom half which is run on timer expiry | ||
| 82 | * @policy: PTIMER_POLICY_* bits specifying behaviour | ||
| 83 | * | ||
| 84 | @@ -XXX,XX +XXX,XX @@ typedef void (*ptimer_cb)(void *opaque); | ||
| 85 | * The ptimer takes ownership of @bh and will delete it | ||
| 86 | * when the ptimer is eventually freed. | ||
| 87 | */ | ||
| 88 | -ptimer_state *ptimer_init(QEMUBH *bh, uint8_t policy_mask); | ||
| 89 | +ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask); | ||
| 90 | |||
| 91 | /** | ||
| 92 | * ptimer_free - Free a ptimer | ||
| 93 | * @s: timer to free | ||
| 94 | * | ||
| 95 | - * Free a ptimer created using ptimer_init() (including | ||
| 96 | + * Free a ptimer created using ptimer_init_with_bh() (including | ||
| 97 | * deleting the bottom half which it is using). | ||
| 98 | */ | ||
| 99 | void ptimer_free(ptimer_state *s); | ||
| 100 | @@ -XXX,XX +XXX,XX @@ void ptimer_set_count(ptimer_state *s, uint64_t count); | ||
| 101 | * @oneshot: non-zero if this timer should only count down once | ||
| 102 | * | ||
| 103 | * Start a ptimer counting down; when it reaches zero the bottom half | ||
| 104 | - * passed to ptimer_init() will be invoked. If the @oneshot argument is zero, | ||
| 105 | + * passed to ptimer_init_with_bh() will be invoked. | ||
| 106 | + * If the @oneshot argument is zero, | ||
| 107 | * the counter value will then be reloaded from the limit and it will | ||
| 108 | * start counting down again. If @oneshot is non-zero, then the counter | ||
| 109 | * will disable itself when it reaches zero. | ||
| 110 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c | ||
| 111 | index XXXXXXX..XXXXXXX 100644 | ||
| 112 | --- a/hw/arm/musicpal.c | ||
| 113 | +++ b/hw/arm/musicpal.c | ||
| 114 | @@ -XXX,XX +XXX,XX @@ static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, | ||
| 115 | s->freq = freq; | ||
| 116 | |||
| 117 | bh = qemu_bh_new(mv88w8618_timer_tick, s); | ||
| 118 | - s->ptimer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
| 119 | + s->ptimer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
| 120 | } | 21 | } |
| 121 | 22 | ||
| 122 | static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset, | ||
| 123 | diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c | ||
| 124 | index XXXXXXX..XXXXXXX 100644 | ||
| 125 | --- a/hw/core/ptimer.c | ||
| 126 | +++ b/hw/core/ptimer.c | ||
| 127 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_ptimer = { | ||
| 128 | } | ||
| 129 | }; | ||
| 130 | |||
| 131 | -ptimer_state *ptimer_init(QEMUBH *bh, uint8_t policy_mask) | ||
| 132 | +ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask) | ||
| 133 | { | ||
| 134 | ptimer_state *s; | ||
| 135 | |||
| 136 | diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c | ||
| 137 | index XXXXXXX..XXXXXXX 100644 | ||
| 138 | --- a/hw/dma/xilinx_axidma.c | ||
| 139 | +++ b/hw/dma/xilinx_axidma.c | ||
| 140 | @@ -XXX,XX +XXX,XX @@ static void xilinx_axidma_realize(DeviceState *dev, Error **errp) | ||
| 141 | |||
| 142 | st->nr = i; | ||
| 143 | st->bh = qemu_bh_new(timer_hit, st); | ||
| 144 | - st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT); | ||
| 145 | + st->ptimer = ptimer_init_with_bh(st->bh, PTIMER_POLICY_DEFAULT); | ||
| 146 | ptimer_set_freq(st->ptimer, s->freqhz); | ||
| 147 | } | ||
| 148 | return; | ||
| 149 | diff --git a/hw/m68k/mcf5206.c b/hw/m68k/mcf5206.c | ||
| 150 | index XXXXXXX..XXXXXXX 100644 | ||
| 151 | --- a/hw/m68k/mcf5206.c | ||
| 152 | +++ b/hw/m68k/mcf5206.c | ||
| 153 | @@ -XXX,XX +XXX,XX @@ static m5206_timer_state *m5206_timer_init(qemu_irq irq) | ||
| 154 | |||
| 155 | s = g_new0(m5206_timer_state, 1); | ||
| 156 | bh = qemu_bh_new(m5206_timer_trigger, s); | ||
| 157 | - s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
| 158 | + s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
| 159 | s->irq = irq; | ||
| 160 | m5206_timer_reset(s); | ||
| 161 | return s; | ||
| 162 | diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c | ||
| 163 | index XXXXXXX..XXXXXXX 100644 | ||
| 164 | --- a/hw/m68k/mcf5208.c | ||
| 165 | +++ b/hw/m68k/mcf5208.c | ||
| 166 | @@ -XXX,XX +XXX,XX @@ static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic) | ||
| 167 | for (i = 0; i < 2; i++) { | ||
| 168 | s = g_new0(m5208_timer_state, 1); | ||
| 169 | bh = qemu_bh_new(m5208_timer_trigger, s); | ||
| 170 | - s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
| 171 | + s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
| 172 | memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s, | ||
| 173 | "m5208-timer", 0x00004000); | ||
| 174 | memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i, | ||
| 175 | diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c | ||
| 176 | index XXXXXXX..XXXXXXX 100644 | ||
| 177 | --- a/hw/net/fsl_etsec/etsec.c | ||
| 178 | +++ b/hw/net/fsl_etsec/etsec.c | ||
| 179 | @@ -XXX,XX +XXX,XX @@ static void etsec_realize(DeviceState *dev, Error **errp) | ||
| 180 | |||
| 181 | |||
| 182 | etsec->bh = qemu_bh_new(etsec_timer_hit, etsec); | ||
| 183 | - etsec->ptimer = ptimer_init(etsec->bh, PTIMER_POLICY_DEFAULT); | ||
| 184 | + etsec->ptimer = ptimer_init_with_bh(etsec->bh, PTIMER_POLICY_DEFAULT); | ||
| 185 | ptimer_set_freq(etsec->ptimer, 100); | ||
| 186 | } | ||
| 187 | |||
| 188 | diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c | ||
| 189 | index XXXXXXX..XXXXXXX 100644 | ||
| 190 | --- a/hw/net/lan9118.c | ||
| 191 | +++ b/hw/net/lan9118.c | ||
| 192 | @@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp) | ||
| 193 | s->txp = &s->tx_packet; | ||
| 194 | |||
| 195 | bh = qemu_bh_new(lan9118_tick, s); | ||
| 196 | - s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
| 197 | + s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
| 198 | ptimer_set_freq(s->timer, 10000); | ||
| 199 | ptimer_set_limit(s->timer, 0xffff, 1); | ||
| 200 | } | ||
| 201 | diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c | ||
| 202 | index XXXXXXX..XXXXXXX 100644 | ||
| 203 | --- a/hw/timer/allwinner-a10-pit.c | ||
| 204 | +++ b/hw/timer/allwinner-a10-pit.c | ||
| 205 | @@ -XXX,XX +XXX,XX @@ static void a10_pit_init(Object *obj) | ||
| 206 | tc->container = s; | ||
| 207 | tc->index = i; | ||
| 208 | bh[i] = qemu_bh_new(a10_pit_timer_cb, tc); | ||
| 209 | - s->timer[i] = ptimer_init(bh[i], PTIMER_POLICY_DEFAULT); | ||
| 210 | + s->timer[i] = ptimer_init_with_bh(bh[i], PTIMER_POLICY_DEFAULT); | ||
| 211 | } | ||
| 212 | } | ||
| 213 | |||
| 214 | diff --git a/hw/timer/altera_timer.c b/hw/timer/altera_timer.c | ||
| 215 | index XXXXXXX..XXXXXXX 100644 | ||
| 216 | --- a/hw/timer/altera_timer.c | ||
| 217 | +++ b/hw/timer/altera_timer.c | ||
| 218 | @@ -XXX,XX +XXX,XX @@ static void altera_timer_realize(DeviceState *dev, Error **errp) | ||
| 219 | } | ||
| 220 | |||
| 221 | t->bh = qemu_bh_new(timer_hit, t); | ||
| 222 | - t->ptimer = ptimer_init(t->bh, PTIMER_POLICY_DEFAULT); | ||
| 223 | + t->ptimer = ptimer_init_with_bh(t->bh, PTIMER_POLICY_DEFAULT); | ||
| 224 | ptimer_set_freq(t->ptimer, t->freq_hz); | ||
| 225 | |||
| 226 | memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, | ||
| 227 | diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c | ||
| 228 | index XXXXXXX..XXXXXXX 100644 | ||
| 229 | --- a/hw/timer/arm_mptimer.c | ||
| 230 | +++ b/hw/timer/arm_mptimer.c | ||
| 231 | @@ -XXX,XX +XXX,XX @@ static void arm_mptimer_reset(DeviceState *dev) | ||
| 232 | } | ||
| 233 | } | ||
| 234 | |||
| 235 | -static void arm_mptimer_init(Object *obj) | ||
| 236 | +static void arm_mptimer_init_with_bh(Object *obj) | ||
| 237 | { | ||
| 238 | ARMMPTimerState *s = ARM_MPTIMER(obj); | ||
| 239 | |||
| 240 | @@ -XXX,XX +XXX,XX @@ static void arm_mptimer_realize(DeviceState *dev, Error **errp) | ||
| 241 | for (i = 0; i < s->num_cpu; i++) { | ||
| 242 | TimerBlock *tb = &s->timerblock[i]; | ||
| 243 | QEMUBH *bh = qemu_bh_new(timerblock_tick, tb); | ||
| 244 | - tb->timer = ptimer_init(bh, PTIMER_POLICY); | ||
| 245 | + tb->timer = ptimer_init_with_bh(bh, PTIMER_POLICY); | ||
| 246 | sysbus_init_irq(sbd, &tb->irq); | ||
| 247 | memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, | ||
| 248 | "arm_mptimer_timerblock", 0x20); | ||
| 249 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo arm_mptimer_info = { | ||
| 250 | .name = TYPE_ARM_MPTIMER, | ||
| 251 | .parent = TYPE_SYS_BUS_DEVICE, | ||
| 252 | .instance_size = sizeof(ARMMPTimerState), | ||
| 253 | - .instance_init = arm_mptimer_init, | ||
| 254 | + .instance_init = arm_mptimer_init_with_bh, | ||
| 255 | .class_init = arm_mptimer_class_init, | ||
| 256 | }; | ||
| 257 | |||
| 258 | diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c | ||
| 259 | index XXXXXXX..XXXXXXX 100644 | ||
| 260 | --- a/hw/timer/arm_timer.c | ||
| 261 | +++ b/hw/timer/arm_timer.c | ||
| 262 | @@ -XXX,XX +XXX,XX @@ static arm_timer_state *arm_timer_init(uint32_t freq) | ||
| 263 | s->control = TIMER_CTRL_IE; | ||
| 264 | |||
| 265 | bh = qemu_bh_new(arm_timer_tick, s); | ||
| 266 | - s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
| 267 | + s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
| 268 | vmstate_register(NULL, -1, &vmstate_arm_timer, s); | ||
| 269 | return s; | ||
| 270 | } | ||
| 271 | diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c | ||
| 272 | index XXXXXXX..XXXXXXX 100644 | ||
| 273 | --- a/hw/timer/cmsdk-apb-dualtimer.c | ||
| 274 | +++ b/hw/timer/cmsdk-apb-dualtimer.c | ||
| 275 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp) | ||
| 276 | QEMUBH *bh = qemu_bh_new(cmsdk_dualtimermod_tick, m); | ||
| 277 | |||
| 278 | m->parent = s; | ||
| 279 | - m->timer = ptimer_init(bh, | ||
| 280 | + m->timer = ptimer_init_with_bh(bh, | ||
| 281 | PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | | ||
| 282 | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | | ||
| 283 | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | | ||
| 284 | diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c | ||
| 285 | index XXXXXXX..XXXXXXX 100644 | ||
| 286 | --- a/hw/timer/cmsdk-apb-timer.c | ||
| 287 | +++ b/hw/timer/cmsdk-apb-timer.c | ||
| 288 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) | ||
| 289 | } | ||
| 290 | |||
| 291 | bh = qemu_bh_new(cmsdk_apb_timer_tick, s); | ||
| 292 | - s->timer = ptimer_init(bh, | ||
| 293 | + s->timer = ptimer_init_with_bh(bh, | ||
| 294 | PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | | ||
| 295 | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | | ||
| 296 | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | | ||
| 297 | diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c | ||
| 298 | index XXXXXXX..XXXXXXX 100644 | ||
| 299 | --- a/hw/timer/digic-timer.c | ||
| 300 | +++ b/hw/timer/digic-timer.c | ||
| 301 | @@ -XXX,XX +XXX,XX @@ static void digic_timer_init(Object *obj) | ||
| 302 | { | ||
| 303 | DigicTimerState *s = DIGIC_TIMER(obj); | ||
| 304 | |||
| 305 | - s->ptimer = ptimer_init(NULL, PTIMER_POLICY_DEFAULT); | ||
| 306 | + s->ptimer = ptimer_init_with_bh(NULL, PTIMER_POLICY_DEFAULT); | ||
| 307 | |||
| 308 | /* | ||
| 309 | * FIXME: there is no documentation on Digic timer | ||
| 310 | diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c | ||
| 311 | index XXXXXXX..XXXXXXX 100644 | ||
| 312 | --- a/hw/timer/etraxfs_timer.c | ||
| 313 | +++ b/hw/timer/etraxfs_timer.c | ||
| 314 | @@ -XXX,XX +XXX,XX @@ static void etraxfs_timer_realize(DeviceState *dev, Error **errp) | ||
| 315 | t->bh_t0 = qemu_bh_new(timer0_hit, t); | ||
| 316 | t->bh_t1 = qemu_bh_new(timer1_hit, t); | ||
| 317 | t->bh_wd = qemu_bh_new(watchdog_hit, t); | ||
| 318 | - t->ptimer_t0 = ptimer_init(t->bh_t0, PTIMER_POLICY_DEFAULT); | ||
| 319 | - t->ptimer_t1 = ptimer_init(t->bh_t1, PTIMER_POLICY_DEFAULT); | ||
| 320 | - t->ptimer_wd = ptimer_init(t->bh_wd, PTIMER_POLICY_DEFAULT); | ||
| 321 | + t->ptimer_t0 = ptimer_init_with_bh(t->bh_t0, PTIMER_POLICY_DEFAULT); | ||
| 322 | + t->ptimer_t1 = ptimer_init_with_bh(t->bh_t1, PTIMER_POLICY_DEFAULT); | ||
| 323 | + t->ptimer_wd = ptimer_init_with_bh(t->bh_wd, PTIMER_POLICY_DEFAULT); | ||
| 324 | |||
| 325 | sysbus_init_irq(sbd, &t->irq); | ||
| 326 | sysbus_init_irq(sbd, &t->nmi); | ||
| 327 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | ||
| 328 | index XXXXXXX..XXXXXXX 100644 | ||
| 329 | --- a/hw/timer/exynos4210_mct.c | ||
| 330 | +++ b/hw/timer/exynos4210_mct.c | ||
| 331 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_init(Object *obj) | ||
| 332 | |||
| 333 | /* Global timer */ | ||
| 334 | bh[0] = qemu_bh_new(exynos4210_gfrc_event, s); | ||
| 335 | - s->g_timer.ptimer_frc = ptimer_init(bh[0], PTIMER_POLICY_DEFAULT); | ||
| 336 | + s->g_timer.ptimer_frc = ptimer_init_with_bh(bh[0], PTIMER_POLICY_DEFAULT); | ||
| 337 | memset(&s->g_timer.reg, 0, sizeof(struct gregs)); | ||
| 338 | |||
| 339 | /* Local timers */ | ||
| 340 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_init(Object *obj) | ||
| 341 | bh[0] = qemu_bh_new(exynos4210_ltick_event, &s->l_timer[i]); | ||
| 342 | bh[1] = qemu_bh_new(exynos4210_lfrc_event, &s->l_timer[i]); | ||
| 343 | s->l_timer[i].tick_timer.ptimer_tick = | ||
| 344 | - ptimer_init(bh[0], PTIMER_POLICY_DEFAULT); | ||
| 345 | - s->l_timer[i].ptimer_frc = ptimer_init(bh[1], PTIMER_POLICY_DEFAULT); | ||
| 346 | + ptimer_init_with_bh(bh[0], PTIMER_POLICY_DEFAULT); | ||
| 347 | + s->l_timer[i].ptimer_frc = | ||
| 348 | + ptimer_init_with_bh(bh[1], PTIMER_POLICY_DEFAULT); | ||
| 349 | s->l_timer[i].id = i; | ||
| 350 | } | ||
| 351 | |||
| 352 | diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c | ||
| 353 | index XXXXXXX..XXXXXXX 100644 | ||
| 354 | --- a/hw/timer/exynos4210_pwm.c | ||
| 355 | +++ b/hw/timer/exynos4210_pwm.c | ||
| 356 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_init(Object *obj) | ||
| 357 | for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { | ||
| 358 | bh = qemu_bh_new(exynos4210_pwm_tick, &s->timer[i]); | ||
| 359 | sysbus_init_irq(dev, &s->timer[i].irq); | ||
| 360 | - s->timer[i].ptimer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
| 361 | + s->timer[i].ptimer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
| 362 | s->timer[i].id = i; | ||
| 363 | s->timer[i].parent = s; | ||
| 364 | } | ||
| 365 | diff --git a/hw/timer/exynos4210_rtc.c b/hw/timer/exynos4210_rtc.c | ||
| 366 | index XXXXXXX..XXXXXXX 100644 | ||
| 367 | --- a/hw/timer/exynos4210_rtc.c | ||
| 368 | +++ b/hw/timer/exynos4210_rtc.c | ||
| 369 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_init(Object *obj) | ||
| 370 | QEMUBH *bh; | ||
| 371 | |||
| 372 | bh = qemu_bh_new(exynos4210_rtc_tick, s); | ||
| 373 | - s->ptimer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
| 374 | + s->ptimer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
| 375 | ptimer_set_freq(s->ptimer, RTC_BASE_FREQ); | ||
| 376 | exynos4210_rtc_update_freq(s, 0); | ||
| 377 | |||
| 378 | bh = qemu_bh_new(exynos4210_rtc_1Hz_tick, s); | ||
| 379 | - s->ptimer_1Hz = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
| 380 | + s->ptimer_1Hz = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
| 381 | ptimer_set_freq(s->ptimer_1Hz, RTC_BASE_FREQ); | ||
| 382 | |||
| 383 | sysbus_init_irq(dev, &s->alm_irq); | ||
| 384 | diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c | ||
| 385 | index XXXXXXX..XXXXXXX 100644 | ||
| 386 | --- a/hw/timer/grlib_gptimer.c | ||
| 387 | +++ b/hw/timer/grlib_gptimer.c | ||
| 388 | @@ -XXX,XX +XXX,XX @@ static void grlib_gptimer_realize(DeviceState *dev, Error **errp) | ||
| 389 | |||
| 390 | timer->unit = unit; | ||
| 391 | timer->bh = qemu_bh_new(grlib_gptimer_hit, timer); | ||
| 392 | - timer->ptimer = ptimer_init(timer->bh, PTIMER_POLICY_DEFAULT); | ||
| 393 | + timer->ptimer = ptimer_init_with_bh(timer->bh, PTIMER_POLICY_DEFAULT); | ||
| 394 | timer->id = i; | ||
| 395 | |||
| 396 | /* One IRQ line for each timer */ | ||
| 397 | diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c | ||
| 398 | index XXXXXXX..XXXXXXX 100644 | ||
| 399 | --- a/hw/timer/imx_epit.c | ||
| 400 | +++ b/hw/timer/imx_epit.c | ||
| 401 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_realize(DeviceState *dev, Error **errp) | ||
| 402 | 0x00001000); | ||
| 403 | sysbus_init_mmio(sbd, &s->iomem); | ||
| 404 | |||
| 405 | - s->timer_reload = ptimer_init(NULL, PTIMER_POLICY_DEFAULT); | ||
| 406 | + s->timer_reload = ptimer_init_with_bh(NULL, PTIMER_POLICY_DEFAULT); | ||
| 407 | |||
| 408 | bh = qemu_bh_new(imx_epit_cmp, s); | ||
| 409 | - s->timer_cmp = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
| 410 | + s->timer_cmp = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
| 411 | } | ||
| 412 | |||
| 413 | static void imx_epit_class_init(ObjectClass *klass, void *data) | ||
| 414 | diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c | ||
| 415 | index XXXXXXX..XXXXXXX 100644 | ||
| 416 | --- a/hw/timer/imx_gpt.c | ||
| 417 | +++ b/hw/timer/imx_gpt.c | ||
| 418 | @@ -XXX,XX +XXX,XX @@ static void imx_gpt_realize(DeviceState *dev, Error **errp) | ||
| 419 | sysbus_init_mmio(sbd, &s->iomem); | ||
| 420 | |||
| 421 | bh = qemu_bh_new(imx_gpt_timeout, s); | ||
| 422 | - s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
| 423 | + s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
| 424 | } | ||
| 425 | |||
| 426 | static void imx_gpt_class_init(ObjectClass *klass, void *data) | ||
| 427 | diff --git a/hw/timer/lm32_timer.c b/hw/timer/lm32_timer.c | ||
| 428 | index XXXXXXX..XXXXXXX 100644 | ||
| 429 | --- a/hw/timer/lm32_timer.c | ||
| 430 | +++ b/hw/timer/lm32_timer.c | ||
| 431 | @@ -XXX,XX +XXX,XX @@ static void lm32_timer_realize(DeviceState *dev, Error **errp) | ||
| 432 | LM32TimerState *s = LM32_TIMER(dev); | ||
| 433 | |||
| 434 | s->bh = qemu_bh_new(timer_hit, s); | ||
| 435 | - s->ptimer = ptimer_init(s->bh, PTIMER_POLICY_DEFAULT); | ||
| 436 | + s->ptimer = ptimer_init_with_bh(s->bh, PTIMER_POLICY_DEFAULT); | ||
| 437 | |||
| 438 | ptimer_set_freq(s->ptimer, s->freq_hz); | ||
| 439 | } | ||
| 440 | diff --git a/hw/timer/milkymist-sysctl.c b/hw/timer/milkymist-sysctl.c | ||
| 441 | index XXXXXXX..XXXXXXX 100644 | ||
| 442 | --- a/hw/timer/milkymist-sysctl.c | ||
| 443 | +++ b/hw/timer/milkymist-sysctl.c | ||
| 444 | @@ -XXX,XX +XXX,XX @@ static void milkymist_sysctl_realize(DeviceState *dev, Error **errp) | ||
| 445 | |||
| 446 | s->bh0 = qemu_bh_new(timer0_hit, s); | ||
| 447 | s->bh1 = qemu_bh_new(timer1_hit, s); | ||
| 448 | - s->ptimer0 = ptimer_init(s->bh0, PTIMER_POLICY_DEFAULT); | ||
| 449 | - s->ptimer1 = ptimer_init(s->bh1, PTIMER_POLICY_DEFAULT); | ||
| 450 | + s->ptimer0 = ptimer_init_with_bh(s->bh0, PTIMER_POLICY_DEFAULT); | ||
| 451 | + s->ptimer1 = ptimer_init_with_bh(s->bh1, PTIMER_POLICY_DEFAULT); | ||
| 452 | |||
| 453 | ptimer_set_freq(s->ptimer0, s->freq_hz); | ||
| 454 | ptimer_set_freq(s->ptimer1, s->freq_hz); | ||
| 455 | diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c | ||
| 456 | index XXXXXXX..XXXXXXX 100644 | ||
| 457 | --- a/hw/timer/mss-timer.c | ||
| 458 | +++ b/hw/timer/mss-timer.c | ||
| 459 | @@ -XXX,XX +XXX,XX @@ static void mss_timer_init(Object *obj) | ||
| 460 | struct Msf2Timer *st = &t->timers[i]; | ||
| 461 | |||
| 462 | st->bh = qemu_bh_new(timer_hit, st); | ||
| 463 | - st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT); | ||
| 464 | + st->ptimer = ptimer_init_with_bh(st->bh, PTIMER_POLICY_DEFAULT); | ||
| 465 | ptimer_set_freq(st->ptimer, t->freq_hz); | ||
| 466 | sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq); | ||
| 467 | } | ||
| 468 | diff --git a/hw/timer/puv3_ost.c b/hw/timer/puv3_ost.c | ||
| 469 | index XXXXXXX..XXXXXXX 100644 | ||
| 470 | --- a/hw/timer/puv3_ost.c | ||
| 471 | +++ b/hw/timer/puv3_ost.c | ||
| 472 | @@ -XXX,XX +XXX,XX @@ static void puv3_ost_realize(DeviceState *dev, Error **errp) | ||
| 473 | sysbus_init_irq(sbd, &s->irq); | ||
| 474 | |||
| 475 | s->bh = qemu_bh_new(puv3_ost_tick, s); | ||
| 476 | - s->ptimer = ptimer_init(s->bh, PTIMER_POLICY_DEFAULT); | ||
| 477 | + s->ptimer = ptimer_init_with_bh(s->bh, PTIMER_POLICY_DEFAULT); | ||
| 478 | ptimer_set_freq(s->ptimer, 50 * 1000 * 1000); | ||
| 479 | |||
| 480 | memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost", | ||
| 481 | diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c | ||
| 482 | index XXXXXXX..XXXXXXX 100644 | ||
| 483 | --- a/hw/timer/sh_timer.c | ||
| 484 | +++ b/hw/timer/sh_timer.c | ||
| 485 | @@ -XXX,XX +XXX,XX @@ static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq) | ||
| 486 | s->irq = irq; | ||
| 487 | |||
| 488 | bh = qemu_bh_new(sh_timer_tick, s); | ||
| 489 | - s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
| 490 | + s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
| 491 | |||
| 492 | sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor); | ||
| 493 | sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt); | ||
| 494 | diff --git a/hw/timer/slavio_timer.c b/hw/timer/slavio_timer.c | ||
| 495 | index XXXXXXX..XXXXXXX 100644 | ||
| 496 | --- a/hw/timer/slavio_timer.c | ||
| 497 | +++ b/hw/timer/slavio_timer.c | ||
| 498 | @@ -XXX,XX +XXX,XX @@ static void slavio_timer_init(Object *obj) | ||
| 499 | tc->timer_index = i; | ||
| 500 | |||
| 501 | bh = qemu_bh_new(slavio_timer_irq, tc); | ||
| 502 | - s->cputimer[i].timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
| 503 | + s->cputimer[i].timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
| 504 | ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD); | ||
| 505 | |||
| 506 | size = i == 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE; | ||
| 507 | diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c | ||
| 508 | index XXXXXXX..XXXXXXX 100644 | ||
| 509 | --- a/hw/timer/xilinx_timer.c | ||
| 510 | +++ b/hw/timer/xilinx_timer.c | ||
| 511 | @@ -XXX,XX +XXX,XX @@ static void xilinx_timer_realize(DeviceState *dev, Error **errp) | ||
| 512 | xt->parent = t; | ||
| 513 | xt->nr = i; | ||
| 514 | xt->bh = qemu_bh_new(timer_hit, xt); | ||
| 515 | - xt->ptimer = ptimer_init(xt->bh, PTIMER_POLICY_DEFAULT); | ||
| 516 | + xt->ptimer = ptimer_init_with_bh(xt->bh, PTIMER_POLICY_DEFAULT); | ||
| 517 | ptimer_set_freq(xt->ptimer, t->freq_hz); | ||
| 518 | } | ||
| 519 | |||
| 520 | diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c | ||
| 521 | index XXXXXXX..XXXXXXX 100644 | ||
| 522 | --- a/hw/watchdog/cmsdk-apb-watchdog.c | ||
| 523 | +++ b/hw/watchdog/cmsdk-apb-watchdog.c | ||
| 524 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) | ||
| 525 | } | ||
| 526 | |||
| 527 | bh = qemu_bh_new(cmsdk_apb_watchdog_tick, s); | ||
| 528 | - s->timer = ptimer_init(bh, | ||
| 529 | + s->timer = ptimer_init_with_bh(bh, | ||
| 530 | PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | | ||
| 531 | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | | ||
| 532 | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | | ||
| 533 | diff --git a/tests/ptimer-test.c b/tests/ptimer-test.c | ||
| 534 | index XXXXXXX..XXXXXXX 100644 | ||
| 535 | --- a/tests/ptimer-test.c | ||
| 536 | +++ b/tests/ptimer-test.c | ||
| 537 | @@ -XXX,XX +XXX,XX @@ static void check_set_count(gconstpointer arg) | ||
| 538 | { | ||
| 539 | const uint8_t *policy = arg; | ||
| 540 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 541 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
| 542 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 543 | |||
| 544 | triggered = false; | ||
| 545 | |||
| 546 | @@ -XXX,XX +XXX,XX @@ static void check_set_limit(gconstpointer arg) | ||
| 547 | { | ||
| 548 | const uint8_t *policy = arg; | ||
| 549 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 550 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
| 551 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 552 | |||
| 553 | triggered = false; | ||
| 554 | |||
| 555 | @@ -XXX,XX +XXX,XX @@ static void check_oneshot(gconstpointer arg) | ||
| 556 | { | ||
| 557 | const uint8_t *policy = arg; | ||
| 558 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 559 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
| 560 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 561 | bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | ||
| 562 | |||
| 563 | triggered = false; | ||
| 564 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
| 565 | { | ||
| 566 | const uint8_t *policy = arg; | ||
| 567 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 568 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
| 569 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 570 | bool wrap_policy = (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); | ||
| 571 | bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); | ||
| 572 | bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD); | ||
| 573 | @@ -XXX,XX +XXX,XX @@ static void check_on_the_fly_mode_change(gconstpointer arg) | ||
| 574 | { | ||
| 575 | const uint8_t *policy = arg; | ||
| 576 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 577 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
| 578 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 579 | bool wrap_policy = (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); | ||
| 580 | bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | ||
| 581 | |||
| 582 | @@ -XXX,XX +XXX,XX @@ static void check_on_the_fly_period_change(gconstpointer arg) | ||
| 583 | { | ||
| 584 | const uint8_t *policy = arg; | ||
| 585 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 586 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
| 587 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 588 | bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | ||
| 589 | |||
| 590 | triggered = false; | ||
| 591 | @@ -XXX,XX +XXX,XX @@ static void check_on_the_fly_freq_change(gconstpointer arg) | ||
| 592 | { | ||
| 593 | const uint8_t *policy = arg; | ||
| 594 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 595 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
| 596 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 597 | bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | ||
| 598 | |||
| 599 | triggered = false; | ||
| 600 | @@ -XXX,XX +XXX,XX @@ static void check_run_with_period_0(gconstpointer arg) | ||
| 601 | { | ||
| 602 | const uint8_t *policy = arg; | ||
| 603 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 604 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
| 605 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 606 | |||
| 607 | triggered = false; | ||
| 608 | |||
| 609 | @@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg) | ||
| 610 | { | ||
| 611 | const uint8_t *policy = arg; | ||
| 612 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 613 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
| 614 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 615 | bool wrap_policy = (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); | ||
| 616 | bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); | ||
| 617 | bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD); | ||
| 618 | @@ -XXX,XX +XXX,XX @@ static void check_periodic_with_load_0(gconstpointer arg) | ||
| 619 | { | ||
| 620 | const uint8_t *policy = arg; | ||
| 621 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 622 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
| 623 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 624 | bool continuous_trigger = (*policy & PTIMER_POLICY_CONTINUOUS_TRIGGER); | ||
| 625 | bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); | ||
| 626 | bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT); | ||
| 627 | @@ -XXX,XX +XXX,XX @@ static void check_oneshot_with_load_0(gconstpointer arg) | ||
| 628 | { | ||
| 629 | const uint8_t *policy = arg; | ||
| 630 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 631 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
| 632 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 633 | bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); | ||
| 634 | bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT); | ||
| 635 | |||
| 636 | -- | 23 | -- |
| 637 | 2.20.1 | 24 | 2.34.1 |
| 638 | |||
| 639 | diff view generated by jsdifflib |
| 1 | Switch the allwinner-a10-pit code away from bottom-half based ptimers to | 1 | Set the default NaN pattern explicitly for hexagon. |
|---|---|---|---|
| 2 | the new transaction-based ptimer API. This just requires adding | 2 | Remove the ifdef from parts64_default_nan(); the only |
| 3 | begin/commit calls around the various places that modify the ptimer | 3 | remaining unconverted targets all use the default case. |
| 4 | state, and using the new ptimer_init() function to create the timer. | ||
| 5 | 4 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Message-id: 20191008171740.9679-7-peter.maydell@linaro.org | 7 | Message-id: 20241202131347.498124-52-peter.maydell@linaro.org |
| 9 | --- | 8 | --- |
| 10 | hw/timer/allwinner-a10-pit.c | 12 ++++++++---- | 9 | target/hexagon/cpu.c | 2 ++ |
| 11 | 1 file changed, 8 insertions(+), 4 deletions(-) | 10 | fpu/softfloat-specialize.c.inc | 5 ----- |
| 11 | 2 files changed, 2 insertions(+), 5 deletions(-) | ||
| 12 | 12 | ||
| 13 | diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c | 13 | diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c |
| 14 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/hw/timer/allwinner-a10-pit.c | 15 | --- a/target/hexagon/cpu.c |
| 16 | +++ b/hw/timer/allwinner-a10-pit.c | 16 | +++ b/target/hexagon/cpu.c |
| 17 | @@ -XXX,XX +XXX,XX @@ | 17 | @@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type) |
| 18 | #include "hw/timer/allwinner-a10-pit.h" | 18 | |
| 19 | #include "migration/vmstate.h" | 19 | set_default_nan_mode(1, &env->fp_status); |
| 20 | #include "qemu/log.h" | 20 | set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); |
| 21 | -#include "qemu/main-loop.h" | 21 | + /* Default NaN value: sign bit set, all frac bits set */ |
| 22 | #include "qemu/module.h" | 22 | + set_float_default_nan_pattern(0b11111111, &env->fp_status); |
| 23 | |||
| 24 | static void a10_pit_update_irq(AwA10PITState *s) | ||
| 25 | @@ -XXX,XX +XXX,XX @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) | ||
| 26 | return 0; | ||
| 27 | } | 23 | } |
| 28 | 24 | ||
| 29 | +/* Must be called inside a ptimer transaction block for s->timer[index] */ | 25 | static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) |
| 30 | static void a10_pit_set_freq(AwA10PITState *s, int index) | 26 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 31 | { | 27 | index XXXXXXX..XXXXXXX 100644 |
| 32 | uint32_t prescaler, source, source_freq; | 28 | --- a/fpu/softfloat-specialize.c.inc |
| 33 | @@ -XXX,XX +XXX,XX @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, | 29 | +++ b/fpu/softfloat-specialize.c.inc |
| 34 | switch (offset & 0x0f) { | 30 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) |
| 35 | case AW_A10_PIT_TIMER_CONTROL: | 31 | uint8_t dnan_pattern = status->default_nan_pattern; |
| 36 | s->control[index] = value; | 32 | |
| 37 | + ptimer_transaction_begin(s->timer[index]); | 33 | if (dnan_pattern == 0) { |
| 38 | a10_pit_set_freq(s, index); | 34 | -#if defined(TARGET_HEXAGON) |
| 39 | if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) { | 35 | - /* Sign bit set, all frac bits set. */ |
| 40 | ptimer_set_count(s->timer[index], s->interval[index]); | 36 | - dnan_pattern = 0b11111111; |
| 41 | @@ -XXX,XX +XXX,XX @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, | 37 | -#else |
| 42 | } else { | 38 | /* |
| 43 | ptimer_stop(s->timer[index]); | 39 | * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, |
| 44 | } | 40 | * S390, SH4, TriCore, and Xtensa. Our other supported targets |
| 45 | + ptimer_transaction_commit(s->timer[index]); | 41 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) |
| 46 | break; | 42 | /* sign bit clear, set frac msb */ |
| 47 | case AW_A10_PIT_TIMER_INTERVAL: | 43 | dnan_pattern = 0b01000000; |
| 48 | s->interval[index] = value; | 44 | } |
| 49 | + ptimer_transaction_begin(s->timer[index]); | 45 | -#endif |
| 50 | ptimer_set_limit(s->timer[index], s->interval[index], 1); | ||
| 51 | + ptimer_transaction_commit(s->timer[index]); | ||
| 52 | break; | ||
| 53 | case AW_A10_PIT_TIMER_COUNT: | ||
| 54 | s->count[index] = value; | ||
| 55 | @@ -XXX,XX +XXX,XX @@ static void a10_pit_reset(DeviceState *dev) | ||
| 56 | s->control[i] = AW_A10_PIT_DEFAULT_CLOCK; | ||
| 57 | s->interval[i] = 0; | ||
| 58 | s->count[i] = 0; | ||
| 59 | + ptimer_transaction_begin(s->timer[i]); | ||
| 60 | ptimer_stop(s->timer[i]); | ||
| 61 | a10_pit_set_freq(s, i); | ||
| 62 | + ptimer_transaction_commit(s->timer[i]); | ||
| 63 | } | 46 | } |
| 64 | s->watch_dog_mode = 0; | 47 | assert(dnan_pattern != 0); |
| 65 | s->watch_dog_control = 0; | ||
| 66 | @@ -XXX,XX +XXX,XX @@ static void a10_pit_init(Object *obj) | ||
| 67 | { | ||
| 68 | AwA10PITState *s = AW_A10_PIT(obj); | ||
| 69 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
| 70 | - QEMUBH * bh[AW_A10_PIT_TIMER_NR]; | ||
| 71 | uint8_t i; | ||
| 72 | |||
| 73 | for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { | ||
| 74 | @@ -XXX,XX +XXX,XX @@ static void a10_pit_init(Object *obj) | ||
| 75 | |||
| 76 | tc->container = s; | ||
| 77 | tc->index = i; | ||
| 78 | - bh[i] = qemu_bh_new(a10_pit_timer_cb, tc); | ||
| 79 | - s->timer[i] = ptimer_init_with_bh(bh[i], PTIMER_POLICY_DEFAULT); | ||
| 80 | + s->timer[i] = ptimer_init(a10_pit_timer_cb, tc, PTIMER_POLICY_DEFAULT); | ||
| 81 | } | ||
| 82 | } | ||
| 83 | 48 | ||
| 84 | -- | 49 | -- |
| 85 | 2.20.1 | 50 | 2.34.1 |
| 86 | |||
| 87 | diff view generated by jsdifflib |
| 1 | The set_swi_errno() function is called to capture the errno | 1 | Set the default NaN pattern explicitly for riscv. |
|---|---|---|---|
| 2 | from a host system call, so that we can return -1 from the | ||
| 3 | semihosting function and later allow the guest to get a more | ||
| 4 | specific error code with the SYS_ERRNO function. It comes in | ||
| 5 | two versions, one for user-only and one for softmmu. We forgot | ||
| 6 | to capture the errno in the softmmu version; fix the error. | ||
| 7 | |||
| 8 | (Semihosting calls directed to gdb are unaffected because | ||
| 9 | they go through a different code path that captures the | ||
| 10 | error return from the gdbstub call in arm_semi_cb() or | ||
| 11 | arm_semi_flen_cb().) | ||
| 12 | 2 | ||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 14 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 15 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 16 | Message-id: 20190916141544.17540-2-peter.maydell@linaro.org | 5 | Message-id: 20241202131347.498124-53-peter.maydell@linaro.org |
| 17 | --- | 6 | --- |
| 18 | target/arm/arm-semi.c | 9 +++++---- | 7 | target/riscv/cpu.c | 2 ++ |
| 19 | 1 file changed, 5 insertions(+), 4 deletions(-) | 8 | 1 file changed, 2 insertions(+) |
| 20 | 9 | ||
| 21 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 10 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c |
| 22 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
| 23 | --- a/target/arm/arm-semi.c | 12 | --- a/target/riscv/cpu.c |
| 24 | +++ b/target/arm/arm-semi.c | 13 | +++ b/target/riscv/cpu.c |
| 25 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t set_swi_errno(TaskState *ts, uint32_t code) | 14 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) |
| 26 | return code; | 15 | cs->exception_index = RISCV_EXCP_NONE; |
| 27 | } | 16 | env->load_res = -1; |
| 28 | #else | 17 | set_default_nan_mode(1, &env->fp_status); |
| 29 | +static target_ulong syscall_err; | 18 | + /* Default NaN value: sign bit clear, frac msb set */ |
| 30 | + | 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); |
| 31 | static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code) | 20 | env->vill = true; |
| 32 | { | 21 | |
| 33 | + if (code == (uint32_t)-1) { | 22 | #ifndef CONFIG_USER_ONLY |
| 34 | + syscall_err = errno; | ||
| 35 | + } | ||
| 36 | return code; | ||
| 37 | } | ||
| 38 | |||
| 39 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code) | ||
| 40 | |||
| 41 | static target_ulong arm_semi_syscall_len; | ||
| 42 | |||
| 43 | -#if !defined(CONFIG_USER_ONLY) | ||
| 44 | -static target_ulong syscall_err; | ||
| 45 | -#endif | ||
| 46 | - | ||
| 47 | static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) | ||
| 48 | { | ||
| 49 | ARMCPU *cpu = ARM_CPU(cs); | ||
| 50 | -- | 23 | -- |
| 51 | 2.20.1 | 24 | 2.34.1 |
| 52 | |||
| 53 | diff view generated by jsdifflib |
| 1 | Convert the ptimer test cases to the transaction-based ptimer API, | 1 | Set the default NaN pattern explicitly for tricore. |
|---|---|---|---|
| 2 | by changing to ptimer_init(), dropping the now-unused QEMUBH | ||
| 3 | variables, and surrounding each set of changes to the ptimer | ||
| 4 | state in ptimer_transaction_begin/commit calls. | ||
| 5 | 2 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Message-id: 20191008171740.9679-4-peter.maydell@linaro.org | 5 | Message-id: 20241202131347.498124-54-peter.maydell@linaro.org |
| 9 | --- | 6 | --- |
| 10 | tests/ptimer-test.c | 106 +++++++++++++++++++++++++++++++++++--------- | 7 | target/tricore/helper.c | 2 ++ |
| 11 | 1 file changed, 84 insertions(+), 22 deletions(-) | 8 | 1 file changed, 2 insertions(+) |
| 12 | 9 | ||
| 13 | diff --git a/tests/ptimer-test.c b/tests/ptimer-test.c | 10 | diff --git a/target/tricore/helper.c b/target/tricore/helper.c |
| 14 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/tests/ptimer-test.c | 12 | --- a/target/tricore/helper.c |
| 16 | +++ b/tests/ptimer-test.c | 13 | +++ b/target/tricore/helper.c |
| 17 | @@ -XXX,XX +XXX,XX @@ static void qemu_clock_step(uint64_t ns) | 14 | @@ -XXX,XX +XXX,XX @@ void fpu_set_state(CPUTriCoreState *env) |
| 18 | static void check_set_count(gconstpointer arg) | 15 | set_flush_to_zero(1, &env->fp_status); |
| 19 | { | 16 | set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); |
| 20 | const uint8_t *policy = arg; | 17 | set_default_nan_mode(1, &env->fp_status); |
| 21 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | 18 | + /* Default NaN pattern: sign bit clear, frac msb set */ |
| 22 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); |
| 23 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
| 24 | |||
| 25 | triggered = false; | ||
| 26 | |||
| 27 | + ptimer_transaction_begin(ptimer); | ||
| 28 | ptimer_set_count(ptimer, 1000); | ||
| 29 | + ptimer_transaction_commit(ptimer); | ||
| 30 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 1000); | ||
| 31 | g_assert_false(triggered); | ||
| 32 | ptimer_free(ptimer); | ||
| 33 | @@ -XXX,XX +XXX,XX @@ static void check_set_count(gconstpointer arg) | ||
| 34 | static void check_set_limit(gconstpointer arg) | ||
| 35 | { | ||
| 36 | const uint8_t *policy = arg; | ||
| 37 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 38 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 39 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
| 40 | |||
| 41 | triggered = false; | ||
| 42 | |||
| 43 | + ptimer_transaction_begin(ptimer); | ||
| 44 | ptimer_set_limit(ptimer, 1000, 0); | ||
| 45 | + ptimer_transaction_commit(ptimer); | ||
| 46 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0); | ||
| 47 | g_assert_cmpuint(ptimer_get_limit(ptimer), ==, 1000); | ||
| 48 | g_assert_false(triggered); | ||
| 49 | |||
| 50 | + ptimer_transaction_begin(ptimer); | ||
| 51 | ptimer_set_limit(ptimer, 2000, 1); | ||
| 52 | + ptimer_transaction_commit(ptimer); | ||
| 53 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 2000); | ||
| 54 | g_assert_cmpuint(ptimer_get_limit(ptimer), ==, 2000); | ||
| 55 | g_assert_false(triggered); | ||
| 56 | @@ -XXX,XX +XXX,XX @@ static void check_set_limit(gconstpointer arg) | ||
| 57 | static void check_oneshot(gconstpointer arg) | ||
| 58 | { | ||
| 59 | const uint8_t *policy = arg; | ||
| 60 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 61 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 62 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
| 63 | bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | ||
| 64 | |||
| 65 | triggered = false; | ||
| 66 | |||
| 67 | + ptimer_transaction_begin(ptimer); | ||
| 68 | ptimer_set_period(ptimer, 2000000); | ||
| 69 | ptimer_set_count(ptimer, 10); | ||
| 70 | ptimer_run(ptimer, 1); | ||
| 71 | + ptimer_transaction_commit(ptimer); | ||
| 72 | |||
| 73 | qemu_clock_step(2000000 * 2 + 1); | ||
| 74 | |||
| 75 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 8 : 7); | ||
| 76 | g_assert_false(triggered); | ||
| 77 | |||
| 78 | + ptimer_transaction_begin(ptimer); | ||
| 79 | ptimer_stop(ptimer); | ||
| 80 | + ptimer_transaction_commit(ptimer); | ||
| 81 | |||
| 82 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 8 : 7); | ||
| 83 | g_assert_false(triggered); | ||
| 84 | @@ -XXX,XX +XXX,XX @@ static void check_oneshot(gconstpointer arg) | ||
| 85 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 8 : 7); | ||
| 86 | g_assert_false(triggered); | ||
| 87 | |||
| 88 | + ptimer_transaction_begin(ptimer); | ||
| 89 | ptimer_run(ptimer, 1); | ||
| 90 | + ptimer_transaction_commit(ptimer); | ||
| 91 | |||
| 92 | qemu_clock_step(2000000 * 7 + 1); | ||
| 93 | |||
| 94 | @@ -XXX,XX +XXX,XX @@ static void check_oneshot(gconstpointer arg) | ||
| 95 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0); | ||
| 96 | g_assert_false(triggered); | ||
| 97 | |||
| 98 | + ptimer_transaction_begin(ptimer); | ||
| 99 | ptimer_set_count(ptimer, 10); | ||
| 100 | + ptimer_transaction_commit(ptimer); | ||
| 101 | |||
| 102 | qemu_clock_step(20000000 + 1); | ||
| 103 | |||
| 104 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 10); | ||
| 105 | g_assert_false(triggered); | ||
| 106 | |||
| 107 | + ptimer_transaction_begin(ptimer); | ||
| 108 | ptimer_set_limit(ptimer, 9, 1); | ||
| 109 | + ptimer_transaction_commit(ptimer); | ||
| 110 | |||
| 111 | qemu_clock_step(20000000 + 1); | ||
| 112 | |||
| 113 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 9); | ||
| 114 | g_assert_false(triggered); | ||
| 115 | |||
| 116 | + ptimer_transaction_begin(ptimer); | ||
| 117 | ptimer_run(ptimer, 1); | ||
| 118 | + ptimer_transaction_commit(ptimer); | ||
| 119 | |||
| 120 | qemu_clock_step(2000000 + 1); | ||
| 121 | |||
| 122 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 8 : 7); | ||
| 123 | g_assert_false(triggered); | ||
| 124 | |||
| 125 | + ptimer_transaction_begin(ptimer); | ||
| 126 | ptimer_set_count(ptimer, 20); | ||
| 127 | + ptimer_transaction_commit(ptimer); | ||
| 128 | |||
| 129 | qemu_clock_step(2000000 * 19 + 1); | ||
| 130 | |||
| 131 | @@ -XXX,XX +XXX,XX @@ static void check_oneshot(gconstpointer arg) | ||
| 132 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0); | ||
| 133 | g_assert_true(triggered); | ||
| 134 | |||
| 135 | + ptimer_transaction_begin(ptimer); | ||
| 136 | ptimer_stop(ptimer); | ||
| 137 | + ptimer_transaction_commit(ptimer); | ||
| 138 | |||
| 139 | triggered = false; | ||
| 140 | |||
| 141 | @@ -XXX,XX +XXX,XX @@ static void check_oneshot(gconstpointer arg) | ||
| 142 | static void check_periodic(gconstpointer arg) | ||
| 143 | { | ||
| 144 | const uint8_t *policy = arg; | ||
| 145 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 146 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 147 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
| 148 | bool wrap_policy = (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); | ||
| 149 | bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); | ||
| 150 | bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD); | ||
| 151 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
| 152 | |||
| 153 | triggered = false; | ||
| 154 | |||
| 155 | + ptimer_transaction_begin(ptimer); | ||
| 156 | ptimer_set_period(ptimer, 2000000); | ||
| 157 | ptimer_set_limit(ptimer, 10, 1); | ||
| 158 | ptimer_run(ptimer, 0); | ||
| 159 | + ptimer_transaction_commit(ptimer); | ||
| 160 | |||
| 161 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 10); | ||
| 162 | g_assert_false(triggered); | ||
| 163 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
| 164 | (no_round_down ? 9 : 8) + (wrap_policy ? 1 : 0)); | ||
| 165 | g_assert_false(triggered); | ||
| 166 | |||
| 167 | + ptimer_transaction_begin(ptimer); | ||
| 168 | ptimer_set_count(ptimer, 20); | ||
| 169 | + ptimer_transaction_commit(ptimer); | ||
| 170 | |||
| 171 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 20); | ||
| 172 | g_assert_false(triggered); | ||
| 173 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
| 174 | |||
| 175 | triggered = false; | ||
| 176 | |||
| 177 | + ptimer_transaction_begin(ptimer); | ||
| 178 | ptimer_set_count(ptimer, 3); | ||
| 179 | + ptimer_transaction_commit(ptimer); | ||
| 180 | |||
| 181 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 3); | ||
| 182 | g_assert_false(triggered); | ||
| 183 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
| 184 | (no_round_down ? 9 : 8) + (wrap_policy ? 1 : 0)); | ||
| 185 | g_assert_true(triggered); | ||
| 186 | |||
| 187 | + ptimer_transaction_begin(ptimer); | ||
| 188 | ptimer_stop(ptimer); | ||
| 189 | + ptimer_transaction_commit(ptimer); | ||
| 190 | triggered = false; | ||
| 191 | |||
| 192 | qemu_clock_step(2000000); | ||
| 193 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
| 194 | (no_round_down ? 9 : 8) + (wrap_policy ? 1 : 0)); | ||
| 195 | g_assert_false(triggered); | ||
| 196 | |||
| 197 | + ptimer_transaction_begin(ptimer); | ||
| 198 | ptimer_set_count(ptimer, 3); | ||
| 199 | ptimer_run(ptimer, 0); | ||
| 200 | + ptimer_transaction_commit(ptimer); | ||
| 201 | |||
| 202 | qemu_clock_step(2000000 * 3 + 1); | ||
| 203 | |||
| 204 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
| 205 | (no_round_down ? 9 : 8) + (wrap_policy ? 1 : 0)); | ||
| 206 | g_assert_false(triggered); | ||
| 207 | |||
| 208 | + ptimer_transaction_begin(ptimer); | ||
| 209 | ptimer_set_count(ptimer, 0); | ||
| 210 | + ptimer_transaction_commit(ptimer); | ||
| 211 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, | ||
| 212 | no_immediate_reload ? 0 : 10); | ||
| 213 | |||
| 214 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
| 215 | (no_round_down ? 8 : 7) + (wrap_policy ? 1 : 0)); | ||
| 216 | g_assert_true(triggered); | ||
| 217 | |||
| 218 | + ptimer_transaction_begin(ptimer); | ||
| 219 | ptimer_stop(ptimer); | ||
| 220 | + ptimer_transaction_commit(ptimer); | ||
| 221 | |||
| 222 | triggered = false; | ||
| 223 | |||
| 224 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
| 225 | (no_round_down ? 8 : 7) + (wrap_policy ? 1 : 0)); | ||
| 226 | g_assert_false(triggered); | ||
| 227 | |||
| 228 | + ptimer_transaction_begin(ptimer); | ||
| 229 | ptimer_run(ptimer, 0); | ||
| 230 | + ptimer_transaction_commit(ptimer); | ||
| 231 | + | ||
| 232 | + ptimer_transaction_begin(ptimer); | ||
| 233 | ptimer_set_period(ptimer, 0); | ||
| 234 | + ptimer_transaction_commit(ptimer); | ||
| 235 | |||
| 236 | qemu_clock_step(2000000 + 1); | ||
| 237 | |||
| 238 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
| 239 | static void check_on_the_fly_mode_change(gconstpointer arg) | ||
| 240 | { | ||
| 241 | const uint8_t *policy = arg; | ||
| 242 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 243 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 244 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
| 245 | bool wrap_policy = (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); | ||
| 246 | bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | ||
| 247 | |||
| 248 | triggered = false; | ||
| 249 | |||
| 250 | + ptimer_transaction_begin(ptimer); | ||
| 251 | ptimer_set_period(ptimer, 2000000); | ||
| 252 | ptimer_set_limit(ptimer, 10, 1); | ||
| 253 | ptimer_run(ptimer, 1); | ||
| 254 | + ptimer_transaction_commit(ptimer); | ||
| 255 | |||
| 256 | qemu_clock_step(2000000 * 9 + 1); | ||
| 257 | |||
| 258 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 1 : 0); | ||
| 259 | g_assert_false(triggered); | ||
| 260 | |||
| 261 | + ptimer_transaction_begin(ptimer); | ||
| 262 | ptimer_run(ptimer, 0); | ||
| 263 | + ptimer_transaction_commit(ptimer); | ||
| 264 | |||
| 265 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 1 : 0); | ||
| 266 | g_assert_false(triggered); | ||
| 267 | @@ -XXX,XX +XXX,XX @@ static void check_on_the_fly_mode_change(gconstpointer arg) | ||
| 268 | |||
| 269 | qemu_clock_step(2000000 * 9); | ||
| 270 | |||
| 271 | + ptimer_transaction_begin(ptimer); | ||
| 272 | ptimer_run(ptimer, 1); | ||
| 273 | + ptimer_transaction_commit(ptimer); | ||
| 274 | |||
| 275 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, | ||
| 276 | (no_round_down ? 1 : 0) + (wrap_policy ? 1 : 0)); | ||
| 277 | @@ -XXX,XX +XXX,XX @@ static void check_on_the_fly_mode_change(gconstpointer arg) | ||
| 278 | static void check_on_the_fly_period_change(gconstpointer arg) | ||
| 279 | { | ||
| 280 | const uint8_t *policy = arg; | ||
| 281 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 282 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 283 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
| 284 | bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | ||
| 285 | |||
| 286 | triggered = false; | ||
| 287 | |||
| 288 | + ptimer_transaction_begin(ptimer); | ||
| 289 | ptimer_set_period(ptimer, 2000000); | ||
| 290 | ptimer_set_limit(ptimer, 8, 1); | ||
| 291 | ptimer_run(ptimer, 1); | ||
| 292 | + ptimer_transaction_commit(ptimer); | ||
| 293 | |||
| 294 | qemu_clock_step(2000000 * 4 + 1); | ||
| 295 | |||
| 296 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 4 : 3); | ||
| 297 | g_assert_false(triggered); | ||
| 298 | |||
| 299 | + ptimer_transaction_begin(ptimer); | ||
| 300 | ptimer_set_period(ptimer, 4000000); | ||
| 301 | + ptimer_transaction_commit(ptimer); | ||
| 302 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 4 : 3); | ||
| 303 | |||
| 304 | qemu_clock_step(4000000 * 2 + 1); | ||
| 305 | @@ -XXX,XX +XXX,XX @@ static void check_on_the_fly_period_change(gconstpointer arg) | ||
| 306 | static void check_on_the_fly_freq_change(gconstpointer arg) | ||
| 307 | { | ||
| 308 | const uint8_t *policy = arg; | ||
| 309 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 310 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 311 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
| 312 | bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | ||
| 313 | |||
| 314 | triggered = false; | ||
| 315 | |||
| 316 | + ptimer_transaction_begin(ptimer); | ||
| 317 | ptimer_set_freq(ptimer, 500); | ||
| 318 | ptimer_set_limit(ptimer, 8, 1); | ||
| 319 | ptimer_run(ptimer, 1); | ||
| 320 | + ptimer_transaction_commit(ptimer); | ||
| 321 | |||
| 322 | qemu_clock_step(2000000 * 4 + 1); | ||
| 323 | |||
| 324 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 4 : 3); | ||
| 325 | g_assert_false(triggered); | ||
| 326 | |||
| 327 | + ptimer_transaction_begin(ptimer); | ||
| 328 | ptimer_set_freq(ptimer, 250); | ||
| 329 | + ptimer_transaction_commit(ptimer); | ||
| 330 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 4 : 3); | ||
| 331 | |||
| 332 | qemu_clock_step(2000000 * 4 + 1); | ||
| 333 | @@ -XXX,XX +XXX,XX @@ static void check_on_the_fly_freq_change(gconstpointer arg) | ||
| 334 | static void check_run_with_period_0(gconstpointer arg) | ||
| 335 | { | ||
| 336 | const uint8_t *policy = arg; | ||
| 337 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 338 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 339 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
| 340 | |||
| 341 | triggered = false; | ||
| 342 | |||
| 343 | + ptimer_transaction_begin(ptimer); | ||
| 344 | ptimer_set_count(ptimer, 99); | ||
| 345 | ptimer_run(ptimer, 1); | ||
| 346 | + ptimer_transaction_commit(ptimer); | ||
| 347 | |||
| 348 | qemu_clock_step(10 * NANOSECONDS_PER_SECOND); | ||
| 349 | |||
| 350 | @@ -XXX,XX +XXX,XX @@ static void check_run_with_period_0(gconstpointer arg) | ||
| 351 | static void check_run_with_delta_0(gconstpointer arg) | ||
| 352 | { | ||
| 353 | const uint8_t *policy = arg; | ||
| 354 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 355 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 356 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
| 357 | bool wrap_policy = (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); | ||
| 358 | bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); | ||
| 359 | bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD); | ||
| 360 | @@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg) | ||
| 361 | |||
| 362 | triggered = false; | ||
| 363 | |||
| 364 | + ptimer_transaction_begin(ptimer); | ||
| 365 | ptimer_set_period(ptimer, 2000000); | ||
| 366 | ptimer_set_limit(ptimer, 99, 0); | ||
| 367 | ptimer_run(ptimer, 1); | ||
| 368 | + ptimer_transaction_commit(ptimer); | ||
| 369 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, | ||
| 370 | no_immediate_reload ? 0 : 99); | ||
| 371 | |||
| 372 | @@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg) | ||
| 373 | g_assert_false(triggered); | ||
| 374 | } | ||
| 375 | |||
| 376 | + ptimer_transaction_begin(ptimer); | ||
| 377 | ptimer_set_count(ptimer, 99); | ||
| 378 | ptimer_run(ptimer, 1); | ||
| 379 | + ptimer_transaction_commit(ptimer); | ||
| 380 | } | ||
| 381 | |||
| 382 | qemu_clock_step(2000000 + 1); | ||
| 383 | @@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg) | ||
| 384 | |||
| 385 | triggered = false; | ||
| 386 | |||
| 387 | + ptimer_transaction_begin(ptimer); | ||
| 388 | ptimer_set_count(ptimer, 0); | ||
| 389 | ptimer_run(ptimer, 0); | ||
| 390 | + ptimer_transaction_commit(ptimer); | ||
| 391 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, | ||
| 392 | no_immediate_reload ? 0 : 99); | ||
| 393 | |||
| 394 | @@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg) | ||
| 395 | wrap_policy ? 0 : (no_round_down ? 99 : 98)); | ||
| 396 | g_assert_true(triggered); | ||
| 397 | |||
| 398 | + ptimer_transaction_begin(ptimer); | ||
| 399 | ptimer_stop(ptimer); | ||
| 400 | + ptimer_transaction_commit(ptimer); | ||
| 401 | ptimer_free(ptimer); | ||
| 402 | } | 20 | } |
| 403 | 21 | ||
| 404 | static void check_periodic_with_load_0(gconstpointer arg) | 22 | uint32_t psw_read(CPUTriCoreState *env) |
| 405 | { | ||
| 406 | const uint8_t *policy = arg; | ||
| 407 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 408 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 409 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
| 410 | bool continuous_trigger = (*policy & PTIMER_POLICY_CONTINUOUS_TRIGGER); | ||
| 411 | bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); | ||
| 412 | bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT); | ||
| 413 | |||
| 414 | triggered = false; | ||
| 415 | |||
| 416 | + ptimer_transaction_begin(ptimer); | ||
| 417 | ptimer_set_period(ptimer, 2000000); | ||
| 418 | ptimer_run(ptimer, 0); | ||
| 419 | + ptimer_transaction_commit(ptimer); | ||
| 420 | |||
| 421 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0); | ||
| 422 | |||
| 423 | @@ -XXX,XX +XXX,XX @@ static void check_periodic_with_load_0(gconstpointer arg) | ||
| 424 | |||
| 425 | triggered = false; | ||
| 426 | |||
| 427 | + ptimer_transaction_begin(ptimer); | ||
| 428 | ptimer_set_count(ptimer, 10); | ||
| 429 | ptimer_run(ptimer, 0); | ||
| 430 | + ptimer_transaction_commit(ptimer); | ||
| 431 | |||
| 432 | qemu_clock_step(2000000 * 10 + 1); | ||
| 433 | |||
| 434 | @@ -XXX,XX +XXX,XX @@ static void check_periodic_with_load_0(gconstpointer arg) | ||
| 435 | g_assert_false(triggered); | ||
| 436 | } | ||
| 437 | |||
| 438 | + ptimer_transaction_begin(ptimer); | ||
| 439 | ptimer_stop(ptimer); | ||
| 440 | + ptimer_transaction_commit(ptimer); | ||
| 441 | ptimer_free(ptimer); | ||
| 442 | } | ||
| 443 | |||
| 444 | static void check_oneshot_with_load_0(gconstpointer arg) | ||
| 445 | { | ||
| 446 | const uint8_t *policy = arg; | ||
| 447 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
| 448 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
| 449 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
| 450 | bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); | ||
| 451 | bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT); | ||
| 452 | |||
| 453 | triggered = false; | ||
| 454 | |||
| 455 | + ptimer_transaction_begin(ptimer); | ||
| 456 | ptimer_set_period(ptimer, 2000000); | ||
| 457 | ptimer_run(ptimer, 1); | ||
| 458 | + ptimer_transaction_commit(ptimer); | ||
| 459 | |||
| 460 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0); | ||
| 461 | |||
| 462 | -- | 23 | -- |
| 463 | 2.20.1 | 24 | 2.34.1 |
| 464 | |||
| 465 | diff view generated by jsdifflib |
| 1 | Switch the digic-timer.c code away from bottom-half based ptimers to | 1 | Now that all our targets have bene converted to explicitly specify |
|---|---|---|---|
| 2 | the new transaction-based ptimer API. This just requires adding | 2 | their pattern for the default NaN value we can remove the remaining |
| 3 | begin/commit calls around the various places that modify the ptimer | 3 | fallback code in parts64_default_nan(). |
| 4 | state, and using the new ptimer_init() function to create the timer. | ||
| 5 | 4 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Message-id: 20191008171740.9679-11-peter.maydell@linaro.org | 7 | Message-id: 20241202131347.498124-55-peter.maydell@linaro.org |
| 9 | --- | 8 | --- |
| 10 | hw/timer/digic-timer.c | 16 ++++++++++++++-- | 9 | fpu/softfloat-specialize.c.inc | 14 -------------- |
| 11 | 1 file changed, 14 insertions(+), 2 deletions(-) | 10 | 1 file changed, 14 deletions(-) |
| 12 | 11 | ||
| 13 | diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c | 12 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 14 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/hw/timer/digic-timer.c | 14 | --- a/fpu/softfloat-specialize.c.inc |
| 16 | +++ b/hw/timer/digic-timer.c | 15 | +++ b/fpu/softfloat-specialize.c.inc |
| 17 | @@ -XXX,XX +XXX,XX @@ | 16 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) |
| 18 | #include "qemu/osdep.h" | 17 | uint64_t frac; |
| 19 | #include "hw/sysbus.h" | 18 | uint8_t dnan_pattern = status->default_nan_pattern; |
| 20 | #include "hw/ptimer.h" | 19 | |
| 21 | -#include "qemu/main-loop.h" | 20 | - if (dnan_pattern == 0) { |
| 22 | #include "qemu/module.h" | 21 | - /* |
| 23 | #include "qemu/log.h" | 22 | - * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, |
| 24 | 23 | - * S390, SH4, TriCore, and Xtensa. Our other supported targets | |
| 25 | @@ -XXX,XX +XXX,XX @@ static void digic_timer_reset(DeviceState *dev) | 24 | - * do not have floating-point. |
| 26 | { | 25 | - */ |
| 27 | DigicTimerState *s = DIGIC_TIMER(dev); | 26 | - if (snan_bit_is_one(status)) { |
| 28 | 27 | - /* sign bit clear, set all frac bits other than msb */ | |
| 29 | + ptimer_transaction_begin(s->ptimer); | 28 | - dnan_pattern = 0b00111111; |
| 30 | ptimer_stop(s->ptimer); | 29 | - } else { |
| 31 | + ptimer_transaction_commit(s->ptimer); | 30 | - /* sign bit clear, set frac msb */ |
| 32 | s->control = 0; | 31 | - dnan_pattern = 0b01000000; |
| 33 | s->relvalue = 0; | 32 | - } |
| 34 | } | 33 | - } |
| 35 | @@ -XXX,XX +XXX,XX @@ static void digic_timer_write(void *opaque, hwaddr offset, | 34 | assert(dnan_pattern != 0); |
| 36 | break; | 35 | |
| 37 | } | 36 | sign = dnan_pattern >> 7; |
| 38 | |||
| 39 | + ptimer_transaction_begin(s->ptimer); | ||
| 40 | if (value & DIGIC_TIMER_CONTROL_EN) { | ||
| 41 | ptimer_run(s->ptimer, 0); | ||
| 42 | } | ||
| 43 | |||
| 44 | s->control = (uint32_t)value; | ||
| 45 | + ptimer_transaction_commit(s->ptimer); | ||
| 46 | break; | ||
| 47 | |||
| 48 | case DIGIC_TIMER_RELVALUE: | ||
| 49 | s->relvalue = extract32(value, 0, 16); | ||
| 50 | + ptimer_transaction_begin(s->ptimer); | ||
| 51 | ptimer_set_limit(s->ptimer, s->relvalue, 1); | ||
| 52 | + ptimer_transaction_commit(s->ptimer); | ||
| 53 | break; | ||
| 54 | |||
| 55 | case DIGIC_TIMER_VALUE: | ||
| 56 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps digic_timer_ops = { | ||
| 57 | .endianness = DEVICE_NATIVE_ENDIAN, | ||
| 58 | }; | ||
| 59 | |||
| 60 | +static void digic_timer_tick(void *opaque) | ||
| 61 | +{ | ||
| 62 | + /* Nothing to do on timer rollover */ | ||
| 63 | +} | ||
| 64 | + | ||
| 65 | static void digic_timer_init(Object *obj) | ||
| 66 | { | ||
| 67 | DigicTimerState *s = DIGIC_TIMER(obj); | ||
| 68 | |||
| 69 | - s->ptimer = ptimer_init_with_bh(NULL, PTIMER_POLICY_DEFAULT); | ||
| 70 | + s->ptimer = ptimer_init(digic_timer_tick, NULL, PTIMER_POLICY_DEFAULT); | ||
| 71 | |||
| 72 | /* | ||
| 73 | * FIXME: there is no documentation on Digic timer | ||
| 74 | * frequency setup so let it always run at 1 MHz | ||
| 75 | */ | ||
| 76 | + ptimer_transaction_begin(s->ptimer); | ||
| 77 | ptimer_set_freq(s->ptimer, 1 * 1000 * 1000); | ||
| 78 | + ptimer_transaction_commit(s->ptimer); | ||
| 79 | |||
| 80 | memory_region_init_io(&s->iomem, OBJECT(s), &digic_timer_ops, s, | ||
| 81 | TYPE_DIGIC_TIMER, 0x100); | ||
| 82 | -- | 37 | -- |
| 83 | 2.20.1 | 38 | 2.34.1 |
| 84 | |||
| 85 | diff view generated by jsdifflib |
| 1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The I2C controller of the AST2400 and AST2500 SoCs have one IRQ shared | 3 | Inline pickNaNMulAdd into its only caller. This makes |
| 4 | by all I2C busses. The AST2600 SoC I2C controller has one IRQ per bus | 4 | one assert redundant with the immediately preceding IF. |
| 5 | and 16 busses. | ||
| 6 | 5 | ||
| 7 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Reviewed-by: Joel Stanley <joel@jms.id.au> | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 9 | Message-id: 20190925143248.10000-17-clg@kaod.org | 8 | Message-id: 20241203203949.483774-3-richard.henderson@linaro.org |
| 9 | [PMM: keep comment from old code in new location] | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | --- | 11 | --- |
| 12 | include/hw/i2c/aspeed_i2c.h | 5 +++- | 12 | fpu/softfloat-parts.c.inc | 41 +++++++++++++++++++++++++- |
| 13 | hw/i2c/aspeed_i2c.c | 46 +++++++++++++++++++++++++++++++++++-- | 13 | fpu/softfloat-specialize.c.inc | 54 ---------------------------------- |
| 14 | 2 files changed, 48 insertions(+), 3 deletions(-) | 14 | 2 files changed, 40 insertions(+), 55 deletions(-) |
| 15 | 15 | ||
| 16 | diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h | 16 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
| 17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/include/hw/i2c/aspeed_i2c.h | 18 | --- a/fpu/softfloat-parts.c.inc |
| 19 | +++ b/include/hw/i2c/aspeed_i2c.h | 19 | +++ b/fpu/softfloat-parts.c.inc |
| 20 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
| 21 | #define TYPE_ASPEED_I2C "aspeed.i2c" | 21 | } |
| 22 | #define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400" | 22 | |
| 23 | #define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500" | 23 | if (s->default_nan_mode) { |
| 24 | +#define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600" | 24 | + /* |
| 25 | #define ASPEED_I2C(obj) \ | 25 | + * We guarantee not to require the target to tell us how to |
| 26 | OBJECT_CHECK(AspeedI2CState, (obj), TYPE_ASPEED_I2C) | 26 | + * pick a NaN if we're always returning the default NaN. |
| 27 | 27 | + * But if we're not in default-NaN mode then the target must | |
| 28 | -#define ASPEED_I2C_NR_BUSSES 14 | 28 | + * specify. |
| 29 | +#define ASPEED_I2C_NR_BUSSES 16 | 29 | + */ |
| 30 | 30 | which = 3; | |
| 31 | struct AspeedI2CState; | 31 | + } else if (infzero) { |
| 32 | 32 | + /* | |
| 33 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedI2CBus { | 33 | + * Inf * 0 + NaN -- some implementations return the |
| 34 | 34 | + * default NaN here, and some return the input NaN. | |
| 35 | I2CBus *bus; | 35 | + */ |
| 36 | uint8_t id; | 36 | + switch (s->float_infzeronan_rule) { |
| 37 | + qemu_irq irq; | 37 | + case float_infzeronan_dnan_never: |
| 38 | 38 | + which = 2; | |
| 39 | uint32_t ctrl; | 39 | + break; |
| 40 | uint32_t timing[2]; | 40 | + case float_infzeronan_dnan_always: |
| 41 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedI2CClass { | 41 | + which = 3; |
| 42 | uint8_t num_busses; | 42 | + break; |
| 43 | uint8_t reg_size; | 43 | + case float_infzeronan_dnan_if_qnan: |
| 44 | uint8_t gap; | 44 | + which = is_qnan(c->cls) ? 3 : 2; |
| 45 | + qemu_irq (*bus_get_irq)(AspeedI2CBus *); | 45 | + break; |
| 46 | } AspeedI2CClass; | 46 | + default: |
| 47 | 47 | + g_assert_not_reached(); | |
| 48 | I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr); | 48 | + } |
| 49 | diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c | 49 | } else { |
| 50 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s); | ||
| 51 | + FloatClass cls[3] = { a->cls, b->cls, c->cls }; | ||
| 52 | + Float3NaNPropRule rule = s->float_3nan_prop_rule; | ||
| 53 | + | ||
| 54 | + assert(rule != float_3nan_prop_none); | ||
| 55 | + if (have_snan && (rule & R_3NAN_SNAN_MASK)) { | ||
| 56 | + /* We have at least one SNaN input and should prefer it */ | ||
| 57 | + do { | ||
| 58 | + which = rule & R_3NAN_1ST_MASK; | ||
| 59 | + rule >>= R_3NAN_1ST_LENGTH; | ||
| 60 | + } while (!is_snan(cls[which])); | ||
| 61 | + } else { | ||
| 62 | + do { | ||
| 63 | + which = rule & R_3NAN_1ST_MASK; | ||
| 64 | + rule >>= R_3NAN_1ST_LENGTH; | ||
| 65 | + } while (!is_nan(cls[which])); | ||
| 66 | + } | ||
| 67 | } | ||
| 68 | |||
| 69 | if (which == 3) { | ||
| 70 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 50 | index XXXXXXX..XXXXXXX 100644 | 71 | index XXXXXXX..XXXXXXX 100644 |
| 51 | --- a/hw/i2c/aspeed_i2c.c | 72 | --- a/fpu/softfloat-specialize.c.inc |
| 52 | +++ b/hw/i2c/aspeed_i2c.c | 73 | +++ b/fpu/softfloat-specialize.c.inc |
| 53 | @@ -XXX,XX +XXX,XX @@ static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus) | 74 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, |
| 54 | |||
| 55 | static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus) | ||
| 56 | { | ||
| 57 | + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); | ||
| 58 | + | ||
| 59 | bus->intr_status &= bus->intr_ctrl; | ||
| 60 | if (bus->intr_status) { | ||
| 61 | bus->controller->intr_status |= 1 << bus->id; | ||
| 62 | - qemu_irq_raise(bus->controller->irq); | ||
| 63 | + qemu_irq_raise(aic->bus_get_irq(bus)); | ||
| 64 | } | 75 | } |
| 65 | } | 76 | } |
| 66 | 77 | ||
| 67 | @@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, | 78 | -/*---------------------------------------------------------------------------- |
| 68 | uint64_t value, unsigned size) | 79 | -| Select which NaN to propagate for a three-input operation. |
| 69 | { | 80 | -| For the moment we assume that no CPU needs the 'larger significand' |
| 70 | AspeedI2CBus *bus = opaque; | 81 | -| information. |
| 71 | + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); | 82 | -| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN |
| 72 | bool handle_rx; | 83 | -*----------------------------------------------------------------------------*/ |
| 73 | 84 | -static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | |
| 74 | switch (offset) { | 85 | - bool infzero, bool have_snan, float_status *status) |
| 75 | @@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, | 86 | -{ |
| 76 | bus->intr_status &= ~(value & 0x7FFF); | 87 | - FloatClass cls[3] = { a_cls, b_cls, c_cls }; |
| 77 | if (!bus->intr_status) { | 88 | - Float3NaNPropRule rule = status->float_3nan_prop_rule; |
| 78 | bus->controller->intr_status &= ~(1 << bus->id); | 89 | - int which; |
| 79 | - qemu_irq_lower(bus->controller->irq); | 90 | - |
| 80 | + qemu_irq_lower(aic->bus_get_irq(bus)); | 91 | - /* |
| 81 | } | 92 | - * We guarantee not to require the target to tell us how to |
| 82 | if (handle_rx && (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST))) { | 93 | - * pick a NaN if we're always returning the default NaN. |
| 83 | aspeed_i2c_handle_rx_cmd(bus); | 94 | - * But if we're not in default-NaN mode then the target must |
| 84 | @@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp) | 95 | - * specify. |
| 85 | for (i = 0; i < aic->num_busses; i++) { | 96 | - */ |
| 86 | char name[32]; | 97 | - assert(!status->default_nan_mode); |
| 87 | int offset = i < aic->gap ? 1 : 5; | 98 | - |
| 88 | + | 99 | - if (infzero) { |
| 89 | + sysbus_init_irq(sbd, &s->busses[i].irq); | 100 | - /* |
| 90 | snprintf(name, sizeof(name), "aspeed.i2c.%d", i); | 101 | - * Inf * 0 + NaN -- some implementations return the default NaN here, |
| 91 | s->busses[i].controller = s; | 102 | - * and some return the input NaN. |
| 92 | s->busses[i].id = i; | 103 | - */ |
| 93 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_i2c_info = { | 104 | - switch (status->float_infzeronan_rule) { |
| 94 | .abstract = true, | 105 | - case float_infzeronan_dnan_never: |
| 95 | }; | 106 | - return 2; |
| 96 | 107 | - case float_infzeronan_dnan_always: | |
| 97 | +static qemu_irq aspeed_2400_i2c_bus_get_irq(AspeedI2CBus *bus) | 108 | - return 3; |
| 98 | +{ | 109 | - case float_infzeronan_dnan_if_qnan: |
| 99 | + return bus->controller->irq; | 110 | - return is_qnan(c_cls) ? 3 : 2; |
| 100 | +} | 111 | - default: |
| 101 | + | 112 | - g_assert_not_reached(); |
| 102 | static void aspeed_2400_i2c_class_init(ObjectClass *klass, void *data) | 113 | - } |
| 103 | { | 114 | - } |
| 104 | DeviceClass *dc = DEVICE_CLASS(klass); | 115 | - |
| 105 | @@ -XXX,XX +XXX,XX @@ static void aspeed_2400_i2c_class_init(ObjectClass *klass, void *data) | 116 | - assert(rule != float_3nan_prop_none); |
| 106 | aic->num_busses = 14; | 117 | - if (have_snan && (rule & R_3NAN_SNAN_MASK)) { |
| 107 | aic->reg_size = 0x40; | 118 | - /* We have at least one SNaN input and should prefer it */ |
| 108 | aic->gap = 7; | 119 | - do { |
| 109 | + aic->bus_get_irq = aspeed_2400_i2c_bus_get_irq; | 120 | - which = rule & R_3NAN_1ST_MASK; |
| 110 | } | 121 | - rule >>= R_3NAN_1ST_LENGTH; |
| 111 | 122 | - } while (!is_snan(cls[which])); | |
| 112 | static const TypeInfo aspeed_2400_i2c_info = { | 123 | - } else { |
| 113 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_2400_i2c_info = { | 124 | - do { |
| 114 | .class_init = aspeed_2400_i2c_class_init, | 125 | - which = rule & R_3NAN_1ST_MASK; |
| 115 | }; | 126 | - rule >>= R_3NAN_1ST_LENGTH; |
| 116 | 127 | - } while (!is_nan(cls[which])); | |
| 117 | +static qemu_irq aspeed_2500_i2c_bus_get_irq(AspeedI2CBus *bus) | 128 | - } |
| 118 | +{ | 129 | - return which; |
| 119 | + return bus->controller->irq; | 130 | -} |
| 120 | +} | 131 | - |
| 121 | + | 132 | /*---------------------------------------------------------------------------- |
| 122 | static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data) | 133 | | Returns 1 if the double-precision floating-point value `a' is a quiet |
| 123 | { | 134 | | NaN; otherwise returns 0. |
| 124 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 125 | @@ -XXX,XX +XXX,XX @@ static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data) | ||
| 126 | aic->num_busses = 14; | ||
| 127 | aic->reg_size = 0x40; | ||
| 128 | aic->gap = 7; | ||
| 129 | + aic->bus_get_irq = aspeed_2500_i2c_bus_get_irq; | ||
| 130 | } | ||
| 131 | |||
| 132 | static const TypeInfo aspeed_2500_i2c_info = { | ||
| 133 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_2500_i2c_info = { | ||
| 134 | .class_init = aspeed_2500_i2c_class_init, | ||
| 135 | }; | ||
| 136 | |||
| 137 | +static qemu_irq aspeed_2600_i2c_bus_get_irq(AspeedI2CBus *bus) | ||
| 138 | +{ | ||
| 139 | + return bus->irq; | ||
| 140 | +} | ||
| 141 | + | ||
| 142 | +static void aspeed_2600_i2c_class_init(ObjectClass *klass, void *data) | ||
| 143 | +{ | ||
| 144 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 145 | + AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); | ||
| 146 | + | ||
| 147 | + dc->desc = "ASPEED 2600 I2C Controller"; | ||
| 148 | + | ||
| 149 | + aic->num_busses = 16; | ||
| 150 | + aic->reg_size = 0x80; | ||
| 151 | + aic->gap = -1; /* no gap */ | ||
| 152 | + aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; | ||
| 153 | +} | ||
| 154 | + | ||
| 155 | +static const TypeInfo aspeed_2600_i2c_info = { | ||
| 156 | + .name = TYPE_ASPEED_2600_I2C, | ||
| 157 | + .parent = TYPE_ASPEED_I2C, | ||
| 158 | + .class_init = aspeed_2600_i2c_class_init, | ||
| 159 | +}; | ||
| 160 | + | ||
| 161 | static void aspeed_i2c_register_types(void) | ||
| 162 | { | ||
| 163 | type_register_static(&aspeed_i2c_info); | ||
| 164 | type_register_static(&aspeed_2400_i2c_info); | ||
| 165 | type_register_static(&aspeed_2500_i2c_info); | ||
| 166 | + type_register_static(&aspeed_2600_i2c_info); | ||
| 167 | } | ||
| 168 | |||
| 169 | type_init(aspeed_i2c_register_types) | ||
| 170 | -- | 135 | -- |
| 171 | 2.20.1 | 136 | 2.34.1 |
| 172 | 137 | ||
| 173 | 138 | diff view generated by jsdifflib |
| 1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | It prepares ground for register differences between SoCs. | 3 | Remove "3" as a special case for which and simply |
| 4 | branch to return the desired value. | ||
| 4 | 5 | ||
| 5 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 6 | Reviewed-by: Joel Stanley <joel@jms.id.au> | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 7 | Message-id: 20190925143248.10000-16-clg@kaod.org | 8 | Message-id: 20241203203949.483774-4-richard.henderson@linaro.org |
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 9 | --- | 10 | --- |
| 10 | include/hw/i2c/aspeed_i2c.h | 15 ++++++++++ | 11 | fpu/softfloat-parts.c.inc | 20 ++++++++++---------- |
| 11 | hw/arm/aspeed_soc.c | 3 +- | 12 | 1 file changed, 10 insertions(+), 10 deletions(-) |
| 12 | hw/i2c/aspeed_i2c.c | 60 ++++++++++++++++++++++++++++++++----- | ||
| 13 | 3 files changed, 69 insertions(+), 9 deletions(-) | ||
| 14 | 13 | ||
| 15 | diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h | 14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
| 16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/include/hw/i2c/aspeed_i2c.h | 16 | --- a/fpu/softfloat-parts.c.inc |
| 18 | +++ b/include/hw/i2c/aspeed_i2c.h | 17 | +++ b/fpu/softfloat-parts.c.inc |
| 19 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
| 20 | #include "hw/sysbus.h" | 19 | * But if we're not in default-NaN mode then the target must |
| 21 | 20 | * specify. | |
| 22 | #define TYPE_ASPEED_I2C "aspeed.i2c" | 21 | */ |
| 23 | +#define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400" | 22 | - which = 3; |
| 24 | +#define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500" | 23 | + goto default_nan; |
| 25 | #define ASPEED_I2C(obj) \ | 24 | } else if (infzero) { |
| 26 | OBJECT_CHECK(AspeedI2CState, (obj), TYPE_ASPEED_I2C) | 25 | /* |
| 27 | 26 | * Inf * 0 + NaN -- some implementations return the | |
| 28 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedI2CState { | 27 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
| 29 | AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES]; | 28 | */ |
| 30 | } AspeedI2CState; | 29 | switch (s->float_infzeronan_rule) { |
| 31 | 30 | case float_infzeronan_dnan_never: | |
| 32 | +#define ASPEED_I2C_CLASS(klass) \ | 31 | - which = 2; |
| 33 | + OBJECT_CLASS_CHECK(AspeedI2CClass, (klass), TYPE_ASPEED_I2C) | 32 | break; |
| 34 | +#define ASPEED_I2C_GET_CLASS(obj) \ | 33 | case float_infzeronan_dnan_always: |
| 35 | + OBJECT_GET_CLASS(AspeedI2CClass, (obj), TYPE_ASPEED_I2C) | 34 | - which = 3; |
| 35 | - break; | ||
| 36 | + goto default_nan; | ||
| 37 | case float_infzeronan_dnan_if_qnan: | ||
| 38 | - which = is_qnan(c->cls) ? 3 : 2; | ||
| 39 | + if (is_qnan(c->cls)) { | ||
| 40 | + goto default_nan; | ||
| 41 | + } | ||
| 42 | break; | ||
| 43 | default: | ||
| 44 | g_assert_not_reached(); | ||
| 45 | } | ||
| 46 | + which = 2; | ||
| 47 | } else { | ||
| 48 | FloatClass cls[3] = { a->cls, b->cls, c->cls }; | ||
| 49 | Float3NaNPropRule rule = s->float_3nan_prop_rule; | ||
| 50 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
| 51 | } | ||
| 52 | } | ||
| 53 | |||
| 54 | - if (which == 3) { | ||
| 55 | - parts_default_nan(a, s); | ||
| 56 | - return a; | ||
| 57 | - } | ||
| 58 | - | ||
| 59 | switch (which) { | ||
| 60 | case 0: | ||
| 61 | break; | ||
| 62 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
| 63 | parts_silence_nan(a, s); | ||
| 64 | } | ||
| 65 | return a; | ||
| 36 | + | 66 | + |
| 37 | +typedef struct AspeedI2CClass { | 67 | + default_nan: |
| 38 | + SysBusDeviceClass parent_class; | 68 | + parts_default_nan(a, s); |
| 39 | + | 69 | + return a; |
| 40 | + uint8_t num_busses; | ||
| 41 | + uint8_t reg_size; | ||
| 42 | + uint8_t gap; | ||
| 43 | +} AspeedI2CClass; | ||
| 44 | + | ||
| 45 | I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr); | ||
| 46 | |||
| 47 | #endif /* ASPEED_I2C_H */ | ||
| 48 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
| 49 | index XXXXXXX..XXXXXXX 100644 | ||
| 50 | --- a/hw/arm/aspeed_soc.c | ||
| 51 | +++ b/hw/arm/aspeed_soc.c | ||
| 52 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | ||
| 53 | object_property_add_const_link(OBJECT(&s->timerctrl), "scu", | ||
| 54 | OBJECT(&s->scu), &error_abort); | ||
| 55 | |||
| 56 | + snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); | ||
| 57 | sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c), | ||
| 58 | - TYPE_ASPEED_I2C); | ||
| 59 | + typename); | ||
| 60 | |||
| 61 | snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); | ||
| 62 | sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc), | ||
| 63 | diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c | ||
| 64 | index XXXXXXX..XXXXXXX 100644 | ||
| 65 | --- a/hw/i2c/aspeed_i2c.c | ||
| 66 | +++ b/hw/i2c/aspeed_i2c.c | ||
| 67 | @@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_reset(DeviceState *dev) | ||
| 68 | { | ||
| 69 | int i; | ||
| 70 | AspeedI2CState *s = ASPEED_I2C(dev); | ||
| 71 | + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); | ||
| 72 | |||
| 73 | s->intr_status = 0; | ||
| 74 | |||
| 75 | - for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) { | ||
| 76 | + for (i = 0; i < aic->num_busses; i++) { | ||
| 77 | s->busses[i].intr_ctrl = 0; | ||
| 78 | s->busses[i].intr_status = 0; | ||
| 79 | s->busses[i].cmd = 0; | ||
| 80 | @@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_reset(DeviceState *dev) | ||
| 81 | } | 70 | } |
| 82 | 71 | ||
| 83 | /* | 72 | /* |
| 84 | - * Address Definitions | ||
| 85 | + * Address Definitions (AST2400 and AST2500) | ||
| 86 | * | ||
| 87 | * 0x000 ... 0x03F: Global Register | ||
| 88 | * 0x040 ... 0x07F: Device 1 | ||
| 89 | @@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp) | ||
| 90 | int i; | ||
| 91 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
| 92 | AspeedI2CState *s = ASPEED_I2C(dev); | ||
| 93 | + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); | ||
| 94 | |||
| 95 | sysbus_init_irq(sbd, &s->irq); | ||
| 96 | memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s, | ||
| 97 | "aspeed.i2c", 0x1000); | ||
| 98 | sysbus_init_mmio(sbd, &s->iomem); | ||
| 99 | |||
| 100 | - for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) { | ||
| 101 | - char name[16]; | ||
| 102 | - int offset = i < 7 ? 1 : 5; | ||
| 103 | + for (i = 0; i < aic->num_busses; i++) { | ||
| 104 | + char name[32]; | ||
| 105 | + int offset = i < aic->gap ? 1 : 5; | ||
| 106 | snprintf(name, sizeof(name), "aspeed.i2c.%d", i); | ||
| 107 | s->busses[i].controller = s; | ||
| 108 | s->busses[i].id = i; | ||
| 109 | s->busses[i].bus = i2c_init_bus(dev, name); | ||
| 110 | memory_region_init_io(&s->busses[i].mr, OBJECT(dev), | ||
| 111 | - &aspeed_i2c_bus_ops, &s->busses[i], name, 0x40); | ||
| 112 | - memory_region_add_subregion(&s->iomem, 0x40 * (i + offset), | ||
| 113 | + &aspeed_i2c_bus_ops, &s->busses[i], name, | ||
| 114 | + aic->reg_size); | ||
| 115 | + memory_region_add_subregion(&s->iomem, aic->reg_size * (i + offset), | ||
| 116 | &s->busses[i].mr); | ||
| 117 | } | ||
| 118 | } | ||
| 119 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_i2c_info = { | ||
| 120 | .parent = TYPE_SYS_BUS_DEVICE, | ||
| 121 | .instance_size = sizeof(AspeedI2CState), | ||
| 122 | .class_init = aspeed_i2c_class_init, | ||
| 123 | + .class_size = sizeof(AspeedI2CClass), | ||
| 124 | + .abstract = true, | ||
| 125 | +}; | ||
| 126 | + | ||
| 127 | +static void aspeed_2400_i2c_class_init(ObjectClass *klass, void *data) | ||
| 128 | +{ | ||
| 129 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 130 | + AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); | ||
| 131 | + | ||
| 132 | + dc->desc = "ASPEED 2400 I2C Controller"; | ||
| 133 | + | ||
| 134 | + aic->num_busses = 14; | ||
| 135 | + aic->reg_size = 0x40; | ||
| 136 | + aic->gap = 7; | ||
| 137 | +} | ||
| 138 | + | ||
| 139 | +static const TypeInfo aspeed_2400_i2c_info = { | ||
| 140 | + .name = TYPE_ASPEED_2400_I2C, | ||
| 141 | + .parent = TYPE_ASPEED_I2C, | ||
| 142 | + .class_init = aspeed_2400_i2c_class_init, | ||
| 143 | +}; | ||
| 144 | + | ||
| 145 | +static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data) | ||
| 146 | +{ | ||
| 147 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 148 | + AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); | ||
| 149 | + | ||
| 150 | + dc->desc = "ASPEED 2500 I2C Controller"; | ||
| 151 | + | ||
| 152 | + aic->num_busses = 14; | ||
| 153 | + aic->reg_size = 0x40; | ||
| 154 | + aic->gap = 7; | ||
| 155 | +} | ||
| 156 | + | ||
| 157 | +static const TypeInfo aspeed_2500_i2c_info = { | ||
| 158 | + .name = TYPE_ASPEED_2500_I2C, | ||
| 159 | + .parent = TYPE_ASPEED_I2C, | ||
| 160 | + .class_init = aspeed_2500_i2c_class_init, | ||
| 161 | }; | ||
| 162 | |||
| 163 | static void aspeed_i2c_register_types(void) | ||
| 164 | { | ||
| 165 | type_register_static(&aspeed_i2c_info); | ||
| 166 | + type_register_static(&aspeed_2400_i2c_info); | ||
| 167 | + type_register_static(&aspeed_2500_i2c_info); | ||
| 168 | } | ||
| 169 | |||
| 170 | type_init(aspeed_i2c_register_types) | ||
| 171 | @@ -XXX,XX +XXX,XX @@ type_init(aspeed_i2c_register_types) | ||
| 172 | I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr) | ||
| 173 | { | ||
| 174 | AspeedI2CState *s = ASPEED_I2C(dev); | ||
| 175 | + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); | ||
| 176 | I2CBus *bus = NULL; | ||
| 177 | |||
| 178 | - if (busnr >= 0 && busnr < ASPEED_I2C_NR_BUSSES) { | ||
| 179 | + if (busnr >= 0 && busnr < aic->num_busses) { | ||
| 180 | bus = s->busses[busnr].bus; | ||
| 181 | } | ||
| 182 | |||
| 183 | -- | 73 | -- |
| 184 | 2.20.1 | 74 | 2.34.1 |
| 185 | 75 | ||
| 186 | 76 | diff view generated by jsdifflib |
| 1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Use class handlers and class constants to differentiate the | 3 | Assign the pointer return value to 'a' directly, |
| 4 | characteristics of the memory controller and remove the 'silicon_rev' | 4 | rather than going through an intermediary index. |
| 5 | property. | ||
| 6 | 5 | ||
| 7 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Reviewed-by: Joel Stanley <joel@jms.id.au> | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 9 | Message-id: 20190925143248.10000-9-clg@kaod.org | 8 | Message-id: 20241203203949.483774-5-richard.henderson@linaro.org |
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | --- | 10 | --- |
| 12 | include/hw/misc/aspeed_sdmc.h | 19 +++- | 11 | fpu/softfloat-parts.c.inc | 32 ++++++++++---------------------- |
| 13 | hw/arm/aspeed_soc.c | 5 +- | 12 | 1 file changed, 10 insertions(+), 22 deletions(-) |
| 14 | hw/misc/aspeed_sdmc.c | 168 +++++++++++++++++++++------------- | ||
| 15 | 3 files changed, 122 insertions(+), 70 deletions(-) | ||
| 16 | 13 | ||
| 17 | diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h | 14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
| 18 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 19 | --- a/include/hw/misc/aspeed_sdmc.h | 16 | --- a/fpu/softfloat-parts.c.inc |
| 20 | +++ b/include/hw/misc/aspeed_sdmc.h | 17 | +++ b/fpu/softfloat-parts.c.inc |
| 21 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
| 22 | 19 | FloatPartsN *c, float_status *s, | |
| 23 | #define TYPE_ASPEED_SDMC "aspeed.sdmc" | 20 | int ab_mask, int abc_mask) |
| 24 | #define ASPEED_SDMC(obj) OBJECT_CHECK(AspeedSDMCState, (obj), TYPE_ASPEED_SDMC) | 21 | { |
| 25 | +#define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400" | 22 | - int which; |
| 26 | +#define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500" | 23 | bool infzero = (ab_mask == float_cmask_infzero); |
| 27 | 24 | bool have_snan = (abc_mask & float_cmask_snan); | |
| 28 | #define ASPEED_SDMC_NR_REGS (0x174 >> 2) | 25 | + FloatPartsN *ret; |
| 29 | 26 | ||
| 30 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSDMCState { | 27 | if (unlikely(have_snan)) { |
| 31 | MemoryRegion iomem; | 28 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); |
| 32 | 29 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | |
| 33 | uint32_t regs[ASPEED_SDMC_NR_REGS]; | 30 | default: |
| 34 | - uint32_t silicon_rev; | 31 | g_assert_not_reached(); |
| 35 | - uint32_t ram_bits; | 32 | } |
| 36 | uint64_t ram_size; | 33 | - which = 2; |
| 37 | uint64_t max_ram_size; | 34 | + ret = c; |
| 38 | - uint32_t fixed_conf; | 35 | } else { |
| 39 | - | 36 | - FloatClass cls[3] = { a->cls, b->cls, c->cls }; |
| 40 | } AspeedSDMCState; | 37 | + FloatPartsN *val[3] = { a, b, c }; |
| 41 | 38 | Float3NaNPropRule rule = s->float_3nan_prop_rule; | |
| 42 | +#define ASPEED_SDMC_CLASS(klass) \ | 39 | |
| 43 | + OBJECT_CLASS_CHECK(AspeedSDMCClass, (klass), TYPE_ASPEED_SDMC) | 40 | assert(rule != float_3nan_prop_none); |
| 44 | +#define ASPEED_SDMC_GET_CLASS(obj) \ | 41 | if (have_snan && (rule & R_3NAN_SNAN_MASK)) { |
| 45 | + OBJECT_GET_CLASS(AspeedSDMCClass, (obj), TYPE_ASPEED_SDMC) | 42 | /* We have at least one SNaN input and should prefer it */ |
| 46 | + | 43 | do { |
| 47 | +typedef struct AspeedSDMCClass { | 44 | - which = rule & R_3NAN_1ST_MASK; |
| 48 | + SysBusDeviceClass parent_class; | 45 | + ret = val[rule & R_3NAN_1ST_MASK]; |
| 49 | + | 46 | rule >>= R_3NAN_1ST_LENGTH; |
| 50 | + uint64_t max_ram_size; | 47 | - } while (!is_snan(cls[which])); |
| 51 | + uint32_t (*compute_conf)(AspeedSDMCState *s, uint32_t data); | 48 | + } while (!is_snan(ret->cls)); |
| 52 | + void (*write)(AspeedSDMCState *s, uint32_t reg, uint32_t data); | 49 | } else { |
| 53 | +} AspeedSDMCClass; | 50 | do { |
| 54 | + | 51 | - which = rule & R_3NAN_1ST_MASK; |
| 55 | #endif /* ASPEED_SDMC_H */ | 52 | + ret = val[rule & R_3NAN_1ST_MASK]; |
| 56 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | 53 | rule >>= R_3NAN_1ST_LENGTH; |
| 57 | index XXXXXXX..XXXXXXX 100644 | 54 | - } while (!is_nan(cls[which])); |
| 58 | --- a/hw/arm/aspeed_soc.c | 55 | + } while (!is_nan(ret->cls)); |
| 59 | +++ b/hw/arm/aspeed_soc.c | 56 | } |
| 60 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | ||
| 61 | sizeof(s->spi[i]), typename); | ||
| 62 | } | 57 | } |
| 63 | 58 | ||
| 64 | + snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); | 59 | - switch (which) { |
| 65 | sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc), | 60 | - case 0: |
| 66 | - TYPE_ASPEED_SDMC); | ||
| 67 | - qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev", | ||
| 68 | - sc->info->silicon_rev); | ||
| 69 | + typename); | ||
| 70 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), | ||
| 71 | "ram-size", &error_abort); | ||
| 72 | object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), | ||
| 73 | diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c | ||
| 74 | index XXXXXXX..XXXXXXX 100644 | ||
| 75 | --- a/hw/misc/aspeed_sdmc.c | ||
| 76 | +++ b/hw/misc/aspeed_sdmc.c | ||
| 77 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data, | ||
| 78 | unsigned int size) | ||
| 79 | { | ||
| 80 | AspeedSDMCState *s = ASPEED_SDMC(opaque); | ||
| 81 | + AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); | ||
| 82 | |||
| 83 | addr >>= 2; | ||
| 84 | |||
| 85 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data, | ||
| 86 | return; | ||
| 87 | } | ||
| 88 | |||
| 89 | - if (addr == R_CONF) { | ||
| 90 | - /* Make sure readonly bits are kept */ | ||
| 91 | - switch (s->silicon_rev) { | ||
| 92 | - case AST2400_A0_SILICON_REV: | ||
| 93 | - case AST2400_A1_SILICON_REV: | ||
| 94 | - data &= ~ASPEED_SDMC_READONLY_MASK; | ||
| 95 | - data |= s->fixed_conf; | ||
| 96 | - break; | ||
| 97 | - case AST2500_A0_SILICON_REV: | ||
| 98 | - case AST2500_A1_SILICON_REV: | ||
| 99 | - data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; | ||
| 100 | - data |= s->fixed_conf; | ||
| 101 | - break; | ||
| 102 | - default: | ||
| 103 | - g_assert_not_reached(); | ||
| 104 | - } | ||
| 105 | - } | ||
| 106 | - if (s->silicon_rev == AST2500_A0_SILICON_REV || | ||
| 107 | - s->silicon_rev == AST2500_A1_SILICON_REV) { | ||
| 108 | - switch (addr) { | ||
| 109 | - case R_STATUS1: | ||
| 110 | - /* Will never return 'busy' */ | ||
| 111 | - data &= ~PHY_BUSY_STATE; | ||
| 112 | - break; | ||
| 113 | - case R_ECC_TEST_CTRL: | ||
| 114 | - /* Always done, always happy */ | ||
| 115 | - data |= ECC_TEST_FINISHED; | ||
| 116 | - data &= ~ECC_TEST_FAIL; | ||
| 117 | - break; | ||
| 118 | - default: | ||
| 119 | - break; | ||
| 120 | - } | ||
| 121 | - } | ||
| 122 | - | ||
| 123 | - s->regs[addr] = data; | ||
| 124 | + asc->write(s, addr, data); | ||
| 125 | } | ||
| 126 | |||
| 127 | static const MemoryRegionOps aspeed_sdmc_ops = { | ||
| 128 | @@ -XXX,XX +XXX,XX @@ static int ast2500_rambits(AspeedSDMCState *s) | ||
| 129 | static void aspeed_sdmc_reset(DeviceState *dev) | ||
| 130 | { | ||
| 131 | AspeedSDMCState *s = ASPEED_SDMC(dev); | ||
| 132 | + AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); | ||
| 133 | |||
| 134 | memset(s->regs, 0, sizeof(s->regs)); | ||
| 135 | |||
| 136 | /* Set ram size bit and defaults values */ | ||
| 137 | - s->regs[R_CONF] = s->fixed_conf; | ||
| 138 | + s->regs[R_CONF] = asc->compute_conf(s, 0); | ||
| 139 | } | ||
| 140 | |||
| 141 | static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) | ||
| 142 | { | ||
| 143 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
| 144 | AspeedSDMCState *s = ASPEED_SDMC(dev); | ||
| 145 | + AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); | ||
| 146 | |||
| 147 | - if (!is_supported_silicon_rev(s->silicon_rev)) { | ||
| 148 | - error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, | ||
| 149 | - s->silicon_rev); | ||
| 150 | - return; | ||
| 151 | - } | ||
| 152 | - | ||
| 153 | - switch (s->silicon_rev) { | ||
| 154 | - case AST2400_A0_SILICON_REV: | ||
| 155 | - case AST2400_A1_SILICON_REV: | ||
| 156 | - s->ram_bits = ast2400_rambits(s); | ||
| 157 | - s->max_ram_size = 512 << 20; | ||
| 158 | - s->fixed_conf = ASPEED_SDMC_VGA_COMPAT | | ||
| 159 | - ASPEED_SDMC_DRAM_SIZE(s->ram_bits); | ||
| 160 | - break; | 61 | - break; |
| 161 | - case AST2500_A0_SILICON_REV: | 62 | - case 1: |
| 162 | - case AST2500_A1_SILICON_REV: | 63 | - a = b; |
| 163 | - s->ram_bits = ast2500_rambits(s); | 64 | - break; |
| 164 | - s->max_ram_size = 1024 << 20; | 65 | - case 2: |
| 165 | - s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) | | 66 | - a = c; |
| 166 | - ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | | ||
| 167 | - ASPEED_SDMC_CACHE_INITIAL_DONE | | ||
| 168 | - ASPEED_SDMC_DRAM_SIZE(s->ram_bits); | ||
| 169 | - break; | 67 | - break; |
| 170 | - default: | 68 | - default: |
| 171 | - g_assert_not_reached(); | 69 | - g_assert_not_reached(); |
| 70 | + if (is_snan(ret->cls)) { | ||
| 71 | + parts_silence_nan(ret, s); | ||
| 72 | } | ||
| 73 | - if (is_snan(a->cls)) { | ||
| 74 | - parts_silence_nan(a, s); | ||
| 172 | - } | 75 | - } |
| 173 | + s->max_ram_size = asc->max_ram_size; | 76 | - return a; |
| 174 | 77 | + return ret; | |
| 175 | memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s, | 78 | |
| 176 | TYPE_ASPEED_SDMC, 0x1000); | 79 | default_nan: |
| 177 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_sdmc = { | 80 | parts_default_nan(a, s); |
| 178 | }; | ||
| 179 | |||
| 180 | static Property aspeed_sdmc_properties[] = { | ||
| 181 | - DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0), | ||
| 182 | DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0), | ||
| 183 | DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0), | ||
| 184 | DEFINE_PROP_END_OF_LIST(), | ||
| 185 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_sdmc_info = { | ||
| 186 | .parent = TYPE_SYS_BUS_DEVICE, | ||
| 187 | .instance_size = sizeof(AspeedSDMCState), | ||
| 188 | .class_init = aspeed_sdmc_class_init, | ||
| 189 | + .class_size = sizeof(AspeedSDMCClass), | ||
| 190 | + .abstract = true, | ||
| 191 | +}; | ||
| 192 | + | ||
| 193 | +static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) | ||
| 194 | +{ | ||
| 195 | + uint32_t fixed_conf = ASPEED_SDMC_VGA_COMPAT | | ||
| 196 | + ASPEED_SDMC_DRAM_SIZE(ast2400_rambits(s)); | ||
| 197 | + | ||
| 198 | + /* Make sure readonly bits are kept */ | ||
| 199 | + data &= ~ASPEED_SDMC_READONLY_MASK; | ||
| 200 | + | ||
| 201 | + return data | fixed_conf; | ||
| 202 | +} | ||
| 203 | + | ||
| 204 | +static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg, | ||
| 205 | + uint32_t data) | ||
| 206 | +{ | ||
| 207 | + switch (reg) { | ||
| 208 | + case R_CONF: | ||
| 209 | + data = aspeed_2400_sdmc_compute_conf(s, data); | ||
| 210 | + break; | ||
| 211 | + default: | ||
| 212 | + break; | ||
| 213 | + } | ||
| 214 | + | ||
| 215 | + s->regs[reg] = data; | ||
| 216 | +} | ||
| 217 | + | ||
| 218 | +static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data) | ||
| 219 | +{ | ||
| 220 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 221 | + AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); | ||
| 222 | + | ||
| 223 | + dc->desc = "ASPEED 2400 SDRAM Memory Controller"; | ||
| 224 | + asc->max_ram_size = 512 << 20; | ||
| 225 | + asc->compute_conf = aspeed_2400_sdmc_compute_conf; | ||
| 226 | + asc->write = aspeed_2400_sdmc_write; | ||
| 227 | +} | ||
| 228 | + | ||
| 229 | +static const TypeInfo aspeed_2400_sdmc_info = { | ||
| 230 | + .name = TYPE_ASPEED_2400_SDMC, | ||
| 231 | + .parent = TYPE_ASPEED_SDMC, | ||
| 232 | + .class_init = aspeed_2400_sdmc_class_init, | ||
| 233 | +}; | ||
| 234 | + | ||
| 235 | +static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) | ||
| 236 | +{ | ||
| 237 | + uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(1) | | ||
| 238 | + ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | | ||
| 239 | + ASPEED_SDMC_CACHE_INITIAL_DONE | | ||
| 240 | + ASPEED_SDMC_DRAM_SIZE(ast2500_rambits(s)); | ||
| 241 | + | ||
| 242 | + /* Make sure readonly bits are kept */ | ||
| 243 | + data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; | ||
| 244 | + | ||
| 245 | + return data | fixed_conf; | ||
| 246 | +} | ||
| 247 | + | ||
| 248 | +static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg, | ||
| 249 | + uint32_t data) | ||
| 250 | +{ | ||
| 251 | + switch (reg) { | ||
| 252 | + case R_CONF: | ||
| 253 | + data = aspeed_2500_sdmc_compute_conf(s, data); | ||
| 254 | + break; | ||
| 255 | + case R_STATUS1: | ||
| 256 | + /* Will never return 'busy' */ | ||
| 257 | + data &= ~PHY_BUSY_STATE; | ||
| 258 | + break; | ||
| 259 | + case R_ECC_TEST_CTRL: | ||
| 260 | + /* Always done, always happy */ | ||
| 261 | + data |= ECC_TEST_FINISHED; | ||
| 262 | + data &= ~ECC_TEST_FAIL; | ||
| 263 | + break; | ||
| 264 | + default: | ||
| 265 | + break; | ||
| 266 | + } | ||
| 267 | + | ||
| 268 | + s->regs[reg] = data; | ||
| 269 | +} | ||
| 270 | + | ||
| 271 | +static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data) | ||
| 272 | +{ | ||
| 273 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 274 | + AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); | ||
| 275 | + | ||
| 276 | + dc->desc = "ASPEED 2500 SDRAM Memory Controller"; | ||
| 277 | + asc->max_ram_size = 1024 << 20; | ||
| 278 | + asc->compute_conf = aspeed_2500_sdmc_compute_conf; | ||
| 279 | + asc->write = aspeed_2500_sdmc_write; | ||
| 280 | +} | ||
| 281 | + | ||
| 282 | +static const TypeInfo aspeed_2500_sdmc_info = { | ||
| 283 | + .name = TYPE_ASPEED_2500_SDMC, | ||
| 284 | + .parent = TYPE_ASPEED_SDMC, | ||
| 285 | + .class_init = aspeed_2500_sdmc_class_init, | ||
| 286 | }; | ||
| 287 | |||
| 288 | static void aspeed_sdmc_register_types(void) | ||
| 289 | { | ||
| 290 | type_register_static(&aspeed_sdmc_info); | ||
| 291 | + type_register_static(&aspeed_2400_sdmc_info); | ||
| 292 | + type_register_static(&aspeed_2500_sdmc_info); | ||
| 293 | } | ||
| 294 | |||
| 295 | type_init(aspeed_sdmc_register_types); | ||
| 296 | -- | 81 | -- |
| 297 | 2.20.1 | 82 | 2.34.1 |
| 298 | 83 | ||
| 299 | 84 | diff view generated by jsdifflib |
| 1 | From: Amithash Prasad <amithash@fb.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | When WDT_RESTART is written, the data is not the contents | 3 | While all indices into val[] should be in [0-2], the mask |
| 4 | of the WDT_CTRL register. Hence ensure we are looking at | 4 | applied is two bits. To help static analysis see there is |
| 5 | WDT_CTRL to check if bit WDT_CTRL_1MHZ_CLK is set or not. | 5 | no possibility of read beyond the end of the array, pad the |
| 6 | array to 4 entries, with the final being (implicitly) NULL. | ||
| 6 | 7 | ||
| 7 | Signed-off-by: Amithash Prasad <amithash@fb.com> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Reviewed-by: Joel Stanley <joel@jms.id.au> | 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 9 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 10 | Message-id: 20241203203949.483774-6-richard.henderson@linaro.org |
| 10 | Message-id: 20190925143248.10000-2-clg@kaod.org | ||
| 11 | [clg: improved Suject prefix ] | ||
| 12 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 13 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
| 14 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 16 | --- | 12 | --- |
| 17 | hw/watchdog/wdt_aspeed.c | 2 +- | 13 | fpu/softfloat-parts.c.inc | 2 +- |
| 18 | 1 file changed, 1 insertion(+), 1 deletion(-) | 14 | 1 file changed, 1 insertion(+), 1 deletion(-) |
| 19 | 15 | ||
| 20 | diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c | 16 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
| 21 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 22 | --- a/hw/watchdog/wdt_aspeed.c | 18 | --- a/fpu/softfloat-parts.c.inc |
| 23 | +++ b/hw/watchdog/wdt_aspeed.c | 19 | +++ b/fpu/softfloat-parts.c.inc |
| 24 | @@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, | 20 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
| 25 | case WDT_RESTART: | ||
| 26 | if ((data & 0xFFFF) == WDT_RESTART_MAGIC) { | ||
| 27 | s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE]; | ||
| 28 | - aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK)); | ||
| 29 | + aspeed_wdt_reload(s, !(s->regs[WDT_CTRL] & WDT_CTRL_1MHZ_CLK)); | ||
| 30 | } | 21 | } |
| 31 | break; | 22 | ret = c; |
| 32 | case WDT_CTRL: | 23 | } else { |
| 24 | - FloatPartsN *val[3] = { a, b, c }; | ||
| 25 | + FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c }; | ||
| 26 | Float3NaNPropRule rule = s->float_3nan_prop_rule; | ||
| 27 | |||
| 28 | assert(rule != float_3nan_prop_none); | ||
| 33 | -- | 29 | -- |
| 34 | 2.20.1 | 30 | 2.34.1 |
| 35 | 31 | ||
| 36 | 32 | diff view generated by jsdifflib |
| 1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Initial definitions for a simple machine using an AST2600 SoC (Cortex | 3 | This function is part of the public interface and |
| 4 | CPU). | 4 | is not "specialized" to any target in any way. |
| 5 | 5 | ||
| 6 | The Cortex CPU and its interrupt controller are too complex to handle | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 7 | in the common Aspeed SoC framework. We introduce a new Aspeed SoC | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 8 | class with instance_init and realize handlers to handle the differences | 8 | Message-id: 20241203203949.483774-7-richard.henderson@linaro.org |
| 9 | with the AST2400 and the AST2500 SoCs. This will add extra work to | ||
| 10 | keep in sync both models with future extensions but it makes the code | ||
| 11 | clearer. | ||
| 12 | |||
| 13 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 14 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
| 15 | Message-id: 20190925143248.10000-19-clg@kaod.org | ||
| 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 17 | --- | 10 | --- |
| 18 | hw/arm/Makefile.objs | 2 +- | 11 | fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++ |
| 19 | include/hw/arm/aspeed_soc.h | 4 + | 12 | fpu/softfloat-specialize.c.inc | 52 ---------------------------------- |
| 20 | hw/arm/aspeed_ast2600.c | 492 ++++++++++++++++++++++++++++++++++++ | 13 | 2 files changed, 52 insertions(+), 52 deletions(-) |
| 21 | 3 files changed, 497 insertions(+), 1 deletion(-) | ||
| 22 | create mode 100644 hw/arm/aspeed_ast2600.c | ||
| 23 | 14 | ||
| 24 | diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs | 15 | diff --git a/fpu/softfloat.c b/fpu/softfloat.c |
| 25 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 26 | --- a/hw/arm/Makefile.objs | 17 | --- a/fpu/softfloat.c |
| 27 | +++ b/hw/arm/Makefile.objs | 18 | +++ b/fpu/softfloat.c |
| 28 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o | 19 | @@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, |
| 29 | obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o | 20 | *zExpPtr = 1 - shiftCount; |
| 30 | obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o | 21 | } |
| 31 | obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o | 22 | |
| 32 | -obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o | 23 | +/*---------------------------------------------------------------------------- |
| 33 | +obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o aspeed_ast2600.o | 24 | +| Takes two extended double-precision floating-point values `a' and `b', one |
| 34 | obj-$(CONFIG_MPS2) += mps2.o | 25 | +| of which is a NaN, and returns the appropriate NaN result. If either `a' or |
| 35 | obj-$(CONFIG_MPS2) += mps2-tz.o | 26 | +| `b' is a signaling NaN, the invalid exception is raised. |
| 36 | obj-$(CONFIG_MSF2) += msf2-soc.o | 27 | +*----------------------------------------------------------------------------*/ |
| 37 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | ||
| 38 | index XXXXXXX..XXXXXXX 100644 | ||
| 39 | --- a/include/hw/arm/aspeed_soc.h | ||
| 40 | +++ b/include/hw/arm/aspeed_soc.h | ||
| 41 | @@ -XXX,XX +XXX,XX @@ | ||
| 42 | #ifndef ASPEED_SOC_H | ||
| 43 | #define ASPEED_SOC_H | ||
| 44 | |||
| 45 | +#include "hw/cpu/a15mpcore.h" | ||
| 46 | #include "hw/intc/aspeed_vic.h" | ||
| 47 | #include "hw/misc/aspeed_scu.h" | ||
| 48 | #include "hw/misc/aspeed_sdmc.h" | ||
| 49 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState { | ||
| 50 | /*< public >*/ | ||
| 51 | ARMCPU cpu[ASPEED_CPUS_NUM]; | ||
| 52 | uint32_t num_cpus; | ||
| 53 | + A15MPPrivState a7mpcore; | ||
| 54 | MemoryRegion sram; | ||
| 55 | AspeedVICState vic; | ||
| 56 | AspeedRtcState rtc; | ||
| 57 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState { | ||
| 58 | AspeedWDTState wdt[ASPEED_WDTS_NUM]; | ||
| 59 | FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; | ||
| 60 | AspeedGPIOState gpio; | ||
| 61 | + AspeedGPIOState gpio_1_8v; | ||
| 62 | AspeedSDHCIState sdhci; | ||
| 63 | } AspeedSoCState; | ||
| 64 | |||
| 65 | @@ -XXX,XX +XXX,XX @@ enum { | ||
| 66 | ASPEED_SRAM, | ||
| 67 | ASPEED_SDHCI, | ||
| 68 | ASPEED_GPIO, | ||
| 69 | + ASPEED_GPIO_1_8V, | ||
| 70 | ASPEED_RTC, | ||
| 71 | ASPEED_TIMER1, | ||
| 72 | ASPEED_TIMER2, | ||
| 73 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c | ||
| 74 | new file mode 100644 | ||
| 75 | index XXXXXXX..XXXXXXX | ||
| 76 | --- /dev/null | ||
| 77 | +++ b/hw/arm/aspeed_ast2600.c | ||
| 78 | @@ -XXX,XX +XXX,XX @@ | ||
| 79 | +/* | ||
| 80 | + * ASPEED SoC 2600 family | ||
| 81 | + * | ||
| 82 | + * Copyright (c) 2016-2019, IBM Corporation. | ||
| 83 | + * | ||
| 84 | + * This code is licensed under the GPL version 2 or later. See | ||
| 85 | + * the COPYING file in the top-level directory. | ||
| 86 | + */ | ||
| 87 | + | 28 | + |
| 88 | +#include "qemu/osdep.h" | 29 | +floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) |
| 89 | +#include "qapi/error.h" | 30 | +{ |
| 90 | +#include "cpu.h" | 31 | + bool aIsLargerSignificand; |
| 91 | +#include "exec/address-spaces.h" | 32 | + FloatClass a_cls, b_cls; |
| 92 | +#include "hw/misc/unimp.h" | ||
| 93 | +#include "hw/arm/aspeed_soc.h" | ||
| 94 | +#include "hw/char/serial.h" | ||
| 95 | +#include "qemu/log.h" | ||
| 96 | +#include "qemu/module.h" | ||
| 97 | +#include "qemu/error-report.h" | ||
| 98 | +#include "hw/i2c/aspeed_i2c.h" | ||
| 99 | +#include "net/net.h" | ||
| 100 | +#include "sysemu/sysemu.h" | ||
| 101 | + | 33 | + |
| 102 | +#define ASPEED_SOC_IOMEM_SIZE 0x00200000 | 34 | + /* This is not complete, but is good enough for pickNaN. */ |
| 35 | + a_cls = (!floatx80_is_any_nan(a) | ||
| 36 | + ? float_class_normal | ||
| 37 | + : floatx80_is_signaling_nan(a, status) | ||
| 38 | + ? float_class_snan | ||
| 39 | + : float_class_qnan); | ||
| 40 | + b_cls = (!floatx80_is_any_nan(b) | ||
| 41 | + ? float_class_normal | ||
| 42 | + : floatx80_is_signaling_nan(b, status) | ||
| 43 | + ? float_class_snan | ||
| 44 | + : float_class_qnan); | ||
| 103 | + | 45 | + |
| 104 | +static const hwaddr aspeed_soc_ast2600_memmap[] = { | 46 | + if (is_snan(a_cls) || is_snan(b_cls)) { |
| 105 | + [ASPEED_SRAM] = 0x10000000, | 47 | + float_raise(float_flag_invalid, status); |
| 106 | + /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ | ||
| 107 | + [ASPEED_IOMEM] = 0x1E600000, | ||
| 108 | + [ASPEED_PWM] = 0x1E610000, | ||
| 109 | + [ASPEED_FMC] = 0x1E620000, | ||
| 110 | + [ASPEED_SPI1] = 0x1E630000, | ||
| 111 | + [ASPEED_SPI2] = 0x1E641000, | ||
| 112 | + [ASPEED_ETH1] = 0x1E660000, | ||
| 113 | + [ASPEED_ETH2] = 0x1E680000, | ||
| 114 | + [ASPEED_VIC] = 0x1E6C0000, | ||
| 115 | + [ASPEED_SDMC] = 0x1E6E0000, | ||
| 116 | + [ASPEED_SCU] = 0x1E6E2000, | ||
| 117 | + [ASPEED_XDMA] = 0x1E6E7000, | ||
| 118 | + [ASPEED_ADC] = 0x1E6E9000, | ||
| 119 | + [ASPEED_SDHCI] = 0x1E740000, | ||
| 120 | + [ASPEED_GPIO] = 0x1E780000, | ||
| 121 | + [ASPEED_GPIO_1_8V] = 0x1E780800, | ||
| 122 | + [ASPEED_RTC] = 0x1E781000, | ||
| 123 | + [ASPEED_TIMER1] = 0x1E782000, | ||
| 124 | + [ASPEED_WDT] = 0x1E785000, | ||
| 125 | + [ASPEED_LPC] = 0x1E789000, | ||
| 126 | + [ASPEED_IBT] = 0x1E789140, | ||
| 127 | + [ASPEED_I2C] = 0x1E78A000, | ||
| 128 | + [ASPEED_UART1] = 0x1E783000, | ||
| 129 | + [ASPEED_UART5] = 0x1E784000, | ||
| 130 | + [ASPEED_VUART] = 0x1E787000, | ||
| 131 | + [ASPEED_SDRAM] = 0x80000000, | ||
| 132 | +}; | ||
| 133 | + | ||
| 134 | +#define ASPEED_A7MPCORE_ADDR 0x40460000 | ||
| 135 | + | ||
| 136 | +#define ASPEED_SOC_AST2600_MAX_IRQ 128 | ||
| 137 | + | ||
| 138 | +static const int aspeed_soc_ast2600_irqmap[] = { | ||
| 139 | + [ASPEED_UART1] = 47, | ||
| 140 | + [ASPEED_UART2] = 48, | ||
| 141 | + [ASPEED_UART3] = 49, | ||
| 142 | + [ASPEED_UART4] = 50, | ||
| 143 | + [ASPEED_UART5] = 8, | ||
| 144 | + [ASPEED_VUART] = 8, | ||
| 145 | + [ASPEED_FMC] = 39, | ||
| 146 | + [ASPEED_SDMC] = 0, | ||
| 147 | + [ASPEED_SCU] = 12, | ||
| 148 | + [ASPEED_ADC] = 78, | ||
| 149 | + [ASPEED_XDMA] = 6, | ||
| 150 | + [ASPEED_SDHCI] = 43, | ||
| 151 | + [ASPEED_GPIO] = 40, | ||
| 152 | + [ASPEED_GPIO_1_8V] = 11, | ||
| 153 | + [ASPEED_RTC] = 13, | ||
| 154 | + [ASPEED_TIMER1] = 16, | ||
| 155 | + [ASPEED_TIMER2] = 17, | ||
| 156 | + [ASPEED_TIMER3] = 18, | ||
| 157 | + [ASPEED_TIMER4] = 19, | ||
| 158 | + [ASPEED_TIMER5] = 20, | ||
| 159 | + [ASPEED_TIMER6] = 21, | ||
| 160 | + [ASPEED_TIMER7] = 22, | ||
| 161 | + [ASPEED_TIMER8] = 23, | ||
| 162 | + [ASPEED_WDT] = 24, | ||
| 163 | + [ASPEED_PWM] = 44, | ||
| 164 | + [ASPEED_LPC] = 35, | ||
| 165 | + [ASPEED_IBT] = 35, /* LPC */ | ||
| 166 | + [ASPEED_I2C] = 110, /* 110 -> 125 */ | ||
| 167 | + [ASPEED_ETH1] = 2, | ||
| 168 | + [ASPEED_ETH2] = 3, | ||
| 169 | +}; | ||
| 170 | + | ||
| 171 | +static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) | ||
| 172 | +{ | ||
| 173 | + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
| 174 | + | ||
| 175 | + return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); | ||
| 176 | +} | ||
| 177 | + | ||
| 178 | +static void aspeed_soc_ast2600_init(Object *obj) | ||
| 179 | +{ | ||
| 180 | + AspeedSoCState *s = ASPEED_SOC(obj); | ||
| 181 | + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
| 182 | + int i; | ||
| 183 | + char socname[8]; | ||
| 184 | + char typename[64]; | ||
| 185 | + | ||
| 186 | + if (sscanf(sc->name, "%7s", socname) != 1) { | ||
| 187 | + g_assert_not_reached(); | ||
| 188 | + } | 48 | + } |
| 189 | + | 49 | + |
| 190 | + for (i = 0; i < sc->num_cpus; i++) { | 50 | + if (status->default_nan_mode) { |
| 191 | + object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), | 51 | + return floatx80_default_nan(status); |
| 192 | + sizeof(s->cpu[i]), sc->cpu_type, | ||
| 193 | + &error_abort, NULL); | ||
| 194 | + } | 52 | + } |
| 195 | + | 53 | + |
| 196 | + snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); | 54 | + if (a.low < b.low) { |
| 197 | + sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu), | 55 | + aIsLargerSignificand = 0; |
| 198 | + typename); | 56 | + } else if (b.low < a.low) { |
| 199 | + qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", | 57 | + aIsLargerSignificand = 1; |
| 200 | + sc->silicon_rev); | 58 | + } else { |
| 201 | + object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), | 59 | + aIsLargerSignificand = (a.high < b.high) ? 1 : 0; |
| 202 | + "hw-strap1", &error_abort); | ||
| 203 | + object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), | ||
| 204 | + "hw-strap2", &error_abort); | ||
| 205 | + object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), | ||
| 206 | + "hw-prot-key", &error_abort); | ||
| 207 | + | ||
| 208 | + sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, | ||
| 209 | + sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV); | ||
| 210 | + | ||
| 211 | + sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc), | ||
| 212 | + TYPE_ASPEED_RTC); | ||
| 213 | + | ||
| 214 | + snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); | ||
| 215 | + sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl), | ||
| 216 | + sizeof(s->timerctrl), typename); | ||
| 217 | + object_property_add_const_link(OBJECT(&s->timerctrl), "scu", | ||
| 218 | + OBJECT(&s->scu), &error_abort); | ||
| 219 | + | ||
| 220 | + snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); | ||
| 221 | + sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c), | ||
| 222 | + typename); | ||
| 223 | + | ||
| 224 | + snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); | ||
| 225 | + sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc), | ||
| 226 | + typename); | ||
| 227 | + object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs", | ||
| 228 | + &error_abort); | ||
| 229 | + object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram", | ||
| 230 | + &error_abort); | ||
| 231 | + | ||
| 232 | + for (i = 0; i < sc->spis_num; i++) { | ||
| 233 | + snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); | ||
| 234 | + sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]), | ||
| 235 | + sizeof(s->spi[i]), typename); | ||
| 236 | + } | 60 | + } |
| 237 | + | 61 | + |
| 238 | + snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); | 62 | + if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { |
| 239 | + sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc), | 63 | + if (is_snan(b_cls)) { |
| 240 | + typename); | 64 | + return floatx80_silence_nan(b, status); |
| 241 | + object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), | 65 | + } |
| 242 | + "ram-size", &error_abort); | 66 | + return b; |
| 243 | + object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), | 67 | + } else { |
| 244 | + "max-ram-size", &error_abort); | 68 | + if (is_snan(a_cls)) { |
| 245 | + | 69 | + return floatx80_silence_nan(a, status); |
| 246 | + for (i = 0; i < sc->wdts_num; i++) { | 70 | + } |
| 247 | + snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); | 71 | + return a; |
| 248 | + sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]), | ||
| 249 | + sizeof(s->wdt[i]), typename); | ||
| 250 | + object_property_add_const_link(OBJECT(&s->wdt[i]), "scu", | ||
| 251 | + OBJECT(&s->scu), &error_abort); | ||
| 252 | + } | ||
| 253 | + | ||
| 254 | + for (i = 0; i < ASPEED_MACS_NUM; i++) { | ||
| 255 | + sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]), | ||
| 256 | + sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); | ||
| 257 | + } | ||
| 258 | + | ||
| 259 | + sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma), | ||
| 260 | + TYPE_ASPEED_XDMA); | ||
| 261 | + | ||
| 262 | + snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); | ||
| 263 | + sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio), | ||
| 264 | + typename); | ||
| 265 | + | ||
| 266 | + snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); | ||
| 267 | + sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v), | ||
| 268 | + sizeof(s->gpio_1_8v), typename); | ||
| 269 | + | ||
| 270 | + sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), | ||
| 271 | + TYPE_ASPEED_SDHCI); | ||
| 272 | + | ||
| 273 | + /* Init sd card slot class here so that they're under the correct parent */ | ||
| 274 | + for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | ||
| 275 | + sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), | ||
| 276 | + sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); | ||
| 277 | + } | 72 | + } |
| 278 | +} | 73 | +} |
| 279 | + | 74 | + |
| 280 | +/* | 75 | /*---------------------------------------------------------------------------- |
| 281 | + * ASPEED ast2600 has 0xf as cluster ID | 76 | | Takes an abstract floating-point value having sign `zSign', exponent `zExp', |
| 282 | + * | 77 | | and extended significand formed by the concatenation of `zSig0' and `zSig1', |
| 283 | + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html | 78 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 284 | + */ | 79 | index XXXXXXX..XXXXXXX 100644 |
| 285 | +static uint64_t aspeed_calc_affinity(int cpu) | 80 | --- a/fpu/softfloat-specialize.c.inc |
| 286 | +{ | 81 | +++ b/fpu/softfloat-specialize.c.inc |
| 287 | + return (0xf << ARM_AFF1_SHIFT) | cpu; | 82 | @@ -XXX,XX +XXX,XX @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status) |
| 288 | +} | 83 | return a; |
| 289 | + | 84 | } |
| 290 | +static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | 85 | |
| 291 | +{ | 86 | -/*---------------------------------------------------------------------------- |
| 292 | + int i; | 87 | -| Takes two extended double-precision floating-point values `a' and `b', one |
| 293 | + AspeedSoCState *s = ASPEED_SOC(dev); | 88 | -| of which is a NaN, and returns the appropriate NaN result. If either `a' or |
| 294 | + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | 89 | -| `b' is a signaling NaN, the invalid exception is raised. |
| 295 | + Error *err = NULL, *local_err = NULL; | 90 | -*----------------------------------------------------------------------------*/ |
| 296 | + qemu_irq irq; | 91 | - |
| 297 | + | 92 | -floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) |
| 298 | + /* IO space */ | 93 | -{ |
| 299 | + create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], | 94 | - bool aIsLargerSignificand; |
| 300 | + ASPEED_SOC_IOMEM_SIZE); | 95 | - FloatClass a_cls, b_cls; |
| 301 | + | 96 | - |
| 302 | + if (s->num_cpus > sc->num_cpus) { | 97 | - /* This is not complete, but is good enough for pickNaN. */ |
| 303 | + warn_report("%s: invalid number of CPUs %d, using default %d", | 98 | - a_cls = (!floatx80_is_any_nan(a) |
| 304 | + sc->name, s->num_cpus, sc->num_cpus); | 99 | - ? float_class_normal |
| 305 | + s->num_cpus = sc->num_cpus; | 100 | - : floatx80_is_signaling_nan(a, status) |
| 306 | + } | 101 | - ? float_class_snan |
| 307 | + | 102 | - : float_class_qnan); |
| 308 | + /* CPU */ | 103 | - b_cls = (!floatx80_is_any_nan(b) |
| 309 | + for (i = 0; i < s->num_cpus; i++) { | 104 | - ? float_class_normal |
| 310 | + object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC, | 105 | - : floatx80_is_signaling_nan(b, status) |
| 311 | + "psci-conduit", &error_abort); | 106 | - ? float_class_snan |
| 312 | + if (s->num_cpus > 1) { | 107 | - : float_class_qnan); |
| 313 | + object_property_set_int(OBJECT(&s->cpu[i]), | 108 | - |
| 314 | + ASPEED_A7MPCORE_ADDR, | 109 | - if (is_snan(a_cls) || is_snan(b_cls)) { |
| 315 | + "reset-cbar", &error_abort); | 110 | - float_raise(float_flag_invalid, status); |
| 316 | + } | 111 | - } |
| 317 | + object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i), | 112 | - |
| 318 | + "mp-affinity", &error_abort); | 113 | - if (status->default_nan_mode) { |
| 319 | + | 114 | - return floatx80_default_nan(status); |
| 320 | + /* | 115 | - } |
| 321 | + * TODO: the secondary CPUs are started and a boot helper | 116 | - |
| 322 | + * is needed when using -kernel | 117 | - if (a.low < b.low) { |
| 323 | + */ | 118 | - aIsLargerSignificand = 0; |
| 324 | + | 119 | - } else if (b.low < a.low) { |
| 325 | + object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); | 120 | - aIsLargerSignificand = 1; |
| 326 | + if (err) { | 121 | - } else { |
| 327 | + error_propagate(errp, err); | 122 | - aIsLargerSignificand = (a.high < b.high) ? 1 : 0; |
| 328 | + return; | 123 | - } |
| 329 | + } | 124 | - |
| 330 | + } | 125 | - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { |
| 331 | + | 126 | - if (is_snan(b_cls)) { |
| 332 | + /* A7MPCORE */ | 127 | - return floatx80_silence_nan(b, status); |
| 333 | + object_property_set_int(OBJECT(&s->a7mpcore), s->num_cpus, "num-cpu", | 128 | - } |
| 334 | + &error_abort); | 129 | - return b; |
| 335 | + object_property_set_int(OBJECT(&s->a7mpcore), | 130 | - } else { |
| 336 | + ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL, | 131 | - if (is_snan(a_cls)) { |
| 337 | + "num-irq", &error_abort); | 132 | - return floatx80_silence_nan(a, status); |
| 338 | + | 133 | - } |
| 339 | + object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized", | 134 | - return a; |
| 340 | + &error_abort); | 135 | - } |
| 341 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); | 136 | -} |
| 342 | + | 137 | - |
| 343 | + for (i = 0; i < s->num_cpus; i++) { | 138 | /*---------------------------------------------------------------------------- |
| 344 | + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); | 139 | | Returns 1 if the quadruple-precision floating-point value `a' is a quiet |
| 345 | + DeviceState *d = DEVICE(qemu_get_cpu(i)); | 140 | | NaN; otherwise returns 0. |
| 346 | + | ||
| 347 | + irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); | ||
| 348 | + sysbus_connect_irq(sbd, i, irq); | ||
| 349 | + irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); | ||
| 350 | + sysbus_connect_irq(sbd, i + s->num_cpus, irq); | ||
| 351 | + irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); | ||
| 352 | + sysbus_connect_irq(sbd, i + 2 * s->num_cpus, irq); | ||
| 353 | + irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); | ||
| 354 | + sysbus_connect_irq(sbd, i + 3 * s->num_cpus, irq); | ||
| 355 | + } | ||
| 356 | + | ||
| 357 | + /* SRAM */ | ||
| 358 | + memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", | ||
| 359 | + sc->sram_size, &err); | ||
| 360 | + if (err) { | ||
| 361 | + error_propagate(errp, err); | ||
| 362 | + return; | ||
| 363 | + } | ||
| 364 | + memory_region_add_subregion(get_system_memory(), | ||
| 365 | + sc->memmap[ASPEED_SRAM], &s->sram); | ||
| 366 | + | ||
| 367 | + /* SCU */ | ||
| 368 | + object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); | ||
| 369 | + if (err) { | ||
| 370 | + error_propagate(errp, err); | ||
| 371 | + return; | ||
| 372 | + } | ||
| 373 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]); | ||
| 374 | + | ||
| 375 | + /* RTC */ | ||
| 376 | + object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); | ||
| 377 | + if (err) { | ||
| 378 | + error_propagate(errp, err); | ||
| 379 | + return; | ||
| 380 | + } | ||
| 381 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]); | ||
| 382 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, | ||
| 383 | + aspeed_soc_get_irq(s, ASPEED_RTC)); | ||
| 384 | + | ||
| 385 | + /* Timer */ | ||
| 386 | + object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err); | ||
| 387 | + if (err) { | ||
| 388 | + error_propagate(errp, err); | ||
| 389 | + return; | ||
| 390 | + } | ||
| 391 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, | ||
| 392 | + sc->memmap[ASPEED_TIMER1]); | ||
| 393 | + for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { | ||
| 394 | + qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); | ||
| 395 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); | ||
| 396 | + } | ||
| 397 | + | ||
| 398 | + /* UART - attach an 8250 to the IO space as our UART5 */ | ||
| 399 | + if (serial_hd(0)) { | ||
| 400 | + qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5); | ||
| 401 | + serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2, | ||
| 402 | + uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); | ||
| 403 | + } | ||
| 404 | + | ||
| 405 | + /* I2C */ | ||
| 406 | + object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err); | ||
| 407 | + if (err) { | ||
| 408 | + error_propagate(errp, err); | ||
| 409 | + return; | ||
| 410 | + } | ||
| 411 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]); | ||
| 412 | + for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { | ||
| 413 | + qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
| 414 | + sc->irqmap[ASPEED_I2C] + i); | ||
| 415 | + /* | ||
| 416 | + * The AST2600 SoC has one IRQ per I2C bus. Skip the common | ||
| 417 | + * IRQ (AST2400 and AST2500) and connect all bussses. | ||
| 418 | + */ | ||
| 419 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq); | ||
| 420 | + } | ||
| 421 | + | ||
| 422 | + /* FMC, The number of CS is set at the board level */ | ||
| 423 | + object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], | ||
| 424 | + "sdram-base", &err); | ||
| 425 | + if (err) { | ||
| 426 | + error_propagate(errp, err); | ||
| 427 | + return; | ||
| 428 | + } | ||
| 429 | + object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); | ||
| 430 | + if (err) { | ||
| 431 | + error_propagate(errp, err); | ||
| 432 | + return; | ||
| 433 | + } | ||
| 434 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]); | ||
| 435 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, | ||
| 436 | + s->fmc.ctrl->flash_window_base); | ||
| 437 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, | ||
| 438 | + aspeed_soc_get_irq(s, ASPEED_FMC)); | ||
| 439 | + | ||
| 440 | + /* SPI */ | ||
| 441 | + for (i = 0; i < sc->spis_num; i++) { | ||
| 442 | + object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err); | ||
| 443 | + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", | ||
| 444 | + &local_err); | ||
| 445 | + error_propagate(&err, local_err); | ||
| 446 | + if (err) { | ||
| 447 | + error_propagate(errp, err); | ||
| 448 | + return; | ||
| 449 | + } | ||
| 450 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, | ||
| 451 | + sc->memmap[ASPEED_SPI1 + i]); | ||
| 452 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, | ||
| 453 | + s->spi[i].ctrl->flash_window_base); | ||
| 454 | + } | ||
| 455 | + | ||
| 456 | + /* SDMC - SDRAM Memory Controller */ | ||
| 457 | + object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); | ||
| 458 | + if (err) { | ||
| 459 | + error_propagate(errp, err); | ||
| 460 | + return; | ||
| 461 | + } | ||
| 462 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]); | ||
| 463 | + | ||
| 464 | + /* Watch dog */ | ||
| 465 | + for (i = 0; i < sc->wdts_num; i++) { | ||
| 466 | + AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); | ||
| 467 | + | ||
| 468 | + object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); | ||
| 469 | + if (err) { | ||
| 470 | + error_propagate(errp, err); | ||
| 471 | + return; | ||
| 472 | + } | ||
| 473 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | ||
| 474 | + sc->memmap[ASPEED_WDT] + i * awc->offset); | ||
| 475 | + } | ||
| 476 | + | ||
| 477 | + /* Net */ | ||
| 478 | + for (i = 0; i < nb_nics; i++) { | ||
| 479 | + qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]); | ||
| 480 | + object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", | ||
| 481 | + &err); | ||
| 482 | + object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized", | ||
| 483 | + &local_err); | ||
| 484 | + error_propagate(&err, local_err); | ||
| 485 | + if (err) { | ||
| 486 | + error_propagate(errp, err); | ||
| 487 | + return; | ||
| 488 | + } | ||
| 489 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | ||
| 490 | + sc->memmap[ASPEED_ETH1 + i]); | ||
| 491 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | ||
| 492 | + aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); | ||
| 493 | + } | ||
| 494 | + | ||
| 495 | + /* XDMA */ | ||
| 496 | + object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err); | ||
| 497 | + if (err) { | ||
| 498 | + error_propagate(errp, err); | ||
| 499 | + return; | ||
| 500 | + } | ||
| 501 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, | ||
| 502 | + sc->memmap[ASPEED_XDMA]); | ||
| 503 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, | ||
| 504 | + aspeed_soc_get_irq(s, ASPEED_XDMA)); | ||
| 505 | + | ||
| 506 | + /* GPIO */ | ||
| 507 | + object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); | ||
| 508 | + if (err) { | ||
| 509 | + error_propagate(errp, err); | ||
| 510 | + return; | ||
| 511 | + } | ||
| 512 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]); | ||
| 513 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, | ||
| 514 | + aspeed_soc_get_irq(s, ASPEED_GPIO)); | ||
| 515 | + | ||
| 516 | + object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err); | ||
| 517 | + if (err) { | ||
| 518 | + error_propagate(errp, err); | ||
| 519 | + return; | ||
| 520 | + } | ||
| 521 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, | ||
| 522 | + sc->memmap[ASPEED_GPIO_1_8V]); | ||
| 523 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, | ||
| 524 | + aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V)); | ||
| 525 | + | ||
| 526 | + /* SDHCI */ | ||
| 527 | + object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err); | ||
| 528 | + if (err) { | ||
| 529 | + error_propagate(errp, err); | ||
| 530 | + return; | ||
| 531 | + } | ||
| 532 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, | ||
| 533 | + sc->memmap[ASPEED_SDHCI]); | ||
| 534 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, | ||
| 535 | + aspeed_soc_get_irq(s, ASPEED_SDHCI)); | ||
| 536 | +} | ||
| 537 | + | ||
| 538 | +static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) | ||
| 539 | +{ | ||
| 540 | + DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 541 | + AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | ||
| 542 | + | ||
| 543 | + dc->realize = aspeed_soc_ast2600_realize; | ||
| 544 | + | ||
| 545 | + sc->name = "ast2600-a0"; | ||
| 546 | + sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); | ||
| 547 | + sc->silicon_rev = AST2600_A0_SILICON_REV; | ||
| 548 | + sc->sram_size = 0x10000; | ||
| 549 | + sc->spis_num = 2; | ||
| 550 | + sc->wdts_num = 4; | ||
| 551 | + sc->irqmap = aspeed_soc_ast2600_irqmap; | ||
| 552 | + sc->memmap = aspeed_soc_ast2600_memmap; | ||
| 553 | + sc->num_cpus = 2; | ||
| 554 | +} | ||
| 555 | + | ||
| 556 | +static const TypeInfo aspeed_soc_ast2600_type_info = { | ||
| 557 | + .name = "ast2600-a0", | ||
| 558 | + .parent = TYPE_ASPEED_SOC, | ||
| 559 | + .instance_size = sizeof(AspeedSoCState), | ||
| 560 | + .instance_init = aspeed_soc_ast2600_init, | ||
| 561 | + .class_init = aspeed_soc_ast2600_class_init, | ||
| 562 | + .class_size = sizeof(AspeedSoCClass), | ||
| 563 | +}; | ||
| 564 | + | ||
| 565 | +static void aspeed_soc_register_types(void) | ||
| 566 | +{ | ||
| 567 | + type_register_static(&aspeed_soc_ast2600_type_info); | ||
| 568 | +}; | ||
| 569 | + | ||
| 570 | +type_init(aspeed_soc_register_types) | ||
| 571 | -- | 141 | -- |
| 572 | 2.20.1 | 142 | 2.34.1 |
| 573 | |||
| 574 | diff view generated by jsdifflib |
| 1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | It cleanups the current models for the Aspeed AST2400 and AST2500 SoCs | 3 | Unpacking and repacking the parts may be slightly more work |
| 4 | and prepares ground for future SoCs. | 4 | than we did before, but we get to reuse more code. For a |
| 5 | code path handling exceptional values, this is an improvement. | ||
| 5 | 6 | ||
| 6 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 7 | Reviewed-by: Joel Stanley <joel@jms.id.au> | 8 | Message-id: 20241203203949.483774-8-richard.henderson@linaro.org |
| 8 | Message-id: 20190925143248.10000-11-clg@kaod.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | 11 | --- |
| 11 | include/hw/watchdog/wdt_aspeed.h | 18 ++++- | 12 | fpu/softfloat.c | 43 +++++-------------------------------------- |
| 12 | hw/arm/aspeed_soc.c | 9 ++- | 13 | 1 file changed, 5 insertions(+), 38 deletions(-) |
| 13 | hw/watchdog/wdt_aspeed.c | 122 ++++++++++++++++--------------- | ||
| 14 | 3 files changed, 86 insertions(+), 63 deletions(-) | ||
| 15 | 14 | ||
| 16 | diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h | 15 | diff --git a/fpu/softfloat.c b/fpu/softfloat.c |
| 17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/include/hw/watchdog/wdt_aspeed.h | 17 | --- a/fpu/softfloat.c |
| 19 | +++ b/include/hw/watchdog/wdt_aspeed.h | 18 | +++ b/fpu/softfloat.c |
| 20 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, |
| 21 | #define TYPE_ASPEED_WDT "aspeed.wdt" | 20 | |
| 22 | #define ASPEED_WDT(obj) \ | 21 | floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) |
| 23 | OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT) | 22 | { |
| 24 | +#define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400" | 23 | - bool aIsLargerSignificand; |
| 25 | +#define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500" | 24 | - FloatClass a_cls, b_cls; |
| 26 | 25 | + FloatParts128 pa, pb, *pr; | |
| 27 | #define ASPEED_WDT_REGS_MAX (0x20 / 4) | 26 | |
| 28 | 27 | - /* This is not complete, but is good enough for pickNaN. */ | |
| 29 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedWDTState { | 28 | - a_cls = (!floatx80_is_any_nan(a) |
| 30 | 29 | - ? float_class_normal | |
| 31 | AspeedSCUState *scu; | 30 | - : floatx80_is_signaling_nan(a, status) |
| 32 | uint32_t pclk_freq; | 31 | - ? float_class_snan |
| 33 | - uint32_t silicon_rev; | 32 | - : float_class_qnan); |
| 34 | - uint32_t ext_pulse_width_mask; | 33 | - b_cls = (!floatx80_is_any_nan(b) |
| 35 | } AspeedWDTState; | 34 | - ? float_class_normal |
| 36 | 35 | - : floatx80_is_signaling_nan(b, status) | |
| 37 | +#define ASPEED_WDT_CLASS(klass) \ | 36 | - ? float_class_snan |
| 38 | + OBJECT_CLASS_CHECK(AspeedWDTClass, (klass), TYPE_ASPEED_WDT) | 37 | - : float_class_qnan); |
| 39 | +#define ASPEED_WDT_GET_CLASS(obj) \ | 38 | - |
| 40 | + OBJECT_GET_CLASS(AspeedWDTClass, (obj), TYPE_ASPEED_WDT) | 39 | - if (is_snan(a_cls) || is_snan(b_cls)) { |
| 41 | + | 40 | - float_raise(float_flag_invalid, status); |
| 42 | +typedef struct AspeedWDTClass { | ||
| 43 | + SysBusDeviceClass parent_class; | ||
| 44 | + | ||
| 45 | + uint32_t offset; | ||
| 46 | + uint32_t ext_pulse_width_mask; | ||
| 47 | + uint32_t reset_ctrl_reg; | ||
| 48 | + void (*reset_pulse)(AspeedWDTState *s, uint32_t property); | ||
| 49 | +} AspeedWDTClass; | ||
| 50 | + | ||
| 51 | #endif /* WDT_ASPEED_H */ | ||
| 52 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
| 53 | index XXXXXXX..XXXXXXX 100644 | ||
| 54 | --- a/hw/arm/aspeed_soc.c | ||
| 55 | +++ b/hw/arm/aspeed_soc.c | ||
| 56 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | ||
| 57 | "max-ram-size", &error_abort); | ||
| 58 | |||
| 59 | for (i = 0; i < sc->info->wdts_num; i++) { | ||
| 60 | + snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); | ||
| 61 | sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]), | ||
| 62 | - sizeof(s->wdt[i]), TYPE_ASPEED_WDT); | ||
| 63 | - qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev", | ||
| 64 | - sc->info->silicon_rev); | ||
| 65 | + sizeof(s->wdt[i]), typename); | ||
| 66 | object_property_add_const_link(OBJECT(&s->wdt[i]), "scu", | ||
| 67 | OBJECT(&s->scu), &error_abort); | ||
| 68 | } | ||
| 69 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
| 70 | |||
| 71 | /* Watch dog */ | ||
| 72 | for (i = 0; i < sc->info->wdts_num; i++) { | ||
| 73 | + AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); | ||
| 74 | + | ||
| 75 | object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); | ||
| 76 | if (err) { | ||
| 77 | error_propagate(errp, err); | ||
| 78 | return; | ||
| 79 | } | ||
| 80 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | ||
| 81 | - sc->info->memmap[ASPEED_WDT] + i * 0x20); | ||
| 82 | + sc->info->memmap[ASPEED_WDT] + i * awc->offset); | ||
| 83 | } | ||
| 84 | |||
| 85 | /* Net */ | ||
| 86 | diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c | ||
| 87 | index XXXXXXX..XXXXXXX 100644 | ||
| 88 | --- a/hw/watchdog/wdt_aspeed.c | ||
| 89 | +++ b/hw/watchdog/wdt_aspeed.c | ||
| 90 | @@ -XXX,XX +XXX,XX @@ static bool aspeed_wdt_is_enabled(const AspeedWDTState *s) | ||
| 91 | return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE; | ||
| 92 | } | ||
| 93 | |||
| 94 | -static bool is_ast2500(const AspeedWDTState *s) | ||
| 95 | -{ | ||
| 96 | - switch (s->silicon_rev) { | ||
| 97 | - case AST2500_A0_SILICON_REV: | ||
| 98 | - case AST2500_A1_SILICON_REV: | ||
| 99 | - return true; | ||
| 100 | - case AST2400_A0_SILICON_REV: | ||
| 101 | - case AST2400_A1_SILICON_REV: | ||
| 102 | - default: | ||
| 103 | - break; | ||
| 104 | - } | 41 | - } |
| 105 | - | 42 | - |
| 106 | - return false; | 43 | - if (status->default_nan_mode) { |
| 107 | -} | 44 | + if (!floatx80_unpack_canonical(&pa, a, status) || |
| 108 | - | 45 | + !floatx80_unpack_canonical(&pb, b, status)) { |
| 109 | static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) | 46 | return floatx80_default_nan(status); |
| 110 | { | ||
| 111 | AspeedWDTState *s = ASPEED_WDT(opaque); | ||
| 112 | @@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, | ||
| 113 | unsigned size) | ||
| 114 | { | ||
| 115 | AspeedWDTState *s = ASPEED_WDT(opaque); | ||
| 116 | + AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s); | ||
| 117 | bool enable = data & WDT_CTRL_ENABLE; | ||
| 118 | |||
| 119 | offset >>= 2; | ||
| 120 | @@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, | ||
| 121 | } | ||
| 122 | break; | ||
| 123 | case WDT_RESET_WIDTH: | ||
| 124 | - { | ||
| 125 | - uint32_t property = data & WDT_POLARITY_MASK; | ||
| 126 | - | ||
| 127 | - if (property && is_ast2500(s)) { | ||
| 128 | - if (property == WDT_ACTIVE_HIGH_MAGIC) { | ||
| 129 | - s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH; | ||
| 130 | - } else if (property == WDT_ACTIVE_LOW_MAGIC) { | ||
| 131 | - s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH; | ||
| 132 | - } else if (property == WDT_PUSH_PULL_MAGIC) { | ||
| 133 | - s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL; | ||
| 134 | - } else if (property == WDT_OPEN_DRAIN_MAGIC) { | ||
| 135 | - s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL; | ||
| 136 | - } | ||
| 137 | + if (awc->reset_pulse) { | ||
| 138 | + awc->reset_pulse(s, data & WDT_POLARITY_MASK); | ||
| 139 | } | ||
| 140 | - s->regs[WDT_RESET_WIDTH] &= ~s->ext_pulse_width_mask; | ||
| 141 | - s->regs[WDT_RESET_WIDTH] |= data & s->ext_pulse_width_mask; | ||
| 142 | + s->regs[WDT_RESET_WIDTH] &= ~awc->ext_pulse_width_mask; | ||
| 143 | + s->regs[WDT_RESET_WIDTH] |= data & awc->ext_pulse_width_mask; | ||
| 144 | break; | ||
| 145 | - } | ||
| 146 | + | ||
| 147 | case WDT_TIMEOUT_STATUS: | ||
| 148 | case WDT_TIMEOUT_CLEAR: | ||
| 149 | qemu_log_mask(LOG_UNIMP, | ||
| 150 | @@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_reset(DeviceState *dev) | ||
| 151 | static void aspeed_wdt_timer_expired(void *dev) | ||
| 152 | { | ||
| 153 | AspeedWDTState *s = ASPEED_WDT(dev); | ||
| 154 | + uint32_t reset_ctrl_reg = ASPEED_WDT_GET_CLASS(s)->reset_ctrl_reg; | ||
| 155 | |||
| 156 | /* Do not reset on SDRAM controller reset */ | ||
| 157 | - if (s->scu->regs[SCU_RESET_CONTROL1] & SCU_RESET_SDRAM) { | ||
| 158 | + if (s->scu->regs[reset_ctrl_reg] & SCU_RESET_SDRAM) { | ||
| 159 | timer_del(s->timer); | ||
| 160 | s->regs[WDT_CTRL] = 0; | ||
| 161 | return; | ||
| 162 | @@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp) | ||
| 163 | } | 47 | } |
| 164 | s->scu = ASPEED_SCU(obj); | 48 | |
| 165 | 49 | - if (a.low < b.low) { | |
| 166 | - if (!is_supported_silicon_rev(s->silicon_rev)) { | 50 | - aIsLargerSignificand = 0; |
| 167 | - error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, | 51 | - } else if (b.low < a.low) { |
| 168 | - s->silicon_rev); | 52 | - aIsLargerSignificand = 1; |
| 169 | - return; | 53 | - } else { |
| 54 | - aIsLargerSignificand = (a.high < b.high) ? 1 : 0; | ||
| 170 | - } | 55 | - } |
| 171 | - | 56 | - |
| 172 | - switch (s->silicon_rev) { | 57 | - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { |
| 173 | - case AST2400_A0_SILICON_REV: | 58 | - if (is_snan(b_cls)) { |
| 174 | - case AST2400_A1_SILICON_REV: | 59 | - return floatx80_silence_nan(b, status); |
| 175 | - s->ext_pulse_width_mask = 0xff; | 60 | - } |
| 176 | - break; | 61 | - return b; |
| 177 | - case AST2500_A0_SILICON_REV: | 62 | - } else { |
| 178 | - case AST2500_A1_SILICON_REV: | 63 | - if (is_snan(a_cls)) { |
| 179 | - s->ext_pulse_width_mask = 0xfffff; | 64 | - return floatx80_silence_nan(a, status); |
| 180 | - break; | 65 | - } |
| 181 | - default: | 66 | - return a; |
| 182 | - g_assert_not_reached(); | ||
| 183 | - } | 67 | - } |
| 184 | - | 68 | + pr = parts_pick_nan(&pa, &pb, status); |
| 185 | s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev); | 69 | + return floatx80_round_pack_canonical(pr, status); |
| 186 | |||
| 187 | /* FIXME: This setting should be derived from the SCU hw strapping | ||
| 188 | @@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp) | ||
| 189 | sysbus_init_mmio(sbd, &s->iomem); | ||
| 190 | } | 70 | } |
| 191 | 71 | ||
| 192 | -static Property aspeed_wdt_properties[] = { | 72 | /*---------------------------------------------------------------------------- |
| 193 | - DEFINE_PROP_UINT32("silicon-rev", AspeedWDTState, silicon_rev, 0), | ||
| 194 | - DEFINE_PROP_END_OF_LIST(), | ||
| 195 | -}; | ||
| 196 | - | ||
| 197 | static void aspeed_wdt_class_init(ObjectClass *klass, void *data) | ||
| 198 | { | ||
| 199 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 200 | |||
| 201 | + dc->desc = "ASPEED Watchdog Controller"; | ||
| 202 | dc->realize = aspeed_wdt_realize; | ||
| 203 | dc->reset = aspeed_wdt_reset; | ||
| 204 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 205 | dc->vmsd = &vmstate_aspeed_wdt; | ||
| 206 | - dc->props = aspeed_wdt_properties; | ||
| 207 | } | ||
| 208 | |||
| 209 | static const TypeInfo aspeed_wdt_info = { | ||
| 210 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_wdt_info = { | ||
| 211 | .name = TYPE_ASPEED_WDT, | ||
| 212 | .instance_size = sizeof(AspeedWDTState), | ||
| 213 | .class_init = aspeed_wdt_class_init, | ||
| 214 | + .class_size = sizeof(AspeedWDTClass), | ||
| 215 | + .abstract = true, | ||
| 216 | +}; | ||
| 217 | + | ||
| 218 | +static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data) | ||
| 219 | +{ | ||
| 220 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 221 | + AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); | ||
| 222 | + | ||
| 223 | + dc->desc = "ASPEED 2400 Watchdog Controller"; | ||
| 224 | + awc->offset = 0x20; | ||
| 225 | + awc->ext_pulse_width_mask = 0xff; | ||
| 226 | + awc->reset_ctrl_reg = SCU_RESET_CONTROL1; | ||
| 227 | +} | ||
| 228 | + | ||
| 229 | +static const TypeInfo aspeed_2400_wdt_info = { | ||
| 230 | + .name = TYPE_ASPEED_2400_WDT, | ||
| 231 | + .parent = TYPE_ASPEED_WDT, | ||
| 232 | + .instance_size = sizeof(AspeedWDTState), | ||
| 233 | + .class_init = aspeed_2400_wdt_class_init, | ||
| 234 | +}; | ||
| 235 | + | ||
| 236 | +static void aspeed_2500_wdt_reset_pulse(AspeedWDTState *s, uint32_t property) | ||
| 237 | +{ | ||
| 238 | + if (property) { | ||
| 239 | + if (property == WDT_ACTIVE_HIGH_MAGIC) { | ||
| 240 | + s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH; | ||
| 241 | + } else if (property == WDT_ACTIVE_LOW_MAGIC) { | ||
| 242 | + s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH; | ||
| 243 | + } else if (property == WDT_PUSH_PULL_MAGIC) { | ||
| 244 | + s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL; | ||
| 245 | + } else if (property == WDT_OPEN_DRAIN_MAGIC) { | ||
| 246 | + s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL; | ||
| 247 | + } | ||
| 248 | + } | ||
| 249 | +} | ||
| 250 | + | ||
| 251 | +static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data) | ||
| 252 | +{ | ||
| 253 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 254 | + AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); | ||
| 255 | + | ||
| 256 | + dc->desc = "ASPEED 2500 Watchdog Controller"; | ||
| 257 | + awc->offset = 0x20; | ||
| 258 | + awc->ext_pulse_width_mask = 0xfffff; | ||
| 259 | + awc->reset_ctrl_reg = SCU_RESET_CONTROL1; | ||
| 260 | + awc->reset_pulse = aspeed_2500_wdt_reset_pulse; | ||
| 261 | +} | ||
| 262 | + | ||
| 263 | +static const TypeInfo aspeed_2500_wdt_info = { | ||
| 264 | + .name = TYPE_ASPEED_2500_WDT, | ||
| 265 | + .parent = TYPE_ASPEED_WDT, | ||
| 266 | + .instance_size = sizeof(AspeedWDTState), | ||
| 267 | + .class_init = aspeed_2500_wdt_class_init, | ||
| 268 | }; | ||
| 269 | |||
| 270 | static void wdt_aspeed_register_types(void) | ||
| 271 | { | ||
| 272 | watchdog_add_model(&model); | ||
| 273 | type_register_static(&aspeed_wdt_info); | ||
| 274 | + type_register_static(&aspeed_2400_wdt_info); | ||
| 275 | + type_register_static(&aspeed_2500_wdt_info); | ||
| 276 | } | ||
| 277 | |||
| 278 | type_init(wdt_aspeed_register_types) | ||
| 279 | -- | 73 | -- |
| 280 | 2.20.1 | 74 | 2.34.1 |
| 281 | |||
| 282 | diff view generated by jsdifflib |
| 1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The AST2600 timer has a third control register that is used to | 3 | Inline pickNaN into its only caller. This makes one assert |
| 4 | implement a set-to-clear feature for the main control register. | 4 | redundant with the immediately preceding IF. |
| 5 | 5 | ||
| 6 | On the AST2600, it is not configurable via 0x38 (control register 3) | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 7 | as it is on the AST2500. | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 8 | 8 | Message-id: 20241203203949.483774-9-richard.henderson@linaro.org | |
| 9 | Based on previous work from Joel Stanley. | ||
| 10 | |||
| 11 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 12 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
| 13 | Message-id: 20190925143248.10000-7-clg@kaod.org | ||
| 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 15 | --- | 10 | --- |
| 16 | include/hw/timer/aspeed_timer.h | 1 + | 11 | fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++---- |
| 17 | hw/timer/aspeed_timer.c | 51 +++++++++++++++++++++++++++++++++ | 12 | fpu/softfloat-specialize.c.inc | 96 ---------------------------------- |
| 18 | 2 files changed, 52 insertions(+) | 13 | 2 files changed, 73 insertions(+), 105 deletions(-) |
| 19 | 14 | ||
| 20 | diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h | 15 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
| 21 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 22 | --- a/include/hw/timer/aspeed_timer.h | 17 | --- a/fpu/softfloat-parts.c.inc |
| 23 | +++ b/include/hw/timer/aspeed_timer.h | 18 | +++ b/fpu/softfloat-parts.c.inc |
| 24 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s) |
| 25 | #define TYPE_ASPEED_TIMER "aspeed.timer" | 20 | static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
| 26 | #define TYPE_ASPEED_2400_TIMER TYPE_ASPEED_TIMER "-ast2400" | 21 | float_status *s) |
| 27 | #define TYPE_ASPEED_2500_TIMER TYPE_ASPEED_TIMER "-ast2500" | 22 | { |
| 28 | +#define TYPE_ASPEED_2600_TIMER TYPE_ASPEED_TIMER "-ast2600" | 23 | + int cmp, which; |
| 29 | 24 | + | |
| 30 | #define ASPEED_TIMER_NR_TIMERS 8 | 25 | if (is_snan(a->cls) || is_snan(b->cls)) { |
| 31 | 26 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); | |
| 32 | diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c | 27 | } |
| 28 | |||
| 29 | if (s->default_nan_mode) { | ||
| 30 | parts_default_nan(a, s); | ||
| 31 | - } else { | ||
| 32 | - int cmp = frac_cmp(a, b); | ||
| 33 | - if (cmp == 0) { | ||
| 34 | - cmp = a->sign < b->sign; | ||
| 35 | - } | ||
| 36 | + return a; | ||
| 37 | + } | ||
| 38 | |||
| 39 | - if (pickNaN(a->cls, b->cls, cmp > 0, s)) { | ||
| 40 | - a = b; | ||
| 41 | - } | ||
| 42 | + cmp = frac_cmp(a, b); | ||
| 43 | + if (cmp == 0) { | ||
| 44 | + cmp = a->sign < b->sign; | ||
| 45 | + } | ||
| 46 | + | ||
| 47 | + switch (s->float_2nan_prop_rule) { | ||
| 48 | + case float_2nan_prop_s_ab: | ||
| 49 | if (is_snan(a->cls)) { | ||
| 50 | - parts_silence_nan(a, s); | ||
| 51 | + which = 0; | ||
| 52 | + } else if (is_snan(b->cls)) { | ||
| 53 | + which = 1; | ||
| 54 | + } else if (is_qnan(a->cls)) { | ||
| 55 | + which = 0; | ||
| 56 | + } else { | ||
| 57 | + which = 1; | ||
| 58 | } | ||
| 59 | + break; | ||
| 60 | + case float_2nan_prop_s_ba: | ||
| 61 | + if (is_snan(b->cls)) { | ||
| 62 | + which = 1; | ||
| 63 | + } else if (is_snan(a->cls)) { | ||
| 64 | + which = 0; | ||
| 65 | + } else if (is_qnan(b->cls)) { | ||
| 66 | + which = 1; | ||
| 67 | + } else { | ||
| 68 | + which = 0; | ||
| 69 | + } | ||
| 70 | + break; | ||
| 71 | + case float_2nan_prop_ab: | ||
| 72 | + which = is_nan(a->cls) ? 0 : 1; | ||
| 73 | + break; | ||
| 74 | + case float_2nan_prop_ba: | ||
| 75 | + which = is_nan(b->cls) ? 1 : 0; | ||
| 76 | + break; | ||
| 77 | + case float_2nan_prop_x87: | ||
| 78 | + /* | ||
| 79 | + * This implements x87 NaN propagation rules: | ||
| 80 | + * SNaN + QNaN => return the QNaN | ||
| 81 | + * two SNaNs => return the one with the larger significand, silenced | ||
| 82 | + * two QNaNs => return the one with the larger significand | ||
| 83 | + * SNaN and a non-NaN => return the SNaN, silenced | ||
| 84 | + * QNaN and a non-NaN => return the QNaN | ||
| 85 | + * | ||
| 86 | + * If we get down to comparing significands and they are the same, | ||
| 87 | + * return the NaN with the positive sign bit (if any). | ||
| 88 | + */ | ||
| 89 | + if (is_snan(a->cls)) { | ||
| 90 | + if (is_snan(b->cls)) { | ||
| 91 | + which = cmp > 0 ? 0 : 1; | ||
| 92 | + } else { | ||
| 93 | + which = is_qnan(b->cls) ? 1 : 0; | ||
| 94 | + } | ||
| 95 | + } else if (is_qnan(a->cls)) { | ||
| 96 | + if (is_snan(b->cls) || !is_qnan(b->cls)) { | ||
| 97 | + which = 0; | ||
| 98 | + } else { | ||
| 99 | + which = cmp > 0 ? 0 : 1; | ||
| 100 | + } | ||
| 101 | + } else { | ||
| 102 | + which = 1; | ||
| 103 | + } | ||
| 104 | + break; | ||
| 105 | + default: | ||
| 106 | + g_assert_not_reached(); | ||
| 107 | + } | ||
| 108 | + | ||
| 109 | + if (which) { | ||
| 110 | + a = b; | ||
| 111 | + } | ||
| 112 | + if (is_snan(a->cls)) { | ||
| 113 | + parts_silence_nan(a, s); | ||
| 114 | } | ||
| 115 | return a; | ||
| 116 | } | ||
| 117 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 33 | index XXXXXXX..XXXXXXX 100644 | 118 | index XXXXXXX..XXXXXXX 100644 |
| 34 | --- a/hw/timer/aspeed_timer.c | 119 | --- a/fpu/softfloat-specialize.c.inc |
| 35 | +++ b/hw/timer/aspeed_timer.c | 120 | +++ b/fpu/softfloat-specialize.c.inc |
| 36 | @@ -XXX,XX +XXX,XX @@ static void aspeed_2500_timer_write(AspeedTimerCtrlState *s, hwaddr offset, | 121 | @@ -XXX,XX +XXX,XX @@ bool float32_is_signaling_nan(float32 a_, float_status *status) |
| 37 | } | 122 | } |
| 38 | } | 123 | } |
| 39 | 124 | ||
| 40 | +static uint64_t aspeed_2600_timer_read(AspeedTimerCtrlState *s, hwaddr offset) | 125 | -/*---------------------------------------------------------------------------- |
| 41 | +{ | 126 | -| Select which NaN to propagate for a two-input operation. |
| 42 | + uint64_t value; | 127 | -| IEEE754 doesn't specify all the details of this, so the |
| 43 | + | 128 | -| algorithm is target-specific. |
| 44 | + switch (offset) { | 129 | -| The routine is passed various bits of information about the |
| 45 | + case 0x38: | 130 | -| two NaNs and should return 0 to select NaN a and 1 for NaN b. |
| 46 | + case 0x3C: | 131 | -| Note that signalling NaNs are always squashed to quiet NaNs |
| 47 | + default: | 132 | -| by the caller, by calling floatXX_silence_nan() before |
| 48 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | 133 | -| returning them. |
| 49 | + __func__, offset); | 134 | -| |
| 50 | + value = 0; | 135 | -| aIsLargerSignificand is only valid if both a and b are NaNs |
| 51 | + break; | 136 | -| of some kind, and is true if a has the larger significand, |
| 52 | + } | 137 | -| or if both a and b have the same significand but a is |
| 53 | + return value; | 138 | -| positive but b is negative. It is only needed for the x87 |
| 54 | +} | 139 | -| tie-break rule. |
| 55 | + | 140 | -*----------------------------------------------------------------------------*/ |
| 56 | +static void aspeed_2600_timer_write(AspeedTimerCtrlState *s, hwaddr offset, | 141 | - |
| 57 | + uint64_t value) | 142 | -static int pickNaN(FloatClass a_cls, FloatClass b_cls, |
| 58 | +{ | 143 | - bool aIsLargerSignificand, float_status *status) |
| 59 | + const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF); | 144 | -{ |
| 60 | + | 145 | - /* |
| 61 | + switch (offset) { | 146 | - * We guarantee not to require the target to tell us how to |
| 62 | + case 0x3C: | 147 | - * pick a NaN if we're always returning the default NaN. |
| 63 | + aspeed_timer_set_ctrl(s, s->ctrl & ~tv); | 148 | - * But if we're not in default-NaN mode then the target must |
| 64 | + break; | 149 | - * specify via set_float_2nan_prop_rule(). |
| 65 | + | 150 | - */ |
| 66 | + case 0x38: | 151 | - assert(!status->default_nan_mode); |
| 67 | + default: | 152 | - |
| 68 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | 153 | - switch (status->float_2nan_prop_rule) { |
| 69 | + __func__, offset); | 154 | - case float_2nan_prop_s_ab: |
| 70 | + break; | 155 | - if (is_snan(a_cls)) { |
| 71 | + } | 156 | - return 0; |
| 72 | +} | 157 | - } else if (is_snan(b_cls)) { |
| 73 | + | 158 | - return 1; |
| 74 | static void aspeed_init_one_timer(AspeedTimerCtrlState *s, uint8_t id) | 159 | - } else if (is_qnan(a_cls)) { |
| 75 | { | 160 | - return 0; |
| 76 | AspeedTimer *t = &s->timers[id]; | 161 | - } else { |
| 77 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_2500_timer_info = { | 162 | - return 1; |
| 78 | .class_init = aspeed_2500_timer_class_init, | 163 | - } |
| 79 | }; | 164 | - break; |
| 80 | 165 | - case float_2nan_prop_s_ba: | |
| 81 | +static void aspeed_2600_timer_class_init(ObjectClass *klass, void *data) | 166 | - if (is_snan(b_cls)) { |
| 82 | +{ | 167 | - return 1; |
| 83 | + DeviceClass *dc = DEVICE_CLASS(klass); | 168 | - } else if (is_snan(a_cls)) { |
| 84 | + AspeedTimerClass *awc = ASPEED_TIMER_CLASS(klass); | 169 | - return 0; |
| 85 | + | 170 | - } else if (is_qnan(b_cls)) { |
| 86 | + dc->desc = "ASPEED 2600 Timer"; | 171 | - return 1; |
| 87 | + awc->read = aspeed_2600_timer_read; | 172 | - } else { |
| 88 | + awc->write = aspeed_2600_timer_write; | 173 | - return 0; |
| 89 | +} | 174 | - } |
| 90 | + | 175 | - break; |
| 91 | +static const TypeInfo aspeed_2600_timer_info = { | 176 | - case float_2nan_prop_ab: |
| 92 | + .name = TYPE_ASPEED_2600_TIMER, | 177 | - if (is_nan(a_cls)) { |
| 93 | + .parent = TYPE_ASPEED_TIMER, | 178 | - return 0; |
| 94 | + .class_init = aspeed_2600_timer_class_init, | 179 | - } else { |
| 95 | +}; | 180 | - return 1; |
| 96 | + | 181 | - } |
| 97 | static void aspeed_timer_register_types(void) | 182 | - break; |
| 98 | { | 183 | - case float_2nan_prop_ba: |
| 99 | type_register_static(&aspeed_timer_info); | 184 | - if (is_nan(b_cls)) { |
| 100 | type_register_static(&aspeed_2400_timer_info); | 185 | - return 1; |
| 101 | type_register_static(&aspeed_2500_timer_info); | 186 | - } else { |
| 102 | + type_register_static(&aspeed_2600_timer_info); | 187 | - return 0; |
| 103 | } | 188 | - } |
| 104 | 189 | - break; | |
| 105 | type_init(aspeed_timer_register_types) | 190 | - case float_2nan_prop_x87: |
| 191 | - /* | ||
| 192 | - * This implements x87 NaN propagation rules: | ||
| 193 | - * SNaN + QNaN => return the QNaN | ||
| 194 | - * two SNaNs => return the one with the larger significand, silenced | ||
| 195 | - * two QNaNs => return the one with the larger significand | ||
| 196 | - * SNaN and a non-NaN => return the SNaN, silenced | ||
| 197 | - * QNaN and a non-NaN => return the QNaN | ||
| 198 | - * | ||
| 199 | - * If we get down to comparing significands and they are the same, | ||
| 200 | - * return the NaN with the positive sign bit (if any). | ||
| 201 | - */ | ||
| 202 | - if (is_snan(a_cls)) { | ||
| 203 | - if (is_snan(b_cls)) { | ||
| 204 | - return aIsLargerSignificand ? 0 : 1; | ||
| 205 | - } | ||
| 206 | - return is_qnan(b_cls) ? 1 : 0; | ||
| 207 | - } else if (is_qnan(a_cls)) { | ||
| 208 | - if (is_snan(b_cls) || !is_qnan(b_cls)) { | ||
| 209 | - return 0; | ||
| 210 | - } else { | ||
| 211 | - return aIsLargerSignificand ? 0 : 1; | ||
| 212 | - } | ||
| 213 | - } else { | ||
| 214 | - return 1; | ||
| 215 | - } | ||
| 216 | - default: | ||
| 217 | - g_assert_not_reached(); | ||
| 218 | - } | ||
| 219 | -} | ||
| 220 | - | ||
| 221 | /*---------------------------------------------------------------------------- | ||
| 222 | | Returns 1 if the double-precision floating-point value `a' is a quiet | ||
| 223 | | NaN; otherwise returns 0. | ||
| 106 | -- | 224 | -- |
| 107 | 2.20.1 | 225 | 2.34.1 |
| 108 | 226 | ||
| 109 | 227 | diff view generated by jsdifflib |
| 1 | From: Joel Stanley <joel@jms.id.au> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The SCU controller on the AST2600 SoC has extra registers. Increase | 3 | Remember if there was an SNaN, and use that to simplify |
| 4 | the number of regs of the model and introduce a new field in the class | 4 | float_2nan_prop_s_{ab,ba} to only the snan component. |
| 5 | to customize the MemoryRegion operations depending on the SoC model. | 5 | Then, fall through to the corresponding |
| 6 | float_2nan_prop_{ab,ba} case to handle any remaining | ||
| 7 | nans, which must be quiet. | ||
| 6 | 8 | ||
| 7 | Signed-off-by: Joel Stanley <joel@jms.id.au> | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 9 | Message-id: 20190925143248.10000-4-clg@kaod.org | 11 | Message-id: 20241203203949.483774-10-richard.henderson@linaro.org |
| 10 | [clg: - improved commit log | ||
| 11 | - changed vmstate version | ||
| 12 | - reworked model integration into new object class | ||
| 13 | - included AST2600_HPLL_PARAM value ] | ||
| 14 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 16 | --- | 13 | --- |
| 17 | include/hw/misc/aspeed_scu.h | 7 +- | 14 | fpu/softfloat-parts.c.inc | 32 ++++++++++++-------------------- |
| 18 | hw/misc/aspeed_scu.c | 192 +++++++++++++++++++++++++++++++++-- | 15 | 1 file changed, 12 insertions(+), 20 deletions(-) |
| 19 | 2 files changed, 191 insertions(+), 8 deletions(-) | ||
| 20 | 16 | ||
| 21 | diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h | 17 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
| 22 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
| 23 | --- a/include/hw/misc/aspeed_scu.h | 19 | --- a/fpu/softfloat-parts.c.inc |
| 24 | +++ b/include/hw/misc/aspeed_scu.h | 20 | +++ b/fpu/softfloat-parts.c.inc |
| 25 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s) |
| 26 | #define ASPEED_SCU(obj) OBJECT_CHECK(AspeedSCUState, (obj), TYPE_ASPEED_SCU) | 22 | static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
| 27 | #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400" | 23 | float_status *s) |
| 28 | #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500" | ||
| 29 | +#define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600" | ||
| 30 | |||
| 31 | #define ASPEED_SCU_NR_REGS (0x1A8 >> 2) | ||
| 32 | +#define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2) | ||
| 33 | |||
| 34 | typedef struct AspeedSCUState { | ||
| 35 | /*< private >*/ | ||
| 36 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSCUState { | ||
| 37 | /*< public >*/ | ||
| 38 | MemoryRegion iomem; | ||
| 39 | |||
| 40 | - uint32_t regs[ASPEED_SCU_NR_REGS]; | ||
| 41 | + uint32_t regs[ASPEED_AST2600_SCU_NR_REGS]; | ||
| 42 | uint32_t silicon_rev; | ||
| 43 | uint32_t hw_strap1; | ||
| 44 | uint32_t hw_strap2; | ||
| 45 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSCUState { | ||
| 46 | #define AST2400_A1_SILICON_REV 0x02010303U | ||
| 47 | #define AST2500_A0_SILICON_REV 0x04000303U | ||
| 48 | #define AST2500_A1_SILICON_REV 0x04010303U | ||
| 49 | +#define AST2600_A0_SILICON_REV 0x05000303U | ||
| 50 | |||
| 51 | #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) | ||
| 52 | |||
| 53 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSCUClass { | ||
| 54 | const uint32_t *resets; | ||
| 55 | uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg); | ||
| 56 | uint32_t apb_divider; | ||
| 57 | + uint32_t nr_regs; | ||
| 58 | + const MemoryRegionOps *ops; | ||
| 59 | } AspeedSCUClass; | ||
| 60 | |||
| 61 | #define ASPEED_SCU_PROT_KEY 0x1688A8A8 | ||
| 62 | diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c | ||
| 63 | index XXXXXXX..XXXXXXX 100644 | ||
| 64 | --- a/hw/misc/aspeed_scu.c | ||
| 65 | +++ b/hw/misc/aspeed_scu.c | ||
| 66 | @@ -XXX,XX +XXX,XX @@ | ||
| 67 | #define BMC_REV TO_REG(0x19C) | ||
| 68 | #define BMC_DEV_ID TO_REG(0x1A4) | ||
| 69 | |||
| 70 | +#define AST2600_PROT_KEY TO_REG(0x00) | ||
| 71 | +#define AST2600_SILICON_REV TO_REG(0x04) | ||
| 72 | +#define AST2600_SILICON_REV2 TO_REG(0x14) | ||
| 73 | +#define AST2600_SYS_RST_CTRL TO_REG(0x40) | ||
| 74 | +#define AST2600_SYS_RST_CTRL_CLR TO_REG(0x44) | ||
| 75 | +#define AST2600_SYS_RST_CTRL2 TO_REG(0x50) | ||
| 76 | +#define AST2600_SYS_RST_CTRL2_CLR TO_REG(0x54) | ||
| 77 | +#define AST2600_CLK_STOP_CTRL TO_REG(0x80) | ||
| 78 | +#define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84) | ||
| 79 | +#define AST2600_CLK_STOP_CTRL2 TO_REG(0x90) | ||
| 80 | +#define AST2600_CLK_STOP_CTR2L_CLR TO_REG(0x94) | ||
| 81 | +#define AST2600_HPLL_PARAM TO_REG(0x200) | ||
| 82 | +#define AST2600_HPLL_EXT TO_REG(0x204) | ||
| 83 | +#define AST2600_MPLL_EXT TO_REG(0x224) | ||
| 84 | +#define AST2600_EPLL_EXT TO_REG(0x244) | ||
| 85 | +#define AST2600_CLK_SEL TO_REG(0x300) | ||
| 86 | +#define AST2600_CLK_SEL2 TO_REG(0x304) | ||
| 87 | +#define AST2600_CLK_SEL3 TO_REG(0x310) | ||
| 88 | +#define AST2600_HW_STRAP1 TO_REG(0x500) | ||
| 89 | +#define AST2600_HW_STRAP1_CLR TO_REG(0x504) | ||
| 90 | +#define AST2600_HW_STRAP1_PROT TO_REG(0x508) | ||
| 91 | +#define AST2600_HW_STRAP2 TO_REG(0x510) | ||
| 92 | +#define AST2600_HW_STRAP2_CLR TO_REG(0x514) | ||
| 93 | +#define AST2600_HW_STRAP2_PROT TO_REG(0x518) | ||
| 94 | +#define AST2600_RNG_CTRL TO_REG(0x524) | ||
| 95 | +#define AST2600_RNG_DATA TO_REG(0x540) | ||
| 96 | + | ||
| 97 | +#define AST2600_CLK TO_REG(0x40) | ||
| 98 | + | ||
| 99 | #define SCU_IO_REGION_SIZE 0x1000 | ||
| 100 | |||
| 101 | static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = { | ||
| 102 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size) | ||
| 103 | AspeedSCUState *s = ASPEED_SCU(opaque); | ||
| 104 | int reg = TO_REG(offset); | ||
| 105 | |||
| 106 | - if (reg >= ARRAY_SIZE(s->regs)) { | ||
| 107 | + if (reg >= ASPEED_SCU_NR_REGS) { | ||
| 108 | qemu_log_mask(LOG_GUEST_ERROR, | ||
| 109 | "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", | ||
| 110 | __func__, offset); | ||
| 111 | @@ -XXX,XX +XXX,XX @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data, | ||
| 112 | AspeedSCUState *s = ASPEED_SCU(opaque); | ||
| 113 | int reg = TO_REG(offset); | ||
| 114 | |||
| 115 | - if (reg >= ARRAY_SIZE(s->regs)) { | ||
| 116 | + if (reg >= ASPEED_SCU_NR_REGS) { | ||
| 117 | qemu_log_mask(LOG_GUEST_ERROR, | ||
| 118 | "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", | ||
| 119 | __func__, offset); | ||
| 120 | @@ -XXX,XX +XXX,XX @@ static void aspeed_scu_reset(DeviceState *dev) | ||
| 121 | AspeedSCUState *s = ASPEED_SCU(dev); | ||
| 122 | AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); | ||
| 123 | |||
| 124 | - memcpy(s->regs, asc->resets, sizeof(s->regs)); | ||
| 125 | + memcpy(s->regs, asc->resets, asc->nr_regs * 4); | ||
| 126 | s->regs[SILICON_REV] = s->silicon_rev; | ||
| 127 | s->regs[HW_STRAP1] = s->hw_strap1; | ||
| 128 | s->regs[HW_STRAP2] = s->hw_strap2; | ||
| 129 | @@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_silicon_revs[] = { | ||
| 130 | AST2400_A1_SILICON_REV, | ||
| 131 | AST2500_A0_SILICON_REV, | ||
| 132 | AST2500_A1_SILICON_REV, | ||
| 133 | + AST2600_A0_SILICON_REV, | ||
| 134 | }; | ||
| 135 | |||
| 136 | bool is_supported_silicon_rev(uint32_t silicon_rev) | ||
| 137 | @@ -XXX,XX +XXX,XX @@ static void aspeed_scu_realize(DeviceState *dev, Error **errp) | ||
| 138 | { | 24 | { |
| 139 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | 25 | + bool have_snan = false; |
| 140 | AspeedSCUState *s = ASPEED_SCU(dev); | 26 | int cmp, which; |
| 141 | + AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); | 27 | |
| 142 | 28 | if (is_snan(a->cls) || is_snan(b->cls)) { | |
| 143 | if (!is_supported_silicon_rev(s->silicon_rev)) { | 29 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); |
| 144 | error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, | 30 | + have_snan = true; |
| 145 | @@ -XXX,XX +XXX,XX @@ static void aspeed_scu_realize(DeviceState *dev, Error **errp) | ||
| 146 | return; | ||
| 147 | } | 31 | } |
| 148 | 32 | ||
| 149 | - memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_scu_ops, s, | 33 | if (s->default_nan_mode) { |
| 150 | + memory_region_init_io(&s->iomem, OBJECT(s), asc->ops, s, | 34 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
| 151 | TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE); | 35 | |
| 152 | 36 | switch (s->float_2nan_prop_rule) { | |
| 153 | sysbus_init_mmio(sbd, &s->iomem); | 37 | case float_2nan_prop_s_ab: |
| 154 | @@ -XXX,XX +XXX,XX @@ static void aspeed_scu_realize(DeviceState *dev, Error **errp) | 38 | - if (is_snan(a->cls)) { |
| 155 | 39 | - which = 0; | |
| 156 | static const VMStateDescription vmstate_aspeed_scu = { | 40 | - } else if (is_snan(b->cls)) { |
| 157 | .name = "aspeed.scu", | 41 | - which = 1; |
| 158 | - .version_id = 1, | 42 | - } else if (is_qnan(a->cls)) { |
| 159 | - .minimum_version_id = 1, | 43 | - which = 0; |
| 160 | + .version_id = 2, | 44 | - } else { |
| 161 | + .minimum_version_id = 2, | 45 | - which = 1; |
| 162 | .fields = (VMStateField[]) { | 46 | + if (have_snan) { |
| 163 | - VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_SCU_NR_REGS), | 47 | + which = is_snan(a->cls) ? 0 : 1; |
| 164 | + VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_AST2600_SCU_NR_REGS), | 48 | + break; |
| 165 | VMSTATE_END_OF_LIST() | 49 | } |
| 166 | } | 50 | - break; |
| 167 | }; | 51 | - case float_2nan_prop_s_ba: |
| 168 | @@ -XXX,XX +XXX,XX @@ static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data) | 52 | - if (is_snan(b->cls)) { |
| 169 | asc->resets = ast2400_a0_resets; | 53 | - which = 1; |
| 170 | asc->calc_hpll = aspeed_2400_scu_calc_hpll; | 54 | - } else if (is_snan(a->cls)) { |
| 171 | asc->apb_divider = 2; | 55 | - which = 0; |
| 172 | + asc->nr_regs = ASPEED_SCU_NR_REGS; | 56 | - } else if (is_qnan(b->cls)) { |
| 173 | + asc->ops = &aspeed_scu_ops; | 57 | - which = 1; |
| 174 | } | 58 | - } else { |
| 175 | 59 | - which = 0; | |
| 176 | static const TypeInfo aspeed_2400_scu_info = { | 60 | - } |
| 177 | @@ -XXX,XX +XXX,XX @@ static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data) | 61 | - break; |
| 178 | asc->resets = ast2500_a1_resets; | 62 | + /* fall through */ |
| 179 | asc->calc_hpll = aspeed_2500_scu_calc_hpll; | 63 | case float_2nan_prop_ab: |
| 180 | asc->apb_divider = 4; | 64 | which = is_nan(a->cls) ? 0 : 1; |
| 181 | + asc->nr_regs = ASPEED_SCU_NR_REGS; | 65 | break; |
| 182 | + asc->ops = &aspeed_scu_ops; | 66 | + case float_2nan_prop_s_ba: |
| 183 | } | 67 | + if (have_snan) { |
| 184 | 68 | + which = is_snan(b->cls) ? 1 : 0; | |
| 185 | static const TypeInfo aspeed_2500_scu_info = { | 69 | + break; |
| 186 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_2500_scu_info = { | ||
| 187 | .class_init = aspeed_2500_scu_class_init, | ||
| 188 | }; | ||
| 189 | |||
| 190 | +static uint64_t aspeed_ast2600_scu_read(void *opaque, hwaddr offset, | ||
| 191 | + unsigned size) | ||
| 192 | +{ | ||
| 193 | + AspeedSCUState *s = ASPEED_SCU(opaque); | ||
| 194 | + int reg = TO_REG(offset); | ||
| 195 | + | ||
| 196 | + if (reg >= ASPEED_AST2600_SCU_NR_REGS) { | ||
| 197 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
| 198 | + "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", | ||
| 199 | + __func__, offset); | ||
| 200 | + return 0; | ||
| 201 | + } | ||
| 202 | + | ||
| 203 | + switch (reg) { | ||
| 204 | + case AST2600_HPLL_EXT: | ||
| 205 | + case AST2600_EPLL_EXT: | ||
| 206 | + case AST2600_MPLL_EXT: | ||
| 207 | + /* PLLs are always "locked" */ | ||
| 208 | + return s->regs[reg] | BIT(31); | ||
| 209 | + case AST2600_RNG_DATA: | ||
| 210 | + /* | ||
| 211 | + * On hardware, RNG_DATA works regardless of the state of the | ||
| 212 | + * enable bit in RNG_CTRL | ||
| 213 | + * | ||
| 214 | + * TODO: Check this is true for ast2600 | ||
| 215 | + */ | ||
| 216 | + s->regs[AST2600_RNG_DATA] = aspeed_scu_get_random(); | ||
| 217 | + break; | ||
| 218 | + } | ||
| 219 | + | ||
| 220 | + return s->regs[reg]; | ||
| 221 | +} | ||
| 222 | + | ||
| 223 | +static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, uint64_t data, | ||
| 224 | + unsigned size) | ||
| 225 | +{ | ||
| 226 | + AspeedSCUState *s = ASPEED_SCU(opaque); | ||
| 227 | + int reg = TO_REG(offset); | ||
| 228 | + | ||
| 229 | + if (reg >= ASPEED_AST2600_SCU_NR_REGS) { | ||
| 230 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
| 231 | + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", | ||
| 232 | + __func__, offset); | ||
| 233 | + return; | ||
| 234 | + } | ||
| 235 | + | ||
| 236 | + if (reg > PROT_KEY && !s->regs[PROT_KEY]) { | ||
| 237 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); | ||
| 238 | + } | ||
| 239 | + | ||
| 240 | + trace_aspeed_scu_write(offset, size, data); | ||
| 241 | + | ||
| 242 | + switch (reg) { | ||
| 243 | + case AST2600_PROT_KEY: | ||
| 244 | + s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0; | ||
| 245 | + return; | ||
| 246 | + case AST2600_HW_STRAP1: | ||
| 247 | + case AST2600_HW_STRAP2: | ||
| 248 | + if (s->regs[reg + 2]) { | ||
| 249 | + return; | ||
| 250 | + } | 70 | + } |
| 251 | + /* fall through */ | 71 | + /* fall through */ |
| 252 | + case AST2600_SYS_RST_CTRL: | 72 | case float_2nan_prop_ba: |
| 253 | + case AST2600_SYS_RST_CTRL2: | 73 | which = is_nan(b->cls) ? 1 : 0; |
| 254 | + /* W1S (Write 1 to set) registers */ | 74 | break; |
| 255 | + s->regs[reg] |= data; | ||
| 256 | + return; | ||
| 257 | + case AST2600_SYS_RST_CTRL_CLR: | ||
| 258 | + case AST2600_SYS_RST_CTRL2_CLR: | ||
| 259 | + case AST2600_HW_STRAP1_CLR: | ||
| 260 | + case AST2600_HW_STRAP2_CLR: | ||
| 261 | + /* W1C (Write 1 to clear) registers */ | ||
| 262 | + s->regs[reg] &= ~data; | ||
| 263 | + return; | ||
| 264 | + | ||
| 265 | + case AST2600_RNG_DATA: | ||
| 266 | + case AST2600_SILICON_REV: | ||
| 267 | + case AST2600_SILICON_REV2: | ||
| 268 | + /* Add read only registers here */ | ||
| 269 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
| 270 | + "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", | ||
| 271 | + __func__, offset); | ||
| 272 | + return; | ||
| 273 | + } | ||
| 274 | + | ||
| 275 | + s->regs[reg] = data; | ||
| 276 | +} | ||
| 277 | + | ||
| 278 | +static const MemoryRegionOps aspeed_ast2600_scu_ops = { | ||
| 279 | + .read = aspeed_ast2600_scu_read, | ||
| 280 | + .write = aspeed_ast2600_scu_write, | ||
| 281 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
| 282 | + .valid.min_access_size = 4, | ||
| 283 | + .valid.max_access_size = 4, | ||
| 284 | + .valid.unaligned = false, | ||
| 285 | +}; | ||
| 286 | + | ||
| 287 | +static const uint32_t ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = { | ||
| 288 | + [AST2600_SILICON_REV] = AST2600_SILICON_REV, | ||
| 289 | + [AST2600_SILICON_REV2] = AST2600_SILICON_REV, | ||
| 290 | + [AST2600_SYS_RST_CTRL] = 0xF7CFFEDC | 0x100, | ||
| 291 | + [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC, | ||
| 292 | + [AST2600_CLK_STOP_CTRL] = 0xEFF43E8B, | ||
| 293 | + [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0, | ||
| 294 | + [AST2600_HPLL_PARAM] = 0x1000405F, | ||
| 295 | +}; | ||
| 296 | + | ||
| 297 | +static void aspeed_ast2600_scu_reset(DeviceState *dev) | ||
| 298 | +{ | ||
| 299 | + AspeedSCUState *s = ASPEED_SCU(dev); | ||
| 300 | + AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); | ||
| 301 | + | ||
| 302 | + memcpy(s->regs, asc->resets, asc->nr_regs * 4); | ||
| 303 | + | ||
| 304 | + s->regs[AST2600_SILICON_REV] = s->silicon_rev; | ||
| 305 | + s->regs[AST2600_SILICON_REV2] = s->silicon_rev; | ||
| 306 | + s->regs[AST2600_HW_STRAP1] = s->hw_strap1; | ||
| 307 | + s->regs[AST2600_HW_STRAP2] = s->hw_strap2; | ||
| 308 | + s->regs[PROT_KEY] = s->hw_prot_key; | ||
| 309 | +} | ||
| 310 | + | ||
| 311 | +static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data) | ||
| 312 | +{ | ||
| 313 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 314 | + AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); | ||
| 315 | + | ||
| 316 | + dc->desc = "ASPEED 2600 System Control Unit"; | ||
| 317 | + dc->reset = aspeed_ast2600_scu_reset; | ||
| 318 | + asc->resets = ast2600_a0_resets; | ||
| 319 | + asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */ | ||
| 320 | + asc->apb_divider = 4; | ||
| 321 | + asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS; | ||
| 322 | + asc->ops = &aspeed_ast2600_scu_ops; | ||
| 323 | +} | ||
| 324 | + | ||
| 325 | +static const TypeInfo aspeed_2600_scu_info = { | ||
| 326 | + .name = TYPE_ASPEED_2600_SCU, | ||
| 327 | + .parent = TYPE_ASPEED_SCU, | ||
| 328 | + .instance_size = sizeof(AspeedSCUState), | ||
| 329 | + .class_init = aspeed_2600_scu_class_init, | ||
| 330 | +}; | ||
| 331 | + | ||
| 332 | static void aspeed_scu_register_types(void) | ||
| 333 | { | ||
| 334 | type_register_static(&aspeed_scu_info); | ||
| 335 | type_register_static(&aspeed_2400_scu_info); | ||
| 336 | type_register_static(&aspeed_2500_scu_info); | ||
| 337 | + type_register_static(&aspeed_2600_scu_info); | ||
| 338 | } | ||
| 339 | |||
| 340 | type_init(aspeed_scu_register_types); | ||
| 341 | -- | 75 | -- |
| 342 | 2.20.1 | 76 | 2.34.1 |
| 343 | |||
| 344 | diff view generated by jsdifflib |
| 1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The AST2600 timer replaces control register 2 with a interrupt status | 3 | Move the fractional comparison to the end of the |
| 4 | register. It is set by hardware when an IRQ occurs and cleared by | 4 | float_2nan_prop_x87 case. This is not required for |
| 5 | software. | 5 | any other 2nan propagation rule. Reorganize the |
| 6 | x87 case itself to break out of the switch when the | ||
| 7 | fractional comparison is not required. | ||
| 6 | 8 | ||
| 7 | Modify the vmstate version to take into account the new fields. | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | |
| 9 | Based on previous work from Joel Stanley. | 11 | Message-id: 20241203203949.483774-11-richard.henderson@linaro.org |
| 10 | |||
| 11 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
| 12 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
| 13 | Message-id: 20190925143248.10000-8-clg@kaod.org | ||
| 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 15 | --- | 13 | --- |
| 16 | include/hw/timer/aspeed_timer.h | 1 + | 14 | fpu/softfloat-parts.c.inc | 19 +++++++++---------- |
| 17 | hw/timer/aspeed_timer.c | 36 +++++++++++++++++++++++++-------- | 15 | 1 file changed, 9 insertions(+), 10 deletions(-) |
| 18 | 2 files changed, 29 insertions(+), 8 deletions(-) | ||
| 19 | 16 | ||
| 20 | diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h | 17 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
| 21 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
| 22 | --- a/include/hw/timer/aspeed_timer.h | 19 | --- a/fpu/softfloat-parts.c.inc |
| 23 | +++ b/include/hw/timer/aspeed_timer.h | 20 | +++ b/fpu/softfloat-parts.c.inc |
| 24 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedTimerCtrlState { | 21 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
| 25 | uint32_t ctrl; | 22 | return a; |
| 26 | uint32_t ctrl2; | ||
| 27 | uint32_t ctrl3; | ||
| 28 | + uint32_t irq_sts; | ||
| 29 | AspeedTimer timers[ASPEED_TIMER_NR_TIMERS]; | ||
| 30 | |||
| 31 | AspeedSCUState *scu; | ||
| 32 | diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c | ||
| 33 | index XXXXXXX..XXXXXXX 100644 | ||
| 34 | --- a/hw/timer/aspeed_timer.c | ||
| 35 | +++ b/hw/timer/aspeed_timer.c | ||
| 36 | @@ -XXX,XX +XXX,XX @@ static uint64_t calculate_next(struct AspeedTimer *t) | ||
| 37 | timer_del(&t->timer); | ||
| 38 | |||
| 39 | if (timer_overflow_interrupt(t)) { | ||
| 40 | + AspeedTimerCtrlState *s = timer_to_ctrl(t); | ||
| 41 | t->level = !t->level; | ||
| 42 | + s->irq_sts |= BIT(t->id); | ||
| 43 | qemu_set_irq(t->irq, t->level); | ||
| 44 | } | 23 | } |
| 45 | 24 | ||
| 46 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_expire(void *opaque) | 25 | - cmp = frac_cmp(a, b); |
| 47 | } | 26 | - if (cmp == 0) { |
| 48 | 27 | - cmp = a->sign < b->sign; | |
| 49 | if (interrupt) { | 28 | - } |
| 50 | + AspeedTimerCtrlState *s = timer_to_ctrl(t); | 29 | - |
| 51 | t->level = !t->level; | 30 | switch (s->float_2nan_prop_rule) { |
| 52 | + s->irq_sts |= BIT(t->id); | 31 | case float_2nan_prop_s_ab: |
| 53 | qemu_set_irq(t->irq, t->level); | 32 | if (have_snan) { |
| 54 | } | 33 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
| 55 | 34 | * return the NaN with the positive sign bit (if any). | |
| 56 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_timer_read(void *opaque, hwaddr offset, unsigned size) | 35 | */ |
| 57 | case 0x30: /* Control Register */ | 36 | if (is_snan(a->cls)) { |
| 58 | value = s->ctrl; | 37 | - if (is_snan(b->cls)) { |
| 38 | - which = cmp > 0 ? 0 : 1; | ||
| 39 | - } else { | ||
| 40 | + if (!is_snan(b->cls)) { | ||
| 41 | which = is_qnan(b->cls) ? 1 : 0; | ||
| 42 | + break; | ||
| 43 | } | ||
| 44 | } else if (is_qnan(a->cls)) { | ||
| 45 | if (is_snan(b->cls) || !is_qnan(b->cls)) { | ||
| 46 | which = 0; | ||
| 47 | - } else { | ||
| 48 | - which = cmp > 0 ? 0 : 1; | ||
| 49 | + break; | ||
| 50 | } | ||
| 51 | } else { | ||
| 52 | which = 1; | ||
| 53 | + break; | ||
| 54 | } | ||
| 55 | + cmp = frac_cmp(a, b); | ||
| 56 | + if (cmp == 0) { | ||
| 57 | + cmp = a->sign < b->sign; | ||
| 58 | + } | ||
| 59 | + which = cmp > 0 ? 0 : 1; | ||
| 59 | break; | 60 | break; |
| 60 | - case 0x34: /* Control Register 2 */ | ||
| 61 | - value = s->ctrl2; | ||
| 62 | - break; | ||
| 63 | case 0x00 ... 0x2c: /* Timers 1 - 4 */ | ||
| 64 | value = aspeed_timer_get_value(&s->timers[(offset >> 4)], reg); | ||
| 65 | break; | ||
| 66 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_write(void *opaque, hwaddr offset, uint64_t value, | ||
| 67 | case 0x30: | ||
| 68 | aspeed_timer_set_ctrl(s, tv); | ||
| 69 | break; | ||
| 70 | - case 0x34: | ||
| 71 | - aspeed_timer_set_ctrl2(s, tv); | ||
| 72 | - break; | ||
| 73 | /* Timer Registers */ | ||
| 74 | case 0x00 ... 0x2c: | ||
| 75 | aspeed_timer_set_value(s, (offset >> TIMER_NR_REGS), reg, tv); | ||
| 76 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_2400_timer_read(AspeedTimerCtrlState *s, hwaddr offset) | ||
| 77 | uint64_t value; | ||
| 78 | |||
| 79 | switch (offset) { | ||
| 80 | + case 0x34: | ||
| 81 | + value = s->ctrl2; | ||
| 82 | + break; | ||
| 83 | case 0x38: | ||
| 84 | case 0x3C: | ||
| 85 | default: | 61 | default: |
| 86 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_2400_timer_read(AspeedTimerCtrlState *s, hwaddr offset) | 62 | g_assert_not_reached(); |
| 87 | static void aspeed_2400_timer_write(AspeedTimerCtrlState *s, hwaddr offset, | ||
| 88 | uint64_t value) | ||
| 89 | { | ||
| 90 | + const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF); | ||
| 91 | + | ||
| 92 | switch (offset) { | ||
| 93 | + case 0x34: | ||
| 94 | + aspeed_timer_set_ctrl2(s, tv); | ||
| 95 | + break; | ||
| 96 | case 0x38: | ||
| 97 | case 0x3C: | ||
| 98 | default: | ||
| 99 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_2500_timer_read(AspeedTimerCtrlState *s, hwaddr offset) | ||
| 100 | uint64_t value; | ||
| 101 | |||
| 102 | switch (offset) { | ||
| 103 | + case 0x34: | ||
| 104 | + value = s->ctrl2; | ||
| 105 | + break; | ||
| 106 | case 0x38: | ||
| 107 | value = s->ctrl3 & BIT(0); | ||
| 108 | break; | ||
| 109 | @@ -XXX,XX +XXX,XX @@ static void aspeed_2500_timer_write(AspeedTimerCtrlState *s, hwaddr offset, | ||
| 110 | uint8_t command; | ||
| 111 | |||
| 112 | switch (offset) { | ||
| 113 | + case 0x34: | ||
| 114 | + aspeed_timer_set_ctrl2(s, tv); | ||
| 115 | + break; | ||
| 116 | case 0x38: | ||
| 117 | command = (value >> 1) & 0xFF; | ||
| 118 | if (command == 0xAE) { | ||
| 119 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_2600_timer_read(AspeedTimerCtrlState *s, hwaddr offset) | ||
| 120 | uint64_t value; | ||
| 121 | |||
| 122 | switch (offset) { | ||
| 123 | + case 0x34: | ||
| 124 | + value = s->irq_sts; | ||
| 125 | + break; | ||
| 126 | case 0x38: | ||
| 127 | case 0x3C: | ||
| 128 | default: | ||
| 129 | @@ -XXX,XX +XXX,XX @@ static void aspeed_2600_timer_write(AspeedTimerCtrlState *s, hwaddr offset, | ||
| 130 | const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF); | ||
| 131 | |||
| 132 | switch (offset) { | ||
| 133 | + case 0x34: | ||
| 134 | + s->irq_sts &= tv; | ||
| 135 | + break; | ||
| 136 | case 0x3C: | ||
| 137 | aspeed_timer_set_ctrl(s, s->ctrl & ~tv); | ||
| 138 | break; | ||
| 139 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_reset(DeviceState *dev) | ||
| 140 | s->ctrl = 0; | ||
| 141 | s->ctrl2 = 0; | ||
| 142 | s->ctrl3 = 0; | ||
| 143 | + s->irq_sts = 0; | ||
| 144 | } | ||
| 145 | |||
| 146 | static const VMStateDescription vmstate_aspeed_timer = { | ||
| 147 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_timer = { | ||
| 148 | |||
| 149 | static const VMStateDescription vmstate_aspeed_timer_state = { | ||
| 150 | .name = "aspeed.timerctrl", | ||
| 151 | - .version_id = 1, | ||
| 152 | - .minimum_version_id = 1, | ||
| 153 | + .version_id = 2, | ||
| 154 | + .minimum_version_id = 2, | ||
| 155 | .fields = (VMStateField[]) { | ||
| 156 | VMSTATE_UINT32(ctrl, AspeedTimerCtrlState), | ||
| 157 | VMSTATE_UINT32(ctrl2, AspeedTimerCtrlState), | ||
| 158 | VMSTATE_UINT32(ctrl3, AspeedTimerCtrlState), | ||
| 159 | + VMSTATE_UINT32(irq_sts, AspeedTimerCtrlState), | ||
| 160 | VMSTATE_STRUCT_ARRAY(timers, AspeedTimerCtrlState, | ||
| 161 | ASPEED_TIMER_NR_TIMERS, 1, vmstate_aspeed_timer, | ||
| 162 | AspeedTimer), | ||
| 163 | -- | 63 | -- |
| 164 | 2.20.1 | 64 | 2.34.1 |
| 165 | |||
| 166 | diff view generated by jsdifflib |
| 1 | From: Eric Auger <eric.auger@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Host kernel within [4.18, 5.3] report an erroneous KVM_MAX_VCPUS=512 | 3 | Replace the "index" selecting between A and B with a result variable |
| 4 | for ARM. The actual capability to instantiate more than 256 vcpus | 4 | of the proper type. This improves clarity within the function. |
| 5 | was fixed in 5.4 with the upgrade of the KVM_IRQ_LINE ABI to support | ||
| 6 | vcpu id encoded on 12 bits instead of 8 and a redistributor consuming | ||
| 7 | a single KVM IO device instead of 2. | ||
| 8 | 5 | ||
| 9 | So let's check this capability when attempting to use more than 256 | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 10 | vcpus within any ARM kvm accelerated machine. | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 11 | 8 | Message-id: 20241203203949.483774-12-richard.henderson@linaro.org | |
| 12 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
| 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 14 | Reviewed-by: Andrew Jones <drjones@redhat.com> | ||
| 15 | Acked-by: Marc Zyngier <maz@kernel.org> | ||
| 16 | Message-id: 20191003154640.22451-4-eric.auger@redhat.com | ||
| 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 18 | --- | 10 | --- |
| 19 | target/arm/kvm.c | 10 +++++++++- | 11 | fpu/softfloat-parts.c.inc | 28 +++++++++++++--------------- |
| 20 | 1 file changed, 9 insertions(+), 1 deletion(-) | 12 | 1 file changed, 13 insertions(+), 15 deletions(-) |
| 21 | 13 | ||
| 22 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c | 14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
| 23 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 24 | --- a/target/arm/kvm.c | 16 | --- a/fpu/softfloat-parts.c.inc |
| 25 | +++ b/target/arm/kvm.c | 17 | +++ b/fpu/softfloat-parts.c.inc |
| 26 | @@ -XXX,XX +XXX,XX @@ int kvm_arm_get_max_vm_ipa_size(MachineState *ms) | 18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
| 27 | 19 | float_status *s) | |
| 28 | int kvm_arch_init(MachineState *ms, KVMState *s) | ||
| 29 | { | 20 | { |
| 30 | + int ret = 0; | 21 | bool have_snan = false; |
| 31 | /* For ARM interrupt delivery is always asynchronous, | 22 | - int cmp, which; |
| 32 | * whether we are using an in-kernel VGIC or not. | 23 | + FloatPartsN *ret; |
| 33 | */ | 24 | + int cmp; |
| 34 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s) | 25 | |
| 35 | 26 | if (is_snan(a->cls) || is_snan(b->cls)) { | |
| 36 | cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); | 27 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); |
| 37 | 28 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, | |
| 38 | - return 0; | 29 | switch (s->float_2nan_prop_rule) { |
| 39 | + if (ms->smp.cpus > 256 && | 30 | case float_2nan_prop_s_ab: |
| 40 | + !kvm_check_extension(s, KVM_CAP_ARM_IRQ_LINE_LAYOUT_2)) { | 31 | if (have_snan) { |
| 41 | + error_report("Using more than 256 vcpus requires a host kernel " | 32 | - which = is_snan(a->cls) ? 0 : 1; |
| 42 | + "with KVM_CAP_ARM_IRQ_LINE_LAYOUT_2"); | 33 | + ret = is_snan(a->cls) ? a : b; |
| 43 | + ret = -EINVAL; | 34 | break; |
| 44 | + } | 35 | } |
| 45 | + | 36 | /* fall through */ |
| 37 | case float_2nan_prop_ab: | ||
| 38 | - which = is_nan(a->cls) ? 0 : 1; | ||
| 39 | + ret = is_nan(a->cls) ? a : b; | ||
| 40 | break; | ||
| 41 | case float_2nan_prop_s_ba: | ||
| 42 | if (have_snan) { | ||
| 43 | - which = is_snan(b->cls) ? 1 : 0; | ||
| 44 | + ret = is_snan(b->cls) ? b : a; | ||
| 45 | break; | ||
| 46 | } | ||
| 47 | /* fall through */ | ||
| 48 | case float_2nan_prop_ba: | ||
| 49 | - which = is_nan(b->cls) ? 1 : 0; | ||
| 50 | + ret = is_nan(b->cls) ? b : a; | ||
| 51 | break; | ||
| 52 | case float_2nan_prop_x87: | ||
| 53 | /* | ||
| 54 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, | ||
| 55 | */ | ||
| 56 | if (is_snan(a->cls)) { | ||
| 57 | if (!is_snan(b->cls)) { | ||
| 58 | - which = is_qnan(b->cls) ? 1 : 0; | ||
| 59 | + ret = is_qnan(b->cls) ? b : a; | ||
| 60 | break; | ||
| 61 | } | ||
| 62 | } else if (is_qnan(a->cls)) { | ||
| 63 | if (is_snan(b->cls) || !is_qnan(b->cls)) { | ||
| 64 | - which = 0; | ||
| 65 | + ret = a; | ||
| 66 | break; | ||
| 67 | } | ||
| 68 | } else { | ||
| 69 | - which = 1; | ||
| 70 | + ret = b; | ||
| 71 | break; | ||
| 72 | } | ||
| 73 | cmp = frac_cmp(a, b); | ||
| 74 | if (cmp == 0) { | ||
| 75 | cmp = a->sign < b->sign; | ||
| 76 | } | ||
| 77 | - which = cmp > 0 ? 0 : 1; | ||
| 78 | + ret = cmp > 0 ? a : b; | ||
| 79 | break; | ||
| 80 | default: | ||
| 81 | g_assert_not_reached(); | ||
| 82 | } | ||
| 83 | |||
| 84 | - if (which) { | ||
| 85 | - a = b; | ||
| 86 | + if (is_snan(ret->cls)) { | ||
| 87 | + parts_silence_nan(ret, s); | ||
| 88 | } | ||
| 89 | - if (is_snan(a->cls)) { | ||
| 90 | - parts_silence_nan(a, s); | ||
| 91 | - } | ||
| 92 | - return a; | ||
| 46 | + return ret; | 93 | + return ret; |
| 47 | } | 94 | } |
| 48 | 95 | ||
| 49 | unsigned long kvm_arch_vcpu_id(CPUState *cpu) | 96 | static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
| 50 | -- | 97 | -- |
| 51 | 2.20.1 | 98 | 2.34.1 |
| 52 | 99 | ||
| 53 | 100 | diff view generated by jsdifflib |
| 1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Leif Lindholm <quic_llindhol@quicinc.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The most important changes will be on the register range 0x34 - 0x3C | 3 | I'm migrating to Qualcomm's new open source email infrastructure, so |
| 4 | memops. Introduce class read/write operations to handle the | 4 | update my email address, and update the mailmap to match. |
| 5 | differences between SoCs. | ||
| 6 | 5 | ||
| 7 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 6 | Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com> |
| 8 | Reviewed-by: Joel Stanley <joel@jms.id.au> | 7 | Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> |
| 9 | Message-id: 20190925143248.10000-5-clg@kaod.org | 8 | Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> |
| 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 10 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 11 | Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | --- | 13 | --- |
| 12 | include/hw/timer/aspeed_timer.h | 15 +++++ | 14 | MAINTAINERS | 2 +- |
| 13 | hw/arm/aspeed_soc.c | 3 +- | 15 | .mailmap | 5 +++-- |
| 14 | hw/timer/aspeed_timer.c | 107 ++++++++++++++++++++++++++++---- | 16 | 2 files changed, 4 insertions(+), 3 deletions(-) |
| 15 | 3 files changed, 113 insertions(+), 12 deletions(-) | ||
| 16 | 17 | ||
| 17 | diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h | 18 | diff --git a/MAINTAINERS b/MAINTAINERS |
| 18 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
| 19 | --- a/include/hw/timer/aspeed_timer.h | 20 | --- a/MAINTAINERS |
| 20 | +++ b/include/hw/timer/aspeed_timer.h | 21 | +++ b/MAINTAINERS |
| 21 | @@ -XXX,XX +XXX,XX @@ | 22 | @@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h |
| 22 | #define ASPEED_TIMER(obj) \ | 23 | SBSA-REF |
| 23 | OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER); | 24 | M: Radoslaw Biernacki <rad@semihalf.com> |
| 24 | #define TYPE_ASPEED_TIMER "aspeed.timer" | 25 | M: Peter Maydell <peter.maydell@linaro.org> |
| 25 | +#define TYPE_ASPEED_2400_TIMER TYPE_ASPEED_TIMER "-ast2400" | 26 | -R: Leif Lindholm <quic_llindhol@quicinc.com> |
| 26 | +#define TYPE_ASPEED_2500_TIMER TYPE_ASPEED_TIMER "-ast2500" | 27 | +R: Leif Lindholm <leif.lindholm@oss.qualcomm.com> |
| 27 | + | 28 | R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
| 28 | #define ASPEED_TIMER_NR_TIMERS 8 | 29 | L: qemu-arm@nongnu.org |
| 29 | 30 | S: Maintained | |
| 30 | typedef struct AspeedTimer { | 31 | diff --git a/.mailmap b/.mailmap |
| 31 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedTimerCtrlState { | ||
| 32 | AspeedSCUState *scu; | ||
| 33 | } AspeedTimerCtrlState; | ||
| 34 | |||
| 35 | +#define ASPEED_TIMER_CLASS(klass) \ | ||
| 36 | + OBJECT_CLASS_CHECK(AspeedTimerClass, (klass), TYPE_ASPEED_TIMER) | ||
| 37 | +#define ASPEED_TIMER_GET_CLASS(obj) \ | ||
| 38 | + OBJECT_GET_CLASS(AspeedTimerClass, (obj), TYPE_ASPEED_TIMER) | ||
| 39 | + | ||
| 40 | +typedef struct AspeedTimerClass { | ||
| 41 | + SysBusDeviceClass parent_class; | ||
| 42 | + | ||
| 43 | + uint64_t (*read)(AspeedTimerCtrlState *s, hwaddr offset); | ||
| 44 | + void (*write)(AspeedTimerCtrlState *s, hwaddr offset, uint64_t value); | ||
| 45 | +} AspeedTimerClass; | ||
| 46 | + | ||
| 47 | #endif /* ASPEED_TIMER_H */ | ||
| 48 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
| 49 | index XXXXXXX..XXXXXXX 100644 | 32 | index XXXXXXX..XXXXXXX 100644 |
| 50 | --- a/hw/arm/aspeed_soc.c | 33 | --- a/.mailmap |
| 51 | +++ b/hw/arm/aspeed_soc.c | 34 | +++ b/.mailmap |
| 52 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | 35 | @@ -XXX,XX +XXX,XX @@ Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com> |
| 53 | sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc), | 36 | Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn> |
| 54 | TYPE_ASPEED_RTC); | 37 | James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com> |
| 55 | 38 | Juan Quintela <quintela@trasno.org> <quintela@redhat.com> | |
| 56 | + snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); | 39 | -Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org> |
| 57 | sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl), | 40 | -Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com> |
| 58 | - sizeof(s->timerctrl), TYPE_ASPEED_TIMER); | 41 | +Leif Lindholm <leif.lindholm@oss.qualcomm.com> <quic_llindhol@quicinc.com> |
| 59 | + sizeof(s->timerctrl), typename); | 42 | +Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif.lindholm@linaro.org> |
| 60 | object_property_add_const_link(OBJECT(&s->timerctrl), "scu", | 43 | +Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif@nuviainc.com> |
| 61 | OBJECT(&s->scu), &error_abort); | 44 | Luc Michel <luc@lmichel.fr> <luc.michel@git.antfield.fr> |
| 62 | 45 | Luc Michel <luc@lmichel.fr> <luc.michel@greensocs.com> | |
| 63 | diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c | 46 | Luc Michel <luc@lmichel.fr> <lmichel@kalray.eu> |
| 64 | index XXXXXXX..XXXXXXX 100644 | ||
| 65 | --- a/hw/timer/aspeed_timer.c | ||
| 66 | +++ b/hw/timer/aspeed_timer.c | ||
| 67 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_timer_read(void *opaque, hwaddr offset, unsigned size) | ||
| 68 | case 0x40 ... 0x8c: /* Timers 5 - 8 */ | ||
| 69 | value = aspeed_timer_get_value(&s->timers[(offset >> 4) - 1], reg); | ||
| 70 | break; | ||
| 71 | - /* Illegal */ | ||
| 72 | - case 0x38: | ||
| 73 | - case 0x3C: | ||
| 74 | default: | ||
| 75 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | ||
| 76 | - __func__, offset); | ||
| 77 | - value = 0; | ||
| 78 | + value = ASPEED_TIMER_GET_CLASS(s)->read(s, offset); | ||
| 79 | break; | ||
| 80 | } | ||
| 81 | trace_aspeed_timer_read(offset, size, value); | ||
| 82 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_write(void *opaque, hwaddr offset, uint64_t value, | ||
| 83 | case 0x40 ... 0x8c: | ||
| 84 | aspeed_timer_set_value(s, (offset >> TIMER_NR_REGS) - 1, reg, tv); | ||
| 85 | break; | ||
| 86 | - /* Illegal */ | ||
| 87 | - case 0x38: | ||
| 88 | - case 0x3C: | ||
| 89 | default: | ||
| 90 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | ||
| 91 | - __func__, offset); | ||
| 92 | + ASPEED_TIMER_GET_CLASS(s)->write(s, offset, value); | ||
| 93 | break; | ||
| 94 | } | ||
| 95 | } | ||
| 96 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_timer_ops = { | ||
| 97 | .valid.unaligned = false, | ||
| 98 | }; | ||
| 99 | |||
| 100 | +static uint64_t aspeed_2400_timer_read(AspeedTimerCtrlState *s, hwaddr offset) | ||
| 101 | +{ | ||
| 102 | + uint64_t value; | ||
| 103 | + | ||
| 104 | + switch (offset) { | ||
| 105 | + case 0x38: | ||
| 106 | + case 0x3C: | ||
| 107 | + default: | ||
| 108 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | ||
| 109 | + __func__, offset); | ||
| 110 | + value = 0; | ||
| 111 | + break; | ||
| 112 | + } | ||
| 113 | + return value; | ||
| 114 | +} | ||
| 115 | + | ||
| 116 | +static void aspeed_2400_timer_write(AspeedTimerCtrlState *s, hwaddr offset, | ||
| 117 | + uint64_t value) | ||
| 118 | +{ | ||
| 119 | + switch (offset) { | ||
| 120 | + case 0x38: | ||
| 121 | + case 0x3C: | ||
| 122 | + default: | ||
| 123 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | ||
| 124 | + __func__, offset); | ||
| 125 | + break; | ||
| 126 | + } | ||
| 127 | +} | ||
| 128 | + | ||
| 129 | +static uint64_t aspeed_2500_timer_read(AspeedTimerCtrlState *s, hwaddr offset) | ||
| 130 | +{ | ||
| 131 | + uint64_t value; | ||
| 132 | + | ||
| 133 | + switch (offset) { | ||
| 134 | + case 0x38: | ||
| 135 | + case 0x3C: | ||
| 136 | + default: | ||
| 137 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | ||
| 138 | + __func__, offset); | ||
| 139 | + value = 0; | ||
| 140 | + break; | ||
| 141 | + } | ||
| 142 | + return value; | ||
| 143 | +} | ||
| 144 | + | ||
| 145 | +static void aspeed_2500_timer_write(AspeedTimerCtrlState *s, hwaddr offset, | ||
| 146 | + uint64_t value) | ||
| 147 | +{ | ||
| 148 | + switch (offset) { | ||
| 149 | + case 0x38: | ||
| 150 | + case 0x3C: | ||
| 151 | + default: | ||
| 152 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | ||
| 153 | + __func__, offset); | ||
| 154 | + break; | ||
| 155 | + } | ||
| 156 | +} | ||
| 157 | + | ||
| 158 | static void aspeed_init_one_timer(AspeedTimerCtrlState *s, uint8_t id) | ||
| 159 | { | ||
| 160 | AspeedTimer *t = &s->timers[id]; | ||
| 161 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_timer_info = { | ||
| 162 | .parent = TYPE_SYS_BUS_DEVICE, | ||
| 163 | .instance_size = sizeof(AspeedTimerCtrlState), | ||
| 164 | .class_init = timer_class_init, | ||
| 165 | + .class_size = sizeof(AspeedTimerClass), | ||
| 166 | + .abstract = true, | ||
| 167 | +}; | ||
| 168 | + | ||
| 169 | +static void aspeed_2400_timer_class_init(ObjectClass *klass, void *data) | ||
| 170 | +{ | ||
| 171 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 172 | + AspeedTimerClass *awc = ASPEED_TIMER_CLASS(klass); | ||
| 173 | + | ||
| 174 | + dc->desc = "ASPEED 2400 Timer"; | ||
| 175 | + awc->read = aspeed_2400_timer_read; | ||
| 176 | + awc->write = aspeed_2400_timer_write; | ||
| 177 | +} | ||
| 178 | + | ||
| 179 | +static const TypeInfo aspeed_2400_timer_info = { | ||
| 180 | + .name = TYPE_ASPEED_2400_TIMER, | ||
| 181 | + .parent = TYPE_ASPEED_TIMER, | ||
| 182 | + .class_init = aspeed_2400_timer_class_init, | ||
| 183 | +}; | ||
| 184 | + | ||
| 185 | +static void aspeed_2500_timer_class_init(ObjectClass *klass, void *data) | ||
| 186 | +{ | ||
| 187 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 188 | + AspeedTimerClass *awc = ASPEED_TIMER_CLASS(klass); | ||
| 189 | + | ||
| 190 | + dc->desc = "ASPEED 2500 Timer"; | ||
| 191 | + awc->read = aspeed_2500_timer_read; | ||
| 192 | + awc->write = aspeed_2500_timer_write; | ||
| 193 | +} | ||
| 194 | + | ||
| 195 | +static const TypeInfo aspeed_2500_timer_info = { | ||
| 196 | + .name = TYPE_ASPEED_2500_TIMER, | ||
| 197 | + .parent = TYPE_ASPEED_TIMER, | ||
| 198 | + .class_init = aspeed_2500_timer_class_init, | ||
| 199 | }; | ||
| 200 | |||
| 201 | static void aspeed_timer_register_types(void) | ||
| 202 | { | ||
| 203 | type_register_static(&aspeed_timer_info); | ||
| 204 | + type_register_static(&aspeed_2400_timer_info); | ||
| 205 | + type_register_static(&aspeed_2500_timer_info); | ||
| 206 | } | ||
| 207 | |||
| 208 | type_init(aspeed_timer_register_types) | ||
| 209 | -- | 47 | -- |
| 210 | 2.20.1 | 48 | 2.34.1 |
| 211 | 49 | ||
| 212 | 50 | diff view generated by jsdifflib |
| 1 | From: Eric Auger <eric.auger@redhat.com> | 1 | From: Vikram Garhwal <vikram.garhwal@bytedance.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Update the headers against commit: | 3 | Previously, maintainer role was paused due to inactive email id. Commit id: |
| 4 | 0f1a7b3fac05 ("timer-of: don't use conditional expression | 4 | c009d715721861984c4987bcc78b7ee183e86d75. |
| 5 | with mixed 'void' types") | ||
| 6 | 5 | ||
| 7 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 6 | Signed-off-by: Vikram Garhwal <vikram.garhwal@bytedance.com> |
| 8 | Acked-by: Marc Zyngier <maz@kernel.org> | 7 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> |
| 9 | Message-id: 20191003154640.22451-2-eric.auger@redhat.com | 8 | Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com |
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | --- | 10 | --- |
| 12 | include/standard-headers/asm-x86/bootparam.h | 2 + | 11 | MAINTAINERS | 2 ++ |
| 13 | include/standard-headers/asm-x86/kvm_para.h | 1 + | 12 | 1 file changed, 2 insertions(+) |
| 14 | include/standard-headers/linux/ethtool.h | 24 +++ | ||
| 15 | include/standard-headers/linux/pci_regs.h | 19 +- | ||
| 16 | include/standard-headers/linux/virtio_fs.h | 19 ++ | ||
| 17 | include/standard-headers/linux/virtio_ids.h | 2 + | ||
| 18 | include/standard-headers/linux/virtio_iommu.h | 165 ++++++++++++++++++ | ||
| 19 | include/standard-headers/linux/virtio_pmem.h | 6 +- | ||
| 20 | linux-headers/asm-arm/kvm.h | 16 +- | ||
| 21 | linux-headers/asm-arm/unistd-common.h | 2 + | ||
| 22 | linux-headers/asm-arm64/kvm.h | 21 ++- | ||
| 23 | linux-headers/asm-generic/mman-common.h | 18 +- | ||
| 24 | linux-headers/asm-generic/mman.h | 10 +- | ||
| 25 | linux-headers/asm-generic/unistd.h | 10 +- | ||
| 26 | linux-headers/asm-mips/mman.h | 3 + | ||
| 27 | linux-headers/asm-mips/unistd_n32.h | 1 + | ||
| 28 | linux-headers/asm-mips/unistd_n64.h | 1 + | ||
| 29 | linux-headers/asm-mips/unistd_o32.h | 1 + | ||
| 30 | linux-headers/asm-powerpc/mman.h | 6 +- | ||
| 31 | linux-headers/asm-powerpc/unistd_32.h | 2 + | ||
| 32 | linux-headers/asm-powerpc/unistd_64.h | 2 + | ||
| 33 | linux-headers/asm-s390/kvm.h | 6 + | ||
| 34 | linux-headers/asm-s390/unistd_32.h | 2 + | ||
| 35 | linux-headers/asm-s390/unistd_64.h | 2 + | ||
| 36 | linux-headers/asm-x86/kvm.h | 28 ++- | ||
| 37 | linux-headers/asm-x86/unistd.h | 2 +- | ||
| 38 | linux-headers/asm-x86/unistd_32.h | 2 + | ||
| 39 | linux-headers/asm-x86/unistd_64.h | 2 + | ||
| 40 | linux-headers/asm-x86/unistd_x32.h | 2 + | ||
| 41 | linux-headers/linux/kvm.h | 12 +- | ||
| 42 | linux-headers/linux/psp-sev.h | 5 +- | ||
| 43 | linux-headers/linux/vfio.h | 71 +++++--- | ||
| 44 | 32 files changed, 406 insertions(+), 59 deletions(-) | ||
| 45 | create mode 100644 include/standard-headers/linux/virtio_fs.h | ||
| 46 | create mode 100644 include/standard-headers/linux/virtio_iommu.h | ||
| 47 | 13 | ||
| 48 | diff --git a/include/standard-headers/asm-x86/bootparam.h b/include/standard-headers/asm-x86/bootparam.h | 14 | diff --git a/MAINTAINERS b/MAINTAINERS |
| 49 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 50 | --- a/include/standard-headers/asm-x86/bootparam.h | 16 | --- a/MAINTAINERS |
| 51 | +++ b/include/standard-headers/asm-x86/bootparam.h | 17 | +++ b/MAINTAINERS |
| 52 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ F: tests/qtest/fuzz-sb16-test.c |
| 53 | #define XLF_EFI_HANDOVER_32 (1<<2) | 19 | |
| 54 | #define XLF_EFI_HANDOVER_64 (1<<3) | 20 | Xilinx CAN |
| 55 | #define XLF_EFI_KEXEC (1<<4) | 21 | M: Francisco Iglesias <francisco.iglesias@amd.com> |
| 56 | +#define XLF_5LEVEL (1<<5) | 22 | +M: Vikram Garhwal <vikram.garhwal@bytedance.com> |
| 57 | +#define XLF_5LEVEL_ENABLED (1<<6) | 23 | S: Maintained |
| 58 | 24 | F: hw/net/can/xlnx-* | |
| 59 | 25 | F: include/hw/net/xlnx-* | |
| 60 | #endif /* _ASM_X86_BOOTPARAM_H */ | 26 | @@ -XXX,XX +XXX,XX @@ F: include/hw/rx/ |
| 61 | diff --git a/include/standard-headers/asm-x86/kvm_para.h b/include/standard-headers/asm-x86/kvm_para.h | 27 | CAN bus subsystem and hardware |
| 62 | index XXXXXXX..XXXXXXX 100644 | 28 | M: Pavel Pisa <pisa@cmp.felk.cvut.cz> |
| 63 | --- a/include/standard-headers/asm-x86/kvm_para.h | 29 | M: Francisco Iglesias <francisco.iglesias@amd.com> |
| 64 | +++ b/include/standard-headers/asm-x86/kvm_para.h | 30 | +M: Vikram Garhwal <vikram.garhwal@bytedance.com> |
| 65 | @@ -XXX,XX +XXX,XX @@ | 31 | S: Maintained |
| 66 | #define KVM_FEATURE_ASYNC_PF_VMEXIT 10 | 32 | W: https://canbus.pages.fel.cvut.cz/ |
| 67 | #define KVM_FEATURE_PV_SEND_IPI 11 | 33 | F: net/can/* |
| 68 | #define KVM_FEATURE_POLL_CONTROL 12 | ||
| 69 | +#define KVM_FEATURE_PV_SCHED_YIELD 13 | ||
| 70 | |||
| 71 | #define KVM_HINTS_REALTIME 0 | ||
| 72 | |||
| 73 | diff --git a/include/standard-headers/linux/ethtool.h b/include/standard-headers/linux/ethtool.h | ||
| 74 | index XXXXXXX..XXXXXXX 100644 | ||
| 75 | --- a/include/standard-headers/linux/ethtool.h | ||
| 76 | +++ b/include/standard-headers/linux/ethtool.h | ||
| 77 | @@ -XXX,XX +XXX,XX @@ struct ethtool_tunable { | ||
| 78 | #define ETHTOOL_PHY_FAST_LINK_DOWN_ON 0 | ||
| 79 | #define ETHTOOL_PHY_FAST_LINK_DOWN_OFF 0xff | ||
| 80 | |||
| 81 | +/* Energy Detect Power Down (EDPD) is a feature supported by some PHYs, where | ||
| 82 | + * the PHY's RX & TX blocks are put into a low-power mode when there is no | ||
| 83 | + * link detected (typically cable is un-plugged). For RX, only a minimal | ||
| 84 | + * link-detection is available, and for TX the PHY wakes up to send link pulses | ||
| 85 | + * to avoid any lock-ups in case the peer PHY may also be running in EDPD mode. | ||
| 86 | + * | ||
| 87 | + * Some PHYs may support configuration of the wake-up interval for TX pulses, | ||
| 88 | + * and some PHYs may support only disabling TX pulses entirely. For the latter | ||
| 89 | + * a special value is required (ETHTOOL_PHY_EDPD_NO_TX) so that this can be | ||
| 90 | + * configured from userspace (should the user want it). | ||
| 91 | + * | ||
| 92 | + * The interval units for TX wake-up are in milliseconds, since this should | ||
| 93 | + * cover a reasonable range of intervals: | ||
| 94 | + * - from 1 millisecond, which does not sound like much of a power-saver | ||
| 95 | + * - to ~65 seconds which is quite a lot to wait for a link to come up when | ||
| 96 | + * plugging a cable | ||
| 97 | + */ | ||
| 98 | +#define ETHTOOL_PHY_EDPD_DFLT_TX_MSECS 0xffff | ||
| 99 | +#define ETHTOOL_PHY_EDPD_NO_TX 0xfffe | ||
| 100 | +#define ETHTOOL_PHY_EDPD_DISABLE 0 | ||
| 101 | + | ||
| 102 | enum phy_tunable_id { | ||
| 103 | ETHTOOL_PHY_ID_UNSPEC, | ||
| 104 | ETHTOOL_PHY_DOWNSHIFT, | ||
| 105 | ETHTOOL_PHY_FAST_LINK_DOWN, | ||
| 106 | + ETHTOOL_PHY_EDPD, | ||
| 107 | /* | ||
| 108 | * Add your fresh new phy tunable attribute above and remember to update | ||
| 109 | * phy_tunable_strings[] in net/core/ethtool.c | ||
| 110 | @@ -XXX,XX +XXX,XX @@ enum ethtool_link_mode_bit_indices { | ||
| 111 | ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT = 64, | ||
| 112 | ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT = 65, | ||
| 113 | ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66, | ||
| 114 | + ETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67, | ||
| 115 | + ETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68, | ||
| 116 | |||
| 117 | /* must be last entry */ | ||
| 118 | __ETHTOOL_LINK_MODE_MASK_NBITS | ||
| 119 | diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h | ||
| 120 | index XXXXXXX..XXXXXXX 100644 | ||
| 121 | --- a/include/standard-headers/linux/pci_regs.h | ||
| 122 | +++ b/include/standard-headers/linux/pci_regs.h | ||
| 123 | @@ -XXX,XX +XXX,XX @@ | ||
| 124 | #define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */ | ||
| 125 | #define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */ | ||
| 126 | #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */ | ||
| 127 | +#define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */ | ||
| 128 | #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ | ||
| 129 | #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ | ||
| 130 | #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ | ||
| 131 | @@ -XXX,XX +XXX,XX @@ | ||
| 132 | #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ | ||
| 133 | #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ | ||
| 134 | #define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */ | ||
| 135 | +#define PCI_EXP_LNKSTA_CLS_32_0GB 0x0005 /* Current Link Speed 32.0GT/s */ | ||
| 136 | #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ | ||
| 137 | #define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */ | ||
| 138 | #define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */ | ||
| 139 | @@ -XXX,XX +XXX,XX @@ | ||
| 140 | #define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */ | ||
| 141 | #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */ | ||
| 142 | #define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */ | ||
| 143 | +#define PCI_EXP_SLTCTL_ATTN_IND_SHIFT 6 /* Attention Indicator shift */ | ||
| 144 | #define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 /* Attention Indicator on */ | ||
| 145 | #define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */ | ||
| 146 | #define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 /* Attention Indicator off */ | ||
| 147 | @@ -XXX,XX +XXX,XX @@ | ||
| 148 | #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */ | ||
| 149 | #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */ | ||
| 150 | #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ | ||
| 151 | +#define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020 /* Supported Speed 32GT/s */ | ||
| 152 | #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ | ||
| 153 | #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ | ||
| 154 | #define PCI_EXP_LNKCTL2_TLS 0x000f | ||
| 155 | @@ -XXX,XX +XXX,XX @@ | ||
| 156 | #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ | ||
| 157 | #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ | ||
| 158 | #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ | ||
| 159 | +#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ | ||
| 160 | #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ | ||
| 161 | #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ | ||
| 162 | #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ | ||
| 163 | @@ -XXX,XX +XXX,XX @@ | ||
| 164 | #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ | ||
| 165 | #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ | ||
| 166 | #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ | ||
| 167 | -#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM | ||
| 168 | +#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ | ||
| 169 | +#define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ | ||
| 170 | +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT | ||
| 171 | |||
| 172 | #define PCI_EXT_CAP_DSN_SIZEOF 12 | ||
| 173 | #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 | ||
| 174 | @@ -XXX,XX +XXX,XX @@ | ||
| 175 | #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ | ||
| 176 | #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ | ||
| 177 | |||
| 178 | +/* Data Link Feature */ | ||
| 179 | +#define PCI_DLF_CAP 0x04 /* Capabilities Register */ | ||
| 180 | +#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ | ||
| 181 | + | ||
| 182 | +/* Physical Layer 16.0 GT/s */ | ||
| 183 | +#define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ | ||
| 184 | +#define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F | ||
| 185 | +#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 | ||
| 186 | +#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 | ||
| 187 | + | ||
| 188 | #endif /* LINUX_PCI_REGS_H */ | ||
| 189 | diff --git a/include/standard-headers/linux/virtio_fs.h b/include/standard-headers/linux/virtio_fs.h | ||
| 190 | new file mode 100644 | ||
| 191 | index XXXXXXX..XXXXXXX | ||
| 192 | --- /dev/null | ||
| 193 | +++ b/include/standard-headers/linux/virtio_fs.h | ||
| 194 | @@ -XXX,XX +XXX,XX @@ | ||
| 195 | +/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */ | ||
| 196 | + | ||
| 197 | +#ifndef _LINUX_VIRTIO_FS_H | ||
| 198 | +#define _LINUX_VIRTIO_FS_H | ||
| 199 | + | ||
| 200 | +#include "standard-headers/linux/types.h" | ||
| 201 | +#include "standard-headers/linux/virtio_ids.h" | ||
| 202 | +#include "standard-headers/linux/virtio_config.h" | ||
| 203 | +#include "standard-headers/linux/virtio_types.h" | ||
| 204 | + | ||
| 205 | +struct virtio_fs_config { | ||
| 206 | + /* Filesystem name (UTF-8, not NUL-terminated, padded with NULs) */ | ||
| 207 | + uint8_t tag[36]; | ||
| 208 | + | ||
| 209 | + /* Number of request queues */ | ||
| 210 | + uint32_t num_request_queues; | ||
| 211 | +} QEMU_PACKED; | ||
| 212 | + | ||
| 213 | +#endif /* _LINUX_VIRTIO_FS_H */ | ||
| 214 | diff --git a/include/standard-headers/linux/virtio_ids.h b/include/standard-headers/linux/virtio_ids.h | ||
| 215 | index XXXXXXX..XXXXXXX 100644 | ||
| 216 | --- a/include/standard-headers/linux/virtio_ids.h | ||
| 217 | +++ b/include/standard-headers/linux/virtio_ids.h | ||
| 218 | @@ -XXX,XX +XXX,XX @@ | ||
| 219 | #define VIRTIO_ID_INPUT 18 /* virtio input */ | ||
| 220 | #define VIRTIO_ID_VSOCK 19 /* virtio vsock transport */ | ||
| 221 | #define VIRTIO_ID_CRYPTO 20 /* virtio crypto */ | ||
| 222 | +#define VIRTIO_ID_IOMMU 23 /* virtio IOMMU */ | ||
| 223 | +#define VIRTIO_ID_FS 26 /* virtio filesystem */ | ||
| 224 | #define VIRTIO_ID_PMEM 27 /* virtio pmem */ | ||
| 225 | |||
| 226 | #endif /* _LINUX_VIRTIO_IDS_H */ | ||
| 227 | diff --git a/include/standard-headers/linux/virtio_iommu.h b/include/standard-headers/linux/virtio_iommu.h | ||
| 228 | new file mode 100644 | ||
| 229 | index XXXXXXX..XXXXXXX | ||
| 230 | --- /dev/null | ||
| 231 | +++ b/include/standard-headers/linux/virtio_iommu.h | ||
| 232 | @@ -XXX,XX +XXX,XX @@ | ||
| 233 | +/* SPDX-License-Identifier: BSD-3-Clause */ | ||
| 234 | +/* | ||
| 235 | + * Virtio-iommu definition v0.12 | ||
| 236 | + * | ||
| 237 | + * Copyright (C) 2019 Arm Ltd. | ||
| 238 | + */ | ||
| 239 | +#ifndef _LINUX_VIRTIO_IOMMU_H | ||
| 240 | +#define _LINUX_VIRTIO_IOMMU_H | ||
| 241 | + | ||
| 242 | +#include "standard-headers/linux/types.h" | ||
| 243 | + | ||
| 244 | +/* Feature bits */ | ||
| 245 | +#define VIRTIO_IOMMU_F_INPUT_RANGE 0 | ||
| 246 | +#define VIRTIO_IOMMU_F_DOMAIN_RANGE 1 | ||
| 247 | +#define VIRTIO_IOMMU_F_MAP_UNMAP 2 | ||
| 248 | +#define VIRTIO_IOMMU_F_BYPASS 3 | ||
| 249 | +#define VIRTIO_IOMMU_F_PROBE 4 | ||
| 250 | +#define VIRTIO_IOMMU_F_MMIO 5 | ||
| 251 | + | ||
| 252 | +struct virtio_iommu_range_64 { | ||
| 253 | + uint64_t start; | ||
| 254 | + uint64_t end; | ||
| 255 | +}; | ||
| 256 | + | ||
| 257 | +struct virtio_iommu_range_32 { | ||
| 258 | + uint32_t start; | ||
| 259 | + uint32_t end; | ||
| 260 | +}; | ||
| 261 | + | ||
| 262 | +struct virtio_iommu_config { | ||
| 263 | + /* Supported page sizes */ | ||
| 264 | + uint64_t page_size_mask; | ||
| 265 | + /* Supported IOVA range */ | ||
| 266 | + struct virtio_iommu_range_64 input_range; | ||
| 267 | + /* Max domain ID size */ | ||
| 268 | + struct virtio_iommu_range_32 domain_range; | ||
| 269 | + /* Probe buffer size */ | ||
| 270 | + uint32_t probe_size; | ||
| 271 | +}; | ||
| 272 | + | ||
| 273 | +/* Request types */ | ||
| 274 | +#define VIRTIO_IOMMU_T_ATTACH 0x01 | ||
| 275 | +#define VIRTIO_IOMMU_T_DETACH 0x02 | ||
| 276 | +#define VIRTIO_IOMMU_T_MAP 0x03 | ||
| 277 | +#define VIRTIO_IOMMU_T_UNMAP 0x04 | ||
| 278 | +#define VIRTIO_IOMMU_T_PROBE 0x05 | ||
| 279 | + | ||
| 280 | +/* Status types */ | ||
| 281 | +#define VIRTIO_IOMMU_S_OK 0x00 | ||
| 282 | +#define VIRTIO_IOMMU_S_IOERR 0x01 | ||
| 283 | +#define VIRTIO_IOMMU_S_UNSUPP 0x02 | ||
| 284 | +#define VIRTIO_IOMMU_S_DEVERR 0x03 | ||
| 285 | +#define VIRTIO_IOMMU_S_INVAL 0x04 | ||
| 286 | +#define VIRTIO_IOMMU_S_RANGE 0x05 | ||
| 287 | +#define VIRTIO_IOMMU_S_NOENT 0x06 | ||
| 288 | +#define VIRTIO_IOMMU_S_FAULT 0x07 | ||
| 289 | +#define VIRTIO_IOMMU_S_NOMEM 0x08 | ||
| 290 | + | ||
| 291 | +struct virtio_iommu_req_head { | ||
| 292 | + uint8_t type; | ||
| 293 | + uint8_t reserved[3]; | ||
| 294 | +}; | ||
| 295 | + | ||
| 296 | +struct virtio_iommu_req_tail { | ||
| 297 | + uint8_t status; | ||
| 298 | + uint8_t reserved[3]; | ||
| 299 | +}; | ||
| 300 | + | ||
| 301 | +struct virtio_iommu_req_attach { | ||
| 302 | + struct virtio_iommu_req_head head; | ||
| 303 | + uint32_t domain; | ||
| 304 | + uint32_t endpoint; | ||
| 305 | + uint8_t reserved[8]; | ||
| 306 | + struct virtio_iommu_req_tail tail; | ||
| 307 | +}; | ||
| 308 | + | ||
| 309 | +struct virtio_iommu_req_detach { | ||
| 310 | + struct virtio_iommu_req_head head; | ||
| 311 | + uint32_t domain; | ||
| 312 | + uint32_t endpoint; | ||
| 313 | + uint8_t reserved[8]; | ||
| 314 | + struct virtio_iommu_req_tail tail; | ||
| 315 | +}; | ||
| 316 | + | ||
| 317 | +#define VIRTIO_IOMMU_MAP_F_READ (1 << 0) | ||
| 318 | +#define VIRTIO_IOMMU_MAP_F_WRITE (1 << 1) | ||
| 319 | +#define VIRTIO_IOMMU_MAP_F_MMIO (1 << 2) | ||
| 320 | + | ||
| 321 | +#define VIRTIO_IOMMU_MAP_F_MASK (VIRTIO_IOMMU_MAP_F_READ | \ | ||
| 322 | + VIRTIO_IOMMU_MAP_F_WRITE | \ | ||
| 323 | + VIRTIO_IOMMU_MAP_F_MMIO) | ||
| 324 | + | ||
| 325 | +struct virtio_iommu_req_map { | ||
| 326 | + struct virtio_iommu_req_head head; | ||
| 327 | + uint32_t domain; | ||
| 328 | + uint64_t virt_start; | ||
| 329 | + uint64_t virt_end; | ||
| 330 | + uint64_t phys_start; | ||
| 331 | + uint32_t flags; | ||
| 332 | + struct virtio_iommu_req_tail tail; | ||
| 333 | +}; | ||
| 334 | + | ||
| 335 | +struct virtio_iommu_req_unmap { | ||
| 336 | + struct virtio_iommu_req_head head; | ||
| 337 | + uint32_t domain; | ||
| 338 | + uint64_t virt_start; | ||
| 339 | + uint64_t virt_end; | ||
| 340 | + uint8_t reserved[4]; | ||
| 341 | + struct virtio_iommu_req_tail tail; | ||
| 342 | +}; | ||
| 343 | + | ||
| 344 | +#define VIRTIO_IOMMU_PROBE_T_NONE 0 | ||
| 345 | +#define VIRTIO_IOMMU_PROBE_T_RESV_MEM 1 | ||
| 346 | + | ||
| 347 | +#define VIRTIO_IOMMU_PROBE_T_MASK 0xfff | ||
| 348 | + | ||
| 349 | +struct virtio_iommu_probe_property { | ||
| 350 | + uint16_t type; | ||
| 351 | + uint16_t length; | ||
| 352 | +}; | ||
| 353 | + | ||
| 354 | +#define VIRTIO_IOMMU_RESV_MEM_T_RESERVED 0 | ||
| 355 | +#define VIRTIO_IOMMU_RESV_MEM_T_MSI 1 | ||
| 356 | + | ||
| 357 | +struct virtio_iommu_probe_resv_mem { | ||
| 358 | + struct virtio_iommu_probe_property head; | ||
| 359 | + uint8_t subtype; | ||
| 360 | + uint8_t reserved[3]; | ||
| 361 | + uint64_t start; | ||
| 362 | + uint64_t end; | ||
| 363 | +}; | ||
| 364 | + | ||
| 365 | +struct virtio_iommu_req_probe { | ||
| 366 | + struct virtio_iommu_req_head head; | ||
| 367 | + uint32_t endpoint; | ||
| 368 | + uint8_t reserved[64]; | ||
| 369 | + | ||
| 370 | + uint8_t properties[]; | ||
| 371 | + | ||
| 372 | + /* | ||
| 373 | + * Tail follows the variable-length properties array. No padding, | ||
| 374 | + * property lengths are all aligned on 8 bytes. | ||
| 375 | + */ | ||
| 376 | +}; | ||
| 377 | + | ||
| 378 | +/* Fault types */ | ||
| 379 | +#define VIRTIO_IOMMU_FAULT_R_UNKNOWN 0 | ||
| 380 | +#define VIRTIO_IOMMU_FAULT_R_DOMAIN 1 | ||
| 381 | +#define VIRTIO_IOMMU_FAULT_R_MAPPING 2 | ||
| 382 | + | ||
| 383 | +#define VIRTIO_IOMMU_FAULT_F_READ (1 << 0) | ||
| 384 | +#define VIRTIO_IOMMU_FAULT_F_WRITE (1 << 1) | ||
| 385 | +#define VIRTIO_IOMMU_FAULT_F_EXEC (1 << 2) | ||
| 386 | +#define VIRTIO_IOMMU_FAULT_F_ADDRESS (1 << 8) | ||
| 387 | + | ||
| 388 | +struct virtio_iommu_fault { | ||
| 389 | + uint8_t reason; | ||
| 390 | + uint8_t reserved[3]; | ||
| 391 | + uint32_t flags; | ||
| 392 | + uint32_t endpoint; | ||
| 393 | + uint8_t reserved2[4]; | ||
| 394 | + uint64_t address; | ||
| 395 | +}; | ||
| 396 | + | ||
| 397 | +#endif | ||
| 398 | diff --git a/include/standard-headers/linux/virtio_pmem.h b/include/standard-headers/linux/virtio_pmem.h | ||
| 399 | index XXXXXXX..XXXXXXX 100644 | ||
| 400 | --- a/include/standard-headers/linux/virtio_pmem.h | ||
| 401 | +++ b/include/standard-headers/linux/virtio_pmem.h | ||
| 402 | @@ -XXX,XX +XXX,XX @@ | ||
| 403 | -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ | ||
| 404 | +/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause */ | ||
| 405 | /* | ||
| 406 | * Definitions for virtio-pmem devices. | ||
| 407 | * | ||
| 408 | @@ -XXX,XX +XXX,XX @@ | ||
| 409 | * Author(s): Pankaj Gupta <pagupta@redhat.com> | ||
| 410 | */ | ||
| 411 | |||
| 412 | -#ifndef _UAPI_LINUX_VIRTIO_PMEM_H | ||
| 413 | -#define _UAPI_LINUX_VIRTIO_PMEM_H | ||
| 414 | +#ifndef _LINUX_VIRTIO_PMEM_H | ||
| 415 | +#define _LINUX_VIRTIO_PMEM_H | ||
| 416 | |||
| 417 | #include "standard-headers/linux/types.h" | ||
| 418 | #include "standard-headers/linux/virtio_ids.h" | ||
| 419 | diff --git a/linux-headers/asm-arm/kvm.h b/linux-headers/asm-arm/kvm.h | ||
| 420 | index XXXXXXX..XXXXXXX 100644 | ||
| 421 | --- a/linux-headers/asm-arm/kvm.h | ||
| 422 | +++ b/linux-headers/asm-arm/kvm.h | ||
| 423 | @@ -XXX,XX +XXX,XX @@ struct kvm_vcpu_events { | ||
| 424 | #define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM | KVM_REG_SIZE_U64 | \ | ||
| 425 | KVM_REG_ARM_FW | ((r) & 0xffff)) | ||
| 426 | #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) | ||
| 427 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1) | ||
| 428 | + /* Higher values mean better protection. */ | ||
| 429 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0 | ||
| 430 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1 | ||
| 431 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2 | ||
| 432 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2) | ||
| 433 | + /* Higher values mean better protection. */ | ||
| 434 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0 | ||
| 435 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1 | ||
| 436 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2 | ||
| 437 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3 | ||
| 438 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4) | ||
| 439 | |||
| 440 | /* Device Control API: ARM VGIC */ | ||
| 441 | #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 | ||
| 442 | @@ -XXX,XX +XXX,XX @@ struct kvm_vcpu_events { | ||
| 443 | #define KVM_DEV_ARM_ITS_CTRL_RESET 4 | ||
| 444 | |||
| 445 | /* KVM_IRQ_LINE irq field index values */ | ||
| 446 | +#define KVM_ARM_IRQ_VCPU2_SHIFT 28 | ||
| 447 | +#define KVM_ARM_IRQ_VCPU2_MASK 0xf | ||
| 448 | #define KVM_ARM_IRQ_TYPE_SHIFT 24 | ||
| 449 | -#define KVM_ARM_IRQ_TYPE_MASK 0xff | ||
| 450 | +#define KVM_ARM_IRQ_TYPE_MASK 0xf | ||
| 451 | #define KVM_ARM_IRQ_VCPU_SHIFT 16 | ||
| 452 | #define KVM_ARM_IRQ_VCPU_MASK 0xff | ||
| 453 | #define KVM_ARM_IRQ_NUM_SHIFT 0 | ||
| 454 | diff --git a/linux-headers/asm-arm/unistd-common.h b/linux-headers/asm-arm/unistd-common.h | ||
| 455 | index XXXXXXX..XXXXXXX 100644 | ||
| 456 | --- a/linux-headers/asm-arm/unistd-common.h | ||
| 457 | +++ b/linux-headers/asm-arm/unistd-common.h | ||
| 458 | @@ -XXX,XX +XXX,XX @@ | ||
| 459 | #define __NR_fsconfig (__NR_SYSCALL_BASE + 431) | ||
| 460 | #define __NR_fsmount (__NR_SYSCALL_BASE + 432) | ||
| 461 | #define __NR_fspick (__NR_SYSCALL_BASE + 433) | ||
| 462 | +#define __NR_pidfd_open (__NR_SYSCALL_BASE + 434) | ||
| 463 | +#define __NR_clone3 (__NR_SYSCALL_BASE + 435) | ||
| 464 | |||
| 465 | #endif /* _ASM_ARM_UNISTD_COMMON_H */ | ||
| 466 | diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h | ||
| 467 | index XXXXXXX..XXXXXXX 100644 | ||
| 468 | --- a/linux-headers/asm-arm64/kvm.h | ||
| 469 | +++ b/linux-headers/asm-arm64/kvm.h | ||
| 470 | @@ -XXX,XX +XXX,XX @@ struct kvm_vcpu_events { | ||
| 471 | #define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ | ||
| 472 | KVM_REG_ARM_FW | ((r) & 0xffff)) | ||
| 473 | #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) | ||
| 474 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1) | ||
| 475 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0 | ||
| 476 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1 | ||
| 477 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2 | ||
| 478 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2) | ||
| 479 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0 | ||
| 480 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1 | ||
| 481 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2 | ||
| 482 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3 | ||
| 483 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4) | ||
| 484 | |||
| 485 | /* SVE registers */ | ||
| 486 | #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) | ||
| 487 | @@ -XXX,XX +XXX,XX @@ struct kvm_vcpu_events { | ||
| 488 | KVM_REG_SIZE_U256 | \ | ||
| 489 | ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) | ||
| 490 | |||
| 491 | +/* | ||
| 492 | + * Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and | ||
| 493 | + * KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness- | ||
| 494 | + * invariant layout which differs from the layout used for the FPSIMD | ||
| 495 | + * V-registers on big-endian systems: see sigcontext.h for more explanation. | ||
| 496 | + */ | ||
| 497 | + | ||
| 498 | #define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN | ||
| 499 | #define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX | ||
| 500 | |||
| 501 | @@ -XXX,XX +XXX,XX @@ struct kvm_vcpu_events { | ||
| 502 | #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 | ||
| 503 | |||
| 504 | /* KVM_IRQ_LINE irq field index values */ | ||
| 505 | +#define KVM_ARM_IRQ_VCPU2_SHIFT 28 | ||
| 506 | +#define KVM_ARM_IRQ_VCPU2_MASK 0xf | ||
| 507 | #define KVM_ARM_IRQ_TYPE_SHIFT 24 | ||
| 508 | -#define KVM_ARM_IRQ_TYPE_MASK 0xff | ||
| 509 | +#define KVM_ARM_IRQ_TYPE_MASK 0xf | ||
| 510 | #define KVM_ARM_IRQ_VCPU_SHIFT 16 | ||
| 511 | #define KVM_ARM_IRQ_VCPU_MASK 0xff | ||
| 512 | #define KVM_ARM_IRQ_NUM_SHIFT 0 | ||
| 513 | diff --git a/linux-headers/asm-generic/mman-common.h b/linux-headers/asm-generic/mman-common.h | ||
| 514 | index XXXXXXX..XXXXXXX 100644 | ||
| 515 | --- a/linux-headers/asm-generic/mman-common.h | ||
| 516 | +++ b/linux-headers/asm-generic/mman-common.h | ||
| 517 | @@ -XXX,XX +XXX,XX @@ | ||
| 518 | #define MAP_TYPE 0x0f /* Mask for type of mapping */ | ||
| 519 | #define MAP_FIXED 0x10 /* Interpret addr exactly */ | ||
| 520 | #define MAP_ANONYMOUS 0x20 /* don't use a file */ | ||
| 521 | -#ifdef CONFIG_MMAP_ALLOW_UNINITIALIZED | ||
| 522 | -# define MAP_UNINITIALIZED 0x4000000 /* For anonymous mmap, memory could be uninitialized */ | ||
| 523 | -#else | ||
| 524 | -# define MAP_UNINITIALIZED 0x0 /* Don't support this flag */ | ||
| 525 | -#endif | ||
| 526 | |||
| 527 | -/* 0x0100 - 0x80000 flags are defined in asm-generic/mman.h */ | ||
| 528 | +/* 0x0100 - 0x4000 flags are defined in asm-generic/mman.h */ | ||
| 529 | +#define MAP_POPULATE 0x008000 /* populate (prefault) pagetables */ | ||
| 530 | +#define MAP_NONBLOCK 0x010000 /* do not block on IO */ | ||
| 531 | +#define MAP_STACK 0x020000 /* give out an address that is best suited for process/thread stacks */ | ||
| 532 | +#define MAP_HUGETLB 0x040000 /* create a huge page mapping */ | ||
| 533 | +#define MAP_SYNC 0x080000 /* perform synchronous page faults for the mapping */ | ||
| 534 | #define MAP_FIXED_NOREPLACE 0x100000 /* MAP_FIXED which doesn't unmap underlying mapping */ | ||
| 535 | |||
| 536 | +#define MAP_UNINITIALIZED 0x4000000 /* For anonymous mmap, memory could be | ||
| 537 | + * uninitialized */ | ||
| 538 | + | ||
| 539 | /* | ||
| 540 | * Flags for mlock | ||
| 541 | */ | ||
| 542 | @@ -XXX,XX +XXX,XX @@ | ||
| 543 | #define MADV_WIPEONFORK 18 /* Zero memory on fork, child only */ | ||
| 544 | #define MADV_KEEPONFORK 19 /* Undo MADV_WIPEONFORK */ | ||
| 545 | |||
| 546 | +#define MADV_COLD 20 /* deactivate these pages */ | ||
| 547 | +#define MADV_PAGEOUT 21 /* reclaim these pages */ | ||
| 548 | + | ||
| 549 | /* compatibility flags */ | ||
| 550 | #define MAP_FILE 0 | ||
| 551 | |||
| 552 | diff --git a/linux-headers/asm-generic/mman.h b/linux-headers/asm-generic/mman.h | ||
| 553 | index XXXXXXX..XXXXXXX 100644 | ||
| 554 | --- a/linux-headers/asm-generic/mman.h | ||
| 555 | +++ b/linux-headers/asm-generic/mman.h | ||
| 556 | @@ -XXX,XX +XXX,XX @@ | ||
| 557 | #define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ | ||
| 558 | #define MAP_LOCKED 0x2000 /* pages are locked */ | ||
| 559 | #define MAP_NORESERVE 0x4000 /* don't check for reservations */ | ||
| 560 | -#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ | ||
| 561 | -#define MAP_NONBLOCK 0x10000 /* do not block on IO */ | ||
| 562 | -#define MAP_STACK 0x20000 /* give out an address that is best suited for process/thread stacks */ | ||
| 563 | -#define MAP_HUGETLB 0x40000 /* create a huge page mapping */ | ||
| 564 | -#define MAP_SYNC 0x80000 /* perform synchronous page faults for the mapping */ | ||
| 565 | |||
| 566 | -/* Bits [26:31] are reserved, see mman-common.h for MAP_HUGETLB usage */ | ||
| 567 | +/* | ||
| 568 | + * Bits [26:31] are reserved, see asm-generic/hugetlb_encode.h | ||
| 569 | + * for MAP_HUGETLB usage | ||
| 570 | + */ | ||
| 571 | |||
| 572 | #define MCL_CURRENT 1 /* lock all current mappings */ | ||
| 573 | #define MCL_FUTURE 2 /* lock all future mappings */ | ||
| 574 | diff --git a/linux-headers/asm-generic/unistd.h b/linux-headers/asm-generic/unistd.h | ||
| 575 | index XXXXXXX..XXXXXXX 100644 | ||
| 576 | --- a/linux-headers/asm-generic/unistd.h | ||
| 577 | +++ b/linux-headers/asm-generic/unistd.h | ||
| 578 | @@ -XXX,XX +XXX,XX @@ __SYSCALL(__NR_semget, sys_semget) | ||
| 579 | __SC_COMP(__NR_semctl, sys_semctl, compat_sys_semctl) | ||
| 580 | #if defined(__ARCH_WANT_TIME32_SYSCALLS) || __BITS_PER_LONG != 32 | ||
| 581 | #define __NR_semtimedop 192 | ||
| 582 | -__SC_COMP(__NR_semtimedop, sys_semtimedop, sys_semtimedop_time32) | ||
| 583 | +__SC_3264(__NR_semtimedop, sys_semtimedop_time32, sys_semtimedop) | ||
| 584 | #endif | ||
| 585 | #define __NR_semop 193 | ||
| 586 | __SYSCALL(__NR_semop, sys_semop) | ||
| 587 | @@ -XXX,XX +XXX,XX @@ __SYSCALL(__NR_fsconfig, sys_fsconfig) | ||
| 588 | __SYSCALL(__NR_fsmount, sys_fsmount) | ||
| 589 | #define __NR_fspick 433 | ||
| 590 | __SYSCALL(__NR_fspick, sys_fspick) | ||
| 591 | +#define __NR_pidfd_open 434 | ||
| 592 | +__SYSCALL(__NR_pidfd_open, sys_pidfd_open) | ||
| 593 | +#ifdef __ARCH_WANT_SYS_CLONE3 | ||
| 594 | +#define __NR_clone3 435 | ||
| 595 | +__SYSCALL(__NR_clone3, sys_clone3) | ||
| 596 | +#endif | ||
| 597 | |||
| 598 | #undef __NR_syscalls | ||
| 599 | -#define __NR_syscalls 434 | ||
| 600 | +#define __NR_syscalls 436 | ||
| 601 | |||
| 602 | /* | ||
| 603 | * 32 bit systems traditionally used different | ||
| 604 | diff --git a/linux-headers/asm-mips/mman.h b/linux-headers/asm-mips/mman.h | ||
| 605 | index XXXXXXX..XXXXXXX 100644 | ||
| 606 | --- a/linux-headers/asm-mips/mman.h | ||
| 607 | +++ b/linux-headers/asm-mips/mman.h | ||
| 608 | @@ -XXX,XX +XXX,XX @@ | ||
| 609 | #define MADV_WIPEONFORK 18 /* Zero memory on fork, child only */ | ||
| 610 | #define MADV_KEEPONFORK 19 /* Undo MADV_WIPEONFORK */ | ||
| 611 | |||
| 612 | +#define MADV_COLD 20 /* deactivate these pages */ | ||
| 613 | +#define MADV_PAGEOUT 21 /* reclaim these pages */ | ||
| 614 | + | ||
| 615 | /* compatibility flags */ | ||
| 616 | #define MAP_FILE 0 | ||
| 617 | |||
| 618 | diff --git a/linux-headers/asm-mips/unistd_n32.h b/linux-headers/asm-mips/unistd_n32.h | ||
| 619 | index XXXXXXX..XXXXXXX 100644 | ||
| 620 | --- a/linux-headers/asm-mips/unistd_n32.h | ||
| 621 | +++ b/linux-headers/asm-mips/unistd_n32.h | ||
| 622 | @@ -XXX,XX +XXX,XX @@ | ||
| 623 | #define __NR_fsconfig (__NR_Linux + 431) | ||
| 624 | #define __NR_fsmount (__NR_Linux + 432) | ||
| 625 | #define __NR_fspick (__NR_Linux + 433) | ||
| 626 | +#define __NR_pidfd_open (__NR_Linux + 434) | ||
| 627 | |||
| 628 | |||
| 629 | #endif /* _ASM_MIPS_UNISTD_N32_H */ | ||
| 630 | diff --git a/linux-headers/asm-mips/unistd_n64.h b/linux-headers/asm-mips/unistd_n64.h | ||
| 631 | index XXXXXXX..XXXXXXX 100644 | ||
| 632 | --- a/linux-headers/asm-mips/unistd_n64.h | ||
| 633 | +++ b/linux-headers/asm-mips/unistd_n64.h | ||
| 634 | @@ -XXX,XX +XXX,XX @@ | ||
| 635 | #define __NR_fsconfig (__NR_Linux + 431) | ||
| 636 | #define __NR_fsmount (__NR_Linux + 432) | ||
| 637 | #define __NR_fspick (__NR_Linux + 433) | ||
| 638 | +#define __NR_pidfd_open (__NR_Linux + 434) | ||
| 639 | |||
| 640 | |||
| 641 | #endif /* _ASM_MIPS_UNISTD_N64_H */ | ||
| 642 | diff --git a/linux-headers/asm-mips/unistd_o32.h b/linux-headers/asm-mips/unistd_o32.h | ||
| 643 | index XXXXXXX..XXXXXXX 100644 | ||
| 644 | --- a/linux-headers/asm-mips/unistd_o32.h | ||
| 645 | +++ b/linux-headers/asm-mips/unistd_o32.h | ||
| 646 | @@ -XXX,XX +XXX,XX @@ | ||
| 647 | #define __NR_fsconfig (__NR_Linux + 431) | ||
| 648 | #define __NR_fsmount (__NR_Linux + 432) | ||
| 649 | #define __NR_fspick (__NR_Linux + 433) | ||
| 650 | +#define __NR_pidfd_open (__NR_Linux + 434) | ||
| 651 | |||
| 652 | |||
| 653 | #endif /* _ASM_MIPS_UNISTD_O32_H */ | ||
| 654 | diff --git a/linux-headers/asm-powerpc/mman.h b/linux-headers/asm-powerpc/mman.h | ||
| 655 | index XXXXXXX..XXXXXXX 100644 | ||
| 656 | --- a/linux-headers/asm-powerpc/mman.h | ||
| 657 | +++ b/linux-headers/asm-powerpc/mman.h | ||
| 658 | @@ -XXX,XX +XXX,XX @@ | ||
| 659 | #define MAP_DENYWRITE 0x0800 /* ETXTBSY */ | ||
| 660 | #define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ | ||
| 661 | |||
| 662 | + | ||
| 663 | #define MCL_CURRENT 0x2000 /* lock all currently mapped pages */ | ||
| 664 | #define MCL_FUTURE 0x4000 /* lock all additions to address space */ | ||
| 665 | #define MCL_ONFAULT 0x8000 /* lock all pages that are faulted in */ | ||
| 666 | |||
| 667 | -#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ | ||
| 668 | -#define MAP_NONBLOCK 0x10000 /* do not block on IO */ | ||
| 669 | -#define MAP_STACK 0x20000 /* give out an address that is best suited for process/thread stacks */ | ||
| 670 | -#define MAP_HUGETLB 0x40000 /* create a huge page mapping */ | ||
| 671 | - | ||
| 672 | /* Override any generic PKEY permission defines */ | ||
| 673 | #define PKEY_DISABLE_EXECUTE 0x4 | ||
| 674 | #undef PKEY_ACCESS_MASK | ||
| 675 | diff --git a/linux-headers/asm-powerpc/unistd_32.h b/linux-headers/asm-powerpc/unistd_32.h | ||
| 676 | index XXXXXXX..XXXXXXX 100644 | ||
| 677 | --- a/linux-headers/asm-powerpc/unistd_32.h | ||
| 678 | +++ b/linux-headers/asm-powerpc/unistd_32.h | ||
| 679 | @@ -XXX,XX +XXX,XX @@ | ||
| 680 | #define __NR_fsconfig 431 | ||
| 681 | #define __NR_fsmount 432 | ||
| 682 | #define __NR_fspick 433 | ||
| 683 | +#define __NR_pidfd_open 434 | ||
| 684 | +#define __NR_clone3 435 | ||
| 685 | |||
| 686 | |||
| 687 | #endif /* _ASM_POWERPC_UNISTD_32_H */ | ||
| 688 | diff --git a/linux-headers/asm-powerpc/unistd_64.h b/linux-headers/asm-powerpc/unistd_64.h | ||
| 689 | index XXXXXXX..XXXXXXX 100644 | ||
| 690 | --- a/linux-headers/asm-powerpc/unistd_64.h | ||
| 691 | +++ b/linux-headers/asm-powerpc/unistd_64.h | ||
| 692 | @@ -XXX,XX +XXX,XX @@ | ||
| 693 | #define __NR_fsconfig 431 | ||
| 694 | #define __NR_fsmount 432 | ||
| 695 | #define __NR_fspick 433 | ||
| 696 | +#define __NR_pidfd_open 434 | ||
| 697 | +#define __NR_clone3 435 | ||
| 698 | |||
| 699 | |||
| 700 | #endif /* _ASM_POWERPC_UNISTD_64_H */ | ||
| 701 | diff --git a/linux-headers/asm-s390/kvm.h b/linux-headers/asm-s390/kvm.h | ||
| 702 | index XXXXXXX..XXXXXXX 100644 | ||
| 703 | --- a/linux-headers/asm-s390/kvm.h | ||
| 704 | +++ b/linux-headers/asm-s390/kvm.h | ||
| 705 | @@ -XXX,XX +XXX,XX @@ struct kvm_guest_debug_arch { | ||
| 706 | #define KVM_SYNC_GSCB (1UL << 9) | ||
| 707 | #define KVM_SYNC_BPBC (1UL << 10) | ||
| 708 | #define KVM_SYNC_ETOKEN (1UL << 11) | ||
| 709 | + | ||
| 710 | +#define KVM_SYNC_S390_VALID_FIELDS \ | ||
| 711 | + (KVM_SYNC_PREFIX | KVM_SYNC_GPRS | KVM_SYNC_ACRS | KVM_SYNC_CRS | \ | ||
| 712 | + KVM_SYNC_ARCH0 | KVM_SYNC_PFAULT | KVM_SYNC_VRS | KVM_SYNC_RICCB | \ | ||
| 713 | + KVM_SYNC_FPRS | KVM_SYNC_GSCB | KVM_SYNC_BPBC | KVM_SYNC_ETOKEN) | ||
| 714 | + | ||
| 715 | /* length and alignment of the sdnx as a power of two */ | ||
| 716 | #define SDNXC 8 | ||
| 717 | #define SDNXL (1UL << SDNXC) | ||
| 718 | diff --git a/linux-headers/asm-s390/unistd_32.h b/linux-headers/asm-s390/unistd_32.h | ||
| 719 | index XXXXXXX..XXXXXXX 100644 | ||
| 720 | --- a/linux-headers/asm-s390/unistd_32.h | ||
| 721 | +++ b/linux-headers/asm-s390/unistd_32.h | ||
| 722 | @@ -XXX,XX +XXX,XX @@ | ||
| 723 | #define __NR_fsconfig 431 | ||
| 724 | #define __NR_fsmount 432 | ||
| 725 | #define __NR_fspick 433 | ||
| 726 | +#define __NR_pidfd_open 434 | ||
| 727 | +#define __NR_clone3 435 | ||
| 728 | |||
| 729 | #endif /* _ASM_S390_UNISTD_32_H */ | ||
| 730 | diff --git a/linux-headers/asm-s390/unistd_64.h b/linux-headers/asm-s390/unistd_64.h | ||
| 731 | index XXXXXXX..XXXXXXX 100644 | ||
| 732 | --- a/linux-headers/asm-s390/unistd_64.h | ||
| 733 | +++ b/linux-headers/asm-s390/unistd_64.h | ||
| 734 | @@ -XXX,XX +XXX,XX @@ | ||
| 735 | #define __NR_fsconfig 431 | ||
| 736 | #define __NR_fsmount 432 | ||
| 737 | #define __NR_fspick 433 | ||
| 738 | +#define __NR_pidfd_open 434 | ||
| 739 | +#define __NR_clone3 435 | ||
| 740 | |||
| 741 | #endif /* _ASM_S390_UNISTD_64_H */ | ||
| 742 | diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h | ||
| 743 | index XXXXXXX..XXXXXXX 100644 | ||
| 744 | --- a/linux-headers/asm-x86/kvm.h | ||
| 745 | +++ b/linux-headers/asm-x86/kvm.h | ||
| 746 | @@ -XXX,XX +XXX,XX @@ struct kvm_sync_regs { | ||
| 747 | struct kvm_vcpu_events events; | ||
| 748 | }; | ||
| 749 | |||
| 750 | -#define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0) | ||
| 751 | -#define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1) | ||
| 752 | -#define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2) | ||
| 753 | -#define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3) | ||
| 754 | +#define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0) | ||
| 755 | +#define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1) | ||
| 756 | +#define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2) | ||
| 757 | +#define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3) | ||
| 758 | +#define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT (1 << 4) | ||
| 759 | |||
| 760 | #define KVM_STATE_NESTED_FORMAT_VMX 0 | ||
| 761 | -#define KVM_STATE_NESTED_FORMAT_SVM 1 | ||
| 762 | +#define KVM_STATE_NESTED_FORMAT_SVM 1 /* unused */ | ||
| 763 | |||
| 764 | #define KVM_STATE_NESTED_GUEST_MODE 0x00000001 | ||
| 765 | #define KVM_STATE_NESTED_RUN_PENDING 0x00000002 | ||
| 766 | #define KVM_STATE_NESTED_EVMCS 0x00000004 | ||
| 767 | |||
| 768 | -#define KVM_STATE_NESTED_VMX_VMCS_SIZE 0x1000 | ||
| 769 | - | ||
| 770 | #define KVM_STATE_NESTED_SMM_GUEST_MODE 0x00000001 | ||
| 771 | #define KVM_STATE_NESTED_SMM_VMXON 0x00000002 | ||
| 772 | |||
| 773 | +#define KVM_STATE_NESTED_VMX_VMCS_SIZE 0x1000 | ||
| 774 | + | ||
| 775 | struct kvm_vmx_nested_state_data { | ||
| 776 | __u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; | ||
| 777 | __u8 shadow_vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; | ||
| 778 | @@ -XXX,XX +XXX,XX @@ struct kvm_nested_state { | ||
| 779 | } data; | ||
| 780 | }; | ||
| 781 | |||
| 782 | +/* for KVM_CAP_PMU_EVENT_FILTER */ | ||
| 783 | +struct kvm_pmu_event_filter { | ||
| 784 | + __u32 action; | ||
| 785 | + __u32 nevents; | ||
| 786 | + __u32 fixed_counter_bitmap; | ||
| 787 | + __u32 flags; | ||
| 788 | + __u32 pad[4]; | ||
| 789 | + __u64 events[0]; | ||
| 790 | +}; | ||
| 791 | + | ||
| 792 | +#define KVM_PMU_EVENT_ALLOW 0 | ||
| 793 | +#define KVM_PMU_EVENT_DENY 1 | ||
| 794 | + | ||
| 795 | #endif /* _ASM_X86_KVM_H */ | ||
| 796 | diff --git a/linux-headers/asm-x86/unistd.h b/linux-headers/asm-x86/unistd.h | ||
| 797 | index XXXXXXX..XXXXXXX 100644 | ||
| 798 | --- a/linux-headers/asm-x86/unistd.h | ||
| 799 | +++ b/linux-headers/asm-x86/unistd.h | ||
| 800 | @@ -XXX,XX +XXX,XX @@ | ||
| 801 | #define _ASM_X86_UNISTD_H | ||
| 802 | |||
| 803 | /* x32 syscall flag bit */ | ||
| 804 | -#define __X32_SYSCALL_BIT 0x40000000 | ||
| 805 | +#define __X32_SYSCALL_BIT 0x40000000UL | ||
| 806 | |||
| 807 | # ifdef __i386__ | ||
| 808 | # include <asm/unistd_32.h> | ||
| 809 | diff --git a/linux-headers/asm-x86/unistd_32.h b/linux-headers/asm-x86/unistd_32.h | ||
| 810 | index XXXXXXX..XXXXXXX 100644 | ||
| 811 | --- a/linux-headers/asm-x86/unistd_32.h | ||
| 812 | +++ b/linux-headers/asm-x86/unistd_32.h | ||
| 813 | @@ -XXX,XX +XXX,XX @@ | ||
| 814 | #define __NR_fsconfig 431 | ||
| 815 | #define __NR_fsmount 432 | ||
| 816 | #define __NR_fspick 433 | ||
| 817 | +#define __NR_pidfd_open 434 | ||
| 818 | +#define __NR_clone3 435 | ||
| 819 | |||
| 820 | #endif /* _ASM_X86_UNISTD_32_H */ | ||
| 821 | diff --git a/linux-headers/asm-x86/unistd_64.h b/linux-headers/asm-x86/unistd_64.h | ||
| 822 | index XXXXXXX..XXXXXXX 100644 | ||
| 823 | --- a/linux-headers/asm-x86/unistd_64.h | ||
| 824 | +++ b/linux-headers/asm-x86/unistd_64.h | ||
| 825 | @@ -XXX,XX +XXX,XX @@ | ||
| 826 | #define __NR_fsconfig 431 | ||
| 827 | #define __NR_fsmount 432 | ||
| 828 | #define __NR_fspick 433 | ||
| 829 | +#define __NR_pidfd_open 434 | ||
| 830 | +#define __NR_clone3 435 | ||
| 831 | |||
| 832 | #endif /* _ASM_X86_UNISTD_64_H */ | ||
| 833 | diff --git a/linux-headers/asm-x86/unistd_x32.h b/linux-headers/asm-x86/unistd_x32.h | ||
| 834 | index XXXXXXX..XXXXXXX 100644 | ||
| 835 | --- a/linux-headers/asm-x86/unistd_x32.h | ||
| 836 | +++ b/linux-headers/asm-x86/unistd_x32.h | ||
| 837 | @@ -XXX,XX +XXX,XX @@ | ||
| 838 | #define __NR_fsconfig (__X32_SYSCALL_BIT + 431) | ||
| 839 | #define __NR_fsmount (__X32_SYSCALL_BIT + 432) | ||
| 840 | #define __NR_fspick (__X32_SYSCALL_BIT + 433) | ||
| 841 | +#define __NR_pidfd_open (__X32_SYSCALL_BIT + 434) | ||
| 842 | +#define __NR_clone3 (__X32_SYSCALL_BIT + 435) | ||
| 843 | #define __NR_rt_sigaction (__X32_SYSCALL_BIT + 512) | ||
| 844 | #define __NR_rt_sigreturn (__X32_SYSCALL_BIT + 513) | ||
| 845 | #define __NR_ioctl (__X32_SYSCALL_BIT + 514) | ||
| 846 | diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h | ||
| 847 | index XXXXXXX..XXXXXXX 100644 | ||
| 848 | --- a/linux-headers/linux/kvm.h | ||
| 849 | +++ b/linux-headers/linux/kvm.h | ||
| 850 | @@ -XXX,XX +XXX,XX @@ struct kvm_irq_level { | ||
| 851 | * ACPI gsi notion of irq. | ||
| 852 | * For IA-64 (APIC model) IOAPIC0: irq 0-23; IOAPIC1: irq 24-47.. | ||
| 853 | * For X86 (standard AT mode) PIC0/1: irq 0-15. IOAPIC0: 0-23.. | ||
| 854 | - * For ARM: See Documentation/virtual/kvm/api.txt | ||
| 855 | + * For ARM: See Documentation/virt/kvm/api.txt | ||
| 856 | */ | ||
| 857 | union { | ||
| 858 | __u32 irq; | ||
| 859 | @@ -XXX,XX +XXX,XX @@ struct kvm_hyperv_exit { | ||
| 860 | #define KVM_INTERNAL_ERROR_SIMUL_EX 2 | ||
| 861 | /* Encounter unexpected vm-exit due to delivery event. */ | ||
| 862 | #define KVM_INTERNAL_ERROR_DELIVERY_EV 3 | ||
| 863 | +/* Encounter unexpected vm-exit reason */ | ||
| 864 | +#define KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON 4 | ||
| 865 | |||
| 866 | /* for KVM_RUN, returned by mmap(vcpu_fd, offset=0) */ | ||
| 867 | struct kvm_run { | ||
| 868 | @@ -XXX,XX +XXX,XX @@ struct kvm_ppc_resize_hpt { | ||
| 869 | #define KVM_CAP_ARM_SVE 170 | ||
| 870 | #define KVM_CAP_ARM_PTRAUTH_ADDRESS 171 | ||
| 871 | #define KVM_CAP_ARM_PTRAUTH_GENERIC 172 | ||
| 872 | +#define KVM_CAP_PMU_EVENT_FILTER 173 | ||
| 873 | +#define KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 174 | ||
| 874 | +#define KVM_CAP_HYPERV_DIRECT_TLBFLUSH 175 | ||
| 875 | |||
| 876 | #ifdef KVM_CAP_IRQ_ROUTING | ||
| 877 | |||
| 878 | @@ -XXX,XX +XXX,XX @@ struct kvm_xen_hvm_config { | ||
| 879 | * | ||
| 880 | * KVM_IRQFD_FLAG_RESAMPLE indicates resamplefd is valid and specifies | ||
| 881 | * the irqfd to operate in resampling mode for level triggered interrupt | ||
| 882 | - * emulation. See Documentation/virtual/kvm/api.txt. | ||
| 883 | + * emulation. See Documentation/virt/kvm/api.txt. | ||
| 884 | */ | ||
| 885 | #define KVM_IRQFD_FLAG_RESAMPLE (1 << 1) | ||
| 886 | |||
| 887 | @@ -XXX,XX +XXX,XX @@ struct kvm_dirty_tlb { | ||
| 888 | #define KVM_REG_S390 0x5000000000000000ULL | ||
| 889 | #define KVM_REG_ARM64 0x6000000000000000ULL | ||
| 890 | #define KVM_REG_MIPS 0x7000000000000000ULL | ||
| 891 | +#define KVM_REG_RISCV 0x8000000000000000ULL | ||
| 892 | |||
| 893 | #define KVM_REG_SIZE_SHIFT 52 | ||
| 894 | #define KVM_REG_SIZE_MASK 0x00f0000000000000ULL | ||
| 895 | @@ -XXX,XX +XXX,XX @@ struct kvm_s390_ucas_mapping { | ||
| 896 | #define KVM_PPC_GET_RMMU_INFO _IOW(KVMIO, 0xb0, struct kvm_ppc_rmmu_info) | ||
| 897 | /* Available with KVM_CAP_PPC_GET_CPU_CHAR */ | ||
| 898 | #define KVM_PPC_GET_CPU_CHAR _IOR(KVMIO, 0xb1, struct kvm_ppc_cpu_char) | ||
| 899 | +/* Available with KVM_CAP_PMU_EVENT_FILTER */ | ||
| 900 | +#define KVM_SET_PMU_EVENT_FILTER _IOW(KVMIO, 0xb2, struct kvm_pmu_event_filter) | ||
| 901 | |||
| 902 | /* ioctl for vm fd */ | ||
| 903 | #define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device) | ||
| 904 | diff --git a/linux-headers/linux/psp-sev.h b/linux-headers/linux/psp-sev.h | ||
| 905 | index XXXXXXX..XXXXXXX 100644 | ||
| 906 | --- a/linux-headers/linux/psp-sev.h | ||
| 907 | +++ b/linux-headers/linux/psp-sev.h | ||
| 908 | @@ -XXX,XX +XXX,XX @@ | ||
| 909 | +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ | ||
| 910 | /* | ||
| 911 | * Userspace interface for AMD Secure Encrypted Virtualization (SEV) | ||
| 912 | * platform management commands. | ||
| 913 | @@ -XXX,XX +XXX,XX @@ | ||
| 914 | * Author: Brijesh Singh <brijesh.singh@amd.com> | ||
| 915 | * | ||
| 916 | * SEV API specification is available at: https://developer.amd.com/sev/ | ||
| 917 | - * | ||
| 918 | - * This program is free software; you can redistribute it and/or modify | ||
| 919 | - * it under the terms of the GNU General Public License version 2 as | ||
| 920 | - * published by the Free Software Foundation. | ||
| 921 | */ | ||
| 922 | |||
| 923 | #ifndef __PSP_SEV_USER_H__ | ||
| 924 | diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h | ||
| 925 | index XXXXXXX..XXXXXXX 100644 | ||
| 926 | --- a/linux-headers/linux/vfio.h | ||
| 927 | +++ b/linux-headers/linux/vfio.h | ||
| 928 | @@ -XXX,XX +XXX,XX @@ struct vfio_region_info_cap_type { | ||
| 929 | __u32 subtype; /* type specific */ | ||
| 930 | }; | ||
| 931 | |||
| 932 | +/* | ||
| 933 | + * List of region types, global per bus driver. | ||
| 934 | + * If you introduce a new type, please add it here. | ||
| 935 | + */ | ||
| 936 | + | ||
| 937 | +/* PCI region type containing a PCI vendor part */ | ||
| 938 | #define VFIO_REGION_TYPE_PCI_VENDOR_TYPE (1 << 31) | ||
| 939 | #define VFIO_REGION_TYPE_PCI_VENDOR_MASK (0xffff) | ||
| 940 | +#define VFIO_REGION_TYPE_GFX (1) | ||
| 941 | +#define VFIO_REGION_TYPE_CCW (2) | ||
| 942 | |||
| 943 | -/* 8086 Vendor sub-types */ | ||
| 944 | +/* sub-types for VFIO_REGION_TYPE_PCI_* */ | ||
| 945 | + | ||
| 946 | +/* 8086 vendor PCI sub-types */ | ||
| 947 | #define VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION (1) | ||
| 948 | #define VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG (2) | ||
| 949 | #define VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG (3) | ||
| 950 | |||
| 951 | -#define VFIO_REGION_TYPE_GFX (1) | ||
| 952 | +/* 10de vendor PCI sub-types */ | ||
| 953 | +/* | ||
| 954 | + * NVIDIA GPU NVlink2 RAM is coherent RAM mapped onto the host address space. | ||
| 955 | + */ | ||
| 956 | +#define VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM (1) | ||
| 957 | + | ||
| 958 | +/* 1014 vendor PCI sub-types */ | ||
| 959 | +/* | ||
| 960 | + * IBM NPU NVlink2 ATSD (Address Translation Shootdown) register of NPU | ||
| 961 | + * to do TLB invalidation on a GPU. | ||
| 962 | + */ | ||
| 963 | +#define VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD (1) | ||
| 964 | + | ||
| 965 | +/* sub-types for VFIO_REGION_TYPE_GFX */ | ||
| 966 | #define VFIO_REGION_SUBTYPE_GFX_EDID (1) | ||
| 967 | |||
| 968 | /** | ||
| 969 | @@ -XXX,XX +XXX,XX @@ struct vfio_region_gfx_edid { | ||
| 970 | #define VFIO_DEVICE_GFX_LINK_STATE_DOWN 2 | ||
| 971 | }; | ||
| 972 | |||
| 973 | -#define VFIO_REGION_TYPE_CCW (2) | ||
| 974 | -/* ccw sub-types */ | ||
| 975 | +/* sub-types for VFIO_REGION_TYPE_CCW */ | ||
| 976 | #define VFIO_REGION_SUBTYPE_CCW_ASYNC_CMD (1) | ||
| 977 | |||
| 978 | -/* | ||
| 979 | - * 10de vendor sub-type | ||
| 980 | - * | ||
| 981 | - * NVIDIA GPU NVlink2 RAM is coherent RAM mapped onto the host address space. | ||
| 982 | - */ | ||
| 983 | -#define VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM (1) | ||
| 984 | - | ||
| 985 | -/* | ||
| 986 | - * 1014 vendor sub-type | ||
| 987 | - * | ||
| 988 | - * IBM NPU NVlink2 ATSD (Address Translation Shootdown) register of NPU | ||
| 989 | - * to do TLB invalidation on a GPU. | ||
| 990 | - */ | ||
| 991 | -#define VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD (1) | ||
| 992 | - | ||
| 993 | /* | ||
| 994 | * The MSIX mappable capability informs that MSIX data of a BAR can be mmapped | ||
| 995 | * which allows direct access to non-MSIX registers which happened to be within | ||
| 996 | @@ -XXX,XX +XXX,XX @@ struct vfio_iommu_type1_info { | ||
| 997 | __u32 argsz; | ||
| 998 | __u32 flags; | ||
| 999 | #define VFIO_IOMMU_INFO_PGSIZES (1 << 0) /* supported page sizes info */ | ||
| 1000 | - __u64 iova_pgsizes; /* Bitmap of supported page sizes */ | ||
| 1001 | +#define VFIO_IOMMU_INFO_CAPS (1 << 1) /* Info supports caps */ | ||
| 1002 | + __u64 iova_pgsizes; /* Bitmap of supported page sizes */ | ||
| 1003 | + __u32 cap_offset; /* Offset within info struct of first cap */ | ||
| 1004 | +}; | ||
| 1005 | + | ||
| 1006 | +/* | ||
| 1007 | + * The IOVA capability allows to report the valid IOVA range(s) | ||
| 1008 | + * excluding any non-relaxable reserved regions exposed by | ||
| 1009 | + * devices attached to the container. Any DMA map attempt | ||
| 1010 | + * outside the valid iova range will return error. | ||
| 1011 | + * | ||
| 1012 | + * The structures below define version 1 of this capability. | ||
| 1013 | + */ | ||
| 1014 | +#define VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE 1 | ||
| 1015 | + | ||
| 1016 | +struct vfio_iova_range { | ||
| 1017 | + __u64 start; | ||
| 1018 | + __u64 end; | ||
| 1019 | +}; | ||
| 1020 | + | ||
| 1021 | +struct vfio_iommu_type1_info_cap_iova_range { | ||
| 1022 | + struct vfio_info_cap_header header; | ||
| 1023 | + __u32 nr_iovas; | ||
| 1024 | + __u32 reserved; | ||
| 1025 | + struct vfio_iova_range iova_ranges[]; | ||
| 1026 | }; | ||
| 1027 | |||
| 1028 | #define VFIO_IOMMU_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12) | ||
| 1029 | -- | 34 | -- |
| 1030 | 2.20.1 | 35 | 2.34.1 |
| 1031 | |||
| 1032 | diff view generated by jsdifflib |