1 | A large arm pullreq, mostly because of 3 series: | 1 | target-arm queue: I have a lot more still in my to-review |
---|---|---|---|
2 | * aspeed 2600 support | 2 | queue, but my rule of thumb is when I get to 50 patches or |
3 | * semihosting v2.0 support | 3 | so to send out what I have. |
4 | * transaction-based ptimers | ||
5 | 4 | ||
6 | thanks | 5 | thanks |
7 | -- PMM | 6 | -- PMM |
8 | 7 | ||
9 | The following changes since commit 22dbfdecc3c52228d3489da3fe81da92b21197bf: | 8 | The following changes since commit 9a7beaad3dbba982f7a461d676b55a5c3851d312: |
10 | 9 | ||
11 | Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20191010.0' into staging (2019-10-14 15:09:08 +0100) | 10 | Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210304' into staging (2021-03-05 10:47:46 +0000) |
12 | 11 | ||
13 | are available in the Git repository at: | 12 | are available in the Git repository at: |
14 | 13 | ||
15 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191014 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210305 |
16 | 15 | ||
17 | for you to fetch changes up to bca1936f8f66c5f8a111569ffd14969de208bf3b: | 16 | for you to fetch changes up to 2c669ff88ec6733420a000103a2b8b9e93df4945: |
18 | 17 | ||
19 | hw/misc/bcm2835_mbox: Add trace events (2019-10-14 16:48:56 +0100) | 18 | hw/arm/mps2: Update old infocenter.arm.com URLs (2021-03-05 15:17:38 +0000) |
20 | 19 | ||
21 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
22 | target-arm queue: | 21 | * sbsa-ref: remove cortex-a53 from list of supported cpus |
23 | * Add Aspeed AST2600 SoC and board support | 22 | * sbsa-ref: add 'max' to list of allowed cpus |
24 | * aspeed/wdt: Check correct register for clock source | 23 | * target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe |
25 | * bcm2835: code cleanups, better logging, trace events | 24 | * npcm7xx: add EMC model |
26 | * implement v2.0 of the Arm semihosting specification | 25 | * xlnx-zynqmp: Remove obsolete 'has_rpu' property |
27 | * provide new 'transaction-based' ptimer API and use it | 26 | * target/arm: Speed up aarch64 TBL/TBX |
28 | for the Arm devices that use ptimers | 27 | * virtio-mmio: improve virtio-mmio get_dev_path alog |
29 | * ARM: KVM: support more than 256 CPUs | 28 | * target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks |
29 | * target/arm: Restrict v8M IDAU to TCG | ||
30 | * target/arm/cpu: Update coding style to make checkpatch.pl happy | ||
31 | * musicpal, tc6393xb, omap_lcdc, tcx: drop dead code for non-32-bit-RGB surfaces | ||
32 | * Add new board: mps3-an524 | ||
30 | 33 | ||
31 | ---------------------------------------------------------------- | 34 | ---------------------------------------------------------------- |
32 | Amithash Prasad (1): | 35 | Doug Evans (3): |
33 | aspeed/wdt: Check correct register for clock source | 36 | hw/net: Add npcm7xx emc model |
37 | hw/arm: Add npcm7xx emc model | ||
38 | tests/qtests: Add npcm7xx emc model test | ||
34 | 39 | ||
35 | Cédric Le Goater (15): | 40 | Marcin Juszkiewicz (2): |
36 | aspeed/timer: Introduce an object class per SoC | 41 | sbsa-ref: remove cortex-a53 from list of supported cpus |
37 | aspeed/timer: Add support for control register 3 | 42 | sbsa-ref: add 'max' to list of allowed cpus |
38 | aspeed/timer: Add AST2600 support | ||
39 | aspeed/timer: Add support for IRQ status register on the AST2600 | ||
40 | aspeed/sdmc: Introduce an object class per SoC | ||
41 | watchdog/aspeed: Introduce an object class per SoC | ||
42 | aspeed/smc: Introduce segment operations | ||
43 | aspeed/smc: Add AST2600 support | ||
44 | aspeed/i2c: Introduce an object class per SoC | ||
45 | aspeed/i2c: Add AST2600 support | ||
46 | aspeed: Introduce an object class per SoC | ||
47 | aspeed/soc: Add AST2600 support | ||
48 | m25p80: Add support for w25q512jv | ||
49 | aspeed: Add an AST2600 eval board | ||
50 | aspeed: add support for the Aspeed MII controller of the AST2600 | ||
51 | 43 | ||
52 | Eddie James (1): | 44 | Peter Collingbourne (1): |
53 | hw/sd/aspeed_sdhci: New device | 45 | target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks |
54 | 46 | ||
55 | Eric Auger (3): | 47 | Peter Maydell (34): |
56 | linux headers: update against v5.4-rc1 | 48 | hw/arm/musicpal: Remove dead code for non-32-bit-RGB surfaces |
57 | intc/arm_gic: Support IRQ injection for more than 256 vpus | 49 | hw/display/tc6393xb: Remove dead code for handling non-32bpp surfaces |
58 | ARM: KVM: Check KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 for smp_cpus > 256 | 50 | hw/display/tc6393xb: Expand out macros in template header |
51 | hw/display/tc6393xb: Inline tc6393xb_draw_graphic32() at its callsite | ||
52 | hw/display/omap_lcdc: Expand out macros in template header | ||
53 | hw/display/omap_lcdc: Drop broken bigendian ifdef | ||
54 | hw/display/omap_lcdc: Fix coding style issues in template header | ||
55 | hw/display/omap_lcdc: Inline template header into C file | ||
56 | hw/display/omap_lcdc: Delete unnecessary macro | ||
57 | hw/display/tcx: Drop unnecessary code for handling BGR format outputs | ||
58 | hw/arm/mps2-tz: Make SYSCLK frequency board-specific | ||
59 | hw/misc/mps2-scc: Support configurable number of OSCCLK values | ||
60 | hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and mps2-an511 | ||
61 | hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board | ||
62 | hw/misc/mps2-fpgaio: Make number of LEDs configurable by board | ||
63 | hw/misc/mps2-fpgaio: Support SWITCH register | ||
64 | hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board | ||
65 | hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type | ||
66 | hw/arm/mps2-tz: Make number of IRQs board-specific | ||
67 | hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524 | ||
68 | hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI | ||
69 | hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interrupts | ||
70 | hw/arm/mps2-tz: Move device IRQ info to data structures | ||
71 | hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs | ||
72 | hw/arm/mps2-tz: Allow boards to have different PPCInfo data | ||
73 | hw/arm/mps2-tz: Make RAM arrangement board-specific | ||
74 | hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data | ||
75 | hw/arm/mps2-tz: Support ROMs as well as RAMs | ||
76 | hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo | ||
77 | hw/arm/mps2-tz: Add new mps3-an524 board | ||
78 | hw/arm/mps2-tz: Stub out USB controller for mps3-an524 | ||
79 | hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524 | ||
80 | docs/system/arm/mps2.rst: Document the new mps3-an524 board | ||
81 | hw/arm/mps2: Update old infocenter.arm.com URLs | ||
59 | 82 | ||
60 | Joel Stanley (5): | 83 | Philippe Mathieu-Daudé (4): |
61 | hw: aspeed_scu: Add AST2600 support | 84 | hw/arm/xlnx-zynqmp: Remove obsolete 'has_rpu' property |
62 | aspeed/sdmc: Add AST2600 support | 85 | hw/i2c/npcm7xx_smbus: Simplify npcm7xx_smbus_init() |
63 | hw: wdt_aspeed: Add AST2600 support | 86 | target/arm: Restrict v8M IDAU to TCG |
64 | aspeed: Parameterise number of MACs | 87 | target/arm/cpu: Update coding style to make checkpatch.pl happy |
65 | aspeed/soc: Add ASPEED Video stub | ||
66 | 88 | ||
67 | Peter Maydell (36): | 89 | Rebecca Cran (3): |
68 | ptimer: Rename ptimer_init() to ptimer_init_with_bh() | 90 | target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe |
69 | ptimer: Provide new transaction-based API | 91 | target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU |
70 | tests/ptimer-test: Switch to transaction-based ptimer API | 92 | target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU |
71 | hw/timer/arm_timer.c: Switch to transaction-based ptimer API | ||
72 | hw/arm/musicpal.c: Switch to transaction-based ptimer API | ||
73 | hw/timer/allwinner-a10-pit.c: Switch to transaction-based ptimer API | ||
74 | hw/timer/arm_mptimer.c: Switch to transaction-based ptimer API | ||
75 | hw/timer/cmsdk-apb-dualtimer.c: Switch to transaction-based ptimer API | ||
76 | hw/timer/cmsdk-apb-timer.c: Switch to transaction-based ptimer API | ||
77 | hw/timer/digic-timer.c: Switch to transaction-based ptimer API | ||
78 | hw/timer/exynos4210_mct.c: Switch GFRC to transaction-based ptimer API | ||
79 | hw/timer/exynos4210_mct.c: Switch LFRC to transaction-based ptimer API | ||
80 | hw/timer/exynos4210_mct.c: Switch ltick to transaction-based ptimer API | ||
81 | hw/timer/exynos4210_pwm.c: Switch to transaction-based ptimer API | ||
82 | hw/timer/exynos4210_rtc.c: Switch 1Hz ptimer to transaction-based API | ||
83 | hw/timer/exynos4210_rtc.c: Switch main ptimer to transaction-based API | ||
84 | hw/timer/imx_epit.c: Switch to transaction-based ptimer API | ||
85 | hw/timer/imx_gpt.c: Switch to transaction-based ptimer API | ||
86 | hw/timer/mss-timerc: Switch to transaction-based ptimer API | ||
87 | hw/watchdog/cmsdk-apb-watchdog.c: Switch to transaction-based ptimer API | ||
88 | hw/net/lan9118.c: Switch to transaction-based ptimer API | ||
89 | target/arm/arm-semi: Capture errno in softmmu version of set_swi_errno() | ||
90 | target/arm/arm-semi: Always set some kind of errno for failed calls | ||
91 | target/arm/arm-semi: Correct comment about gdb syscall races | ||
92 | target/arm/arm-semi: Make semihosting code hand out its own file descriptors | ||
93 | target/arm/arm-semi: Restrict use of TaskState* | ||
94 | target/arm/arm-semi: Use set_swi_errno() in gdbstub callback functions | ||
95 | target/arm/arm-semi: Factor out implementation of SYS_CLOSE | ||
96 | target/arm/arm-semi: Factor out implementation of SYS_WRITE | ||
97 | target/arm/arm-semi: Factor out implementation of SYS_READ | ||
98 | target/arm/arm-semi: Factor out implementation of SYS_ISTTY | ||
99 | target/arm/arm-semi: Factor out implementation of SYS_SEEK | ||
100 | target/arm/arm-semi: Factor out implementation of SYS_FLEN | ||
101 | target/arm/arm-semi: Implement support for semihosting feature detection | ||
102 | target/arm/arm-semi: Implement SH_EXT_EXIT_EXTENDED extension | ||
103 | target/arm/arm-semi: Implement SH_EXT_STDOUT_STDERR extension | ||
104 | 93 | ||
105 | Philippe Mathieu-Daudé (6): | 94 | Richard Henderson (1): |
106 | hw/arm/raspi: Use the IEC binary prefix definitions | 95 | target/arm: Speed up aarch64 TBL/TBX |
107 | hw/arm/bcm2835_peripherals: Improve logging | ||
108 | hw/arm/bcm2835_peripherals: Name various address spaces | ||
109 | hw/arm/bcm2835: Rename some definitions | ||
110 | hw/arm/bcm2835: Add various unimplemented peripherals | ||
111 | hw/misc/bcm2835_mbox: Add trace events | ||
112 | 96 | ||
113 | Rashmica Gupta (1): | 97 | schspa (1): |
114 | hw/gpio: Add in AST2600 specific implementation | 98 | virtio-mmio: improve virtio-mmio get_dev_path alog |
115 | 99 | ||
116 | hw/arm/Makefile.objs | 2 +- | 100 | docs/system/arm/mps2.rst | 24 +- |
117 | hw/sd/Makefile.objs | 1 + | 101 | docs/system/arm/nuvoton.rst | 3 +- |
118 | include/hw/arm/aspeed.h | 1 + | 102 | hw/display/omap_lcd_template.h | 169 -------- |
119 | include/hw/arm/aspeed_soc.h | 29 +- | 103 | hw/display/tc6393xb_template.h | 72 ---- |
120 | include/hw/arm/bcm2835_peripherals.h | 15 + | 104 | include/hw/arm/armsse.h | 4 +- |
121 | include/hw/arm/raspi_platform.h | 24 +- | 105 | include/hw/arm/npcm7xx.h | 2 + |
122 | include/hw/i2c/aspeed_i2c.h | 20 +- | 106 | include/hw/arm/xlnx-zynqmp.h | 2 - |
123 | include/hw/misc/aspeed_scu.h | 7 +- | 107 | include/hw/misc/armsse-cpuid.h | 2 +- |
124 | include/hw/misc/aspeed_sdmc.h | 20 +- | 108 | include/hw/misc/armsse-mhu.h | 2 +- |
125 | include/hw/net/ftgmac100.h | 17 + | 109 | include/hw/misc/iotkit-secctl.h | 2 +- |
126 | include/hw/ptimer.h | 83 ++- | 110 | include/hw/misc/iotkit-sysctl.h | 2 +- |
127 | include/hw/sd/aspeed_sdhci.h | 34 ++ | 111 | include/hw/misc/iotkit-sysinfo.h | 2 +- |
128 | include/hw/ssi/aspeed_smc.h | 4 + | 112 | include/hw/misc/mps2-fpgaio.h | 8 +- |
129 | include/hw/timer/aspeed_timer.h | 18 + | 113 | include/hw/misc/mps2-scc.h | 10 +- |
130 | include/hw/timer/mss-timer.h | 1 - | 114 | include/hw/net/npcm7xx_emc.h | 286 +++++++++++++ |
131 | include/hw/watchdog/wdt_aspeed.h | 19 +- | 115 | include/ui/console.h | 10 - |
132 | include/standard-headers/asm-x86/bootparam.h | 2 + | 116 | target/arm/cpu.h | 15 +- |
133 | include/standard-headers/asm-x86/kvm_para.h | 1 + | 117 | target/arm/helper-a64.h | 2 +- |
134 | include/standard-headers/linux/ethtool.h | 24 + | 118 | target/arm/internals.h | 6 + |
135 | include/standard-headers/linux/pci_regs.h | 19 +- | 119 | hw/arm/mps2-tz.c | 632 +++++++++++++++++++++++----- |
136 | include/standard-headers/linux/virtio_fs.h | 19 + | 120 | hw/arm/mps2.c | 5 + |
137 | include/standard-headers/linux/virtio_ids.h | 2 + | 121 | hw/arm/musicpal.c | 64 ++- |
138 | include/standard-headers/linux/virtio_iommu.h | 165 ++++++ | 122 | hw/arm/npcm7xx.c | 50 ++- |
139 | include/standard-headers/linux/virtio_pmem.h | 6 +- | 123 | hw/arm/sbsa-ref.c | 2 +- |
140 | linux-headers/asm-arm/kvm.h | 16 +- | 124 | hw/arm/xlnx-zynqmp.c | 6 - |
141 | linux-headers/asm-arm/unistd-common.h | 2 + | 125 | hw/display/omap_lcdc.c | 129 +++++- |
142 | linux-headers/asm-arm64/kvm.h | 21 +- | 126 | hw/display/tc6393xb.c | 48 +-- |
143 | linux-headers/asm-generic/mman-common.h | 18 +- | 127 | hw/display/tcx.c | 31 +- |
144 | linux-headers/asm-generic/mman.h | 10 +- | 128 | hw/i2c/npcm7xx_smbus.c | 1 - |
145 | linux-headers/asm-generic/unistd.h | 10 +- | 129 | hw/misc/armsse-cpuid.c | 2 +- |
146 | linux-headers/asm-mips/mman.h | 3 + | 130 | hw/misc/armsse-mhu.c | 2 +- |
147 | linux-headers/asm-mips/unistd_n32.h | 1 + | 131 | hw/misc/iotkit-sysctl.c | 2 +- |
148 | linux-headers/asm-mips/unistd_n64.h | 1 + | 132 | hw/misc/iotkit-sysinfo.c | 2 +- |
149 | linux-headers/asm-mips/unistd_o32.h | 1 + | 133 | hw/misc/mps2-fpgaio.c | 43 +- |
150 | linux-headers/asm-powerpc/mman.h | 6 +- | 134 | hw/misc/mps2-scc.c | 93 ++++- |
151 | linux-headers/asm-powerpc/unistd_32.h | 2 + | 135 | hw/net/npcm7xx_emc.c | 857 ++++++++++++++++++++++++++++++++++++++ |
152 | linux-headers/asm-powerpc/unistd_64.h | 2 + | 136 | hw/virtio/virtio-mmio.c | 13 +- |
153 | linux-headers/asm-s390/kvm.h | 6 + | 137 | target/arm/cpu.c | 23 +- |
154 | linux-headers/asm-s390/unistd_32.h | 2 + | 138 | target/arm/cpu64.c | 5 + |
155 | linux-headers/asm-s390/unistd_64.h | 2 + | 139 | target/arm/cpu_tcg.c | 8 + |
156 | linux-headers/asm-x86/kvm.h | 28 +- | 140 | target/arm/helper-a64.c | 32 -- |
157 | linux-headers/asm-x86/unistd.h | 2 +- | 141 | target/arm/helper.c | 39 +- |
158 | linux-headers/asm-x86/unistd_32.h | 2 + | 142 | target/arm/mte_helper.c | 13 +- |
159 | linux-headers/asm-x86/unistd_64.h | 2 + | 143 | target/arm/translate-a64.c | 70 +--- |
160 | linux-headers/asm-x86/unistd_x32.h | 2 + | 144 | target/arm/vec_helper.c | 48 +++ |
161 | linux-headers/linux/kvm.h | 12 +- | 145 | tests/qtest/npcm7xx_emc-test.c | 862 +++++++++++++++++++++++++++++++++++++++ |
162 | linux-headers/linux/psp-sev.h | 5 +- | 146 | hw/net/meson.build | 1 + |
163 | linux-headers/linux/vfio.h | 71 ++- | 147 | hw/net/trace-events | 17 + |
164 | target/arm/kvm_arm.h | 1 + | 148 | tests/qtest/meson.build | 3 +- |
165 | hw/arm/aspeed.c | 42 +- | 149 | 49 files changed, 3098 insertions(+), 628 deletions(-) |
166 | hw/arm/aspeed_ast2600.c | 523 +++++++++++++++++++ | 150 | delete mode 100644 hw/display/omap_lcd_template.h |
167 | hw/arm/aspeed_soc.c | 199 +++++--- | 151 | delete mode 100644 hw/display/tc6393xb_template.h |
168 | hw/arm/bcm2835_peripherals.c | 38 +- | 152 | create mode 100644 include/hw/net/npcm7xx_emc.h |
169 | hw/arm/bcm2836.c | 2 +- | 153 | create mode 100644 hw/net/npcm7xx_emc.c |
170 | hw/arm/musicpal.c | 16 +- | 154 | create mode 100644 tests/qtest/npcm7xx_emc-test.c |
171 | hw/arm/raspi.c | 4 +- | ||
172 | hw/block/m25p80.c | 1 + | ||
173 | hw/char/bcm2835_aux.c | 5 +- | ||
174 | hw/core/ptimer.c | 154 +++++- | ||
175 | hw/display/bcm2835_fb.c | 2 +- | ||
176 | hw/dma/bcm2835_dma.c | 10 +- | ||
177 | hw/dma/xilinx_axidma.c | 2 +- | ||
178 | hw/gpio/aspeed_gpio.c | 142 +++++- | ||
179 | hw/i2c/aspeed_i2c.c | 106 +++- | ||
180 | hw/intc/arm_gic_kvm.c | 7 +- | ||
181 | hw/intc/bcm2836_control.c | 7 +- | ||
182 | hw/m68k/mcf5206.c | 2 +- | ||
183 | hw/m68k/mcf5208.c | 2 +- | ||
184 | hw/misc/aspeed_scu.c | 194 ++++++- | ||
185 | hw/misc/aspeed_sdmc.c | 250 ++++++--- | ||
186 | hw/misc/bcm2835_mbox.c | 14 +- | ||
187 | hw/misc/bcm2835_property.c | 20 +- | ||
188 | hw/net/fsl_etsec/etsec.c | 2 +- | ||
189 | hw/net/ftgmac100.c | 162 ++++++ | ||
190 | hw/net/lan9118.c | 11 +- | ||
191 | hw/sd/aspeed_sdhci.c | 198 ++++++++ | ||
192 | hw/ssi/aspeed_smc.c | 177 ++++++- | ||
193 | hw/timer/allwinner-a10-pit.c | 12 +- | ||
194 | hw/timer/altera_timer.c | 2 +- | ||
195 | hw/timer/arm_mptimer.c | 18 +- | ||
196 | hw/timer/arm_timer.c | 16 +- | ||
197 | hw/timer/aspeed_timer.c | 213 +++++++- | ||
198 | hw/timer/cmsdk-apb-dualtimer.c | 14 +- | ||
199 | hw/timer/cmsdk-apb-timer.c | 15 +- | ||
200 | hw/timer/digic-timer.c | 16 +- | ||
201 | hw/timer/etraxfs_timer.c | 6 +- | ||
202 | hw/timer/exynos4210_mct.c | 107 +++- | ||
203 | hw/timer/exynos4210_pwm.c | 17 +- | ||
204 | hw/timer/exynos4210_rtc.c | 22 +- | ||
205 | hw/timer/grlib_gptimer.c | 2 +- | ||
206 | hw/timer/imx_epit.c | 32 +- | ||
207 | hw/timer/imx_gpt.c | 21 +- | ||
208 | hw/timer/lm32_timer.c | 2 +- | ||
209 | hw/timer/milkymist-sysctl.c | 4 +- | ||
210 | hw/timer/mss-timer.c | 11 +- | ||
211 | hw/timer/puv3_ost.c | 2 +- | ||
212 | hw/timer/sh_timer.c | 2 +- | ||
213 | hw/timer/slavio_timer.c | 2 +- | ||
214 | hw/timer/xilinx_timer.c | 2 +- | ||
215 | hw/watchdog/cmsdk-apb-watchdog.c | 13 +- | ||
216 | hw/watchdog/wdt_aspeed.c | 153 +++--- | ||
217 | target/arm/arm-semi.c | 707 +++++++++++++++++++++----- | ||
218 | target/arm/cpu.c | 10 +- | ||
219 | target/arm/kvm.c | 22 +- | ||
220 | tests/ptimer-test.c | 106 +++- | ||
221 | hw/misc/trace-events | 6 + | ||
222 | 106 files changed, 3958 insertions(+), 650 deletions(-) | ||
223 | create mode 100644 include/hw/sd/aspeed_sdhci.h | ||
224 | create mode 100644 include/standard-headers/linux/virtio_fs.h | ||
225 | create mode 100644 include/standard-headers/linux/virtio_iommu.h | ||
226 | create mode 100644 hw/arm/aspeed_ast2600.c | ||
227 | create mode 100644 hw/sd/aspeed_sdhci.c | ||
228 | 155 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 3 | Cortex-A53 supports 40bits of address space. sbsa-ref's memory starts |
4 | Reviewed-by: Joel Stanley <joel@jms.id.au> | 4 | above this limit. |
5 | Message-id: 20190925143248.10000-21-clg@kaod.org | 5 | |
6 | Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Acked-by: Leif Lindholm <leif@nuviainc.com> | ||
9 | Message-id: 20210216150122.3830863-2-marcin.juszkiewicz@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 11 | --- |
8 | include/hw/arm/aspeed.h | 1 + | 12 | hw/arm/sbsa-ref.c | 1 - |
9 | hw/arm/aspeed.c | 23 +++++++++++++++++++++++ | 13 | 1 file changed, 1 deletion(-) |
10 | 2 files changed, 24 insertions(+) | ||
11 | 14 | ||
12 | diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h | 15 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c |
13 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/include/hw/arm/aspeed.h | 17 | --- a/hw/arm/sbsa-ref.c |
15 | +++ b/include/hw/arm/aspeed.h | 18 | +++ b/hw/arm/sbsa-ref.c |
16 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedBoardConfig { | 19 | @@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = { |
17 | const char *desc; | ||
18 | const char *soc_name; | ||
19 | uint32_t hw_strap1; | ||
20 | + uint32_t hw_strap2; | ||
21 | const char *fmc_model; | ||
22 | const char *spi_model; | ||
23 | uint32_t num_cs; | ||
24 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/hw/arm/aspeed.c | ||
27 | +++ b/hw/arm/aspeed.c | ||
28 | @@ -XXX,XX +XXX,XX @@ struct AspeedBoardState { | ||
29 | /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ | ||
30 | #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 | ||
31 | |||
32 | +/* AST2600 evb hardware value */ | ||
33 | +#define AST2600_EVB_HW_STRAP1 0x000000C0 | ||
34 | +#define AST2600_EVB_HW_STRAP2 0x00000003 | ||
35 | + | ||
36 | /* | ||
37 | * The max ram region is for firmwares that scan the address space | ||
38 | * with load/store to guess how much RAM the SoC has. | ||
39 | @@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine, | ||
40 | &error_abort); | ||
41 | object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1", | ||
42 | &error_abort); | ||
43 | + object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap2, "hw-strap2", | ||
44 | + &error_abort); | ||
45 | object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs", | ||
46 | &error_abort); | ||
47 | object_property_set_int(OBJECT(&bmc->soc), machine->smp.cpus, "num-cpus", | ||
48 | @@ -XXX,XX +XXX,XX @@ static void ast2500_evb_i2c_init(AspeedBoardState *bmc) | ||
49 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); | ||
50 | } | ||
51 | |||
52 | +static void ast2600_evb_i2c_init(AspeedBoardState *bmc) | ||
53 | +{ | ||
54 | + /* Start with some devices on our I2C busses */ | ||
55 | + ast2500_evb_i2c_init(bmc); | ||
56 | +} | ||
57 | + | ||
58 | static void romulus_bmc_i2c_init(AspeedBoardState *bmc) | ||
59 | { | ||
60 | AspeedSoCState *soc = &bmc->soc; | ||
61 | @@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = { | ||
62 | .num_cs = 2, | ||
63 | .i2c_init = witherspoon_bmc_i2c_init, | ||
64 | .ram = 512 * MiB, | ||
65 | + }, { | ||
66 | + .name = MACHINE_TYPE_NAME("ast2600-evb"), | ||
67 | + .desc = "Aspeed AST2600 EVB (Cortex A7)", | ||
68 | + .soc_name = "ast2600-a0", | ||
69 | + .hw_strap1 = AST2600_EVB_HW_STRAP1, | ||
70 | + .hw_strap2 = AST2600_EVB_HW_STRAP2, | ||
71 | + .fmc_model = "w25q512jv", | ||
72 | + .spi_model = "mx66u51235f", | ||
73 | + .num_cs = 1, | ||
74 | + .i2c_init = ast2600_evb_i2c_init, | ||
75 | + .ram = 2 * GiB, | ||
76 | }, | ||
77 | }; | 20 | }; |
78 | 21 | ||
22 | static const char * const valid_cpus[] = { | ||
23 | - ARM_CPU_TYPE_NAME("cortex-a53"), | ||
24 | ARM_CPU_TYPE_NAME("cortex-a57"), | ||
25 | ARM_CPU_TYPE_NAME("cortex-a72"), | ||
26 | }; | ||
79 | -- | 27 | -- |
80 | 2.20.1 | 28 | 2.20.1 |
81 | 29 | ||
82 | 30 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 3 | Let add 'max' cpu while work goes on adding newer CPU types than |
4 | Reviewed-by: Joel Stanley <joel@jms.id.au> | 4 | Cortex-A72. This allows us to check SVE etc support. |
5 | Message-id: 20190925143248.10000-20-clg@kaod.org | 5 | |
6 | Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> | ||
7 | Acked-by: Leif Lindholm <leif@nuviainc.com> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Message-id: 20210216150122.3830863-3-marcin.juszkiewicz@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 11 | --- |
8 | hw/block/m25p80.c | 1 + | 12 | hw/arm/sbsa-ref.c | 1 + |
9 | 1 file changed, 1 insertion(+) | 13 | 1 file changed, 1 insertion(+) |
10 | 14 | ||
11 | diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c | 15 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c |
12 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/block/m25p80.c | 17 | --- a/hw/arm/sbsa-ref.c |
14 | +++ b/hw/block/m25p80.c | 18 | +++ b/hw/arm/sbsa-ref.c |
15 | @@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = { | 19 | @@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = { |
16 | { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) }, | 20 | static const char * const valid_cpus[] = { |
17 | { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) }, | 21 | ARM_CPU_TYPE_NAME("cortex-a57"), |
18 | { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) }, | 22 | ARM_CPU_TYPE_NAME("cortex-a72"), |
19 | + { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K) }, | 23 | + ARM_CPU_TYPE_NAME("max"), |
20 | }; | 24 | }; |
21 | 25 | ||
22 | typedef enum { | 26 | static bool cpu_type_valid(const char *cpu) |
23 | -- | 27 | -- |
24 | 2.20.1 | 28 | 2.20.1 |
25 | 29 | ||
26 | 30 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Rebecca Cran <rebecca@nuviainc.com> |
---|---|---|---|
2 | 2 | ||
3 | The I2C controller of the AST2400 and AST2500 SoCs have one IRQ shared | 3 | Add support for FEAT_SSBS. SSBS (Speculative Store Bypass Safe) is an |
4 | by all I2C busses. The AST2600 SoC I2C controller has one IRQ per bus | 4 | optional feature in ARMv8.0, and mandatory in ARMv8.5. |
5 | and 16 busses. | ||
6 | 5 | ||
7 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 6 | Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> |
8 | Reviewed-by: Joel Stanley <joel@jms.id.au> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20190925143248.10000-17-clg@kaod.org | 8 | Message-id: 20210216224543.16142-2-rebecca@nuviainc.com |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 10 | --- |
12 | include/hw/i2c/aspeed_i2c.h | 5 +++- | 11 | target/arm/cpu.h | 15 ++++++++++++++- |
13 | hw/i2c/aspeed_i2c.c | 46 +++++++++++++++++++++++++++++++++++-- | 12 | target/arm/internals.h | 6 ++++++ |
14 | 2 files changed, 48 insertions(+), 3 deletions(-) | 13 | target/arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++ |
14 | target/arm/translate-a64.c | 12 ++++++++++++ | ||
15 | 4 files changed, 69 insertions(+), 1 deletion(-) | ||
15 | 16 | ||
16 | diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h | 17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
17 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/i2c/aspeed_i2c.h | 19 | --- a/target/arm/cpu.h |
19 | +++ b/include/hw/i2c/aspeed_i2c.h | 20 | +++ b/target/arm/cpu.h |
20 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); |
21 | #define TYPE_ASPEED_I2C "aspeed.i2c" | 22 | #define SCTLR_TE (1U << 30) /* AArch32 only */ |
22 | #define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400" | 23 | #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ |
23 | #define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500" | 24 | #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ |
24 | +#define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600" | 25 | +#define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ |
25 | #define ASPEED_I2C(obj) \ | 26 | #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ |
26 | OBJECT_CHECK(AspeedI2CState, (obj), TYPE_ASPEED_I2C) | 27 | #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ |
27 | 28 | #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ | |
28 | -#define ASPEED_I2C_NR_BUSSES 14 | 29 | @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); |
29 | +#define ASPEED_I2C_NR_BUSSES 16 | 30 | #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ |
30 | 31 | #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ | |
31 | struct AspeedI2CState; | 32 | #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ |
32 | 33 | -#define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ | |
33 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedI2CBus { | 34 | +#define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ |
34 | 35 | ||
35 | I2CBus *bus; | 36 | #define CPTR_TCPAC (1U << 31) |
36 | uint8_t id; | 37 | #define CPTR_TTA (1U << 20) |
37 | + qemu_irq irq; | 38 | @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); |
38 | 39 | #define CPSR_IL (1U << 20) | |
39 | uint32_t ctrl; | 40 | #define CPSR_DIT (1U << 21) |
40 | uint32_t timing[2]; | 41 | #define CPSR_PAN (1U << 22) |
41 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedI2CClass { | 42 | +#define CPSR_SSBS (1U << 23) |
42 | uint8_t num_busses; | 43 | #define CPSR_J (1U << 24) |
43 | uint8_t reg_size; | 44 | #define CPSR_IT_0_1 (3U << 25) |
44 | uint8_t gap; | 45 | #define CPSR_Q (1U << 27) |
45 | + qemu_irq (*bus_get_irq)(AspeedI2CBus *); | 46 | @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); |
46 | } AspeedI2CClass; | 47 | #define PSTATE_A (1U << 8) |
47 | 48 | #define PSTATE_D (1U << 9) | |
48 | I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr); | 49 | #define PSTATE_BTYPE (3U << 10) |
49 | diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c | 50 | +#define PSTATE_SSBS (1U << 12) |
50 | index XXXXXXX..XXXXXXX 100644 | 51 | #define PSTATE_IL (1U << 20) |
51 | --- a/hw/i2c/aspeed_i2c.c | 52 | #define PSTATE_SS (1U << 21) |
52 | +++ b/hw/i2c/aspeed_i2c.c | 53 | #define PSTATE_PAN (1U << 22) |
53 | @@ -XXX,XX +XXX,XX @@ static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus) | 54 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) |
54 | 55 | return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; | |
55 | static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus) | ||
56 | { | ||
57 | + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); | ||
58 | + | ||
59 | bus->intr_status &= bus->intr_ctrl; | ||
60 | if (bus->intr_status) { | ||
61 | bus->controller->intr_status |= 1 << bus->id; | ||
62 | - qemu_irq_raise(bus->controller->irq); | ||
63 | + qemu_irq_raise(aic->bus_get_irq(bus)); | ||
64 | } | ||
65 | } | 56 | } |
66 | 57 | ||
67 | @@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, | 58 | +static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) |
68 | uint64_t value, unsigned size) | ||
69 | { | ||
70 | AspeedI2CBus *bus = opaque; | ||
71 | + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); | ||
72 | bool handle_rx; | ||
73 | |||
74 | switch (offset) { | ||
75 | @@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, | ||
76 | bus->intr_status &= ~(value & 0x7FFF); | ||
77 | if (!bus->intr_status) { | ||
78 | bus->controller->intr_status &= ~(1 << bus->id); | ||
79 | - qemu_irq_lower(bus->controller->irq); | ||
80 | + qemu_irq_lower(aic->bus_get_irq(bus)); | ||
81 | } | ||
82 | if (handle_rx && (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST))) { | ||
83 | aspeed_i2c_handle_rx_cmd(bus); | ||
84 | @@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp) | ||
85 | for (i = 0; i < aic->num_busses; i++) { | ||
86 | char name[32]; | ||
87 | int offset = i < aic->gap ? 1 : 5; | ||
88 | + | ||
89 | + sysbus_init_irq(sbd, &s->busses[i].irq); | ||
90 | snprintf(name, sizeof(name), "aspeed.i2c.%d", i); | ||
91 | s->busses[i].controller = s; | ||
92 | s->busses[i].id = i; | ||
93 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_i2c_info = { | ||
94 | .abstract = true, | ||
95 | }; | ||
96 | |||
97 | +static qemu_irq aspeed_2400_i2c_bus_get_irq(AspeedI2CBus *bus) | ||
98 | +{ | 59 | +{ |
99 | + return bus->controller->irq; | 60 | + return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; |
100 | +} | 61 | +} |
101 | + | 62 | + |
102 | static void aspeed_2400_i2c_class_init(ObjectClass *klass, void *data) | 63 | /* |
103 | { | 64 | * 64-bit feature tests via id registers. |
104 | DeviceClass *dc = DEVICE_CLASS(klass); | 65 | */ |
105 | @@ -XXX,XX +XXX,XX @@ static void aspeed_2400_i2c_class_init(ObjectClass *klass, void *data) | 66 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) |
106 | aic->num_busses = 14; | 67 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; |
107 | aic->reg_size = 0x40; | ||
108 | aic->gap = 7; | ||
109 | + aic->bus_get_irq = aspeed_2400_i2c_bus_get_irq; | ||
110 | } | 68 | } |
111 | 69 | ||
112 | static const TypeInfo aspeed_2400_i2c_info = { | 70 | +static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) |
113 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_2400_i2c_info = { | ||
114 | .class_init = aspeed_2400_i2c_class_init, | ||
115 | }; | ||
116 | |||
117 | +static qemu_irq aspeed_2500_i2c_bus_get_irq(AspeedI2CBus *bus) | ||
118 | +{ | 71 | +{ |
119 | + return bus->controller->irq; | 72 | + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; |
120 | +} | 73 | +} |
121 | + | 74 | + |
122 | static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data) | 75 | /* |
123 | { | 76 | * Feature tests for "does this exist in either 32-bit or 64-bit?" |
124 | DeviceClass *dc = DEVICE_CLASS(klass); | 77 | */ |
125 | @@ -XXX,XX +XXX,XX @@ static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data) | 78 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
126 | aic->num_busses = 14; | 79 | index XXXXXXX..XXXXXXX 100644 |
127 | aic->reg_size = 0x40; | 80 | --- a/target/arm/internals.h |
128 | aic->gap = 7; | 81 | +++ b/target/arm/internals.h |
129 | + aic->bus_get_irq = aspeed_2500_i2c_bus_get_irq; | 82 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, |
83 | if (isar_feature_aa32_dit(id)) { | ||
84 | valid |= CPSR_DIT; | ||
85 | } | ||
86 | + if (isar_feature_aa32_ssbs(id)) { | ||
87 | + valid |= CPSR_SSBS; | ||
88 | + } | ||
89 | |||
90 | return valid; | ||
130 | } | 91 | } |
131 | 92 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) | |
132 | static const TypeInfo aspeed_2500_i2c_info = { | 93 | if (isar_feature_aa64_dit(id)) { |
133 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_2500_i2c_info = { | 94 | valid |= PSTATE_DIT; |
134 | .class_init = aspeed_2500_i2c_class_init, | 95 | } |
96 | + if (isar_feature_aa64_ssbs(id)) { | ||
97 | + valid |= PSTATE_SSBS; | ||
98 | + } | ||
99 | if (isar_feature_aa64_mte(id)) { | ||
100 | valid |= PSTATE_TCO; | ||
101 | } | ||
102 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
103 | index XXXXXXX..XXXXXXX 100644 | ||
104 | --- a/target/arm/helper.c | ||
105 | +++ b/target/arm/helper.c | ||
106 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dit_reginfo = { | ||
107 | .readfn = aa64_dit_read, .writefn = aa64_dit_write | ||
135 | }; | 108 | }; |
136 | 109 | ||
137 | +static qemu_irq aspeed_2600_i2c_bus_get_irq(AspeedI2CBus *bus) | 110 | +static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri) |
138 | +{ | 111 | +{ |
139 | + return bus->irq; | 112 | + return env->pstate & PSTATE_SSBS; |
140 | +} | 113 | +} |
141 | + | 114 | + |
142 | +static void aspeed_2600_i2c_class_init(ObjectClass *klass, void *data) | 115 | +static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri, |
116 | + uint64_t value) | ||
143 | +{ | 117 | +{ |
144 | + DeviceClass *dc = DEVICE_CLASS(klass); | 118 | + env->pstate = (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS); |
145 | + AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); | ||
146 | + | ||
147 | + dc->desc = "ASPEED 2600 I2C Controller"; | ||
148 | + | ||
149 | + aic->num_busses = 16; | ||
150 | + aic->reg_size = 0x80; | ||
151 | + aic->gap = -1; /* no gap */ | ||
152 | + aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; | ||
153 | +} | 119 | +} |
154 | + | 120 | + |
155 | +static const TypeInfo aspeed_2600_i2c_info = { | 121 | +static const ARMCPRegInfo ssbs_reginfo = { |
156 | + .name = TYPE_ASPEED_2600_I2C, | 122 | + .name = "SSBS", .state = ARM_CP_STATE_AA64, |
157 | + .parent = TYPE_ASPEED_I2C, | 123 | + .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 6, |
158 | + .class_init = aspeed_2600_i2c_class_init, | 124 | + .type = ARM_CP_NO_RAW, .access = PL0_RW, |
125 | + .readfn = aa64_ssbs_read, .writefn = aa64_ssbs_write | ||
159 | +}; | 126 | +}; |
160 | + | 127 | + |
161 | static void aspeed_i2c_register_types(void) | 128 | static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, |
162 | { | 129 | const ARMCPRegInfo *ri, |
163 | type_register_static(&aspeed_i2c_info); | 130 | bool isread) |
164 | type_register_static(&aspeed_2400_i2c_info); | 131 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) |
165 | type_register_static(&aspeed_2500_i2c_info); | 132 | if (cpu_isar_feature(aa64_dit, cpu)) { |
166 | + type_register_static(&aspeed_2600_i2c_info); | 133 | define_one_arm_cp_reg(cpu, &dit_reginfo); |
167 | } | 134 | } |
168 | 135 | + if (cpu_isar_feature(aa64_ssbs, cpu)) { | |
169 | type_init(aspeed_i2c_register_types) | 136 | + define_one_arm_cp_reg(cpu, &ssbs_reginfo); |
137 | + } | ||
138 | |||
139 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { | ||
140 | define_arm_cp_regs(cpu, vhe_reginfo); | ||
141 | @@ -XXX,XX +XXX,XX @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, | ||
142 | env->uncached_cpsr &= ~(CPSR_IL | CPSR_J); | ||
143 | env->daif |= mask; | ||
144 | |||
145 | + if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) { | ||
146 | + if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) { | ||
147 | + env->uncached_cpsr |= CPSR_SSBS; | ||
148 | + } else { | ||
149 | + env->uncached_cpsr &= ~CPSR_SSBS; | ||
150 | + } | ||
151 | + } | ||
152 | + | ||
153 | if (new_mode == ARM_CPU_MODE_HYP) { | ||
154 | env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0; | ||
155 | env->elr_el[2] = env->regs[15]; | ||
156 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | ||
157 | new_mode |= PSTATE_TCO; | ||
158 | } | ||
159 | |||
160 | + if (cpu_isar_feature(aa64_ssbs, cpu)) { | ||
161 | + if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) { | ||
162 | + new_mode |= PSTATE_SSBS; | ||
163 | + } else { | ||
164 | + new_mode &= ~PSTATE_SSBS; | ||
165 | + } | ||
166 | + } | ||
167 | + | ||
168 | pstate_write(env, PSTATE_DAIF | new_mode); | ||
169 | env->aarch64 = 1; | ||
170 | aarch64_restore_sp(env, new_el); | ||
171 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
172 | index XXXXXXX..XXXXXXX 100644 | ||
173 | --- a/target/arm/translate-a64.c | ||
174 | +++ b/target/arm/translate-a64.c | ||
175 | @@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn, | ||
176 | tcg_temp_free_i32(t1); | ||
177 | break; | ||
178 | |||
179 | + case 0x19: /* SSBS */ | ||
180 | + if (!dc_isar_feature(aa64_ssbs, s)) { | ||
181 | + goto do_unallocated; | ||
182 | + } | ||
183 | + if (crm & 1) { | ||
184 | + set_pstate_bits(PSTATE_SSBS); | ||
185 | + } else { | ||
186 | + clear_pstate_bits(PSTATE_SSBS); | ||
187 | + } | ||
188 | + /* Don't need to rebuild hflags since SSBS is a nop */ | ||
189 | + break; | ||
190 | + | ||
191 | case 0x1a: /* DIT */ | ||
192 | if (!dc_isar_feature(aa64_dit, s)) { | ||
193 | goto do_unallocated; | ||
170 | -- | 194 | -- |
171 | 2.20.1 | 195 | 2.20.1 |
172 | 196 | ||
173 | 197 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Rebecca Cran <rebecca@nuviainc.com> |
---|---|---|---|
2 | 2 | ||
3 | Base addresses and sizes taken from the "BCM2835 ARM Peripherals" | 3 | Set ID_AA64PFR1_EL1.SSBS to 2 and ID_PFR2.SSBS to 1. |
4 | datasheet from February 06 2012: | ||
5 | https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf | ||
6 | 4 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> |
8 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 7 | Message-id: 20210216224543.16142-3-rebecca@nuviainc.com |
10 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
11 | Message-id: 20190926173428.10713-6-f4bug@amsat.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 9 | --- |
14 | include/hw/arm/bcm2835_peripherals.h | 15 ++++++++++++++ | 10 | target/arm/cpu64.c | 5 +++++ |
15 | include/hw/arm/raspi_platform.h | 8 +++++++ | 11 | 1 file changed, 5 insertions(+) |
16 | hw/arm/bcm2835_peripherals.c | 31 ++++++++++++++++++++++++++++ | ||
17 | 3 files changed, 54 insertions(+) | ||
18 | 12 | ||
19 | diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h | 13 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
20 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/include/hw/arm/bcm2835_peripherals.h | 15 | --- a/target/arm/cpu64.c |
22 | +++ b/include/hw/arm/bcm2835_peripherals.h | 16 | +++ b/target/arm/cpu64.c |
23 | @@ -XXX,XX +XXX,XX @@ | 17 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
24 | #include "hw/sd/sdhci.h" | 18 | |
25 | #include "hw/sd/bcm2835_sdhost.h" | 19 | t = cpu->isar.id_aa64pfr1; |
26 | #include "hw/gpio/bcm2835_gpio.h" | 20 | t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); |
27 | +#include "hw/misc/unimp.h" | 21 | + t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); |
28 | 22 | /* | |
29 | #define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals" | 23 | * Begin with full support for MTE. This will be downgraded to MTE=0 |
30 | #define BCM2835_PERIPHERALS(obj) \ | 24 | * during realize if the board provides no tag memory, much like |
31 | @@ -XXX,XX +XXX,XX @@ typedef struct BCM2835PeripheralState { | 25 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
32 | MemoryRegion ram_alias[4]; | 26 | u = FIELD_DP32(u, ID_PFR0, DIT, 1); |
33 | qemu_irq irq, fiq; | 27 | cpu->isar.id_pfr0 = u; |
34 | 28 | ||
35 | + UnimplementedDeviceState systmr; | 29 | + u = cpu->isar.id_pfr2; |
36 | + UnimplementedDeviceState armtmr; | 30 | + u = FIELD_DP32(u, ID_PFR2, SSBS, 1); |
37 | + UnimplementedDeviceState cprman; | 31 | + cpu->isar.id_pfr2 = u; |
38 | + UnimplementedDeviceState a2w; | ||
39 | PL011State uart0; | ||
40 | BCM2835AuxState aux; | ||
41 | BCM2835FBState fb; | ||
42 | @@ -XXX,XX +XXX,XX @@ typedef struct BCM2835PeripheralState { | ||
43 | SDHCIState sdhci; | ||
44 | BCM2835SDHostState sdhost; | ||
45 | BCM2835GpioState gpio; | ||
46 | + UnimplementedDeviceState i2s; | ||
47 | + UnimplementedDeviceState spi[1]; | ||
48 | + UnimplementedDeviceState i2c[3]; | ||
49 | + UnimplementedDeviceState otp; | ||
50 | + UnimplementedDeviceState dbus; | ||
51 | + UnimplementedDeviceState ave0; | ||
52 | + UnimplementedDeviceState bscsl; | ||
53 | + UnimplementedDeviceState smi; | ||
54 | + UnimplementedDeviceState dwc2; | ||
55 | + UnimplementedDeviceState sdramc; | ||
56 | } BCM2835PeripheralState; | ||
57 | |||
58 | #endif /* BCM2835_PERIPHERALS_H */ | ||
59 | diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h | ||
60 | index XXXXXXX..XXXXXXX 100644 | ||
61 | --- a/include/hw/arm/raspi_platform.h | ||
62 | +++ b/include/hw/arm/raspi_platform.h | ||
63 | @@ -XXX,XX +XXX,XX @@ | ||
64 | * Doorbells & Mailboxes */ | ||
65 | #define CPRMAN_OFFSET 0x100000 /* Power Management, Watchdog */ | ||
66 | #define CM_OFFSET 0x101000 /* Clock Management */ | ||
67 | +#define A2W_OFFSET 0x102000 /* Reset controller */ | ||
68 | +#define AVS_OFFSET 0x103000 /* Audio Video Standard */ | ||
69 | #define RNG_OFFSET 0x104000 | ||
70 | #define GPIO_OFFSET 0x200000 | ||
71 | #define UART0_OFFSET 0x201000 | ||
72 | @@ -XXX,XX +XXX,XX @@ | ||
73 | #define I2S_OFFSET 0x203000 | ||
74 | #define SPI0_OFFSET 0x204000 | ||
75 | #define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */ | ||
76 | +#define OTP_OFFSET 0x20f000 | ||
77 | +#define BSC_SL_OFFSET 0x214000 /* SPI slave */ | ||
78 | #define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */ | ||
79 | #define EMMC1_OFFSET 0x300000 | ||
80 | #define SMI_OFFSET 0x600000 | ||
81 | #define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */ | ||
82 | +#define BSC2_OFFSET 0x805000 /* BSC2 I2C/TWI */ | ||
83 | +#define DBUS_OFFSET 0x900000 | ||
84 | +#define AVE0_OFFSET 0x910000 | ||
85 | #define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */ | ||
86 | +#define SDRAMC_OFFSET 0xe00000 | ||
87 | #define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */ | ||
88 | |||
89 | /* GPU interrupts */ | ||
90 | diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c | ||
91 | index XXXXXXX..XXXXXXX 100644 | ||
92 | --- a/hw/arm/bcm2835_peripherals.c | ||
93 | +++ b/hw/arm/bcm2835_peripherals.c | ||
94 | @@ -XXX,XX +XXX,XX @@ | ||
95 | /* Capabilities for SD controller: no DMA, high-speed, default clocks etc. */ | ||
96 | #define BCM2835_SDHC_CAPAREG 0x52134b4 | ||
97 | |||
98 | +static void create_unimp(BCM2835PeripheralState *ps, | ||
99 | + UnimplementedDeviceState *uds, | ||
100 | + const char *name, hwaddr ofs, hwaddr size) | ||
101 | +{ | ||
102 | + sysbus_init_child_obj(OBJECT(ps), name, uds, | ||
103 | + sizeof(UnimplementedDeviceState), | ||
104 | + TYPE_UNIMPLEMENTED_DEVICE); | ||
105 | + qdev_prop_set_string(DEVICE(uds), "name", name); | ||
106 | + qdev_prop_set_uint64(DEVICE(uds), "size", size); | ||
107 | + object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal); | ||
108 | + memory_region_add_subregion_overlap(&ps->peri_mr, ofs, | ||
109 | + sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0), -1000); | ||
110 | +} | ||
111 | + | 32 | + |
112 | static void bcm2835_peripherals_init(Object *obj) | 33 | u = cpu->isar.id_mmfr3; |
113 | { | 34 | u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ |
114 | BCM2835PeripheralState *s = BCM2835_PERIPHERALS(obj); | 35 | cpu->isar.id_mmfr3 = u; |
115 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) | ||
116 | error_propagate(errp, err); | ||
117 | return; | ||
118 | } | ||
119 | + | ||
120 | + create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40); | ||
121 | + create_unimp(s, &s->systmr, "bcm2835-systimer", ST_OFFSET, 0x20); | ||
122 | + create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000); | ||
123 | + create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000); | ||
124 | + create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100); | ||
125 | + create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100); | ||
126 | + create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20); | ||
127 | + create_unimp(s, &s->bscsl, "bcm2835-spis", BSC_SL_OFFSET, 0x100); | ||
128 | + create_unimp(s, &s->i2c[0], "bcm2835-i2c0", BSC0_OFFSET, 0x20); | ||
129 | + create_unimp(s, &s->i2c[1], "bcm2835-i2c1", BSC1_OFFSET, 0x20); | ||
130 | + create_unimp(s, &s->i2c[2], "bcm2835-i2c2", BSC2_OFFSET, 0x20); | ||
131 | + create_unimp(s, &s->otp, "bcm2835-otp", OTP_OFFSET, 0x80); | ||
132 | + create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000); | ||
133 | + create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000); | ||
134 | + create_unimp(s, &s->dwc2, "dwc-usb2", USB_OTG_OFFSET, 0x1000); | ||
135 | + create_unimp(s, &s->sdramc, "bcm2835-sdramc", SDRAMC_OFFSET, 0x100); | ||
136 | } | ||
137 | |||
138 | static void bcm2835_peripherals_class_init(ObjectClass *oc, void *data) | ||
139 | -- | 36 | -- |
140 | 2.20.1 | 37 | 2.20.1 |
141 | 38 | ||
142 | 39 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | From: Rebecca Cran <rebecca@nuviainc.com> |
---|---|---|---|
2 | 2 | ||
3 | Host kernels that expose the KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 capability | 3 | Enable FEAT_SSBS for the "max" 32-bit CPU. |
4 | allow injection of interrupts along with vcpu ids larger than 255. | ||
5 | Let's encode the vpcu id on 12 bits according to the upgraded KVM_IRQ_LINE | ||
6 | ABI when needed. | ||
7 | 4 | ||
8 | Given that we have two callsites that need to assemble | 5 | Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> |
9 | the value for kvm_set_irq(), a new helper routine, kvm_arm_set_irq | ||
10 | is introduced. | ||
11 | |||
12 | Without that patch qemu exits with "kvm_set_irq: Invalid argument" | ||
13 | message. | ||
14 | |||
15 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
16 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> | ||
17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
18 | Reviewed-by: Andrew Jones <drjones@redhat.com> | 7 | Message-id: 20210216224543.16142-4-rebecca@nuviainc.com |
19 | Acked-by: Marc Zyngier <maz@kernel.org> | 8 | [PMM: fix typo causing compilation failure] |
20 | Message-id: 20191003154640.22451-3-eric.auger@redhat.com | ||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
22 | --- | 10 | --- |
23 | target/arm/kvm_arm.h | 1 + | 11 | target/arm/cpu.c | 4 ++++ |
24 | hw/intc/arm_gic_kvm.c | 7 ++----- | 12 | 1 file changed, 4 insertions(+) |
25 | target/arm/cpu.c | 10 ++++------ | ||
26 | target/arm/kvm.c | 12 ++++++++++++ | ||
27 | 4 files changed, 19 insertions(+), 11 deletions(-) | ||
28 | 13 | ||
29 | diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/kvm_arm.h | ||
32 | +++ b/target/arm/kvm_arm.h | ||
33 | @@ -XXX,XX +XXX,XX @@ int kvm_arm_vgic_probe(void); | ||
34 | |||
35 | void kvm_arm_pmu_set_irq(CPUState *cs, int irq); | ||
36 | void kvm_arm_pmu_init(CPUState *cs); | ||
37 | +int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); | ||
38 | |||
39 | #else | ||
40 | |||
41 | diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/hw/intc/arm_gic_kvm.c | ||
44 | +++ b/hw/intc/arm_gic_kvm.c | ||
45 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_gic_set_irq(uint32_t num_irq, int irq, int level) | ||
46 | * has separate fields in the irq number for type, | ||
47 | * CPU number and interrupt number. | ||
48 | */ | ||
49 | - int kvm_irq, irqtype, cpu; | ||
50 | + int irqtype, cpu; | ||
51 | |||
52 | if (irq < (num_irq - GIC_INTERNAL)) { | ||
53 | /* External interrupt. The kernel numbers these like the GIC | ||
54 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_gic_set_irq(uint32_t num_irq, int irq, int level) | ||
55 | cpu = irq / GIC_INTERNAL; | ||
56 | irq %= GIC_INTERNAL; | ||
57 | } | ||
58 | - kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT) | ||
59 | - | (cpu << KVM_ARM_IRQ_VCPU_SHIFT) | irq; | ||
60 | - | ||
61 | - kvm_set_irq(kvm_state, kvm_irq, !!level); | ||
62 | + kvm_arm_set_irq(cpu, irqtype, irq, !!level); | ||
63 | } | ||
64 | |||
65 | static void kvm_arm_gicv2_set_irq(void *opaque, int irq, int level) | ||
66 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
67 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
68 | --- a/target/arm/cpu.c | 16 | --- a/target/arm/cpu.c |
69 | +++ b/target/arm/cpu.c | 17 | +++ b/target/arm/cpu.c |
70 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) | 18 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) |
71 | ARMCPU *cpu = opaque; | 19 | t = cpu->isar.id_pfr0; |
72 | CPUARMState *env = &cpu->env; | 20 | t = FIELD_DP32(t, ID_PFR0, DIT, 1); |
73 | CPUState *cs = CPU(cpu); | 21 | cpu->isar.id_pfr0 = t; |
74 | - int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; | 22 | + |
75 | uint32_t linestate_bit; | 23 | + t = cpu->isar.id_pfr2; |
76 | + int irq_id; | 24 | + t = FIELD_DP32(t, ID_PFR2, SSBS, 1); |
77 | 25 | + cpu->isar.id_pfr2 = t; | |
78 | switch (irq) { | ||
79 | case ARM_CPU_IRQ: | ||
80 | - kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; | ||
81 | + irq_id = KVM_ARM_IRQ_CPU_IRQ; | ||
82 | linestate_bit = CPU_INTERRUPT_HARD; | ||
83 | break; | ||
84 | case ARM_CPU_FIQ: | ||
85 | - kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; | ||
86 | + irq_id = KVM_ARM_IRQ_CPU_FIQ; | ||
87 | linestate_bit = CPU_INTERRUPT_FIQ; | ||
88 | break; | ||
89 | default: | ||
90 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) | ||
91 | } else { | ||
92 | env->irq_line_state &= ~linestate_bit; | ||
93 | } | 26 | } |
94 | - | ||
95 | - kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; | ||
96 | - kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); | ||
97 | + kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); | ||
98 | #endif | 27 | #endif |
99 | } | 28 | } |
100 | |||
101 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c | ||
102 | index XXXXXXX..XXXXXXX 100644 | ||
103 | --- a/target/arm/kvm.c | ||
104 | +++ b/target/arm/kvm.c | ||
105 | @@ -XXX,XX +XXX,XX @@ int kvm_arm_vgic_probe(void) | ||
106 | } | ||
107 | } | ||
108 | |||
109 | +int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level) | ||
110 | +{ | ||
111 | + int kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT) | irq; | ||
112 | + int cpu_idx1 = cpu % 256; | ||
113 | + int cpu_idx2 = cpu / 256; | ||
114 | + | ||
115 | + kvm_irq |= (cpu_idx1 << KVM_ARM_IRQ_VCPU_SHIFT) | | ||
116 | + (cpu_idx2 << KVM_ARM_IRQ_VCPU2_SHIFT); | ||
117 | + | ||
118 | + return kvm_set_irq(kvm_state, kvm_irq, !!level); | ||
119 | +} | ||
120 | + | ||
121 | int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, | ||
122 | uint64_t address, uint32_t data, PCIDevice *dev) | ||
123 | { | ||
124 | -- | 29 | -- |
125 | 2.20.1 | 30 | 2.20.1 |
126 | 31 | ||
127 | 32 | diff view generated by jsdifflib |
1 | From: Eddie James <eajames@linux.ibm.com> | 1 | From: Doug Evans <dje@google.com> |
---|---|---|---|
2 | 2 | ||
3 | The Aspeed SOCs have two SD/MMC controllers. Add a device that | 3 | This is a 10/100 ethernet device that has several features. |
4 | encapsulates both of these controllers and models the Aspeed-specific | 4 | Only the ones needed by the Linux driver have been implemented. |
5 | registers and behavior. | 5 | See npcm7xx_emc.c for a list of unimplemented features. |
6 | 6 | ||
7 | Tested by reading from mmcblk0 in Linux: | 7 | Reviewed-by: Hao Wu <wuhaotsh@google.com> |
8 | qemu-system-arm -machine romulus-bmc -nographic \ | 8 | Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com> |
9 | -drive file=flash-romulus,format=raw,if=mtd \ | 9 | Signed-off-by: Doug Evans <dje@google.com> |
10 | -device sd-card,drive=sd0 -drive file=_tmp/kernel,format=raw,if=sd,id=sd0 | 10 | Message-id: 20210218212453.831406-2-dje@google.com |
11 | |||
12 | Signed-off-by: Eddie James <eajames@linux.ibm.com> | ||
13 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
14 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
15 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
16 | Message-id: 20190925143248.10000-3-clg@kaod.org | ||
17 | [clg: - changed the controller MMIO window size to 0x1000 | ||
18 | - moved the MMIO mapping of the SDHCI slots at the SoC level | ||
19 | - merged code to add SD drives on the SD buses at the machine level ] | ||
20 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
22 | --- | 12 | --- |
23 | hw/sd/Makefile.objs | 1 + | 13 | include/hw/net/npcm7xx_emc.h | 286 ++++++++++++ |
24 | include/hw/arm/aspeed_soc.h | 3 + | 14 | hw/net/npcm7xx_emc.c | 857 +++++++++++++++++++++++++++++++++++ |
25 | include/hw/sd/aspeed_sdhci.h | 34 ++++++ | 15 | hw/net/meson.build | 1 + |
26 | hw/arm/aspeed.c | 15 ++- | 16 | hw/net/trace-events | 17 + |
27 | hw/arm/aspeed_soc.c | 23 ++++ | 17 | 4 files changed, 1161 insertions(+) |
28 | hw/sd/aspeed_sdhci.c | 198 +++++++++++++++++++++++++++++++++++ | 18 | create mode 100644 include/hw/net/npcm7xx_emc.h |
29 | 6 files changed, 273 insertions(+), 1 deletion(-) | 19 | create mode 100644 hw/net/npcm7xx_emc.c |
30 | create mode 100644 include/hw/sd/aspeed_sdhci.h | ||
31 | create mode 100644 hw/sd/aspeed_sdhci.c | ||
32 | 20 | ||
33 | diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs | 21 | diff --git a/include/hw/net/npcm7xx_emc.h b/include/hw/net/npcm7xx_emc.h |
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/hw/sd/Makefile.objs | ||
36 | +++ b/hw/sd/Makefile.objs | ||
37 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MILKYMIST) += milkymist-memcard.o | ||
38 | obj-$(CONFIG_OMAP) += omap_mmc.o | ||
39 | obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o | ||
40 | obj-$(CONFIG_RASPI) += bcm2835_sdhost.o | ||
41 | +obj-$(CONFIG_ASPEED_SOC) += aspeed_sdhci.o | ||
42 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/include/hw/arm/aspeed_soc.h | ||
45 | +++ b/include/hw/arm/aspeed_soc.h | ||
46 | @@ -XXX,XX +XXX,XX @@ | ||
47 | #include "hw/net/ftgmac100.h" | ||
48 | #include "target/arm/cpu.h" | ||
49 | #include "hw/gpio/aspeed_gpio.h" | ||
50 | +#include "hw/sd/aspeed_sdhci.h" | ||
51 | |||
52 | #define ASPEED_SPIS_NUM 2 | ||
53 | #define ASPEED_WDTS_NUM 3 | ||
54 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState { | ||
55 | AspeedWDTState wdt[ASPEED_WDTS_NUM]; | ||
56 | FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; | ||
57 | AspeedGPIOState gpio; | ||
58 | + AspeedSDHCIState sdhci; | ||
59 | } AspeedSoCState; | ||
60 | |||
61 | #define TYPE_ASPEED_SOC "aspeed-soc" | ||
62 | @@ -XXX,XX +XXX,XX @@ enum { | ||
63 | ASPEED_SCU, | ||
64 | ASPEED_ADC, | ||
65 | ASPEED_SRAM, | ||
66 | + ASPEED_SDHCI, | ||
67 | ASPEED_GPIO, | ||
68 | ASPEED_RTC, | ||
69 | ASPEED_TIMER1, | ||
70 | diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h | ||
71 | new file mode 100644 | 22 | new file mode 100644 |
72 | index XXXXXXX..XXXXXXX | 23 | index XXXXXXX..XXXXXXX |
73 | --- /dev/null | 24 | --- /dev/null |
74 | +++ b/include/hw/sd/aspeed_sdhci.h | 25 | +++ b/include/hw/net/npcm7xx_emc.h |
75 | @@ -XXX,XX +XXX,XX @@ | 26 | @@ -XXX,XX +XXX,XX @@ |
76 | +/* | 27 | +/* |
77 | + * Aspeed SD Host Controller | 28 | + * Nuvoton NPCM7xx EMC Module |
78 | + * Eddie James <eajames@linux.ibm.com> | ||
79 | + * | 29 | + * |
80 | + * Copyright (C) 2019 IBM Corp | 30 | + * Copyright 2020 Google LLC |
81 | + * SPDX-License-Identifer: GPL-2.0-or-later | 31 | + * |
32 | + * This program is free software; you can redistribute it and/or modify it | ||
33 | + * under the terms of the GNU General Public License as published by the | ||
34 | + * Free Software Foundation; either version 2 of the License, or | ||
35 | + * (at your option) any later version. | ||
36 | + * | ||
37 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
38 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
39 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
40 | + * for more details. | ||
82 | + */ | 41 | + */ |
83 | + | 42 | + |
84 | +#ifndef ASPEED_SDHCI_H | 43 | +#ifndef NPCM7XX_EMC_H |
85 | +#define ASPEED_SDHCI_H | 44 | +#define NPCM7XX_EMC_H |
86 | + | 45 | + |
87 | +#include "hw/sd/sdhci.h" | 46 | +#include "hw/irq.h" |
88 | + | 47 | +#include "hw/sysbus.h" |
89 | +#define TYPE_ASPEED_SDHCI "aspeed.sdhci" | 48 | +#include "net/net.h" |
90 | +#define ASPEED_SDHCI(obj) OBJECT_CHECK(AspeedSDHCIState, (obj), \ | 49 | + |
91 | + TYPE_ASPEED_SDHCI) | 50 | +/* 32-bit register indices. */ |
92 | + | 51 | +enum NPCM7xxPWMRegister { |
93 | +#define ASPEED_SDHCI_CAPABILITIES 0x01E80080 | 52 | + /* Control registers. */ |
94 | +#define ASPEED_SDHCI_NUM_SLOTS 2 | 53 | + REG_CAMCMR, |
95 | +#define ASPEED_SDHCI_NUM_REGS (ASPEED_SDHCI_REG_SIZE / sizeof(uint32_t)) | 54 | + REG_CAMEN, |
96 | +#define ASPEED_SDHCI_REG_SIZE 0x100 | 55 | + |
97 | + | 56 | + /* There are 16 CAMn[ML] registers. */ |
98 | +typedef struct AspeedSDHCIState { | 57 | + REG_CAMM_BASE, |
58 | + REG_CAML_BASE, | ||
59 | + REG_CAMML_LAST = 0x21, | ||
60 | + | ||
61 | + REG_TXDLSA = 0x22, | ||
62 | + REG_RXDLSA, | ||
63 | + REG_MCMDR, | ||
64 | + REG_MIID, | ||
65 | + REG_MIIDA, | ||
66 | + REG_FFTCR, | ||
67 | + REG_TSDR, | ||
68 | + REG_RSDR, | ||
69 | + REG_DMARFC, | ||
70 | + REG_MIEN, | ||
71 | + | ||
72 | + /* Status registers. */ | ||
73 | + REG_MISTA, | ||
74 | + REG_MGSTA, | ||
75 | + REG_MPCNT, | ||
76 | + REG_MRPC, | ||
77 | + REG_MRPCC, | ||
78 | + REG_MREPC, | ||
79 | + REG_DMARFS, | ||
80 | + REG_CTXDSA, | ||
81 | + REG_CTXBSA, | ||
82 | + REG_CRXDSA, | ||
83 | + REG_CRXBSA, | ||
84 | + | ||
85 | + NPCM7XX_NUM_EMC_REGS, | ||
86 | +}; | ||
87 | + | ||
88 | +/* REG_CAMCMR fields */ | ||
89 | +/* Enable CAM Compare */ | ||
90 | +#define REG_CAMCMR_ECMP (1 << 4) | ||
91 | +/* Complement CAM Compare */ | ||
92 | +#define REG_CAMCMR_CCAM (1 << 3) | ||
93 | +/* Accept Broadcast Packet */ | ||
94 | +#define REG_CAMCMR_ABP (1 << 2) | ||
95 | +/* Accept Multicast Packet */ | ||
96 | +#define REG_CAMCMR_AMP (1 << 1) | ||
97 | +/* Accept Unicast Packet */ | ||
98 | +#define REG_CAMCMR_AUP (1 << 0) | ||
99 | + | ||
100 | +/* REG_MCMDR fields */ | ||
101 | +/* Software Reset */ | ||
102 | +#define REG_MCMDR_SWR (1 << 24) | ||
103 | +/* Internal Loopback Select */ | ||
104 | +#define REG_MCMDR_LBK (1 << 21) | ||
105 | +/* Operation Mode Select */ | ||
106 | +#define REG_MCMDR_OPMOD (1 << 20) | ||
107 | +/* Enable MDC Clock Generation */ | ||
108 | +#define REG_MCMDR_ENMDC (1 << 19) | ||
109 | +/* Full-Duplex Mode Select */ | ||
110 | +#define REG_MCMDR_FDUP (1 << 18) | ||
111 | +/* Enable SQE Checking */ | ||
112 | +#define REG_MCMDR_ENSEQ (1 << 17) | ||
113 | +/* Send PAUSE Frame */ | ||
114 | +#define REG_MCMDR_SDPZ (1 << 16) | ||
115 | +/* No Defer */ | ||
116 | +#define REG_MCMDR_NDEF (1 << 9) | ||
117 | +/* Frame Transmission On */ | ||
118 | +#define REG_MCMDR_TXON (1 << 8) | ||
119 | +/* Strip CRC Checksum */ | ||
120 | +#define REG_MCMDR_SPCRC (1 << 5) | ||
121 | +/* Accept CRC Error Packet */ | ||
122 | +#define REG_MCMDR_AEP (1 << 4) | ||
123 | +/* Accept Control Packet */ | ||
124 | +#define REG_MCMDR_ACP (1 << 3) | ||
125 | +/* Accept Runt Packet */ | ||
126 | +#define REG_MCMDR_ARP (1 << 2) | ||
127 | +/* Accept Long Packet */ | ||
128 | +#define REG_MCMDR_ALP (1 << 1) | ||
129 | +/* Frame Reception On */ | ||
130 | +#define REG_MCMDR_RXON (1 << 0) | ||
131 | + | ||
132 | +/* REG_MIEN fields */ | ||
133 | +/* Enable Transmit Descriptor Unavailable Interrupt */ | ||
134 | +#define REG_MIEN_ENTDU (1 << 23) | ||
135 | +/* Enable Transmit Completion Interrupt */ | ||
136 | +#define REG_MIEN_ENTXCP (1 << 18) | ||
137 | +/* Enable Transmit Interrupt */ | ||
138 | +#define REG_MIEN_ENTXINTR (1 << 16) | ||
139 | +/* Enable Receive Descriptor Unavailable Interrupt */ | ||
140 | +#define REG_MIEN_ENRDU (1 << 10) | ||
141 | +/* Enable Receive Good Interrupt */ | ||
142 | +#define REG_MIEN_ENRXGD (1 << 4) | ||
143 | +/* Enable Receive Interrupt */ | ||
144 | +#define REG_MIEN_ENRXINTR (1 << 0) | ||
145 | + | ||
146 | +/* REG_MISTA fields */ | ||
147 | +/* TODO: Add error fields and support simulated errors? */ | ||
148 | +/* Transmit Bus Error Interrupt */ | ||
149 | +#define REG_MISTA_TXBERR (1 << 24) | ||
150 | +/* Transmit Descriptor Unavailable Interrupt */ | ||
151 | +#define REG_MISTA_TDU (1 << 23) | ||
152 | +/* Transmit Completion Interrupt */ | ||
153 | +#define REG_MISTA_TXCP (1 << 18) | ||
154 | +/* Transmit Interrupt */ | ||
155 | +#define REG_MISTA_TXINTR (1 << 16) | ||
156 | +/* Receive Bus Error Interrupt */ | ||
157 | +#define REG_MISTA_RXBERR (1 << 11) | ||
158 | +/* Receive Descriptor Unavailable Interrupt */ | ||
159 | +#define REG_MISTA_RDU (1 << 10) | ||
160 | +/* DMA Early Notification Interrupt */ | ||
161 | +#define REG_MISTA_DENI (1 << 9) | ||
162 | +/* Maximum Frame Length Interrupt */ | ||
163 | +#define REG_MISTA_DFOI (1 << 8) | ||
164 | +/* Receive Good Interrupt */ | ||
165 | +#define REG_MISTA_RXGD (1 << 4) | ||
166 | +/* Packet Too Long Interrupt */ | ||
167 | +#define REG_MISTA_PTLE (1 << 3) | ||
168 | +/* Receive Interrupt */ | ||
169 | +#define REG_MISTA_RXINTR (1 << 0) | ||
170 | + | ||
171 | +/* REG_MGSTA fields */ | ||
172 | +/* Transmission Halted */ | ||
173 | +#define REG_MGSTA_TXHA (1 << 11) | ||
174 | +/* Receive Halted */ | ||
175 | +#define REG_MGSTA_RXHA (1 << 11) | ||
176 | + | ||
177 | +/* REG_DMARFC fields */ | ||
178 | +/* Maximum Receive Frame Length */ | ||
179 | +#define REG_DMARFC_RXMS(word) extract32((word), 0, 16) | ||
180 | + | ||
181 | +/* REG MIIDA fields */ | ||
182 | +/* Busy Bit */ | ||
183 | +#define REG_MIIDA_BUSY (1 << 17) | ||
184 | + | ||
185 | +/* Transmit and receive descriptors */ | ||
186 | +typedef struct NPCM7xxEMCTxDesc NPCM7xxEMCTxDesc; | ||
187 | +typedef struct NPCM7xxEMCRxDesc NPCM7xxEMCRxDesc; | ||
188 | + | ||
189 | +struct NPCM7xxEMCTxDesc { | ||
190 | + uint32_t flags; | ||
191 | + uint32_t txbsa; | ||
192 | + uint32_t status_and_length; | ||
193 | + uint32_t ntxdsa; | ||
194 | +}; | ||
195 | + | ||
196 | +struct NPCM7xxEMCRxDesc { | ||
197 | + uint32_t status_and_length; | ||
198 | + uint32_t rxbsa; | ||
199 | + uint32_t reserved; | ||
200 | + uint32_t nrxdsa; | ||
201 | +}; | ||
202 | + | ||
203 | +/* NPCM7xxEMCTxDesc.flags values */ | ||
204 | +/* Owner: 0 = cpu, 1 = emc */ | ||
205 | +#define TX_DESC_FLAG_OWNER_MASK (1 << 31) | ||
206 | +/* Transmit interrupt enable */ | ||
207 | +#define TX_DESC_FLAG_INTEN (1 << 2) | ||
208 | +/* CRC append */ | ||
209 | +#define TX_DESC_FLAG_CRCAPP (1 << 1) | ||
210 | +/* Padding enable */ | ||
211 | +#define TX_DESC_FLAG_PADEN (1 << 0) | ||
212 | + | ||
213 | +/* NPCM7xxEMCTxDesc.status_and_length values */ | ||
214 | +/* Collision count */ | ||
215 | +#define TX_DESC_STATUS_CCNT_SHIFT 28 | ||
216 | +#define TX_DESC_STATUS_CCNT_BITSIZE 4 | ||
217 | +/* SQE error */ | ||
218 | +#define TX_DESC_STATUS_SQE (1 << 26) | ||
219 | +/* Transmission paused */ | ||
220 | +#define TX_DESC_STATUS_PAU (1 << 25) | ||
221 | +/* P transmission halted */ | ||
222 | +#define TX_DESC_STATUS_TXHA (1 << 24) | ||
223 | +/* Late collision */ | ||
224 | +#define TX_DESC_STATUS_LC (1 << 23) | ||
225 | +/* Transmission abort */ | ||
226 | +#define TX_DESC_STATUS_TXABT (1 << 22) | ||
227 | +/* No carrier sense */ | ||
228 | +#define TX_DESC_STATUS_NCS (1 << 21) | ||
229 | +/* Defer exceed */ | ||
230 | +#define TX_DESC_STATUS_EXDEF (1 << 20) | ||
231 | +/* Transmission complete */ | ||
232 | +#define TX_DESC_STATUS_TXCP (1 << 19) | ||
233 | +/* Transmission deferred */ | ||
234 | +#define TX_DESC_STATUS_DEF (1 << 17) | ||
235 | +/* Transmit interrupt */ | ||
236 | +#define TX_DESC_STATUS_TXINTR (1 << 16) | ||
237 | + | ||
238 | +#define TX_DESC_PKT_LEN(word) extract32((word), 0, 16) | ||
239 | + | ||
240 | +/* Transmit buffer start address */ | ||
241 | +#define TX_DESC_TXBSA(word) ((uint32_t) (word) & ~3u) | ||
242 | + | ||
243 | +/* Next transmit descriptor start address */ | ||
244 | +#define TX_DESC_NTXDSA(word) ((uint32_t) (word) & ~3u) | ||
245 | + | ||
246 | +/* NPCM7xxEMCRxDesc.status_and_length values */ | ||
247 | +/* Owner: 0b00 = cpu, 0b01 = undefined, 0b10 = emc, 0b11 = undefined */ | ||
248 | +#define RX_DESC_STATUS_OWNER_SHIFT 30 | ||
249 | +#define RX_DESC_STATUS_OWNER_BITSIZE 2 | ||
250 | +#define RX_DESC_STATUS_OWNER_MASK (3 << RX_DESC_STATUS_OWNER_SHIFT) | ||
251 | +/* Runt packet */ | ||
252 | +#define RX_DESC_STATUS_RP (1 << 22) | ||
253 | +/* Alignment error */ | ||
254 | +#define RX_DESC_STATUS_ALIE (1 << 21) | ||
255 | +/* Frame reception complete */ | ||
256 | +#define RX_DESC_STATUS_RXGD (1 << 20) | ||
257 | +/* Packet too long */ | ||
258 | +#define RX_DESC_STATUS_PTLE (1 << 19) | ||
259 | +/* CRC error */ | ||
260 | +#define RX_DESC_STATUS_CRCE (1 << 17) | ||
261 | +/* Receive interrupt */ | ||
262 | +#define RX_DESC_STATUS_RXINTR (1 << 16) | ||
263 | + | ||
264 | +#define RX_DESC_PKT_LEN(word) extract32((word), 0, 16) | ||
265 | + | ||
266 | +/* Receive buffer start address */ | ||
267 | +#define RX_DESC_RXBSA(word) ((uint32_t) (word) & ~3u) | ||
268 | + | ||
269 | +/* Next receive descriptor start address */ | ||
270 | +#define RX_DESC_NRXDSA(word) ((uint32_t) (word) & ~3u) | ||
271 | + | ||
272 | +/* Minimum packet length, when TX_DESC_FLAG_PADEN is set. */ | ||
273 | +#define MIN_PACKET_LENGTH 64 | ||
274 | + | ||
275 | +struct NPCM7xxEMCState { | ||
276 | + /*< private >*/ | ||
99 | + SysBusDevice parent; | 277 | + SysBusDevice parent; |
100 | + | 278 | + /*< public >*/ |
101 | + SDHCIState slots[ASPEED_SDHCI_NUM_SLOTS]; | ||
102 | + | 279 | + |
103 | + MemoryRegion iomem; | 280 | + MemoryRegion iomem; |
104 | + qemu_irq irq; | 281 | + |
105 | + | 282 | + qemu_irq tx_irq; |
106 | + uint32_t regs[ASPEED_SDHCI_NUM_REGS]; | 283 | + qemu_irq rx_irq; |
107 | +} AspeedSDHCIState; | 284 | + |
108 | + | 285 | + NICState *nic; |
109 | +#endif /* ASPEED_SDHCI_H */ | 286 | + NICConf conf; |
110 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | 287 | + |
111 | index XXXXXXX..XXXXXXX 100644 | 288 | + /* 0 or 1, for log messages */ |
112 | --- a/hw/arm/aspeed.c | 289 | + uint8_t emc_num; |
113 | +++ b/hw/arm/aspeed.c | 290 | + |
114 | @@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine, | 291 | + uint32_t regs[NPCM7XX_NUM_EMC_REGS]; |
115 | AspeedSoCClass *sc; | 292 | + |
116 | DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); | 293 | + /* |
117 | ram_addr_t max_ram_size; | 294 | + * tx is active. Set to true by TSDR and then switches off when out of |
118 | + int i; | 295 | + * descriptors. If the TXON bit in REG_MCMDR is off then this is off. |
119 | 296 | + */ | |
120 | bmc = g_new0(AspeedBoardState, 1); | 297 | + bool tx_active; |
121 | 298 | + | |
122 | @@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine, | 299 | + /* |
123 | cfg->i2c_init(bmc); | 300 | + * rx is active. Set to true by RSDR and then switches off when out of |
124 | } | 301 | + * descriptors. If the RXON bit in REG_MCMDR is off then this is off. |
125 | 302 | + */ | |
126 | + for (i = 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) { | 303 | + bool rx_active; |
127 | + SDHCIState *sdhci = &bmc->soc.sdhci.slots[i]; | 304 | +}; |
128 | + DriveInfo *dinfo = drive_get_next(IF_SD); | 305 | + |
129 | + BlockBackend *blk; | 306 | +typedef struct NPCM7xxEMCState NPCM7xxEMCState; |
130 | + DeviceState *card; | 307 | + |
131 | + | 308 | +#define TYPE_NPCM7XX_EMC "npcm7xx-emc" |
132 | + blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; | 309 | +#define NPCM7XX_EMC(obj) \ |
133 | + card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), | 310 | + OBJECT_CHECK(NPCM7xxEMCState, (obj), TYPE_NPCM7XX_EMC) |
134 | + TYPE_SD_CARD); | 311 | + |
135 | + qdev_prop_set_drive(card, "drive", blk, &error_fatal); | 312 | +#endif /* NPCM7XX_EMC_H */ |
136 | + object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); | 313 | diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c |
137 | + } | ||
138 | + | ||
139 | arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); | ||
140 | } | ||
141 | |||
142 | @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data) | ||
143 | mc->desc = board->desc; | ||
144 | mc->init = aspeed_machine_init; | ||
145 | mc->max_cpus = ASPEED_CPUS_NUM; | ||
146 | - mc->no_sdcard = 1; | ||
147 | mc->no_floppy = 1; | ||
148 | mc->no_cdrom = 1; | ||
149 | mc->no_parallel = 1; | ||
150 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
151 | index XXXXXXX..XXXXXXX 100644 | ||
152 | --- a/hw/arm/aspeed_soc.c | ||
153 | +++ b/hw/arm/aspeed_soc.c | ||
154 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2400_memmap[] = { | ||
155 | [ASPEED_XDMA] = 0x1E6E7000, | ||
156 | [ASPEED_ADC] = 0x1E6E9000, | ||
157 | [ASPEED_SRAM] = 0x1E720000, | ||
158 | + [ASPEED_SDHCI] = 0x1E740000, | ||
159 | [ASPEED_GPIO] = 0x1E780000, | ||
160 | [ASPEED_RTC] = 0x1E781000, | ||
161 | [ASPEED_TIMER1] = 0x1E782000, | ||
162 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2500_memmap[] = { | ||
163 | [ASPEED_XDMA] = 0x1E6E7000, | ||
164 | [ASPEED_ADC] = 0x1E6E9000, | ||
165 | [ASPEED_SRAM] = 0x1E720000, | ||
166 | + [ASPEED_SDHCI] = 0x1E740000, | ||
167 | [ASPEED_GPIO] = 0x1E780000, | ||
168 | [ASPEED_RTC] = 0x1E781000, | ||
169 | [ASPEED_TIMER1] = 0x1E782000, | ||
170 | @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2400_irqmap[] = { | ||
171 | [ASPEED_ETH1] = 2, | ||
172 | [ASPEED_ETH2] = 3, | ||
173 | [ASPEED_XDMA] = 6, | ||
174 | + [ASPEED_SDHCI] = 26, | ||
175 | }; | ||
176 | |||
177 | #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap | ||
178 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | ||
179 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); | ||
180 | sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio), | ||
181 | typename); | ||
182 | + | ||
183 | + sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), | ||
184 | + TYPE_ASPEED_SDHCI); | ||
185 | + | ||
186 | + /* Init sd card slot class here so that they're under the correct parent */ | ||
187 | + for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | ||
188 | + sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), | ||
189 | + sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); | ||
190 | + } | ||
191 | } | ||
192 | |||
193 | static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
194 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
195 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->info->memmap[ASPEED_GPIO]); | ||
196 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, | ||
197 | aspeed_soc_get_irq(s, ASPEED_GPIO)); | ||
198 | + | ||
199 | + /* SDHCI */ | ||
200 | + object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err); | ||
201 | + if (err) { | ||
202 | + error_propagate(errp, err); | ||
203 | + return; | ||
204 | + } | ||
205 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, | ||
206 | + sc->info->memmap[ASPEED_SDHCI]); | ||
207 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, | ||
208 | + aspeed_soc_get_irq(s, ASPEED_SDHCI)); | ||
209 | } | ||
210 | static Property aspeed_soc_properties[] = { | ||
211 | DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0), | ||
212 | diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c | ||
213 | new file mode 100644 | 314 | new file mode 100644 |
214 | index XXXXXXX..XXXXXXX | 315 | index XXXXXXX..XXXXXXX |
215 | --- /dev/null | 316 | --- /dev/null |
216 | +++ b/hw/sd/aspeed_sdhci.c | 317 | +++ b/hw/net/npcm7xx_emc.c |
217 | @@ -XXX,XX +XXX,XX @@ | 318 | @@ -XXX,XX +XXX,XX @@ |
218 | +/* | 319 | +/* |
219 | + * Aspeed SD Host Controller | 320 | + * Nuvoton NPCM7xx EMC Module |
220 | + * Eddie James <eajames@linux.ibm.com> | ||
221 | + * | 321 | + * |
222 | + * Copyright (C) 2019 IBM Corp | 322 | + * Copyright 2020 Google LLC |
223 | + * SPDX-License-Identifer: GPL-2.0-or-later | 323 | + * |
324 | + * This program is free software; you can redistribute it and/or modify it | ||
325 | + * under the terms of the GNU General Public License as published by the | ||
326 | + * Free Software Foundation; either version 2 of the License, or | ||
327 | + * (at your option) any later version. | ||
328 | + * | ||
329 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
330 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
331 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
332 | + * for more details. | ||
333 | + * | ||
334 | + * Unsupported/unimplemented features: | ||
335 | + * - MCMDR.FDUP (full duplex) is ignored, half duplex is not supported | ||
336 | + * - Only CAM0 is supported, CAM[1-15] are not | ||
337 | + * - writes to CAMEN.[1-15] are ignored, these bits always read as zeroes | ||
338 | + * - MII is not implemented, MIIDA.BUSY and MIID always return zero | ||
339 | + * - MCMDR.LBK is not implemented | ||
340 | + * - MCMDR.{OPMOD,ENSQE,AEP,ARP} are not supported | ||
341 | + * - H/W FIFOs are not supported, MCMDR.FFTCR is ignored | ||
342 | + * - MGSTA.SQE is not supported | ||
343 | + * - pause and control frames are not implemented | ||
344 | + * - MGSTA.CCNT is not supported | ||
345 | + * - MPCNT, DMARFS are not implemented | ||
224 | + */ | 346 | + */ |
225 | + | 347 | + |
226 | +#include "qemu/osdep.h" | 348 | +#include "qemu/osdep.h" |
349 | + | ||
350 | +/* For crc32 */ | ||
351 | +#include <zlib.h> | ||
352 | + | ||
353 | +#include "qemu-common.h" | ||
354 | +#include "hw/irq.h" | ||
355 | +#include "hw/qdev-clock.h" | ||
356 | +#include "hw/qdev-properties.h" | ||
357 | +#include "hw/net/npcm7xx_emc.h" | ||
358 | +#include "net/eth.h" | ||
359 | +#include "migration/vmstate.h" | ||
360 | +#include "qemu/bitops.h" | ||
361 | +#include "qemu/error-report.h" | ||
227 | +#include "qemu/log.h" | 362 | +#include "qemu/log.h" |
228 | +#include "qemu/error-report.h" | 363 | +#include "qemu/module.h" |
229 | +#include "hw/sd/aspeed_sdhci.h" | 364 | +#include "qemu/units.h" |
230 | +#include "qapi/error.h" | 365 | +#include "sysemu/dma.h" |
231 | +#include "hw/irq.h" | 366 | +#include "trace.h" |
232 | +#include "migration/vmstate.h" | 367 | + |
233 | + | 368 | +#define CRC_LENGTH 4 |
234 | +#define ASPEED_SDHCI_INFO 0x00 | 369 | + |
235 | +#define ASPEED_SDHCI_INFO_RESET 0x00030000 | 370 | +/* |
236 | +#define ASPEED_SDHCI_DEBOUNCE 0x04 | 371 | + * The maximum size of a (layer 2) ethernet frame as defined by 802.3. |
237 | +#define ASPEED_SDHCI_DEBOUNCE_RESET 0x00000005 | 372 | + * 1518 = 6(dest macaddr) + 6(src macaddr) + 2(proto) + 4(crc) + 1500(payload) |
238 | +#define ASPEED_SDHCI_BUS 0x08 | 373 | + * This does not include an additional 4 for the vlan field (802.1q). |
239 | +#define ASPEED_SDHCI_SDIO_140 0x10 | 374 | + */ |
240 | +#define ASPEED_SDHCI_SDIO_148 0x18 | 375 | +#define MAX_ETH_FRAME_SIZE 1518 |
241 | +#define ASPEED_SDHCI_SDIO_240 0x20 | 376 | + |
242 | +#define ASPEED_SDHCI_SDIO_248 0x28 | 377 | +static const char *emc_reg_name(int regno) |
243 | +#define ASPEED_SDHCI_WP_POL 0xec | 378 | +{ |
244 | +#define ASPEED_SDHCI_CARD_DET 0xf0 | 379 | +#define REG(name) case REG_ ## name: return #name; |
245 | +#define ASPEED_SDHCI_IRQ_STAT 0xfc | 380 | + switch (regno) { |
246 | + | 381 | + REG(CAMCMR) |
247 | +#define TO_REG(addr) ((addr) / sizeof(uint32_t)) | 382 | + REG(CAMEN) |
248 | + | 383 | + REG(TXDLSA) |
249 | +static uint64_t aspeed_sdhci_read(void *opaque, hwaddr addr, unsigned int size) | 384 | + REG(RXDLSA) |
250 | +{ | 385 | + REG(MCMDR) |
251 | + uint32_t val = 0; | 386 | + REG(MIID) |
252 | + AspeedSDHCIState *sdhci = opaque; | 387 | + REG(MIIDA) |
253 | + | 388 | + REG(FFTCR) |
254 | + switch (addr) { | 389 | + REG(TSDR) |
255 | + case ASPEED_SDHCI_SDIO_140: | 390 | + REG(RSDR) |
256 | + val = (uint32_t)sdhci->slots[0].capareg; | 391 | + REG(DMARFC) |
257 | + break; | 392 | + REG(MIEN) |
258 | + case ASPEED_SDHCI_SDIO_148: | 393 | + REG(MISTA) |
259 | + val = (uint32_t)sdhci->slots[0].maxcurr; | 394 | + REG(MGSTA) |
260 | + break; | 395 | + REG(MPCNT) |
261 | + case ASPEED_SDHCI_SDIO_240: | 396 | + REG(MRPC) |
262 | + val = (uint32_t)sdhci->slots[1].capareg; | 397 | + REG(MRPCC) |
263 | + break; | 398 | + REG(MREPC) |
264 | + case ASPEED_SDHCI_SDIO_248: | 399 | + REG(DMARFS) |
265 | + val = (uint32_t)sdhci->slots[1].maxcurr; | 400 | + REG(CTXDSA) |
266 | + break; | 401 | + REG(CTXBSA) |
402 | + REG(CRXDSA) | ||
403 | + REG(CRXBSA) | ||
404 | + case REG_CAMM_BASE + 0: return "CAM0M"; | ||
405 | + case REG_CAML_BASE + 0: return "CAM0L"; | ||
406 | + case REG_CAMM_BASE + 2 ... REG_CAMML_LAST: | ||
407 | + /* Only CAM0 is supported, fold the others into something simple. */ | ||
408 | + if (regno & 1) { | ||
409 | + return "CAM<n>L"; | ||
410 | + } else { | ||
411 | + return "CAM<n>M"; | ||
412 | + } | ||
413 | + default: return "UNKNOWN"; | ||
414 | + } | ||
415 | +#undef REG | ||
416 | +} | ||
417 | + | ||
418 | +static void emc_reset(NPCM7xxEMCState *emc) | ||
419 | +{ | ||
420 | + trace_npcm7xx_emc_reset(emc->emc_num); | ||
421 | + | ||
422 | + memset(&emc->regs[0], 0, sizeof(emc->regs)); | ||
423 | + | ||
424 | + /* These regs have non-zero reset values. */ | ||
425 | + emc->regs[REG_TXDLSA] = 0xfffffffc; | ||
426 | + emc->regs[REG_RXDLSA] = 0xfffffffc; | ||
427 | + emc->regs[REG_MIIDA] = 0x00900000; | ||
428 | + emc->regs[REG_FFTCR] = 0x0101; | ||
429 | + emc->regs[REG_DMARFC] = 0x0800; | ||
430 | + emc->regs[REG_MPCNT] = 0x7fff; | ||
431 | + | ||
432 | + emc->tx_active = false; | ||
433 | + emc->rx_active = false; | ||
434 | +} | ||
435 | + | ||
436 | +static void npcm7xx_emc_reset(DeviceState *dev) | ||
437 | +{ | ||
438 | + NPCM7xxEMCState *emc = NPCM7XX_EMC(dev); | ||
439 | + emc_reset(emc); | ||
440 | +} | ||
441 | + | ||
442 | +static void emc_soft_reset(NPCM7xxEMCState *emc) | ||
443 | +{ | ||
444 | + /* | ||
445 | + * The docs say at least MCMDR.{LBK,OPMOD} bits are not changed during a | ||
446 | + * soft reset, but does not go into further detail. For now, KISS. | ||
447 | + */ | ||
448 | + uint32_t mcmdr = emc->regs[REG_MCMDR]; | ||
449 | + emc_reset(emc); | ||
450 | + emc->regs[REG_MCMDR] = mcmdr & (REG_MCMDR_LBK | REG_MCMDR_OPMOD); | ||
451 | + | ||
452 | + qemu_set_irq(emc->tx_irq, 0); | ||
453 | + qemu_set_irq(emc->rx_irq, 0); | ||
454 | +} | ||
455 | + | ||
456 | +static void emc_set_link(NetClientState *nc) | ||
457 | +{ | ||
458 | + /* Nothing to do yet. */ | ||
459 | +} | ||
460 | + | ||
461 | +/* MISTA.TXINTR is the union of the individual bits with their enables. */ | ||
462 | +static void emc_update_mista_txintr(NPCM7xxEMCState *emc) | ||
463 | +{ | ||
464 | + /* Only look at the bits we support. */ | ||
465 | + uint32_t mask = (REG_MISTA_TXBERR | | ||
466 | + REG_MISTA_TDU | | ||
467 | + REG_MISTA_TXCP); | ||
468 | + if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & mask) { | ||
469 | + emc->regs[REG_MISTA] |= REG_MISTA_TXINTR; | ||
470 | + } else { | ||
471 | + emc->regs[REG_MISTA] &= ~REG_MISTA_TXINTR; | ||
472 | + } | ||
473 | +} | ||
474 | + | ||
475 | +/* MISTA.RXINTR is the union of the individual bits with their enables. */ | ||
476 | +static void emc_update_mista_rxintr(NPCM7xxEMCState *emc) | ||
477 | +{ | ||
478 | + /* Only look at the bits we support. */ | ||
479 | + uint32_t mask = (REG_MISTA_RXBERR | | ||
480 | + REG_MISTA_RDU | | ||
481 | + REG_MISTA_RXGD); | ||
482 | + if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & mask) { | ||
483 | + emc->regs[REG_MISTA] |= REG_MISTA_RXINTR; | ||
484 | + } else { | ||
485 | + emc->regs[REG_MISTA] &= ~REG_MISTA_RXINTR; | ||
486 | + } | ||
487 | +} | ||
488 | + | ||
489 | +/* N.B. emc_update_mista_txintr must have already been called. */ | ||
490 | +static void emc_update_tx_irq(NPCM7xxEMCState *emc) | ||
491 | +{ | ||
492 | + int level = !!(emc->regs[REG_MISTA] & | ||
493 | + emc->regs[REG_MIEN] & | ||
494 | + REG_MISTA_TXINTR); | ||
495 | + trace_npcm7xx_emc_update_tx_irq(level); | ||
496 | + qemu_set_irq(emc->tx_irq, level); | ||
497 | +} | ||
498 | + | ||
499 | +/* N.B. emc_update_mista_rxintr must have already been called. */ | ||
500 | +static void emc_update_rx_irq(NPCM7xxEMCState *emc) | ||
501 | +{ | ||
502 | + int level = !!(emc->regs[REG_MISTA] & | ||
503 | + emc->regs[REG_MIEN] & | ||
504 | + REG_MISTA_RXINTR); | ||
505 | + trace_npcm7xx_emc_update_rx_irq(level); | ||
506 | + qemu_set_irq(emc->rx_irq, level); | ||
507 | +} | ||
508 | + | ||
509 | +/* Update IRQ states due to changes in MIEN,MISTA. */ | ||
510 | +static void emc_update_irq_from_reg_change(NPCM7xxEMCState *emc) | ||
511 | +{ | ||
512 | + emc_update_mista_txintr(emc); | ||
513 | + emc_update_tx_irq(emc); | ||
514 | + | ||
515 | + emc_update_mista_rxintr(emc); | ||
516 | + emc_update_rx_irq(emc); | ||
517 | +} | ||
518 | + | ||
519 | +static int emc_read_tx_desc(dma_addr_t addr, NPCM7xxEMCTxDesc *desc) | ||
520 | +{ | ||
521 | + if (dma_memory_read(&address_space_memory, addr, desc, sizeof(*desc))) { | ||
522 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x%" | ||
523 | + HWADDR_PRIx "\n", __func__, addr); | ||
524 | + return -1; | ||
525 | + } | ||
526 | + desc->flags = le32_to_cpu(desc->flags); | ||
527 | + desc->txbsa = le32_to_cpu(desc->txbsa); | ||
528 | + desc->status_and_length = le32_to_cpu(desc->status_and_length); | ||
529 | + desc->ntxdsa = le32_to_cpu(desc->ntxdsa); | ||
530 | + return 0; | ||
531 | +} | ||
532 | + | ||
533 | +static int emc_write_tx_desc(const NPCM7xxEMCTxDesc *desc, dma_addr_t addr) | ||
534 | +{ | ||
535 | + NPCM7xxEMCTxDesc le_desc; | ||
536 | + | ||
537 | + le_desc.flags = cpu_to_le32(desc->flags); | ||
538 | + le_desc.txbsa = cpu_to_le32(desc->txbsa); | ||
539 | + le_desc.status_and_length = cpu_to_le32(desc->status_and_length); | ||
540 | + le_desc.ntxdsa = cpu_to_le32(desc->ntxdsa); | ||
541 | + if (dma_memory_write(&address_space_memory, addr, &le_desc, | ||
542 | + sizeof(le_desc))) { | ||
543 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0x%" | ||
544 | + HWADDR_PRIx "\n", __func__, addr); | ||
545 | + return -1; | ||
546 | + } | ||
547 | + return 0; | ||
548 | +} | ||
549 | + | ||
550 | +static int emc_read_rx_desc(dma_addr_t addr, NPCM7xxEMCRxDesc *desc) | ||
551 | +{ | ||
552 | + if (dma_memory_read(&address_space_memory, addr, desc, sizeof(*desc))) { | ||
553 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x%" | ||
554 | + HWADDR_PRIx "\n", __func__, addr); | ||
555 | + return -1; | ||
556 | + } | ||
557 | + desc->status_and_length = le32_to_cpu(desc->status_and_length); | ||
558 | + desc->rxbsa = le32_to_cpu(desc->rxbsa); | ||
559 | + desc->reserved = le32_to_cpu(desc->reserved); | ||
560 | + desc->nrxdsa = le32_to_cpu(desc->nrxdsa); | ||
561 | + return 0; | ||
562 | +} | ||
563 | + | ||
564 | +static int emc_write_rx_desc(const NPCM7xxEMCRxDesc *desc, dma_addr_t addr) | ||
565 | +{ | ||
566 | + NPCM7xxEMCRxDesc le_desc; | ||
567 | + | ||
568 | + le_desc.status_and_length = cpu_to_le32(desc->status_and_length); | ||
569 | + le_desc.rxbsa = cpu_to_le32(desc->rxbsa); | ||
570 | + le_desc.reserved = cpu_to_le32(desc->reserved); | ||
571 | + le_desc.nrxdsa = cpu_to_le32(desc->nrxdsa); | ||
572 | + if (dma_memory_write(&address_space_memory, addr, &le_desc, | ||
573 | + sizeof(le_desc))) { | ||
574 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0x%" | ||
575 | + HWADDR_PRIx "\n", __func__, addr); | ||
576 | + return -1; | ||
577 | + } | ||
578 | + return 0; | ||
579 | +} | ||
580 | + | ||
581 | +static void emc_set_mista(NPCM7xxEMCState *emc, uint32_t flags) | ||
582 | +{ | ||
583 | + trace_npcm7xx_emc_set_mista(flags); | ||
584 | + emc->regs[REG_MISTA] |= flags; | ||
585 | + if (extract32(flags, 16, 16)) { | ||
586 | + emc_update_mista_txintr(emc); | ||
587 | + } | ||
588 | + if (extract32(flags, 0, 16)) { | ||
589 | + emc_update_mista_rxintr(emc); | ||
590 | + } | ||
591 | +} | ||
592 | + | ||
593 | +static void emc_halt_tx(NPCM7xxEMCState *emc, uint32_t mista_flag) | ||
594 | +{ | ||
595 | + emc->tx_active = false; | ||
596 | + emc_set_mista(emc, mista_flag); | ||
597 | +} | ||
598 | + | ||
599 | +static void emc_halt_rx(NPCM7xxEMCState *emc, uint32_t mista_flag) | ||
600 | +{ | ||
601 | + emc->rx_active = false; | ||
602 | + emc_set_mista(emc, mista_flag); | ||
603 | +} | ||
604 | + | ||
605 | +static void emc_set_next_tx_descriptor(NPCM7xxEMCState *emc, | ||
606 | + const NPCM7xxEMCTxDesc *tx_desc, | ||
607 | + uint32_t desc_addr) | ||
608 | +{ | ||
609 | + /* Update the current descriptor, if only to reset the owner flag. */ | ||
610 | + if (emc_write_tx_desc(tx_desc, desc_addr)) { | ||
611 | + /* | ||
612 | + * We just read it so this shouldn't generally happen. | ||
613 | + * Error already reported. | ||
614 | + */ | ||
615 | + emc_set_mista(emc, REG_MISTA_TXBERR); | ||
616 | + } | ||
617 | + emc->regs[REG_CTXDSA] = TX_DESC_NTXDSA(tx_desc->ntxdsa); | ||
618 | +} | ||
619 | + | ||
620 | +static void emc_set_next_rx_descriptor(NPCM7xxEMCState *emc, | ||
621 | + const NPCM7xxEMCRxDesc *rx_desc, | ||
622 | + uint32_t desc_addr) | ||
623 | +{ | ||
624 | + /* Update the current descriptor, if only to reset the owner flag. */ | ||
625 | + if (emc_write_rx_desc(rx_desc, desc_addr)) { | ||
626 | + /* | ||
627 | + * We just read it so this shouldn't generally happen. | ||
628 | + * Error already reported. | ||
629 | + */ | ||
630 | + emc_set_mista(emc, REG_MISTA_RXBERR); | ||
631 | + } | ||
632 | + emc->regs[REG_CRXDSA] = RX_DESC_NRXDSA(rx_desc->nrxdsa); | ||
633 | +} | ||
634 | + | ||
635 | +static void emc_try_send_next_packet(NPCM7xxEMCState *emc) | ||
636 | +{ | ||
637 | + /* Working buffer for sending out packets. Most packets fit in this. */ | ||
638 | +#define TX_BUFFER_SIZE 2048 | ||
639 | + uint8_t tx_send_buffer[TX_BUFFER_SIZE]; | ||
640 | + uint32_t desc_addr = TX_DESC_NTXDSA(emc->regs[REG_CTXDSA]); | ||
641 | + NPCM7xxEMCTxDesc tx_desc; | ||
642 | + uint32_t next_buf_addr, length; | ||
643 | + uint8_t *buf; | ||
644 | + g_autofree uint8_t *malloced_buf = NULL; | ||
645 | + | ||
646 | + if (emc_read_tx_desc(desc_addr, &tx_desc)) { | ||
647 | + /* Error reading descriptor, already reported. */ | ||
648 | + emc_halt_tx(emc, REG_MISTA_TXBERR); | ||
649 | + emc_update_tx_irq(emc); | ||
650 | + return; | ||
651 | + } | ||
652 | + | ||
653 | + /* Nothing we can do if we don't own the descriptor. */ | ||
654 | + if (!(tx_desc.flags & TX_DESC_FLAG_OWNER_MASK)) { | ||
655 | + trace_npcm7xx_emc_cpu_owned_desc(desc_addr); | ||
656 | + emc_halt_tx(emc, REG_MISTA_TDU); | ||
657 | + emc_update_tx_irq(emc); | ||
658 | + return; | ||
659 | + } | ||
660 | + | ||
661 | + /* Give the descriptor back regardless of what happens. */ | ||
662 | + tx_desc.flags &= ~TX_DESC_FLAG_OWNER_MASK; | ||
663 | + tx_desc.status_and_length &= 0xffff; | ||
664 | + | ||
665 | + /* | ||
666 | + * Despite the h/w documentation saying the tx buffer is word aligned, | ||
667 | + * the linux driver does not word align the buffer. There is value in not | ||
668 | + * aligning the buffer: See the description of NET_IP_ALIGN in linux | ||
669 | + * kernel sources. | ||
670 | + */ | ||
671 | + next_buf_addr = tx_desc.txbsa; | ||
672 | + emc->regs[REG_CTXBSA] = next_buf_addr; | ||
673 | + length = TX_DESC_PKT_LEN(tx_desc.status_and_length); | ||
674 | + buf = &tx_send_buffer[0]; | ||
675 | + | ||
676 | + if (length > sizeof(tx_send_buffer)) { | ||
677 | + malloced_buf = g_malloc(length); | ||
678 | + buf = malloced_buf; | ||
679 | + } | ||
680 | + | ||
681 | + if (dma_memory_read(&address_space_memory, next_buf_addr, buf, length)) { | ||
682 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read packet @ 0x%x\n", | ||
683 | + __func__, next_buf_addr); | ||
684 | + emc_set_mista(emc, REG_MISTA_TXBERR); | ||
685 | + emc_set_next_tx_descriptor(emc, &tx_desc, desc_addr); | ||
686 | + emc_update_tx_irq(emc); | ||
687 | + trace_npcm7xx_emc_tx_done(emc->regs[REG_CTXDSA]); | ||
688 | + return; | ||
689 | + } | ||
690 | + | ||
691 | + if ((tx_desc.flags & TX_DESC_FLAG_PADEN) && (length < MIN_PACKET_LENGTH)) { | ||
692 | + memset(buf + length, 0, MIN_PACKET_LENGTH - length); | ||
693 | + length = MIN_PACKET_LENGTH; | ||
694 | + } | ||
695 | + | ||
696 | + /* N.B. emc_receive can get called here. */ | ||
697 | + qemu_send_packet(qemu_get_queue(emc->nic), buf, length); | ||
698 | + trace_npcm7xx_emc_sent_packet(length); | ||
699 | + | ||
700 | + tx_desc.status_and_length |= TX_DESC_STATUS_TXCP; | ||
701 | + if (tx_desc.flags & TX_DESC_FLAG_INTEN) { | ||
702 | + emc_set_mista(emc, REG_MISTA_TXCP); | ||
703 | + } | ||
704 | + if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & REG_MISTA_TXINTR) { | ||
705 | + tx_desc.status_and_length |= TX_DESC_STATUS_TXINTR; | ||
706 | + } | ||
707 | + | ||
708 | + emc_set_next_tx_descriptor(emc, &tx_desc, desc_addr); | ||
709 | + emc_update_tx_irq(emc); | ||
710 | + trace_npcm7xx_emc_tx_done(emc->regs[REG_CTXDSA]); | ||
711 | +} | ||
712 | + | ||
713 | +static bool emc_can_receive(NetClientState *nc) | ||
714 | +{ | ||
715 | + NPCM7xxEMCState *emc = NPCM7XX_EMC(qemu_get_nic_opaque(nc)); | ||
716 | + | ||
717 | + bool can_receive = emc->rx_active; | ||
718 | + trace_npcm7xx_emc_can_receive(can_receive); | ||
719 | + return can_receive; | ||
720 | +} | ||
721 | + | ||
722 | +/* If result is false then *fail_reason contains the reason. */ | ||
723 | +static bool emc_receive_filter1(NPCM7xxEMCState *emc, const uint8_t *buf, | ||
724 | + size_t len, const char **fail_reason) | ||
725 | +{ | ||
726 | + eth_pkt_types_e pkt_type = get_eth_packet_type(PKT_GET_ETH_HDR(buf)); | ||
727 | + | ||
728 | + switch (pkt_type) { | ||
729 | + case ETH_PKT_BCAST: | ||
730 | + if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) { | ||
731 | + return true; | ||
732 | + } else { | ||
733 | + *fail_reason = "Broadcast packet disabled"; | ||
734 | + return !!(emc->regs[REG_CAMCMR] & REG_CAMCMR_ABP); | ||
735 | + } | ||
736 | + case ETH_PKT_MCAST: | ||
737 | + if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) { | ||
738 | + return true; | ||
739 | + } else { | ||
740 | + *fail_reason = "Multicast packet disabled"; | ||
741 | + return !!(emc->regs[REG_CAMCMR] & REG_CAMCMR_AMP); | ||
742 | + } | ||
743 | + case ETH_PKT_UCAST: { | ||
744 | + bool matches; | ||
745 | + if (emc->regs[REG_CAMCMR] & REG_CAMCMR_AUP) { | ||
746 | + return true; | ||
747 | + } | ||
748 | + matches = ((emc->regs[REG_CAMCMR] & REG_CAMCMR_ECMP) && | ||
749 | + /* We only support one CAM register, CAM0. */ | ||
750 | + (emc->regs[REG_CAMEN] & (1 << 0)) && | ||
751 | + memcmp(buf, emc->conf.macaddr.a, ETH_ALEN) == 0); | ||
752 | + if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) { | ||
753 | + *fail_reason = "MACADDR matched, comparison complemented"; | ||
754 | + return !matches; | ||
755 | + } else { | ||
756 | + *fail_reason = "MACADDR didn't match"; | ||
757 | + return matches; | ||
758 | + } | ||
759 | + } | ||
267 | + default: | 760 | + default: |
268 | + if (addr < ASPEED_SDHCI_REG_SIZE) { | 761 | + g_assert_not_reached(); |
269 | + val = sdhci->regs[TO_REG(addr)]; | 762 | + } |
763 | +} | ||
764 | + | ||
765 | +static bool emc_receive_filter(NPCM7xxEMCState *emc, const uint8_t *buf, | ||
766 | + size_t len) | ||
767 | +{ | ||
768 | + const char *fail_reason = NULL; | ||
769 | + bool ok = emc_receive_filter1(emc, buf, len, &fail_reason); | ||
770 | + if (!ok) { | ||
771 | + trace_npcm7xx_emc_packet_filtered_out(fail_reason); | ||
772 | + } | ||
773 | + return ok; | ||
774 | +} | ||
775 | + | ||
776 | +static ssize_t emc_receive(NetClientState *nc, const uint8_t *buf, size_t len1) | ||
777 | +{ | ||
778 | + NPCM7xxEMCState *emc = NPCM7XX_EMC(qemu_get_nic_opaque(nc)); | ||
779 | + const uint32_t len = len1; | ||
780 | + size_t max_frame_len; | ||
781 | + bool long_frame; | ||
782 | + uint32_t desc_addr; | ||
783 | + NPCM7xxEMCRxDesc rx_desc; | ||
784 | + uint32_t crc; | ||
785 | + uint8_t *crc_ptr; | ||
786 | + uint32_t buf_addr; | ||
787 | + | ||
788 | + trace_npcm7xx_emc_receiving_packet(len); | ||
789 | + | ||
790 | + if (!emc_can_receive(nc)) { | ||
791 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Unexpected packet\n", __func__); | ||
792 | + return -1; | ||
793 | + } | ||
794 | + | ||
795 | + if (len < ETH_HLEN || | ||
796 | + /* Defensive programming: drop unsupportable large packets. */ | ||
797 | + len > 0xffff - CRC_LENGTH) { | ||
798 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Dropped frame of %u bytes\n", | ||
799 | + __func__, len); | ||
800 | + return len; | ||
801 | + } | ||
802 | + | ||
803 | + /* | ||
804 | + * DENI is set if EMC received the Length/Type field of the incoming | ||
805 | + * packet, so it will be set regardless of what happens next. | ||
806 | + */ | ||
807 | + emc_set_mista(emc, REG_MISTA_DENI); | ||
808 | + | ||
809 | + if (!emc_receive_filter(emc, buf, len)) { | ||
810 | + emc_update_rx_irq(emc); | ||
811 | + return len; | ||
812 | + } | ||
813 | + | ||
814 | + /* Huge frames (> DMARFC) are dropped. */ | ||
815 | + max_frame_len = REG_DMARFC_RXMS(emc->regs[REG_DMARFC]); | ||
816 | + if (len + CRC_LENGTH > max_frame_len) { | ||
817 | + trace_npcm7xx_emc_packet_dropped(len); | ||
818 | + emc_set_mista(emc, REG_MISTA_DFOI); | ||
819 | + emc_update_rx_irq(emc); | ||
820 | + return len; | ||
821 | + } | ||
822 | + | ||
823 | + /* | ||
824 | + * Long Frames (> MAX_ETH_FRAME_SIZE) are also dropped, unless MCMDR.ALP | ||
825 | + * is set. | ||
826 | + */ | ||
827 | + long_frame = false; | ||
828 | + if (len + CRC_LENGTH > MAX_ETH_FRAME_SIZE) { | ||
829 | + if (emc->regs[REG_MCMDR] & REG_MCMDR_ALP) { | ||
830 | + long_frame = true; | ||
270 | + } else { | 831 | + } else { |
832 | + trace_npcm7xx_emc_packet_dropped(len); | ||
833 | + emc_set_mista(emc, REG_MISTA_PTLE); | ||
834 | + emc_update_rx_irq(emc); | ||
835 | + return len; | ||
836 | + } | ||
837 | + } | ||
838 | + | ||
839 | + desc_addr = RX_DESC_NRXDSA(emc->regs[REG_CRXDSA]); | ||
840 | + if (emc_read_rx_desc(desc_addr, &rx_desc)) { | ||
841 | + /* Error reading descriptor, already reported. */ | ||
842 | + emc_halt_rx(emc, REG_MISTA_RXBERR); | ||
843 | + emc_update_rx_irq(emc); | ||
844 | + return len; | ||
845 | + } | ||
846 | + | ||
847 | + /* Nothing we can do if we don't own the descriptor. */ | ||
848 | + if (!(rx_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK)) { | ||
849 | + trace_npcm7xx_emc_cpu_owned_desc(desc_addr); | ||
850 | + emc_halt_rx(emc, REG_MISTA_RDU); | ||
851 | + emc_update_rx_irq(emc); | ||
852 | + return len; | ||
853 | + } | ||
854 | + | ||
855 | + crc = 0; | ||
856 | + crc_ptr = (uint8_t *) &crc; | ||
857 | + if (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC)) { | ||
858 | + crc = cpu_to_be32(crc32(~0, buf, len)); | ||
859 | + } | ||
860 | + | ||
861 | + /* Give the descriptor back regardless of what happens. */ | ||
862 | + rx_desc.status_and_length &= ~RX_DESC_STATUS_OWNER_MASK; | ||
863 | + | ||
864 | + buf_addr = rx_desc.rxbsa; | ||
865 | + emc->regs[REG_CRXBSA] = buf_addr; | ||
866 | + if (dma_memory_write(&address_space_memory, buf_addr, buf, len) || | ||
867 | + (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC) && | ||
868 | + dma_memory_write(&address_space_memory, buf_addr + len, crc_ptr, | ||
869 | + 4))) { | ||
870 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bus error writing packet\n", | ||
871 | + __func__); | ||
872 | + emc_set_mista(emc, REG_MISTA_RXBERR); | ||
873 | + emc_set_next_rx_descriptor(emc, &rx_desc, desc_addr); | ||
874 | + emc_update_rx_irq(emc); | ||
875 | + trace_npcm7xx_emc_rx_done(emc->regs[REG_CRXDSA]); | ||
876 | + return len; | ||
877 | + } | ||
878 | + | ||
879 | + trace_npcm7xx_emc_received_packet(len); | ||
880 | + | ||
881 | + /* Note: We've already verified len+4 <= 0xffff. */ | ||
882 | + rx_desc.status_and_length = len; | ||
883 | + if (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC)) { | ||
884 | + rx_desc.status_and_length += 4; | ||
885 | + } | ||
886 | + rx_desc.status_and_length |= RX_DESC_STATUS_RXGD; | ||
887 | + emc_set_mista(emc, REG_MISTA_RXGD); | ||
888 | + | ||
889 | + if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & REG_MISTA_RXINTR) { | ||
890 | + rx_desc.status_and_length |= RX_DESC_STATUS_RXINTR; | ||
891 | + } | ||
892 | + if (long_frame) { | ||
893 | + rx_desc.status_and_length |= RX_DESC_STATUS_PTLE; | ||
894 | + } | ||
895 | + | ||
896 | + emc_set_next_rx_descriptor(emc, &rx_desc, desc_addr); | ||
897 | + emc_update_rx_irq(emc); | ||
898 | + trace_npcm7xx_emc_rx_done(emc->regs[REG_CRXDSA]); | ||
899 | + return len; | ||
900 | +} | ||
901 | + | ||
902 | +static void emc_try_receive_next_packet(NPCM7xxEMCState *emc) | ||
903 | +{ | ||
904 | + if (emc_can_receive(qemu_get_queue(emc->nic))) { | ||
905 | + qemu_flush_queued_packets(qemu_get_queue(emc->nic)); | ||
906 | + } | ||
907 | +} | ||
908 | + | ||
909 | +static uint64_t npcm7xx_emc_read(void *opaque, hwaddr offset, unsigned size) | ||
910 | +{ | ||
911 | + NPCM7xxEMCState *emc = opaque; | ||
912 | + uint32_t reg = offset / sizeof(uint32_t); | ||
913 | + uint32_t result; | ||
914 | + | ||
915 | + if (reg >= NPCM7XX_NUM_EMC_REGS) { | ||
916 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
917 | + "%s: Invalid offset 0x%04" HWADDR_PRIx "\n", | ||
918 | + __func__, offset); | ||
919 | + return 0; | ||
920 | + } | ||
921 | + | ||
922 | + switch (reg) { | ||
923 | + case REG_MIID: | ||
924 | + /* | ||
925 | + * We don't implement MII. For determinism, always return zero as | ||
926 | + * writes record the last value written for debugging purposes. | ||
927 | + */ | ||
928 | + qemu_log_mask(LOG_UNIMP, "%s: Read of MIID, returning 0\n", __func__); | ||
929 | + result = 0; | ||
930 | + break; | ||
931 | + case REG_TSDR: | ||
932 | + case REG_RSDR: | ||
933 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
934 | + "%s: Read of write-only reg, %s/%d\n", | ||
935 | + __func__, emc_reg_name(reg), reg); | ||
936 | + return 0; | ||
937 | + default: | ||
938 | + result = emc->regs[reg]; | ||
939 | + break; | ||
940 | + } | ||
941 | + | ||
942 | + trace_npcm7xx_emc_reg_read(emc->emc_num, result, emc_reg_name(reg), reg); | ||
943 | + return result; | ||
944 | +} | ||
945 | + | ||
946 | +static void npcm7xx_emc_write(void *opaque, hwaddr offset, | ||
947 | + uint64_t v, unsigned size) | ||
948 | +{ | ||
949 | + NPCM7xxEMCState *emc = opaque; | ||
950 | + uint32_t reg = offset / sizeof(uint32_t); | ||
951 | + uint32_t value = v; | ||
952 | + | ||
953 | + g_assert(size == sizeof(uint32_t)); | ||
954 | + | ||
955 | + if (reg >= NPCM7XX_NUM_EMC_REGS) { | ||
956 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
957 | + "%s: Invalid offset 0x%04" HWADDR_PRIx "\n", | ||
958 | + __func__, offset); | ||
959 | + return; | ||
960 | + } | ||
961 | + | ||
962 | + trace_npcm7xx_emc_reg_write(emc->emc_num, emc_reg_name(reg), reg, value); | ||
963 | + | ||
964 | + switch (reg) { | ||
965 | + case REG_CAMCMR: | ||
966 | + emc->regs[reg] = value; | ||
967 | + break; | ||
968 | + case REG_CAMEN: | ||
969 | + /* Only CAM0 is supported, don't pretend otherwise. */ | ||
970 | + if (value & ~1) { | ||
271 | + qemu_log_mask(LOG_GUEST_ERROR, | 971 | + qemu_log_mask(LOG_GUEST_ERROR, |
272 | + "%s: Out-of-bounds read at 0x%" HWADDR_PRIx "\n", | 972 | + "%s: Only CAM0 is supported, cannot enable others" |
273 | + __func__, addr); | 973 | + ": 0x%x\n", |
274 | + } | 974 | + __func__, value); |
275 | + } | 975 | + } |
276 | + | 976 | + emc->regs[reg] = value & 1; |
277 | + return (uint64_t)val; | 977 | + break; |
278 | +} | 978 | + case REG_CAMM_BASE + 0: |
279 | + | 979 | + emc->regs[reg] = value; |
280 | +static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val, | 980 | + emc->conf.macaddr.a[0] = value >> 24; |
281 | + unsigned int size) | 981 | + emc->conf.macaddr.a[1] = value >> 16; |
282 | +{ | 982 | + emc->conf.macaddr.a[2] = value >> 8; |
283 | + AspeedSDHCIState *sdhci = opaque; | 983 | + emc->conf.macaddr.a[3] = value >> 0; |
284 | + | 984 | + break; |
285 | + switch (addr) { | 985 | + case REG_CAML_BASE + 0: |
286 | + case ASPEED_SDHCI_SDIO_140: | 986 | + emc->regs[reg] = value; |
287 | + sdhci->slots[0].capareg = (uint64_t)(uint32_t)val; | 987 | + emc->conf.macaddr.a[4] = value >> 24; |
288 | + break; | 988 | + emc->conf.macaddr.a[5] = value >> 16; |
289 | + case ASPEED_SDHCI_SDIO_148: | 989 | + break; |
290 | + sdhci->slots[0].maxcurr = (uint64_t)(uint32_t)val; | 990 | + case REG_MCMDR: { |
291 | + break; | 991 | + uint32_t prev; |
292 | + case ASPEED_SDHCI_SDIO_240: | 992 | + if (value & REG_MCMDR_SWR) { |
293 | + sdhci->slots[1].capareg = (uint64_t)(uint32_t)val; | 993 | + emc_soft_reset(emc); |
294 | + break; | 994 | + /* On h/w the reset happens over multiple cycles. For now KISS. */ |
295 | + case ASPEED_SDHCI_SDIO_248: | 995 | + break; |
296 | + sdhci->slots[1].maxcurr = (uint64_t)(uint32_t)val; | 996 | + } |
997 | + prev = emc->regs[reg]; | ||
998 | + emc->regs[reg] = value; | ||
999 | + /* Update tx state. */ | ||
1000 | + if (!(prev & REG_MCMDR_TXON) && | ||
1001 | + (value & REG_MCMDR_TXON)) { | ||
1002 | + emc->regs[REG_CTXDSA] = emc->regs[REG_TXDLSA]; | ||
1003 | + /* | ||
1004 | + * Linux kernel turns TX on with CPU still holding descriptor, | ||
1005 | + * which suggests we should wait for a write to TSDR before trying | ||
1006 | + * to send a packet: so we don't send one here. | ||
1007 | + */ | ||
1008 | + } else if ((prev & REG_MCMDR_TXON) && | ||
1009 | + !(value & REG_MCMDR_TXON)) { | ||
1010 | + emc->regs[REG_MGSTA] |= REG_MGSTA_TXHA; | ||
1011 | + } | ||
1012 | + if (!(value & REG_MCMDR_TXON)) { | ||
1013 | + emc_halt_tx(emc, 0); | ||
1014 | + } | ||
1015 | + /* Update rx state. */ | ||
1016 | + if (!(prev & REG_MCMDR_RXON) && | ||
1017 | + (value & REG_MCMDR_RXON)) { | ||
1018 | + emc->regs[REG_CRXDSA] = emc->regs[REG_RXDLSA]; | ||
1019 | + } else if ((prev & REG_MCMDR_RXON) && | ||
1020 | + !(value & REG_MCMDR_RXON)) { | ||
1021 | + emc->regs[REG_MGSTA] |= REG_MGSTA_RXHA; | ||
1022 | + } | ||
1023 | + if (!(value & REG_MCMDR_RXON)) { | ||
1024 | + emc_halt_rx(emc, 0); | ||
1025 | + } | ||
1026 | + break; | ||
1027 | + } | ||
1028 | + case REG_TXDLSA: | ||
1029 | + case REG_RXDLSA: | ||
1030 | + case REG_DMARFC: | ||
1031 | + case REG_MIID: | ||
1032 | + emc->regs[reg] = value; | ||
1033 | + break; | ||
1034 | + case REG_MIEN: | ||
1035 | + emc->regs[reg] = value; | ||
1036 | + emc_update_irq_from_reg_change(emc); | ||
1037 | + break; | ||
1038 | + case REG_MISTA: | ||
1039 | + /* Clear the bits that have 1 in "value". */ | ||
1040 | + emc->regs[reg] &= ~value; | ||
1041 | + emc_update_irq_from_reg_change(emc); | ||
1042 | + break; | ||
1043 | + case REG_MGSTA: | ||
1044 | + /* Clear the bits that have 1 in "value". */ | ||
1045 | + emc->regs[reg] &= ~value; | ||
1046 | + break; | ||
1047 | + case REG_TSDR: | ||
1048 | + if (emc->regs[REG_MCMDR] & REG_MCMDR_TXON) { | ||
1049 | + emc->tx_active = true; | ||
1050 | + /* Keep trying to send packets until we run out. */ | ||
1051 | + while (emc->tx_active) { | ||
1052 | + emc_try_send_next_packet(emc); | ||
1053 | + } | ||
1054 | + } | ||
1055 | + break; | ||
1056 | + case REG_RSDR: | ||
1057 | + if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) { | ||
1058 | + emc->rx_active = true; | ||
1059 | + emc_try_receive_next_packet(emc); | ||
1060 | + } | ||
1061 | + break; | ||
1062 | + case REG_MIIDA: | ||
1063 | + emc->regs[reg] = value & ~REG_MIIDA_BUSY; | ||
1064 | + break; | ||
1065 | + case REG_MRPC: | ||
1066 | + case REG_MRPCC: | ||
1067 | + case REG_MREPC: | ||
1068 | + case REG_CTXDSA: | ||
1069 | + case REG_CTXBSA: | ||
1070 | + case REG_CRXDSA: | ||
1071 | + case REG_CRXBSA: | ||
1072 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
1073 | + "%s: Write to read-only reg %s/%d\n", | ||
1074 | + __func__, emc_reg_name(reg), reg); | ||
297 | + break; | 1075 | + break; |
298 | + default: | 1076 | + default: |
299 | + if (addr < ASPEED_SDHCI_REG_SIZE) { | 1077 | + qemu_log_mask(LOG_UNIMP, "%s: Write to unimplemented reg %s/%d\n", |
300 | + sdhci->regs[TO_REG(addr)] = (uint32_t)val; | 1078 | + __func__, emc_reg_name(reg), reg); |
301 | + } else { | 1079 | + break; |
302 | + qemu_log_mask(LOG_GUEST_ERROR, | 1080 | + } |
303 | + "%s: Out-of-bounds write at 0x%" HWADDR_PRIx "\n", | 1081 | +} |
304 | + __func__, addr); | 1082 | + |
305 | + } | 1083 | +static const struct MemoryRegionOps npcm7xx_emc_ops = { |
306 | + } | 1084 | + .read = npcm7xx_emc_read, |
307 | +} | 1085 | + .write = npcm7xx_emc_write, |
308 | + | 1086 | + .endianness = DEVICE_LITTLE_ENDIAN, |
309 | +static const MemoryRegionOps aspeed_sdhci_ops = { | 1087 | + .valid = { |
310 | + .read = aspeed_sdhci_read, | 1088 | + .min_access_size = 4, |
311 | + .write = aspeed_sdhci_write, | 1089 | + .max_access_size = 4, |
312 | + .endianness = DEVICE_NATIVE_ENDIAN, | 1090 | + .unaligned = false, |
313 | + .valid.min_access_size = 4, | 1091 | + }, |
314 | + .valid.max_access_size = 4, | ||
315 | +}; | 1092 | +}; |
316 | + | 1093 | + |
317 | +static void aspeed_sdhci_set_irq(void *opaque, int n, int level) | 1094 | +static void emc_cleanup(NetClientState *nc) |
318 | +{ | 1095 | +{ |
319 | + AspeedSDHCIState *sdhci = opaque; | 1096 | + /* Nothing to do yet. */ |
320 | + | 1097 | +} |
321 | + if (level) { | 1098 | + |
322 | + sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] |= BIT(n); | 1099 | +static NetClientInfo net_npcm7xx_emc_info = { |
323 | + | 1100 | + .type = NET_CLIENT_DRIVER_NIC, |
324 | + qemu_irq_raise(sdhci->irq); | 1101 | + .size = sizeof(NICState), |
325 | + } else { | 1102 | + .can_receive = emc_can_receive, |
326 | + sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] &= ~BIT(n); | 1103 | + .receive = emc_receive, |
327 | + | 1104 | + .cleanup = emc_cleanup, |
328 | + qemu_irq_lower(sdhci->irq); | 1105 | + .link_status_changed = emc_set_link, |
329 | + } | 1106 | +}; |
330 | +} | 1107 | + |
331 | + | 1108 | +static void npcm7xx_emc_realize(DeviceState *dev, Error **errp) |
332 | +static void aspeed_sdhci_realize(DeviceState *dev, Error **errp) | 1109 | +{ |
333 | +{ | 1110 | + NPCM7xxEMCState *emc = NPCM7XX_EMC(dev); |
334 | + Error *err = NULL; | 1111 | + SysBusDevice *sbd = SYS_BUS_DEVICE(emc); |
335 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | 1112 | + |
336 | + AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev); | 1113 | + memory_region_init_io(&emc->iomem, OBJECT(emc), &npcm7xx_emc_ops, emc, |
337 | + | 1114 | + TYPE_NPCM7XX_EMC, 4 * KiB); |
338 | + /* Create input irqs for the slots */ | 1115 | + sysbus_init_mmio(sbd, &emc->iomem); |
339 | + qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq, | 1116 | + sysbus_init_irq(sbd, &emc->tx_irq); |
340 | + sdhci, NULL, ASPEED_SDHCI_NUM_SLOTS); | 1117 | + sysbus_init_irq(sbd, &emc->rx_irq); |
341 | + | 1118 | + |
342 | + sysbus_init_irq(sbd, &sdhci->irq); | 1119 | + qemu_macaddr_default_if_unset(&emc->conf.macaddr); |
343 | + memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops, | 1120 | + emc->nic = qemu_new_nic(&net_npcm7xx_emc_info, &emc->conf, |
344 | + sdhci, TYPE_ASPEED_SDHCI, 0x1000); | 1121 | + object_get_typename(OBJECT(dev)), dev->id, emc); |
345 | + sysbus_init_mmio(sbd, &sdhci->iomem); | 1122 | + qemu_format_nic_info_str(qemu_get_queue(emc->nic), emc->conf.macaddr.a); |
346 | + | 1123 | +} |
347 | + for (int i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | 1124 | + |
348 | + Object *sdhci_slot = OBJECT(&sdhci->slots[i]); | 1125 | +static void npcm7xx_emc_unrealize(DeviceState *dev) |
349 | + SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slots[i]); | 1126 | +{ |
350 | + | 1127 | + NPCM7xxEMCState *emc = NPCM7XX_EMC(dev); |
351 | + object_property_set_int(sdhci_slot, 2, "sd-spec-version", &err); | 1128 | + |
352 | + if (err) { | 1129 | + qemu_del_nic(emc->nic); |
353 | + error_propagate(errp, err); | 1130 | +} |
354 | + return; | 1131 | + |
355 | + } | 1132 | +static const VMStateDescription vmstate_npcm7xx_emc = { |
356 | + | 1133 | + .name = TYPE_NPCM7XX_EMC, |
357 | + object_property_set_uint(sdhci_slot, ASPEED_SDHCI_CAPABILITIES, | 1134 | + .version_id = 0, |
358 | + "capareg", &err); | 1135 | + .minimum_version_id = 0, |
359 | + if (err) { | ||
360 | + error_propagate(errp, err); | ||
361 | + return; | ||
362 | + } | ||
363 | + | ||
364 | + object_property_set_bool(sdhci_slot, true, "realized", &err); | ||
365 | + if (err) { | ||
366 | + error_propagate(errp, err); | ||
367 | + return; | ||
368 | + } | ||
369 | + | ||
370 | + sysbus_connect_irq(sbd_slot, 0, qdev_get_gpio_in(DEVICE(sbd), i)); | ||
371 | + memory_region_add_subregion(&sdhci->iomem, (i + 1) * 0x100, | ||
372 | + &sdhci->slots[i].iomem); | ||
373 | + } | ||
374 | +} | ||
375 | + | ||
376 | +static void aspeed_sdhci_reset(DeviceState *dev) | ||
377 | +{ | ||
378 | + AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev); | ||
379 | + | ||
380 | + memset(sdhci->regs, 0, ASPEED_SDHCI_REG_SIZE); | ||
381 | + sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] = ASPEED_SDHCI_INFO_RESET; | ||
382 | + sdhci->regs[TO_REG(ASPEED_SDHCI_DEBOUNCE)] = ASPEED_SDHCI_DEBOUNCE_RESET; | ||
383 | +} | ||
384 | + | ||
385 | +static const VMStateDescription vmstate_aspeed_sdhci = { | ||
386 | + .name = TYPE_ASPEED_SDHCI, | ||
387 | + .version_id = 1, | ||
388 | + .fields = (VMStateField[]) { | 1136 | + .fields = (VMStateField[]) { |
389 | + VMSTATE_UINT32_ARRAY(regs, AspeedSDHCIState, ASPEED_SDHCI_NUM_REGS), | 1137 | + VMSTATE_UINT8(emc_num, NPCM7xxEMCState), |
1138 | + VMSTATE_UINT32_ARRAY(regs, NPCM7xxEMCState, NPCM7XX_NUM_EMC_REGS), | ||
1139 | + VMSTATE_BOOL(tx_active, NPCM7xxEMCState), | ||
1140 | + VMSTATE_BOOL(rx_active, NPCM7xxEMCState), | ||
390 | + VMSTATE_END_OF_LIST(), | 1141 | + VMSTATE_END_OF_LIST(), |
391 | + }, | 1142 | + }, |
392 | +}; | 1143 | +}; |
393 | + | 1144 | + |
394 | +static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) | 1145 | +static Property npcm7xx_emc_properties[] = { |
395 | +{ | 1146 | + DEFINE_NIC_PROPERTIES(NPCM7xxEMCState, conf), |
396 | + DeviceClass *dc = DEVICE_CLASS(classp); | 1147 | + DEFINE_PROP_END_OF_LIST(), |
397 | + | ||
398 | + dc->realize = aspeed_sdhci_realize; | ||
399 | + dc->reset = aspeed_sdhci_reset; | ||
400 | + dc->vmsd = &vmstate_aspeed_sdhci; | ||
401 | +} | ||
402 | + | ||
403 | +static TypeInfo aspeed_sdhci_info = { | ||
404 | + .name = TYPE_ASPEED_SDHCI, | ||
405 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
406 | + .instance_size = sizeof(AspeedSDHCIState), | ||
407 | + .class_init = aspeed_sdhci_class_init, | ||
408 | +}; | 1148 | +}; |
409 | + | 1149 | + |
410 | +static void aspeed_sdhci_register_types(void) | 1150 | +static void npcm7xx_emc_class_init(ObjectClass *klass, void *data) |
411 | +{ | 1151 | +{ |
412 | + type_register_static(&aspeed_sdhci_info); | 1152 | + DeviceClass *dc = DEVICE_CLASS(klass); |
413 | +} | 1153 | + |
414 | + | 1154 | + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); |
415 | +type_init(aspeed_sdhci_register_types) | 1155 | + dc->desc = "NPCM7xx EMC Controller"; |
1156 | + dc->realize = npcm7xx_emc_realize; | ||
1157 | + dc->unrealize = npcm7xx_emc_unrealize; | ||
1158 | + dc->reset = npcm7xx_emc_reset; | ||
1159 | + dc->vmsd = &vmstate_npcm7xx_emc; | ||
1160 | + device_class_set_props(dc, npcm7xx_emc_properties); | ||
1161 | +} | ||
1162 | + | ||
1163 | +static const TypeInfo npcm7xx_emc_info = { | ||
1164 | + .name = TYPE_NPCM7XX_EMC, | ||
1165 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
1166 | + .instance_size = sizeof(NPCM7xxEMCState), | ||
1167 | + .class_init = npcm7xx_emc_class_init, | ||
1168 | +}; | ||
1169 | + | ||
1170 | +static void npcm7xx_emc_register_type(void) | ||
1171 | +{ | ||
1172 | + type_register_static(&npcm7xx_emc_info); | ||
1173 | +} | ||
1174 | + | ||
1175 | +type_init(npcm7xx_emc_register_type) | ||
1176 | diff --git a/hw/net/meson.build b/hw/net/meson.build | ||
1177 | index XXXXXXX..XXXXXXX 100644 | ||
1178 | --- a/hw/net/meson.build | ||
1179 | +++ b/hw/net/meson.build | ||
1180 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_I82596_COMMON', if_true: files('i82596.c')) | ||
1181 | softmmu_ss.add(when: 'CONFIG_SUNHME', if_true: files('sunhme.c')) | ||
1182 | softmmu_ss.add(when: 'CONFIG_FTGMAC100', if_true: files('ftgmac100.c')) | ||
1183 | softmmu_ss.add(when: 'CONFIG_SUNGEM', if_true: files('sungem.c')) | ||
1184 | +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_emc.c')) | ||
1185 | |||
1186 | softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_eth.c')) | ||
1187 | softmmu_ss.add(when: 'CONFIG_COLDFIRE', if_true: files('mcf_fec.c')) | ||
1188 | diff --git a/hw/net/trace-events b/hw/net/trace-events | ||
1189 | index XXXXXXX..XXXXXXX 100644 | ||
1190 | --- a/hw/net/trace-events | ||
1191 | +++ b/hw/net/trace-events | ||
1192 | @@ -XXX,XX +XXX,XX @@ imx_fec_receive_last(int last) "rx frame flags 0x%04x" | ||
1193 | imx_enet_receive(size_t size) "len %zu" | ||
1194 | imx_enet_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d" | ||
1195 | imx_enet_receive_last(int last) "rx frame flags 0x%04x" | ||
1196 | + | ||
1197 | +# npcm7xx_emc.c | ||
1198 | +npcm7xx_emc_reset(int emc_num) "Resetting emc%d" | ||
1199 | +npcm7xx_emc_update_tx_irq(int level) "Setting tx irq to %d" | ||
1200 | +npcm7xx_emc_update_rx_irq(int level) "Setting rx irq to %d" | ||
1201 | +npcm7xx_emc_set_mista(uint32_t flags) "ORing 0x%x into MISTA" | ||
1202 | +npcm7xx_emc_cpu_owned_desc(uint32_t addr) "Can't process cpu-owned descriptor @0x%x" | ||
1203 | +npcm7xx_emc_sent_packet(uint32_t len) "Sent %u byte packet" | ||
1204 | +npcm7xx_emc_tx_done(uint32_t ctxdsa) "TX done, CTXDSA=0x%x" | ||
1205 | +npcm7xx_emc_can_receive(int can_receive) "Can receive: %d" | ||
1206 | +npcm7xx_emc_packet_filtered_out(const char* fail_reason) "Packet filtered out: %s" | ||
1207 | +npcm7xx_emc_packet_dropped(uint32_t len) "%u byte packet dropped" | ||
1208 | +npcm7xx_emc_receiving_packet(uint32_t len) "Receiving %u byte packet" | ||
1209 | +npcm7xx_emc_received_packet(uint32_t len) "Received %u byte packet" | ||
1210 | +npcm7xx_emc_rx_done(uint32_t crxdsa) "RX done, CRXDSA=0x%x" | ||
1211 | +npcm7xx_emc_reg_read(int emc_num, uint32_t result, const char *name, int regno) "emc%d: 0x%x = reg[%s/%d]" | ||
1212 | +npcm7xx_emc_reg_write(int emc_num, const char *name, int regno, uint32_t value) "emc%d: reg[%s/%d] = 0x%x" | ||
416 | -- | 1213 | -- |
417 | 2.20.1 | 1214 | 2.20.1 |
418 | 1215 | ||
419 | 1216 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Doug Evans <dje@google.com> |
---|---|---|---|
2 | 2 | ||
3 | The AST2600 SoC SMC controller is a SPI only controller now and has a | 3 | This is a 10/100 ethernet device that has several features. |
4 | few extensions which we will need to take into account when SW | 4 | Only the ones needed by the Linux driver have been implemented. |
5 | requires it. This is enough to support u-boot and Linux. | 5 | See npcm7xx_emc.c for a list of unimplemented features. |
6 | 6 | ||
7 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 7 | Reviewed-by: Hao Wu <wuhaotsh@google.com> |
8 | Acked-by: Joel Stanley <joel@jms.id.au> | 8 | Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com> |
9 | Message-id: 20190925143248.10000-14-clg@kaod.org | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Doug Evans <dje@google.com> | ||
11 | Message-id: 20210218212453.831406-3-dje@google.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 13 | --- |
12 | hw/ssi/aspeed_smc.c | 132 ++++++++++++++++++++++++++++++++++++++++++-- | 14 | docs/system/arm/nuvoton.rst | 3 ++- |
13 | 1 file changed, 128 insertions(+), 4 deletions(-) | 15 | include/hw/arm/npcm7xx.h | 2 ++ |
16 | hw/arm/npcm7xx.c | 50 +++++++++++++++++++++++++++++++++++-- | ||
17 | 3 files changed, 52 insertions(+), 3 deletions(-) | ||
14 | 18 | ||
15 | diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c | 19 | diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst |
16 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/ssi/aspeed_smc.c | 21 | --- a/docs/system/arm/nuvoton.rst |
18 | +++ b/hw/ssi/aspeed_smc.c | 22 | +++ b/docs/system/arm/nuvoton.rst |
23 | @@ -XXX,XX +XXX,XX @@ Supported devices | ||
24 | * Analog to Digital Converter (ADC) | ||
25 | * Pulse Width Modulation (PWM) | ||
26 | * SMBus controller (SMBF) | ||
27 | + * Ethernet controller (EMC) | ||
28 | |||
29 | Missing devices | ||
30 | --------------- | ||
31 | @@ -XXX,XX +XXX,XX @@ Missing devices | ||
32 | * Shared memory (SHM) | ||
33 | * eSPI slave interface | ||
34 | |||
35 | - * Ethernet controllers (GMAC and EMC) | ||
36 | + * Ethernet controller (GMAC) | ||
37 | * USB device (USBD) | ||
38 | * Peripheral SPI controller (PSPI) | ||
39 | * SD/MMC host | ||
40 | diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/include/hw/arm/npcm7xx.h | ||
43 | +++ b/include/hw/arm/npcm7xx.h | ||
19 | @@ -XXX,XX +XXX,XX @@ | 44 | @@ -XXX,XX +XXX,XX @@ |
20 | #include "qemu/error-report.h" | 45 | #include "hw/misc/npcm7xx_gcr.h" |
21 | #include "qapi/error.h" | 46 | #include "hw/misc/npcm7xx_pwm.h" |
22 | #include "exec/address-spaces.h" | 47 | #include "hw/misc/npcm7xx_rng.h" |
23 | +#include "qemu/units.h" | 48 | +#include "hw/net/npcm7xx_emc.h" |
24 | 49 | #include "hw/nvram/npcm7xx_otp.h" | |
25 | #include "hw/irq.h" | 50 | #include "hw/timer/npcm7xx_timer.h" |
26 | #include "hw/qdev-properties.h" | 51 | #include "hw/ssi/npcm7xx_fiu.h" |
27 | @@ -XXX,XX +XXX,XX @@ | 52 | @@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState { |
28 | #define CONF_FLASH_TYPE0 0 | 53 | EHCISysBusState ehci; |
29 | #define CONF_FLASH_TYPE_NOR 0x0 | 54 | OHCISysBusState ohci; |
30 | #define CONF_FLASH_TYPE_NAND 0x1 | 55 | NPCM7xxFIUState fiu[2]; |
31 | -#define CONF_FLASH_TYPE_SPI 0x2 | 56 | + NPCM7xxEMCState emc[2]; |
32 | +#define CONF_FLASH_TYPE_SPI 0x2 /* AST2600 is SPI only */ | 57 | } NPCM7xxState; |
33 | 58 | ||
34 | /* CE Control Register */ | 59 | #define TYPE_NPCM7XX "npcm7xx" |
35 | #define R_CE_CTRL (0x04 / 4) | 60 | diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c |
36 | @@ -XXX,XX +XXX,XX @@ | 61 | index XXXXXXX..XXXXXXX 100644 |
37 | 62 | --- a/hw/arm/npcm7xx.c | |
38 | /* CEx Control Register */ | 63 | +++ b/hw/arm/npcm7xx.c |
39 | #define R_CTRL0 (0x10 / 4) | 64 | @@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt { |
40 | +#define CTRL_IO_QPI (1 << 31) | 65 | NPCM7XX_UART1_IRQ, |
41 | +#define CTRL_IO_QUAD_DATA (1 << 30) | 66 | NPCM7XX_UART2_IRQ, |
42 | #define CTRL_IO_DUAL_DATA (1 << 29) | 67 | NPCM7XX_UART3_IRQ, |
43 | #define CTRL_IO_DUAL_ADDR_DATA (1 << 28) /* Includes dummies */ | 68 | + NPCM7XX_EMC1RX_IRQ = 15, |
44 | +#define CTRL_IO_QUAD_ADDR_DATA (1 << 28) /* Includes dummies */ | 69 | + NPCM7XX_EMC1TX_IRQ, |
45 | #define CTRL_CMD_SHIFT 16 | 70 | NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */ |
46 | #define CTRL_CMD_MASK 0xff | 71 | NPCM7XX_TIMER1_IRQ, |
47 | #define CTRL_DUMMY_HIGH_SHIFT 14 | 72 | NPCM7XX_TIMER2_IRQ, |
48 | @@ -XXX,XX +XXX,XX @@ | 73 | @@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt { |
49 | /* Misc Control Register #2 */ | 74 | NPCM7XX_SMBUS15_IRQ, |
50 | #define R_TIMINGS (0x94 / 4) | 75 | NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */ |
51 | 76 | NPCM7XX_PWM1_IRQ, /* PWM module 1 */ | |
52 | -/* SPI controller registers and bits */ | 77 | + NPCM7XX_EMC2RX_IRQ = 114, |
53 | +/* SPI controller registers and bits (AST2400) */ | 78 | + NPCM7XX_EMC2TX_IRQ, |
54 | #define R_SPI_CONF (0x00 / 4) | 79 | NPCM7XX_GPIO0_IRQ = 116, |
55 | #define SPI_CONF_ENABLE_W0 0 | 80 | NPCM7XX_GPIO1_IRQ, |
56 | #define R_SPI_CTRL0 (0x4 / 4) | 81 | NPCM7XX_GPIO2_IRQ, |
57 | @@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s, | 82 | @@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_smbus_addr[] = { |
58 | static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, uint32_t reg, | 83 | 0xf008f000, |
59 | AspeedSegments *seg); | 84 | }; |
60 | 85 | ||
61 | +/* | 86 | +/* Register base address for each EMC Module */ |
62 | + * AST2600 definitions | 87 | +static const hwaddr npcm7xx_emc_addr[] = { |
63 | + */ | 88 | + 0xf0825000, |
64 | +#define ASPEED26_SOC_FMC_FLASH_BASE 0x20000000 | 89 | + 0xf0826000, |
65 | +#define ASPEED26_SOC_SPI_FLASH_BASE 0x30000000 | ||
66 | +#define ASPEED26_SOC_SPI2_FLASH_BASE 0x50000000 | ||
67 | + | ||
68 | +static const AspeedSegments aspeed_segments_ast2600_fmc[] = { | ||
69 | + { 0x0, 128 * MiB }, /* start address is readonly */ | ||
70 | + { 0x0, 0 }, /* disabled */ | ||
71 | + { 0x0, 0 }, /* disabled */ | ||
72 | +}; | 90 | +}; |
73 | + | 91 | + |
74 | +static const AspeedSegments aspeed_segments_ast2600_spi1[] = { | 92 | static const struct { |
75 | + { 0x0, 128 * MiB }, /* start address is readonly */ | 93 | hwaddr regs_addr; |
76 | + { 0x0, 0 }, /* disabled */ | 94 | uint32_t unconnected_pins; |
77 | +}; | 95 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj) |
96 | for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { | ||
97 | object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM); | ||
98 | } | ||
78 | + | 99 | + |
79 | +static const AspeedSegments aspeed_segments_ast2600_spi2[] = { | 100 | + for (i = 0; i < ARRAY_SIZE(s->emc); i++) { |
80 | + { 0x0, 128 * MiB }, /* start address is readonly */ | 101 | + object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC); |
81 | + { 0x0, 0 }, /* disabled */ | 102 | + } |
82 | + { 0x0, 0 }, /* disabled */ | ||
83 | +}; | ||
84 | + | ||
85 | +static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s, | ||
86 | + const AspeedSegments *seg); | ||
87 | +static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s, | ||
88 | + uint32_t reg, AspeedSegments *seg); | ||
89 | + | ||
90 | static const AspeedSMCController controllers[] = { | ||
91 | { | ||
92 | .name = "aspeed.smc-ast2400", | ||
93 | @@ -XXX,XX +XXX,XX @@ static const AspeedSMCController controllers[] = { | ||
94 | .nregs = ASPEED_SMC_R_MAX, | ||
95 | .segment_to_reg = aspeed_smc_segment_to_reg, | ||
96 | .reg_to_segment = aspeed_smc_reg_to_segment, | ||
97 | + }, { | ||
98 | + .name = "aspeed.fmc-ast2600", | ||
99 | + .r_conf = R_CONF, | ||
100 | + .r_ce_ctrl = R_CE_CTRL, | ||
101 | + .r_ctrl0 = R_CTRL0, | ||
102 | + .r_timings = R_TIMINGS, | ||
103 | + .conf_enable_w0 = CONF_ENABLE_W0, | ||
104 | + .max_slaves = 3, | ||
105 | + .segments = aspeed_segments_ast2600_fmc, | ||
106 | + .flash_window_base = ASPEED26_SOC_FMC_FLASH_BASE, | ||
107 | + .flash_window_size = 0x10000000, | ||
108 | + .has_dma = true, | ||
109 | + .nregs = ASPEED_SMC_R_MAX, | ||
110 | + .segment_to_reg = aspeed_2600_smc_segment_to_reg, | ||
111 | + .reg_to_segment = aspeed_2600_smc_reg_to_segment, | ||
112 | + }, { | ||
113 | + .name = "aspeed.spi1-ast2600", | ||
114 | + .r_conf = R_CONF, | ||
115 | + .r_ce_ctrl = R_CE_CTRL, | ||
116 | + .r_ctrl0 = R_CTRL0, | ||
117 | + .r_timings = R_TIMINGS, | ||
118 | + .conf_enable_w0 = CONF_ENABLE_W0, | ||
119 | + .max_slaves = 2, | ||
120 | + .segments = aspeed_segments_ast2600_spi1, | ||
121 | + .flash_window_base = ASPEED26_SOC_SPI_FLASH_BASE, | ||
122 | + .flash_window_size = 0x10000000, | ||
123 | + .has_dma = false, | ||
124 | + .nregs = ASPEED_SMC_R_MAX, | ||
125 | + .segment_to_reg = aspeed_2600_smc_segment_to_reg, | ||
126 | + .reg_to_segment = aspeed_2600_smc_reg_to_segment, | ||
127 | + }, { | ||
128 | + .name = "aspeed.spi2-ast2600", | ||
129 | + .r_conf = R_CONF, | ||
130 | + .r_ce_ctrl = R_CE_CTRL, | ||
131 | + .r_ctrl0 = R_CTRL0, | ||
132 | + .r_timings = R_TIMINGS, | ||
133 | + .conf_enable_w0 = CONF_ENABLE_W0, | ||
134 | + .max_slaves = 3, | ||
135 | + .segments = aspeed_segments_ast2600_spi2, | ||
136 | + .flash_window_base = ASPEED26_SOC_SPI2_FLASH_BASE, | ||
137 | + .flash_window_size = 0x10000000, | ||
138 | + .has_dma = false, | ||
139 | + .nregs = ASPEED_SMC_R_MAX, | ||
140 | + .segment_to_reg = aspeed_2600_smc_segment_to_reg, | ||
141 | + .reg_to_segment = aspeed_2600_smc_reg_to_segment, | ||
142 | }, | ||
143 | }; | ||
144 | |||
145 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, | ||
146 | seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr; | ||
147 | } | 103 | } |
148 | 104 | ||
149 | +/* | 105 | static void npcm7xx_realize(DeviceState *dev, Error **errp) |
150 | + * The Segment Registers of the AST2600 have a 1MB unit. The address | 106 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) |
151 | + * range of a flash SPI slave is encoded with offsets in the overall | 107 | sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i)); |
152 | + * controller window. The previous SoC AST2400 and AST2500 used | 108 | } |
153 | + * absolute addresses. Only bits [27:20] are relevant and the end | 109 | |
154 | + * address is an upper bound limit. | 110 | + /* |
155 | + */ | 111 | + * EMC Modules. Cannot fail. |
156 | +#define AST2600_SEG_ADDR_MASK 0x0ff00000 | 112 | + * The mapping of the device to its netdev backend works as follows: |
157 | + | 113 | + * emc[i] = nd_table[i] |
158 | +static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s, | 114 | + * This works around the inability to specify the netdev property for the |
159 | + const AspeedSegments *seg) | 115 | + * emc device: it's not pluggable and thus the -device option can't be |
160 | +{ | 116 | + * used. |
161 | + uint32_t reg = 0; | 117 | + */ |
162 | + | 118 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_emc_addr) != ARRAY_SIZE(s->emc)); |
163 | + /* Disabled segments have a nil register */ | 119 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->emc) != 2); |
164 | + if (!seg->size) { | 120 | + for (i = 0; i < ARRAY_SIZE(s->emc); i++) { |
165 | + return 0; | 121 | + s->emc[i].emc_num = i; |
122 | + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->emc[i]); | ||
123 | + if (nd_table[i].used) { | ||
124 | + qemu_check_nic_model(&nd_table[i], TYPE_NPCM7XX_EMC); | ||
125 | + qdev_set_nic_properties(DEVICE(sbd), &nd_table[i]); | ||
126 | + } | ||
127 | + /* | ||
128 | + * The device exists regardless of whether it's connected to a QEMU | ||
129 | + * netdev backend. So always instantiate it even if there is no | ||
130 | + * backend. | ||
131 | + */ | ||
132 | + sysbus_realize(sbd, &error_abort); | ||
133 | + sysbus_mmio_map(sbd, 0, npcm7xx_emc_addr[i]); | ||
134 | + int tx_irq = i == 0 ? NPCM7XX_EMC1TX_IRQ : NPCM7XX_EMC2TX_IRQ; | ||
135 | + int rx_irq = i == 0 ? NPCM7XX_EMC1RX_IRQ : NPCM7XX_EMC2RX_IRQ; | ||
136 | + /* | ||
137 | + * N.B. The values for the second argument sysbus_connect_irq are | ||
138 | + * chosen to match the registration order in npcm7xx_emc_realize. | ||
139 | + */ | ||
140 | + sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, tx_irq)); | ||
141 | + sysbus_connect_irq(sbd, 1, npcm7xx_irq(s, rx_irq)); | ||
166 | + } | 142 | + } |
167 | + | 143 | + |
168 | + reg |= (seg->addr & AST2600_SEG_ADDR_MASK) >> 16; /* start offset */ | 144 | /* |
169 | + reg |= (seg->addr + seg->size - 1) & AST2600_SEG_ADDR_MASK; /* end offset */ | 145 | * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects |
170 | + return reg; | 146 | * specified, but this is a programming error. |
171 | +} | 147 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) |
172 | + | 148 | create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB); |
173 | +static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s, | 149 | create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB); |
174 | + uint32_t reg, AspeedSegments *seg) | 150 | create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB); |
175 | +{ | 151 | - create_unimplemented_device("npcm7xx.emc1", 0xf0825000, 4 * KiB); |
176 | + uint32_t start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK; | 152 | - create_unimplemented_device("npcm7xx.emc2", 0xf0826000, 4 * KiB); |
177 | + uint32_t end_offset = reg & AST2600_SEG_ADDR_MASK; | 153 | create_unimplemented_device("npcm7xx.usbd[0]", 0xf0830000, 4 * KiB); |
178 | + | 154 | create_unimplemented_device("npcm7xx.usbd[1]", 0xf0831000, 4 * KiB); |
179 | + seg->addr = s->ctrl->flash_window_base + start_offset; | 155 | create_unimplemented_device("npcm7xx.usbd[2]", 0xf0832000, 4 * KiB); |
180 | + seg->size = end_offset + MiB - start_offset; | ||
181 | +} | ||
182 | + | ||
183 | static bool aspeed_smc_flash_overlap(const AspeedSMCState *s, | ||
184 | const AspeedSegments *new, | ||
185 | int cs) | ||
186 | @@ -XXX,XX +XXX,XX @@ static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl) | ||
187 | const AspeedSMCState *s = fl->controller; | ||
188 | int cmd = (s->regs[s->r_ctrl0 + fl->id] >> CTRL_CMD_SHIFT) & CTRL_CMD_MASK; | ||
189 | |||
190 | - /* In read mode, the default SPI command is READ (0x3). In other | ||
191 | - * modes, the command should necessarily be defined */ | ||
192 | + /* | ||
193 | + * In read mode, the default SPI command is READ (0x3). In other | ||
194 | + * modes, the command should necessarily be defined | ||
195 | + * | ||
196 | + * TODO: add support for READ4 (0x13) on AST2600 | ||
197 | + */ | ||
198 | if (aspeed_smc_flash_mode(fl) == CTRL_READMODE) { | ||
199 | cmd = SPI_OP_READ; | ||
200 | } | ||
201 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_reset(DeviceState *d) | ||
202 | s->ctrl->segment_to_reg(s, &s->ctrl->segments[i]); | ||
203 | } | ||
204 | |||
205 | + /* HW strapping flash type for the AST2600 controllers */ | ||
206 | + if (s->ctrl->segments == aspeed_segments_ast2600_fmc) { | ||
207 | + /* flash type is fixed to SPI for all */ | ||
208 | + s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0); | ||
209 | + s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1); | ||
210 | + s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE2); | ||
211 | + } | ||
212 | + | ||
213 | /* HW strapping flash type for FMC controllers */ | ||
214 | if (s->ctrl->segments == aspeed_segments_ast2500_fmc) { | ||
215 | /* flash type is fixed to SPI for CE0 and CE1 */ | ||
216 | -- | 156 | -- |
217 | 2.20.1 | 157 | 2.20.1 |
218 | 158 | ||
219 | 159 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Doug Evans <dje@google.com> |
---|---|---|---|
2 | 2 | ||
3 | Initial definitions for a simple machine using an AST2600 SoC (Cortex | 3 | Reviewed-by: Hao Wu <wuhaotsh@google.com> |
4 | CPU). | 4 | Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com> |
5 | 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | |
6 | The Cortex CPU and its interrupt controller are too complex to handle | 6 | Signed-off-by: Doug Evans <dje@google.com> |
7 | in the common Aspeed SoC framework. We introduce a new Aspeed SoC | 7 | Message-id: 20210218212453.831406-4-dje@google.com |
8 | class with instance_init and realize handlers to handle the differences | ||
9 | with the AST2400 and the AST2500 SoCs. This will add extra work to | ||
10 | keep in sync both models with future extensions but it makes the code | ||
11 | clearer. | ||
12 | |||
13 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
14 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
15 | Message-id: 20190925143248.10000-19-clg@kaod.org | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 9 | --- |
18 | hw/arm/Makefile.objs | 2 +- | 10 | tests/qtest/npcm7xx_emc-test.c | 862 +++++++++++++++++++++++++++++++++ |
19 | include/hw/arm/aspeed_soc.h | 4 + | 11 | tests/qtest/meson.build | 3 +- |
20 | hw/arm/aspeed_ast2600.c | 492 ++++++++++++++++++++++++++++++++++++ | 12 | 2 files changed, 864 insertions(+), 1 deletion(-) |
21 | 3 files changed, 497 insertions(+), 1 deletion(-) | 13 | create mode 100644 tests/qtest/npcm7xx_emc-test.c |
22 | create mode 100644 hw/arm/aspeed_ast2600.c | ||
23 | 14 | ||
24 | diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs | 15 | diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c |
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/hw/arm/Makefile.objs | ||
27 | +++ b/hw/arm/Makefile.objs | ||
28 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o | ||
29 | obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o | ||
30 | obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o | ||
31 | obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o | ||
32 | -obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o | ||
33 | +obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o aspeed_ast2600.o | ||
34 | obj-$(CONFIG_MPS2) += mps2.o | ||
35 | obj-$(CONFIG_MPS2) += mps2-tz.o | ||
36 | obj-$(CONFIG_MSF2) += msf2-soc.o | ||
37 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/include/hw/arm/aspeed_soc.h | ||
40 | +++ b/include/hw/arm/aspeed_soc.h | ||
41 | @@ -XXX,XX +XXX,XX @@ | ||
42 | #ifndef ASPEED_SOC_H | ||
43 | #define ASPEED_SOC_H | ||
44 | |||
45 | +#include "hw/cpu/a15mpcore.h" | ||
46 | #include "hw/intc/aspeed_vic.h" | ||
47 | #include "hw/misc/aspeed_scu.h" | ||
48 | #include "hw/misc/aspeed_sdmc.h" | ||
49 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState { | ||
50 | /*< public >*/ | ||
51 | ARMCPU cpu[ASPEED_CPUS_NUM]; | ||
52 | uint32_t num_cpus; | ||
53 | + A15MPPrivState a7mpcore; | ||
54 | MemoryRegion sram; | ||
55 | AspeedVICState vic; | ||
56 | AspeedRtcState rtc; | ||
57 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState { | ||
58 | AspeedWDTState wdt[ASPEED_WDTS_NUM]; | ||
59 | FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; | ||
60 | AspeedGPIOState gpio; | ||
61 | + AspeedGPIOState gpio_1_8v; | ||
62 | AspeedSDHCIState sdhci; | ||
63 | } AspeedSoCState; | ||
64 | |||
65 | @@ -XXX,XX +XXX,XX @@ enum { | ||
66 | ASPEED_SRAM, | ||
67 | ASPEED_SDHCI, | ||
68 | ASPEED_GPIO, | ||
69 | + ASPEED_GPIO_1_8V, | ||
70 | ASPEED_RTC, | ||
71 | ASPEED_TIMER1, | ||
72 | ASPEED_TIMER2, | ||
73 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c | ||
74 | new file mode 100644 | 16 | new file mode 100644 |
75 | index XXXXXXX..XXXXXXX | 17 | index XXXXXXX..XXXXXXX |
76 | --- /dev/null | 18 | --- /dev/null |
77 | +++ b/hw/arm/aspeed_ast2600.c | 19 | +++ b/tests/qtest/npcm7xx_emc-test.c |
78 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ |
79 | +/* | 21 | +/* |
80 | + * ASPEED SoC 2600 family | 22 | + * QTests for Nuvoton NPCM7xx EMC Modules. |
81 | + * | 23 | + * |
82 | + * Copyright (c) 2016-2019, IBM Corporation. | 24 | + * Copyright 2020 Google LLC |
83 | + * | 25 | + * |
84 | + * This code is licensed under the GPL version 2 or later. See | 26 | + * This program is free software; you can redistribute it and/or modify it |
85 | + * the COPYING file in the top-level directory. | 27 | + * under the terms of the GNU General Public License as published by the |
28 | + * Free Software Foundation; either version 2 of the License, or | ||
29 | + * (at your option) any later version. | ||
30 | + * | ||
31 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
32 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
33 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
34 | + * for more details. | ||
86 | + */ | 35 | + */ |
87 | + | 36 | + |
88 | +#include "qemu/osdep.h" | 37 | +#include "qemu/osdep.h" |
89 | +#include "qapi/error.h" | 38 | +#include "qemu-common.h" |
90 | +#include "cpu.h" | 39 | +#include "libqos/libqos.h" |
91 | +#include "exec/address-spaces.h" | 40 | +#include "qapi/qmp/qdict.h" |
92 | +#include "hw/misc/unimp.h" | 41 | +#include "qapi/qmp/qnum.h" |
93 | +#include "hw/arm/aspeed_soc.h" | 42 | +#include "qemu/bitops.h" |
94 | +#include "hw/char/serial.h" | 43 | +#include "qemu/iov.h" |
95 | +#include "qemu/log.h" | 44 | + |
96 | +#include "qemu/module.h" | 45 | +/* Name of the emc device. */ |
97 | +#include "qemu/error-report.h" | 46 | +#define TYPE_NPCM7XX_EMC "npcm7xx-emc" |
98 | +#include "hw/i2c/aspeed_i2c.h" | 47 | + |
99 | +#include "net/net.h" | 48 | +/* Timeout for various operations, in seconds. */ |
100 | +#include "sysemu/sysemu.h" | 49 | +#define TIMEOUT_SECONDS 10 |
101 | + | 50 | + |
102 | +#define ASPEED_SOC_IOMEM_SIZE 0x00200000 | 51 | +/* Address in memory of the descriptor. */ |
103 | + | 52 | +#define DESC_ADDR (1 << 20) /* 1 MiB */ |
104 | +static const hwaddr aspeed_soc_ast2600_memmap[] = { | 53 | + |
105 | + [ASPEED_SRAM] = 0x10000000, | 54 | +/* Address in memory of the data packet. */ |
106 | + /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ | 55 | +#define DATA_ADDR (DESC_ADDR + 4096) |
107 | + [ASPEED_IOMEM] = 0x1E600000, | 56 | + |
108 | + [ASPEED_PWM] = 0x1E610000, | 57 | +#define CRC_LENGTH 4 |
109 | + [ASPEED_FMC] = 0x1E620000, | 58 | + |
110 | + [ASPEED_SPI1] = 0x1E630000, | 59 | +#define NUM_TX_DESCRIPTORS 3 |
111 | + [ASPEED_SPI2] = 0x1E641000, | 60 | +#define NUM_RX_DESCRIPTORS 2 |
112 | + [ASPEED_ETH1] = 0x1E660000, | 61 | + |
113 | + [ASPEED_ETH2] = 0x1E680000, | 62 | +/* Size of tx,rx test buffers. */ |
114 | + [ASPEED_VIC] = 0x1E6C0000, | 63 | +#define TX_DATA_LEN 64 |
115 | + [ASPEED_SDMC] = 0x1E6E0000, | 64 | +#define RX_DATA_LEN 64 |
116 | + [ASPEED_SCU] = 0x1E6E2000, | 65 | + |
117 | + [ASPEED_XDMA] = 0x1E6E7000, | 66 | +#define TX_STEP_COUNT 10000 |
118 | + [ASPEED_ADC] = 0x1E6E9000, | 67 | +#define RX_STEP_COUNT 10000 |
119 | + [ASPEED_SDHCI] = 0x1E740000, | 68 | + |
120 | + [ASPEED_GPIO] = 0x1E780000, | 69 | +/* 32-bit register indices. */ |
121 | + [ASPEED_GPIO_1_8V] = 0x1E780800, | 70 | +typedef enum NPCM7xxPWMRegister { |
122 | + [ASPEED_RTC] = 0x1E781000, | 71 | + /* Control registers. */ |
123 | + [ASPEED_TIMER1] = 0x1E782000, | 72 | + REG_CAMCMR, |
124 | + [ASPEED_WDT] = 0x1E785000, | 73 | + REG_CAMEN, |
125 | + [ASPEED_LPC] = 0x1E789000, | 74 | + |
126 | + [ASPEED_IBT] = 0x1E789140, | 75 | + /* There are 16 CAMn[ML] registers. */ |
127 | + [ASPEED_I2C] = 0x1E78A000, | 76 | + REG_CAMM_BASE, |
128 | + [ASPEED_UART1] = 0x1E783000, | 77 | + REG_CAML_BASE, |
129 | + [ASPEED_UART5] = 0x1E784000, | 78 | + |
130 | + [ASPEED_VUART] = 0x1E787000, | 79 | + REG_TXDLSA = 0x22, |
131 | + [ASPEED_SDRAM] = 0x80000000, | 80 | + REG_RXDLSA, |
81 | + REG_MCMDR, | ||
82 | + REG_MIID, | ||
83 | + REG_MIIDA, | ||
84 | + REG_FFTCR, | ||
85 | + REG_TSDR, | ||
86 | + REG_RSDR, | ||
87 | + REG_DMARFC, | ||
88 | + REG_MIEN, | ||
89 | + | ||
90 | + /* Status registers. */ | ||
91 | + REG_MISTA, | ||
92 | + REG_MGSTA, | ||
93 | + REG_MPCNT, | ||
94 | + REG_MRPC, | ||
95 | + REG_MRPCC, | ||
96 | + REG_MREPC, | ||
97 | + REG_DMARFS, | ||
98 | + REG_CTXDSA, | ||
99 | + REG_CTXBSA, | ||
100 | + REG_CRXDSA, | ||
101 | + REG_CRXBSA, | ||
102 | + | ||
103 | + NPCM7XX_NUM_EMC_REGS, | ||
104 | +} NPCM7xxPWMRegister; | ||
105 | + | ||
106 | +enum { NUM_CAMML_REGS = 16 }; | ||
107 | + | ||
108 | +/* REG_CAMCMR fields */ | ||
109 | +/* Enable CAM Compare */ | ||
110 | +#define REG_CAMCMR_ECMP (1 << 4) | ||
111 | +/* Accept Unicast Packet */ | ||
112 | +#define REG_CAMCMR_AUP (1 << 0) | ||
113 | + | ||
114 | +/* REG_MCMDR fields */ | ||
115 | +/* Software Reset */ | ||
116 | +#define REG_MCMDR_SWR (1 << 24) | ||
117 | +/* Frame Transmission On */ | ||
118 | +#define REG_MCMDR_TXON (1 << 8) | ||
119 | +/* Accept Long Packet */ | ||
120 | +#define REG_MCMDR_ALP (1 << 1) | ||
121 | +/* Frame Reception On */ | ||
122 | +#define REG_MCMDR_RXON (1 << 0) | ||
123 | + | ||
124 | +/* REG_MIEN fields */ | ||
125 | +/* Enable Transmit Completion Interrupt */ | ||
126 | +#define REG_MIEN_ENTXCP (1 << 18) | ||
127 | +/* Enable Transmit Interrupt */ | ||
128 | +#define REG_MIEN_ENTXINTR (1 << 16) | ||
129 | +/* Enable Receive Good Interrupt */ | ||
130 | +#define REG_MIEN_ENRXGD (1 << 4) | ||
131 | +/* ENable Receive Interrupt */ | ||
132 | +#define REG_MIEN_ENRXINTR (1 << 0) | ||
133 | + | ||
134 | +/* REG_MISTA fields */ | ||
135 | +/* Transmit Bus Error Interrupt */ | ||
136 | +#define REG_MISTA_TXBERR (1 << 24) | ||
137 | +/* Transmit Descriptor Unavailable Interrupt */ | ||
138 | +#define REG_MISTA_TDU (1 << 23) | ||
139 | +/* Transmit Completion Interrupt */ | ||
140 | +#define REG_MISTA_TXCP (1 << 18) | ||
141 | +/* Transmit Interrupt */ | ||
142 | +#define REG_MISTA_TXINTR (1 << 16) | ||
143 | +/* Receive Bus Error Interrupt */ | ||
144 | +#define REG_MISTA_RXBERR (1 << 11) | ||
145 | +/* Receive Descriptor Unavailable Interrupt */ | ||
146 | +#define REG_MISTA_RDU (1 << 10) | ||
147 | +/* DMA Early Notification Interrupt */ | ||
148 | +#define REG_MISTA_DENI (1 << 9) | ||
149 | +/* Maximum Frame Length Interrupt */ | ||
150 | +#define REG_MISTA_DFOI (1 << 8) | ||
151 | +/* Receive Good Interrupt */ | ||
152 | +#define REG_MISTA_RXGD (1 << 4) | ||
153 | +/* Packet Too Long Interrupt */ | ||
154 | +#define REG_MISTA_PTLE (1 << 3) | ||
155 | +/* Receive Interrupt */ | ||
156 | +#define REG_MISTA_RXINTR (1 << 0) | ||
157 | + | ||
158 | +typedef struct NPCM7xxEMCTxDesc NPCM7xxEMCTxDesc; | ||
159 | +typedef struct NPCM7xxEMCRxDesc NPCM7xxEMCRxDesc; | ||
160 | + | ||
161 | +struct NPCM7xxEMCTxDesc { | ||
162 | + uint32_t flags; | ||
163 | + uint32_t txbsa; | ||
164 | + uint32_t status_and_length; | ||
165 | + uint32_t ntxdsa; | ||
132 | +}; | 166 | +}; |
133 | + | 167 | + |
134 | +#define ASPEED_A7MPCORE_ADDR 0x40460000 | 168 | +struct NPCM7xxEMCRxDesc { |
135 | + | 169 | + uint32_t status_and_length; |
136 | +#define ASPEED_SOC_AST2600_MAX_IRQ 128 | 170 | + uint32_t rxbsa; |
137 | + | 171 | + uint32_t reserved; |
138 | +static const int aspeed_soc_ast2600_irqmap[] = { | 172 | + uint32_t nrxdsa; |
139 | + [ASPEED_UART1] = 47, | ||
140 | + [ASPEED_UART2] = 48, | ||
141 | + [ASPEED_UART3] = 49, | ||
142 | + [ASPEED_UART4] = 50, | ||
143 | + [ASPEED_UART5] = 8, | ||
144 | + [ASPEED_VUART] = 8, | ||
145 | + [ASPEED_FMC] = 39, | ||
146 | + [ASPEED_SDMC] = 0, | ||
147 | + [ASPEED_SCU] = 12, | ||
148 | + [ASPEED_ADC] = 78, | ||
149 | + [ASPEED_XDMA] = 6, | ||
150 | + [ASPEED_SDHCI] = 43, | ||
151 | + [ASPEED_GPIO] = 40, | ||
152 | + [ASPEED_GPIO_1_8V] = 11, | ||
153 | + [ASPEED_RTC] = 13, | ||
154 | + [ASPEED_TIMER1] = 16, | ||
155 | + [ASPEED_TIMER2] = 17, | ||
156 | + [ASPEED_TIMER3] = 18, | ||
157 | + [ASPEED_TIMER4] = 19, | ||
158 | + [ASPEED_TIMER5] = 20, | ||
159 | + [ASPEED_TIMER6] = 21, | ||
160 | + [ASPEED_TIMER7] = 22, | ||
161 | + [ASPEED_TIMER8] = 23, | ||
162 | + [ASPEED_WDT] = 24, | ||
163 | + [ASPEED_PWM] = 44, | ||
164 | + [ASPEED_LPC] = 35, | ||
165 | + [ASPEED_IBT] = 35, /* LPC */ | ||
166 | + [ASPEED_I2C] = 110, /* 110 -> 125 */ | ||
167 | + [ASPEED_ETH1] = 2, | ||
168 | + [ASPEED_ETH2] = 3, | ||
169 | +}; | 173 | +}; |
170 | + | 174 | + |
171 | +static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) | 175 | +/* NPCM7xxEMCTxDesc.flags values */ |
172 | +{ | 176 | +/* Owner: 0 = cpu, 1 = emc */ |
173 | + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | 177 | +#define TX_DESC_FLAG_OWNER_MASK (1 << 31) |
174 | + | 178 | +/* Transmit interrupt enable */ |
175 | + return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); | 179 | +#define TX_DESC_FLAG_INTEN (1 << 2) |
176 | +} | 180 | + |
177 | + | 181 | +/* NPCM7xxEMCTxDesc.status_and_length values */ |
178 | +static void aspeed_soc_ast2600_init(Object *obj) | 182 | +/* Transmission complete */ |
179 | +{ | 183 | +#define TX_DESC_STATUS_TXCP (1 << 19) |
180 | + AspeedSoCState *s = ASPEED_SOC(obj); | 184 | +/* Transmit interrupt */ |
181 | + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | 185 | +#define TX_DESC_STATUS_TXINTR (1 << 16) |
186 | + | ||
187 | +/* NPCM7xxEMCRxDesc.status_and_length values */ | ||
188 | +/* Owner: 0b00 = cpu, 0b10 = emc */ | ||
189 | +#define RX_DESC_STATUS_OWNER_SHIFT 30 | ||
190 | +#define RX_DESC_STATUS_OWNER_MASK 0xc0000000 | ||
191 | +/* Frame Reception Complete */ | ||
192 | +#define RX_DESC_STATUS_RXGD (1 << 20) | ||
193 | +/* Packet too long */ | ||
194 | +#define RX_DESC_STATUS_PTLE (1 << 19) | ||
195 | +/* Receive Interrupt */ | ||
196 | +#define RX_DESC_STATUS_RXINTR (1 << 16) | ||
197 | + | ||
198 | +#define RX_DESC_PKT_LEN(word) ((uint32_t) (word) & 0xffff) | ||
199 | + | ||
200 | +typedef struct EMCModule { | ||
201 | + int rx_irq; | ||
202 | + int tx_irq; | ||
203 | + uint64_t base_addr; | ||
204 | +} EMCModule; | ||
205 | + | ||
206 | +typedef struct TestData { | ||
207 | + const EMCModule *module; | ||
208 | +} TestData; | ||
209 | + | ||
210 | +static const EMCModule emc_module_list[] = { | ||
211 | + { | ||
212 | + .rx_irq = 15, | ||
213 | + .tx_irq = 16, | ||
214 | + .base_addr = 0xf0825000 | ||
215 | + }, | ||
216 | + { | ||
217 | + .rx_irq = 114, | ||
218 | + .tx_irq = 115, | ||
219 | + .base_addr = 0xf0826000 | ||
220 | + } | ||
221 | +}; | ||
222 | + | ||
223 | +/* Returns the index of the EMC module. */ | ||
224 | +static int emc_module_index(const EMCModule *mod) | ||
225 | +{ | ||
226 | + ptrdiff_t diff = mod - emc_module_list; | ||
227 | + | ||
228 | + g_assert_true(diff >= 0 && diff < ARRAY_SIZE(emc_module_list)); | ||
229 | + | ||
230 | + return diff; | ||
231 | +} | ||
232 | + | ||
233 | +static void packet_test_clear(void *sockets) | ||
234 | +{ | ||
235 | + int *test_sockets = sockets; | ||
236 | + | ||
237 | + close(test_sockets[0]); | ||
238 | + g_free(test_sockets); | ||
239 | +} | ||
240 | + | ||
241 | +static int *packet_test_init(int module_num, GString *cmd_line) | ||
242 | +{ | ||
243 | + int *test_sockets = g_new(int, 2); | ||
244 | + int ret = socketpair(PF_UNIX, SOCK_STREAM, 0, test_sockets); | ||
245 | + g_assert_cmpint(ret, != , -1); | ||
246 | + | ||
247 | + /* | ||
248 | + * KISS and use -nic. We specify two nics (both emc{0,1}) because there's | ||
249 | + * currently no way to specify only emc1: The driver implicitly relies on | ||
250 | + * emc[i] == nd_table[i]. | ||
251 | + */ | ||
252 | + if (module_num == 0) { | ||
253 | + g_string_append_printf(cmd_line, | ||
254 | + " -nic socket,fd=%d,model=" TYPE_NPCM7XX_EMC " " | ||
255 | + " -nic user,model=" TYPE_NPCM7XX_EMC " ", | ||
256 | + test_sockets[1]); | ||
257 | + } else { | ||
258 | + g_string_append_printf(cmd_line, | ||
259 | + " -nic user,model=" TYPE_NPCM7XX_EMC " " | ||
260 | + " -nic socket,fd=%d,model=" TYPE_NPCM7XX_EMC " ", | ||
261 | + test_sockets[1]); | ||
262 | + } | ||
263 | + | ||
264 | + g_test_queue_destroy(packet_test_clear, test_sockets); | ||
265 | + return test_sockets; | ||
266 | +} | ||
267 | + | ||
268 | +static uint32_t emc_read(QTestState *qts, const EMCModule *mod, | ||
269 | + NPCM7xxPWMRegister regno) | ||
270 | +{ | ||
271 | + return qtest_readl(qts, mod->base_addr + regno * sizeof(uint32_t)); | ||
272 | +} | ||
273 | + | ||
274 | +static void emc_write(QTestState *qts, const EMCModule *mod, | ||
275 | + NPCM7xxPWMRegister regno, uint32_t value) | ||
276 | +{ | ||
277 | + qtest_writel(qts, mod->base_addr + regno * sizeof(uint32_t), value); | ||
278 | +} | ||
279 | + | ||
280 | +static void emc_read_tx_desc(QTestState *qts, uint32_t addr, | ||
281 | + NPCM7xxEMCTxDesc *desc) | ||
282 | +{ | ||
283 | + qtest_memread(qts, addr, desc, sizeof(*desc)); | ||
284 | + desc->flags = le32_to_cpu(desc->flags); | ||
285 | + desc->txbsa = le32_to_cpu(desc->txbsa); | ||
286 | + desc->status_and_length = le32_to_cpu(desc->status_and_length); | ||
287 | + desc->ntxdsa = le32_to_cpu(desc->ntxdsa); | ||
288 | +} | ||
289 | + | ||
290 | +static void emc_write_tx_desc(QTestState *qts, const NPCM7xxEMCTxDesc *desc, | ||
291 | + uint32_t addr) | ||
292 | +{ | ||
293 | + NPCM7xxEMCTxDesc le_desc; | ||
294 | + | ||
295 | + le_desc.flags = cpu_to_le32(desc->flags); | ||
296 | + le_desc.txbsa = cpu_to_le32(desc->txbsa); | ||
297 | + le_desc.status_and_length = cpu_to_le32(desc->status_and_length); | ||
298 | + le_desc.ntxdsa = cpu_to_le32(desc->ntxdsa); | ||
299 | + qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc)); | ||
300 | +} | ||
301 | + | ||
302 | +static void emc_read_rx_desc(QTestState *qts, uint32_t addr, | ||
303 | + NPCM7xxEMCRxDesc *desc) | ||
304 | +{ | ||
305 | + qtest_memread(qts, addr, desc, sizeof(*desc)); | ||
306 | + desc->status_and_length = le32_to_cpu(desc->status_and_length); | ||
307 | + desc->rxbsa = le32_to_cpu(desc->rxbsa); | ||
308 | + desc->reserved = le32_to_cpu(desc->reserved); | ||
309 | + desc->nrxdsa = le32_to_cpu(desc->nrxdsa); | ||
310 | +} | ||
311 | + | ||
312 | +static void emc_write_rx_desc(QTestState *qts, const NPCM7xxEMCRxDesc *desc, | ||
313 | + uint32_t addr) | ||
314 | +{ | ||
315 | + NPCM7xxEMCRxDesc le_desc; | ||
316 | + | ||
317 | + le_desc.status_and_length = cpu_to_le32(desc->status_and_length); | ||
318 | + le_desc.rxbsa = cpu_to_le32(desc->rxbsa); | ||
319 | + le_desc.reserved = cpu_to_le32(desc->reserved); | ||
320 | + le_desc.nrxdsa = cpu_to_le32(desc->nrxdsa); | ||
321 | + qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc)); | ||
322 | +} | ||
323 | + | ||
324 | +/* | ||
325 | + * Reset the EMC module. | ||
326 | + * The module must be reset before, e.g., TXDLSA,RXDLSA are changed. | ||
327 | + */ | ||
328 | +static bool emc_soft_reset(QTestState *qts, const EMCModule *mod) | ||
329 | +{ | ||
330 | + uint32_t val; | ||
331 | + uint64_t end_time; | ||
332 | + | ||
333 | + emc_write(qts, mod, REG_MCMDR, REG_MCMDR_SWR); | ||
334 | + | ||
335 | + /* | ||
336 | + * Wait for device to reset as the linux driver does. | ||
337 | + * During reset the AHB reads 0 for all registers. So first wait for | ||
338 | + * something that resets to non-zero, and then wait for SWR becoming 0. | ||
339 | + */ | ||
340 | + end_time = g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND; | ||
341 | + | ||
342 | + do { | ||
343 | + qtest_clock_step(qts, 100); | ||
344 | + val = emc_read(qts, mod, REG_FFTCR); | ||
345 | + } while (val == 0 && g_get_monotonic_time() < end_time); | ||
346 | + if (val != 0) { | ||
347 | + do { | ||
348 | + qtest_clock_step(qts, 100); | ||
349 | + val = emc_read(qts, mod, REG_MCMDR); | ||
350 | + if ((val & REG_MCMDR_SWR) == 0) { | ||
351 | + /* | ||
352 | + * N.B. The CAMs have been reset here, so macaddr matching of | ||
353 | + * incoming packets will not work. | ||
354 | + */ | ||
355 | + return true; | ||
356 | + } | ||
357 | + } while (g_get_monotonic_time() < end_time); | ||
358 | + } | ||
359 | + | ||
360 | + g_message("%s: Timeout expired", __func__); | ||
361 | + return false; | ||
362 | +} | ||
363 | + | ||
364 | +/* Check emc registers are reset to default value. */ | ||
365 | +static void test_init(gconstpointer test_data) | ||
366 | +{ | ||
367 | + const TestData *td = test_data; | ||
368 | + const EMCModule *mod = td->module; | ||
369 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
182 | + int i; | 370 | + int i; |
183 | + char socname[8]; | 371 | + |
184 | + char typename[64]; | 372 | +#define CHECK_REG(regno, value) \ |
185 | + | 373 | + do { \ |
186 | + if (sscanf(sc->name, "%7s", socname) != 1) { | 374 | + g_assert_cmphex(emc_read(qts, mod, (regno)), ==, (value)); \ |
187 | + g_assert_not_reached(); | 375 | + } while (0) |
188 | + } | 376 | + |
189 | + | 377 | + CHECK_REG(REG_CAMCMR, 0); |
190 | + for (i = 0; i < sc->num_cpus; i++) { | 378 | + CHECK_REG(REG_CAMEN, 0); |
191 | + object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), | 379 | + CHECK_REG(REG_TXDLSA, 0xfffffffc); |
192 | + sizeof(s->cpu[i]), sc->cpu_type, | 380 | + CHECK_REG(REG_RXDLSA, 0xfffffffc); |
193 | + &error_abort, NULL); | 381 | + CHECK_REG(REG_MCMDR, 0); |
194 | + } | 382 | + CHECK_REG(REG_MIID, 0); |
195 | + | 383 | + CHECK_REG(REG_MIIDA, 0x00900000); |
196 | + snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); | 384 | + CHECK_REG(REG_FFTCR, 0x0101); |
197 | + sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu), | 385 | + CHECK_REG(REG_DMARFC, 0x0800); |
198 | + typename); | 386 | + CHECK_REG(REG_MIEN, 0); |
199 | + qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", | 387 | + CHECK_REG(REG_MISTA, 0); |
200 | + sc->silicon_rev); | 388 | + CHECK_REG(REG_MGSTA, 0); |
201 | + object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), | 389 | + CHECK_REG(REG_MPCNT, 0x7fff); |
202 | + "hw-strap1", &error_abort); | 390 | + CHECK_REG(REG_MRPC, 0); |
203 | + object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), | 391 | + CHECK_REG(REG_MRPCC, 0); |
204 | + "hw-strap2", &error_abort); | 392 | + CHECK_REG(REG_MREPC, 0); |
205 | + object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), | 393 | + CHECK_REG(REG_DMARFS, 0); |
206 | + "hw-prot-key", &error_abort); | 394 | + CHECK_REG(REG_CTXDSA, 0); |
207 | + | 395 | + CHECK_REG(REG_CTXBSA, 0); |
208 | + sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, | 396 | + CHECK_REG(REG_CRXDSA, 0); |
209 | + sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV); | 397 | + CHECK_REG(REG_CRXBSA, 0); |
210 | + | 398 | + |
211 | + sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc), | 399 | +#undef CHECK_REG |
212 | + TYPE_ASPEED_RTC); | 400 | + |
213 | + | 401 | + for (i = 0; i < NUM_CAMML_REGS; ++i) { |
214 | + snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); | 402 | + g_assert_cmpuint(emc_read(qts, mod, REG_CAMM_BASE + i * 2), ==, |
215 | + sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl), | 403 | + 0); |
216 | + sizeof(s->timerctrl), typename); | 404 | + g_assert_cmpuint(emc_read(qts, mod, REG_CAML_BASE + i * 2), ==, |
217 | + object_property_add_const_link(OBJECT(&s->timerctrl), "scu", | 405 | + 0); |
218 | + OBJECT(&s->scu), &error_abort); | 406 | + } |
219 | + | 407 | + |
220 | + snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); | 408 | + qtest_quit(qts); |
221 | + sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c), | 409 | +} |
222 | + typename); | 410 | + |
223 | + | 411 | +static bool emc_wait_irq(QTestState *qts, const EMCModule *mod, int step, |
224 | + snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); | 412 | + bool is_tx) |
225 | + sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc), | 413 | +{ |
226 | + typename); | 414 | + uint64_t end_time = |
227 | + object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs", | 415 | + g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND; |
228 | + &error_abort); | 416 | + |
229 | + object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram", | 417 | + do { |
230 | + &error_abort); | 418 | + if (qtest_get_irq(qts, is_tx ? mod->tx_irq : mod->rx_irq)) { |
231 | + | 419 | + return true; |
232 | + for (i = 0; i < sc->spis_num; i++) { | ||
233 | + snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); | ||
234 | + sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]), | ||
235 | + sizeof(s->spi[i]), typename); | ||
236 | + } | ||
237 | + | ||
238 | + snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); | ||
239 | + sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc), | ||
240 | + typename); | ||
241 | + object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), | ||
242 | + "ram-size", &error_abort); | ||
243 | + object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), | ||
244 | + "max-ram-size", &error_abort); | ||
245 | + | ||
246 | + for (i = 0; i < sc->wdts_num; i++) { | ||
247 | + snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); | ||
248 | + sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]), | ||
249 | + sizeof(s->wdt[i]), typename); | ||
250 | + object_property_add_const_link(OBJECT(&s->wdt[i]), "scu", | ||
251 | + OBJECT(&s->scu), &error_abort); | ||
252 | + } | ||
253 | + | ||
254 | + for (i = 0; i < ASPEED_MACS_NUM; i++) { | ||
255 | + sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]), | ||
256 | + sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); | ||
257 | + } | ||
258 | + | ||
259 | + sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma), | ||
260 | + TYPE_ASPEED_XDMA); | ||
261 | + | ||
262 | + snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); | ||
263 | + sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio), | ||
264 | + typename); | ||
265 | + | ||
266 | + snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); | ||
267 | + sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v), | ||
268 | + sizeof(s->gpio_1_8v), typename); | ||
269 | + | ||
270 | + sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), | ||
271 | + TYPE_ASPEED_SDHCI); | ||
272 | + | ||
273 | + /* Init sd card slot class here so that they're under the correct parent */ | ||
274 | + for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | ||
275 | + sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), | ||
276 | + sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); | ||
277 | + } | ||
278 | +} | ||
279 | + | ||
280 | +/* | ||
281 | + * ASPEED ast2600 has 0xf as cluster ID | ||
282 | + * | ||
283 | + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html | ||
284 | + */ | ||
285 | +static uint64_t aspeed_calc_affinity(int cpu) | ||
286 | +{ | ||
287 | + return (0xf << ARM_AFF1_SHIFT) | cpu; | ||
288 | +} | ||
289 | + | ||
290 | +static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | ||
291 | +{ | ||
292 | + int i; | ||
293 | + AspeedSoCState *s = ASPEED_SOC(dev); | ||
294 | + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
295 | + Error *err = NULL, *local_err = NULL; | ||
296 | + qemu_irq irq; | ||
297 | + | ||
298 | + /* IO space */ | ||
299 | + create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], | ||
300 | + ASPEED_SOC_IOMEM_SIZE); | ||
301 | + | ||
302 | + if (s->num_cpus > sc->num_cpus) { | ||
303 | + warn_report("%s: invalid number of CPUs %d, using default %d", | ||
304 | + sc->name, s->num_cpus, sc->num_cpus); | ||
305 | + s->num_cpus = sc->num_cpus; | ||
306 | + } | ||
307 | + | ||
308 | + /* CPU */ | ||
309 | + for (i = 0; i < s->num_cpus; i++) { | ||
310 | + object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC, | ||
311 | + "psci-conduit", &error_abort); | ||
312 | + if (s->num_cpus > 1) { | ||
313 | + object_property_set_int(OBJECT(&s->cpu[i]), | ||
314 | + ASPEED_A7MPCORE_ADDR, | ||
315 | + "reset-cbar", &error_abort); | ||
316 | + } | 420 | + } |
317 | + object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i), | 421 | + qtest_clock_step(qts, step); |
318 | + "mp-affinity", &error_abort); | 422 | + } while (g_get_monotonic_time() < end_time); |
319 | + | 423 | + |
320 | + /* | 424 | + g_message("%s: Timeout expired", __func__); |
321 | + * TODO: the secondary CPUs are started and a boot helper | 425 | + return false; |
322 | + * is needed when using -kernel | 426 | +} |
323 | + */ | 427 | + |
324 | + | 428 | +static bool emc_wait_mista(QTestState *qts, const EMCModule *mod, int step, |
325 | + object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); | 429 | + uint32_t flag) |
326 | + if (err) { | 430 | +{ |
327 | + error_propagate(errp, err); | 431 | + uint64_t end_time = |
328 | + return; | 432 | + g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND; |
433 | + | ||
434 | + do { | ||
435 | + uint32_t mista = emc_read(qts, mod, REG_MISTA); | ||
436 | + if (mista & flag) { | ||
437 | + return true; | ||
329 | + } | 438 | + } |
330 | + } | 439 | + qtest_clock_step(qts, step); |
331 | + | 440 | + } while (g_get_monotonic_time() < end_time); |
332 | + /* A7MPCORE */ | 441 | + |
333 | + object_property_set_int(OBJECT(&s->a7mpcore), s->num_cpus, "num-cpu", | 442 | + g_message("%s: Timeout expired", __func__); |
334 | + &error_abort); | 443 | + return false; |
335 | + object_property_set_int(OBJECT(&s->a7mpcore), | 444 | +} |
336 | + ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL, | 445 | + |
337 | + "num-irq", &error_abort); | 446 | +static bool wait_socket_readable(int fd) |
338 | + | 447 | +{ |
339 | + object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized", | 448 | + fd_set read_fds; |
340 | + &error_abort); | 449 | + struct timeval tv; |
341 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); | 450 | + int rv; |
342 | + | 451 | + |
343 | + for (i = 0; i < s->num_cpus; i++) { | 452 | + FD_ZERO(&read_fds); |
344 | + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); | 453 | + FD_SET(fd, &read_fds); |
345 | + DeviceState *d = DEVICE(qemu_get_cpu(i)); | 454 | + tv.tv_sec = TIMEOUT_SECONDS; |
346 | + | 455 | + tv.tv_usec = 0; |
347 | + irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); | 456 | + rv = select(fd + 1, &read_fds, NULL, NULL, &tv); |
348 | + sysbus_connect_irq(sbd, i, irq); | 457 | + if (rv == -1) { |
349 | + irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); | 458 | + perror("select"); |
350 | + sysbus_connect_irq(sbd, i + s->num_cpus, irq); | 459 | + } else if (rv == 0) { |
351 | + irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); | 460 | + g_message("%s: Timeout expired", __func__); |
352 | + sysbus_connect_irq(sbd, i + 2 * s->num_cpus, irq); | 461 | + } |
353 | + irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); | 462 | + return rv == 1; |
354 | + sysbus_connect_irq(sbd, i + 3 * s->num_cpus, irq); | 463 | +} |
355 | + } | 464 | + |
356 | + | 465 | +/* Initialize *desc (in host endian format). */ |
357 | + /* SRAM */ | 466 | +static void init_tx_desc(NPCM7xxEMCTxDesc *desc, size_t count, |
358 | + memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", | 467 | + uint32_t desc_addr) |
359 | + sc->sram_size, &err); | 468 | +{ |
360 | + if (err) { | 469 | + g_assert(count >= 2); |
361 | + error_propagate(errp, err); | 470 | + memset(&desc[0], 0, sizeof(*desc) * count); |
362 | + return; | 471 | + /* Leave the last one alone, owned by the cpu -> stops transmission. */ |
363 | + } | 472 | + for (size_t i = 0; i < count - 1; ++i) { |
364 | + memory_region_add_subregion(get_system_memory(), | 473 | + desc[i].flags = |
365 | + sc->memmap[ASPEED_SRAM], &s->sram); | 474 | + (TX_DESC_FLAG_OWNER_MASK | /* owner = 1: emc */ |
366 | + | 475 | + TX_DESC_FLAG_INTEN | |
367 | + /* SCU */ | 476 | + 0 | /* crc append = 0 */ |
368 | + object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); | 477 | + 0 /* padding enable = 0 */); |
369 | + if (err) { | 478 | + desc[i].status_and_length = |
370 | + error_propagate(errp, err); | 479 | + (0 | /* collision count = 0 */ |
371 | + return; | 480 | + 0 | /* SQE = 0 */ |
372 | + } | 481 | + 0 | /* PAU = 0 */ |
373 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]); | 482 | + 0 | /* TXHA = 0 */ |
374 | + | 483 | + 0 | /* LC = 0 */ |
375 | + /* RTC */ | 484 | + 0 | /* TXABT = 0 */ |
376 | + object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); | 485 | + 0 | /* NCS = 0 */ |
377 | + if (err) { | 486 | + 0 | /* EXDEF = 0 */ |
378 | + error_propagate(errp, err); | 487 | + 0 | /* TXCP = 0 */ |
379 | + return; | 488 | + 0 | /* DEF = 0 */ |
380 | + } | 489 | + 0 | /* TXINTR = 0 */ |
381 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]); | 490 | + 0 /* length filled in later */); |
382 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, | 491 | + desc[i].ntxdsa = desc_addr + (i + 1) * sizeof(*desc); |
383 | + aspeed_soc_get_irq(s, ASPEED_RTC)); | 492 | + } |
384 | + | 493 | +} |
385 | + /* Timer */ | 494 | + |
386 | + object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err); | 495 | +static void enable_tx(QTestState *qts, const EMCModule *mod, |
387 | + if (err) { | 496 | + const NPCM7xxEMCTxDesc *desc, size_t count, |
388 | + error_propagate(errp, err); | 497 | + uint32_t desc_addr, uint32_t mien_flags) |
389 | + return; | 498 | +{ |
390 | + } | 499 | + /* Write the descriptors to guest memory. */ |
391 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, | 500 | + for (size_t i = 0; i < count; ++i) { |
392 | + sc->memmap[ASPEED_TIMER1]); | 501 | + emc_write_tx_desc(qts, desc + i, desc_addr + i * sizeof(*desc)); |
393 | + for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { | 502 | + } |
394 | + qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); | 503 | + |
395 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); | 504 | + /* Trigger sending the packet. */ |
396 | + } | 505 | + /* The module must be reset before changing TXDLSA. */ |
397 | + | 506 | + g_assert(emc_soft_reset(qts, mod)); |
398 | + /* UART - attach an 8250 to the IO space as our UART5 */ | 507 | + emc_write(qts, mod, REG_TXDLSA, desc_addr); |
399 | + if (serial_hd(0)) { | 508 | + emc_write(qts, mod, REG_CTXDSA, ~0); |
400 | + qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5); | 509 | + emc_write(qts, mod, REG_MIEN, REG_MIEN_ENTXCP | mien_flags); |
401 | + serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2, | 510 | + { |
402 | + uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); | 511 | + uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR); |
403 | + } | 512 | + mcmdr |= REG_MCMDR_TXON; |
404 | + | 513 | + emc_write(qts, mod, REG_MCMDR, mcmdr); |
405 | + /* I2C */ | 514 | + } |
406 | + object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err); | 515 | + |
407 | + if (err) { | 516 | + /* Prod the device to send the packet. */ |
408 | + error_propagate(errp, err); | 517 | + emc_write(qts, mod, REG_TSDR, 1); |
409 | + return; | 518 | +} |
410 | + } | 519 | + |
411 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]); | 520 | +static void emc_send_verify1(QTestState *qts, const EMCModule *mod, int fd, |
412 | + for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { | 521 | + bool with_irq, uint32_t desc_addr, |
413 | + qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), | 522 | + uint32_t next_desc_addr, |
414 | + sc->irqmap[ASPEED_I2C] + i); | 523 | + const char *test_data, int test_size) |
415 | + /* | 524 | +{ |
416 | + * The AST2600 SoC has one IRQ per I2C bus. Skip the common | 525 | + NPCM7xxEMCTxDesc result_desc; |
417 | + * IRQ (AST2400 and AST2500) and connect all bussses. | 526 | + uint32_t expected_mask, expected_value, recv_len; |
418 | + */ | 527 | + int ret; |
419 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq); | 528 | + char buffer[TX_DATA_LEN]; |
420 | + } | 529 | + |
421 | + | 530 | + g_assert(wait_socket_readable(fd)); |
422 | + /* FMC, The number of CS is set at the board level */ | 531 | + |
423 | + object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], | 532 | + /* Read the descriptor back. */ |
424 | + "sdram-base", &err); | 533 | + emc_read_tx_desc(qts, desc_addr, &result_desc); |
425 | + if (err) { | 534 | + /* Descriptor should be owned by cpu now. */ |
426 | + error_propagate(errp, err); | 535 | + g_assert((result_desc.flags & TX_DESC_FLAG_OWNER_MASK) == 0); |
427 | + return; | 536 | + /* Test the status bits, ignoring the length field. */ |
428 | + } | 537 | + expected_mask = 0xffff << 16; |
429 | + object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); | 538 | + expected_value = TX_DESC_STATUS_TXCP; |
430 | + if (err) { | 539 | + if (with_irq) { |
431 | + error_propagate(errp, err); | 540 | + expected_value |= TX_DESC_STATUS_TXINTR; |
432 | + return; | 541 | + } |
433 | + } | 542 | + g_assert_cmphex((result_desc.status_and_length & expected_mask), ==, |
434 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]); | 543 | + expected_value); |
435 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, | 544 | + |
436 | + s->fmc.ctrl->flash_window_base); | 545 | + /* Check data sent to the backend. */ |
437 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, | 546 | + recv_len = ~0; |
438 | + aspeed_soc_get_irq(s, ASPEED_FMC)); | 547 | + ret = qemu_recv(fd, &recv_len, sizeof(recv_len), MSG_DONTWAIT); |
439 | + | 548 | + g_assert_cmpint(ret, == , sizeof(recv_len)); |
440 | + /* SPI */ | 549 | + |
441 | + for (i = 0; i < sc->spis_num; i++) { | 550 | + g_assert(wait_socket_readable(fd)); |
442 | + object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err); | 551 | + memset(buffer, 0xff, sizeof(buffer)); |
443 | + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", | 552 | + ret = qemu_recv(fd, buffer, test_size, MSG_DONTWAIT); |
444 | + &local_err); | 553 | + g_assert_cmpmem(buffer, ret, test_data, test_size); |
445 | + error_propagate(&err, local_err); | 554 | +} |
446 | + if (err) { | 555 | + |
447 | + error_propagate(errp, err); | 556 | +static void emc_send_verify(QTestState *qts, const EMCModule *mod, int fd, |
448 | + return; | 557 | + bool with_irq) |
558 | +{ | ||
559 | + NPCM7xxEMCTxDesc desc[NUM_TX_DESCRIPTORS]; | ||
560 | + uint32_t desc_addr = DESC_ADDR; | ||
561 | + static const char test1_data[] = "TEST1"; | ||
562 | + static const char test2_data[] = "Testing 1 2 3 ..."; | ||
563 | + uint32_t data1_addr = DATA_ADDR; | ||
564 | + uint32_t data2_addr = data1_addr + sizeof(test1_data); | ||
565 | + bool got_tdu; | ||
566 | + uint32_t end_desc_addr; | ||
567 | + | ||
568 | + /* Prepare test data buffer. */ | ||
569 | + qtest_memwrite(qts, data1_addr, test1_data, sizeof(test1_data)); | ||
570 | + qtest_memwrite(qts, data2_addr, test2_data, sizeof(test2_data)); | ||
571 | + | ||
572 | + init_tx_desc(&desc[0], NUM_TX_DESCRIPTORS, desc_addr); | ||
573 | + desc[0].txbsa = data1_addr; | ||
574 | + desc[0].status_and_length |= sizeof(test1_data); | ||
575 | + desc[1].txbsa = data2_addr; | ||
576 | + desc[1].status_and_length |= sizeof(test2_data); | ||
577 | + | ||
578 | + enable_tx(qts, mod, &desc[0], NUM_TX_DESCRIPTORS, desc_addr, | ||
579 | + with_irq ? REG_MIEN_ENTXINTR : 0); | ||
580 | + | ||
581 | + /* | ||
582 | + * It's problematic to observe the interrupt for each packet. | ||
583 | + * Instead just wait until all the packets go out. | ||
584 | + */ | ||
585 | + got_tdu = false; | ||
586 | + while (!got_tdu) { | ||
587 | + if (with_irq) { | ||
588 | + g_assert_true(emc_wait_irq(qts, mod, TX_STEP_COUNT, | ||
589 | + /*is_tx=*/true)); | ||
590 | + } else { | ||
591 | + g_assert_true(emc_wait_mista(qts, mod, TX_STEP_COUNT, | ||
592 | + REG_MISTA_TXINTR)); | ||
449 | + } | 593 | + } |
450 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, | 594 | + got_tdu = !!(emc_read(qts, mod, REG_MISTA) & REG_MISTA_TDU); |
451 | + sc->memmap[ASPEED_SPI1 + i]); | 595 | + /* If we don't have TDU yet, reset the interrupt. */ |
452 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, | 596 | + if (!got_tdu) { |
453 | + s->spi[i].ctrl->flash_window_base); | 597 | + emc_write(qts, mod, REG_MISTA, |
454 | + } | 598 | + emc_read(qts, mod, REG_MISTA) & 0xffff0000); |
455 | + | ||
456 | + /* SDMC - SDRAM Memory Controller */ | ||
457 | + object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); | ||
458 | + if (err) { | ||
459 | + error_propagate(errp, err); | ||
460 | + return; | ||
461 | + } | ||
462 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]); | ||
463 | + | ||
464 | + /* Watch dog */ | ||
465 | + for (i = 0; i < sc->wdts_num; i++) { | ||
466 | + AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); | ||
467 | + | ||
468 | + object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); | ||
469 | + if (err) { | ||
470 | + error_propagate(errp, err); | ||
471 | + return; | ||
472 | + } | 599 | + } |
473 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | 600 | + } |
474 | + sc->memmap[ASPEED_WDT] + i * awc->offset); | 601 | + |
475 | + } | 602 | + end_desc_addr = desc_addr + 2 * sizeof(desc[0]); |
476 | + | 603 | + g_assert_cmphex(emc_read(qts, mod, REG_CTXDSA), ==, end_desc_addr); |
477 | + /* Net */ | 604 | + g_assert_cmphex(emc_read(qts, mod, REG_MISTA), ==, |
478 | + for (i = 0; i < nb_nics; i++) { | 605 | + REG_MISTA_TXCP | REG_MISTA_TXINTR | REG_MISTA_TDU); |
479 | + qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]); | 606 | + |
480 | + object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", | 607 | + emc_send_verify1(qts, mod, fd, with_irq, |
481 | + &err); | 608 | + desc_addr, end_desc_addr, |
482 | + object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized", | 609 | + test1_data, sizeof(test1_data)); |
483 | + &local_err); | 610 | + emc_send_verify1(qts, mod, fd, with_irq, |
484 | + error_propagate(&err, local_err); | 611 | + desc_addr + sizeof(desc[0]), end_desc_addr, |
485 | + if (err) { | 612 | + test2_data, sizeof(test2_data)); |
486 | + error_propagate(errp, err); | 613 | +} |
487 | + return; | 614 | + |
488 | + } | 615 | +/* Initialize *desc (in host endian format). */ |
489 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | 616 | +static void init_rx_desc(NPCM7xxEMCRxDesc *desc, size_t count, |
490 | + sc->memmap[ASPEED_ETH1 + i]); | 617 | + uint32_t desc_addr, uint32_t data_addr) |
491 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | 618 | +{ |
492 | + aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); | 619 | + g_assert_true(count >= 2); |
493 | + } | 620 | + memset(desc, 0, sizeof(*desc) * count); |
494 | + | 621 | + desc[0].rxbsa = data_addr; |
495 | + /* XDMA */ | 622 | + desc[0].status_and_length = |
496 | + object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err); | 623 | + (0b10 << RX_DESC_STATUS_OWNER_SHIFT | /* owner = 10: emc */ |
497 | + if (err) { | 624 | + 0 | /* RP = 0 */ |
498 | + error_propagate(errp, err); | 625 | + 0 | /* ALIE = 0 */ |
499 | + return; | 626 | + 0 | /* RXGD = 0 */ |
500 | + } | 627 | + 0 | /* PTLE = 0 */ |
501 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, | 628 | + 0 | /* CRCE = 0 */ |
502 | + sc->memmap[ASPEED_XDMA]); | 629 | + 0 | /* RXINTR = 0 */ |
503 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, | 630 | + 0 /* length (filled in later) */); |
504 | + aspeed_soc_get_irq(s, ASPEED_XDMA)); | 631 | + /* Leave the last one alone, owned by the cpu -> stops transmission. */ |
505 | + | 632 | + desc[0].nrxdsa = desc_addr + sizeof(*desc); |
506 | + /* GPIO */ | 633 | +} |
507 | + object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); | 634 | + |
508 | + if (err) { | 635 | +static void enable_rx(QTestState *qts, const EMCModule *mod, |
509 | + error_propagate(errp, err); | 636 | + const NPCM7xxEMCRxDesc *desc, size_t count, |
510 | + return; | 637 | + uint32_t desc_addr, uint32_t mien_flags, |
511 | + } | 638 | + uint32_t mcmdr_flags) |
512 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]); | 639 | +{ |
513 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, | 640 | + /* |
514 | + aspeed_soc_get_irq(s, ASPEED_GPIO)); | 641 | + * Write the descriptor to guest memory. |
515 | + | 642 | + * FWIW, IWBN if the docs said the buffer needs to be at least DMARFC |
516 | + object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err); | 643 | + * bytes. |
517 | + if (err) { | 644 | + */ |
518 | + error_propagate(errp, err); | 645 | + for (size_t i = 0; i < count; ++i) { |
519 | + return; | 646 | + emc_write_rx_desc(qts, desc + i, desc_addr + i * sizeof(*desc)); |
520 | + } | 647 | + } |
521 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, | 648 | + |
522 | + sc->memmap[ASPEED_GPIO_1_8V]); | 649 | + /* Trigger receiving the packet. */ |
523 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, | 650 | + /* The module must be reset before changing RXDLSA. */ |
524 | + aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V)); | 651 | + g_assert(emc_soft_reset(qts, mod)); |
525 | + | 652 | + emc_write(qts, mod, REG_RXDLSA, desc_addr); |
526 | + /* SDHCI */ | 653 | + emc_write(qts, mod, REG_MIEN, REG_MIEN_ENRXGD | mien_flags); |
527 | + object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err); | 654 | + |
528 | + if (err) { | 655 | + /* |
529 | + error_propagate(errp, err); | 656 | + * We don't know what the device's macaddr is, so just accept all |
530 | + return; | 657 | + * unicast packets (AUP). |
531 | + } | 658 | + */ |
532 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, | 659 | + emc_write(qts, mod, REG_CAMCMR, REG_CAMCMR_AUP); |
533 | + sc->memmap[ASPEED_SDHCI]); | 660 | + emc_write(qts, mod, REG_CAMEN, 1 << 0); |
534 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, | 661 | + { |
535 | + aspeed_soc_get_irq(s, ASPEED_SDHCI)); | 662 | + uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR); |
536 | +} | 663 | + mcmdr |= REG_MCMDR_RXON | mcmdr_flags; |
537 | + | 664 | + emc_write(qts, mod, REG_MCMDR, mcmdr); |
538 | +static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) | 665 | + } |
539 | +{ | 666 | + |
540 | + DeviceClass *dc = DEVICE_CLASS(oc); | 667 | + /* Prod the device to accept a packet. */ |
541 | + AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | 668 | + emc_write(qts, mod, REG_RSDR, 1); |
542 | + | 669 | +} |
543 | + dc->realize = aspeed_soc_ast2600_realize; | 670 | + |
544 | + | 671 | +static void emc_recv_verify(QTestState *qts, const EMCModule *mod, int fd, |
545 | + sc->name = "ast2600-a0"; | 672 | + bool with_irq) |
546 | + sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); | 673 | +{ |
547 | + sc->silicon_rev = AST2600_A0_SILICON_REV; | 674 | + NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS]; |
548 | + sc->sram_size = 0x10000; | 675 | + uint32_t desc_addr = DESC_ADDR; |
549 | + sc->spis_num = 2; | 676 | + uint32_t data_addr = DATA_ADDR; |
550 | + sc->wdts_num = 4; | 677 | + int ret; |
551 | + sc->irqmap = aspeed_soc_ast2600_irqmap; | 678 | + uint32_t expected_mask, expected_value; |
552 | + sc->memmap = aspeed_soc_ast2600_memmap; | 679 | + NPCM7xxEMCRxDesc result_desc; |
553 | + sc->num_cpus = 2; | 680 | + |
554 | +} | 681 | + /* Prepare test data buffer. */ |
555 | + | 682 | + const char test[RX_DATA_LEN] = "TEST"; |
556 | +static const TypeInfo aspeed_soc_ast2600_type_info = { | 683 | + int len = htonl(sizeof(test)); |
557 | + .name = "ast2600-a0", | 684 | + const struct iovec iov[] = { |
558 | + .parent = TYPE_ASPEED_SOC, | 685 | + { |
559 | + .instance_size = sizeof(AspeedSoCState), | 686 | + .iov_base = &len, |
560 | + .instance_init = aspeed_soc_ast2600_init, | 687 | + .iov_len = sizeof(len), |
561 | + .class_init = aspeed_soc_ast2600_class_init, | 688 | + },{ |
562 | + .class_size = sizeof(AspeedSoCClass), | 689 | + .iov_base = (char *) test, |
563 | +}; | 690 | + .iov_len = sizeof(test), |
564 | + | 691 | + }, |
565 | +static void aspeed_soc_register_types(void) | 692 | + }; |
566 | +{ | 693 | + |
567 | + type_register_static(&aspeed_soc_ast2600_type_info); | 694 | + /* |
568 | +}; | 695 | + * Reset the device BEFORE sending a test packet, otherwise the packet |
569 | + | 696 | + * may get swallowed by an active device of an earlier test. |
570 | +type_init(aspeed_soc_register_types) | 697 | + */ |
698 | + init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr); | ||
699 | + enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr, | ||
700 | + with_irq ? REG_MIEN_ENRXINTR : 0, 0); | ||
701 | + | ||
702 | + /* Send test packet to device's socket. */ | ||
703 | + ret = iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test)); | ||
704 | + g_assert_cmpint(ret, == , sizeof(test) + sizeof(len)); | ||
705 | + | ||
706 | + /* Wait for RX interrupt. */ | ||
707 | + if (with_irq) { | ||
708 | + g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false)); | ||
709 | + } else { | ||
710 | + g_assert_true(emc_wait_mista(qts, mod, RX_STEP_COUNT, REG_MISTA_RXGD)); | ||
711 | + } | ||
712 | + | ||
713 | + g_assert_cmphex(emc_read(qts, mod, REG_CRXDSA), ==, | ||
714 | + desc_addr + sizeof(desc[0])); | ||
715 | + | ||
716 | + expected_mask = 0xffff; | ||
717 | + expected_value = (REG_MISTA_DENI | | ||
718 | + REG_MISTA_RXGD | | ||
719 | + REG_MISTA_RXINTR); | ||
720 | + g_assert_cmphex((emc_read(qts, mod, REG_MISTA) & expected_mask), | ||
721 | + ==, expected_value); | ||
722 | + | ||
723 | + /* Read the descriptor back. */ | ||
724 | + emc_read_rx_desc(qts, desc_addr, &result_desc); | ||
725 | + /* Descriptor should be owned by cpu now. */ | ||
726 | + g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) == 0); | ||
727 | + /* Test the status bits, ignoring the length field. */ | ||
728 | + expected_mask = 0xffff << 16; | ||
729 | + expected_value = RX_DESC_STATUS_RXGD; | ||
730 | + if (with_irq) { | ||
731 | + expected_value |= RX_DESC_STATUS_RXINTR; | ||
732 | + } | ||
733 | + g_assert_cmphex((result_desc.status_and_length & expected_mask), ==, | ||
734 | + expected_value); | ||
735 | + g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), ==, | ||
736 | + RX_DATA_LEN + CRC_LENGTH); | ||
737 | + | ||
738 | + { | ||
739 | + char buffer[RX_DATA_LEN]; | ||
740 | + qtest_memread(qts, data_addr, buffer, sizeof(buffer)); | ||
741 | + g_assert_cmpstr(buffer, == , "TEST"); | ||
742 | + } | ||
743 | +} | ||
744 | + | ||
745 | +static void emc_test_ptle(QTestState *qts, const EMCModule *mod, int fd) | ||
746 | +{ | ||
747 | + NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS]; | ||
748 | + uint32_t desc_addr = DESC_ADDR; | ||
749 | + uint32_t data_addr = DATA_ADDR; | ||
750 | + int ret; | ||
751 | + NPCM7xxEMCRxDesc result_desc; | ||
752 | + uint32_t expected_mask, expected_value; | ||
753 | + | ||
754 | + /* Prepare test data buffer. */ | ||
755 | +#define PTLE_DATA_LEN 1600 | ||
756 | + char test_data[PTLE_DATA_LEN]; | ||
757 | + int len = htonl(sizeof(test_data)); | ||
758 | + const struct iovec iov[] = { | ||
759 | + { | ||
760 | + .iov_base = &len, | ||
761 | + .iov_len = sizeof(len), | ||
762 | + },{ | ||
763 | + .iov_base = (char *) test_data, | ||
764 | + .iov_len = sizeof(test_data), | ||
765 | + }, | ||
766 | + }; | ||
767 | + memset(test_data, 42, sizeof(test_data)); | ||
768 | + | ||
769 | + /* | ||
770 | + * Reset the device BEFORE sending a test packet, otherwise the packet | ||
771 | + * may get swallowed by an active device of an earlier test. | ||
772 | + */ | ||
773 | + init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr); | ||
774 | + enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr, | ||
775 | + REG_MIEN_ENRXINTR, REG_MCMDR_ALP); | ||
776 | + | ||
777 | + /* Send test packet to device's socket. */ | ||
778 | + ret = iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test_data)); | ||
779 | + g_assert_cmpint(ret, == , sizeof(test_data) + sizeof(len)); | ||
780 | + | ||
781 | + /* Wait for RX interrupt. */ | ||
782 | + g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false)); | ||
783 | + | ||
784 | + /* Read the descriptor back. */ | ||
785 | + emc_read_rx_desc(qts, desc_addr, &result_desc); | ||
786 | + /* Descriptor should be owned by cpu now. */ | ||
787 | + g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) == 0); | ||
788 | + /* Test the status bits, ignoring the length field. */ | ||
789 | + expected_mask = 0xffff << 16; | ||
790 | + expected_value = (RX_DESC_STATUS_RXGD | | ||
791 | + RX_DESC_STATUS_PTLE | | ||
792 | + RX_DESC_STATUS_RXINTR); | ||
793 | + g_assert_cmphex((result_desc.status_and_length & expected_mask), ==, | ||
794 | + expected_value); | ||
795 | + g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), ==, | ||
796 | + PTLE_DATA_LEN + CRC_LENGTH); | ||
797 | + | ||
798 | + { | ||
799 | + char buffer[PTLE_DATA_LEN]; | ||
800 | + qtest_memread(qts, data_addr, buffer, sizeof(buffer)); | ||
801 | + g_assert(memcmp(buffer, test_data, PTLE_DATA_LEN) == 0); | ||
802 | + } | ||
803 | +} | ||
804 | + | ||
805 | +static void test_tx(gconstpointer test_data) | ||
806 | +{ | ||
807 | + const TestData *td = test_data; | ||
808 | + GString *cmd_line = g_string_new("-machine quanta-gsj"); | ||
809 | + int *test_sockets = packet_test_init(emc_module_index(td->module), | ||
810 | + cmd_line); | ||
811 | + QTestState *qts = qtest_init(cmd_line->str); | ||
812 | + | ||
813 | + /* | ||
814 | + * TODO: For pedantic correctness test_sockets[0] should be closed after | ||
815 | + * the fork and before the exec, but that will require some harness | ||
816 | + * improvements. | ||
817 | + */ | ||
818 | + close(test_sockets[1]); | ||
819 | + /* Defensive programming */ | ||
820 | + test_sockets[1] = -1; | ||
821 | + | ||
822 | + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); | ||
823 | + | ||
824 | + emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/false); | ||
825 | + emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/true); | ||
826 | + | ||
827 | + qtest_quit(qts); | ||
828 | +} | ||
829 | + | ||
830 | +static void test_rx(gconstpointer test_data) | ||
831 | +{ | ||
832 | + const TestData *td = test_data; | ||
833 | + GString *cmd_line = g_string_new("-machine quanta-gsj"); | ||
834 | + int *test_sockets = packet_test_init(emc_module_index(td->module), | ||
835 | + cmd_line); | ||
836 | + QTestState *qts = qtest_init(cmd_line->str); | ||
837 | + | ||
838 | + /* | ||
839 | + * TODO: For pedantic correctness test_sockets[0] should be closed after | ||
840 | + * the fork and before the exec, but that will require some harness | ||
841 | + * improvements. | ||
842 | + */ | ||
843 | + close(test_sockets[1]); | ||
844 | + /* Defensive programming */ | ||
845 | + test_sockets[1] = -1; | ||
846 | + | ||
847 | + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); | ||
848 | + | ||
849 | + emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/false); | ||
850 | + emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/true); | ||
851 | + emc_test_ptle(qts, td->module, test_sockets[0]); | ||
852 | + | ||
853 | + qtest_quit(qts); | ||
854 | +} | ||
855 | + | ||
856 | +static void emc_add_test(const char *name, const TestData* td, | ||
857 | + GTestDataFunc fn) | ||
858 | +{ | ||
859 | + g_autofree char *full_name = g_strdup_printf( | ||
860 | + "npcm7xx_emc/emc[%d]/%s", emc_module_index(td->module), name); | ||
861 | + qtest_add_data_func(full_name, td, fn); | ||
862 | +} | ||
863 | +#define add_test(name, td) emc_add_test(#name, td, test_##name) | ||
864 | + | ||
865 | +int main(int argc, char **argv) | ||
866 | +{ | ||
867 | + TestData test_data_list[ARRAY_SIZE(emc_module_list)]; | ||
868 | + | ||
869 | + g_test_init(&argc, &argv, NULL); | ||
870 | + | ||
871 | + for (int i = 0; i < ARRAY_SIZE(emc_module_list); ++i) { | ||
872 | + TestData *td = &test_data_list[i]; | ||
873 | + | ||
874 | + td->module = &emc_module_list[i]; | ||
875 | + | ||
876 | + add_test(init, td); | ||
877 | + add_test(tx, td); | ||
878 | + add_test(rx, td); | ||
879 | + } | ||
880 | + | ||
881 | + return g_test_run(); | ||
882 | +} | ||
883 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | ||
884 | index XXXXXXX..XXXXXXX 100644 | ||
885 | --- a/tests/qtest/meson.build | ||
886 | +++ b/tests/qtest/meson.build | ||
887 | @@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \ | ||
888 | 'npcm7xx_rng-test', | ||
889 | 'npcm7xx_smbus-test', | ||
890 | 'npcm7xx_timer-test', | ||
891 | - 'npcm7xx_watchdog_timer-test'] | ||
892 | + 'npcm7xx_watchdog_timer-test'] + \ | ||
893 | + (slirp.found() ? ['npcm7xx_emc-test'] : []) | ||
894 | qtests_arm = \ | ||
895 | (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \ | ||
896 | (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ | ||
571 | -- | 897 | -- |
572 | 2.20.1 | 898 | 2.20.1 |
573 | 899 | ||
574 | 900 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | The UART1 is part of the AUX peripheral, | 3 | We hint the 'has_rpu' property is no longer required since commit |
4 | the PCM_CLOCK (yet unimplemented) is part of the CPRMAN. | 4 | 6908ec448b4 ("xlnx-zynqmp: Properly support the smp command line |
5 | option") which was released in QEMU v2.11.0. | ||
6 | |||
7 | Beside, this device is marked 'user_creatable = false', so the | ||
8 | only thing that could be setting the property is the board code | ||
9 | that creates the device. | ||
10 | |||
11 | Since the property is not user-facing, we can remove it without | ||
12 | going through the deprecation process. | ||
5 | 13 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 15 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 16 | Message-id: 20210219144350.1979905-1-f4bug@amsat.org |
9 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
10 | Message-id: 20190926173428.10713-5-f4bug@amsat.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 18 | --- |
13 | include/hw/arm/raspi_platform.h | 16 +++++++--------- | 19 | include/hw/arm/xlnx-zynqmp.h | 2 -- |
14 | hw/arm/bcm2835_peripherals.c | 7 ++++--- | 20 | hw/arm/xlnx-zynqmp.c | 6 ------ |
15 | hw/arm/bcm2836.c | 2 +- | 21 | 2 files changed, 8 deletions(-) |
16 | 3 files changed, 12 insertions(+), 13 deletions(-) | ||
17 | 22 | ||
18 | diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h | 23 | diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h |
19 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/include/hw/arm/raspi_platform.h | 25 | --- a/include/hw/arm/xlnx-zynqmp.h |
21 | +++ b/include/hw/arm/raspi_platform.h | 26 | +++ b/include/hw/arm/xlnx-zynqmp.h |
22 | @@ -XXX,XX +XXX,XX @@ | 27 | @@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState { |
23 | #ifndef HW_ARM_RASPI_PLATFORM_H | 28 | bool secure; |
24 | #define HW_ARM_RASPI_PLATFORM_H | 29 | /* Has the ARM Virtualization extensions? */ |
25 | 30 | bool virt; | |
26 | -#define MCORE_OFFSET 0x0000 /* Fake frame buffer device | 31 | - /* Has the RPU subsystem? */ |
27 | - * (the multicore sync block) */ | 32 | - bool has_rpu; |
28 | +#define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */ | 33 | |
29 | #define IC0_OFFSET 0x2000 | 34 | /* CAN bus. */ |
30 | #define ST_OFFSET 0x3000 /* System Timer */ | 35 | CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN]; |
31 | #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */ | 36 | diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c |
32 | @@ -XXX,XX +XXX,XX @@ | ||
33 | #define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */ | ||
34 | #define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores | ||
35 | * Doorbells & Mailboxes */ | ||
36 | -#define PM_OFFSET 0x100000 /* Power Management, Reset controller | ||
37 | - * and Watchdog registers */ | ||
38 | -#define PCM_CLOCK_OFFSET 0x101098 | ||
39 | +#define CPRMAN_OFFSET 0x100000 /* Power Management, Watchdog */ | ||
40 | +#define CM_OFFSET 0x101000 /* Clock Management */ | ||
41 | #define RNG_OFFSET 0x104000 | ||
42 | #define GPIO_OFFSET 0x200000 | ||
43 | #define UART0_OFFSET 0x201000 | ||
44 | @@ -XXX,XX +XXX,XX @@ | ||
45 | #define I2S_OFFSET 0x203000 | ||
46 | #define SPI0_OFFSET 0x204000 | ||
47 | #define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */ | ||
48 | -#define UART1_OFFSET 0x215000 | ||
49 | -#define EMMC_OFFSET 0x300000 | ||
50 | +#define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */ | ||
51 | +#define EMMC1_OFFSET 0x300000 | ||
52 | #define SMI_OFFSET 0x600000 | ||
53 | #define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */ | ||
54 | -#define USB_OFFSET 0x980000 /* DTC_OTG USB controller */ | ||
55 | +#define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */ | ||
56 | #define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */ | ||
57 | |||
58 | /* GPU interrupts */ | ||
59 | @@ -XXX,XX +XXX,XX @@ | ||
60 | #define INTERRUPT_SPI 54 | ||
61 | #define INTERRUPT_I2SPCM 55 | ||
62 | #define INTERRUPT_SDIO 56 | ||
63 | -#define INTERRUPT_UART 57 | ||
64 | +#define INTERRUPT_UART0 57 | ||
65 | #define INTERRUPT_SLIMBUS 58 | ||
66 | #define INTERRUPT_VEC 59 | ||
67 | #define INTERRUPT_CPG 60 | ||
68 | diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c | ||
69 | index XXXXXXX..XXXXXXX 100644 | 37 | index XXXXXXX..XXXXXXX 100644 |
70 | --- a/hw/arm/bcm2835_peripherals.c | 38 | --- a/hw/arm/xlnx-zynqmp.c |
71 | +++ b/hw/arm/bcm2835_peripherals.c | 39 | +++ b/hw/arm/xlnx-zynqmp.c |
72 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) | 40 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) |
73 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart0), 0)); | 41 | } |
74 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart0), 0, | ||
75 | qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, | ||
76 | - INTERRUPT_UART)); | ||
77 | + INTERRUPT_UART0)); | ||
78 | + | ||
79 | /* AUX / UART1 */ | ||
80 | qdev_prop_set_chr(DEVICE(&s->aux), "chardev", serial_hd(1)); | ||
81 | |||
82 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) | ||
83 | return; | ||
84 | } | 42 | } |
85 | 43 | ||
86 | - memory_region_add_subregion(&s->peri_mr, UART1_OFFSET, | 44 | - if (s->has_rpu) { |
87 | + memory_region_add_subregion(&s->peri_mr, AUX_OFFSET, | 45 | - info_report("The 'has_rpu' property is no longer required, to use the " |
88 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->aux), 0)); | 46 | - "RPUs just use -smp 6."); |
89 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->aux), 0, | 47 | - } |
90 | qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, | 48 | - |
91 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) | 49 | xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err); |
92 | return; | 50 | if (err) { |
93 | } | 51 | error_propagate(errp, err); |
94 | 52 | @@ -XXX,XX +XXX,XX @@ static Property xlnx_zynqmp_props[] = { | |
95 | - memory_region_add_subregion(&s->peri_mr, EMMC_OFFSET, | 53 | DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), |
96 | + memory_region_add_subregion(&s->peri_mr, EMMC1_OFFSET, | 54 | DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), |
97 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhci), 0)); | 55 | DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), |
98 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, | 56 | - DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), |
99 | qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, | 57 | DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, |
100 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c | 58 | MemoryRegion *), |
101 | index XXXXXXX..XXXXXXX 100644 | 59 | DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS, |
102 | --- a/hw/arm/bcm2836.c | ||
103 | +++ b/hw/arm/bcm2836.c | ||
104 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
105 | |||
106 | /* set periphbase/CBAR value for CPU-local registers */ | ||
107 | object_property_set_int(OBJECT(&s->cpus[n]), | ||
108 | - BCM2836_PERI_BASE + MCORE_OFFSET, | ||
109 | + BCM2836_PERI_BASE + MSYNC_OFFSET, | ||
110 | "reset-cbar", &err); | ||
111 | if (err) { | ||
112 | error_propagate(errp, err); | ||
113 | -- | 60 | -- |
114 | 2.20.1 | 61 | 2.20.1 |
115 | 62 | ||
116 | 63 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Use class handlers and class constants to differentiate the | 3 | Always perform one call instead of two for 16-byte operands. |
4 | characteristics of the memory controller and remove the 'silicon_rev' | 4 | Use byte loads/stores directly into the vector register file |
5 | property. | 5 | instead of extractions and deposits to a 64-bit local variable. |
6 | 6 | ||
7 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 7 | In order to easily receive pointers into the vector register file, |
8 | Reviewed-by: Joel Stanley <joel@jms.id.au> | 8 | convert the helper to the gvec out-of-line signature. Move the |
9 | Message-id: 20190925143248.10000-9-clg@kaod.org | 9 | helper into vec_helper.c, where it can make use of H1 and clear_tail. |
10 | |||
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
13 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
14 | Message-id: 20210224230532.276878-1-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 16 | --- |
12 | include/hw/misc/aspeed_sdmc.h | 19 +++- | 17 | target/arm/helper-a64.h | 2 +- |
13 | hw/arm/aspeed_soc.c | 5 +- | 18 | target/arm/helper-a64.c | 32 --------------------- |
14 | hw/misc/aspeed_sdmc.c | 168 +++++++++++++++++++++------------- | 19 | target/arm/translate-a64.c | 58 +++++--------------------------------- |
15 | 3 files changed, 122 insertions(+), 70 deletions(-) | 20 | target/arm/vec_helper.c | 48 +++++++++++++++++++++++++++++++ |
16 | 21 | 4 files changed, 56 insertions(+), 84 deletions(-) | |
17 | diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h | 22 | |
18 | index XXXXXXX..XXXXXXX 100644 | 23 | diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h |
19 | --- a/include/hw/misc/aspeed_sdmc.h | 24 | index XXXXXXX..XXXXXXX 100644 |
20 | +++ b/include/hw/misc/aspeed_sdmc.h | 25 | --- a/target/arm/helper-a64.h |
21 | @@ -XXX,XX +XXX,XX @@ | 26 | +++ b/target/arm/helper-a64.h |
22 | 27 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr) | |
23 | #define TYPE_ASPEED_SDMC "aspeed.sdmc" | 28 | DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr) |
24 | #define ASPEED_SDMC(obj) OBJECT_CHECK(AspeedSDMCState, (obj), TYPE_ASPEED_SDMC) | 29 | DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr) |
25 | +#define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400" | 30 | DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, ptr) |
26 | +#define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500" | 31 | -DEF_HELPER_FLAGS_5(simd_tbl, TCG_CALL_NO_RWG_SE, i64, env, i64, i64, i32, i32) |
27 | 32 | +DEF_HELPER_FLAGS_4(simd_tblx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | |
28 | #define ASPEED_SDMC_NR_REGS (0x174 >> 2) | 33 | DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, ptr) |
29 | 34 | DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr) | |
30 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSDMCState { | 35 | DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr) |
31 | MemoryRegion iomem; | 36 | diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c |
32 | 37 | index XXXXXXX..XXXXXXX 100644 | |
33 | uint32_t regs[ASPEED_SDMC_NR_REGS]; | 38 | --- a/target/arm/helper-a64.c |
34 | - uint32_t silicon_rev; | 39 | +++ b/target/arm/helper-a64.c |
35 | - uint32_t ram_bits; | 40 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp) |
36 | uint64_t ram_size; | 41 | return float64_mul(a, b, fpst); |
37 | uint64_t max_ram_size; | 42 | } |
38 | - uint32_t fixed_conf; | 43 | |
39 | - | 44 | -uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t indices, |
40 | } AspeedSDMCState; | 45 | - uint32_t rn, uint32_t numregs) |
41 | 46 | -{ | |
42 | +#define ASPEED_SDMC_CLASS(klass) \ | 47 | - /* Helper function for SIMD TBL and TBX. We have to do the table |
43 | + OBJECT_CLASS_CHECK(AspeedSDMCClass, (klass), TYPE_ASPEED_SDMC) | 48 | - * lookup part for the 64 bits worth of indices we're passed in. |
44 | +#define ASPEED_SDMC_GET_CLASS(obj) \ | 49 | - * result is the initial results vector (either zeroes for TBL |
45 | + OBJECT_GET_CLASS(AspeedSDMCClass, (obj), TYPE_ASPEED_SDMC) | 50 | - * or some guest values for TBX), rn the register number where |
46 | + | 51 | - * the table starts, and numregs the number of registers in the table. |
47 | +typedef struct AspeedSDMCClass { | 52 | - * We return the results of the lookups. |
48 | + SysBusDeviceClass parent_class; | 53 | - */ |
49 | + | 54 | - int shift; |
50 | + uint64_t max_ram_size; | 55 | - |
51 | + uint32_t (*compute_conf)(AspeedSDMCState *s, uint32_t data); | 56 | - for (shift = 0; shift < 64; shift += 8) { |
52 | + void (*write)(AspeedSDMCState *s, uint32_t reg, uint32_t data); | 57 | - int index = extract64(indices, shift, 8); |
53 | +} AspeedSDMCClass; | 58 | - if (index < 16 * numregs) { |
54 | + | 59 | - /* Convert index (a byte offset into the virtual table |
55 | #endif /* ASPEED_SDMC_H */ | 60 | - * which is a series of 128-bit vectors concatenated) |
56 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | 61 | - * into the correct register element plus a bit offset |
57 | index XXXXXXX..XXXXXXX 100644 | 62 | - * into that element, bearing in mind that the table |
58 | --- a/hw/arm/aspeed_soc.c | 63 | - * can wrap around from V31 to V0. |
59 | +++ b/hw/arm/aspeed_soc.c | 64 | - */ |
60 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | 65 | - int elt = (rn * 2 + (index >> 3)) % 64; |
61 | sizeof(s->spi[i]), typename); | 66 | - int bitidx = (index & 7) * 8; |
62 | } | 67 | - uint64_t *q = aa64_vfp_qreg(env, elt >> 1); |
63 | 68 | - uint64_t val = extract64(q[elt & 1], bitidx, 8); | |
64 | + snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); | 69 | - |
65 | sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc), | 70 | - result = deposit64(result, shift, 8, val); |
66 | - TYPE_ASPEED_SDMC); | 71 | - } |
67 | - qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev", | 72 | - } |
68 | - sc->info->silicon_rev); | 73 | - return result; |
69 | + typename); | 74 | -} |
70 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), | 75 | - |
71 | "ram-size", &error_abort); | 76 | /* 64bit/double versions of the neon float compare functions */ |
72 | object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), | 77 | uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp) |
73 | diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c | ||
74 | index XXXXXXX..XXXXXXX 100644 | ||
75 | --- a/hw/misc/aspeed_sdmc.c | ||
76 | +++ b/hw/misc/aspeed_sdmc.c | ||
77 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data, | ||
78 | unsigned int size) | ||
79 | { | 78 | { |
80 | AspeedSDMCState *s = ASPEED_SDMC(opaque); | 79 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
81 | + AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); | 80 | index XXXXXXX..XXXXXXX 100644 |
82 | 81 | --- a/target/arm/translate-a64.c | |
83 | addr >>= 2; | 82 | +++ b/target/arm/translate-a64.c |
84 | 83 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn) | |
85 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data, | 84 | int rm = extract32(insn, 16, 5); |
85 | int rn = extract32(insn, 5, 5); | ||
86 | int rd = extract32(insn, 0, 5); | ||
87 | - int is_tblx = extract32(insn, 12, 1); | ||
88 | - int len = extract32(insn, 13, 2); | ||
89 | - TCGv_i64 tcg_resl, tcg_resh, tcg_idx; | ||
90 | - TCGv_i32 tcg_regno, tcg_numregs; | ||
91 | + int is_tbx = extract32(insn, 12, 1); | ||
92 | + int len = (extract32(insn, 13, 2) + 1) * 16; | ||
93 | |||
94 | if (op2 != 0) { | ||
95 | unallocated_encoding(s); | ||
96 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn) | ||
86 | return; | 97 | return; |
87 | } | 98 | } |
88 | 99 | ||
89 | - if (addr == R_CONF) { | 100 | - /* This does a table lookup: for every byte element in the input |
90 | - /* Make sure readonly bits are kept */ | 101 | - * we index into a table formed from up to four vector registers, |
91 | - switch (s->silicon_rev) { | 102 | - * and then the output is the result of the lookups. Our helper |
92 | - case AST2400_A0_SILICON_REV: | 103 | - * function does the lookup operation for a single 64 bit part of |
93 | - case AST2400_A1_SILICON_REV: | 104 | - * the input. |
94 | - data &= ~ASPEED_SDMC_READONLY_MASK; | 105 | - */ |
95 | - data |= s->fixed_conf; | 106 | - tcg_resl = tcg_temp_new_i64(); |
96 | - break; | 107 | - tcg_resh = NULL; |
97 | - case AST2500_A0_SILICON_REV: | 108 | - |
98 | - case AST2500_A1_SILICON_REV: | 109 | - if (is_tblx) { |
99 | - data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; | 110 | - read_vec_element(s, tcg_resl, rd, 0, MO_64); |
100 | - data |= s->fixed_conf; | 111 | - } else { |
101 | - break; | 112 | - tcg_gen_movi_i64(tcg_resl, 0); |
102 | - default: | 113 | - } |
103 | - g_assert_not_reached(); | 114 | - |
115 | - if (is_q) { | ||
116 | - tcg_resh = tcg_temp_new_i64(); | ||
117 | - if (is_tblx) { | ||
118 | - read_vec_element(s, tcg_resh, rd, 1, MO_64); | ||
119 | - } else { | ||
120 | - tcg_gen_movi_i64(tcg_resh, 0); | ||
104 | - } | 121 | - } |
105 | - } | 122 | - } |
106 | - if (s->silicon_rev == AST2500_A0_SILICON_REV || | 123 | - |
107 | - s->silicon_rev == AST2500_A1_SILICON_REV) { | 124 | - tcg_idx = tcg_temp_new_i64(); |
108 | - switch (addr) { | 125 | - tcg_regno = tcg_const_i32(rn); |
109 | - case R_STATUS1: | 126 | - tcg_numregs = tcg_const_i32(len + 1); |
110 | - /* Will never return 'busy' */ | 127 | - read_vec_element(s, tcg_idx, rm, 0, MO_64); |
111 | - data &= ~PHY_BUSY_STATE; | 128 | - gen_helper_simd_tbl(tcg_resl, cpu_env, tcg_resl, tcg_idx, |
112 | - break; | 129 | - tcg_regno, tcg_numregs); |
113 | - case R_ECC_TEST_CTRL: | 130 | - if (is_q) { |
114 | - /* Always done, always happy */ | 131 | - read_vec_element(s, tcg_idx, rm, 1, MO_64); |
115 | - data |= ECC_TEST_FINISHED; | 132 | - gen_helper_simd_tbl(tcg_resh, cpu_env, tcg_resh, tcg_idx, |
116 | - data &= ~ECC_TEST_FAIL; | 133 | - tcg_regno, tcg_numregs); |
117 | - break; | 134 | - } |
118 | - default: | 135 | - tcg_temp_free_i64(tcg_idx); |
119 | - break; | 136 | - tcg_temp_free_i32(tcg_regno); |
120 | - } | 137 | - tcg_temp_free_i32(tcg_numregs); |
121 | - } | 138 | - |
122 | - | 139 | - write_vec_element(s, tcg_resl, rd, 0, MO_64); |
123 | - s->regs[addr] = data; | 140 | - tcg_temp_free_i64(tcg_resl); |
124 | + asc->write(s, addr, data); | 141 | - |
142 | - if (is_q) { | ||
143 | - write_vec_element(s, tcg_resh, rd, 1, MO_64); | ||
144 | - tcg_temp_free_i64(tcg_resh); | ||
145 | - } | ||
146 | - clear_vec_high(s, is_q, rd); | ||
147 | + tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, rd), | ||
148 | + vec_full_reg_offset(s, rm), cpu_env, | ||
149 | + is_q ? 16 : 8, vec_full_reg_size(s), | ||
150 | + (len << 6) | (is_tbx << 5) | rn, | ||
151 | + gen_helper_simd_tblx); | ||
125 | } | 152 | } |
126 | 153 | ||
127 | static const MemoryRegionOps aspeed_sdmc_ops = { | 154 | /* ZIP/UZP/TRN |
128 | @@ -XXX,XX +XXX,XX @@ static int ast2500_rambits(AspeedSDMCState *s) | 155 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c |
129 | static void aspeed_sdmc_reset(DeviceState *dev) | 156 | index XXXXXXX..XXXXXXX 100644 |
130 | { | 157 | --- a/target/arm/vec_helper.c |
131 | AspeedSDMCState *s = ASPEED_SDMC(dev); | 158 | +++ b/target/arm/vec_helper.c |
132 | + AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); | 159 | @@ -XXX,XX +XXX,XX @@ DO_VRINT_RMODE(gvec_vrint_rm_h, helper_rinth, uint16_t) |
133 | 160 | DO_VRINT_RMODE(gvec_vrint_rm_s, helper_rints, uint32_t) | |
134 | memset(s->regs, 0, sizeof(s->regs)); | 161 | |
135 | 162 | #undef DO_VRINT_RMODE | |
136 | /* Set ram size bit and defaults values */ | 163 | + |
137 | - s->regs[R_CONF] = s->fixed_conf; | 164 | +#ifdef TARGET_AARCH64 |
138 | + s->regs[R_CONF] = asc->compute_conf(s, 0); | 165 | +void HELPER(simd_tblx)(void *vd, void *vm, void *venv, uint32_t desc) |
139 | } | ||
140 | |||
141 | static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) | ||
142 | { | ||
143 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
144 | AspeedSDMCState *s = ASPEED_SDMC(dev); | ||
145 | + AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); | ||
146 | |||
147 | - if (!is_supported_silicon_rev(s->silicon_rev)) { | ||
148 | - error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, | ||
149 | - s->silicon_rev); | ||
150 | - return; | ||
151 | - } | ||
152 | - | ||
153 | - switch (s->silicon_rev) { | ||
154 | - case AST2400_A0_SILICON_REV: | ||
155 | - case AST2400_A1_SILICON_REV: | ||
156 | - s->ram_bits = ast2400_rambits(s); | ||
157 | - s->max_ram_size = 512 << 20; | ||
158 | - s->fixed_conf = ASPEED_SDMC_VGA_COMPAT | | ||
159 | - ASPEED_SDMC_DRAM_SIZE(s->ram_bits); | ||
160 | - break; | ||
161 | - case AST2500_A0_SILICON_REV: | ||
162 | - case AST2500_A1_SILICON_REV: | ||
163 | - s->ram_bits = ast2500_rambits(s); | ||
164 | - s->max_ram_size = 1024 << 20; | ||
165 | - s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) | | ||
166 | - ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | | ||
167 | - ASPEED_SDMC_CACHE_INITIAL_DONE | | ||
168 | - ASPEED_SDMC_DRAM_SIZE(s->ram_bits); | ||
169 | - break; | ||
170 | - default: | ||
171 | - g_assert_not_reached(); | ||
172 | - } | ||
173 | + s->max_ram_size = asc->max_ram_size; | ||
174 | |||
175 | memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s, | ||
176 | TYPE_ASPEED_SDMC, 0x1000); | ||
177 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_sdmc = { | ||
178 | }; | ||
179 | |||
180 | static Property aspeed_sdmc_properties[] = { | ||
181 | - DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0), | ||
182 | DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0), | ||
183 | DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0), | ||
184 | DEFINE_PROP_END_OF_LIST(), | ||
185 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_sdmc_info = { | ||
186 | .parent = TYPE_SYS_BUS_DEVICE, | ||
187 | .instance_size = sizeof(AspeedSDMCState), | ||
188 | .class_init = aspeed_sdmc_class_init, | ||
189 | + .class_size = sizeof(AspeedSDMCClass), | ||
190 | + .abstract = true, | ||
191 | +}; | ||
192 | + | ||
193 | +static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) | ||
194 | +{ | 166 | +{ |
195 | + uint32_t fixed_conf = ASPEED_SDMC_VGA_COMPAT | | 167 | + const uint8_t *indices = vm; |
196 | + ASPEED_SDMC_DRAM_SIZE(ast2400_rambits(s)); | 168 | + CPUARMState *env = venv; |
197 | + | 169 | + size_t oprsz = simd_oprsz(desc); |
198 | + /* Make sure readonly bits are kept */ | 170 | + uint32_t rn = extract32(desc, SIMD_DATA_SHIFT, 5); |
199 | + data &= ~ASPEED_SDMC_READONLY_MASK; | 171 | + bool is_tbx = extract32(desc, SIMD_DATA_SHIFT + 5, 1); |
200 | + | 172 | + uint32_t table_len = desc >> (SIMD_DATA_SHIFT + 6); |
201 | + return data | fixed_conf; | 173 | + union { |
174 | + uint8_t b[16]; | ||
175 | + uint64_t d[2]; | ||
176 | + } result; | ||
177 | + | ||
178 | + /* | ||
179 | + * We must construct the final result in a temp, lest the output | ||
180 | + * overlaps the input table. For TBL, begin with zero; for TBX, | ||
181 | + * begin with the original register contents. Note that we always | ||
182 | + * copy 16 bytes here to avoid an extra branch; clearing the high | ||
183 | + * bits of the register for oprsz == 8 is handled below. | ||
184 | + */ | ||
185 | + if (is_tbx) { | ||
186 | + memcpy(&result, vd, 16); | ||
187 | + } else { | ||
188 | + memset(&result, 0, 16); | ||
189 | + } | ||
190 | + | ||
191 | + for (size_t i = 0; i < oprsz; ++i) { | ||
192 | + uint32_t index = indices[H1(i)]; | ||
193 | + | ||
194 | + if (index < table_len) { | ||
195 | + /* | ||
196 | + * Convert index (a byte offset into the virtual table | ||
197 | + * which is a series of 128-bit vectors concatenated) | ||
198 | + * into the correct register element, bearing in mind | ||
199 | + * that the table can wrap around from V31 to V0. | ||
200 | + */ | ||
201 | + const uint8_t *table = (const uint8_t *) | ||
202 | + aa64_vfp_qreg(env, (rn + (index >> 4)) % 32); | ||
203 | + result.b[H1(i)] = table[H1(index % 16)]; | ||
204 | + } | ||
205 | + } | ||
206 | + | ||
207 | + memcpy(vd, &result, 16); | ||
208 | + clear_tail(vd, oprsz, simd_maxsz(desc)); | ||
202 | +} | 209 | +} |
203 | + | 210 | +#endif |
204 | +static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg, | ||
205 | + uint32_t data) | ||
206 | +{ | ||
207 | + switch (reg) { | ||
208 | + case R_CONF: | ||
209 | + data = aspeed_2400_sdmc_compute_conf(s, data); | ||
210 | + break; | ||
211 | + default: | ||
212 | + break; | ||
213 | + } | ||
214 | + | ||
215 | + s->regs[reg] = data; | ||
216 | +} | ||
217 | + | ||
218 | +static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data) | ||
219 | +{ | ||
220 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
221 | + AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); | ||
222 | + | ||
223 | + dc->desc = "ASPEED 2400 SDRAM Memory Controller"; | ||
224 | + asc->max_ram_size = 512 << 20; | ||
225 | + asc->compute_conf = aspeed_2400_sdmc_compute_conf; | ||
226 | + asc->write = aspeed_2400_sdmc_write; | ||
227 | +} | ||
228 | + | ||
229 | +static const TypeInfo aspeed_2400_sdmc_info = { | ||
230 | + .name = TYPE_ASPEED_2400_SDMC, | ||
231 | + .parent = TYPE_ASPEED_SDMC, | ||
232 | + .class_init = aspeed_2400_sdmc_class_init, | ||
233 | +}; | ||
234 | + | ||
235 | +static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) | ||
236 | +{ | ||
237 | + uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(1) | | ||
238 | + ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | | ||
239 | + ASPEED_SDMC_CACHE_INITIAL_DONE | | ||
240 | + ASPEED_SDMC_DRAM_SIZE(ast2500_rambits(s)); | ||
241 | + | ||
242 | + /* Make sure readonly bits are kept */ | ||
243 | + data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; | ||
244 | + | ||
245 | + return data | fixed_conf; | ||
246 | +} | ||
247 | + | ||
248 | +static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg, | ||
249 | + uint32_t data) | ||
250 | +{ | ||
251 | + switch (reg) { | ||
252 | + case R_CONF: | ||
253 | + data = aspeed_2500_sdmc_compute_conf(s, data); | ||
254 | + break; | ||
255 | + case R_STATUS1: | ||
256 | + /* Will never return 'busy' */ | ||
257 | + data &= ~PHY_BUSY_STATE; | ||
258 | + break; | ||
259 | + case R_ECC_TEST_CTRL: | ||
260 | + /* Always done, always happy */ | ||
261 | + data |= ECC_TEST_FINISHED; | ||
262 | + data &= ~ECC_TEST_FAIL; | ||
263 | + break; | ||
264 | + default: | ||
265 | + break; | ||
266 | + } | ||
267 | + | ||
268 | + s->regs[reg] = data; | ||
269 | +} | ||
270 | + | ||
271 | +static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data) | ||
272 | +{ | ||
273 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
274 | + AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); | ||
275 | + | ||
276 | + dc->desc = "ASPEED 2500 SDRAM Memory Controller"; | ||
277 | + asc->max_ram_size = 1024 << 20; | ||
278 | + asc->compute_conf = aspeed_2500_sdmc_compute_conf; | ||
279 | + asc->write = aspeed_2500_sdmc_write; | ||
280 | +} | ||
281 | + | ||
282 | +static const TypeInfo aspeed_2500_sdmc_info = { | ||
283 | + .name = TYPE_ASPEED_2500_SDMC, | ||
284 | + .parent = TYPE_ASPEED_SDMC, | ||
285 | + .class_init = aspeed_2500_sdmc_class_init, | ||
286 | }; | ||
287 | |||
288 | static void aspeed_sdmc_register_types(void) | ||
289 | { | ||
290 | type_register_static(&aspeed_sdmc_info); | ||
291 | + type_register_static(&aspeed_2400_sdmc_info); | ||
292 | + type_register_static(&aspeed_2500_sdmc_info); | ||
293 | } | ||
294 | |||
295 | type_init(aspeed_sdmc_register_types); | ||
296 | -- | 211 | -- |
297 | 2.20.1 | 212 | 2.20.1 |
298 | 213 | ||
299 | 214 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | Various address spaces from the BCM2835 are reported as | 3 | The STATUS register will be reset to IDLE in |
4 | 'anonymous' in memory tree: | 4 | cnpcm7xx_smbus_enter_reset(), no need to preset |
5 | 5 | it in instance_init(). | |
6 | (qemu) info mtree | ||
7 | |||
8 | address-space: anonymous | ||
9 | 0000000000000000-000000000000008f (prio 0, i/o): bcm2835-mbox | ||
10 | 0000000000000010-000000000000001f (prio 0, i/o): bcm2835-fb | ||
11 | 0000000000000080-000000000000008f (prio 0, i/o): bcm2835-property | ||
12 | |||
13 | address-space: anonymous | ||
14 | 0000000000000000-00000000ffffffff (prio 0, i/o): bcm2835-gpu | ||
15 | 0000000000000000-000000003fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
16 | 0000000040000000-000000007fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
17 | 000000007e000000-000000007effffff (prio 1, i/o): alias bcm2835-peripherals @bcm2835-peripherals 0000000000000000-0000000000ffffff | ||
18 | 0000000080000000-00000000bfffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
19 | 00000000c0000000-00000000ffffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
20 | |||
21 | [...] | ||
22 | |||
23 | Since the address_space_init() function takes a 'name' argument, | ||
24 | set it to correctly describe each address space: | ||
25 | |||
26 | (qemu) info mtree | ||
27 | |||
28 | address-space: bcm2835-mbox-memory | ||
29 | 0000000000000000-000000000000008f (prio 0, i/o): bcm2835-mbox | ||
30 | 0000000000000010-000000000000001f (prio 0, i/o): bcm2835-fb | ||
31 | 0000000000000080-000000000000008f (prio 0, i/o): bcm2835-property | ||
32 | |||
33 | address-space: bcm2835-fb-memory | ||
34 | 0000000000000000-00000000ffffffff (prio 0, i/o): bcm2835-gpu | ||
35 | 0000000000000000-000000003fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
36 | 0000000040000000-000000007fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
37 | 000000007e000000-000000007effffff (prio 1, i/o): alias bcm2835-peripherals @bcm2835-peripherals 0000000000000000-0000000000ffffff | ||
38 | 0000000080000000-00000000bfffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
39 | 00000000c0000000-00000000ffffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
40 | |||
41 | address-space: bcm2835-property-memory | ||
42 | 0000000000000000-00000000ffffffff (prio 0, i/o): bcm2835-gpu | ||
43 | 0000000000000000-000000003fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
44 | 0000000040000000-000000007fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
45 | 000000007e000000-000000007effffff (prio 1, i/o): alias bcm2835-peripherals @bcm2835-peripherals 0000000000000000-0000000000ffffff | ||
46 | 0000000080000000-00000000bfffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
47 | 00000000c0000000-00000000ffffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
48 | |||
49 | address-space: bcm2835-dma-memory | ||
50 | 0000000000000000-00000000ffffffff (prio 0, i/o): bcm2835-gpu | ||
51 | 0000000000000000-000000003fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
52 | 0000000040000000-000000007fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
53 | 000000007e000000-000000007effffff (prio 1, i/o): alias bcm2835-peripherals @bcm2835-peripherals 0000000000000000-0000000000ffffff | ||
54 | 0000000080000000-00000000bfffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
55 | 00000000c0000000-00000000ffffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff | ||
56 | 6 | ||
57 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
58 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 8 | Reviewed-by: Hao Wu <wuhaotsh@google.com> |
59 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 9 | Message-id: 20210228224813.312532-1-f4bug@amsat.org |
60 | Reviewed-by: Cleber Rosa <crosa@redhat.com> | ||
61 | Message-id: 20190926173428.10713-4-f4bug@amsat.org | ||
62 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
63 | --- | 11 | --- |
64 | hw/display/bcm2835_fb.c | 2 +- | 12 | hw/i2c/npcm7xx_smbus.c | 1 - |
65 | hw/dma/bcm2835_dma.c | 2 +- | 13 | 1 file changed, 1 deletion(-) |
66 | hw/misc/bcm2835_mbox.c | 2 +- | ||
67 | hw/misc/bcm2835_property.c | 2 +- | ||
68 | 4 files changed, 4 insertions(+), 4 deletions(-) | ||
69 | 14 | ||
70 | diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c | 15 | diff --git a/hw/i2c/npcm7xx_smbus.c b/hw/i2c/npcm7xx_smbus.c |
71 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
72 | --- a/hw/display/bcm2835_fb.c | 17 | --- a/hw/i2c/npcm7xx_smbus.c |
73 | +++ b/hw/display/bcm2835_fb.c | 18 | +++ b/hw/i2c/npcm7xx_smbus.c |
74 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_fb_realize(DeviceState *dev, Error **errp) | 19 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_smbus_init(Object *obj) |
75 | s->initial_config.base = s->vcram_base + BCM2835_FB_OFFSET; | 20 | sysbus_init_mmio(sbd, &s->iomem); |
76 | 21 | ||
77 | s->dma_mr = MEMORY_REGION(obj); | 22 | s->bus = i2c_init_bus(DEVICE(s), "i2c-bus"); |
78 | - address_space_init(&s->dma_as, s->dma_mr, NULL); | 23 | - s->status = NPCM7XX_SMBUS_STATUS_IDLE; |
79 | + address_space_init(&s->dma_as, s->dma_mr, TYPE_BCM2835_FB "-memory"); | ||
80 | |||
81 | bcm2835_fb_reset(dev); | ||
82 | |||
83 | diff --git a/hw/dma/bcm2835_dma.c b/hw/dma/bcm2835_dma.c | ||
84 | index XXXXXXX..XXXXXXX 100644 | ||
85 | --- a/hw/dma/bcm2835_dma.c | ||
86 | +++ b/hw/dma/bcm2835_dma.c | ||
87 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_dma_realize(DeviceState *dev, Error **errp) | ||
88 | } | ||
89 | |||
90 | s->dma_mr = MEMORY_REGION(obj); | ||
91 | - address_space_init(&s->dma_as, s->dma_mr, NULL); | ||
92 | + address_space_init(&s->dma_as, s->dma_mr, TYPE_BCM2835_DMA "-memory"); | ||
93 | |||
94 | bcm2835_dma_reset(dev); | ||
95 | } | 24 | } |
96 | diff --git a/hw/misc/bcm2835_mbox.c b/hw/misc/bcm2835_mbox.c | 25 | |
97 | index XXXXXXX..XXXXXXX 100644 | 26 | static const VMStateDescription vmstate_npcm7xx_smbus = { |
98 | --- a/hw/misc/bcm2835_mbox.c | ||
99 | +++ b/hw/misc/bcm2835_mbox.c | ||
100 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_mbox_realize(DeviceState *dev, Error **errp) | ||
101 | } | ||
102 | |||
103 | s->mbox_mr = MEMORY_REGION(obj); | ||
104 | - address_space_init(&s->mbox_as, s->mbox_mr, NULL); | ||
105 | + address_space_init(&s->mbox_as, s->mbox_mr, TYPE_BCM2835_MBOX "-memory"); | ||
106 | bcm2835_mbox_reset(dev); | ||
107 | } | ||
108 | |||
109 | diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c | ||
110 | index XXXXXXX..XXXXXXX 100644 | ||
111 | --- a/hw/misc/bcm2835_property.c | ||
112 | +++ b/hw/misc/bcm2835_property.c | ||
113 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_realize(DeviceState *dev, Error **errp) | ||
114 | } | ||
115 | |||
116 | s->dma_mr = MEMORY_REGION(obj); | ||
117 | - address_space_init(&s->dma_as, s->dma_mr, NULL); | ||
118 | + address_space_init(&s->dma_as, s->dma_mr, TYPE_BCM2835_PROPERTY "-memory"); | ||
119 | |||
120 | /* TODO: connect to MAC address of USB NIC device, once we emulate it */ | ||
121 | qemu_macaddr_default_if_unset(&s->macaddr); | ||
122 | -- | 27 | -- |
123 | 2.20.1 | 28 | 2.20.1 |
124 | 29 | ||
125 | 30 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: schspa <schspa@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | The AST2600 timer replaces control register 2 with a interrupt status | 3 | At the moment the following QEMU command line triggers an assertion |
4 | register. It is set by hardware when an IRQ occurs and cleared by | 4 | failure On xlnx-versal SOC: |
5 | software. | 5 | qemu-system-aarch64 \ |
6 | -machine xlnx-versal-virt -nographic -smp 2 -m 128 \ | ||
7 | -fsdev local,id=shareid,path=${HOME}/work,security_model=none \ | ||
8 | -device virtio-9p-device,fsdev=shareid,mount_tag=share \ | ||
9 | -fsdev local,id=shareid1,path=${HOME}/Music,security_model=none \ | ||
10 | -device virtio-9p-device,fsdev=shareid1,mount_tag=share1 | ||
6 | 11 | ||
7 | Modify the vmstate version to take into account the new fields. | 12 | qemu-system-aarch64: ../migration/savevm.c:860: |
13 | vmstate_register_with_alias_id: | ||
14 | Assertion `!se->compat || se->instance_id == 0' failed. | ||
8 | 15 | ||
9 | Based on previous work from Joel Stanley. | 16 | This problem was fixed on arm virt platform in commit f58b39d2d5b |
17 | ("virtio-mmio: format transport base address in BusClass.get_dev_path") | ||
10 | 18 | ||
11 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 19 | It works perfectly on arm virt platform. but there is still there on |
12 | Reviewed-by: Joel Stanley <joel@jms.id.au> | 20 | xlnx-versal SOC. |
13 | Message-id: 20190925143248.10000-8-clg@kaod.org | 21 | |
22 | The main difference between arm virt and xlnx-versal is they use | ||
23 | different way to create virtio-mmio qdev. on arm virt, it calls | ||
24 | sysbus_create_simple("virtio-mmio", base, pic[irq]); which will call | ||
25 | sysbus_mmio_map internally and assign base address to subsys device | ||
26 | mmio correctly. but xlnx-versal's implements won't do this. | ||
27 | |||
28 | However, xlnx-versal can't switch to sysbus_create_simple() to create | ||
29 | virtio-mmio device. It's because xlnx-versal's cpu use | ||
30 | VersalVirt.soc.fpd.apu.mr as it's memory. which is subregion of | ||
31 | system_memory. sysbus_create_simple will add virtio to system_memory, | ||
32 | which can't be accessed by cpu. | ||
33 | |||
34 | Besides, xlnx-versal can't add sysbus_mmio_map api call too, because | ||
35 | this will add memory region to system_memory, and it can't be added | ||
36 | to VersalVirt.soc.fpd.apu.mr again. | ||
37 | |||
38 | We can solve this by assign correct base address offset on dev_path. | ||
39 | |||
40 | This path was test on aarch64 virt & xlnx-versal platform. | ||
41 | |||
42 | Signed-off-by: schspa <schspa@gmail.com> | ||
43 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 44 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 45 | --- |
16 | include/hw/timer/aspeed_timer.h | 1 + | 46 | hw/virtio/virtio-mmio.c | 13 +++++++------ |
17 | hw/timer/aspeed_timer.c | 36 +++++++++++++++++++++++++-------- | 47 | 1 file changed, 7 insertions(+), 6 deletions(-) |
18 | 2 files changed, 29 insertions(+), 8 deletions(-) | ||
19 | 48 | ||
20 | diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h | 49 | diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c |
21 | index XXXXXXX..XXXXXXX 100644 | 50 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/include/hw/timer/aspeed_timer.h | 51 | --- a/hw/virtio/virtio-mmio.c |
23 | +++ b/include/hw/timer/aspeed_timer.h | 52 | +++ b/hw/virtio/virtio-mmio.c |
24 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedTimerCtrlState { | 53 | @@ -XXX,XX +XXX,XX @@ static char *virtio_mmio_bus_get_dev_path(DeviceState *dev) |
25 | uint32_t ctrl; | 54 | BusState *virtio_mmio_bus; |
26 | uint32_t ctrl2; | 55 | VirtIOMMIOProxy *virtio_mmio_proxy; |
27 | uint32_t ctrl3; | 56 | char *proxy_path; |
28 | + uint32_t irq_sts; | 57 | - SysBusDevice *proxy_sbd; |
29 | AspeedTimer timers[ASPEED_TIMER_NR_TIMERS]; | 58 | char *path; |
30 | 59 | + MemoryRegionSection section; | |
31 | AspeedSCUState *scu; | 60 | |
32 | diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c | 61 | virtio_mmio_bus = qdev_get_parent_bus(dev); |
33 | index XXXXXXX..XXXXXXX 100644 | 62 | virtio_mmio_proxy = VIRTIO_MMIO(virtio_mmio_bus->parent); |
34 | --- a/hw/timer/aspeed_timer.c | 63 | @@ -XXX,XX +XXX,XX @@ static char *virtio_mmio_bus_get_dev_path(DeviceState *dev) |
35 | +++ b/hw/timer/aspeed_timer.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static uint64_t calculate_next(struct AspeedTimer *t) | ||
37 | timer_del(&t->timer); | ||
38 | |||
39 | if (timer_overflow_interrupt(t)) { | ||
40 | + AspeedTimerCtrlState *s = timer_to_ctrl(t); | ||
41 | t->level = !t->level; | ||
42 | + s->irq_sts |= BIT(t->id); | ||
43 | qemu_set_irq(t->irq, t->level); | ||
44 | } | 64 | } |
45 | 65 | ||
46 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_expire(void *opaque) | 66 | /* Otherwise, we append the base address of the transport. */ |
67 | - proxy_sbd = SYS_BUS_DEVICE(virtio_mmio_proxy); | ||
68 | - assert(proxy_sbd->num_mmio == 1); | ||
69 | - assert(proxy_sbd->mmio[0].memory == &virtio_mmio_proxy->iomem); | ||
70 | + section = memory_region_find(&virtio_mmio_proxy->iomem, 0, 0x200); | ||
71 | + assert(section.mr); | ||
72 | |||
73 | if (proxy_path) { | ||
74 | path = g_strdup_printf("%s/virtio-mmio@" TARGET_FMT_plx, proxy_path, | ||
75 | - proxy_sbd->mmio[0].addr); | ||
76 | + section.offset_within_address_space); | ||
77 | } else { | ||
78 | path = g_strdup_printf("virtio-mmio@" TARGET_FMT_plx, | ||
79 | - proxy_sbd->mmio[0].addr); | ||
80 | + section.offset_within_address_space); | ||
47 | } | 81 | } |
48 | 82 | + memory_region_unref(section.mr); | |
49 | if (interrupt) { | ||
50 | + AspeedTimerCtrlState *s = timer_to_ctrl(t); | ||
51 | t->level = !t->level; | ||
52 | + s->irq_sts |= BIT(t->id); | ||
53 | qemu_set_irq(t->irq, t->level); | ||
54 | } | ||
55 | |||
56 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_timer_read(void *opaque, hwaddr offset, unsigned size) | ||
57 | case 0x30: /* Control Register */ | ||
58 | value = s->ctrl; | ||
59 | break; | ||
60 | - case 0x34: /* Control Register 2 */ | ||
61 | - value = s->ctrl2; | ||
62 | - break; | ||
63 | case 0x00 ... 0x2c: /* Timers 1 - 4 */ | ||
64 | value = aspeed_timer_get_value(&s->timers[(offset >> 4)], reg); | ||
65 | break; | ||
66 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_write(void *opaque, hwaddr offset, uint64_t value, | ||
67 | case 0x30: | ||
68 | aspeed_timer_set_ctrl(s, tv); | ||
69 | break; | ||
70 | - case 0x34: | ||
71 | - aspeed_timer_set_ctrl2(s, tv); | ||
72 | - break; | ||
73 | /* Timer Registers */ | ||
74 | case 0x00 ... 0x2c: | ||
75 | aspeed_timer_set_value(s, (offset >> TIMER_NR_REGS), reg, tv); | ||
76 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_2400_timer_read(AspeedTimerCtrlState *s, hwaddr offset) | ||
77 | uint64_t value; | ||
78 | |||
79 | switch (offset) { | ||
80 | + case 0x34: | ||
81 | + value = s->ctrl2; | ||
82 | + break; | ||
83 | case 0x38: | ||
84 | case 0x3C: | ||
85 | default: | ||
86 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_2400_timer_read(AspeedTimerCtrlState *s, hwaddr offset) | ||
87 | static void aspeed_2400_timer_write(AspeedTimerCtrlState *s, hwaddr offset, | ||
88 | uint64_t value) | ||
89 | { | ||
90 | + const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF); | ||
91 | + | 83 | + |
92 | switch (offset) { | 84 | g_free(proxy_path); |
93 | + case 0x34: | 85 | return path; |
94 | + aspeed_timer_set_ctrl2(s, tv); | ||
95 | + break; | ||
96 | case 0x38: | ||
97 | case 0x3C: | ||
98 | default: | ||
99 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_2500_timer_read(AspeedTimerCtrlState *s, hwaddr offset) | ||
100 | uint64_t value; | ||
101 | |||
102 | switch (offset) { | ||
103 | + case 0x34: | ||
104 | + value = s->ctrl2; | ||
105 | + break; | ||
106 | case 0x38: | ||
107 | value = s->ctrl3 & BIT(0); | ||
108 | break; | ||
109 | @@ -XXX,XX +XXX,XX @@ static void aspeed_2500_timer_write(AspeedTimerCtrlState *s, hwaddr offset, | ||
110 | uint8_t command; | ||
111 | |||
112 | switch (offset) { | ||
113 | + case 0x34: | ||
114 | + aspeed_timer_set_ctrl2(s, tv); | ||
115 | + break; | ||
116 | case 0x38: | ||
117 | command = (value >> 1) & 0xFF; | ||
118 | if (command == 0xAE) { | ||
119 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_2600_timer_read(AspeedTimerCtrlState *s, hwaddr offset) | ||
120 | uint64_t value; | ||
121 | |||
122 | switch (offset) { | ||
123 | + case 0x34: | ||
124 | + value = s->irq_sts; | ||
125 | + break; | ||
126 | case 0x38: | ||
127 | case 0x3C: | ||
128 | default: | ||
129 | @@ -XXX,XX +XXX,XX @@ static void aspeed_2600_timer_write(AspeedTimerCtrlState *s, hwaddr offset, | ||
130 | const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF); | ||
131 | |||
132 | switch (offset) { | ||
133 | + case 0x34: | ||
134 | + s->irq_sts &= tv; | ||
135 | + break; | ||
136 | case 0x3C: | ||
137 | aspeed_timer_set_ctrl(s, s->ctrl & ~tv); | ||
138 | break; | ||
139 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_reset(DeviceState *dev) | ||
140 | s->ctrl = 0; | ||
141 | s->ctrl2 = 0; | ||
142 | s->ctrl3 = 0; | ||
143 | + s->irq_sts = 0; | ||
144 | } | 86 | } |
145 | |||
146 | static const VMStateDescription vmstate_aspeed_timer = { | ||
147 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_timer = { | ||
148 | |||
149 | static const VMStateDescription vmstate_aspeed_timer_state = { | ||
150 | .name = "aspeed.timerctrl", | ||
151 | - .version_id = 1, | ||
152 | - .minimum_version_id = 1, | ||
153 | + .version_id = 2, | ||
154 | + .minimum_version_id = 2, | ||
155 | .fields = (VMStateField[]) { | ||
156 | VMSTATE_UINT32(ctrl, AspeedTimerCtrlState), | ||
157 | VMSTATE_UINT32(ctrl2, AspeedTimerCtrlState), | ||
158 | VMSTATE_UINT32(ctrl3, AspeedTimerCtrlState), | ||
159 | + VMSTATE_UINT32(irq_sts, AspeedTimerCtrlState), | ||
160 | VMSTATE_STRUCT_ARRAY(timers, AspeedTimerCtrlState, | ||
161 | ASPEED_TIMER_NR_TIMERS, 1, vmstate_aspeed_timer, | ||
162 | AspeedTimer), | ||
163 | -- | 87 | -- |
164 | 2.20.1 | 88 | 2.20.1 |
165 | 89 | ||
166 | 90 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Peter Collingbourne <pcc@google.com> |
---|---|---|---|
2 | 2 | ||
3 | Various logging improvements as once: | 3 | Section D6.7 of the ARM ARM states: |
4 | - Use 0x prefix for hex numbers | ||
5 | - Display value written during write accesses | ||
6 | - Move some logs from GUEST_ERROR to UNIMP | ||
7 | 4 | ||
8 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 5 | For the purpose of determining Tag Check Fault handling, unprivileged |
9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 6 | load and store instructions are treated as if executed at EL0 when |
10 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 7 | executed at either: |
11 | Reviewed-by: Cleber Rosa <crosa@redhat.com> | 8 | - EL1, when the Effective value of PSTATE.UAO is 0. |
12 | Message-id: 20190926173428.10713-3-f4bug@amsat.org | 9 | - EL2, when both the Effective value of HCR_EL2.{E2H, TGE} is {1, 1} |
10 | and the Effective value of PSTATE.UAO is 0. | ||
11 | |||
12 | ARM has confirmed a defect in the pseudocode function | ||
13 | AArch64.TagCheckFault that makes it inconsistent with the above | ||
14 | wording. The remedy is to adjust references to PSTATE.EL in that | ||
15 | function to instead refer to AArch64.AccessUsesEL(acctype), so | ||
16 | that unprivileged instructions use SCTLR_EL1.TCF0 and TFSRE0_EL1. | ||
17 | The exception type for synchronous tag check faults remains unchanged. | ||
18 | |||
19 | This patch implements the described change by partially reverting | ||
20 | commits 50244cc76abc and cc97b0019bb5. | ||
21 | |||
22 | Signed-off-by: Peter Collingbourne <pcc@google.com> | ||
23 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
24 | Message-id: 20210219201820.2672077-1-pcc@google.com | ||
25 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 27 | --- |
15 | hw/char/bcm2835_aux.c | 5 +++-- | 28 | target/arm/helper.c | 2 +- |
16 | hw/dma/bcm2835_dma.c | 8 ++++---- | 29 | target/arm/mte_helper.c | 13 +++++++++---- |
17 | hw/intc/bcm2836_control.c | 7 ++++--- | 30 | 2 files changed, 10 insertions(+), 5 deletions(-) |
18 | hw/misc/bcm2835_mbox.c | 7 ++++--- | ||
19 | hw/misc/bcm2835_property.c | 16 ++++++++++------ | ||
20 | 5 files changed, 25 insertions(+), 18 deletions(-) | ||
21 | 31 | ||
22 | diff --git a/hw/char/bcm2835_aux.c b/hw/char/bcm2835_aux.c | 32 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
23 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/hw/char/bcm2835_aux.c | 34 | --- a/target/arm/helper.c |
25 | +++ b/hw/char/bcm2835_aux.c | 35 | +++ b/target/arm/helper.c |
26 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_aux_write(void *opaque, hwaddr offset, uint64_t value, | 36 | @@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, |
27 | switch (offset) { | 37 | if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV) |
28 | case AUX_ENABLES: | 38 | && tbid |
29 | if (value != 1) { | 39 | && !(env->pstate & PSTATE_TCO) |
30 | - qemu_log_mask(LOG_UNIMP, "%s: unsupported attempt to enable SPI " | 40 | - && (sctlr & SCTLR_TCF) |
31 | - "or disable UART\n", __func__); | 41 | + && (sctlr & SCTLR_TCF0) |
32 | + qemu_log_mask(LOG_UNIMP, "%s: unsupported attempt to enable SPI" | 42 | && allocation_tag_access_enabled(env, 0, sctlr)) { |
33 | + " or disable UART: 0x%"PRIx64"\n", | 43 | flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1); |
34 | + __func__, value); | ||
35 | } | 44 | } |
36 | break; | 45 | diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c |
37 | |||
38 | diff --git a/hw/dma/bcm2835_dma.c b/hw/dma/bcm2835_dma.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | 46 | index XXXXXXX..XXXXXXX 100644 |
40 | --- a/hw/dma/bcm2835_dma.c | 47 | --- a/target/arm/mte_helper.c |
41 | +++ b/hw/dma/bcm2835_dma.c | 48 | +++ b/target/arm/mte_helper.c |
42 | @@ -XXX,XX +XXX,XX @@ static uint64_t bcm2835_dma_read(BCM2835DMAState *s, hwaddr offset, | 49 | @@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc, |
43 | res = ch->debug; | 50 | reg_el = regime_el(env, arm_mmu_idx); |
44 | break; | 51 | sctlr = env->cp15.sctlr_el[reg_el]; |
45 | default: | 52 | |
46 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", | 53 | - el = arm_current_el(env); |
47 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n", | 54 | - if (el == 0) { |
48 | __func__, offset); | 55 | + switch (arm_mmu_idx) { |
49 | break; | 56 | + case ARMMMUIdx_E10_0: |
57 | + case ARMMMUIdx_E20_0: | ||
58 | + el = 0; | ||
59 | tcf = extract64(sctlr, 38, 2); | ||
60 | - } else { | ||
61 | + break; | ||
62 | + default: | ||
63 | + el = reg_el; | ||
64 | tcf = extract64(sctlr, 40, 2); | ||
50 | } | 65 | } |
51 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_dma_write(BCM2835DMAState *s, hwaddr offset, | 66 | |
52 | ch->debug = value; | 67 | @@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc, |
53 | break; | 68 | env->exception.vaddress = dirty_ptr; |
54 | default: | 69 | |
55 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", | 70 | is_write = FIELD_EX32(desc, MTEDESC, WRITE); |
56 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n", | 71 | - syn = syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, is_write, 0x11); |
57 | __func__, offset); | 72 | + syn = syn_data_abort_no_iss(arm_current_el(env) != 0, 0, 0, 0, 0, |
58 | break; | 73 | + is_write, 0x11); |
59 | } | 74 | raise_exception(env, EXCP_DATA_ABORT, syn, exception_target_el(env)); |
60 | @@ -XXX,XX +XXX,XX @@ static uint64_t bcm2835_dma0_read(void *opaque, hwaddr offset, unsigned size) | 75 | /* noreturn, but fall through to the assert anyway */ |
61 | case BCM2708_DMA_ENABLE: | ||
62 | return s->enable; | ||
63 | default: | ||
64 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", | ||
65 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n", | ||
66 | __func__, offset); | ||
67 | return 0; | ||
68 | } | ||
69 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_dma0_write(void *opaque, hwaddr offset, uint64_t value, | ||
70 | s->enable = (value & 0xffff); | ||
71 | break; | ||
72 | default: | ||
73 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", | ||
74 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n", | ||
75 | __func__, offset); | ||
76 | } | ||
77 | } | ||
78 | diff --git a/hw/intc/bcm2836_control.c b/hw/intc/bcm2836_control.c | ||
79 | index XXXXXXX..XXXXXXX 100644 | ||
80 | --- a/hw/intc/bcm2836_control.c | ||
81 | +++ b/hw/intc/bcm2836_control.c | ||
82 | @@ -XXX,XX +XXX,XX @@ static uint64_t bcm2836_control_read(void *opaque, hwaddr offset, unsigned size) | ||
83 | } else if (offset >= REG_MBOX0_RDCLR && offset < REG_LIMIT) { | ||
84 | return s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2]; | ||
85 | } else { | ||
86 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", | ||
87 | + qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx"\n", | ||
88 | __func__, offset); | ||
89 | return 0; | ||
90 | } | ||
91 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_control_write(void *opaque, hwaddr offset, | ||
92 | } else if (offset >= REG_MBOX0_RDCLR && offset < REG_LIMIT) { | ||
93 | s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2] &= ~val; | ||
94 | } else { | ||
95 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", | ||
96 | - __func__, offset); | ||
97 | + qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx | ||
98 | + " value 0x%"PRIx64"\n", | ||
99 | + __func__, offset, val); | ||
100 | return; | ||
101 | } | ||
102 | |||
103 | diff --git a/hw/misc/bcm2835_mbox.c b/hw/misc/bcm2835_mbox.c | ||
104 | index XXXXXXX..XXXXXXX 100644 | ||
105 | --- a/hw/misc/bcm2835_mbox.c | ||
106 | +++ b/hw/misc/bcm2835_mbox.c | ||
107 | @@ -XXX,XX +XXX,XX @@ static uint64_t bcm2835_mbox_read(void *opaque, hwaddr offset, unsigned size) | ||
108 | break; | ||
109 | |||
110 | default: | ||
111 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", | ||
112 | + qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx"\n", | ||
113 | __func__, offset); | ||
114 | return 0; | ||
115 | } | ||
116 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_mbox_write(void *opaque, hwaddr offset, | ||
117 | break; | ||
118 | |||
119 | default: | ||
120 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", | ||
121 | - __func__, offset); | ||
122 | + qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx | ||
123 | + " value 0x%"PRIx64"\n", | ||
124 | + __func__, offset, value); | ||
125 | return; | ||
126 | } | ||
127 | |||
128 | diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c | ||
129 | index XXXXXXX..XXXXXXX 100644 | ||
130 | --- a/hw/misc/bcm2835_property.c | ||
131 | +++ b/hw/misc/bcm2835_property.c | ||
132 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) | ||
133 | break; | ||
134 | case 0x00010001: /* Get board model */ | ||
135 | qemu_log_mask(LOG_UNIMP, | ||
136 | - "bcm2835_property: %x get board model NYI\n", tag); | ||
137 | + "bcm2835_property: 0x%08x get board model NYI\n", | ||
138 | + tag); | ||
139 | resplen = 4; | ||
140 | break; | ||
141 | case 0x00010002: /* Get board revision */ | ||
142 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) | ||
143 | break; | ||
144 | case 0x00010004: /* Get board serial */ | ||
145 | qemu_log_mask(LOG_UNIMP, | ||
146 | - "bcm2835_property: %x get board serial NYI\n", tag); | ||
147 | + "bcm2835_property: 0x%08x get board serial NYI\n", | ||
148 | + tag); | ||
149 | resplen = 8; | ||
150 | break; | ||
151 | case 0x00010005: /* Get ARM memory */ | ||
152 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) | ||
153 | |||
154 | case 0x00038001: /* Set clock state */ | ||
155 | qemu_log_mask(LOG_UNIMP, | ||
156 | - "bcm2835_property: %x set clock state NYI\n", tag); | ||
157 | + "bcm2835_property: 0x%08x set clock state NYI\n", | ||
158 | + tag); | ||
159 | resplen = 8; | ||
160 | break; | ||
161 | |||
162 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) | ||
163 | case 0x00038004: /* Set max clock rate */ | ||
164 | case 0x00038007: /* Set min clock rate */ | ||
165 | qemu_log_mask(LOG_UNIMP, | ||
166 | - "bcm2835_property: %x set clock rates NYI\n", tag); | ||
167 | + "bcm2835_property: 0x%08x set clock rate NYI\n", | ||
168 | + tag); | ||
169 | resplen = 8; | ||
170 | break; | ||
171 | |||
172 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) | ||
173 | break; | ||
174 | |||
175 | default: | ||
176 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
177 | - "bcm2835_property: unhandled tag %08x\n", tag); | ||
178 | + qemu_log_mask(LOG_UNIMP, | ||
179 | + "bcm2835_property: unhandled tag 0x%08x\n", tag); | ||
180 | break; | ||
181 | } | ||
182 | 76 | ||
183 | -- | 77 | -- |
184 | 2.20.1 | 78 | 2.20.1 |
185 | 79 | ||
186 | 80 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | It prepares ground for the AST2600. | 3 | IDAU is specific to M-profile. KVM only supports A-profile. |
4 | Restrict this interface to TCG, as it is pointless (and | ||
5 | confusing) on a KVM-only build. | ||
4 | 6 | ||
5 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Reviewed-by: Joel Stanley <joel@jms.id.au> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Message-id: 20190925143248.10000-18-clg@kaod.org | 9 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
10 | Message-id: 20210221222617.2579610-2-f4bug@amsat.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 12 | --- |
10 | include/hw/arm/aspeed_soc.h | 9 +-- | 13 | target/arm/cpu.c | 7 ------- |
11 | hw/arm/aspeed.c | 4 +- | 14 | target/arm/cpu_tcg.c | 8 ++++++++ |
12 | hw/arm/aspeed_soc.c | 148 +++++++++++++++++++----------------- | 15 | 2 files changed, 8 insertions(+), 7 deletions(-) |
13 | 3 files changed, 84 insertions(+), 77 deletions(-) | ||
14 | 16 | ||
15 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | 17 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
16 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/include/hw/arm/aspeed_soc.h | 19 | --- a/target/arm/cpu.c |
18 | +++ b/include/hw/arm/aspeed_soc.h | 20 | +++ b/target/arm/cpu.c |
19 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState { | 21 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo arm_cpu_type_info = { |
20 | #define TYPE_ASPEED_SOC "aspeed-soc" | 22 | .class_init = arm_cpu_class_init, |
21 | #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC) | 23 | }; |
22 | 24 | ||
23 | -typedef struct AspeedSoCInfo { | 25 | -static const TypeInfo idau_interface_type_info = { |
24 | +typedef struct AspeedSoCClass { | 26 | - .name = TYPE_IDAU_INTERFACE, |
25 | + DeviceClass parent_class; | 27 | - .parent = TYPE_INTERFACE, |
26 | + | 28 | - .class_size = sizeof(IDAUInterfaceClass), |
27 | const char *name; | ||
28 | const char *cpu_type; | ||
29 | uint32_t silicon_rev; | ||
30 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCInfo { | ||
31 | const int *irqmap; | ||
32 | const hwaddr *memmap; | ||
33 | uint32_t num_cpus; | ||
34 | -} AspeedSoCInfo; | ||
35 | - | ||
36 | -typedef struct AspeedSoCClass { | ||
37 | - DeviceClass parent_class; | ||
38 | - AspeedSoCInfo *info; | ||
39 | } AspeedSoCClass; | ||
40 | |||
41 | #define ASPEED_SOC_CLASS(klass) \ | ||
42 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/hw/arm/aspeed.c | ||
45 | +++ b/hw/arm/aspeed.c | ||
46 | @@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine, | ||
47 | memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size); | ||
48 | memory_region_add_subregion(&bmc->ram_container, 0, &bmc->ram); | ||
49 | memory_region_add_subregion(get_system_memory(), | ||
50 | - sc->info->memmap[ASPEED_SDRAM], | ||
51 | + sc->memmap[ASPEED_SDRAM], | ||
52 | &bmc->ram_container); | ||
53 | |||
54 | max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", | ||
55 | @@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine, | ||
56 | } | ||
57 | |||
58 | aspeed_board_binfo.ram_size = ram_size; | ||
59 | - aspeed_board_binfo.loader_start = sc->info->memmap[ASPEED_SDRAM]; | ||
60 | + aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM]; | ||
61 | aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus; | ||
62 | |||
63 | if (cfg->i2c_init) { | ||
64 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
65 | index XXXXXXX..XXXXXXX 100644 | ||
66 | --- a/hw/arm/aspeed_soc.c | ||
67 | +++ b/hw/arm/aspeed_soc.c | ||
68 | @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2400_irqmap[] = { | ||
69 | |||
70 | #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap | ||
71 | |||
72 | -static const AspeedSoCInfo aspeed_socs[] = { | ||
73 | - { | ||
74 | - .name = "ast2400-a1", | ||
75 | - .cpu_type = ARM_CPU_TYPE_NAME("arm926"), | ||
76 | - .silicon_rev = AST2400_A1_SILICON_REV, | ||
77 | - .sram_size = 0x8000, | ||
78 | - .spis_num = 1, | ||
79 | - .wdts_num = 2, | ||
80 | - .irqmap = aspeed_soc_ast2400_irqmap, | ||
81 | - .memmap = aspeed_soc_ast2400_memmap, | ||
82 | - .num_cpus = 1, | ||
83 | - }, { | ||
84 | - .name = "ast2500-a1", | ||
85 | - .cpu_type = ARM_CPU_TYPE_NAME("arm1176"), | ||
86 | - .silicon_rev = AST2500_A1_SILICON_REV, | ||
87 | - .sram_size = 0x9000, | ||
88 | - .spis_num = 2, | ||
89 | - .wdts_num = 3, | ||
90 | - .irqmap = aspeed_soc_ast2500_irqmap, | ||
91 | - .memmap = aspeed_soc_ast2500_memmap, | ||
92 | - .num_cpus = 1, | ||
93 | - }, | ||
94 | -}; | 29 | -}; |
95 | - | 30 | - |
96 | static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) | 31 | static void arm_cpu_register_types(void) |
97 | { | 32 | { |
98 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | 33 | const size_t cpu_count = ARRAY_SIZE(arm_cpus); |
99 | 34 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void) | |
100 | - return qdev_get_gpio_in(DEVICE(&s->vic), sc->info->irqmap[ctrl]); | 35 | if (cpu_count) { |
101 | + return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[ctrl]); | 36 | size_t i; |
102 | } | 37 | |
103 | 38 | - type_register_static(&idau_interface_type_info); | |
104 | static void aspeed_soc_init(Object *obj) | 39 | for (i = 0; i < cpu_count; ++i) { |
105 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | 40 | arm_cpu_register(&arm_cpus[i]); |
106 | char socname[8]; | ||
107 | char typename[64]; | ||
108 | |||
109 | - if (sscanf(sc->info->name, "%7s", socname) != 1) { | ||
110 | + if (sscanf(sc->name, "%7s", socname) != 1) { | ||
111 | g_assert_not_reached(); | ||
112 | } | ||
113 | |||
114 | - for (i = 0; i < sc->info->num_cpus; i++) { | ||
115 | + for (i = 0; i < sc->num_cpus; i++) { | ||
116 | object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), | ||
117 | - sizeof(s->cpu[i]), sc->info->cpu_type, | ||
118 | + sizeof(s->cpu[i]), sc->cpu_type, | ||
119 | &error_abort, NULL); | ||
120 | } | ||
121 | |||
122 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | ||
123 | sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu), | ||
124 | typename); | ||
125 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", | ||
126 | - sc->info->silicon_rev); | ||
127 | + sc->silicon_rev); | ||
128 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), | ||
129 | "hw-strap1", &error_abort); | ||
130 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), | ||
131 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | ||
132 | object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram", | ||
133 | &error_abort); | ||
134 | |||
135 | - for (i = 0; i < sc->info->spis_num; i++) { | ||
136 | + for (i = 0; i < sc->spis_num; i++) { | ||
137 | snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); | ||
138 | sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]), | ||
139 | sizeof(s->spi[i]), typename); | ||
140 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | ||
141 | object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), | ||
142 | "max-ram-size", &error_abort); | ||
143 | |||
144 | - for (i = 0; i < sc->info->wdts_num; i++) { | ||
145 | + for (i = 0; i < sc->wdts_num; i++) { | ||
146 | snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); | ||
147 | sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]), | ||
148 | sizeof(s->wdt[i]), typename); | ||
149 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
150 | Error *err = NULL, *local_err = NULL; | ||
151 | |||
152 | /* IO space */ | ||
153 | - create_unimplemented_device("aspeed_soc.io", sc->info->memmap[ASPEED_IOMEM], | ||
154 | + create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], | ||
155 | ASPEED_SOC_IOMEM_SIZE); | ||
156 | |||
157 | - if (s->num_cpus > sc->info->num_cpus) { | ||
158 | + if (s->num_cpus > sc->num_cpus) { | ||
159 | warn_report("%s: invalid number of CPUs %d, using default %d", | ||
160 | - sc->info->name, s->num_cpus, sc->info->num_cpus); | ||
161 | - s->num_cpus = sc->info->num_cpus; | ||
162 | + sc->name, s->num_cpus, sc->num_cpus); | ||
163 | + s->num_cpus = sc->num_cpus; | ||
164 | } | ||
165 | |||
166 | /* CPU */ | ||
167 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
168 | |||
169 | /* SRAM */ | ||
170 | memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", | ||
171 | - sc->info->sram_size, &err); | ||
172 | + sc->sram_size, &err); | ||
173 | if (err) { | ||
174 | error_propagate(errp, err); | ||
175 | return; | ||
176 | } | ||
177 | memory_region_add_subregion(get_system_memory(), | ||
178 | - sc->info->memmap[ASPEED_SRAM], &s->sram); | ||
179 | + sc->memmap[ASPEED_SRAM], &s->sram); | ||
180 | |||
181 | /* SCU */ | ||
182 | object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); | ||
183 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
184 | error_propagate(errp, err); | ||
185 | return; | ||
186 | } | ||
187 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->info->memmap[ASPEED_SCU]); | ||
188 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]); | ||
189 | |||
190 | /* VIC */ | ||
191 | object_property_set_bool(OBJECT(&s->vic), true, "realized", &err); | ||
192 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
193 | error_propagate(errp, err); | ||
194 | return; | ||
195 | } | ||
196 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->info->memmap[ASPEED_VIC]); | ||
197 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_VIC]); | ||
198 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0, | ||
199 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); | ||
200 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1, | ||
201 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
202 | error_propagate(errp, err); | ||
203 | return; | ||
204 | } | ||
205 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->info->memmap[ASPEED_RTC]); | ||
206 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]); | ||
207 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, | ||
208 | aspeed_soc_get_irq(s, ASPEED_RTC)); | ||
209 | |||
210 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
211 | return; | ||
212 | } | ||
213 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, | ||
214 | - sc->info->memmap[ASPEED_TIMER1]); | ||
215 | + sc->memmap[ASPEED_TIMER1]); | ||
216 | for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { | ||
217 | qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); | ||
218 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); | ||
219 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
220 | /* UART - attach an 8250 to the IO space as our UART5 */ | ||
221 | if (serial_hd(0)) { | ||
222 | qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5); | ||
223 | - serial_mm_init(get_system_memory(), sc->info->memmap[ASPEED_UART5], 2, | ||
224 | + serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2, | ||
225 | uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); | ||
226 | } | ||
227 | |||
228 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
229 | error_propagate(errp, err); | ||
230 | return; | ||
231 | } | ||
232 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->info->memmap[ASPEED_I2C]); | ||
233 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]); | ||
234 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, | ||
235 | aspeed_soc_get_irq(s, ASPEED_I2C)); | ||
236 | |||
237 | /* FMC, The number of CS is set at the board level */ | ||
238 | - object_property_set_int(OBJECT(&s->fmc), sc->info->memmap[ASPEED_SDRAM], | ||
239 | + object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], | ||
240 | "sdram-base", &err); | ||
241 | if (err) { | ||
242 | error_propagate(errp, err); | ||
243 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
244 | error_propagate(errp, err); | ||
245 | return; | ||
246 | } | ||
247 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->info->memmap[ASPEED_FMC]); | ||
248 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]); | ||
249 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, | ||
250 | s->fmc.ctrl->flash_window_base); | ||
251 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, | ||
252 | aspeed_soc_get_irq(s, ASPEED_FMC)); | ||
253 | |||
254 | /* SPI */ | ||
255 | - for (i = 0; i < sc->info->spis_num; i++) { | ||
256 | + for (i = 0; i < sc->spis_num; i++) { | ||
257 | object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err); | ||
258 | object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", | ||
259 | &local_err); | ||
260 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
261 | return; | ||
262 | } | 41 | } |
263 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, | 42 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c |
264 | - sc->info->memmap[ASPEED_SPI1 + i]); | 43 | index XXXXXXX..XXXXXXX 100644 |
265 | + sc->memmap[ASPEED_SPI1 + i]); | 44 | --- a/target/arm/cpu_tcg.c |
266 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, | 45 | +++ b/target/arm/cpu_tcg.c |
267 | s->spi[i].ctrl->flash_window_base); | 46 | @@ -XXX,XX +XXX,XX @@ |
268 | } | 47 | #include "hw/core/tcg-cpu-ops.h" |
269 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | 48 | #endif /* CONFIG_TCG */ |
270 | error_propagate(errp, err); | 49 | #include "internals.h" |
271 | return; | 50 | +#include "target/arm/idau.h" |
272 | } | 51 | |
273 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->info->memmap[ASPEED_SDMC]); | 52 | /* CPU models. These are not needed for the AArch64 linux-user build. */ |
274 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]); | 53 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) |
275 | 54 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = { | |
276 | /* Watch dog */ | 55 | { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, |
277 | - for (i = 0; i < sc->info->wdts_num; i++) { | ||
278 | + for (i = 0; i < sc->wdts_num; i++) { | ||
279 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); | ||
280 | |||
281 | object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); | ||
282 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
283 | return; | ||
284 | } | ||
285 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | ||
286 | - sc->info->memmap[ASPEED_WDT] + i * awc->offset); | ||
287 | + sc->memmap[ASPEED_WDT] + i * awc->offset); | ||
288 | } | ||
289 | |||
290 | /* Net */ | ||
291 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
292 | return; | ||
293 | } | ||
294 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | ||
295 | - sc->info->memmap[ASPEED_ETH1 + i]); | ||
296 | + sc->memmap[ASPEED_ETH1 + i]); | ||
297 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | ||
298 | aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); | ||
299 | } | ||
300 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
301 | return; | ||
302 | } | ||
303 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, | ||
304 | - sc->info->memmap[ASPEED_XDMA]); | ||
305 | + sc->memmap[ASPEED_XDMA]); | ||
306 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, | ||
307 | aspeed_soc_get_irq(s, ASPEED_XDMA)); | ||
308 | |||
309 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
310 | error_propagate(errp, err); | ||
311 | return; | ||
312 | } | ||
313 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->info->memmap[ASPEED_GPIO]); | ||
314 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]); | ||
315 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, | ||
316 | aspeed_soc_get_irq(s, ASPEED_GPIO)); | ||
317 | |||
318 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
319 | return; | ||
320 | } | ||
321 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, | ||
322 | - sc->info->memmap[ASPEED_SDHCI]); | ||
323 | + sc->memmap[ASPEED_SDHCI]); | ||
324 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, | ||
325 | aspeed_soc_get_irq(s, ASPEED_SDHCI)); | ||
326 | } | ||
327 | @@ -XXX,XX +XXX,XX @@ static Property aspeed_soc_properties[] = { | ||
328 | static void aspeed_soc_class_init(ObjectClass *oc, void *data) | ||
329 | { | ||
330 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
331 | - AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | ||
332 | |||
333 | - sc->info = (AspeedSoCInfo *) data; | ||
334 | dc->realize = aspeed_soc_realize; | ||
335 | /* Reason: Uses serial_hds and nd_table in realize() directly */ | ||
336 | dc->user_creatable = false; | ||
337 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data) | ||
338 | static const TypeInfo aspeed_soc_type_info = { | ||
339 | .name = TYPE_ASPEED_SOC, | ||
340 | .parent = TYPE_DEVICE, | ||
341 | - .instance_init = aspeed_soc_init, | ||
342 | .instance_size = sizeof(AspeedSoCState), | ||
343 | .class_size = sizeof(AspeedSoCClass), | ||
344 | + .class_init = aspeed_soc_class_init, | ||
345 | .abstract = true, | ||
346 | }; | 56 | }; |
347 | 57 | ||
348 | -static void aspeed_soc_register_types(void) | 58 | +static const TypeInfo idau_interface_type_info = { |
349 | +static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) | 59 | + .name = TYPE_IDAU_INTERFACE, |
350 | { | 60 | + .parent = TYPE_INTERFACE, |
351 | - int i; | 61 | + .class_size = sizeof(IDAUInterfaceClass), |
352 | + AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | ||
353 | |||
354 | - type_register_static(&aspeed_soc_type_info); | ||
355 | - for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) { | ||
356 | - TypeInfo ti = { | ||
357 | - .name = aspeed_socs[i].name, | ||
358 | - .parent = TYPE_ASPEED_SOC, | ||
359 | - .class_init = aspeed_soc_class_init, | ||
360 | - .class_data = (void *) &aspeed_socs[i], | ||
361 | - }; | ||
362 | - type_register(&ti); | ||
363 | - } | ||
364 | + sc->name = "ast2400-a1"; | ||
365 | + sc->cpu_type = ARM_CPU_TYPE_NAME("arm926"); | ||
366 | + sc->silicon_rev = AST2400_A1_SILICON_REV; | ||
367 | + sc->sram_size = 0x8000; | ||
368 | + sc->spis_num = 1; | ||
369 | + sc->wdts_num = 2; | ||
370 | + sc->irqmap = aspeed_soc_ast2400_irqmap; | ||
371 | + sc->memmap = aspeed_soc_ast2400_memmap; | ||
372 | + sc->num_cpus = 1; | ||
373 | } | ||
374 | |||
375 | +static const TypeInfo aspeed_soc_ast2400_type_info = { | ||
376 | + .name = "ast2400-a1", | ||
377 | + .parent = TYPE_ASPEED_SOC, | ||
378 | + .instance_init = aspeed_soc_init, | ||
379 | + .instance_size = sizeof(AspeedSoCState), | ||
380 | + .class_init = aspeed_soc_ast2400_class_init, | ||
381 | +}; | 62 | +}; |
382 | + | 63 | + |
383 | +static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) | 64 | static void arm_tcg_cpu_register_types(void) |
384 | +{ | 65 | { |
385 | + AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | 66 | size_t i; |
386 | + | 67 | |
387 | + sc->name = "ast2500-a1"; | 68 | + type_register_static(&idau_interface_type_info); |
388 | + sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); | 69 | for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) { |
389 | + sc->silicon_rev = AST2500_A1_SILICON_REV; | 70 | arm_cpu_register(&arm_tcg_cpus[i]); |
390 | + sc->sram_size = 0x9000; | 71 | } |
391 | + sc->spis_num = 2; | ||
392 | + sc->wdts_num = 3; | ||
393 | + sc->irqmap = aspeed_soc_ast2500_irqmap; | ||
394 | + sc->memmap = aspeed_soc_ast2500_memmap; | ||
395 | + sc->num_cpus = 1; | ||
396 | +} | ||
397 | + | ||
398 | +static const TypeInfo aspeed_soc_ast2500_type_info = { | ||
399 | + .name = "ast2500-a1", | ||
400 | + .parent = TYPE_ASPEED_SOC, | ||
401 | + .instance_init = aspeed_soc_init, | ||
402 | + .instance_size = sizeof(AspeedSoCState), | ||
403 | + .class_init = aspeed_soc_ast2500_class_init, | ||
404 | +}; | ||
405 | +static void aspeed_soc_register_types(void) | ||
406 | +{ | ||
407 | + type_register_static(&aspeed_soc_type_info); | ||
408 | + type_register_static(&aspeed_soc_ast2400_type_info); | ||
409 | + type_register_static(&aspeed_soc_ast2500_type_info); | ||
410 | +}; | ||
411 | + | ||
412 | type_init(aspeed_soc_register_types) | ||
413 | -- | 72 | -- |
414 | 2.20.1 | 73 | 2.20.1 |
415 | 74 | ||
416 | 75 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | Add trace events for read/write accesses and IRQ. | 3 | We will move this code in the next commit. Clean it up |
4 | 4 | first to avoid checkpatch.pl errors. | |
5 | Properties are structures used for the ARM particular MBOX. | ||
6 | Since one call in bcm2835_property.c concerns the mbox block, | ||
7 | name this trace event in the same bcm2835_mbox* namespace. | ||
8 | 5 | ||
9 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 6 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
10 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 7 | Message-id: 20210221222617.2579610-3-f4bug@amsat.org |
11 | Message-id: 20190926173428.10713-8-f4bug@amsat.org | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 10 | --- |
14 | hw/misc/bcm2835_mbox.c | 5 +++++ | 11 | target/arm/cpu.c | 12 ++++++++---- |
15 | hw/misc/bcm2835_property.c | 2 ++ | 12 | 1 file changed, 8 insertions(+), 4 deletions(-) |
16 | hw/misc/trace-events | 6 ++++++ | ||
17 | 3 files changed, 13 insertions(+) | ||
18 | 13 | ||
19 | diff --git a/hw/misc/bcm2835_mbox.c b/hw/misc/bcm2835_mbox.c | 14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
20 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/misc/bcm2835_mbox.c | 16 | --- a/target/arm/cpu.c |
22 | +++ b/hw/misc/bcm2835_mbox.c | 17 | +++ b/target/arm/cpu.c |
23 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj) |
24 | #include "migration/vmstate.h" | ||
25 | #include "qemu/log.h" | ||
26 | #include "qemu/module.h" | ||
27 | +#include "trace.h" | ||
28 | |||
29 | #define MAIL0_PEEK 0x90 | ||
30 | #define MAIL0_SENDER 0x94 | ||
31 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_mbox_update(BCM2835MboxState *s) | ||
32 | set = true; | ||
33 | } | ||
34 | } | ||
35 | + trace_bcm2835_mbox_irq(set); | ||
36 | qemu_set_irq(s->arm_irq, set); | ||
37 | } | 19 | } |
38 | 20 | ||
39 | @@ -XXX,XX +XXX,XX @@ static uint64_t bcm2835_mbox_read(void *opaque, hwaddr offset, unsigned size) | 21 | static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
40 | default: | 22 | - /* power_control should be set to maximum latency. Again, |
41 | qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx"\n", | 23 | + /* |
42 | __func__, offset); | 24 | + * power_control should be set to maximum latency. Again, |
43 | + trace_bcm2835_mbox_read(size, offset, res); | 25 | * default to 0 and set by private hook |
44 | return 0; | 26 | */ |
45 | } | 27 | { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
46 | + trace_bcm2835_mbox_read(size, offset, res); | 28 | @@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj) |
47 | 29 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
48 | bcm2835_mbox_update(s); | 30 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
49 | 31 | set_feature(&cpu->env, ARM_FEATURE_EL3); | |
50 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_mbox_write(void *opaque, hwaddr offset, | 32 | - /* Note that A9 supports the MP extensions even for |
51 | 33 | + /* | |
52 | offset &= 0xff; | 34 | + * Note that A9 supports the MP extensions even for |
53 | 35 | * A9UP and single-core A9MP (which are both different | |
54 | + trace_bcm2835_mbox_write(size, offset, value); | 36 | * and valid configurations; we don't model A9UP). |
55 | switch (offset) { | 37 | */ |
56 | case MAIL0_SENDER: | 38 | @@ -XXX,XX +XXX,XX @@ static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
57 | break; | 39 | { |
58 | diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c | 40 | MachineState *ms = MACHINE(qdev_get_machine()); |
59 | index XXXXXXX..XXXXXXX 100644 | 41 | |
60 | --- a/hw/misc/bcm2835_property.c | 42 | - /* Linux wants the number of processors from here. |
61 | +++ b/hw/misc/bcm2835_property.c | 43 | + /* |
62 | @@ -XXX,XX +XXX,XX @@ | 44 | + * Linux wants the number of processors from here. |
63 | #include "sysemu/dma.h" | 45 | * Might as well set the interrupt-controller bit too. |
64 | #include "qemu/log.h" | 46 | */ |
65 | #include "qemu/module.h" | 47 | return ((ms->smp.cpus - 1) << 24) | (1 << 23); |
66 | +#include "trace.h" | 48 | @@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj) |
67 | 49 | cpu->isar.id_mmfr1 = 0x40000000; | |
68 | /* https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface */ | 50 | cpu->isar.id_mmfr2 = 0x01240000; |
69 | 51 | cpu->isar.id_mmfr3 = 0x02102211; | |
70 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) | 52 | - /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but |
71 | break; | 53 | + /* |
72 | } | 54 | + * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but |
73 | 55 | * table 4-41 gives 0x02101110, which includes the arm div insns. | |
74 | + trace_bcm2835_mbox_property(tag, bufsize, resplen); | 56 | */ |
75 | if (tag == 0) { | 57 | cpu->isar.id_isar0 = 0x02101110; |
76 | break; | ||
77 | } | ||
78 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
79 | index XXXXXXX..XXXXXXX 100644 | ||
80 | --- a/hw/misc/trace-events | ||
81 | +++ b/hw/misc/trace-events | ||
82 | @@ -XXX,XX +XXX,XX @@ armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU wri | ||
83 | |||
84 | # aspeed_xdma.c | ||
85 | aspeed_xdma_write(uint64_t offset, uint64_t data) "XDMA write: offset 0x%" PRIx64 " data 0x%" PRIx64 | ||
86 | + | ||
87 | +# bcm2835_mbox.c | ||
88 | +bcm2835_mbox_write(unsigned int size, uint64_t addr, uint64_t value) "mbox write sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 | ||
89 | +bcm2835_mbox_read(unsigned int size, uint64_t addr, uint64_t value) "mbox read sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 | ||
90 | +bcm2835_mbox_irq(unsigned level) "mbox irq:ARM level:%u" | ||
91 | +bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbox property tag:0x%08x in_sz:%u out_sz:%zu" | ||
92 | -- | 58 | -- |
93 | 2.20.1 | 59 | 2.20.1 |
94 | 60 | ||
95 | 61 | diff view generated by jsdifflib |
1 | Switch the musicpal code away from bottom-half based ptimers to | 1 | For a long time now the UI layer has guaranteed that the console |
---|---|---|---|
2 | the new transaction-based ptimer API. This just requires adding | 2 | surface is always 32 bits per pixel RGB. Remove the legacy dead |
3 | begin/commit calls around the various places that modify the ptimer | 3 | code from the milkymist display device which was handling the |
4 | state, and using the new ptimer_init() function to create the timer. | 4 | possibility that the console surface was some other format. |
5 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20191008171740.9679-6-peter.maydell@linaro.org | 8 | Message-id: 20210215103215.4944-2-peter.maydell@linaro.org |
9 | --- | 9 | --- |
10 | hw/arm/musicpal.c | 16 ++++++++++------ | 10 | hw/arm/musicpal.c | 64 ++++++++++++++++++----------------------------- |
11 | 1 file changed, 10 insertions(+), 6 deletions(-) | 11 | 1 file changed, 24 insertions(+), 40 deletions(-) |
12 | 12 | ||
13 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c | 13 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c |
14 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/arm/musicpal.c | 15 | --- a/hw/arm/musicpal.c |
16 | +++ b/hw/arm/musicpal.c | 16 | +++ b/hw/arm/musicpal.c |
17 | @@ -XXX,XX +XXX,XX @@ static void mv88w8618_timer_tick(void *opaque) | 17 | @@ -XXX,XX +XXX,XX @@ static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col) |
18 | static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, | ||
19 | uint32_t freq) | ||
20 | { | ||
21 | - QEMUBH *bh; | ||
22 | - | ||
23 | sysbus_init_irq(dev, &s->irq); | ||
24 | s->freq = freq; | ||
25 | |||
26 | - bh = qemu_bh_new(mv88w8618_timer_tick, s); | ||
27 | - s->ptimer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
28 | + s->ptimer = ptimer_init(mv88w8618_timer_tick, s, PTIMER_POLICY_DEFAULT); | ||
29 | } | ||
30 | |||
31 | static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset, | ||
32 | @@ -XXX,XX +XXX,XX @@ static void mv88w8618_pit_write(void *opaque, hwaddr offset, | ||
33 | case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH: | ||
34 | t = &s->timer[offset >> 2]; | ||
35 | t->limit = value; | ||
36 | + ptimer_transaction_begin(t->ptimer); | ||
37 | if (t->limit > 0) { | ||
38 | ptimer_set_limit(t->ptimer, t->limit, 1); | ||
39 | } else { | ||
40 | ptimer_stop(t->ptimer); | ||
41 | } | ||
42 | + ptimer_transaction_commit(t->ptimer); | ||
43 | break; | ||
44 | |||
45 | case MP_PIT_CONTROL: | ||
46 | for (i = 0; i < 4; i++) { | ||
47 | t = &s->timer[i]; | ||
48 | + ptimer_transaction_begin(t->ptimer); | ||
49 | if (value & 0xf && t->limit > 0) { | ||
50 | ptimer_set_limit(t->ptimer, t->limit, 0); | ||
51 | ptimer_set_freq(t->ptimer, t->freq); | ||
52 | @@ -XXX,XX +XXX,XX @@ static void mv88w8618_pit_write(void *opaque, hwaddr offset, | ||
53 | } else { | ||
54 | ptimer_stop(t->ptimer); | ||
55 | } | ||
56 | + ptimer_transaction_commit(t->ptimer); | ||
57 | value >>= 4; | ||
58 | } | ||
59 | break; | ||
60 | @@ -XXX,XX +XXX,XX @@ static void mv88w8618_pit_reset(DeviceState *d) | ||
61 | int i; | ||
62 | |||
63 | for (i = 0; i < 4; i++) { | ||
64 | - ptimer_stop(s->timer[i].ptimer); | ||
65 | - s->timer[i].limit = 0; | ||
66 | + mv88w8618_timer_state *t = &s->timer[i]; | ||
67 | + ptimer_transaction_begin(t->ptimer); | ||
68 | + ptimer_stop(t->ptimer); | ||
69 | + ptimer_transaction_commit(t->ptimer); | ||
70 | + t->limit = 0; | ||
71 | } | 18 | } |
72 | } | 19 | } |
73 | 20 | ||
21 | -#define SET_LCD_PIXEL(depth, type) \ | ||
22 | -static inline void glue(set_lcd_pixel, depth) \ | ||
23 | - (musicpal_lcd_state *s, int x, int y, type col) \ | ||
24 | -{ \ | ||
25 | - int dx, dy; \ | ||
26 | - DisplaySurface *surface = qemu_console_surface(s->con); \ | ||
27 | - type *pixel = &((type *) surface_data(surface))[(y * 128 * 3 + x) * 3]; \ | ||
28 | -\ | ||
29 | - for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \ | ||
30 | - for (dx = 0; dx < 3; dx++, pixel++) \ | ||
31 | - *pixel = col; \ | ||
32 | +static inline void set_lcd_pixel32(musicpal_lcd_state *s, | ||
33 | + int x, int y, uint32_t col) | ||
34 | +{ | ||
35 | + int dx, dy; | ||
36 | + DisplaySurface *surface = qemu_console_surface(s->con); | ||
37 | + uint32_t *pixel = | ||
38 | + &((uint32_t *) surface_data(surface))[(y * 128 * 3 + x) * 3]; | ||
39 | + | ||
40 | + for (dy = 0; dy < 3; dy++, pixel += 127 * 3) { | ||
41 | + for (dx = 0; dx < 3; dx++, pixel++) { | ||
42 | + *pixel = col; | ||
43 | + } | ||
44 | + } | ||
45 | } | ||
46 | -SET_LCD_PIXEL(8, uint8_t) | ||
47 | -SET_LCD_PIXEL(16, uint16_t) | ||
48 | -SET_LCD_PIXEL(32, uint32_t) | ||
49 | |||
50 | static void lcd_refresh(void *opaque) | ||
51 | { | ||
52 | musicpal_lcd_state *s = opaque; | ||
53 | - DisplaySurface *surface = qemu_console_surface(s->con); | ||
54 | int x, y, col; | ||
55 | |||
56 | - switch (surface_bits_per_pixel(surface)) { | ||
57 | - case 0: | ||
58 | - return; | ||
59 | -#define LCD_REFRESH(depth, func) \ | ||
60 | - case depth: \ | ||
61 | - col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \ | ||
62 | - scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \ | ||
63 | - scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \ | ||
64 | - for (x = 0; x < 128; x++) { \ | ||
65 | - for (y = 0; y < 64; y++) { \ | ||
66 | - if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \ | ||
67 | - glue(set_lcd_pixel, depth)(s, x, y, col); \ | ||
68 | - } else { \ | ||
69 | - glue(set_lcd_pixel, depth)(s, x, y, 0); \ | ||
70 | - } \ | ||
71 | - } \ | ||
72 | - } \ | ||
73 | - break; | ||
74 | - LCD_REFRESH(8, rgb_to_pixel8) | ||
75 | - LCD_REFRESH(16, rgb_to_pixel16) | ||
76 | - LCD_REFRESH(32, (is_surface_bgr(surface) ? | ||
77 | - rgb_to_pixel32bgr : rgb_to_pixel32)) | ||
78 | - default: | ||
79 | - hw_error("unsupported colour depth %i\n", | ||
80 | - surface_bits_per_pixel(surface)); | ||
81 | + col = rgb_to_pixel32(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), | ||
82 | + scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), | ||
83 | + scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); | ||
84 | + for (x = 0; x < 128; x++) { | ||
85 | + for (y = 0; y < 64; y++) { | ||
86 | + if (s->video_ram[x + (y / 8) * 128] & (1 << (y % 8))) { | ||
87 | + set_lcd_pixel32(s, x, y, col); | ||
88 | + } else { | ||
89 | + set_lcd_pixel32(s, x, y, 0); | ||
90 | + } | ||
91 | + } | ||
92 | } | ||
93 | |||
94 | dpy_gfx_update(s->con, 0, 0, 128*3, 64*3); | ||
74 | -- | 95 | -- |
75 | 2.20.1 | 96 | 2.20.1 |
76 | 97 | ||
77 | 98 | diff view generated by jsdifflib |
1 | Switch the cmsdk-apb-watchdog code away from bottom-half based | 1 | For a long time now the UI layer has guaranteed that the console |
---|---|---|---|
2 | ptimers to the new transaction-based ptimer API. This just requires | 2 | surface is always 32 bits per pixel RGB. Remove the legacy dead |
3 | adding begin/commit calls around the various places that modify the | 3 | code from the tc6393xb display device which was handling the |
4 | ptimer state, and using the new ptimer_init() function to create the | 4 | possibility that the console surface was some other format. |
5 | timer. | ||
6 | 5 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20191008171740.9679-21-peter.maydell@linaro.org | 8 | Message-id: 20210215103215.4944-3-peter.maydell@linaro.org |
10 | --- | 9 | --- |
11 | hw/watchdog/cmsdk-apb-watchdog.c | 13 +++++++++---- | 10 | include/ui/console.h | 10 ---------- |
12 | 1 file changed, 9 insertions(+), 4 deletions(-) | 11 | hw/display/tc6393xb.c | 33 +-------------------------------- |
12 | 2 files changed, 1 insertion(+), 42 deletions(-) | ||
13 | 13 | ||
14 | diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c | 14 | diff --git a/include/ui/console.h b/include/ui/console.h |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/watchdog/cmsdk-apb-watchdog.c | 16 | --- a/include/ui/console.h |
17 | +++ b/hw/watchdog/cmsdk-apb-watchdog.c | 17 | +++ b/include/ui/console.h |
18 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ PixelFormat qemu_default_pixelformat(int bpp); |
19 | #include "qemu/log.h" | 19 | DisplaySurface *qemu_create_displaysurface(int width, int height); |
20 | #include "trace.h" | 20 | void qemu_free_displaysurface(DisplaySurface *surface); |
21 | #include "qapi/error.h" | 21 | |
22 | -#include "qemu/main-loop.h" | 22 | -static inline int is_surface_bgr(DisplaySurface *surface) |
23 | #include "qemu/module.h" | 23 | -{ |
24 | #include "sysemu/watchdog.h" | 24 | - if (PIXMAN_FORMAT_BPP(surface->format) == 32 && |
25 | #include "hw/sysbus.h" | 25 | - PIXMAN_FORMAT_TYPE(surface->format) == PIXMAN_TYPE_ABGR) { |
26 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset, | 26 | - return 1; |
27 | * Reset the load value and the current count, and make sure | 27 | - } else { |
28 | * we're counting. | 28 | - return 0; |
29 | */ | 29 | - } |
30 | + ptimer_transaction_begin(s->timer); | 30 | -} |
31 | ptimer_set_limit(s->timer, value, 1); | 31 | - |
32 | ptimer_run(s->timer, 0); | 32 | static inline int is_buffer_shared(DisplaySurface *surface) |
33 | + ptimer_transaction_commit(s->timer); | 33 | { |
34 | break; | 34 | return !(surface->flags & QEMU_ALLOCATED_FLAG); |
35 | case A_WDOGCONTROL: | 35 | diff --git a/hw/display/tc6393xb.c b/hw/display/tc6393xb.c |
36 | if (s->is_luminary && 0 != (R_WDOGCONTROL_INTEN_MASK & s->control)) { | 36 | index XXXXXXX..XXXXXXX 100644 |
37 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset, | 37 | --- a/hw/display/tc6393xb.c |
38 | break; | 38 | +++ b/hw/display/tc6393xb.c |
39 | case A_WDOGINTCLR: | 39 | @@ -XXX,XX +XXX,XX @@ static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) |
40 | s->intstatus = 0; | 40 | (uint32_t) addr, value & 0xff); |
41 | + ptimer_transaction_begin(s->timer); | ||
42 | ptimer_set_count(s->timer, ptimer_get_limit(s->timer)); | ||
43 | + ptimer_transaction_commit(s->timer); | ||
44 | cmsdk_apb_watchdog_update(s); | ||
45 | break; | ||
46 | case A_WDOGLOCK: | ||
47 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_reset(DeviceState *dev) | ||
48 | s->itop = 0; | ||
49 | s->resetstatus = 0; | ||
50 | /* Set the limit and the count */ | ||
51 | + ptimer_transaction_begin(s->timer); | ||
52 | ptimer_set_limit(s->timer, 0xffffffff, 1); | ||
53 | ptimer_run(s->timer, 0); | ||
54 | + ptimer_transaction_commit(s->timer); | ||
55 | } | 41 | } |
56 | 42 | ||
57 | static void cmsdk_apb_watchdog_init(Object *obj) | 43 | -#define BITS 8 |
58 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_init(Object *obj) | 44 | -#include "tc6393xb_template.h" |
59 | static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) | 45 | -#define BITS 15 |
46 | -#include "tc6393xb_template.h" | ||
47 | -#define BITS 16 | ||
48 | -#include "tc6393xb_template.h" | ||
49 | -#define BITS 24 | ||
50 | -#include "tc6393xb_template.h" | ||
51 | #define BITS 32 | ||
52 | #include "tc6393xb_template.h" | ||
53 | |||
54 | static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update) | ||
60 | { | 55 | { |
61 | CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev); | 56 | - DisplaySurface *surface = qemu_console_surface(s->con); |
62 | - QEMUBH *bh; | 57 | - |
63 | 58 | - switch (surface_bits_per_pixel(surface)) { | |
64 | if (s->wdogclk_frq == 0) { | 59 | - case 8: |
65 | error_setg(errp, | 60 | - tc6393xb_draw_graphic8(s); |
66 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) | 61 | - break; |
67 | return; | 62 | - case 15: |
68 | } | 63 | - tc6393xb_draw_graphic15(s); |
69 | 64 | - break; | |
70 | - bh = qemu_bh_new(cmsdk_apb_watchdog_tick, s); | 65 | - case 16: |
71 | - s->timer = ptimer_init_with_bh(bh, | 66 | - tc6393xb_draw_graphic16(s); |
72 | + s->timer = ptimer_init(cmsdk_apb_watchdog_tick, s, | 67 | - break; |
73 | PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | | 68 | - case 24: |
74 | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | | 69 | - tc6393xb_draw_graphic24(s); |
75 | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | | 70 | - break; |
76 | PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | 71 | - case 32: |
77 | 72 | - tc6393xb_draw_graphic32(s); | |
78 | + ptimer_transaction_begin(s->timer); | 73 | - break; |
79 | ptimer_set_freq(s->timer, s->wdogclk_frq); | 74 | - default: |
80 | + ptimer_transaction_commit(s->timer); | 75 | - printf("tc6393xb: unknown depth %d\n", |
76 | - surface_bits_per_pixel(surface)); | ||
77 | - return; | ||
78 | - } | ||
79 | - | ||
80 | + tc6393xb_draw_graphic32(s); | ||
81 | dpy_gfx_update_full(s->con); | ||
81 | } | 82 | } |
82 | 83 | ||
83 | static const VMStateDescription cmsdk_apb_watchdog_vmstate = { | ||
84 | -- | 84 | -- |
85 | 2.20.1 | 85 | 2.20.1 |
86 | 86 | ||
87 | 87 | diff view generated by jsdifflib |
1 | Switch the exynos MCT LFRC timers over to the ptimer transaction API. | 1 | Now the template header is included only for BITS==32, expand |
---|---|---|---|
2 | out all the macros that depended on the BITS setting. | ||
2 | 3 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20191008171740.9679-13-peter.maydell@linaro.org | 6 | Message-id: 20210215103215.4944-4-peter.maydell@linaro.org |
6 | --- | 7 | --- |
7 | hw/timer/exynos4210_mct.c | 27 +++++++++++++++++++++++---- | 8 | hw/display/tc6393xb_template.h | 35 ++++------------------------------ |
8 | 1 file changed, 23 insertions(+), 4 deletions(-) | 9 | 1 file changed, 4 insertions(+), 31 deletions(-) |
9 | 10 | ||
10 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | 11 | diff --git a/hw/display/tc6393xb_template.h b/hw/display/tc6393xb_template.h |
11 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/hw/timer/exynos4210_mct.c | 13 | --- a/hw/display/tc6393xb_template.h |
13 | +++ b/hw/timer/exynos4210_mct.c | 14 | +++ b/hw/display/tc6393xb_template.h |
14 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_lfrc_get_count(Exynos4210MCTLT *s) | 15 | @@ -XXX,XX +XXX,XX @@ |
15 | 16 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
16 | /* | ||
17 | * Set counter of FRC local timer. | ||
18 | + * Must be called from within exynos4210_lfrc_tx_begin/commit block. | ||
19 | */ | 17 | */ |
20 | static void exynos4210_lfrc_update_count(Exynos4210MCTLT *s) | 18 | |
19 | -#if BITS == 8 | ||
20 | -# define SET_PIXEL(addr, color) (*(uint8_t *)addr = color) | ||
21 | -#elif BITS == 15 || BITS == 16 | ||
22 | -# define SET_PIXEL(addr, color) (*(uint16_t *)addr = color) | ||
23 | -#elif BITS == 24 | ||
24 | -# define SET_PIXEL(addr, color) \ | ||
25 | - do { \ | ||
26 | - addr[0] = color; \ | ||
27 | - addr[1] = (color) >> 8; \ | ||
28 | - addr[2] = (color) >> 16; \ | ||
29 | - } while (0) | ||
30 | -#elif BITS == 32 | ||
31 | -# define SET_PIXEL(addr, color) (*(uint32_t *)addr = color) | ||
32 | -#else | ||
33 | -# error unknown bit depth | ||
34 | -#endif | ||
35 | - | ||
36 | - | ||
37 | -static void glue(tc6393xb_draw_graphic, BITS)(TC6393xbState *s) | ||
38 | +static void tc6393xb_draw_graphic32(TC6393xbState *s) | ||
21 | { | 39 | { |
22 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_lfrc_update_count(Exynos4210MCTLT *s) | 40 | DisplaySurface *surface = qemu_console_surface(s->con); |
23 | 41 | int i; | |
24 | /* | 42 | @@ -XXX,XX +XXX,XX @@ static void glue(tc6393xb_draw_graphic, BITS)(TC6393xbState *s) |
25 | * Start local FRC timer | 43 | data_buffer = s->vram_ptr; |
26 | + * Must be called from within exynos4210_lfrc_tx_begin/commit block. | 44 | data_display = surface_data(surface); |
27 | */ | 45 | for(i = 0; i < s->scr_height; i++) { |
28 | static void exynos4210_lfrc_start(Exynos4210MCTLT *s) | 46 | -#if (BITS == 16) |
29 | { | 47 | - memcpy(data_display, data_buffer, s->scr_width * 2); |
30 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_lfrc_start(Exynos4210MCTLT *s) | 48 | - data_buffer += s->scr_width; |
31 | 49 | - data_display += surface_stride(surface); | |
32 | /* | 50 | -#else |
33 | * Stop local FRC timer | 51 | int j; |
34 | + * Must be called from within exynos4210_lfrc_tx_begin/commit block. | 52 | - for (j = 0; j < s->scr_width; j++, data_display += BITS / 8, data_buffer++) { |
35 | */ | 53 | + for (j = 0; j < s->scr_width; j++, data_display += 4, data_buffer++) { |
36 | static void exynos4210_lfrc_stop(Exynos4210MCTLT *s) | 54 | uint16_t color = *data_buffer; |
37 | { | 55 | - uint32_t dest_color = glue(rgb_to_pixel, BITS)( |
38 | ptimer_stop(s->ptimer_frc); | 56 | + uint32_t dest_color = rgb_to_pixel32( |
39 | } | 57 | ((color & 0xf800) * 0x108) >> 11, |
40 | 58 | ((color & 0x7e0) * 0x41) >> 9, | |
41 | +/* Start ptimer transaction for local FRC timer */ | 59 | ((color & 0x1f) * 0x21) >> 2 |
42 | +static void exynos4210_lfrc_tx_begin(Exynos4210MCTLT *s) | 60 | ); |
43 | +{ | 61 | - SET_PIXEL(data_display, dest_color); |
44 | + ptimer_transaction_begin(s->ptimer_frc); | 62 | + *(uint32_t *)data_display = dest_color; |
45 | +} | 63 | } |
46 | + | 64 | -#endif |
47 | +/* Commit ptimer transaction for local FRC timer */ | ||
48 | +static void exynos4210_lfrc_tx_commit(Exynos4210MCTLT *s) | ||
49 | +{ | ||
50 | + ptimer_transaction_commit(s->ptimer_frc); | ||
51 | +} | ||
52 | + | ||
53 | /* | ||
54 | * Local timer free running counter tick handler | ||
55 | */ | ||
56 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s) | ||
57 | |||
58 | /* local timer */ | ||
59 | ptimer_set_freq(s->l_timer[0].tick_timer.ptimer_tick, s->freq); | ||
60 | - ptimer_set_freq(s->l_timer[0].ptimer_frc, s->freq); | ||
61 | + tx_ptimer_set_freq(s->l_timer[0].ptimer_frc, s->freq); | ||
62 | ptimer_set_freq(s->l_timer[1].tick_timer.ptimer_tick, s->freq); | ||
63 | - ptimer_set_freq(s->l_timer[1].ptimer_frc, s->freq); | ||
64 | + tx_ptimer_set_freq(s->l_timer[1].ptimer_frc, s->freq); | ||
65 | } | 65 | } |
66 | } | 66 | } |
67 | 67 | - | |
68 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_reset(DeviceState *d) | 68 | -#undef BITS |
69 | s->l_timer[i].tick_timer.count = 0; | 69 | -#undef SET_PIXEL |
70 | s->l_timer[i].tick_timer.distance = 0; | ||
71 | s->l_timer[i].tick_timer.progress = 0; | ||
72 | + exynos4210_lfrc_tx_begin(&s->l_timer[i]); | ||
73 | ptimer_stop(s->l_timer[i].ptimer_frc); | ||
74 | + exynos4210_lfrc_tx_commit(&s->l_timer[i]); | ||
75 | |||
76 | exynos4210_ltick_timer_init(&s->l_timer[i].tick_timer); | ||
77 | } | ||
78 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
79 | } | ||
80 | |||
81 | /* Start or Stop local FRC if TCON changed */ | ||
82 | + exynos4210_lfrc_tx_begin(&s->l_timer[lt_i]); | ||
83 | if ((value & L_TCON_FRC_START) > | ||
84 | (s->l_timer[lt_i].reg.tcon & L_TCON_FRC_START)) { | ||
85 | DPRINTF("local timer[%d] start frc\n", lt_i); | ||
86 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
87 | DPRINTF("local timer[%d] stop frc\n", lt_i); | ||
88 | exynos4210_lfrc_stop(&s->l_timer[lt_i]); | ||
89 | } | ||
90 | + exynos4210_lfrc_tx_commit(&s->l_timer[lt_i]); | ||
91 | break; | ||
92 | |||
93 | case L0_TCNTB: case L1_TCNTB: | ||
94 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_init(Object *obj) | ||
95 | /* Local timers */ | ||
96 | for (i = 0; i < 2; i++) { | ||
97 | bh[0] = qemu_bh_new(exynos4210_ltick_event, &s->l_timer[i]); | ||
98 | - bh[1] = qemu_bh_new(exynos4210_lfrc_event, &s->l_timer[i]); | ||
99 | s->l_timer[i].tick_timer.ptimer_tick = | ||
100 | ptimer_init_with_bh(bh[0], PTIMER_POLICY_DEFAULT); | ||
101 | s->l_timer[i].ptimer_frc = | ||
102 | - ptimer_init_with_bh(bh[1], PTIMER_POLICY_DEFAULT); | ||
103 | + ptimer_init(exynos4210_lfrc_event, &s->l_timer[i], | ||
104 | + PTIMER_POLICY_DEFAULT); | ||
105 | s->l_timer[i].id = i; | ||
106 | } | ||
107 | |||
108 | -- | 70 | -- |
109 | 2.20.1 | 71 | 2.20.1 |
110 | 72 | ||
111 | 73 | diff view generated by jsdifflib |
1 | Switch the allwinner-a10-pit code away from bottom-half based ptimers to | 1 | The function tc6393xb_draw_graphic32() is called in exactly one place, |
---|---|---|---|
2 | the new transaction-based ptimer API. This just requires adding | 2 | so just inline the function body at its callsite. This allows us to |
3 | begin/commit calls around the various places that modify the ptimer | 3 | drop the template header entirely. |
4 | state, and using the new ptimer_init() function to create the timer. | 4 | |
5 | The code move includes a single added space after 'for' to fix | ||
6 | the coding style. | ||
5 | 7 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20191008171740.9679-7-peter.maydell@linaro.org | 10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
11 | Message-id: 20210215103215.4944-5-peter.maydell@linaro.org | ||
9 | --- | 12 | --- |
10 | hw/timer/allwinner-a10-pit.c | 12 ++++++++---- | 13 | hw/display/tc6393xb_template.h | 45 ---------------------------------- |
11 | 1 file changed, 8 insertions(+), 4 deletions(-) | 14 | hw/display/tc6393xb.c | 23 ++++++++++++++--- |
15 | 2 files changed, 19 insertions(+), 49 deletions(-) | ||
16 | delete mode 100644 hw/display/tc6393xb_template.h | ||
12 | 17 | ||
13 | diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c | 18 | diff --git a/hw/display/tc6393xb_template.h b/hw/display/tc6393xb_template.h |
19 | deleted file mode 100644 | ||
20 | index XXXXXXX..XXXXXXX | ||
21 | --- a/hw/display/tc6393xb_template.h | ||
22 | +++ /dev/null | ||
23 | @@ -XXX,XX +XXX,XX @@ | ||
24 | -/* | ||
25 | - * Toshiba TC6393XB I/O Controller. | ||
26 | - * Found in Sharp Zaurus SL-6000 (tosa) or some | ||
27 | - * Toshiba e-Series PDAs. | ||
28 | - * | ||
29 | - * FB support code. Based on G364 fb emulator | ||
30 | - * | ||
31 | - * Copyright (c) 2007 Hervé Poussineau | ||
32 | - * | ||
33 | - * This program is free software; you can redistribute it and/or | ||
34 | - * modify it under the terms of the GNU General Public License as | ||
35 | - * published by the Free Software Foundation; either version 2 of | ||
36 | - * the License, or (at your option) any later version. | ||
37 | - * | ||
38 | - * This program is distributed in the hope that it will be useful, | ||
39 | - * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
40 | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
41 | - * GNU General Public License for more details. | ||
42 | - * | ||
43 | - * You should have received a copy of the GNU General Public License along | ||
44 | - * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
45 | - */ | ||
46 | - | ||
47 | -static void tc6393xb_draw_graphic32(TC6393xbState *s) | ||
48 | -{ | ||
49 | - DisplaySurface *surface = qemu_console_surface(s->con); | ||
50 | - int i; | ||
51 | - uint16_t *data_buffer; | ||
52 | - uint8_t *data_display; | ||
53 | - | ||
54 | - data_buffer = s->vram_ptr; | ||
55 | - data_display = surface_data(surface); | ||
56 | - for(i = 0; i < s->scr_height; i++) { | ||
57 | - int j; | ||
58 | - for (j = 0; j < s->scr_width; j++, data_display += 4, data_buffer++) { | ||
59 | - uint16_t color = *data_buffer; | ||
60 | - uint32_t dest_color = rgb_to_pixel32( | ||
61 | - ((color & 0xf800) * 0x108) >> 11, | ||
62 | - ((color & 0x7e0) * 0x41) >> 9, | ||
63 | - ((color & 0x1f) * 0x21) >> 2 | ||
64 | - ); | ||
65 | - *(uint32_t *)data_display = dest_color; | ||
66 | - } | ||
67 | - } | ||
68 | -} | ||
69 | diff --git a/hw/display/tc6393xb.c b/hw/display/tc6393xb.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | 70 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/timer/allwinner-a10-pit.c | 71 | --- a/hw/display/tc6393xb.c |
16 | +++ b/hw/timer/allwinner-a10-pit.c | 72 | +++ b/hw/display/tc6393xb.c |
17 | @@ -XXX,XX +XXX,XX @@ | 73 | @@ -XXX,XX +XXX,XX @@ static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) |
18 | #include "hw/timer/allwinner-a10-pit.h" | 74 | (uint32_t) addr, value & 0xff); |
19 | #include "migration/vmstate.h" | ||
20 | #include "qemu/log.h" | ||
21 | -#include "qemu/main-loop.h" | ||
22 | #include "qemu/module.h" | ||
23 | |||
24 | static void a10_pit_update_irq(AwA10PITState *s) | ||
25 | @@ -XXX,XX +XXX,XX @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) | ||
26 | return 0; | ||
27 | } | 75 | } |
28 | 76 | ||
29 | +/* Must be called inside a ptimer transaction block for s->timer[index] */ | 77 | -#define BITS 32 |
30 | static void a10_pit_set_freq(AwA10PITState *s, int index) | 78 | -#include "tc6393xb_template.h" |
79 | - | ||
80 | static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update) | ||
31 | { | 81 | { |
32 | uint32_t prescaler, source, source_freq; | 82 | - tc6393xb_draw_graphic32(s); |
33 | @@ -XXX,XX +XXX,XX @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, | 83 | + DisplaySurface *surface = qemu_console_surface(s->con); |
34 | switch (offset & 0x0f) { | 84 | + int i; |
35 | case AW_A10_PIT_TIMER_CONTROL: | 85 | + uint16_t *data_buffer; |
36 | s->control[index] = value; | 86 | + uint8_t *data_display; |
37 | + ptimer_transaction_begin(s->timer[index]); | 87 | + |
38 | a10_pit_set_freq(s, index); | 88 | + data_buffer = s->vram_ptr; |
39 | if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) { | 89 | + data_display = surface_data(surface); |
40 | ptimer_set_count(s->timer[index], s->interval[index]); | 90 | + for (i = 0; i < s->scr_height; i++) { |
41 | @@ -XXX,XX +XXX,XX @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, | 91 | + int j; |
42 | } else { | 92 | + for (j = 0; j < s->scr_width; j++, data_display += 4, data_buffer++) { |
43 | ptimer_stop(s->timer[index]); | 93 | + uint16_t color = *data_buffer; |
44 | } | 94 | + uint32_t dest_color = rgb_to_pixel32( |
45 | + ptimer_transaction_commit(s->timer[index]); | 95 | + ((color & 0xf800) * 0x108) >> 11, |
46 | break; | 96 | + ((color & 0x7e0) * 0x41) >> 9, |
47 | case AW_A10_PIT_TIMER_INTERVAL: | 97 | + ((color & 0x1f) * 0x21) >> 2 |
48 | s->interval[index] = value; | 98 | + ); |
49 | + ptimer_transaction_begin(s->timer[index]); | 99 | + *(uint32_t *)data_display = dest_color; |
50 | ptimer_set_limit(s->timer[index], s->interval[index], 1); | 100 | + } |
51 | + ptimer_transaction_commit(s->timer[index]); | 101 | + } |
52 | break; | 102 | dpy_gfx_update_full(s->con); |
53 | case AW_A10_PIT_TIMER_COUNT: | ||
54 | s->count[index] = value; | ||
55 | @@ -XXX,XX +XXX,XX @@ static void a10_pit_reset(DeviceState *dev) | ||
56 | s->control[i] = AW_A10_PIT_DEFAULT_CLOCK; | ||
57 | s->interval[i] = 0; | ||
58 | s->count[i] = 0; | ||
59 | + ptimer_transaction_begin(s->timer[i]); | ||
60 | ptimer_stop(s->timer[i]); | ||
61 | a10_pit_set_freq(s, i); | ||
62 | + ptimer_transaction_commit(s->timer[i]); | ||
63 | } | ||
64 | s->watch_dog_mode = 0; | ||
65 | s->watch_dog_control = 0; | ||
66 | @@ -XXX,XX +XXX,XX @@ static void a10_pit_init(Object *obj) | ||
67 | { | ||
68 | AwA10PITState *s = AW_A10_PIT(obj); | ||
69 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
70 | - QEMUBH * bh[AW_A10_PIT_TIMER_NR]; | ||
71 | uint8_t i; | ||
72 | |||
73 | for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { | ||
74 | @@ -XXX,XX +XXX,XX @@ static void a10_pit_init(Object *obj) | ||
75 | |||
76 | tc->container = s; | ||
77 | tc->index = i; | ||
78 | - bh[i] = qemu_bh_new(a10_pit_timer_cb, tc); | ||
79 | - s->timer[i] = ptimer_init_with_bh(bh[i], PTIMER_POLICY_DEFAULT); | ||
80 | + s->timer[i] = ptimer_init(a10_pit_timer_cb, tc, PTIMER_POLICY_DEFAULT); | ||
81 | } | ||
82 | } | 103 | } |
83 | 104 | ||
84 | -- | 105 | -- |
85 | 2.20.1 | 106 | 2.20.1 |
86 | 107 | ||
87 | 108 | diff view generated by jsdifflib |
1 | We want to switch the exynos MCT code away from bottom-half based ptimers to | 1 | The omap_lcdc template header is already only included once, for |
---|---|---|---|
2 | the new transaction-based ptimer API. The MCT is complicated | 2 | DEPTH==32, but it still has all the macro-driven parameterization |
3 | and uses multiple different ptimers, so it's clearer to switch | 3 | for other depths. Expand out all the macros in the header. |
4 | it a piece at a time. Here we change over only the GFRC. | ||
5 | 4 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20191008171740.9679-12-peter.maydell@linaro.org | 7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
8 | Message-id: 20210215103215.4944-6-peter.maydell@linaro.org | ||
9 | --- | 9 | --- |
10 | hw/timer/exynos4210_mct.c | 48 ++++++++++++++++++++++++++++++++++++--- | 10 | hw/display/omap_lcd_template.h | 67 ++++++++++++++-------------------- |
11 | 1 file changed, 45 insertions(+), 3 deletions(-) | 11 | 1 file changed, 28 insertions(+), 39 deletions(-) |
12 | 12 | ||
13 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | 13 | diff --git a/hw/display/omap_lcd_template.h b/hw/display/omap_lcd_template.h |
14 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/timer/exynos4210_mct.c | 15 | --- a/hw/display/omap_lcd_template.h |
16 | +++ b/hw/timer/exynos4210_mct.c | 16 | +++ b/hw/display/omap_lcd_template.h |
17 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s); | 17 | @@ -XXX,XX +XXX,XX @@ |
18 | 18 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
19 | */ | ||
20 | |||
21 | -#if DEPTH == 32 | ||
22 | -# define BPP 4 | ||
23 | -# define PIXEL_TYPE uint32_t | ||
24 | -#else | ||
25 | -# error unsupport depth | ||
26 | -#endif | ||
27 | - | ||
19 | /* | 28 | /* |
20 | * Set counter of FRC global timer. | 29 | * 2-bit colour |
21 | + * Must be called within exynos4210_gfrc_tx_begin/commit block. | ||
22 | */ | 30 | */ |
23 | static void exynos4210_gfrc_set_count(Exynos4210MCTGT *s, uint64_t count) | 31 | -static void glue(draw_line2_, DEPTH)(void *opaque, |
32 | - uint8_t *d, const uint8_t *s, int width, int deststep) | ||
33 | +static void draw_line2_32(void *opaque, uint8_t *d, const uint8_t *s, | ||
34 | + int width, int deststep) | ||
24 | { | 35 | { |
25 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_gfrc_get_count(Exynos4210MCTGT *s) | 36 | uint16_t *pal = opaque; |
26 | 37 | uint8_t v, r, g, b; | |
38 | @@ -XXX,XX +XXX,XX @@ static void glue(draw_line2_, DEPTH)(void *opaque, | ||
39 | r = (pal[v & 3] >> 4) & 0xf0; | ||
40 | g = pal[v & 3] & 0xf0; | ||
41 | b = (pal[v & 3] << 4) & 0xf0; | ||
42 | - ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b); | ||
43 | - d += BPP; | ||
44 | + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
45 | + d += 4; | ||
46 | v >>= 2; | ||
47 | r = (pal[v & 3] >> 4) & 0xf0; | ||
48 | g = pal[v & 3] & 0xf0; | ||
49 | b = (pal[v & 3] << 4) & 0xf0; | ||
50 | - ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b); | ||
51 | - d += BPP; | ||
52 | + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
53 | + d += 4; | ||
54 | v >>= 2; | ||
55 | r = (pal[v & 3] >> 4) & 0xf0; | ||
56 | g = pal[v & 3] & 0xf0; | ||
57 | b = (pal[v & 3] << 4) & 0xf0; | ||
58 | - ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b); | ||
59 | - d += BPP; | ||
60 | + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
61 | + d += 4; | ||
62 | v >>= 2; | ||
63 | r = (pal[v & 3] >> 4) & 0xf0; | ||
64 | g = pal[v & 3] & 0xf0; | ||
65 | b = (pal[v & 3] << 4) & 0xf0; | ||
66 | - ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b); | ||
67 | - d += BPP; | ||
68 | + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
69 | + d += 4; | ||
70 | s ++; | ||
71 | width -= 4; | ||
72 | } while (width > 0); | ||
73 | @@ -XXX,XX +XXX,XX @@ static void glue(draw_line2_, DEPTH)(void *opaque, | ||
27 | /* | 74 | /* |
28 | * Stop global FRC timer | 75 | * 4-bit colour |
29 | + * Must be called within exynos4210_gfrc_tx_begin/commit block. | ||
30 | */ | 76 | */ |
31 | static void exynos4210_gfrc_stop(Exynos4210MCTGT *s) | 77 | -static void glue(draw_line4_, DEPTH)(void *opaque, |
78 | - uint8_t *d, const uint8_t *s, int width, int deststep) | ||
79 | +static void draw_line4_32(void *opaque, uint8_t *d, const uint8_t *s, | ||
80 | + int width, int deststep) | ||
32 | { | 81 | { |
33 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gfrc_stop(Exynos4210MCTGT *s) | 82 | uint16_t *pal = opaque; |
34 | 83 | uint8_t v, r, g, b; | |
84 | @@ -XXX,XX +XXX,XX @@ static void glue(draw_line4_, DEPTH)(void *opaque, | ||
85 | r = (pal[v & 0xf] >> 4) & 0xf0; | ||
86 | g = pal[v & 0xf] & 0xf0; | ||
87 | b = (pal[v & 0xf] << 4) & 0xf0; | ||
88 | - ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b); | ||
89 | - d += BPP; | ||
90 | + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
91 | + d += 4; | ||
92 | v >>= 4; | ||
93 | r = (pal[v & 0xf] >> 4) & 0xf0; | ||
94 | g = pal[v & 0xf] & 0xf0; | ||
95 | b = (pal[v & 0xf] << 4) & 0xf0; | ||
96 | - ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b); | ||
97 | - d += BPP; | ||
98 | + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
99 | + d += 4; | ||
100 | s ++; | ||
101 | width -= 2; | ||
102 | } while (width > 0); | ||
103 | @@ -XXX,XX +XXX,XX @@ static void glue(draw_line4_, DEPTH)(void *opaque, | ||
35 | /* | 104 | /* |
36 | * Start global FRC timer | 105 | * 8-bit colour |
37 | + * Must be called within exynos4210_gfrc_tx_begin/commit block. | ||
38 | */ | 106 | */ |
39 | static void exynos4210_gfrc_start(Exynos4210MCTGT *s) | 107 | -static void glue(draw_line8_, DEPTH)(void *opaque, |
108 | - uint8_t *d, const uint8_t *s, int width, int deststep) | ||
109 | +static void draw_line8_32(void *opaque, uint8_t *d, const uint8_t *s, | ||
110 | + int width, int deststep) | ||
40 | { | 111 | { |
41 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gfrc_start(Exynos4210MCTGT *s) | 112 | uint16_t *pal = opaque; |
42 | ptimer_run(s->ptimer_frc, 1); | 113 | uint8_t v, r, g, b; |
114 | @@ -XXX,XX +XXX,XX @@ static void glue(draw_line8_, DEPTH)(void *opaque, | ||
115 | r = (pal[v] >> 4) & 0xf0; | ||
116 | g = pal[v] & 0xf0; | ||
117 | b = (pal[v] << 4) & 0xf0; | ||
118 | - ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b); | ||
119 | + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
120 | s ++; | ||
121 | - d += BPP; | ||
122 | + d += 4; | ||
123 | } while (-- width != 0); | ||
43 | } | 124 | } |
44 | 125 | ||
45 | +/* | ||
46 | + * Start ptimer transaction for global FRC timer; this is just for | ||
47 | + * consistency with the way we wrap operations like stop and run. | ||
48 | + */ | ||
49 | +static void exynos4210_gfrc_tx_begin(Exynos4210MCTGT *s) | ||
50 | +{ | ||
51 | + ptimer_transaction_begin(s->ptimer_frc); | ||
52 | +} | ||
53 | + | ||
54 | +/* Commit ptimer transaction for global FRC timer. */ | ||
55 | +static void exynos4210_gfrc_tx_commit(Exynos4210MCTGT *s) | ||
56 | +{ | ||
57 | + ptimer_transaction_commit(s->ptimer_frc); | ||
58 | +} | ||
59 | + | ||
60 | /* | 126 | /* |
61 | * Find next nearest Comparator. If current Comparator value equals to other | 127 | * 12-bit colour |
62 | * Comparator value, skip them both | 128 | */ |
63 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_gcomp_get_distance(Exynos4210MCTState *s, int32_t id) | 129 | -static void glue(draw_line12_, DEPTH)(void *opaque, |
130 | - uint8_t *d, const uint8_t *s, int width, int deststep) | ||
131 | +static void draw_line12_32(void *opaque, uint8_t *d, const uint8_t *s, | ||
132 | + int width, int deststep) | ||
133 | { | ||
134 | uint16_t v; | ||
135 | uint8_t r, g, b; | ||
136 | @@ -XXX,XX +XXX,XX @@ static void glue(draw_line12_, DEPTH)(void *opaque, | ||
137 | r = (v >> 4) & 0xf0; | ||
138 | g = v & 0xf0; | ||
139 | b = (v << 4) & 0xf0; | ||
140 | - ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b); | ||
141 | + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
142 | s += 2; | ||
143 | - d += BPP; | ||
144 | + d += 4; | ||
145 | } while (-- width != 0); | ||
146 | } | ||
64 | 147 | ||
65 | /* | 148 | /* |
66 | * Restart global FRC timer | 149 | * 16-bit colour |
67 | + * Must be called within exynos4210_gfrc_tx_begin/commit block. | ||
68 | */ | 150 | */ |
69 | static void exynos4210_gfrc_restart(Exynos4210MCTState *s) | 151 | -static void glue(draw_line16_, DEPTH)(void *opaque, |
152 | - uint8_t *d, const uint8_t *s, int width, int deststep) | ||
153 | +static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s, | ||
154 | + int width, int deststep) | ||
70 | { | 155 | { |
71 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_ltick_event(void *opaque) | 156 | #if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN) |
72 | exynos4210_ltick_int_start(&s->tick_timer); | 157 | memcpy(d, s, width * 2); |
158 | @@ -XXX,XX +XXX,XX @@ static void glue(draw_line16_, DEPTH)(void *opaque, | ||
159 | r = (v >> 8) & 0xf8; | ||
160 | g = (v >> 3) & 0xfc; | ||
161 | b = (v << 3) & 0xf8; | ||
162 | - ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b); | ||
163 | + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
164 | s += 2; | ||
165 | - d += BPP; | ||
166 | + d += 4; | ||
167 | } while (-- width != 0); | ||
168 | #endif | ||
73 | } | 169 | } |
74 | 170 | - | |
75 | +static void tx_ptimer_set_freq(ptimer_state *s, uint32_t freq) | 171 | -#undef DEPTH |
76 | +{ | 172 | -#undef BPP |
77 | + /* | 173 | -#undef PIXEL_TYPE |
78 | + * callers of exynos4210_mct_update_freq() never do anything | ||
79 | + * else that needs to be in the same ptimer transaction, so | ||
80 | + * to avoid a lot of repetition we have a convenience function | ||
81 | + * for begin/set_freq/commit. | ||
82 | + */ | ||
83 | + ptimer_transaction_begin(s); | ||
84 | + ptimer_set_freq(s, freq); | ||
85 | + ptimer_transaction_commit(s); | ||
86 | +} | ||
87 | + | ||
88 | /* update timer frequency */ | ||
89 | static void exynos4210_mct_update_freq(Exynos4210MCTState *s) | ||
90 | { | ||
91 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s) | ||
92 | DPRINTF("freq=%dHz\n", s->freq); | ||
93 | |||
94 | /* global timer */ | ||
95 | - ptimer_set_freq(s->g_timer.ptimer_frc, s->freq); | ||
96 | + tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq); | ||
97 | |||
98 | /* local timer */ | ||
99 | ptimer_set_freq(s->l_timer[0].tick_timer.ptimer_tick, s->freq); | ||
100 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_reset(DeviceState *d) | ||
101 | |||
102 | /* global timer */ | ||
103 | memset(&s->g_timer.reg, 0, sizeof(s->g_timer.reg)); | ||
104 | + exynos4210_gfrc_tx_begin(&s->g_timer); | ||
105 | exynos4210_gfrc_stop(&s->g_timer); | ||
106 | + exynos4210_gfrc_tx_commit(&s->g_timer); | ||
107 | |||
108 | /* local timer */ | ||
109 | memset(s->l_timer[0].reg.cnt, 0, sizeof(s->l_timer[0].reg.cnt)); | ||
110 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
111 | } | ||
112 | |||
113 | s->g_timer.reg.cnt = new_frc; | ||
114 | + exynos4210_gfrc_tx_begin(&s->g_timer); | ||
115 | exynos4210_gfrc_restart(s); | ||
116 | + exynos4210_gfrc_tx_commit(&s->g_timer); | ||
117 | break; | ||
118 | |||
119 | case G_CNT_WSTAT: | ||
120 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
121 | s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index); | ||
122 | } | ||
123 | |||
124 | + exynos4210_gfrc_tx_begin(&s->g_timer); | ||
125 | exynos4210_gfrc_restart(s); | ||
126 | + exynos4210_gfrc_tx_commit(&s->g_timer); | ||
127 | break; | ||
128 | |||
129 | case G_TCON: | ||
130 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
131 | |||
132 | DPRINTF("global timer write to reg.g_tcon %llx\n", value); | ||
133 | |||
134 | + exynos4210_gfrc_tx_begin(&s->g_timer); | ||
135 | + | ||
136 | /* Start FRC if transition from disabled to enabled */ | ||
137 | if ((value & G_TCON_TIMER_ENABLE) > (old_val & | ||
138 | G_TCON_TIMER_ENABLE)) { | ||
139 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
140 | exynos4210_gfrc_restart(s); | ||
141 | } | ||
142 | } | ||
143 | + | ||
144 | + exynos4210_gfrc_tx_commit(&s->g_timer); | ||
145 | break; | ||
146 | |||
147 | case G_INT_CSTAT: | ||
148 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_init(Object *obj) | ||
149 | QEMUBH *bh[2]; | ||
150 | |||
151 | /* Global timer */ | ||
152 | - bh[0] = qemu_bh_new(exynos4210_gfrc_event, s); | ||
153 | - s->g_timer.ptimer_frc = ptimer_init_with_bh(bh[0], PTIMER_POLICY_DEFAULT); | ||
154 | + s->g_timer.ptimer_frc = ptimer_init(exynos4210_gfrc_event, s, | ||
155 | + PTIMER_POLICY_DEFAULT); | ||
156 | memset(&s->g_timer.reg, 0, sizeof(struct gregs)); | ||
157 | |||
158 | /* Local timers */ | ||
159 | -- | 174 | -- |
160 | 2.20.1 | 175 | 2.20.1 |
161 | 176 | ||
162 | 177 | diff view generated by jsdifflib |
1 | Switch the arm_timer.c code away from bottom-half based ptimers | 1 | The draw_line16_32() function in the omap_lcdc template header |
---|---|---|---|
2 | to the new transaction-based ptimer API. This just requires | 2 | includes an ifdef for the case where HOST_WORDS_BIGENDIAN matches |
3 | adding begin/commit calls around the various arms of | 3 | TARGET_WORDS_BIGENDIAN. This is trying to optimise for "source |
4 | arm_timer_write() that modify the ptimer state, and using the | 4 | bitmap and destination bitmap format match", but it is broken, |
5 | new ptimer_init() function to create the timer. | 5 | because in this function the formats don't match: the source is |
6 | 16-bit colour and the destination is 32-bit colour, so a memcpy() | ||
7 | will produce corrupted graphics output. Drop the bogus ifdef. | ||
6 | 8 | ||
7 | Fixes: https://bugs.launchpad.net/qemu/+bug/1777777 | 9 | This bug was introduced in commit ea644cf343129, when we dropped |
10 | support for DEPTH values other than 32 from the template header. | ||
11 | The old #if line was | ||
12 | #if DEPTH == 16 && defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN) | ||
13 | and this was mistakenly changed to | ||
14 | #if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN) | ||
15 | rather than deleting the #if as now having an always-false condition. | ||
16 | |||
17 | Fixes: ea644cf343129 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20191008171740.9679-5-peter.maydell@linaro.org | 20 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
21 | Message-id: 20210215103215.4944-7-peter.maydell@linaro.org | ||
11 | --- | 22 | --- |
12 | hw/timer/arm_timer.c | 16 +++++++++++----- | 23 | hw/display/omap_lcd_template.h | 4 ---- |
13 | 1 file changed, 11 insertions(+), 5 deletions(-) | 24 | 1 file changed, 4 deletions(-) |
14 | 25 | ||
15 | diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c | 26 | diff --git a/hw/display/omap_lcd_template.h b/hw/display/omap_lcd_template.h |
16 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/timer/arm_timer.c | 28 | --- a/hw/display/omap_lcd_template.h |
18 | +++ b/hw/timer/arm_timer.c | 29 | +++ b/hw/display/omap_lcd_template.h |
19 | @@ -XXX,XX +XXX,XX @@ | 30 | @@ -XXX,XX +XXX,XX @@ static void draw_line12_32(void *opaque, uint8_t *d, const uint8_t *s, |
20 | #include "hw/irq.h" | 31 | static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s, |
21 | #include "hw/ptimer.h" | 32 | int width, int deststep) |
22 | #include "hw/qdev-properties.h" | ||
23 | -#include "qemu/main-loop.h" | ||
24 | #include "qemu/module.h" | ||
25 | #include "qemu/log.h" | ||
26 | |||
27 | @@ -XXX,XX +XXX,XX @@ static uint32_t arm_timer_read(void *opaque, hwaddr offset) | ||
28 | } | ||
29 | } | ||
30 | |||
31 | -/* Reset the timer limit after settings have changed. */ | ||
32 | +/* | ||
33 | + * Reset the timer limit after settings have changed. | ||
34 | + * May only be called from inside a ptimer transaction block. | ||
35 | + */ | ||
36 | static void arm_timer_recalibrate(arm_timer_state *s, int reload) | ||
37 | { | 33 | { |
38 | uint32_t limit; | 34 | -#if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN) |
39 | @@ -XXX,XX +XXX,XX @@ static void arm_timer_write(void *opaque, hwaddr offset, | 35 | - memcpy(d, s, width * 2); |
40 | switch (offset >> 2) { | 36 | -#else |
41 | case 0: /* TimerLoad */ | 37 | uint16_t v; |
42 | s->limit = value; | 38 | uint8_t r, g, b; |
43 | + ptimer_transaction_begin(s->timer); | 39 | |
44 | arm_timer_recalibrate(s, 1); | 40 | @@ -XXX,XX +XXX,XX @@ static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s, |
45 | + ptimer_transaction_commit(s->timer); | 41 | s += 2; |
46 | break; | 42 | d += 4; |
47 | case 1: /* TimerValue */ | 43 | } while (-- width != 0); |
48 | /* ??? Linux seems to want to write to this readonly register. | 44 | -#endif |
49 | Ignore it. */ | ||
50 | break; | ||
51 | case 2: /* TimerControl */ | ||
52 | + ptimer_transaction_begin(s->timer); | ||
53 | if (s->control & TIMER_CTRL_ENABLE) { | ||
54 | /* Pause the timer if it is running. This may cause some | ||
55 | inaccuracy dure to rounding, but avoids a whole lot of other | ||
56 | @@ -XXX,XX +XXX,XX @@ static void arm_timer_write(void *opaque, hwaddr offset, | ||
57 | /* Restart the timer if still enabled. */ | ||
58 | ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0); | ||
59 | } | ||
60 | + ptimer_transaction_commit(s->timer); | ||
61 | break; | ||
62 | case 3: /* TimerIntClr */ | ||
63 | s->int_level = 0; | ||
64 | break; | ||
65 | case 6: /* TimerBGLoad */ | ||
66 | s->limit = value; | ||
67 | + ptimer_transaction_begin(s->timer); | ||
68 | arm_timer_recalibrate(s, 0); | ||
69 | + ptimer_transaction_commit(s->timer); | ||
70 | break; | ||
71 | default: | ||
72 | qemu_log_mask(LOG_GUEST_ERROR, | ||
73 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_arm_timer = { | ||
74 | static arm_timer_state *arm_timer_init(uint32_t freq) | ||
75 | { | ||
76 | arm_timer_state *s; | ||
77 | - QEMUBH *bh; | ||
78 | |||
79 | s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state)); | ||
80 | s->freq = freq; | ||
81 | s->control = TIMER_CTRL_IE; | ||
82 | |||
83 | - bh = qemu_bh_new(arm_timer_tick, s); | ||
84 | - s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
85 | + s->timer = ptimer_init(arm_timer_tick, s, PTIMER_POLICY_DEFAULT); | ||
86 | vmstate_register(NULL, -1, &vmstate_arm_timer, s); | ||
87 | return s; | ||
88 | } | 45 | } |
89 | -- | 46 | -- |
90 | 2.20.1 | 47 | 2.20.1 |
91 | 48 | ||
92 | 49 | diff view generated by jsdifflib |
1 | Provide the new transaction-based API. If a ptimer is created | 1 | Fix some minor coding style issues in the template header, |
---|---|---|---|
2 | using ptimer_init() rather than ptimer_init_with_bh(), then | 2 | so checkpatch doesn't complain when we move the code. |
3 | instead of providing a QEMUBH, it provides a pointer to the | ||
4 | callback function directly, and has opted into the transaction | ||
5 | API. All calls to functions which modify ptimer state: | ||
6 | - ptimer_set_period() | ||
7 | - ptimer_set_freq() | ||
8 | - ptimer_set_limit() | ||
9 | - ptimer_set_count() | ||
10 | - ptimer_run() | ||
11 | - ptimer_stop() | ||
12 | must be between matched calls to ptimer_transaction_begin() | ||
13 | and ptimer_transaction_commit(). When ptimer_transaction_commit() | ||
14 | is called it will evaluate the state of the timer after all the | ||
15 | changes in the transaction, and call the callback if necessary. | ||
16 | |||
17 | In the old API the individual update functions generally would | ||
18 | call ptimer_trigger() immediately, which would schedule the QEMUBH. | ||
19 | In the new API the update functions will instead defer the | ||
20 | "set s->next_event and call ptimer_reload()" work to | ||
21 | ptimer_transaction_commit(). | ||
22 | |||
23 | Because ptimer_trigger() can now immediately call into the | ||
24 | device code which may then call other ptimer functions that | ||
25 | update ptimer_state fields, we must be more careful in | ||
26 | ptimer_reload() not to cache fields from ptimer_state across | ||
27 | the ptimer_trigger() call. (This was harmless with the QEMUBH | ||
28 | mechanism as the BH would not be invoked until much later.) | ||
29 | |||
30 | We use assertions to check that: | ||
31 | * the functions modifying ptimer state are not called outside | ||
32 | a transaction block | ||
33 | * ptimer_transaction_begin() and _commit() calls are paired | ||
34 | * the transaction API is not used with a QEMUBH ptimer | ||
35 | |||
36 | There is some slight repetition of code: | ||
37 | * most of the set functions have similar looking "if s->bh | ||
38 | call ptimer_reload, otherwise set s->need_reload" code | ||
39 | * ptimer_init() and ptimer_init_with_bh() have similar code | ||
40 | We deliberately don't try to avoid this repetition, because | ||
41 | it will all be deleted when the QEMUBH version of the API | ||
42 | is removed. | ||
43 | 3 | ||
44 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
45 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
46 | Message-id: 20191008171740.9679-3-peter.maydell@linaro.org | 6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
7 | Message-id: 20210215103215.4944-8-peter.maydell@linaro.org | ||
47 | --- | 8 | --- |
48 | include/hw/ptimer.h | 72 +++++++++++++++++++++ | 9 | hw/display/omap_lcd_template.h | 6 +++--- |
49 | hw/core/ptimer.c | 152 +++++++++++++++++++++++++++++++++++++++----- | 10 | 1 file changed, 3 insertions(+), 3 deletions(-) |
50 | 2 files changed, 209 insertions(+), 15 deletions(-) | ||
51 | 11 | ||
52 | diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h | 12 | diff --git a/hw/display/omap_lcd_template.h b/hw/display/omap_lcd_template.h |
53 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
54 | --- a/include/hw/ptimer.h | 14 | --- a/hw/display/omap_lcd_template.h |
55 | +++ b/include/hw/ptimer.h | 15 | +++ b/hw/display/omap_lcd_template.h |
56 | @@ -XXX,XX +XXX,XX @@ typedef void (*ptimer_cb)(void *opaque); | 16 | @@ -XXX,XX +XXX,XX @@ static void draw_line2_32(void *opaque, uint8_t *d, const uint8_t *s, |
57 | */ | 17 | b = (pal[v & 3] << 4) & 0xf0; |
58 | ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask); | 18 | ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); |
59 | 19 | d += 4; | |
60 | +/** | 20 | - s ++; |
61 | + * ptimer_init - Allocate and return a new ptimer | 21 | + s++; |
62 | + * @callback: function to call on ptimer expiry | 22 | width -= 4; |
63 | + * @callback_opaque: opaque pointer passed to @callback | 23 | } while (width > 0); |
64 | + * @policy: PTIMER_POLICY_* bits specifying behaviour | ||
65 | + * | ||
66 | + * The ptimer returned must be freed using ptimer_free(). | ||
67 | + * | ||
68 | + * If a ptimer is created using this API then will use the | ||
69 | + * transaction-based API for modifying ptimer state: all calls | ||
70 | + * to functions which modify ptimer state: | ||
71 | + * - ptimer_set_period() | ||
72 | + * - ptimer_set_freq() | ||
73 | + * - ptimer_set_limit() | ||
74 | + * - ptimer_set_count() | ||
75 | + * - ptimer_run() | ||
76 | + * - ptimer_stop() | ||
77 | + * must be between matched calls to ptimer_transaction_begin() | ||
78 | + * and ptimer_transaction_commit(). When ptimer_transaction_commit() | ||
79 | + * is called it will evaluate the state of the timer after all the | ||
80 | + * changes in the transaction, and call the callback if necessary. | ||
81 | + * | ||
82 | + * The callback function is always called from within a transaction | ||
83 | + * begin/commit block, so the callback should not call the | ||
84 | + * ptimer_transaction_begin() function itself. If the callback changes | ||
85 | + * the ptimer state such that another ptimer expiry is triggered, then | ||
86 | + * the callback will be called a second time after the first call returns. | ||
87 | + */ | ||
88 | +ptimer_state *ptimer_init(ptimer_cb callback, | ||
89 | + void *callback_opaque, | ||
90 | + uint8_t policy_mask); | ||
91 | + | ||
92 | /** | ||
93 | * ptimer_free - Free a ptimer | ||
94 | * @s: timer to free | ||
95 | @@ -XXX,XX +XXX,XX @@ ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask); | ||
96 | */ | ||
97 | void ptimer_free(ptimer_state *s); | ||
98 | |||
99 | +/** | ||
100 | + * ptimer_transaction_begin() - Start a ptimer modification transaction | ||
101 | + * | ||
102 | + * This function must be called before making any calls to functions | ||
103 | + * which modify the ptimer's state (see the ptimer_init() documentation | ||
104 | + * for a list of these), and must always have a matched call to | ||
105 | + * ptimer_transaction_commit(). | ||
106 | + * It is an error to call this function for a BH-based ptimer; | ||
107 | + * attempting to do this will trigger an assert. | ||
108 | + */ | ||
109 | +void ptimer_transaction_begin(ptimer_state *s); | ||
110 | + | ||
111 | +/** | ||
112 | + * ptimer_transaction_commit() - Commit a ptimer modification transaction | ||
113 | + * | ||
114 | + * This function must be called after calls to functions which modify | ||
115 | + * the ptimer's state, and completes the update of the ptimer. If the | ||
116 | + * ptimer state now means that we should trigger the timer expiry | ||
117 | + * callback, it will be called directly. | ||
118 | + */ | ||
119 | +void ptimer_transaction_commit(ptimer_state *s); | ||
120 | + | ||
121 | /** | ||
122 | * ptimer_set_period - Set counter increment interval in nanoseconds | ||
123 | * @s: ptimer to configure | ||
124 | @@ -XXX,XX +XXX,XX @@ void ptimer_free(ptimer_state *s); | ||
125 | * Note that if your counter behaviour is specified as having a | ||
126 | * particular frequency rather than a period then ptimer_set_freq() | ||
127 | * may be more appropriate. | ||
128 | + * | ||
129 | + * This function will assert if it is called outside a | ||
130 | + * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. | ||
131 | */ | ||
132 | void ptimer_set_period(ptimer_state *s, int64_t period); | ||
133 | |||
134 | @@ -XXX,XX +XXX,XX @@ void ptimer_set_period(ptimer_state *s, int64_t period); | ||
135 | * as setting the frequency then this function is more appropriate, | ||
136 | * because it allows specifying an effective period which is | ||
137 | * precise to fractions of a nanosecond, avoiding rounding errors. | ||
138 | + * | ||
139 | + * This function will assert if it is called outside a | ||
140 | + * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. | ||
141 | */ | ||
142 | void ptimer_set_freq(ptimer_state *s, uint32_t freq); | ||
143 | |||
144 | @@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_limit(ptimer_state *s); | ||
145 | * Set the limit value of the down-counter. The @reload flag can | ||
146 | * be used to emulate the behaviour of timers which immediately | ||
147 | * reload the counter when their reload register is written to. | ||
148 | + * | ||
149 | + * This function will assert if it is called outside a | ||
150 | + * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. | ||
151 | */ | ||
152 | void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload); | ||
153 | |||
154 | @@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_count(ptimer_state *s); | ||
155 | * Set the value of the down-counter. If the counter is currently | ||
156 | * enabled this will arrange for a timer callback at the appropriate | ||
157 | * point in the future. | ||
158 | + * | ||
159 | + * This function will assert if it is called outside a | ||
160 | + * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. | ||
161 | */ | ||
162 | void ptimer_set_count(ptimer_state *s, uint64_t count); | ||
163 | |||
164 | @@ -XXX,XX +XXX,XX @@ void ptimer_set_count(ptimer_state *s, uint64_t count); | ||
165 | * the counter value will then be reloaded from the limit and it will | ||
166 | * start counting down again. If @oneshot is non-zero, then the counter | ||
167 | * will disable itself when it reaches zero. | ||
168 | + * | ||
169 | + * This function will assert if it is called outside a | ||
170 | + * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. | ||
171 | */ | ||
172 | void ptimer_run(ptimer_state *s, int oneshot); | ||
173 | |||
174 | @@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot); | ||
175 | * | ||
176 | * Note that this can cause it to "lose" time, even if it is immediately | ||
177 | * restarted. | ||
178 | + * | ||
179 | + * This function will assert if it is called outside a | ||
180 | + * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. | ||
181 | */ | ||
182 | void ptimer_stop(ptimer_state *s); | ||
183 | |||
184 | diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c | ||
185 | index XXXXXXX..XXXXXXX 100644 | ||
186 | --- a/hw/core/ptimer.c | ||
187 | +++ b/hw/core/ptimer.c | ||
188 | @@ -XXX,XX +XXX,XX @@ struct ptimer_state | ||
189 | uint8_t policy_mask; | ||
190 | QEMUBH *bh; | ||
191 | QEMUTimer *timer; | ||
192 | + ptimer_cb callback; | ||
193 | + void *callback_opaque; | ||
194 | + /* | ||
195 | + * These track whether we're in a transaction block, and if we | ||
196 | + * need to do a timer reload when the block finishes. They don't | ||
197 | + * need to be migrated because migration can never happen in the | ||
198 | + * middle of a transaction block. | ||
199 | + */ | ||
200 | + bool in_transaction; | ||
201 | + bool need_reload; | ||
202 | }; | ||
203 | |||
204 | /* Use a bottom-half routine to avoid reentrancy issues. */ | ||
205 | @@ -XXX,XX +XXX,XX @@ static void ptimer_trigger(ptimer_state *s) | ||
206 | if (s->bh) { | ||
207 | replay_bh_schedule_event(s->bh); | ||
208 | } | ||
209 | + if (s->callback) { | ||
210 | + s->callback(s->callback_opaque); | ||
211 | + } | ||
212 | } | 24 | } |
213 | 25 | @@ -XXX,XX +XXX,XX @@ static void draw_line4_32(void *opaque, uint8_t *d, const uint8_t *s, | |
214 | static void ptimer_reload(ptimer_state *s, int delta_adjust) | 26 | b = (pal[v & 0xf] << 4) & 0xf0; |
215 | { | 27 | ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); |
216 | - uint32_t period_frac = s->period_frac; | 28 | d += 4; |
217 | - uint64_t period = s->period; | 29 | - s ++; |
218 | - uint64_t delta = s->delta; | 30 | + s++; |
219 | + uint32_t period_frac; | 31 | width -= 2; |
220 | + uint64_t period; | 32 | } while (width > 0); |
221 | + uint64_t delta; | ||
222 | bool suppress_trigger = false; | ||
223 | |||
224 | /* | ||
225 | @@ -XXX,XX +XXX,XX @@ static void ptimer_reload(ptimer_state *s, int delta_adjust) | ||
226 | (s->policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT)) { | ||
227 | suppress_trigger = true; | ||
228 | } | ||
229 | - if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER) | ||
230 | + if (s->delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER) | ||
231 | && !suppress_trigger) { | ||
232 | ptimer_trigger(s); | ||
233 | } | ||
234 | |||
235 | + /* | ||
236 | + * Note that ptimer_trigger() might call the device callback function, | ||
237 | + * which can then modify timer state, so we must not cache any fields | ||
238 | + * from ptimer_state until after we have called it. | ||
239 | + */ | ||
240 | + delta = s->delta; | ||
241 | + period = s->period; | ||
242 | + period_frac = s->period_frac; | ||
243 | + | ||
244 | if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_RELOAD)) { | ||
245 | delta = s->delta = s->limit; | ||
246 | } | ||
247 | @@ -XXX,XX +XXX,XX @@ static void ptimer_tick(void *opaque) | ||
248 | ptimer_state *s = (ptimer_state *)opaque; | ||
249 | bool trigger = true; | ||
250 | |||
251 | + /* | ||
252 | + * We perform all the tick actions within a begin/commit block | ||
253 | + * because the callback function that ptimer_trigger() calls | ||
254 | + * might make calls into the ptimer APIs that provoke another | ||
255 | + * trigger, and we want that to cause the callback function | ||
256 | + * to be called iteratively, not recursively. | ||
257 | + */ | ||
258 | + ptimer_transaction_begin(s); | ||
259 | + | ||
260 | if (s->enabled == 2) { | ||
261 | s->delta = 0; | ||
262 | s->enabled = 0; | ||
263 | @@ -XXX,XX +XXX,XX @@ static void ptimer_tick(void *opaque) | ||
264 | if (trigger) { | ||
265 | ptimer_trigger(s); | ||
266 | } | ||
267 | + | ||
268 | + ptimer_transaction_commit(s); | ||
269 | } | 33 | } |
270 | 34 | @@ -XXX,XX +XXX,XX @@ static void draw_line8_32(void *opaque, uint8_t *d, const uint8_t *s, | |
271 | uint64_t ptimer_get_count(ptimer_state *s) | 35 | g = pal[v] & 0xf0; |
272 | @@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_count(ptimer_state *s) | 36 | b = (pal[v] << 4) & 0xf0; |
273 | 37 | ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | |
274 | void ptimer_set_count(ptimer_state *s, uint64_t count) | 38 | - s ++; |
275 | { | 39 | + s++; |
276 | + assert(s->in_transaction || !s->callback); | 40 | d += 4; |
277 | s->delta = count; | 41 | } while (-- width != 0); |
278 | if (s->enabled) { | ||
279 | - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
280 | - ptimer_reload(s, 0); | ||
281 | + if (!s->callback) { | ||
282 | + s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
283 | + ptimer_reload(s, 0); | ||
284 | + } else { | ||
285 | + s->need_reload = true; | ||
286 | + } | ||
287 | } | ||
288 | } | ||
289 | |||
290 | @@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot) | ||
291 | { | ||
292 | bool was_disabled = !s->enabled; | ||
293 | |||
294 | + assert(s->in_transaction || !s->callback); | ||
295 | + | ||
296 | if (was_disabled && s->period == 0) { | ||
297 | if (!qtest_enabled()) { | ||
298 | fprintf(stderr, "Timer with period zero, disabling\n"); | ||
299 | @@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot) | ||
300 | } | ||
301 | s->enabled = oneshot ? 2 : 1; | ||
302 | if (was_disabled) { | ||
303 | - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
304 | - ptimer_reload(s, 0); | ||
305 | + if (!s->callback) { | ||
306 | + s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
307 | + ptimer_reload(s, 0); | ||
308 | + } else { | ||
309 | + s->need_reload = true; | ||
310 | + } | ||
311 | } | ||
312 | } | ||
313 | |||
314 | @@ -XXX,XX +XXX,XX @@ void ptimer_run(ptimer_state *s, int oneshot) | ||
315 | is immediately restarted. */ | ||
316 | void ptimer_stop(ptimer_state *s) | ||
317 | { | ||
318 | + assert(s->in_transaction || !s->callback); | ||
319 | + | ||
320 | if (!s->enabled) | ||
321 | return; | ||
322 | |||
323 | s->delta = ptimer_get_count(s); | ||
324 | timer_del(s->timer); | ||
325 | s->enabled = 0; | ||
326 | + if (s->callback) { | ||
327 | + s->need_reload = false; | ||
328 | + } | ||
329 | } | ||
330 | |||
331 | /* Set counter increment interval in nanoseconds. */ | ||
332 | void ptimer_set_period(ptimer_state *s, int64_t period) | ||
333 | { | ||
334 | + assert(s->in_transaction || !s->callback); | ||
335 | s->delta = ptimer_get_count(s); | ||
336 | s->period = period; | ||
337 | s->period_frac = 0; | ||
338 | if (s->enabled) { | ||
339 | - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
340 | - ptimer_reload(s, 0); | ||
341 | + if (!s->callback) { | ||
342 | + s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
343 | + ptimer_reload(s, 0); | ||
344 | + } else { | ||
345 | + s->need_reload = true; | ||
346 | + } | ||
347 | } | ||
348 | } | ||
349 | |||
350 | /* Set counter frequency in Hz. */ | ||
351 | void ptimer_set_freq(ptimer_state *s, uint32_t freq) | ||
352 | { | ||
353 | + assert(s->in_transaction || !s->callback); | ||
354 | s->delta = ptimer_get_count(s); | ||
355 | s->period = 1000000000ll / freq; | ||
356 | s->period_frac = (1000000000ll << 32) / freq; | ||
357 | if (s->enabled) { | ||
358 | - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
359 | - ptimer_reload(s, 0); | ||
360 | + if (!s->callback) { | ||
361 | + s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
362 | + ptimer_reload(s, 0); | ||
363 | + } else { | ||
364 | + s->need_reload = true; | ||
365 | + } | ||
366 | } | ||
367 | } | ||
368 | |||
369 | @@ -XXX,XX +XXX,XX @@ void ptimer_set_freq(ptimer_state *s, uint32_t freq) | ||
370 | count = limit. */ | ||
371 | void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload) | ||
372 | { | ||
373 | + assert(s->in_transaction || !s->callback); | ||
374 | s->limit = limit; | ||
375 | if (reload) | ||
376 | s->delta = limit; | ||
377 | if (s->enabled && reload) { | ||
378 | - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
379 | - ptimer_reload(s, 0); | ||
380 | + if (!s->callback) { | ||
381 | + s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
382 | + ptimer_reload(s, 0); | ||
383 | + } else { | ||
384 | + s->need_reload = true; | ||
385 | + } | ||
386 | } | ||
387 | } | ||
388 | |||
389 | @@ -XXX,XX +XXX,XX @@ uint64_t ptimer_get_limit(ptimer_state *s) | ||
390 | return s->limit; | ||
391 | } | ||
392 | |||
393 | +void ptimer_transaction_begin(ptimer_state *s) | ||
394 | +{ | ||
395 | + assert(!s->in_transaction || !s->callback); | ||
396 | + s->in_transaction = true; | ||
397 | + s->need_reload = false; | ||
398 | +} | ||
399 | + | ||
400 | +void ptimer_transaction_commit(ptimer_state *s) | ||
401 | +{ | ||
402 | + assert(s->in_transaction); | ||
403 | + /* | ||
404 | + * We must loop here because ptimer_reload() can call the callback | ||
405 | + * function, which might then update ptimer state in a way that | ||
406 | + * means we need to do another reload and possibly another callback. | ||
407 | + * A disabled timer never needs reloading (and if we don't check | ||
408 | + * this then we loop forever if ptimer_reload() disables the timer). | ||
409 | + */ | ||
410 | + while (s->need_reload && s->enabled) { | ||
411 | + s->need_reload = false; | ||
412 | + s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
413 | + ptimer_reload(s, 0); | ||
414 | + } | ||
415 | + /* Now we've finished reload we can leave the transaction block. */ | ||
416 | + s->in_transaction = false; | ||
417 | +} | ||
418 | + | ||
419 | const VMStateDescription vmstate_ptimer = { | ||
420 | .name = "ptimer", | ||
421 | .version_id = 1, | ||
422 | @@ -XXX,XX +XXX,XX @@ ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask) | ||
423 | return s; | ||
424 | } | ||
425 | |||
426 | +ptimer_state *ptimer_init(ptimer_cb callback, void *callback_opaque, | ||
427 | + uint8_t policy_mask) | ||
428 | +{ | ||
429 | + ptimer_state *s; | ||
430 | + | ||
431 | + /* | ||
432 | + * The callback function is mandatory; so we use it to distinguish | ||
433 | + * old-style QEMUBH ptimers from new transaction API ptimers. | ||
434 | + * (ptimer_init_with_bh() allows a NULL bh pointer and at least | ||
435 | + * one device (digic-timer) passes NULL, so it's not the case | ||
436 | + * that either s->bh != NULL or s->callback != NULL.) | ||
437 | + */ | ||
438 | + assert(callback); | ||
439 | + | ||
440 | + s = g_new0(ptimer_state, 1); | ||
441 | + s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s); | ||
442 | + s->policy_mask = policy_mask; | ||
443 | + s->callback = callback; | ||
444 | + s->callback_opaque = callback_opaque; | ||
445 | + | ||
446 | + /* | ||
447 | + * These two policies are incompatible -- trigger-on-decrement implies | ||
448 | + * a timer trigger when the count becomes 0, but no-immediate-trigger | ||
449 | + * implies a trigger when the count stops being 0. | ||
450 | + */ | ||
451 | + assert(!((policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) && | ||
452 | + (policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER))); | ||
453 | + return s; | ||
454 | +} | ||
455 | + | ||
456 | void ptimer_free(ptimer_state *s) | ||
457 | { | ||
458 | - qemu_bh_delete(s->bh); | ||
459 | + if (s->bh) { | ||
460 | + qemu_bh_delete(s->bh); | ||
461 | + } | ||
462 | timer_free(s->timer); | ||
463 | g_free(s); | ||
464 | } | 42 | } |
465 | -- | 43 | -- |
466 | 2.20.1 | 44 | 2.20.1 |
467 | 45 | ||
468 | 46 | diff view generated by jsdifflib |
1 | Convert the ptimer test cases to the transaction-based ptimer API, | 1 | We only include the template header once, so just inline it into the |
---|---|---|---|
2 | by changing to ptimer_init(), dropping the now-unused QEMUBH | 2 | source file for the device. |
3 | variables, and surrounding each set of changes to the ptimer | ||
4 | state in ptimer_transaction_begin/commit calls. | ||
5 | 3 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20191008171740.9679-4-peter.maydell@linaro.org | 6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
7 | Message-id: 20210215103215.4944-9-peter.maydell@linaro.org | ||
9 | --- | 8 | --- |
10 | tests/ptimer-test.c | 106 +++++++++++++++++++++++++++++++++++--------- | 9 | hw/display/omap_lcd_template.h | 154 --------------------------------- |
11 | 1 file changed, 84 insertions(+), 22 deletions(-) | 10 | hw/display/omap_lcdc.c | 127 ++++++++++++++++++++++++++- |
11 | 2 files changed, 125 insertions(+), 156 deletions(-) | ||
12 | delete mode 100644 hw/display/omap_lcd_template.h | ||
12 | 13 | ||
13 | diff --git a/tests/ptimer-test.c b/tests/ptimer-test.c | 14 | diff --git a/hw/display/omap_lcd_template.h b/hw/display/omap_lcd_template.h |
15 | deleted file mode 100644 | ||
16 | index XXXXXXX..XXXXXXX | ||
17 | --- a/hw/display/omap_lcd_template.h | ||
18 | +++ /dev/null | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | -/* | ||
21 | - * QEMU OMAP LCD Emulator templates | ||
22 | - * | ||
23 | - * Copyright (c) 2006 Andrzej Zaborowski <balrog@zabor.org> | ||
24 | - * | ||
25 | - * Redistribution and use in source and binary forms, with or without | ||
26 | - * modification, are permitted provided that the following conditions | ||
27 | - * are met: | ||
28 | - * | ||
29 | - * 1. Redistributions of source code must retain the above copyright | ||
30 | - * notice, this list of conditions and the following disclaimer. | ||
31 | - * 2. Redistributions in binary form must reproduce the above copyright | ||
32 | - * notice, this list of conditions and the following disclaimer in | ||
33 | - * the documentation and/or other materials provided with the | ||
34 | - * distribution. | ||
35 | - * | ||
36 | - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' | ||
37 | - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | ||
38 | - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A | ||
39 | - * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR | ||
40 | - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | ||
41 | - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | ||
42 | - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | ||
43 | - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY | ||
44 | - * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
45 | - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | ||
46 | - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
47 | - */ | ||
48 | - | ||
49 | -/* | ||
50 | - * 2-bit colour | ||
51 | - */ | ||
52 | -static void draw_line2_32(void *opaque, uint8_t *d, const uint8_t *s, | ||
53 | - int width, int deststep) | ||
54 | -{ | ||
55 | - uint16_t *pal = opaque; | ||
56 | - uint8_t v, r, g, b; | ||
57 | - | ||
58 | - do { | ||
59 | - v = ldub_p((void *) s); | ||
60 | - r = (pal[v & 3] >> 4) & 0xf0; | ||
61 | - g = pal[v & 3] & 0xf0; | ||
62 | - b = (pal[v & 3] << 4) & 0xf0; | ||
63 | - ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
64 | - d += 4; | ||
65 | - v >>= 2; | ||
66 | - r = (pal[v & 3] >> 4) & 0xf0; | ||
67 | - g = pal[v & 3] & 0xf0; | ||
68 | - b = (pal[v & 3] << 4) & 0xf0; | ||
69 | - ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
70 | - d += 4; | ||
71 | - v >>= 2; | ||
72 | - r = (pal[v & 3] >> 4) & 0xf0; | ||
73 | - g = pal[v & 3] & 0xf0; | ||
74 | - b = (pal[v & 3] << 4) & 0xf0; | ||
75 | - ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
76 | - d += 4; | ||
77 | - v >>= 2; | ||
78 | - r = (pal[v & 3] >> 4) & 0xf0; | ||
79 | - g = pal[v & 3] & 0xf0; | ||
80 | - b = (pal[v & 3] << 4) & 0xf0; | ||
81 | - ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
82 | - d += 4; | ||
83 | - s++; | ||
84 | - width -= 4; | ||
85 | - } while (width > 0); | ||
86 | -} | ||
87 | - | ||
88 | -/* | ||
89 | - * 4-bit colour | ||
90 | - */ | ||
91 | -static void draw_line4_32(void *opaque, uint8_t *d, const uint8_t *s, | ||
92 | - int width, int deststep) | ||
93 | -{ | ||
94 | - uint16_t *pal = opaque; | ||
95 | - uint8_t v, r, g, b; | ||
96 | - | ||
97 | - do { | ||
98 | - v = ldub_p((void *) s); | ||
99 | - r = (pal[v & 0xf] >> 4) & 0xf0; | ||
100 | - g = pal[v & 0xf] & 0xf0; | ||
101 | - b = (pal[v & 0xf] << 4) & 0xf0; | ||
102 | - ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
103 | - d += 4; | ||
104 | - v >>= 4; | ||
105 | - r = (pal[v & 0xf] >> 4) & 0xf0; | ||
106 | - g = pal[v & 0xf] & 0xf0; | ||
107 | - b = (pal[v & 0xf] << 4) & 0xf0; | ||
108 | - ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
109 | - d += 4; | ||
110 | - s++; | ||
111 | - width -= 2; | ||
112 | - } while (width > 0); | ||
113 | -} | ||
114 | - | ||
115 | -/* | ||
116 | - * 8-bit colour | ||
117 | - */ | ||
118 | -static void draw_line8_32(void *opaque, uint8_t *d, const uint8_t *s, | ||
119 | - int width, int deststep) | ||
120 | -{ | ||
121 | - uint16_t *pal = opaque; | ||
122 | - uint8_t v, r, g, b; | ||
123 | - | ||
124 | - do { | ||
125 | - v = ldub_p((void *) s); | ||
126 | - r = (pal[v] >> 4) & 0xf0; | ||
127 | - g = pal[v] & 0xf0; | ||
128 | - b = (pal[v] << 4) & 0xf0; | ||
129 | - ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
130 | - s++; | ||
131 | - d += 4; | ||
132 | - } while (-- width != 0); | ||
133 | -} | ||
134 | - | ||
135 | -/* | ||
136 | - * 12-bit colour | ||
137 | - */ | ||
138 | -static void draw_line12_32(void *opaque, uint8_t *d, const uint8_t *s, | ||
139 | - int width, int deststep) | ||
140 | -{ | ||
141 | - uint16_t v; | ||
142 | - uint8_t r, g, b; | ||
143 | - | ||
144 | - do { | ||
145 | - v = lduw_le_p((void *) s); | ||
146 | - r = (v >> 4) & 0xf0; | ||
147 | - g = v & 0xf0; | ||
148 | - b = (v << 4) & 0xf0; | ||
149 | - ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
150 | - s += 2; | ||
151 | - d += 4; | ||
152 | - } while (-- width != 0); | ||
153 | -} | ||
154 | - | ||
155 | -/* | ||
156 | - * 16-bit colour | ||
157 | - */ | ||
158 | -static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s, | ||
159 | - int width, int deststep) | ||
160 | -{ | ||
161 | - uint16_t v; | ||
162 | - uint8_t r, g, b; | ||
163 | - | ||
164 | - do { | ||
165 | - v = lduw_le_p((void *) s); | ||
166 | - r = (v >> 8) & 0xf8; | ||
167 | - g = (v >> 3) & 0xfc; | ||
168 | - b = (v << 3) & 0xf8; | ||
169 | - ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
170 | - s += 2; | ||
171 | - d += 4; | ||
172 | - } while (-- width != 0); | ||
173 | -} | ||
174 | diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | 175 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/tests/ptimer-test.c | 176 | --- a/hw/display/omap_lcdc.c |
16 | +++ b/tests/ptimer-test.c | 177 | +++ b/hw/display/omap_lcdc.c |
17 | @@ -XXX,XX +XXX,XX @@ static void qemu_clock_step(uint64_t ns) | 178 | @@ -XXX,XX +XXX,XX @@ static void omap_lcd_interrupts(struct omap_lcd_panel_s *s) |
18 | static void check_set_count(gconstpointer arg) | 179 | |
180 | #define draw_line_func drawfn | ||
181 | |||
182 | -#define DEPTH 32 | ||
183 | -#include "omap_lcd_template.h" | ||
184 | +/* | ||
185 | + * 2-bit colour | ||
186 | + */ | ||
187 | +static void draw_line2_32(void *opaque, uint8_t *d, const uint8_t *s, | ||
188 | + int width, int deststep) | ||
189 | +{ | ||
190 | + uint16_t *pal = opaque; | ||
191 | + uint8_t v, r, g, b; | ||
192 | + | ||
193 | + do { | ||
194 | + v = ldub_p((void *) s); | ||
195 | + r = (pal[v & 3] >> 4) & 0xf0; | ||
196 | + g = pal[v & 3] & 0xf0; | ||
197 | + b = (pal[v & 3] << 4) & 0xf0; | ||
198 | + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
199 | + d += 4; | ||
200 | + v >>= 2; | ||
201 | + r = (pal[v & 3] >> 4) & 0xf0; | ||
202 | + g = pal[v & 3] & 0xf0; | ||
203 | + b = (pal[v & 3] << 4) & 0xf0; | ||
204 | + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
205 | + d += 4; | ||
206 | + v >>= 2; | ||
207 | + r = (pal[v & 3] >> 4) & 0xf0; | ||
208 | + g = pal[v & 3] & 0xf0; | ||
209 | + b = (pal[v & 3] << 4) & 0xf0; | ||
210 | + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
211 | + d += 4; | ||
212 | + v >>= 2; | ||
213 | + r = (pal[v & 3] >> 4) & 0xf0; | ||
214 | + g = pal[v & 3] & 0xf0; | ||
215 | + b = (pal[v & 3] << 4) & 0xf0; | ||
216 | + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
217 | + d += 4; | ||
218 | + s++; | ||
219 | + width -= 4; | ||
220 | + } while (width > 0); | ||
221 | +} | ||
222 | + | ||
223 | +/* | ||
224 | + * 4-bit colour | ||
225 | + */ | ||
226 | +static void draw_line4_32(void *opaque, uint8_t *d, const uint8_t *s, | ||
227 | + int width, int deststep) | ||
228 | +{ | ||
229 | + uint16_t *pal = opaque; | ||
230 | + uint8_t v, r, g, b; | ||
231 | + | ||
232 | + do { | ||
233 | + v = ldub_p((void *) s); | ||
234 | + r = (pal[v & 0xf] >> 4) & 0xf0; | ||
235 | + g = pal[v & 0xf] & 0xf0; | ||
236 | + b = (pal[v & 0xf] << 4) & 0xf0; | ||
237 | + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
238 | + d += 4; | ||
239 | + v >>= 4; | ||
240 | + r = (pal[v & 0xf] >> 4) & 0xf0; | ||
241 | + g = pal[v & 0xf] & 0xf0; | ||
242 | + b = (pal[v & 0xf] << 4) & 0xf0; | ||
243 | + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
244 | + d += 4; | ||
245 | + s++; | ||
246 | + width -= 2; | ||
247 | + } while (width > 0); | ||
248 | +} | ||
249 | + | ||
250 | +/* | ||
251 | + * 8-bit colour | ||
252 | + */ | ||
253 | +static void draw_line8_32(void *opaque, uint8_t *d, const uint8_t *s, | ||
254 | + int width, int deststep) | ||
255 | +{ | ||
256 | + uint16_t *pal = opaque; | ||
257 | + uint8_t v, r, g, b; | ||
258 | + | ||
259 | + do { | ||
260 | + v = ldub_p((void *) s); | ||
261 | + r = (pal[v] >> 4) & 0xf0; | ||
262 | + g = pal[v] & 0xf0; | ||
263 | + b = (pal[v] << 4) & 0xf0; | ||
264 | + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
265 | + s++; | ||
266 | + d += 4; | ||
267 | + } while (-- width != 0); | ||
268 | +} | ||
269 | + | ||
270 | +/* | ||
271 | + * 12-bit colour | ||
272 | + */ | ||
273 | +static void draw_line12_32(void *opaque, uint8_t *d, const uint8_t *s, | ||
274 | + int width, int deststep) | ||
275 | +{ | ||
276 | + uint16_t v; | ||
277 | + uint8_t r, g, b; | ||
278 | + | ||
279 | + do { | ||
280 | + v = lduw_le_p((void *) s); | ||
281 | + r = (v >> 4) & 0xf0; | ||
282 | + g = v & 0xf0; | ||
283 | + b = (v << 4) & 0xf0; | ||
284 | + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
285 | + s += 2; | ||
286 | + d += 4; | ||
287 | + } while (-- width != 0); | ||
288 | +} | ||
289 | + | ||
290 | +/* | ||
291 | + * 16-bit colour | ||
292 | + */ | ||
293 | +static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s, | ||
294 | + int width, int deststep) | ||
295 | +{ | ||
296 | + uint16_t v; | ||
297 | + uint8_t r, g, b; | ||
298 | + | ||
299 | + do { | ||
300 | + v = lduw_le_p((void *) s); | ||
301 | + r = (v >> 8) & 0xf8; | ||
302 | + g = (v >> 3) & 0xfc; | ||
303 | + b = (v << 3) & 0xf8; | ||
304 | + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); | ||
305 | + s += 2; | ||
306 | + d += 4; | ||
307 | + } while (-- width != 0); | ||
308 | +} | ||
309 | |||
310 | static void omap_update_display(void *opaque) | ||
19 | { | 311 | { |
20 | const uint8_t *policy = arg; | ||
21 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
22 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
23 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
24 | |||
25 | triggered = false; | ||
26 | |||
27 | + ptimer_transaction_begin(ptimer); | ||
28 | ptimer_set_count(ptimer, 1000); | ||
29 | + ptimer_transaction_commit(ptimer); | ||
30 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 1000); | ||
31 | g_assert_false(triggered); | ||
32 | ptimer_free(ptimer); | ||
33 | @@ -XXX,XX +XXX,XX @@ static void check_set_count(gconstpointer arg) | ||
34 | static void check_set_limit(gconstpointer arg) | ||
35 | { | ||
36 | const uint8_t *policy = arg; | ||
37 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
38 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
39 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
40 | |||
41 | triggered = false; | ||
42 | |||
43 | + ptimer_transaction_begin(ptimer); | ||
44 | ptimer_set_limit(ptimer, 1000, 0); | ||
45 | + ptimer_transaction_commit(ptimer); | ||
46 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0); | ||
47 | g_assert_cmpuint(ptimer_get_limit(ptimer), ==, 1000); | ||
48 | g_assert_false(triggered); | ||
49 | |||
50 | + ptimer_transaction_begin(ptimer); | ||
51 | ptimer_set_limit(ptimer, 2000, 1); | ||
52 | + ptimer_transaction_commit(ptimer); | ||
53 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 2000); | ||
54 | g_assert_cmpuint(ptimer_get_limit(ptimer), ==, 2000); | ||
55 | g_assert_false(triggered); | ||
56 | @@ -XXX,XX +XXX,XX @@ static void check_set_limit(gconstpointer arg) | ||
57 | static void check_oneshot(gconstpointer arg) | ||
58 | { | ||
59 | const uint8_t *policy = arg; | ||
60 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
61 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
62 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
63 | bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | ||
64 | |||
65 | triggered = false; | ||
66 | |||
67 | + ptimer_transaction_begin(ptimer); | ||
68 | ptimer_set_period(ptimer, 2000000); | ||
69 | ptimer_set_count(ptimer, 10); | ||
70 | ptimer_run(ptimer, 1); | ||
71 | + ptimer_transaction_commit(ptimer); | ||
72 | |||
73 | qemu_clock_step(2000000 * 2 + 1); | ||
74 | |||
75 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 8 : 7); | ||
76 | g_assert_false(triggered); | ||
77 | |||
78 | + ptimer_transaction_begin(ptimer); | ||
79 | ptimer_stop(ptimer); | ||
80 | + ptimer_transaction_commit(ptimer); | ||
81 | |||
82 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 8 : 7); | ||
83 | g_assert_false(triggered); | ||
84 | @@ -XXX,XX +XXX,XX @@ static void check_oneshot(gconstpointer arg) | ||
85 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 8 : 7); | ||
86 | g_assert_false(triggered); | ||
87 | |||
88 | + ptimer_transaction_begin(ptimer); | ||
89 | ptimer_run(ptimer, 1); | ||
90 | + ptimer_transaction_commit(ptimer); | ||
91 | |||
92 | qemu_clock_step(2000000 * 7 + 1); | ||
93 | |||
94 | @@ -XXX,XX +XXX,XX @@ static void check_oneshot(gconstpointer arg) | ||
95 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0); | ||
96 | g_assert_false(triggered); | ||
97 | |||
98 | + ptimer_transaction_begin(ptimer); | ||
99 | ptimer_set_count(ptimer, 10); | ||
100 | + ptimer_transaction_commit(ptimer); | ||
101 | |||
102 | qemu_clock_step(20000000 + 1); | ||
103 | |||
104 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 10); | ||
105 | g_assert_false(triggered); | ||
106 | |||
107 | + ptimer_transaction_begin(ptimer); | ||
108 | ptimer_set_limit(ptimer, 9, 1); | ||
109 | + ptimer_transaction_commit(ptimer); | ||
110 | |||
111 | qemu_clock_step(20000000 + 1); | ||
112 | |||
113 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 9); | ||
114 | g_assert_false(triggered); | ||
115 | |||
116 | + ptimer_transaction_begin(ptimer); | ||
117 | ptimer_run(ptimer, 1); | ||
118 | + ptimer_transaction_commit(ptimer); | ||
119 | |||
120 | qemu_clock_step(2000000 + 1); | ||
121 | |||
122 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 8 : 7); | ||
123 | g_assert_false(triggered); | ||
124 | |||
125 | + ptimer_transaction_begin(ptimer); | ||
126 | ptimer_set_count(ptimer, 20); | ||
127 | + ptimer_transaction_commit(ptimer); | ||
128 | |||
129 | qemu_clock_step(2000000 * 19 + 1); | ||
130 | |||
131 | @@ -XXX,XX +XXX,XX @@ static void check_oneshot(gconstpointer arg) | ||
132 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0); | ||
133 | g_assert_true(triggered); | ||
134 | |||
135 | + ptimer_transaction_begin(ptimer); | ||
136 | ptimer_stop(ptimer); | ||
137 | + ptimer_transaction_commit(ptimer); | ||
138 | |||
139 | triggered = false; | ||
140 | |||
141 | @@ -XXX,XX +XXX,XX @@ static void check_oneshot(gconstpointer arg) | ||
142 | static void check_periodic(gconstpointer arg) | ||
143 | { | ||
144 | const uint8_t *policy = arg; | ||
145 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
146 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
147 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
148 | bool wrap_policy = (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); | ||
149 | bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); | ||
150 | bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD); | ||
151 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
152 | |||
153 | triggered = false; | ||
154 | |||
155 | + ptimer_transaction_begin(ptimer); | ||
156 | ptimer_set_period(ptimer, 2000000); | ||
157 | ptimer_set_limit(ptimer, 10, 1); | ||
158 | ptimer_run(ptimer, 0); | ||
159 | + ptimer_transaction_commit(ptimer); | ||
160 | |||
161 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 10); | ||
162 | g_assert_false(triggered); | ||
163 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
164 | (no_round_down ? 9 : 8) + (wrap_policy ? 1 : 0)); | ||
165 | g_assert_false(triggered); | ||
166 | |||
167 | + ptimer_transaction_begin(ptimer); | ||
168 | ptimer_set_count(ptimer, 20); | ||
169 | + ptimer_transaction_commit(ptimer); | ||
170 | |||
171 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 20); | ||
172 | g_assert_false(triggered); | ||
173 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
174 | |||
175 | triggered = false; | ||
176 | |||
177 | + ptimer_transaction_begin(ptimer); | ||
178 | ptimer_set_count(ptimer, 3); | ||
179 | + ptimer_transaction_commit(ptimer); | ||
180 | |||
181 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 3); | ||
182 | g_assert_false(triggered); | ||
183 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
184 | (no_round_down ? 9 : 8) + (wrap_policy ? 1 : 0)); | ||
185 | g_assert_true(triggered); | ||
186 | |||
187 | + ptimer_transaction_begin(ptimer); | ||
188 | ptimer_stop(ptimer); | ||
189 | + ptimer_transaction_commit(ptimer); | ||
190 | triggered = false; | ||
191 | |||
192 | qemu_clock_step(2000000); | ||
193 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
194 | (no_round_down ? 9 : 8) + (wrap_policy ? 1 : 0)); | ||
195 | g_assert_false(triggered); | ||
196 | |||
197 | + ptimer_transaction_begin(ptimer); | ||
198 | ptimer_set_count(ptimer, 3); | ||
199 | ptimer_run(ptimer, 0); | ||
200 | + ptimer_transaction_commit(ptimer); | ||
201 | |||
202 | qemu_clock_step(2000000 * 3 + 1); | ||
203 | |||
204 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
205 | (no_round_down ? 9 : 8) + (wrap_policy ? 1 : 0)); | ||
206 | g_assert_false(triggered); | ||
207 | |||
208 | + ptimer_transaction_begin(ptimer); | ||
209 | ptimer_set_count(ptimer, 0); | ||
210 | + ptimer_transaction_commit(ptimer); | ||
211 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, | ||
212 | no_immediate_reload ? 0 : 10); | ||
213 | |||
214 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
215 | (no_round_down ? 8 : 7) + (wrap_policy ? 1 : 0)); | ||
216 | g_assert_true(triggered); | ||
217 | |||
218 | + ptimer_transaction_begin(ptimer); | ||
219 | ptimer_stop(ptimer); | ||
220 | + ptimer_transaction_commit(ptimer); | ||
221 | |||
222 | triggered = false; | ||
223 | |||
224 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
225 | (no_round_down ? 8 : 7) + (wrap_policy ? 1 : 0)); | ||
226 | g_assert_false(triggered); | ||
227 | |||
228 | + ptimer_transaction_begin(ptimer); | ||
229 | ptimer_run(ptimer, 0); | ||
230 | + ptimer_transaction_commit(ptimer); | ||
231 | + | ||
232 | + ptimer_transaction_begin(ptimer); | ||
233 | ptimer_set_period(ptimer, 0); | ||
234 | + ptimer_transaction_commit(ptimer); | ||
235 | |||
236 | qemu_clock_step(2000000 + 1); | ||
237 | |||
238 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
239 | static void check_on_the_fly_mode_change(gconstpointer arg) | ||
240 | { | ||
241 | const uint8_t *policy = arg; | ||
242 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
243 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
244 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
245 | bool wrap_policy = (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); | ||
246 | bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | ||
247 | |||
248 | triggered = false; | ||
249 | |||
250 | + ptimer_transaction_begin(ptimer); | ||
251 | ptimer_set_period(ptimer, 2000000); | ||
252 | ptimer_set_limit(ptimer, 10, 1); | ||
253 | ptimer_run(ptimer, 1); | ||
254 | + ptimer_transaction_commit(ptimer); | ||
255 | |||
256 | qemu_clock_step(2000000 * 9 + 1); | ||
257 | |||
258 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 1 : 0); | ||
259 | g_assert_false(triggered); | ||
260 | |||
261 | + ptimer_transaction_begin(ptimer); | ||
262 | ptimer_run(ptimer, 0); | ||
263 | + ptimer_transaction_commit(ptimer); | ||
264 | |||
265 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 1 : 0); | ||
266 | g_assert_false(triggered); | ||
267 | @@ -XXX,XX +XXX,XX @@ static void check_on_the_fly_mode_change(gconstpointer arg) | ||
268 | |||
269 | qemu_clock_step(2000000 * 9); | ||
270 | |||
271 | + ptimer_transaction_begin(ptimer); | ||
272 | ptimer_run(ptimer, 1); | ||
273 | + ptimer_transaction_commit(ptimer); | ||
274 | |||
275 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, | ||
276 | (no_round_down ? 1 : 0) + (wrap_policy ? 1 : 0)); | ||
277 | @@ -XXX,XX +XXX,XX @@ static void check_on_the_fly_mode_change(gconstpointer arg) | ||
278 | static void check_on_the_fly_period_change(gconstpointer arg) | ||
279 | { | ||
280 | const uint8_t *policy = arg; | ||
281 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
282 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
283 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
284 | bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | ||
285 | |||
286 | triggered = false; | ||
287 | |||
288 | + ptimer_transaction_begin(ptimer); | ||
289 | ptimer_set_period(ptimer, 2000000); | ||
290 | ptimer_set_limit(ptimer, 8, 1); | ||
291 | ptimer_run(ptimer, 1); | ||
292 | + ptimer_transaction_commit(ptimer); | ||
293 | |||
294 | qemu_clock_step(2000000 * 4 + 1); | ||
295 | |||
296 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 4 : 3); | ||
297 | g_assert_false(triggered); | ||
298 | |||
299 | + ptimer_transaction_begin(ptimer); | ||
300 | ptimer_set_period(ptimer, 4000000); | ||
301 | + ptimer_transaction_commit(ptimer); | ||
302 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 4 : 3); | ||
303 | |||
304 | qemu_clock_step(4000000 * 2 + 1); | ||
305 | @@ -XXX,XX +XXX,XX @@ static void check_on_the_fly_period_change(gconstpointer arg) | ||
306 | static void check_on_the_fly_freq_change(gconstpointer arg) | ||
307 | { | ||
308 | const uint8_t *policy = arg; | ||
309 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
310 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
311 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
312 | bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | ||
313 | |||
314 | triggered = false; | ||
315 | |||
316 | + ptimer_transaction_begin(ptimer); | ||
317 | ptimer_set_freq(ptimer, 500); | ||
318 | ptimer_set_limit(ptimer, 8, 1); | ||
319 | ptimer_run(ptimer, 1); | ||
320 | + ptimer_transaction_commit(ptimer); | ||
321 | |||
322 | qemu_clock_step(2000000 * 4 + 1); | ||
323 | |||
324 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 4 : 3); | ||
325 | g_assert_false(triggered); | ||
326 | |||
327 | + ptimer_transaction_begin(ptimer); | ||
328 | ptimer_set_freq(ptimer, 250); | ||
329 | + ptimer_transaction_commit(ptimer); | ||
330 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, no_round_down ? 4 : 3); | ||
331 | |||
332 | qemu_clock_step(2000000 * 4 + 1); | ||
333 | @@ -XXX,XX +XXX,XX @@ static void check_on_the_fly_freq_change(gconstpointer arg) | ||
334 | static void check_run_with_period_0(gconstpointer arg) | ||
335 | { | ||
336 | const uint8_t *policy = arg; | ||
337 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
338 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
339 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
340 | |||
341 | triggered = false; | ||
342 | |||
343 | + ptimer_transaction_begin(ptimer); | ||
344 | ptimer_set_count(ptimer, 99); | ||
345 | ptimer_run(ptimer, 1); | ||
346 | + ptimer_transaction_commit(ptimer); | ||
347 | |||
348 | qemu_clock_step(10 * NANOSECONDS_PER_SECOND); | ||
349 | |||
350 | @@ -XXX,XX +XXX,XX @@ static void check_run_with_period_0(gconstpointer arg) | ||
351 | static void check_run_with_delta_0(gconstpointer arg) | ||
352 | { | ||
353 | const uint8_t *policy = arg; | ||
354 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
355 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
356 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
357 | bool wrap_policy = (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); | ||
358 | bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); | ||
359 | bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD); | ||
360 | @@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg) | ||
361 | |||
362 | triggered = false; | ||
363 | |||
364 | + ptimer_transaction_begin(ptimer); | ||
365 | ptimer_set_period(ptimer, 2000000); | ||
366 | ptimer_set_limit(ptimer, 99, 0); | ||
367 | ptimer_run(ptimer, 1); | ||
368 | + ptimer_transaction_commit(ptimer); | ||
369 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, | ||
370 | no_immediate_reload ? 0 : 99); | ||
371 | |||
372 | @@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg) | ||
373 | g_assert_false(triggered); | ||
374 | } | ||
375 | |||
376 | + ptimer_transaction_begin(ptimer); | ||
377 | ptimer_set_count(ptimer, 99); | ||
378 | ptimer_run(ptimer, 1); | ||
379 | + ptimer_transaction_commit(ptimer); | ||
380 | } | ||
381 | |||
382 | qemu_clock_step(2000000 + 1); | ||
383 | @@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg) | ||
384 | |||
385 | triggered = false; | ||
386 | |||
387 | + ptimer_transaction_begin(ptimer); | ||
388 | ptimer_set_count(ptimer, 0); | ||
389 | ptimer_run(ptimer, 0); | ||
390 | + ptimer_transaction_commit(ptimer); | ||
391 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, | ||
392 | no_immediate_reload ? 0 : 99); | ||
393 | |||
394 | @@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg) | ||
395 | wrap_policy ? 0 : (no_round_down ? 99 : 98)); | ||
396 | g_assert_true(triggered); | ||
397 | |||
398 | + ptimer_transaction_begin(ptimer); | ||
399 | ptimer_stop(ptimer); | ||
400 | + ptimer_transaction_commit(ptimer); | ||
401 | ptimer_free(ptimer); | ||
402 | } | ||
403 | |||
404 | static void check_periodic_with_load_0(gconstpointer arg) | ||
405 | { | ||
406 | const uint8_t *policy = arg; | ||
407 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
408 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
409 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
410 | bool continuous_trigger = (*policy & PTIMER_POLICY_CONTINUOUS_TRIGGER); | ||
411 | bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); | ||
412 | bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT); | ||
413 | |||
414 | triggered = false; | ||
415 | |||
416 | + ptimer_transaction_begin(ptimer); | ||
417 | ptimer_set_period(ptimer, 2000000); | ||
418 | ptimer_run(ptimer, 0); | ||
419 | + ptimer_transaction_commit(ptimer); | ||
420 | |||
421 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0); | ||
422 | |||
423 | @@ -XXX,XX +XXX,XX @@ static void check_periodic_with_load_0(gconstpointer arg) | ||
424 | |||
425 | triggered = false; | ||
426 | |||
427 | + ptimer_transaction_begin(ptimer); | ||
428 | ptimer_set_count(ptimer, 10); | ||
429 | ptimer_run(ptimer, 0); | ||
430 | + ptimer_transaction_commit(ptimer); | ||
431 | |||
432 | qemu_clock_step(2000000 * 10 + 1); | ||
433 | |||
434 | @@ -XXX,XX +XXX,XX @@ static void check_periodic_with_load_0(gconstpointer arg) | ||
435 | g_assert_false(triggered); | ||
436 | } | ||
437 | |||
438 | + ptimer_transaction_begin(ptimer); | ||
439 | ptimer_stop(ptimer); | ||
440 | + ptimer_transaction_commit(ptimer); | ||
441 | ptimer_free(ptimer); | ||
442 | } | ||
443 | |||
444 | static void check_oneshot_with_load_0(gconstpointer arg) | ||
445 | { | ||
446 | const uint8_t *policy = arg; | ||
447 | - QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
448 | - ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
449 | + ptimer_state *ptimer = ptimer_init(ptimer_trigger, NULL, *policy); | ||
450 | bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); | ||
451 | bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT); | ||
452 | |||
453 | triggered = false; | ||
454 | |||
455 | + ptimer_transaction_begin(ptimer); | ||
456 | ptimer_set_period(ptimer, 2000000); | ||
457 | ptimer_run(ptimer, 1); | ||
458 | + ptimer_transaction_commit(ptimer); | ||
459 | |||
460 | g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0); | ||
461 | |||
462 | -- | 312 | -- |
463 | 2.20.1 | 313 | 2.20.1 |
464 | 314 | ||
465 | 315 | diff view generated by jsdifflib |
1 | The semihosting code needs accuss to the linux-user only | 1 | The macro draw_line_func is used only once; just expand it. |
---|---|---|---|
2 | TaskState pointer so it can set the semihosting errno per-thread | ||
3 | for linux-user mode. At the moment we do this by having some | ||
4 | ifdefs so that we define a 'ts' local in do_arm_semihosting() | ||
5 | which is either a real TaskState * or just a CPUARMState *, | ||
6 | depending on which mode we're compiling for. | ||
7 | |||
8 | This is awkward if we want to refactor do_arm_semihosting() | ||
9 | into other functions which might need to be passed the TaskState. | ||
10 | Restrict usage of the TaskState local by: | ||
11 | * making set_swi_errno() always take the CPUARMState pointer | ||
12 | and (for the linux-user version) get TaskState from that | ||
13 | * creating a new get_swi_errno() which reads the errno | ||
14 | * having the two semihosting calls which need the TaskState | ||
15 | for other purposes (SYS_GET_CMDLINE and SYS_HEAPINFO) | ||
16 | define a variable with scope restricted to just that code | ||
17 | 2 | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
20 | Message-id: 20190916141544.17540-6-peter.maydell@linaro.org | 5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
6 | Message-id: 20210215103215.4944-10-peter.maydell@linaro.org | ||
21 | --- | 7 | --- |
22 | target/arm/arm-semi.c | 111 ++++++++++++++++++++++++------------------ | 8 | hw/display/omap_lcdc.c | 4 +--- |
23 | 1 file changed, 63 insertions(+), 48 deletions(-) | 9 | 1 file changed, 1 insertion(+), 3 deletions(-) |
24 | 10 | ||
25 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 11 | diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c |
26 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/target/arm/arm-semi.c | 13 | --- a/hw/display/omap_lcdc.c |
28 | +++ b/target/arm/arm-semi.c | 14 | +++ b/hw/display/omap_lcdc.c |
29 | @@ -XXX,XX +XXX,XX @@ static GuestFD *get_guestfd(int guestfd) | 15 | @@ -XXX,XX +XXX,XX @@ static void omap_lcd_interrupts(struct omap_lcd_panel_s *s) |
30 | return gf; | 16 | qemu_irq_lower(s->irq); |
31 | } | 17 | } |
32 | 18 | ||
33 | -#ifdef CONFIG_USER_ONLY | 19 | -#define draw_line_func drawfn |
34 | -static inline uint32_t set_swi_errno(TaskState *ts, uint32_t code) | 20 | - |
35 | -{ | 21 | /* |
36 | - if (code == (uint32_t)-1) | 22 | * 2-bit colour |
37 | - ts->swi_errno = errno; | 23 | */ |
38 | - return code; | 24 | @@ -XXX,XX +XXX,XX @@ static void omap_update_display(void *opaque) |
39 | -} | ||
40 | -#else | ||
41 | +/* | ||
42 | + * The semihosting API has no concept of its errno being thread-safe, | ||
43 | + * as the API design predates SMP CPUs and was intended as a simple | ||
44 | + * real-hardware set of debug functionality. For QEMU, we make the | ||
45 | + * errno be per-thread in linux-user mode; in softmmu it is a simple | ||
46 | + * global, and we assume that the guest takes care of avoiding any races. | ||
47 | + */ | ||
48 | +#ifndef CONFIG_USER_ONLY | ||
49 | static target_ulong syscall_err; | ||
50 | |||
51 | +#include "exec/softmmu-semi.h" | ||
52 | +#endif | ||
53 | + | ||
54 | static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code) | ||
55 | { | 25 | { |
56 | if (code == (uint32_t)-1) { | 26 | struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque; |
57 | +#ifdef CONFIG_USER_ONLY | 27 | DisplaySurface *surface; |
58 | + CPUState *cs = env_cpu(env); | 28 | - draw_line_func draw_line; |
59 | + TaskState *ts = cs->opaque; | 29 | + drawfn draw_line; |
60 | + | 30 | int size, height, first, last; |
61 | + ts->swi_errno = errno; | 31 | int width, linesize, step, bpp, frame_offset; |
62 | +#else | 32 | hwaddr frame_base; |
63 | syscall_err = errno; | ||
64 | +#endif | ||
65 | } | ||
66 | return code; | ||
67 | } | ||
68 | |||
69 | -#include "exec/softmmu-semi.h" | ||
70 | +static inline uint32_t get_swi_errno(CPUARMState *env) | ||
71 | +{ | ||
72 | +#ifdef CONFIG_USER_ONLY | ||
73 | + CPUState *cs = env_cpu(env); | ||
74 | + TaskState *ts = cs->opaque; | ||
75 | + | ||
76 | + return ts->swi_errno; | ||
77 | +#else | ||
78 | + return syscall_err; | ||
79 | #endif | ||
80 | +} | ||
81 | |||
82 | static target_ulong arm_semi_syscall_len; | ||
83 | |||
84 | @@ -XXX,XX +XXX,XX @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, | ||
85 | if (is_a64(env)) { \ | ||
86 | if (get_user_u64(arg ## n, args + (n) * 8)) { \ | ||
87 | errno = EFAULT; \ | ||
88 | - return set_swi_errno(ts, -1); \ | ||
89 | + return set_swi_errno(env, -1); \ | ||
90 | } \ | ||
91 | } else { \ | ||
92 | if (get_user_u32(arg ## n, args + (n) * 4)) { \ | ||
93 | errno = EFAULT; \ | ||
94 | - return set_swi_errno(ts, -1); \ | ||
95 | + return set_swi_errno(env, -1); \ | ||
96 | } \ | ||
97 | } \ | ||
98 | } while (0) | ||
99 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
100 | int nr; | ||
101 | uint32_t ret; | ||
102 | uint32_t len; | ||
103 | -#ifdef CONFIG_USER_ONLY | ||
104 | - TaskState *ts = cs->opaque; | ||
105 | -#else | ||
106 | - CPUARMState *ts = env; | ||
107 | -#endif | ||
108 | GuestFD *gf; | ||
109 | |||
110 | if (is_a64(env)) { | ||
111 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
112 | s = lock_user_string(arg0); | ||
113 | if (!s) { | ||
114 | errno = EFAULT; | ||
115 | - return set_swi_errno(ts, -1); | ||
116 | + return set_swi_errno(env, -1); | ||
117 | } | ||
118 | if (arg1 >= 12) { | ||
119 | unlock_user(s, arg0, 0); | ||
120 | errno = EINVAL; | ||
121 | - return set_swi_errno(ts, -1); | ||
122 | + return set_swi_errno(env, -1); | ||
123 | } | ||
124 | |||
125 | guestfd = alloc_guestfd(); | ||
126 | if (guestfd < 0) { | ||
127 | unlock_user(s, arg0, 0); | ||
128 | errno = EMFILE; | ||
129 | - return set_swi_errno(ts, -1); | ||
130 | + return set_swi_errno(env, -1); | ||
131 | } | ||
132 | |||
133 | if (strcmp(s, ":tt") == 0) { | ||
134 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
135 | ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0, | ||
136 | (int)arg2+1, gdb_open_modeflags[arg1]); | ||
137 | } else { | ||
138 | - ret = set_swi_errno(ts, open(s, open_modeflags[arg1], 0644)); | ||
139 | + ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644)); | ||
140 | if (ret == (uint32_t)-1) { | ||
141 | dealloc_guestfd(guestfd); | ||
142 | } else { | ||
143 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
144 | gf = get_guestfd(arg0); | ||
145 | if (!gf) { | ||
146 | errno = EBADF; | ||
147 | - return set_swi_errno(ts, -1); | ||
148 | + return set_swi_errno(env, -1); | ||
149 | } | ||
150 | |||
151 | if (use_gdb_syscalls()) { | ||
152 | ret = arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); | ||
153 | } else { | ||
154 | - ret = set_swi_errno(ts, close(gf->hostfd)); | ||
155 | + ret = set_swi_errno(env, close(gf->hostfd)); | ||
156 | } | ||
157 | dealloc_guestfd(arg0); | ||
158 | return ret; | ||
159 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
160 | gf = get_guestfd(arg0); | ||
161 | if (!gf) { | ||
162 | errno = EBADF; | ||
163 | - return set_swi_errno(ts, -1); | ||
164 | + return set_swi_errno(env, -1); | ||
165 | } | ||
166 | |||
167 | if (use_gdb_syscalls()) { | ||
168 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
169 | /* Return bytes not written on error */ | ||
170 | return len; | ||
171 | } | ||
172 | - ret = set_swi_errno(ts, write(gf->hostfd, s, len)); | ||
173 | + ret = set_swi_errno(env, write(gf->hostfd, s, len)); | ||
174 | unlock_user(s, arg1, 0); | ||
175 | if (ret == (uint32_t)-1) { | ||
176 | ret = 0; | ||
177 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
178 | gf = get_guestfd(arg0); | ||
179 | if (!gf) { | ||
180 | errno = EBADF; | ||
181 | - return set_swi_errno(ts, -1); | ||
182 | + return set_swi_errno(env, -1); | ||
183 | } | ||
184 | |||
185 | if (use_gdb_syscalls()) { | ||
186 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
187 | return len; | ||
188 | } | ||
189 | do { | ||
190 | - ret = set_swi_errno(ts, read(gf->hostfd, s, len)); | ||
191 | + ret = set_swi_errno(env, read(gf->hostfd, s, len)); | ||
192 | } while (ret == -1 && errno == EINTR); | ||
193 | unlock_user(s, arg1, len); | ||
194 | if (ret == (uint32_t)-1) { | ||
195 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
196 | gf = get_guestfd(arg0); | ||
197 | if (!gf) { | ||
198 | errno = EBADF; | ||
199 | - return set_swi_errno(ts, -1); | ||
200 | + return set_swi_errno(env, -1); | ||
201 | } | ||
202 | |||
203 | if (use_gdb_syscalls()) { | ||
204 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
205 | gf = get_guestfd(arg0); | ||
206 | if (!gf) { | ||
207 | errno = EBADF; | ||
208 | - return set_swi_errno(ts, -1); | ||
209 | + return set_swi_errno(env, -1); | ||
210 | } | ||
211 | |||
212 | if (use_gdb_syscalls()) { | ||
213 | return arm_gdb_syscall(cpu, arm_semi_cb, "lseek,%x,%x,0", | ||
214 | gf->hostfd, arg1); | ||
215 | } else { | ||
216 | - ret = set_swi_errno(ts, lseek(gf->hostfd, arg1, SEEK_SET)); | ||
217 | + ret = set_swi_errno(env, lseek(gf->hostfd, arg1, SEEK_SET)); | ||
218 | if (ret == (uint32_t)-1) | ||
219 | return -1; | ||
220 | return 0; | ||
221 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
222 | gf = get_guestfd(arg0); | ||
223 | if (!gf) { | ||
224 | errno = EBADF; | ||
225 | - return set_swi_errno(ts, -1); | ||
226 | + return set_swi_errno(env, -1); | ||
227 | } | ||
228 | |||
229 | if (use_gdb_syscalls()) { | ||
230 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
231 | gf->hostfd, arm_flen_buf(cpu)); | ||
232 | } else { | ||
233 | struct stat buf; | ||
234 | - ret = set_swi_errno(ts, fstat(gf->hostfd, &buf)); | ||
235 | + ret = set_swi_errno(env, fstat(gf->hostfd, &buf)); | ||
236 | if (ret == (uint32_t)-1) | ||
237 | return -1; | ||
238 | return buf.st_size; | ||
239 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
240 | s = lock_user_string(arg0); | ||
241 | if (!s) { | ||
242 | errno = EFAULT; | ||
243 | - return set_swi_errno(ts, -1); | ||
244 | + return set_swi_errno(env, -1); | ||
245 | } | ||
246 | - ret = set_swi_errno(ts, remove(s)); | ||
247 | + ret = set_swi_errno(env, remove(s)); | ||
248 | unlock_user(s, arg0, 0); | ||
249 | } | ||
250 | return ret; | ||
251 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
252 | s2 = lock_user_string(arg2); | ||
253 | if (!s || !s2) { | ||
254 | errno = EFAULT; | ||
255 | - ret = set_swi_errno(ts, -1); | ||
256 | + ret = set_swi_errno(env, -1); | ||
257 | } else { | ||
258 | - ret = set_swi_errno(ts, rename(s, s2)); | ||
259 | + ret = set_swi_errno(env, rename(s, s2)); | ||
260 | } | ||
261 | if (s2) | ||
262 | unlock_user(s2, arg2, 0); | ||
263 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
264 | case TARGET_SYS_CLOCK: | ||
265 | return clock() / (CLOCKS_PER_SEC / 100); | ||
266 | case TARGET_SYS_TIME: | ||
267 | - return set_swi_errno(ts, time(NULL)); | ||
268 | + return set_swi_errno(env, time(NULL)); | ||
269 | case TARGET_SYS_SYSTEM: | ||
270 | GET_ARG(0); | ||
271 | GET_ARG(1); | ||
272 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
273 | s = lock_user_string(arg0); | ||
274 | if (!s) { | ||
275 | errno = EFAULT; | ||
276 | - return set_swi_errno(ts, -1); | ||
277 | + return set_swi_errno(env, -1); | ||
278 | } | ||
279 | - ret = set_swi_errno(ts, system(s)); | ||
280 | + ret = set_swi_errno(env, system(s)); | ||
281 | unlock_user(s, arg0, 0); | ||
282 | return ret; | ||
283 | } | ||
284 | case TARGET_SYS_ERRNO: | ||
285 | -#ifdef CONFIG_USER_ONLY | ||
286 | - return ts->swi_errno; | ||
287 | -#else | ||
288 | - return syscall_err; | ||
289 | -#endif | ||
290 | + return get_swi_errno(env); | ||
291 | case TARGET_SYS_GET_CMDLINE: | ||
292 | { | ||
293 | /* Build a command-line from the original argv. | ||
294 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
295 | int status = 0; | ||
296 | #if !defined(CONFIG_USER_ONLY) | ||
297 | const char *cmdline; | ||
298 | +#else | ||
299 | + TaskState *ts = cs->opaque; | ||
300 | #endif | ||
301 | GET_ARG(0); | ||
302 | GET_ARG(1); | ||
303 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
304 | if (output_size > input_size) { | ||
305 | /* Not enough space to store command-line arguments. */ | ||
306 | errno = E2BIG; | ||
307 | - return set_swi_errno(ts, -1); | ||
308 | + return set_swi_errno(env, -1); | ||
309 | } | ||
310 | |||
311 | /* Adjust the command-line length. */ | ||
312 | if (SET_ARG(1, output_size - 1)) { | ||
313 | /* Couldn't write back to argument block */ | ||
314 | errno = EFAULT; | ||
315 | - return set_swi_errno(ts, -1); | ||
316 | + return set_swi_errno(env, -1); | ||
317 | } | ||
318 | |||
319 | /* Lock the buffer on the ARM side. */ | ||
320 | output_buffer = lock_user(VERIFY_WRITE, arg0, output_size, 0); | ||
321 | if (!output_buffer) { | ||
322 | errno = EFAULT; | ||
323 | - return set_swi_errno(ts, -1); | ||
324 | + return set_swi_errno(env, -1); | ||
325 | } | ||
326 | |||
327 | /* Copy the command-line arguments. */ | ||
328 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
329 | if (copy_from_user(output_buffer, ts->info->arg_start, | ||
330 | output_size)) { | ||
331 | errno = EFAULT; | ||
332 | - status = set_swi_errno(ts, -1); | ||
333 | + status = set_swi_errno(env, -1); | ||
334 | goto out; | ||
335 | } | ||
336 | |||
337 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
338 | target_ulong retvals[4]; | ||
339 | target_ulong limit; | ||
340 | int i; | ||
341 | +#ifdef CONFIG_USER_ONLY | ||
342 | + TaskState *ts = cs->opaque; | ||
343 | +#endif | ||
344 | |||
345 | GET_ARG(0); | ||
346 | |||
347 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
348 | if (fail) { | ||
349 | /* Couldn't write back to argument block */ | ||
350 | errno = EFAULT; | ||
351 | - return set_swi_errno(ts, -1); | ||
352 | + return set_swi_errno(env, -1); | ||
353 | } | ||
354 | } | ||
355 | return 0; | ||
356 | -- | 33 | -- |
357 | 2.20.1 | 34 | 2.20.1 |
358 | 35 | ||
359 | 36 | diff view generated by jsdifflib |
1 | Currently for the semihosting calls which take a file descriptor | 1 | For a long time now the UI layer has guaranteed that the console |
---|---|---|---|
2 | (SYS_CLOSE, SYS_WRITE, SYS_READ, SYS_ISTTY, SYS_SEEK, SYS_FLEN) | 2 | surface is always 32 bits per pixel, RGB. The TCX code already |
3 | we have effectively two implementations, one for real host files | 3 | assumes 32bpp, but it still has some checks of is_surface_bgr() |
4 | and one for when we indirect via the gdbstub. We want to add a | 4 | in an attempt to support 32bpp BGR. is_surface_bgr() will always |
5 | third one to deal with the magic :semihosting-features file. | 5 | return false for the qemu_console_surface(), unless the display |
6 | device itself has deliberately created an alternate-format | ||
7 | surface via a function like qemu_create_displaysurface_from(). | ||
6 | 8 | ||
7 | Instead of having a three-way if statement in each of these | 9 | Drop the never-used BGR-handling code, and assert that we have |
8 | cases, factor out the implementation of the calls to separate | 10 | a 32-bit surface rather than just doing nothing if it isn't. |
9 | functions which we dispatch to via function pointers selected | ||
10 | via the GuestFDType for the guest fd. | ||
11 | |||
12 | In this commit, we set up the framework for the dispatch, | ||
13 | and convert the SYS_CLOSE call to use it. | ||
14 | 11 | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 13 | Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> |
17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
18 | Message-id: 20190916141544.17540-8-peter.maydell@linaro.org | 15 | Message-id: 20210215102149.20513-1-peter.maydell@linaro.org |
19 | --- | 16 | --- |
20 | target/arm/arm-semi.c | 44 ++++++++++++++++++++++++++++++++++++------- | 17 | hw/display/tcx.c | 31 ++++++++----------------------- |
21 | 1 file changed, 37 insertions(+), 7 deletions(-) | 18 | 1 file changed, 8 insertions(+), 23 deletions(-) |
22 | 19 | ||
23 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 20 | diff --git a/hw/display/tcx.c b/hw/display/tcx.c |
24 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/target/arm/arm-semi.c | 22 | --- a/hw/display/tcx.c |
26 | +++ b/target/arm/arm-semi.c | 23 | +++ b/hw/display/tcx.c |
27 | @@ -XXX,XX +XXX,XX @@ static int open_modeflags[12] = { | 24 | @@ -XXX,XX +XXX,XX @@ static int tcx_check_dirty(TCXState *s, DirtyBitmapSnapshot *snap, |
28 | typedef enum GuestFDType { | 25 | |
29 | GuestFDUnused = 0, | 26 | static void update_palette_entries(TCXState *s, int start, int end) |
30 | GuestFDHost = 1, | 27 | { |
31 | + GuestFDGDB = 2, | 28 | - DisplaySurface *surface = qemu_console_surface(s->con); |
32 | } GuestFDType; | 29 | int i; |
30 | |||
31 | for (i = start; i < end; i++) { | ||
32 | - if (is_surface_bgr(surface)) { | ||
33 | - s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); | ||
34 | - } else { | ||
35 | - s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); | ||
36 | - } | ||
37 | + s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); | ||
38 | } | ||
39 | tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); | ||
40 | } | ||
41 | @@ -XXX,XX +XXX,XX @@ static void tcx_draw_cursor32(TCXState *s1, uint8_t *d, | ||
42 | } | ||
33 | 43 | ||
34 | /* | 44 | /* |
35 | @@ -XXX,XX +XXX,XX @@ static GuestFD *do_get_guestfd(int guestfd) | 45 | - XXX Could be much more optimal: |
36 | /* | 46 | - * detect if line/page/whole screen is in 24 bit mode |
37 | * Associate the specified guest fd (which must have been | 47 | - * if destination is also BGR, use memcpy |
38 | * allocated via alloc_fd() and not previously used) with | 48 | - */ |
39 | - * the specified host fd. | 49 | + * XXX Could be much more optimal: |
40 | + * the specified host/gdb fd. | 50 | + * detect if line/page/whole screen is in 24 bit mode |
41 | */ | 51 | + */ |
42 | static void associate_guestfd(int guestfd, int hostfd) | 52 | static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, |
53 | const uint8_t *s, int width, | ||
54 | const uint32_t *cplane, | ||
55 | const uint32_t *s24) | ||
43 | { | 56 | { |
44 | GuestFD *gf = do_get_guestfd(guestfd); | 57 | - DisplaySurface *surface = qemu_console_surface(s1->con); |
45 | 58 | - int x, bgr, r, g, b; | |
46 | assert(gf); | 59 | + int x, r, g, b; |
47 | - gf->type = GuestFDHost; | 60 | uint8_t val, *p8; |
48 | + gf->type = use_gdb_syscalls() ? GuestFDGDB : GuestFDHost; | 61 | uint32_t *p = (uint32_t *)d; |
49 | gf->hostfd = hostfd; | 62 | uint32_t dval; |
50 | } | 63 | - bgr = is_surface_bgr(surface); |
51 | 64 | for(x = 0; x < width; x++, s++, s24++) { | |
52 | @@ -XXX,XX +XXX,XX @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, | 65 | if (be32_to_cpu(*cplane) & 0x03000000) { |
53 | return is_a64(env) ? env->xregs[0] : env->regs[0]; | 66 | /* 24-bit direct, BGR order */ |
54 | } | 67 | @@ -XXX,XX +XXX,XX @@ static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, |
55 | 68 | b = *p8++; | |
56 | +/* | 69 | g = *p8++; |
57 | + * Types for functions implementing various semihosting calls | 70 | r = *p8; |
58 | + * for specific types of guest file descriptor. These must all | 71 | - if (bgr) |
59 | + * do the work and return the required return value for the guest, | 72 | - dval = rgb_to_pixel32bgr(r, g, b); |
60 | + * setting the guest errno if appropriate. | 73 | - else |
61 | + */ | 74 | - dval = rgb_to_pixel32(r, g, b); |
62 | +typedef uint32_t sys_closefn(ARMCPU *cpu, GuestFD *gf); | 75 | + dval = rgb_to_pixel32(r, g, b); |
63 | + | 76 | } else { |
64 | +static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) | 77 | /* 8-bit pseudocolor */ |
65 | +{ | 78 | val = *s; |
66 | + CPUARMState *env = &cpu->env; | 79 | @@ -XXX,XX +XXX,XX @@ static void tcx_update_display(void *opaque) |
67 | + | 80 | int y, y_start, dd, ds; |
68 | + return set_swi_errno(env, close(gf->hostfd)); | 81 | uint8_t *d, *s; |
69 | +} | 82 | |
70 | + | 83 | - if (surface_bits_per_pixel(surface) != 32) { |
71 | +static uint32_t gdb_closefn(ARMCPU *cpu, GuestFD *gf) | 84 | - return; |
72 | +{ | 85 | - } |
73 | + return arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); | 86 | + assert(surface_bits_per_pixel(surface) == 32); |
74 | +} | 87 | |
75 | + | 88 | page = 0; |
76 | +typedef struct GuestFDFunctions { | 89 | y_start = -1; |
77 | + sys_closefn *closefn; | 90 | @@ -XXX,XX +XXX,XX @@ static void tcx24_update_display(void *opaque) |
78 | +} GuestFDFunctions; | 91 | uint8_t *d, *s; |
79 | + | 92 | uint32_t *cptr, *s24; |
80 | +static const GuestFDFunctions guestfd_fns[] = { | 93 | |
81 | + [GuestFDHost] = { | 94 | - if (surface_bits_per_pixel(surface) != 32) { |
82 | + .closefn = host_closefn, | 95 | - return; |
83 | + }, | 96 | - } |
84 | + [GuestFDGDB] = { | 97 | + assert(surface_bits_per_pixel(surface) == 32); |
85 | + .closefn = gdb_closefn, | 98 | |
86 | + }, | 99 | page = 0; |
87 | +}; | 100 | y_start = -1; |
88 | + | ||
89 | /* Read the input value from the argument block; fail the semihosting | ||
90 | * call if the memory read fails. | ||
91 | */ | ||
92 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
93 | return set_swi_errno(env, -1); | ||
94 | } | ||
95 | |||
96 | - if (use_gdb_syscalls()) { | ||
97 | - ret = arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); | ||
98 | - } else { | ||
99 | - ret = set_swi_errno(env, close(gf->hostfd)); | ||
100 | - } | ||
101 | + ret = guestfd_fns[gf->type].closefn(cpu, gf); | ||
102 | dealloc_guestfd(arg0); | ||
103 | return ret; | ||
104 | case TARGET_SYS_WRITEC: | ||
105 | -- | 101 | -- |
106 | 2.20.1 | 102 | 2.20.1 |
107 | 103 | ||
108 | 104 | diff view generated by jsdifflib |
1 | From: Joel Stanley <joel@jms.id.au> | 1 | The AN524 has a different SYSCLK frequency from the AN505 and AN521; |
---|---|---|---|
2 | make the SYSCLK frequency a field in the MPS2TZMachineClass rather | ||
3 | than a compile-time constant so we can support the AN524. | ||
2 | 4 | ||
3 | The AST2600 SDMC controller is slightly different from its predecessor | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | (DRAM training). Max memory is now 2G on the AST2600. | 6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20210215115138.20465-2-peter.maydell@linaro.org | ||
9 | --- | ||
10 | hw/arm/mps2-tz.c | 10 ++++++---- | ||
11 | 1 file changed, 6 insertions(+), 4 deletions(-) | ||
5 | 12 | ||
6 | Signed-off-by: Joel Stanley <joel@jms.id.au> | 13 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
7 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
8 | Message-id: 20190925143248.10000-10-clg@kaod.org | ||
9 | [clg: - improved commit log | ||
10 | - reworked model integration into new object class ] | ||
11 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | include/hw/misc/aspeed_sdmc.h | 1 + | ||
15 | hw/misc/aspeed_scu.c | 2 + | ||
16 | hw/misc/aspeed_sdmc.c | 82 +++++++++++++++++++++++++++++++++++ | ||
17 | 3 files changed, 85 insertions(+) | ||
18 | |||
19 | diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/include/hw/misc/aspeed_sdmc.h | 15 | --- a/hw/arm/mps2-tz.c |
22 | +++ b/include/hw/misc/aspeed_sdmc.h | 16 | +++ b/hw/arm/mps2-tz.c |
23 | @@ -XXX,XX +XXX,XX @@ | 17 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass { |
24 | #define ASPEED_SDMC(obj) OBJECT_CHECK(AspeedSDMCState, (obj), TYPE_ASPEED_SDMC) | 18 | MachineClass parent; |
25 | #define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400" | 19 | MPS2TZFPGAType fpga_type; |
26 | #define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500" | 20 | uint32_t scc_id; |
27 | +#define TYPE_ASPEED_2600_SDMC TYPE_ASPEED_SDMC "-ast2600" | 21 | + uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ |
28 | 22 | const char *armsse_type; | |
29 | #define ASPEED_SDMC_NR_REGS (0x174 >> 2) | ||
30 | |||
31 | diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/hw/misc/aspeed_scu.c | ||
34 | +++ b/hw/misc/aspeed_scu.c | ||
35 | @@ -XXX,XX +XXX,XX @@ | ||
36 | #define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84) | ||
37 | #define AST2600_CLK_STOP_CTRL2 TO_REG(0x90) | ||
38 | #define AST2600_CLK_STOP_CTR2L_CLR TO_REG(0x94) | ||
39 | +#define AST2600_SDRAM_HANDSHAKE TO_REG(0x100) | ||
40 | #define AST2600_HPLL_PARAM TO_REG(0x200) | ||
41 | #define AST2600_HPLL_EXT TO_REG(0x204) | ||
42 | #define AST2600_MPLL_EXT TO_REG(0x224) | ||
43 | @@ -XXX,XX +XXX,XX @@ static const uint32_t ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = { | ||
44 | [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC, | ||
45 | [AST2600_CLK_STOP_CTRL] = 0xEFF43E8B, | ||
46 | [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0, | ||
47 | + [AST2600_SDRAM_HANDSHAKE] = 0x00000040, /* SoC completed DRAM init */ | ||
48 | [AST2600_HPLL_PARAM] = 0x1000405F, | ||
49 | }; | 23 | }; |
50 | 24 | ||
51 | diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c | 25 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState { |
52 | index XXXXXXX..XXXXXXX 100644 | 26 | |
53 | --- a/hw/misc/aspeed_sdmc.c | 27 | OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) |
54 | +++ b/hw/misc/aspeed_sdmc.c | 28 | |
55 | @@ -XXX,XX +XXX,XX @@ | 29 | -/* Main SYSCLK frequency in Hz */ |
56 | /* Control/Status Register #1 (ast2500) */ | 30 | -#define SYSCLK_FRQ 20000000 |
57 | #define R_STATUS1 (0x60 / 4) | 31 | /* Slow 32Khz S32KCLK frequency in Hz */ |
58 | #define PHY_BUSY_STATE BIT(0) | 32 | #define S32KCLK_FRQ (32 * 1000) |
59 | +#define PHY_PLL_LOCK_STATUS BIT(4) | 33 | |
60 | 34 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, | |
61 | #define R_ECC_TEST_CTRL (0x70 / 4) | 35 | static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, |
62 | #define ECC_TEST_FINISHED BIT(12) | 36 | const char *name, hwaddr size) |
63 | @@ -XXX,XX +XXX,XX @@ | 37 | { |
64 | #define ASPEED_SDMC_AST2500_512MB 0x2 | 38 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
65 | #define ASPEED_SDMC_AST2500_1024MB 0x3 | 39 | CMSDKAPBUART *uart = opaque; |
66 | 40 | int i = uart - &mms->uart[0]; | |
67 | +#define ASPEED_SDMC_AST2600_256MB 0x0 | 41 | int rxirqno = i * 2; |
68 | +#define ASPEED_SDMC_AST2600_512MB 0x1 | 42 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, |
69 | +#define ASPEED_SDMC_AST2600_1024MB 0x2 | 43 | |
70 | +#define ASPEED_SDMC_AST2600_2048MB 0x3 | 44 | object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART); |
71 | + | 45 | qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); |
72 | #define ASPEED_SDMC_AST2500_READONLY_MASK \ | 46 | - qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); |
73 | (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \ | 47 | + qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->sysclk_frq); |
74 | ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT | \ | 48 | sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); |
75 | @@ -XXX,XX +XXX,XX @@ static int ast2500_rambits(AspeedSDMCState *s) | 49 | s = SYS_BUS_DEVICE(uart); |
76 | return ASPEED_SDMC_AST2500_512MB; | 50 | sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno)); |
51 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) | ||
52 | |||
53 | /* These clocks don't need migration because they are fixed-frequency */ | ||
54 | mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); | ||
55 | - clock_set_hz(mms->sysclk, SYSCLK_FRQ); | ||
56 | + clock_set_hz(mms->sysclk, mmc->sysclk_frq); | ||
57 | mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); | ||
58 | clock_set_hz(mms->s32kclk, S32KCLK_FRQ); | ||
59 | |||
60 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) | ||
61 | mmc->fpga_type = FPGA_AN505; | ||
62 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); | ||
63 | mmc->scc_id = 0x41045050; | ||
64 | + mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ | ||
65 | mmc->armsse_type = TYPE_IOTKIT; | ||
77 | } | 66 | } |
78 | 67 | ||
79 | +static int ast2600_rambits(AspeedSDMCState *s) | 68 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) |
80 | +{ | 69 | mmc->fpga_type = FPGA_AN521; |
81 | + switch (s->ram_size >> 20) { | 70 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); |
82 | + case 256: | 71 | mmc->scc_id = 0x41045210; |
83 | + return ASPEED_SDMC_AST2600_256MB; | 72 | + mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ |
84 | + case 512: | 73 | mmc->armsse_type = TYPE_SSE200; |
85 | + return ASPEED_SDMC_AST2600_512MB; | ||
86 | + case 1024: | ||
87 | + return ASPEED_SDMC_AST2600_1024MB; | ||
88 | + case 2048: | ||
89 | + return ASPEED_SDMC_AST2600_2048MB; | ||
90 | + default: | ||
91 | + break; | ||
92 | + } | ||
93 | + | ||
94 | + /* use a common default */ | ||
95 | + warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 512M", | ||
96 | + s->ram_size); | ||
97 | + s->ram_size = 512 << 20; | ||
98 | + return ASPEED_SDMC_AST2600_512MB; | ||
99 | +} | ||
100 | + | ||
101 | static void aspeed_sdmc_reset(DeviceState *dev) | ||
102 | { | ||
103 | AspeedSDMCState *s = ASPEED_SDMC(dev); | ||
104 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_2500_sdmc_info = { | ||
105 | .class_init = aspeed_2500_sdmc_class_init, | ||
106 | }; | ||
107 | |||
108 | +static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) | ||
109 | +{ | ||
110 | + uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(3) | | ||
111 | + ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | | ||
112 | + ASPEED_SDMC_DRAM_SIZE(ast2600_rambits(s)); | ||
113 | + | ||
114 | + /* Make sure readonly bits are kept (use ast2500 mask) */ | ||
115 | + data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; | ||
116 | + | ||
117 | + return data | fixed_conf; | ||
118 | +} | ||
119 | + | ||
120 | +static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg, | ||
121 | + uint32_t data) | ||
122 | +{ | ||
123 | + switch (reg) { | ||
124 | + case R_CONF: | ||
125 | + data = aspeed_2600_sdmc_compute_conf(s, data); | ||
126 | + break; | ||
127 | + case R_STATUS1: | ||
128 | + /* Will never return 'busy'. 'lock status' is always set */ | ||
129 | + data &= ~PHY_BUSY_STATE; | ||
130 | + data |= PHY_PLL_LOCK_STATUS; | ||
131 | + break; | ||
132 | + case R_ECC_TEST_CTRL: | ||
133 | + /* Always done, always happy */ | ||
134 | + data |= ECC_TEST_FINISHED; | ||
135 | + data &= ~ECC_TEST_FAIL; | ||
136 | + break; | ||
137 | + default: | ||
138 | + break; | ||
139 | + } | ||
140 | + | ||
141 | + s->regs[reg] = data; | ||
142 | +} | ||
143 | + | ||
144 | +static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data) | ||
145 | +{ | ||
146 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
147 | + AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); | ||
148 | + | ||
149 | + dc->desc = "ASPEED 2600 SDRAM Memory Controller"; | ||
150 | + asc->max_ram_size = 2048 << 20; | ||
151 | + asc->compute_conf = aspeed_2600_sdmc_compute_conf; | ||
152 | + asc->write = aspeed_2600_sdmc_write; | ||
153 | +} | ||
154 | + | ||
155 | +static const TypeInfo aspeed_2600_sdmc_info = { | ||
156 | + .name = TYPE_ASPEED_2600_SDMC, | ||
157 | + .parent = TYPE_ASPEED_SDMC, | ||
158 | + .class_init = aspeed_2600_sdmc_class_init, | ||
159 | +}; | ||
160 | + | ||
161 | static void aspeed_sdmc_register_types(void) | ||
162 | { | ||
163 | type_register_static(&aspeed_sdmc_info); | ||
164 | type_register_static(&aspeed_2400_sdmc_info); | ||
165 | type_register_static(&aspeed_2500_sdmc_info); | ||
166 | + type_register_static(&aspeed_2600_sdmc_info); | ||
167 | } | 74 | } |
168 | 75 | ||
169 | type_init(aspeed_sdmc_register_types); | ||
170 | -- | 76 | -- |
171 | 2.20.1 | 77 | 2.20.1 |
172 | 78 | ||
173 | 79 | diff view generated by jsdifflib |
1 | From: Joel Stanley <joel@jms.id.au> | 1 | Currently the MPS2 SCC device implements a fixed number of OSCCLK |
---|---|---|---|
2 | values (3). The variant of this device in the MPS3 AN524 board has 6 | ||
3 | OSCCLK values. Switch to using a PROP_ARRAY, which allows board code | ||
4 | to specify how large the OSCCLK array should be as well as its | ||
5 | values. | ||
2 | 6 | ||
3 | The SCU controller on the AST2600 SoC has extra registers. Increase | 7 | With a variable-length property array, the SCC no longer specifies |
4 | the number of regs of the model and introduce a new field in the class | 8 | default values for the OSCCLKs, so we must set them explicitly in the |
5 | to customize the MemoryRegion operations depending on the SoC model. | 9 | board code. This defaults are actually incorrect for the an521 and |
10 | an505; we will correct this bug in a following patch. | ||
6 | 11 | ||
7 | Signed-off-by: Joel Stanley <joel@jms.id.au> | 12 | This is a migration compatibility break for all the mps boards. |
8 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 13 | |
9 | Message-id: 20190925143248.10000-4-clg@kaod.org | ||
10 | [clg: - improved commit log | ||
11 | - changed vmstate version | ||
12 | - reworked model integration into new object class | ||
13 | - included AST2600_HPLL_PARAM value ] | ||
14 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
17 | Message-id: 20210215115138.20465-3-peter.maydell@linaro.org | ||
16 | --- | 18 | --- |
17 | include/hw/misc/aspeed_scu.h | 7 +- | 19 | include/hw/misc/mps2-scc.h | 7 +++---- |
18 | hw/misc/aspeed_scu.c | 192 +++++++++++++++++++++++++++++++++-- | 20 | hw/arm/mps2-tz.c | 5 +++++ |
19 | 2 files changed, 191 insertions(+), 8 deletions(-) | 21 | hw/arm/mps2.c | 5 +++++ |
22 | hw/misc/mps2-scc.c | 24 +++++++++++++----------- | ||
23 | 4 files changed, 26 insertions(+), 15 deletions(-) | ||
20 | 24 | ||
21 | diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h | 25 | diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h |
22 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/include/hw/misc/aspeed_scu.h | 27 | --- a/include/hw/misc/mps2-scc.h |
24 | +++ b/include/hw/misc/aspeed_scu.h | 28 | +++ b/include/hw/misc/mps2-scc.h |
25 | @@ -XXX,XX +XXX,XX @@ | 29 | @@ -XXX,XX +XXX,XX @@ |
26 | #define ASPEED_SCU(obj) OBJECT_CHECK(AspeedSCUState, (obj), TYPE_ASPEED_SCU) | 30 | #define TYPE_MPS2_SCC "mps2-scc" |
27 | #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400" | 31 | OBJECT_DECLARE_SIMPLE_TYPE(MPS2SCC, MPS2_SCC) |
28 | #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500" | 32 | |
29 | +#define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600" | 33 | -#define NUM_OSCCLK 3 |
30 | 34 | - | |
31 | #define ASPEED_SCU_NR_REGS (0x1A8 >> 2) | 35 | struct MPS2SCC { |
32 | +#define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2) | ||
33 | |||
34 | typedef struct AspeedSCUState { | ||
35 | /*< private >*/ | 36 | /*< private >*/ |
36 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSCUState { | 37 | SysBusDevice parent_obj; |
37 | /*< public >*/ | 38 | @@ -XXX,XX +XXX,XX @@ struct MPS2SCC { |
38 | MemoryRegion iomem; | 39 | uint32_t dll; |
39 | 40 | uint32_t aid; | |
40 | - uint32_t regs[ASPEED_SCU_NR_REGS]; | 41 | uint32_t id; |
41 | + uint32_t regs[ASPEED_AST2600_SCU_NR_REGS]; | 42 | - uint32_t oscclk[NUM_OSCCLK]; |
42 | uint32_t silicon_rev; | 43 | - uint32_t oscclk_reset[NUM_OSCCLK]; |
43 | uint32_t hw_strap1; | 44 | + uint32_t num_oscclk; |
44 | uint32_t hw_strap2; | 45 | + uint32_t *oscclk; |
45 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSCUState { | 46 | + uint32_t *oscclk_reset; |
46 | #define AST2400_A1_SILICON_REV 0x02010303U | 47 | }; |
47 | #define AST2500_A0_SILICON_REV 0x04000303U | 48 | |
48 | #define AST2500_A1_SILICON_REV 0x04010303U | 49 | #endif |
49 | +#define AST2600_A0_SILICON_REV 0x05000303U | 50 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
50 | |||
51 | #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) | ||
52 | |||
53 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSCUClass { | ||
54 | const uint32_t *resets; | ||
55 | uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg); | ||
56 | uint32_t apb_divider; | ||
57 | + uint32_t nr_regs; | ||
58 | + const MemoryRegionOps *ops; | ||
59 | } AspeedSCUClass; | ||
60 | |||
61 | #define ASPEED_SCU_PROT_KEY 0x1688A8A8 | ||
62 | diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c | ||
63 | index XXXXXXX..XXXXXXX 100644 | 51 | index XXXXXXX..XXXXXXX 100644 |
64 | --- a/hw/misc/aspeed_scu.c | 52 | --- a/hw/arm/mps2-tz.c |
65 | +++ b/hw/misc/aspeed_scu.c | 53 | +++ b/hw/arm/mps2-tz.c |
66 | @@ -XXX,XX +XXX,XX @@ | 54 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, |
67 | #define BMC_REV TO_REG(0x19C) | 55 | qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); |
68 | #define BMC_DEV_ID TO_REG(0x1A4) | 56 | qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); |
69 | 57 | qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); | |
70 | +#define AST2600_PROT_KEY TO_REG(0x00) | 58 | + /* This will need to be per-FPGA image eventually */ |
71 | +#define AST2600_SILICON_REV TO_REG(0x04) | 59 | + qdev_prop_set_uint32(sccdev, "len-oscclk", 3); |
72 | +#define AST2600_SILICON_REV2 TO_REG(0x14) | 60 | + qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000); |
73 | +#define AST2600_SYS_RST_CTRL TO_REG(0x40) | 61 | + qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000); |
74 | +#define AST2600_SYS_RST_CTRL_CLR TO_REG(0x44) | 62 | + qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); |
75 | +#define AST2600_SYS_RST_CTRL2 TO_REG(0x50) | 63 | sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); |
76 | +#define AST2600_SYS_RST_CTRL2_CLR TO_REG(0x54) | 64 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); |
77 | +#define AST2600_CLK_STOP_CTRL TO_REG(0x80) | 65 | } |
78 | +#define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84) | 66 | diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c |
79 | +#define AST2600_CLK_STOP_CTRL2 TO_REG(0x90) | 67 | index XXXXXXX..XXXXXXX 100644 |
80 | +#define AST2600_CLK_STOP_CTR2L_CLR TO_REG(0x94) | 68 | --- a/hw/arm/mps2.c |
81 | +#define AST2600_HPLL_PARAM TO_REG(0x200) | 69 | +++ b/hw/arm/mps2.c |
82 | +#define AST2600_HPLL_EXT TO_REG(0x204) | 70 | @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) |
83 | +#define AST2600_MPLL_EXT TO_REG(0x224) | 71 | qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); |
84 | +#define AST2600_EPLL_EXT TO_REG(0x244) | 72 | qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); |
85 | +#define AST2600_CLK_SEL TO_REG(0x300) | 73 | qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); |
86 | +#define AST2600_CLK_SEL2 TO_REG(0x304) | 74 | + /* All these FPGA images have the same OSCCLK configuration */ |
87 | +#define AST2600_CLK_SEL3 TO_REG(0x310) | 75 | + qdev_prop_set_uint32(sccdev, "len-oscclk", 3); |
88 | +#define AST2600_HW_STRAP1 TO_REG(0x500) | 76 | + qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000); |
89 | +#define AST2600_HW_STRAP1_CLR TO_REG(0x504) | 77 | + qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000); |
90 | +#define AST2600_HW_STRAP1_PROT TO_REG(0x508) | 78 | + qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); |
91 | +#define AST2600_HW_STRAP2 TO_REG(0x510) | 79 | sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal); |
92 | +#define AST2600_HW_STRAP2_CLR TO_REG(0x514) | 80 | sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000); |
93 | +#define AST2600_HW_STRAP2_PROT TO_REG(0x518) | 81 | object_initialize_child(OBJECT(mms), "fpgaio", |
94 | +#define AST2600_RNG_CTRL TO_REG(0x524) | 82 | diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c |
95 | +#define AST2600_RNG_DATA TO_REG(0x540) | 83 | index XXXXXXX..XXXXXXX 100644 |
84 | --- a/hw/misc/mps2-scc.c | ||
85 | +++ b/hw/misc/mps2-scc.c | ||
86 | @@ -XXX,XX +XXX,XX @@ static bool scc_cfg_write(MPS2SCC *s, unsigned function, | ||
87 | { | ||
88 | trace_mps2_scc_cfg_write(function, device, value); | ||
89 | |||
90 | - if (function != 1 || device >= NUM_OSCCLK) { | ||
91 | + if (function != 1 || device >= s->num_oscclk) { | ||
92 | qemu_log_mask(LOG_GUEST_ERROR, | ||
93 | "MPS2 SCC config write: bad function %d device %d\n", | ||
94 | function, device); | ||
95 | @@ -XXX,XX +XXX,XX @@ static bool scc_cfg_write(MPS2SCC *s, unsigned function, | ||
96 | static bool scc_cfg_read(MPS2SCC *s, unsigned function, | ||
97 | unsigned device, uint32_t *value) | ||
98 | { | ||
99 | - if (function != 1 || device >= NUM_OSCCLK) { | ||
100 | + if (function != 1 || device >= s->num_oscclk) { | ||
101 | qemu_log_mask(LOG_GUEST_ERROR, | ||
102 | "MPS2 SCC config read: bad function %d device %d\n", | ||
103 | function, device); | ||
104 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_reset(DeviceState *dev) | ||
105 | s->cfgctrl = 0x100000; | ||
106 | s->cfgstat = 0; | ||
107 | s->dll = 0xffff0001; | ||
108 | - for (i = 0; i < NUM_OSCCLK; i++) { | ||
109 | + for (i = 0; i < s->num_oscclk; i++) { | ||
110 | s->oscclk[i] = s->oscclk_reset[i]; | ||
111 | } | ||
112 | for (i = 0; i < ARRAY_SIZE(s->led); i++) { | ||
113 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_realize(DeviceState *dev, Error **errp) | ||
114 | LED_COLOR_GREEN, name); | ||
115 | g_free(name); | ||
116 | } | ||
96 | + | 117 | + |
97 | +#define AST2600_CLK TO_REG(0x40) | 118 | + s->oscclk = g_new0(uint32_t, s->num_oscclk); |
98 | + | 119 | } |
99 | #define SCU_IO_REGION_SIZE 0x1000 | 120 | |
100 | 121 | static const VMStateDescription mps2_scc_vmstate = { | |
101 | static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = { | 122 | .name = "mps2-scc", |
102 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size) | ||
103 | AspeedSCUState *s = ASPEED_SCU(opaque); | ||
104 | int reg = TO_REG(offset); | ||
105 | |||
106 | - if (reg >= ARRAY_SIZE(s->regs)) { | ||
107 | + if (reg >= ASPEED_SCU_NR_REGS) { | ||
108 | qemu_log_mask(LOG_GUEST_ERROR, | ||
109 | "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", | ||
110 | __func__, offset); | ||
111 | @@ -XXX,XX +XXX,XX @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data, | ||
112 | AspeedSCUState *s = ASPEED_SCU(opaque); | ||
113 | int reg = TO_REG(offset); | ||
114 | |||
115 | - if (reg >= ARRAY_SIZE(s->regs)) { | ||
116 | + if (reg >= ASPEED_SCU_NR_REGS) { | ||
117 | qemu_log_mask(LOG_GUEST_ERROR, | ||
118 | "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", | ||
119 | __func__, offset); | ||
120 | @@ -XXX,XX +XXX,XX @@ static void aspeed_scu_reset(DeviceState *dev) | ||
121 | AspeedSCUState *s = ASPEED_SCU(dev); | ||
122 | AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); | ||
123 | |||
124 | - memcpy(s->regs, asc->resets, sizeof(s->regs)); | ||
125 | + memcpy(s->regs, asc->resets, asc->nr_regs * 4); | ||
126 | s->regs[SILICON_REV] = s->silicon_rev; | ||
127 | s->regs[HW_STRAP1] = s->hw_strap1; | ||
128 | s->regs[HW_STRAP2] = s->hw_strap2; | ||
129 | @@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_silicon_revs[] = { | ||
130 | AST2400_A1_SILICON_REV, | ||
131 | AST2500_A0_SILICON_REV, | ||
132 | AST2500_A1_SILICON_REV, | ||
133 | + AST2600_A0_SILICON_REV, | ||
134 | }; | ||
135 | |||
136 | bool is_supported_silicon_rev(uint32_t silicon_rev) | ||
137 | @@ -XXX,XX +XXX,XX @@ static void aspeed_scu_realize(DeviceState *dev, Error **errp) | ||
138 | { | ||
139 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
140 | AspeedSCUState *s = ASPEED_SCU(dev); | ||
141 | + AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); | ||
142 | |||
143 | if (!is_supported_silicon_rev(s->silicon_rev)) { | ||
144 | error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, | ||
145 | @@ -XXX,XX +XXX,XX @@ static void aspeed_scu_realize(DeviceState *dev, Error **errp) | ||
146 | return; | ||
147 | } | ||
148 | |||
149 | - memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_scu_ops, s, | ||
150 | + memory_region_init_io(&s->iomem, OBJECT(s), asc->ops, s, | ||
151 | TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE); | ||
152 | |||
153 | sysbus_init_mmio(sbd, &s->iomem); | ||
154 | @@ -XXX,XX +XXX,XX @@ static void aspeed_scu_realize(DeviceState *dev, Error **errp) | ||
155 | |||
156 | static const VMStateDescription vmstate_aspeed_scu = { | ||
157 | .name = "aspeed.scu", | ||
158 | - .version_id = 1, | 123 | - .version_id = 1, |
159 | - .minimum_version_id = 1, | 124 | - .minimum_version_id = 1, |
160 | + .version_id = 2, | 125 | + .version_id = 2, |
161 | + .minimum_version_id = 2, | 126 | + .minimum_version_id = 2, |
162 | .fields = (VMStateField[]) { | 127 | .fields = (VMStateField[]) { |
163 | - VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_SCU_NR_REGS), | 128 | VMSTATE_UINT32(cfg0, MPS2SCC), |
164 | + VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_AST2600_SCU_NR_REGS), | 129 | VMSTATE_UINT32(cfg1, MPS2SCC), |
130 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription mps2_scc_vmstate = { | ||
131 | VMSTATE_UINT32(cfgctrl, MPS2SCC), | ||
132 | VMSTATE_UINT32(cfgstat, MPS2SCC), | ||
133 | VMSTATE_UINT32(dll, MPS2SCC), | ||
134 | - VMSTATE_UINT32_ARRAY(oscclk, MPS2SCC, NUM_OSCCLK), | ||
135 | + VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk, | ||
136 | + 0, vmstate_info_uint32, uint32_t), | ||
165 | VMSTATE_END_OF_LIST() | 137 | VMSTATE_END_OF_LIST() |
166 | } | 138 | } |
167 | }; | 139 | }; |
168 | @@ -XXX,XX +XXX,XX @@ static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data) | 140 | @@ -XXX,XX +XXX,XX @@ static Property mps2_scc_properties[] = { |
169 | asc->resets = ast2400_a0_resets; | 141 | DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0), |
170 | asc->calc_hpll = aspeed_2400_scu_calc_hpll; | 142 | DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0), |
171 | asc->apb_divider = 2; | 143 | DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0), |
172 | + asc->nr_regs = ASPEED_SCU_NR_REGS; | 144 | - /* These are the initial settings for the source clocks on the board. |
173 | + asc->ops = &aspeed_scu_ops; | 145 | + /* |
174 | } | 146 | + * These are the initial settings for the source clocks on the board. |
175 | 147 | * In hardware they can be configured via a config file read by the | |
176 | static const TypeInfo aspeed_2400_scu_info = { | 148 | * motherboard configuration controller to suit the FPGA image. |
177 | @@ -XXX,XX +XXX,XX @@ static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data) | 149 | - * These default values are used by most of the standard FPGA images. |
178 | asc->resets = ast2500_a1_resets; | 150 | */ |
179 | asc->calc_hpll = aspeed_2500_scu_calc_hpll; | 151 | - DEFINE_PROP_UINT32("oscclk0", MPS2SCC, oscclk_reset[0], 50000000), |
180 | asc->apb_divider = 4; | 152 | - DEFINE_PROP_UINT32("oscclk1", MPS2SCC, oscclk_reset[1], 24576000), |
181 | + asc->nr_regs = ASPEED_SCU_NR_REGS; | 153 | - DEFINE_PROP_UINT32("oscclk2", MPS2SCC, oscclk_reset[2], 25000000), |
182 | + asc->ops = &aspeed_scu_ops; | 154 | + DEFINE_PROP_ARRAY("oscclk", MPS2SCC, num_oscclk, oscclk_reset, |
183 | } | 155 | + qdev_prop_uint32, uint32_t), |
184 | 156 | DEFINE_PROP_END_OF_LIST(), | |
185 | static const TypeInfo aspeed_2500_scu_info = { | ||
186 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_2500_scu_info = { | ||
187 | .class_init = aspeed_2500_scu_class_init, | ||
188 | }; | 157 | }; |
189 | 158 | ||
190 | +static uint64_t aspeed_ast2600_scu_read(void *opaque, hwaddr offset, | ||
191 | + unsigned size) | ||
192 | +{ | ||
193 | + AspeedSCUState *s = ASPEED_SCU(opaque); | ||
194 | + int reg = TO_REG(offset); | ||
195 | + | ||
196 | + if (reg >= ASPEED_AST2600_SCU_NR_REGS) { | ||
197 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
198 | + "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", | ||
199 | + __func__, offset); | ||
200 | + return 0; | ||
201 | + } | ||
202 | + | ||
203 | + switch (reg) { | ||
204 | + case AST2600_HPLL_EXT: | ||
205 | + case AST2600_EPLL_EXT: | ||
206 | + case AST2600_MPLL_EXT: | ||
207 | + /* PLLs are always "locked" */ | ||
208 | + return s->regs[reg] | BIT(31); | ||
209 | + case AST2600_RNG_DATA: | ||
210 | + /* | ||
211 | + * On hardware, RNG_DATA works regardless of the state of the | ||
212 | + * enable bit in RNG_CTRL | ||
213 | + * | ||
214 | + * TODO: Check this is true for ast2600 | ||
215 | + */ | ||
216 | + s->regs[AST2600_RNG_DATA] = aspeed_scu_get_random(); | ||
217 | + break; | ||
218 | + } | ||
219 | + | ||
220 | + return s->regs[reg]; | ||
221 | +} | ||
222 | + | ||
223 | +static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, uint64_t data, | ||
224 | + unsigned size) | ||
225 | +{ | ||
226 | + AspeedSCUState *s = ASPEED_SCU(opaque); | ||
227 | + int reg = TO_REG(offset); | ||
228 | + | ||
229 | + if (reg >= ASPEED_AST2600_SCU_NR_REGS) { | ||
230 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
231 | + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", | ||
232 | + __func__, offset); | ||
233 | + return; | ||
234 | + } | ||
235 | + | ||
236 | + if (reg > PROT_KEY && !s->regs[PROT_KEY]) { | ||
237 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); | ||
238 | + } | ||
239 | + | ||
240 | + trace_aspeed_scu_write(offset, size, data); | ||
241 | + | ||
242 | + switch (reg) { | ||
243 | + case AST2600_PROT_KEY: | ||
244 | + s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0; | ||
245 | + return; | ||
246 | + case AST2600_HW_STRAP1: | ||
247 | + case AST2600_HW_STRAP2: | ||
248 | + if (s->regs[reg + 2]) { | ||
249 | + return; | ||
250 | + } | ||
251 | + /* fall through */ | ||
252 | + case AST2600_SYS_RST_CTRL: | ||
253 | + case AST2600_SYS_RST_CTRL2: | ||
254 | + /* W1S (Write 1 to set) registers */ | ||
255 | + s->regs[reg] |= data; | ||
256 | + return; | ||
257 | + case AST2600_SYS_RST_CTRL_CLR: | ||
258 | + case AST2600_SYS_RST_CTRL2_CLR: | ||
259 | + case AST2600_HW_STRAP1_CLR: | ||
260 | + case AST2600_HW_STRAP2_CLR: | ||
261 | + /* W1C (Write 1 to clear) registers */ | ||
262 | + s->regs[reg] &= ~data; | ||
263 | + return; | ||
264 | + | ||
265 | + case AST2600_RNG_DATA: | ||
266 | + case AST2600_SILICON_REV: | ||
267 | + case AST2600_SILICON_REV2: | ||
268 | + /* Add read only registers here */ | ||
269 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
270 | + "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", | ||
271 | + __func__, offset); | ||
272 | + return; | ||
273 | + } | ||
274 | + | ||
275 | + s->regs[reg] = data; | ||
276 | +} | ||
277 | + | ||
278 | +static const MemoryRegionOps aspeed_ast2600_scu_ops = { | ||
279 | + .read = aspeed_ast2600_scu_read, | ||
280 | + .write = aspeed_ast2600_scu_write, | ||
281 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
282 | + .valid.min_access_size = 4, | ||
283 | + .valid.max_access_size = 4, | ||
284 | + .valid.unaligned = false, | ||
285 | +}; | ||
286 | + | ||
287 | +static const uint32_t ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = { | ||
288 | + [AST2600_SILICON_REV] = AST2600_SILICON_REV, | ||
289 | + [AST2600_SILICON_REV2] = AST2600_SILICON_REV, | ||
290 | + [AST2600_SYS_RST_CTRL] = 0xF7CFFEDC | 0x100, | ||
291 | + [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC, | ||
292 | + [AST2600_CLK_STOP_CTRL] = 0xEFF43E8B, | ||
293 | + [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0, | ||
294 | + [AST2600_HPLL_PARAM] = 0x1000405F, | ||
295 | +}; | ||
296 | + | ||
297 | +static void aspeed_ast2600_scu_reset(DeviceState *dev) | ||
298 | +{ | ||
299 | + AspeedSCUState *s = ASPEED_SCU(dev); | ||
300 | + AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); | ||
301 | + | ||
302 | + memcpy(s->regs, asc->resets, asc->nr_regs * 4); | ||
303 | + | ||
304 | + s->regs[AST2600_SILICON_REV] = s->silicon_rev; | ||
305 | + s->regs[AST2600_SILICON_REV2] = s->silicon_rev; | ||
306 | + s->regs[AST2600_HW_STRAP1] = s->hw_strap1; | ||
307 | + s->regs[AST2600_HW_STRAP2] = s->hw_strap2; | ||
308 | + s->regs[PROT_KEY] = s->hw_prot_key; | ||
309 | +} | ||
310 | + | ||
311 | +static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data) | ||
312 | +{ | ||
313 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
314 | + AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); | ||
315 | + | ||
316 | + dc->desc = "ASPEED 2600 System Control Unit"; | ||
317 | + dc->reset = aspeed_ast2600_scu_reset; | ||
318 | + asc->resets = ast2600_a0_resets; | ||
319 | + asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */ | ||
320 | + asc->apb_divider = 4; | ||
321 | + asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS; | ||
322 | + asc->ops = &aspeed_ast2600_scu_ops; | ||
323 | +} | ||
324 | + | ||
325 | +static const TypeInfo aspeed_2600_scu_info = { | ||
326 | + .name = TYPE_ASPEED_2600_SCU, | ||
327 | + .parent = TYPE_ASPEED_SCU, | ||
328 | + .instance_size = sizeof(AspeedSCUState), | ||
329 | + .class_init = aspeed_2600_scu_class_init, | ||
330 | +}; | ||
331 | + | ||
332 | static void aspeed_scu_register_types(void) | ||
333 | { | ||
334 | type_register_static(&aspeed_scu_info); | ||
335 | type_register_static(&aspeed_2400_scu_info); | ||
336 | type_register_static(&aspeed_2500_scu_info); | ||
337 | + type_register_static(&aspeed_2600_scu_info); | ||
338 | } | ||
339 | |||
340 | type_init(aspeed_scu_register_types); | ||
341 | -- | 159 | -- |
342 | 2.20.1 | 160 | 2.20.1 |
343 | 161 | ||
344 | 162 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | We were previously using the default OSCCLK settings, which are |
---|---|---|---|
2 | correct for the older MPS2 boards (mps2-an385, mps2-an386, | ||
3 | mps2-an500, mps2-an511), but wrong for the mps2-an505 and mps2-511 | ||
4 | implemented in mps2-tz.c. Now we're setting the values explicitly we | ||
5 | can fix them to be correct. | ||
2 | 6 | ||
3 | IEC binary prefixes ease code review: the unit is explicit. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
8 | Reviewed-by: Cleber Rosa <crosa@redhat.com> | ||
9 | Message-id: 20190926173428.10713-2-f4bug@amsat.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20210215115138.20465-4-peter.maydell@linaro.org | ||
11 | --- | 11 | --- |
12 | hw/arm/raspi.c | 4 ++-- | 12 | hw/arm/mps2-tz.c | 4 ++-- |
13 | 1 file changed, 2 insertions(+), 2 deletions(-) | 13 | 1 file changed, 2 insertions(+), 2 deletions(-) |
14 | 14 | ||
15 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | 15 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/raspi.c | 17 | --- a/hw/arm/mps2-tz.c |
18 | +++ b/hw/arm/raspi.c | 18 | +++ b/hw/arm/mps2-tz.c |
19 | @@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc) | 19 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, |
20 | mc->max_cpus = BCM283X_NCPUS; | 20 | qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); |
21 | mc->min_cpus = BCM283X_NCPUS; | 21 | /* This will need to be per-FPGA image eventually */ |
22 | mc->default_cpus = BCM283X_NCPUS; | 22 | qdev_prop_set_uint32(sccdev, "len-oscclk", 3); |
23 | - mc->default_ram_size = 1024 * 1024 * 1024; | 23 | - qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000); |
24 | + mc->default_ram_size = 1 * GiB; | 24 | - qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000); |
25 | mc->ignore_memory_transaction_failures = true; | 25 | + qdev_prop_set_uint32(sccdev, "oscclk[0]", 40000000); |
26 | }; | 26 | + qdev_prop_set_uint32(sccdev, "oscclk[1]", 24580000); |
27 | DEFINE_MACHINE("raspi2", raspi2_machine_init) | 27 | qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); |
28 | @@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc) | 28 | sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); |
29 | mc->max_cpus = BCM283X_NCPUS; | 29 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); |
30 | mc->min_cpus = BCM283X_NCPUS; | ||
31 | mc->default_cpus = BCM283X_NCPUS; | ||
32 | - mc->default_ram_size = 1024 * 1024 * 1024; | ||
33 | + mc->default_ram_size = 1 * GiB; | ||
34 | } | ||
35 | DEFINE_MACHINE("raspi3", raspi3_machine_init) | ||
36 | #endif | ||
37 | -- | 30 | -- |
38 | 2.20.1 | 31 | 2.20.1 |
39 | 32 | ||
40 | 33 | diff view generated by jsdifflib |
1 | From: Rashmica Gupta <rashmica.g@gmail.com> | 1 | The AN505 and AN511 happen to share the same OSCCLK values, but the |
---|---|---|---|
2 | AN524 will have a different set (and more of them), so split the | ||
3 | settings out to be per-board. | ||
2 | 4 | ||
3 | The AST2600 has the same sets of 3.6v gpios as the AST2400 plus an | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | addtional two sets of 1.8V gpios. | 6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20210215115138.20465-5-peter.maydell@linaro.org | ||
9 | --- | ||
10 | hw/arm/mps2-tz.c | 23 ++++++++++++++++++----- | ||
11 | 1 file changed, 18 insertions(+), 5 deletions(-) | ||
5 | 12 | ||
6 | Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com> | 13 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
7 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
8 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
9 | Acked-by: Joel Stanley <joel@jms.id.au> | ||
10 | Message-id: 20190925143248.10000-15-clg@kaod.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | hw/gpio/aspeed_gpio.c | 142 ++++++++++++++++++++++++++++++++++++++++-- | ||
14 | 1 file changed, 137 insertions(+), 5 deletions(-) | ||
15 | |||
16 | diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/gpio/aspeed_gpio.c | 15 | --- a/hw/arm/mps2-tz.c |
19 | +++ b/hw/gpio/aspeed_gpio.c | 16 | +++ b/hw/arm/mps2-tz.c |
20 | @@ -XXX,XX +XXX,XX @@ | 17 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass { |
21 | #define GPIO_3_6V_MEM_SIZE 0x1F0 | 18 | MPS2TZFPGAType fpga_type; |
22 | #define GPIO_3_6V_REG_ARRAY_SIZE (GPIO_3_6V_MEM_SIZE >> 2) | 19 | uint32_t scc_id; |
23 | 20 | uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ | |
24 | +/* AST2600 only - 1.8V gpios */ | 21 | + uint32_t len_oscclk; |
25 | +/* | 22 | + const uint32_t *oscclk; |
26 | + * The AST2600 has same 3.6V gpios as the AST2400 (memory offsets 0x0-0x198) | 23 | const char *armsse_type; |
27 | + * and addtional 1.8V gpios (memory offsets 0x800-0x9D4). | ||
28 | + */ | ||
29 | +#define GPIO_1_8V_REG_OFFSET 0x800 | ||
30 | +#define GPIO_1_8V_ABCD_DATA_VALUE ((0x800 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
31 | +#define GPIO_1_8V_ABCD_DIRECTION ((0x804 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
32 | +#define GPIO_1_8V_ABCD_INT_ENABLE ((0x808 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
33 | +#define GPIO_1_8V_ABCD_INT_SENS_0 ((0x80C - GPIO_1_8V_REG_OFFSET) >> 2) | ||
34 | +#define GPIO_1_8V_ABCD_INT_SENS_1 ((0x810 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
35 | +#define GPIO_1_8V_ABCD_INT_SENS_2 ((0x814 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
36 | +#define GPIO_1_8V_ABCD_INT_STATUS ((0x818 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
37 | +#define GPIO_1_8V_ABCD_RESET_TOLERANT ((0x81C - GPIO_1_8V_REG_OFFSET) >> 2) | ||
38 | +#define GPIO_1_8V_E_DATA_VALUE ((0x820 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
39 | +#define GPIO_1_8V_E_DIRECTION ((0x824 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
40 | +#define GPIO_1_8V_E_INT_ENABLE ((0x828 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
41 | +#define GPIO_1_8V_E_INT_SENS_0 ((0x82C - GPIO_1_8V_REG_OFFSET) >> 2) | ||
42 | +#define GPIO_1_8V_E_INT_SENS_1 ((0x830 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
43 | +#define GPIO_1_8V_E_INT_SENS_2 ((0x834 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
44 | +#define GPIO_1_8V_E_INT_STATUS ((0x838 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
45 | +#define GPIO_1_8V_E_RESET_TOLERANT ((0x83C - GPIO_1_8V_REG_OFFSET) >> 2) | ||
46 | +#define GPIO_1_8V_ABCD_DEBOUNCE_1 ((0x840 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
47 | +#define GPIO_1_8V_ABCD_DEBOUNCE_2 ((0x844 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
48 | +#define GPIO_1_8V_E_DEBOUNCE_1 ((0x848 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
49 | +#define GPIO_1_8V_E_DEBOUNCE_2 ((0x84C - GPIO_1_8V_REG_OFFSET) >> 2) | ||
50 | +#define GPIO_1_8V_DEBOUNCE_TIME_1 ((0x850 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
51 | +#define GPIO_1_8V_DEBOUNCE_TIME_2 ((0x854 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
52 | +#define GPIO_1_8V_DEBOUNCE_TIME_3 ((0x858 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
53 | +#define GPIO_1_8V_ABCD_COMMAND_SRC_0 ((0x860 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
54 | +#define GPIO_1_8V_ABCD_COMMAND_SRC_1 ((0x864 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
55 | +#define GPIO_1_8V_E_COMMAND_SRC_0 ((0x868 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
56 | +#define GPIO_1_8V_E_COMMAND_SRC_1 ((0x86C - GPIO_1_8V_REG_OFFSET) >> 2) | ||
57 | +#define GPIO_1_8V_ABCD_DATA_READ ((0x8C0 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
58 | +#define GPIO_1_8V_E_DATA_READ ((0x8C4 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
59 | +#define GPIO_1_8V_ABCD_INPUT_MASK ((0x9D0 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
60 | +#define GPIO_1_8V_E_INPUT_MASK ((0x9D4 - GPIO_1_8V_REG_OFFSET) >> 2) | ||
61 | +#define GPIO_1_8V_MEM_SIZE 0x9D8 | ||
62 | +#define GPIO_1_8V_REG_ARRAY_SIZE ((GPIO_1_8V_MEM_SIZE - \ | ||
63 | + GPIO_1_8V_REG_OFFSET) >> 2) | ||
64 | +#define GPIO_MAX_MEM_SIZE MAX(GPIO_3_6V_MEM_SIZE, GPIO_1_8V_MEM_SIZE) | ||
65 | + | ||
66 | static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio) | ||
67 | { | ||
68 | uint32_t falling_edge = 0, rising_edge = 0; | ||
69 | @@ -XXX,XX +XXX,XX @@ static const AspeedGPIOReg aspeed_3_6v_gpios[GPIO_3_6V_REG_ARRAY_SIZE] = { | ||
70 | [GPIO_AC_INPUT_MASK] = { 7, gpio_reg_input_mask }, | ||
71 | }; | 24 | }; |
72 | 25 | ||
73 | +static const AspeedGPIOReg aspeed_1_8v_gpios[GPIO_1_8V_REG_ARRAY_SIZE] = { | 26 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) |
74 | + /* 1.8V Set ABCD */ | 27 | /* Slow 32Khz S32KCLK frequency in Hz */ |
75 | + [GPIO_1_8V_ABCD_DATA_VALUE] = {0, gpio_reg_data_value}, | 28 | #define S32KCLK_FRQ (32 * 1000) |
76 | + [GPIO_1_8V_ABCD_DIRECTION] = {0, gpio_reg_direction}, | 29 | |
77 | + [GPIO_1_8V_ABCD_INT_ENABLE] = {0, gpio_reg_int_enable}, | 30 | +static const uint32_t an505_oscclk[] = { |
78 | + [GPIO_1_8V_ABCD_INT_SENS_0] = {0, gpio_reg_int_sens_0}, | 31 | + 40000000, |
79 | + [GPIO_1_8V_ABCD_INT_SENS_1] = {0, gpio_reg_int_sens_1}, | 32 | + 24580000, |
80 | + [GPIO_1_8V_ABCD_INT_SENS_2] = {0, gpio_reg_int_sens_2}, | 33 | + 25000000, |
81 | + [GPIO_1_8V_ABCD_INT_STATUS] = {0, gpio_reg_int_status}, | ||
82 | + [GPIO_1_8V_ABCD_RESET_TOLERANT] = {0, gpio_reg_reset_tolerant}, | ||
83 | + [GPIO_1_8V_ABCD_DEBOUNCE_1] = {0, gpio_reg_debounce_1}, | ||
84 | + [GPIO_1_8V_ABCD_DEBOUNCE_2] = {0, gpio_reg_debounce_2}, | ||
85 | + [GPIO_1_8V_ABCD_COMMAND_SRC_0] = {0, gpio_reg_cmd_source_0}, | ||
86 | + [GPIO_1_8V_ABCD_COMMAND_SRC_1] = {0, gpio_reg_cmd_source_1}, | ||
87 | + [GPIO_1_8V_ABCD_DATA_READ] = {0, gpio_reg_data_read}, | ||
88 | + [GPIO_1_8V_ABCD_INPUT_MASK] = {0, gpio_reg_input_mask}, | ||
89 | + /* 1.8V Set E */ | ||
90 | + [GPIO_1_8V_E_DATA_VALUE] = {1, gpio_reg_data_value}, | ||
91 | + [GPIO_1_8V_E_DIRECTION] = {1, gpio_reg_direction}, | ||
92 | + [GPIO_1_8V_E_INT_ENABLE] = {1, gpio_reg_int_enable}, | ||
93 | + [GPIO_1_8V_E_INT_SENS_0] = {1, gpio_reg_int_sens_0}, | ||
94 | + [GPIO_1_8V_E_INT_SENS_1] = {1, gpio_reg_int_sens_1}, | ||
95 | + [GPIO_1_8V_E_INT_SENS_2] = {1, gpio_reg_int_sens_2}, | ||
96 | + [GPIO_1_8V_E_INT_STATUS] = {1, gpio_reg_int_status}, | ||
97 | + [GPIO_1_8V_E_RESET_TOLERANT] = {1, gpio_reg_reset_tolerant}, | ||
98 | + [GPIO_1_8V_E_DEBOUNCE_1] = {1, gpio_reg_debounce_1}, | ||
99 | + [GPIO_1_8V_E_DEBOUNCE_2] = {1, gpio_reg_debounce_2}, | ||
100 | + [GPIO_1_8V_E_COMMAND_SRC_0] = {1, gpio_reg_cmd_source_0}, | ||
101 | + [GPIO_1_8V_E_COMMAND_SRC_1] = {1, gpio_reg_cmd_source_1}, | ||
102 | + [GPIO_1_8V_E_DATA_READ] = {1, gpio_reg_data_read}, | ||
103 | + [GPIO_1_8V_E_INPUT_MASK] = {1, gpio_reg_input_mask}, | ||
104 | +}; | 34 | +}; |
105 | + | 35 | + |
106 | static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size) | 36 | /* Create an alias of an entire original MemoryRegion @orig |
107 | { | 37 | * located at @base in the memory map. |
108 | AspeedGPIOState *s = ASPEED_GPIO(opaque); | 38 | */ |
109 | @@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_get_pin(Object *obj, Visitor *v, const char *name, | 39 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, |
110 | int set_idx, group_idx = 0; | 40 | MPS2SCC *scc = opaque; |
111 | 41 | DeviceState *sccdev; | |
112 | if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { | 42 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
113 | - error_setg(errp, "%s: error reading %s", __func__, name); | 43 | + uint32_t i; |
114 | - return; | 44 | |
115 | + /* 1.8V gpio */ | 45 | object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); |
116 | + if (sscanf(name, "gpio%3s%1d", group, &pin) != 2) { | 46 | sccdev = DEVICE(scc); |
117 | + error_setg(errp, "%s: error reading %s", __func__, name); | 47 | qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); |
118 | + return; | 48 | qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); |
119 | + } | 49 | qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); |
120 | } | 50 | - /* This will need to be per-FPGA image eventually */ |
121 | set_idx = get_set_idx(s, group, &group_idx); | 51 | - qdev_prop_set_uint32(sccdev, "len-oscclk", 3); |
122 | if (set_idx == -1) { | 52 | - qdev_prop_set_uint32(sccdev, "oscclk[0]", 40000000); |
123 | @@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_set_pin(Object *obj, Visitor *v, const char *name, | 53 | - qdev_prop_set_uint32(sccdev, "oscclk[1]", 24580000); |
124 | return; | 54 | - qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); |
125 | } | 55 | + qdev_prop_set_uint32(sccdev, "len-oscclk", mmc->len_oscclk); |
126 | if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { | 56 | + for (i = 0; i < mmc->len_oscclk; i++) { |
127 | - error_setg(errp, "%s: error reading %s", __func__, name); | 57 | + g_autofree char *propname = g_strdup_printf("oscclk[%u]", i); |
128 | - return; | 58 | + qdev_prop_set_uint32(sccdev, propname, mmc->oscclk[i]); |
129 | + /* 1.8V gpio */ | 59 | + } |
130 | + if (sscanf(name, "gpio%3s%1d", group, &pin) != 2) { | 60 | sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); |
131 | + error_setg(errp, "%s: error reading %s", __func__, name); | 61 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); |
132 | + return; | ||
133 | + } | ||
134 | } | ||
135 | set_idx = get_set_idx(s, group, &group_idx); | ||
136 | if (set_idx == -1) { | ||
137 | @@ -XXX,XX +XXX,XX @@ static const GPIOSetProperties ast2500_set_props[] = { | ||
138 | [7] = {0x000000ff, 0x000000ff, {"AC"} }, | ||
139 | }; | ||
140 | |||
141 | +static GPIOSetProperties ast2600_3_6v_set_props[] = { | ||
142 | + [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, | ||
143 | + [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, | ||
144 | + [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, | ||
145 | + [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, | ||
146 | + [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} }, | ||
147 | + [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} }, | ||
148 | + [6] = {0xffff0000, 0x0fff0000, {"Y", "Z", "", ""} }, | ||
149 | +}; | ||
150 | + | ||
151 | +static GPIOSetProperties ast2600_1_8v_set_props[] = { | ||
152 | + [0] = {0xffffffff, 0xffffffff, {"18A", "18B", "18C", "18D"} }, | ||
153 | + [1] = {0x0000000f, 0x0000000f, {"18E"} }, | ||
154 | +}; | ||
155 | + | ||
156 | static const MemoryRegionOps aspeed_gpio_ops = { | ||
157 | .read = aspeed_gpio_read, | ||
158 | .write = aspeed_gpio_write, | ||
159 | @@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_realize(DeviceState *dev, Error **errp) | ||
160 | } | ||
161 | |||
162 | memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s, | ||
163 | - TYPE_ASPEED_GPIO, GPIO_3_6V_MEM_SIZE); | ||
164 | + TYPE_ASPEED_GPIO, GPIO_MAX_MEM_SIZE); | ||
165 | |||
166 | sysbus_init_mmio(sbd, &s->iomem); | ||
167 | } | 62 | } |
168 | @@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data) | 63 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) |
169 | agc->reg_table = aspeed_3_6v_gpios; | 64 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); |
65 | mmc->scc_id = 0x41045050; | ||
66 | mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ | ||
67 | + mmc->oscclk = an505_oscclk; | ||
68 | + mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); | ||
69 | mmc->armsse_type = TYPE_IOTKIT; | ||
170 | } | 70 | } |
171 | 71 | ||
172 | +static void aspeed_gpio_ast2600_3_6v_class_init(ObjectClass *klass, void *data) | 72 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) |
173 | +{ | 73 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); |
174 | + AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); | 74 | mmc->scc_id = 0x41045210; |
175 | + | 75 | mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ |
176 | + agc->props = ast2600_3_6v_set_props; | 76 | + mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */ |
177 | + agc->nr_gpio_pins = 208; | 77 | + mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); |
178 | + agc->nr_gpio_sets = 7; | 78 | mmc->armsse_type = TYPE_SSE200; |
179 | + agc->reg_table = aspeed_3_6v_gpios; | ||
180 | +} | ||
181 | + | ||
182 | +static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *data) | ||
183 | +{ | ||
184 | + AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); | ||
185 | + | ||
186 | + agc->props = ast2600_1_8v_set_props; | ||
187 | + agc->nr_gpio_pins = 36; | ||
188 | + agc->nr_gpio_sets = 2; | ||
189 | + agc->reg_table = aspeed_1_8v_gpios; | ||
190 | +} | ||
191 | + | ||
192 | static const TypeInfo aspeed_gpio_info = { | ||
193 | .name = TYPE_ASPEED_GPIO, | ||
194 | .parent = TYPE_SYS_BUS_DEVICE, | ||
195 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_gpio_ast2500_info = { | ||
196 | .instance_init = aspeed_gpio_init, | ||
197 | }; | ||
198 | |||
199 | +static const TypeInfo aspeed_gpio_ast2600_3_6v_info = { | ||
200 | + .name = TYPE_ASPEED_GPIO "-ast2600", | ||
201 | + .parent = TYPE_ASPEED_GPIO, | ||
202 | + .class_init = aspeed_gpio_ast2600_3_6v_class_init, | ||
203 | + .instance_init = aspeed_gpio_init, | ||
204 | +}; | ||
205 | + | ||
206 | +static const TypeInfo aspeed_gpio_ast2600_1_8v_info = { | ||
207 | + .name = TYPE_ASPEED_GPIO "-ast2600-1_8v", | ||
208 | + .parent = TYPE_ASPEED_GPIO, | ||
209 | + .class_init = aspeed_gpio_ast2600_1_8v_class_init, | ||
210 | + .instance_init = aspeed_gpio_init, | ||
211 | +}; | ||
212 | + | ||
213 | static void aspeed_gpio_register_types(void) | ||
214 | { | ||
215 | type_register_static(&aspeed_gpio_info); | ||
216 | type_register_static(&aspeed_gpio_ast2400_info); | ||
217 | type_register_static(&aspeed_gpio_ast2500_info); | ||
218 | + type_register_static(&aspeed_gpio_ast2600_3_6v_info); | ||
219 | + type_register_static(&aspeed_gpio_ast2600_1_8v_info); | ||
220 | } | 79 | } |
221 | 80 | ||
222 | type_init(aspeed_gpio_register_types); | ||
223 | -- | 81 | -- |
224 | 2.20.1 | 82 | 2.20.1 |
225 | 83 | ||
226 | 84 | diff view generated by jsdifflib |
1 | Factor out the implementation of SYS_ISTTY via the new function | 1 | The MPS2 board has 2 LEDs, but the MPS3 board has 10 LEDs. The |
---|---|---|---|
2 | tables. | 2 | FPGAIO device is similar on both sets of boards, but the LED0 |
3 | register has correspondingly more bits that have an effect. Add a | ||
4 | device property for number of LEDs. | ||
3 | 5 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
6 | Message-id: 20190916141544.17540-11-peter.maydell@linaro.org | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20210215115138.20465-6-peter.maydell@linaro.org | ||
7 | --- | 10 | --- |
8 | target/arm/arm-semi.c | 20 +++++++++++++++----- | 11 | include/hw/misc/mps2-fpgaio.h | 5 ++++- |
9 | 1 file changed, 15 insertions(+), 5 deletions(-) | 12 | hw/misc/mps2-fpgaio.c | 31 +++++++++++++++++++++++-------- |
13 | 2 files changed, 27 insertions(+), 9 deletions(-) | ||
10 | 14 | ||
11 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 15 | diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h |
12 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/arm-semi.c | 17 | --- a/include/hw/misc/mps2-fpgaio.h |
14 | +++ b/target/arm/arm-semi.c | 18 | +++ b/include/hw/misc/mps2-fpgaio.h |
15 | @@ -XXX,XX +XXX,XX @@ typedef uint32_t sys_writefn(ARMCPU *cpu, GuestFD *gf, | 19 | @@ -XXX,XX +XXX,XX @@ |
16 | target_ulong buf, uint32_t len); | 20 | #define TYPE_MPS2_FPGAIO "mps2-fpgaio" |
17 | typedef uint32_t sys_readfn(ARMCPU *cpu, GuestFD *gf, | 21 | OBJECT_DECLARE_SIMPLE_TYPE(MPS2FPGAIO, MPS2_FPGAIO) |
18 | target_ulong buf, uint32_t len); | 22 | |
19 | +typedef uint32_t sys_isattyfn(ARMCPU *cpu, GuestFD *gf); | 23 | +#define MPS2FPGAIO_MAX_LEDS 32 |
20 | 24 | + | |
21 | static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) | 25 | struct MPS2FPGAIO { |
26 | /*< private >*/ | ||
27 | SysBusDevice parent_obj; | ||
28 | |||
29 | /*< public >*/ | ||
30 | MemoryRegion iomem; | ||
31 | - LEDState *led[2]; | ||
32 | + LEDState *led[MPS2FPGAIO_MAX_LEDS]; | ||
33 | + uint32_t num_leds; | ||
34 | |||
35 | uint32_t led0; | ||
36 | uint32_t prescale; | ||
37 | diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/hw/misc/mps2-fpgaio.c | ||
40 | +++ b/hw/misc/mps2-fpgaio.c | ||
41 | @@ -XXX,XX +XXX,XX @@ static void mps2_fpgaio_write(void *opaque, hwaddr offset, uint64_t value, | ||
42 | |||
43 | switch (offset) { | ||
44 | case A_LED0: | ||
45 | - s->led0 = value & 0x3; | ||
46 | - led_set_state(s->led[0], value & 0x01); | ||
47 | - led_set_state(s->led[1], value & 0x02); | ||
48 | + if (s->num_leds != 0) { | ||
49 | + uint32_t i; | ||
50 | + | ||
51 | + s->led0 = value & MAKE_64BIT_MASK(0, s->num_leds); | ||
52 | + for (i = 0; i < s->num_leds; i++) { | ||
53 | + led_set_state(s->led[i], value & (1 << i)); | ||
54 | + } | ||
55 | + } | ||
56 | break; | ||
57 | case A_PRESCALE: | ||
58 | resync_counter(s); | ||
59 | @@ -XXX,XX +XXX,XX @@ static void mps2_fpgaio_reset(DeviceState *dev) | ||
60 | s->pscntr = 0; | ||
61 | s->pscntr_sync_ticks = now; | ||
62 | |||
63 | - for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) { | ||
64 | + for (size_t i = 0; i < s->num_leds; i++) { | ||
65 | device_cold_reset(DEVICE(s->led[i])); | ||
66 | } | ||
67 | } | ||
68 | @@ -XXX,XX +XXX,XX @@ static void mps2_fpgaio_init(Object *obj) | ||
69 | static void mps2_fpgaio_realize(DeviceState *dev, Error **errp) | ||
22 | { | 70 | { |
23 | @@ -XXX,XX +XXX,XX @@ static uint32_t host_readfn(ARMCPU *cpu, GuestFD *gf, | 71 | MPS2FPGAIO *s = MPS2_FPGAIO(dev); |
24 | return len - ret; | 72 | + uint32_t i; |
73 | |||
74 | - s->led[0] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH, | ||
75 | - LED_COLOR_GREEN, "USERLED0"); | ||
76 | - s->led[1] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH, | ||
77 | - LED_COLOR_GREEN, "USERLED1"); | ||
78 | + if (s->num_leds > MPS2FPGAIO_MAX_LEDS) { | ||
79 | + error_setg(errp, "num-leds cannot be greater than %d", | ||
80 | + MPS2FPGAIO_MAX_LEDS); | ||
81 | + return; | ||
82 | + } | ||
83 | + | ||
84 | + for (i = 0; i < s->num_leds; i++) { | ||
85 | + g_autofree char *ledname = g_strdup_printf("USERLED%d", i); | ||
86 | + s->led[i] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH, | ||
87 | + LED_COLOR_GREEN, ledname); | ||
88 | + } | ||
25 | } | 89 | } |
26 | 90 | ||
27 | +static uint32_t host_isattyfn(ARMCPU *cpu, GuestFD *gf) | 91 | static bool mps2_fpgaio_counters_needed(void *opaque) |
28 | +{ | 92 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription mps2_fpgaio_vmstate = { |
29 | + return isatty(gf->hostfd); | 93 | static Property mps2_fpgaio_properties[] = { |
30 | +} | 94 | /* Frequency of the prescale counter */ |
31 | + | 95 | DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000), |
32 | static uint32_t gdb_closefn(ARMCPU *cpu, GuestFD *gf) | 96 | + /* Number of LEDs controlled by LED0 register */ |
33 | { | 97 | + DEFINE_PROP_UINT32("num-leds", MPS2FPGAIO, num_leds, 2), |
34 | return arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); | 98 | DEFINE_PROP_END_OF_LIST(), |
35 | @@ -XXX,XX +XXX,XX @@ static uint32_t gdb_readfn(ARMCPU *cpu, GuestFD *gf, | ||
36 | gf->hostfd, buf, len); | ||
37 | } | ||
38 | |||
39 | +static uint32_t gdb_isattyfn(ARMCPU *cpu, GuestFD *gf) | ||
40 | +{ | ||
41 | + return arm_gdb_syscall(cpu, arm_semi_cb, "isatty,%x", gf->hostfd); | ||
42 | +} | ||
43 | + | ||
44 | typedef struct GuestFDFunctions { | ||
45 | sys_closefn *closefn; | ||
46 | sys_writefn *writefn; | ||
47 | sys_readfn *readfn; | ||
48 | + sys_isattyfn *isattyfn; | ||
49 | } GuestFDFunctions; | ||
50 | |||
51 | static const GuestFDFunctions guestfd_fns[] = { | ||
52 | @@ -XXX,XX +XXX,XX @@ static const GuestFDFunctions guestfd_fns[] = { | ||
53 | .closefn = host_closefn, | ||
54 | .writefn = host_writefn, | ||
55 | .readfn = host_readfn, | ||
56 | + .isattyfn = host_isattyfn, | ||
57 | }, | ||
58 | [GuestFDGDB] = { | ||
59 | .closefn = gdb_closefn, | ||
60 | .writefn = gdb_writefn, | ||
61 | .readfn = gdb_readfn, | ||
62 | + .isattyfn = gdb_isattyfn, | ||
63 | }, | ||
64 | }; | 99 | }; |
65 | 100 | ||
66 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
67 | return set_swi_errno(env, -1); | ||
68 | } | ||
69 | |||
70 | - if (use_gdb_syscalls()) { | ||
71 | - return arm_gdb_syscall(cpu, arm_semi_cb, "isatty,%x", gf->hostfd); | ||
72 | - } else { | ||
73 | - return isatty(gf->hostfd); | ||
74 | - } | ||
75 | + return guestfd_fns[gf->type].isattyfn(cpu, gf); | ||
76 | case TARGET_SYS_SEEK: | ||
77 | GET_ARG(0); | ||
78 | GET_ARG(1); | ||
79 | -- | 101 | -- |
80 | 2.20.1 | 102 | 2.20.1 |
81 | 103 | ||
82 | 104 | diff view generated by jsdifflib |
1 | SH_EXT_STDOUT_STDERR is a v2.0 semihosting extension: the guest | 1 | MPS3 boards have an extra SWITCH register in the FPGAIO block which |
---|---|---|---|
2 | can open ":tt" with a file mode requesting append access in | 2 | reports the value of some switches. Implement this, governed by a |
3 | order to open stderr, in addition to the existing "open for | 3 | property the board code can use to specify whether whether it exists. |
4 | read for stdin or write for stdout". Implement this and | ||
5 | report it via the :semihosting-features data. | ||
6 | 4 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
9 | Message-id: 20190916141544.17540-16-peter.maydell@linaro.org | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20210215115138.20465-7-peter.maydell@linaro.org | ||
10 | --- | 9 | --- |
11 | target/arm/arm-semi.c | 19 +++++++++++++++++-- | 10 | include/hw/misc/mps2-fpgaio.h | 1 + |
12 | 1 file changed, 17 insertions(+), 2 deletions(-) | 11 | hw/misc/mps2-fpgaio.c | 10 ++++++++++ |
12 | 2 files changed, 11 insertions(+) | ||
13 | 13 | ||
14 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 14 | diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/arm-semi.c | 16 | --- a/include/hw/misc/mps2-fpgaio.h |
17 | +++ b/target/arm/arm-semi.c | 17 | +++ b/include/hw/misc/mps2-fpgaio.h |
18 | @@ -XXX,XX +XXX,XX @@ static uint32_t gdb_flenfn(ARMCPU *cpu, GuestFD *gf) | 18 | @@ -XXX,XX +XXX,XX @@ struct MPS2FPGAIO { |
19 | 19 | MemoryRegion iomem; | |
20 | /* Feature bits reportable in feature byte 0 */ | 20 | LEDState *led[MPS2FPGAIO_MAX_LEDS]; |
21 | #define SH_EXT_EXIT_EXTENDED (1 << 0) | 21 | uint32_t num_leds; |
22 | +#define SH_EXT_STDOUT_STDERR (1 << 1) | 22 | + bool has_switches; |
23 | 23 | ||
24 | static const uint8_t featurefile_data[] = { | 24 | uint32_t led0; |
25 | SHFB_MAGIC_0, | 25 | uint32_t prescale; |
26 | SHFB_MAGIC_1, | 26 | diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c |
27 | SHFB_MAGIC_2, | 27 | index XXXXXXX..XXXXXXX 100644 |
28 | SHFB_MAGIC_3, | 28 | --- a/hw/misc/mps2-fpgaio.c |
29 | - SH_EXT_EXIT_EXTENDED, /* Feature byte 0 */ | 29 | +++ b/hw/misc/mps2-fpgaio.c |
30 | + SH_EXT_EXIT_EXTENDED | SH_EXT_STDOUT_STDERR, /* Feature byte 0 */ | 30 | @@ -XXX,XX +XXX,XX @@ REG32(CLK100HZ, 0x14) |
31 | REG32(COUNTER, 0x18) | ||
32 | REG32(PRESCALE, 0x1c) | ||
33 | REG32(PSCNTR, 0x20) | ||
34 | +REG32(SWITCH, 0x28) | ||
35 | REG32(MISC, 0x4c) | ||
36 | |||
37 | static uint32_t counter_from_tickoff(int64_t now, int64_t tick_offset, int frq) | ||
38 | @@ -XXX,XX +XXX,XX @@ static uint64_t mps2_fpgaio_read(void *opaque, hwaddr offset, unsigned size) | ||
39 | resync_counter(s); | ||
40 | r = s->pscntr; | ||
41 | break; | ||
42 | + case A_SWITCH: | ||
43 | + if (!s->has_switches) { | ||
44 | + goto bad_offset; | ||
45 | + } | ||
46 | + /* User-togglable board switches. We don't model that, so report 0. */ | ||
47 | + r = 0; | ||
48 | + break; | ||
49 | default: | ||
50 | + bad_offset: | ||
51 | qemu_log_mask(LOG_GUEST_ERROR, | ||
52 | "MPS2 FPGAIO read: bad offset %x\n", (int) offset); | ||
53 | r = 0; | ||
54 | @@ -XXX,XX +XXX,XX @@ static Property mps2_fpgaio_properties[] = { | ||
55 | DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000), | ||
56 | /* Number of LEDs controlled by LED0 register */ | ||
57 | DEFINE_PROP_UINT32("num-leds", MPS2FPGAIO, num_leds, 2), | ||
58 | + DEFINE_PROP_BOOL("has-switches", MPS2FPGAIO, has_switches, false), | ||
59 | DEFINE_PROP_END_OF_LIST(), | ||
31 | }; | 60 | }; |
32 | 61 | ||
33 | static void init_featurefile_guestfd(int guestfd) | ||
34 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
35 | } | ||
36 | |||
37 | if (strcmp(s, ":tt") == 0) { | ||
38 | - int result_fileno = arg1 < 4 ? STDIN_FILENO : STDOUT_FILENO; | ||
39 | + int result_fileno; | ||
40 | + | ||
41 | + /* | ||
42 | + * We implement SH_EXT_STDOUT_STDERR, so: | ||
43 | + * open for read == stdin | ||
44 | + * open for write == stdout | ||
45 | + * open for append == stderr | ||
46 | + */ | ||
47 | + if (arg1 < 4) { | ||
48 | + result_fileno = STDIN_FILENO; | ||
49 | + } else if (arg1 < 8) { | ||
50 | + result_fileno = STDOUT_FILENO; | ||
51 | + } else { | ||
52 | + result_fileno = STDERR_FILENO; | ||
53 | + } | ||
54 | associate_guestfd(guestfd, result_fileno); | ||
55 | unlock_user(s, arg0, 0); | ||
56 | return guestfd; | ||
57 | -- | 62 | -- |
58 | 2.20.1 | 63 | 2.20.1 |
59 | 64 | ||
60 | 65 | diff view generated by jsdifflib |
1 | Switch the imx_epit.c code away from bottom-half based ptimers to | 1 | Set the FPGAIO num-leds and have-switches properties explicitly |
---|---|---|---|
2 | the new transaction-based ptimer API. This just requires adding | 2 | per-board, rather than relying on the defaults. The AN505 and AN521 |
3 | begin/commit calls around the various places that modify the ptimer | 3 | both have the same settings as the default values, but the AN524 will |
4 | state, and using the new ptimer_init() function to create the timer. | 4 | be different. |
5 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20191008171740.9679-19-peter.maydell@linaro.org | 9 | Message-id: 20210215115138.20465-8-peter.maydell@linaro.org |
9 | --- | 10 | --- |
10 | hw/timer/imx_gpt.c | 21 +++++++++++++++++---- | 11 | hw/arm/mps2-tz.c | 9 +++++++++ |
11 | 1 file changed, 17 insertions(+), 4 deletions(-) | 12 | 1 file changed, 9 insertions(+) |
12 | 13 | ||
13 | diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c | 14 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
14 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/timer/imx_gpt.c | 16 | --- a/hw/arm/mps2-tz.c |
16 | +++ b/hw/timer/imx_gpt.c | 17 | +++ b/hw/arm/mps2-tz.c |
17 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass { |
18 | #include "hw/irq.h" | 19 | uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ |
19 | #include "hw/timer/imx_gpt.h" | 20 | uint32_t len_oscclk; |
20 | #include "migration/vmstate.h" | 21 | const uint32_t *oscclk; |
21 | -#include "qemu/main-loop.h" | 22 | + uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ |
22 | #include "qemu/module.h" | 23 | + bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ |
23 | #include "qemu/log.h" | 24 | const char *armsse_type; |
24 | |||
25 | @@ -XXX,XX +XXX,XX @@ static const IMXClk imx7_gpt_clocks[] = { | ||
26 | CLK_NONE, /* 111 not defined */ | ||
27 | }; | 25 | }; |
28 | 26 | ||
29 | +/* Must be called from within ptimer_transaction_begin/commit block */ | 27 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, |
30 | static void imx_gpt_set_freq(IMXGPTState *s) | 28 | const char *name, hwaddr size) |
31 | { | 29 | { |
32 | uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3); | 30 | MPS2FPGAIO *fpgaio = opaque; |
33 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg, | 31 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
34 | return timeout; | 32 | |
33 | object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO); | ||
34 | + qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds); | ||
35 | + qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_switches); | ||
36 | sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); | ||
37 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); | ||
35 | } | 38 | } |
36 | 39 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) | |
37 | +/* Must be called from within ptimer_transaction_begin/commit block */ | 40 | mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ |
38 | static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event) | 41 | mmc->oscclk = an505_oscclk; |
39 | { | 42 | mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); |
40 | uint32_t timeout = GPT_TIMER_MAX; | 43 | + mmc->fpgaio_num_leds = 2; |
41 | @@ -XXX,XX +XXX,XX @@ static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size) | 44 | + mmc->fpgaio_has_switches = false; |
42 | 45 | mmc->armsse_type = TYPE_IOTKIT; | |
43 | static void imx_gpt_reset_common(IMXGPTState *s, bool is_soft_reset) | ||
44 | { | ||
45 | + ptimer_transaction_begin(s->timer); | ||
46 | /* stop timer */ | ||
47 | ptimer_stop(s->timer); | ||
48 | |||
49 | @@ -XXX,XX +XXX,XX @@ static void imx_gpt_reset_common(IMXGPTState *s, bool is_soft_reset) | ||
50 | if (s->freq && (s->cr & GPT_CR_EN)) { | ||
51 | ptimer_run(s->timer, 1); | ||
52 | } | ||
53 | + ptimer_transaction_commit(s->timer); | ||
54 | } | 46 | } |
55 | 47 | ||
56 | static void imx_gpt_soft_reset(DeviceState *dev) | 48 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) |
57 | @@ -XXX,XX +XXX,XX @@ static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, | 49 | mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ |
58 | imx_gpt_soft_reset(DEVICE(s)); | 50 | mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */ |
59 | } else { | 51 | mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); |
60 | /* set our freq, as the source might have changed */ | 52 | + mmc->fpgaio_num_leds = 2; |
61 | + ptimer_transaction_begin(s->timer); | 53 | + mmc->fpgaio_has_switches = false; |
62 | imx_gpt_set_freq(s); | 54 | mmc->armsse_type = TYPE_SSE200; |
63 | |||
64 | if ((oldreg ^ s->cr) & GPT_CR_EN) { | ||
65 | @@ -XXX,XX +XXX,XX @@ static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, | ||
66 | ptimer_stop(s->timer); | ||
67 | } | ||
68 | } | ||
69 | + ptimer_transaction_commit(s->timer); | ||
70 | } | ||
71 | break; | ||
72 | |||
73 | case 1: /* Prescaler */ | ||
74 | s->pr = value & 0xfff; | ||
75 | + ptimer_transaction_begin(s->timer); | ||
76 | imx_gpt_set_freq(s); | ||
77 | + ptimer_transaction_commit(s->timer); | ||
78 | break; | ||
79 | |||
80 | case 2: /* SR */ | ||
81 | @@ -XXX,XX +XXX,XX @@ static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, | ||
82 | s->ir = value & 0x3f; | ||
83 | imx_gpt_update_int(s); | ||
84 | |||
85 | + ptimer_transaction_begin(s->timer); | ||
86 | imx_gpt_compute_next_timeout(s, false); | ||
87 | + ptimer_transaction_commit(s->timer); | ||
88 | |||
89 | break; | ||
90 | |||
91 | case 4: /* OCR1 -- output compare register */ | ||
92 | s->ocr1 = value; | ||
93 | |||
94 | + ptimer_transaction_begin(s->timer); | ||
95 | /* In non-freerun mode, reset count when this register is written */ | ||
96 | if (!(s->cr & GPT_CR_FRR)) { | ||
97 | s->next_timeout = GPT_TIMER_MAX; | ||
98 | @@ -XXX,XX +XXX,XX @@ static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, | ||
99 | |||
100 | /* compute the new timeout */ | ||
101 | imx_gpt_compute_next_timeout(s, false); | ||
102 | + ptimer_transaction_commit(s->timer); | ||
103 | |||
104 | break; | ||
105 | |||
106 | @@ -XXX,XX +XXX,XX @@ static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, | ||
107 | s->ocr2 = value; | ||
108 | |||
109 | /* compute the new timeout */ | ||
110 | + ptimer_transaction_begin(s->timer); | ||
111 | imx_gpt_compute_next_timeout(s, false); | ||
112 | + ptimer_transaction_commit(s->timer); | ||
113 | |||
114 | break; | ||
115 | |||
116 | @@ -XXX,XX +XXX,XX @@ static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, | ||
117 | s->ocr3 = value; | ||
118 | |||
119 | /* compute the new timeout */ | ||
120 | + ptimer_transaction_begin(s->timer); | ||
121 | imx_gpt_compute_next_timeout(s, false); | ||
122 | + ptimer_transaction_commit(s->timer); | ||
123 | |||
124 | break; | ||
125 | |||
126 | @@ -XXX,XX +XXX,XX @@ static void imx_gpt_realize(DeviceState *dev, Error **errp) | ||
127 | { | ||
128 | IMXGPTState *s = IMX_GPT(dev); | ||
129 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
130 | - QEMUBH *bh; | ||
131 | |||
132 | sysbus_init_irq(sbd, &s->irq); | ||
133 | memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT, | ||
134 | 0x00001000); | ||
135 | sysbus_init_mmio(sbd, &s->iomem); | ||
136 | |||
137 | - bh = qemu_bh_new(imx_gpt_timeout, s); | ||
138 | - s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
139 | + s->timer = ptimer_init(imx_gpt_timeout, s, PTIMER_POLICY_DEFAULT); | ||
140 | } | 55 | } |
141 | 56 | ||
142 | static void imx_gpt_class_init(ObjectClass *klass, void *data) | ||
143 | -- | 57 | -- |
144 | 2.20.1 | 58 | 2.20.1 |
145 | 59 | ||
146 | 60 | diff view generated by jsdifflib |
1 | Currently the ptimer design uses a QEMU bottom-half as its | 1 | In the mps2-tz board code, we handle devices whose interrupt lines |
---|---|---|---|
2 | mechanism for calling back into the device model using the | 2 | must be wired to all CPUs by creating IRQ splitter devices for the |
3 | ptimer when the timer has expired. Unfortunately this design | 3 | AN521, because it has 2 CPUs, but wiring the device IRQ directly to |
4 | is fatally flawed, because it means that there is a lag | 4 | the SSE/IoTKit input for the AN505, which has only 1 CPU. |
5 | between the ptimer updating its own state and the device | ||
6 | callback function updating device state, and guest accesses | ||
7 | to device registers between the two can return inconsistent | ||
8 | device state. | ||
9 | 5 | ||
10 | We want to replace the bottom-half design with one where | 6 | We can avoid making an explicit check on the board type constant by |
11 | the guest device's callback is called either immediately | 7 | instead creating and using the IRQ splitters for any board with more |
12 | (when the ptimer triggers by timeout) or when the device | 8 | than 1 CPU. This avoids having to add extra cases to the |
13 | model code closes a transaction-begin/end section (when the | 9 | conditionals every time we add new boards. |
14 | ptimer triggers because the device model changed the | ||
15 | ptimer's count value or other state). As the first step, | ||
16 | rename ptimer_init() to ptimer_init_with_bh(), to free up | ||
17 | the ptimer_init() name for the new API. We can then convert | ||
18 | all the ptimer users away from ptimer_init_with_bh() before | ||
19 | removing it entirely. | ||
20 | |||
21 | (Commit created with | ||
22 | git grep -l ptimer_init | xargs sed -i -e 's/ptimer_init/ptimer_init_with_bh/' | ||
23 | and three overlong lines folded by hand.) | ||
24 | 10 | ||
25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
26 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
27 | Message-id: 20191008171740.9679-2-peter.maydell@linaro.org | 14 | Message-id: 20210215115138.20465-9-peter.maydell@linaro.org |
28 | --- | 15 | --- |
29 | include/hw/ptimer.h | 11 ++++++----- | 16 | hw/arm/mps2-tz.c | 19 +++++++++---------- |
30 | hw/arm/musicpal.c | 2 +- | 17 | 1 file changed, 9 insertions(+), 10 deletions(-) |
31 | hw/core/ptimer.c | 2 +- | ||
32 | hw/dma/xilinx_axidma.c | 2 +- | ||
33 | hw/m68k/mcf5206.c | 2 +- | ||
34 | hw/m68k/mcf5208.c | 2 +- | ||
35 | hw/net/fsl_etsec/etsec.c | 2 +- | ||
36 | hw/net/lan9118.c | 2 +- | ||
37 | hw/timer/allwinner-a10-pit.c | 2 +- | ||
38 | hw/timer/altera_timer.c | 2 +- | ||
39 | hw/timer/arm_mptimer.c | 6 +++--- | ||
40 | hw/timer/arm_timer.c | 2 +- | ||
41 | hw/timer/cmsdk-apb-dualtimer.c | 2 +- | ||
42 | hw/timer/cmsdk-apb-timer.c | 2 +- | ||
43 | hw/timer/digic-timer.c | 2 +- | ||
44 | hw/timer/etraxfs_timer.c | 6 +++--- | ||
45 | hw/timer/exynos4210_mct.c | 7 ++++--- | ||
46 | hw/timer/exynos4210_pwm.c | 2 +- | ||
47 | hw/timer/exynos4210_rtc.c | 4 ++-- | ||
48 | hw/timer/grlib_gptimer.c | 2 +- | ||
49 | hw/timer/imx_epit.c | 4 ++-- | ||
50 | hw/timer/imx_gpt.c | 2 +- | ||
51 | hw/timer/lm32_timer.c | 2 +- | ||
52 | hw/timer/milkymist-sysctl.c | 4 ++-- | ||
53 | hw/timer/mss-timer.c | 2 +- | ||
54 | hw/timer/puv3_ost.c | 2 +- | ||
55 | hw/timer/sh_timer.c | 2 +- | ||
56 | hw/timer/slavio_timer.c | 2 +- | ||
57 | hw/timer/xilinx_timer.c | 2 +- | ||
58 | hw/watchdog/cmsdk-apb-watchdog.c | 2 +- | ||
59 | tests/ptimer-test.c | 22 +++++++++++----------- | ||
60 | 31 files changed, 56 insertions(+), 54 deletions(-) | ||
61 | 18 | ||
62 | diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h | 19 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
63 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
64 | --- a/include/hw/ptimer.h | 21 | --- a/hw/arm/mps2-tz.c |
65 | +++ b/include/hw/ptimer.h | 22 | +++ b/hw/arm/mps2-tz.c |
66 | @@ -XXX,XX +XXX,XX @@ | 23 | @@ -XXX,XX +XXX,XX @@ static void make_ram_alias(MemoryRegion *mr, const char *name, |
67 | * ptimer_set_count() or ptimer_set_limit() will not trigger the timer | 24 | static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) |
68 | * (though it will cause a reload). Only a counter decrement to "0" | ||
69 | * will cause a trigger. Not compatible with NO_IMMEDIATE_TRIGGER; | ||
70 | - * ptimer_init() will assert() that you don't set both. | ||
71 | + * ptimer_init_with_bh() will assert() that you don't set both. | ||
72 | */ | ||
73 | #define PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT (1 << 5) | ||
74 | |||
75 | @@ -XXX,XX +XXX,XX @@ typedef struct ptimer_state ptimer_state; | ||
76 | typedef void (*ptimer_cb)(void *opaque); | ||
77 | |||
78 | /** | ||
79 | - * ptimer_init - Allocate and return a new ptimer | ||
80 | + * ptimer_init_with_bh - Allocate and return a new ptimer | ||
81 | * @bh: QEMU bottom half which is run on timer expiry | ||
82 | * @policy: PTIMER_POLICY_* bits specifying behaviour | ||
83 | * | ||
84 | @@ -XXX,XX +XXX,XX @@ typedef void (*ptimer_cb)(void *opaque); | ||
85 | * The ptimer takes ownership of @bh and will delete it | ||
86 | * when the ptimer is eventually freed. | ||
87 | */ | ||
88 | -ptimer_state *ptimer_init(QEMUBH *bh, uint8_t policy_mask); | ||
89 | +ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask); | ||
90 | |||
91 | /** | ||
92 | * ptimer_free - Free a ptimer | ||
93 | * @s: timer to free | ||
94 | * | ||
95 | - * Free a ptimer created using ptimer_init() (including | ||
96 | + * Free a ptimer created using ptimer_init_with_bh() (including | ||
97 | * deleting the bottom half which it is using). | ||
98 | */ | ||
99 | void ptimer_free(ptimer_state *s); | ||
100 | @@ -XXX,XX +XXX,XX @@ void ptimer_set_count(ptimer_state *s, uint64_t count); | ||
101 | * @oneshot: non-zero if this timer should only count down once | ||
102 | * | ||
103 | * Start a ptimer counting down; when it reaches zero the bottom half | ||
104 | - * passed to ptimer_init() will be invoked. If the @oneshot argument is zero, | ||
105 | + * passed to ptimer_init_with_bh() will be invoked. | ||
106 | + * If the @oneshot argument is zero, | ||
107 | * the counter value will then be reloaded from the limit and it will | ||
108 | * start counting down again. If @oneshot is non-zero, then the counter | ||
109 | * will disable itself when it reaches zero. | ||
110 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c | ||
111 | index XXXXXXX..XXXXXXX 100644 | ||
112 | --- a/hw/arm/musicpal.c | ||
113 | +++ b/hw/arm/musicpal.c | ||
114 | @@ -XXX,XX +XXX,XX @@ static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, | ||
115 | s->freq = freq; | ||
116 | |||
117 | bh = qemu_bh_new(mv88w8618_timer_tick, s); | ||
118 | - s->ptimer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
119 | + s->ptimer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
120 | } | ||
121 | |||
122 | static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset, | ||
123 | diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c | ||
124 | index XXXXXXX..XXXXXXX 100644 | ||
125 | --- a/hw/core/ptimer.c | ||
126 | +++ b/hw/core/ptimer.c | ||
127 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_ptimer = { | ||
128 | } | ||
129 | }; | ||
130 | |||
131 | -ptimer_state *ptimer_init(QEMUBH *bh, uint8_t policy_mask) | ||
132 | +ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask) | ||
133 | { | 25 | { |
134 | ptimer_state *s; | 26 | /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ |
135 | 27 | - MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); | |
136 | diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c | 28 | + MachineClass *mc = MACHINE_GET_CLASS(mms); |
137 | index XXXXXXX..XXXXXXX 100644 | 29 | |
138 | --- a/hw/dma/xilinx_axidma.c | 30 | assert(irqno < MPS2TZ_NUMIRQ); |
139 | +++ b/hw/dma/xilinx_axidma.c | 31 | |
140 | @@ -XXX,XX +XXX,XX @@ static void xilinx_axidma_realize(DeviceState *dev, Error **errp) | 32 | - switch (mmc->fpga_type) { |
141 | 33 | - case FPGA_AN505: | |
142 | st->nr = i; | 34 | - return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno); |
143 | st->bh = qemu_bh_new(timer_hit, st); | 35 | - case FPGA_AN521: |
144 | - st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT); | 36 | + if (mc->max_cpus > 1) { |
145 | + st->ptimer = ptimer_init_with_bh(st->bh, PTIMER_POLICY_DEFAULT); | 37 | return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); |
146 | ptimer_set_freq(st->ptimer, s->freqhz); | 38 | - default: |
147 | } | 39 | - g_assert_not_reached(); |
148 | return; | 40 | + } else { |
149 | diff --git a/hw/m68k/mcf5206.c b/hw/m68k/mcf5206.c | 41 | + return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno); |
150 | index XXXXXXX..XXXXXXX 100644 | ||
151 | --- a/hw/m68k/mcf5206.c | ||
152 | +++ b/hw/m68k/mcf5206.c | ||
153 | @@ -XXX,XX +XXX,XX @@ static m5206_timer_state *m5206_timer_init(qemu_irq irq) | ||
154 | |||
155 | s = g_new0(m5206_timer_state, 1); | ||
156 | bh = qemu_bh_new(m5206_timer_trigger, s); | ||
157 | - s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
158 | + s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
159 | s->irq = irq; | ||
160 | m5206_timer_reset(s); | ||
161 | return s; | ||
162 | diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c | ||
163 | index XXXXXXX..XXXXXXX 100644 | ||
164 | --- a/hw/m68k/mcf5208.c | ||
165 | +++ b/hw/m68k/mcf5208.c | ||
166 | @@ -XXX,XX +XXX,XX @@ static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic) | ||
167 | for (i = 0; i < 2; i++) { | ||
168 | s = g_new0(m5208_timer_state, 1); | ||
169 | bh = qemu_bh_new(m5208_timer_trigger, s); | ||
170 | - s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
171 | + s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
172 | memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s, | ||
173 | "m5208-timer", 0x00004000); | ||
174 | memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i, | ||
175 | diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c | ||
176 | index XXXXXXX..XXXXXXX 100644 | ||
177 | --- a/hw/net/fsl_etsec/etsec.c | ||
178 | +++ b/hw/net/fsl_etsec/etsec.c | ||
179 | @@ -XXX,XX +XXX,XX @@ static void etsec_realize(DeviceState *dev, Error **errp) | ||
180 | |||
181 | |||
182 | etsec->bh = qemu_bh_new(etsec_timer_hit, etsec); | ||
183 | - etsec->ptimer = ptimer_init(etsec->bh, PTIMER_POLICY_DEFAULT); | ||
184 | + etsec->ptimer = ptimer_init_with_bh(etsec->bh, PTIMER_POLICY_DEFAULT); | ||
185 | ptimer_set_freq(etsec->ptimer, 100); | ||
186 | } | ||
187 | |||
188 | diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c | ||
189 | index XXXXXXX..XXXXXXX 100644 | ||
190 | --- a/hw/net/lan9118.c | ||
191 | +++ b/hw/net/lan9118.c | ||
192 | @@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp) | ||
193 | s->txp = &s->tx_packet; | ||
194 | |||
195 | bh = qemu_bh_new(lan9118_tick, s); | ||
196 | - s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
197 | + s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
198 | ptimer_set_freq(s->timer, 10000); | ||
199 | ptimer_set_limit(s->timer, 0xffff, 1); | ||
200 | } | ||
201 | diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c | ||
202 | index XXXXXXX..XXXXXXX 100644 | ||
203 | --- a/hw/timer/allwinner-a10-pit.c | ||
204 | +++ b/hw/timer/allwinner-a10-pit.c | ||
205 | @@ -XXX,XX +XXX,XX @@ static void a10_pit_init(Object *obj) | ||
206 | tc->container = s; | ||
207 | tc->index = i; | ||
208 | bh[i] = qemu_bh_new(a10_pit_timer_cb, tc); | ||
209 | - s->timer[i] = ptimer_init(bh[i], PTIMER_POLICY_DEFAULT); | ||
210 | + s->timer[i] = ptimer_init_with_bh(bh[i], PTIMER_POLICY_DEFAULT); | ||
211 | } | 42 | } |
212 | } | 43 | } |
213 | 44 | ||
214 | diff --git a/hw/timer/altera_timer.c b/hw/timer/altera_timer.c | 45 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) |
215 | index XXXXXXX..XXXXXXX 100644 | 46 | sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); |
216 | --- a/hw/timer/altera_timer.c | ||
217 | +++ b/hw/timer/altera_timer.c | ||
218 | @@ -XXX,XX +XXX,XX @@ static void altera_timer_realize(DeviceState *dev, Error **errp) | ||
219 | } | ||
220 | |||
221 | t->bh = qemu_bh_new(timer_hit, t); | ||
222 | - t->ptimer = ptimer_init(t->bh, PTIMER_POLICY_DEFAULT); | ||
223 | + t->ptimer = ptimer_init_with_bh(t->bh, PTIMER_POLICY_DEFAULT); | ||
224 | ptimer_set_freq(t->ptimer, t->freq_hz); | ||
225 | |||
226 | memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, | ||
227 | diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c | ||
228 | index XXXXXXX..XXXXXXX 100644 | ||
229 | --- a/hw/timer/arm_mptimer.c | ||
230 | +++ b/hw/timer/arm_mptimer.c | ||
231 | @@ -XXX,XX +XXX,XX @@ static void arm_mptimer_reset(DeviceState *dev) | ||
232 | } | ||
233 | } | ||
234 | |||
235 | -static void arm_mptimer_init(Object *obj) | ||
236 | +static void arm_mptimer_init_with_bh(Object *obj) | ||
237 | { | ||
238 | ARMMPTimerState *s = ARM_MPTIMER(obj); | ||
239 | |||
240 | @@ -XXX,XX +XXX,XX @@ static void arm_mptimer_realize(DeviceState *dev, Error **errp) | ||
241 | for (i = 0; i < s->num_cpu; i++) { | ||
242 | TimerBlock *tb = &s->timerblock[i]; | ||
243 | QEMUBH *bh = qemu_bh_new(timerblock_tick, tb); | ||
244 | - tb->timer = ptimer_init(bh, PTIMER_POLICY); | ||
245 | + tb->timer = ptimer_init_with_bh(bh, PTIMER_POLICY); | ||
246 | sysbus_init_irq(sbd, &tb->irq); | ||
247 | memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, | ||
248 | "arm_mptimer_timerblock", 0x20); | ||
249 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo arm_mptimer_info = { | ||
250 | .name = TYPE_ARM_MPTIMER, | ||
251 | .parent = TYPE_SYS_BUS_DEVICE, | ||
252 | .instance_size = sizeof(ARMMPTimerState), | ||
253 | - .instance_init = arm_mptimer_init, | ||
254 | + .instance_init = arm_mptimer_init_with_bh, | ||
255 | .class_init = arm_mptimer_class_init, | ||
256 | }; | ||
257 | |||
258 | diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c | ||
259 | index XXXXXXX..XXXXXXX 100644 | ||
260 | --- a/hw/timer/arm_timer.c | ||
261 | +++ b/hw/timer/arm_timer.c | ||
262 | @@ -XXX,XX +XXX,XX @@ static arm_timer_state *arm_timer_init(uint32_t freq) | ||
263 | s->control = TIMER_CTRL_IE; | ||
264 | |||
265 | bh = qemu_bh_new(arm_timer_tick, s); | ||
266 | - s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
267 | + s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
268 | vmstate_register(NULL, -1, &vmstate_arm_timer, s); | ||
269 | return s; | ||
270 | } | ||
271 | diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c | ||
272 | index XXXXXXX..XXXXXXX 100644 | ||
273 | --- a/hw/timer/cmsdk-apb-dualtimer.c | ||
274 | +++ b/hw/timer/cmsdk-apb-dualtimer.c | ||
275 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp) | ||
276 | QEMUBH *bh = qemu_bh_new(cmsdk_dualtimermod_tick, m); | ||
277 | |||
278 | m->parent = s; | ||
279 | - m->timer = ptimer_init(bh, | ||
280 | + m->timer = ptimer_init_with_bh(bh, | ||
281 | PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | | ||
282 | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | | ||
283 | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | | ||
284 | diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c | ||
285 | index XXXXXXX..XXXXXXX 100644 | ||
286 | --- a/hw/timer/cmsdk-apb-timer.c | ||
287 | +++ b/hw/timer/cmsdk-apb-timer.c | ||
288 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) | ||
289 | } | ||
290 | |||
291 | bh = qemu_bh_new(cmsdk_apb_timer_tick, s); | ||
292 | - s->timer = ptimer_init(bh, | ||
293 | + s->timer = ptimer_init_with_bh(bh, | ||
294 | PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | | ||
295 | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | | ||
296 | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | | ||
297 | diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c | ||
298 | index XXXXXXX..XXXXXXX 100644 | ||
299 | --- a/hw/timer/digic-timer.c | ||
300 | +++ b/hw/timer/digic-timer.c | ||
301 | @@ -XXX,XX +XXX,XX @@ static void digic_timer_init(Object *obj) | ||
302 | { | ||
303 | DigicTimerState *s = DIGIC_TIMER(obj); | ||
304 | |||
305 | - s->ptimer = ptimer_init(NULL, PTIMER_POLICY_DEFAULT); | ||
306 | + s->ptimer = ptimer_init_with_bh(NULL, PTIMER_POLICY_DEFAULT); | ||
307 | 47 | ||
308 | /* | 48 | /* |
309 | * FIXME: there is no documentation on Digic timer | 49 | - * The AN521 needs us to create splitters to feed the IRQ inputs |
310 | diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c | 50 | - * for each CPU in the SSE-200 from each device in the board. |
311 | index XXXXXXX..XXXXXXX 100644 | 51 | + * If this board has more than one CPU, then we need to create splitters |
312 | --- a/hw/timer/etraxfs_timer.c | 52 | + * to feed the IRQ inputs for each CPU in the SSE from each device in the |
313 | +++ b/hw/timer/etraxfs_timer.c | 53 | + * board. If there is only one CPU, we can just wire the device IRQ |
314 | @@ -XXX,XX +XXX,XX @@ static void etraxfs_timer_realize(DeviceState *dev, Error **errp) | 54 | + * directly to the SSE's IRQ input. |
315 | t->bh_t0 = qemu_bh_new(timer0_hit, t); | 55 | */ |
316 | t->bh_t1 = qemu_bh_new(timer1_hit, t); | 56 | - if (mmc->fpga_type == FPGA_AN521) { |
317 | t->bh_wd = qemu_bh_new(watchdog_hit, t); | 57 | + if (mc->max_cpus > 1) { |
318 | - t->ptimer_t0 = ptimer_init(t->bh_t0, PTIMER_POLICY_DEFAULT); | 58 | for (i = 0; i < MPS2TZ_NUMIRQ; i++) { |
319 | - t->ptimer_t1 = ptimer_init(t->bh_t1, PTIMER_POLICY_DEFAULT); | 59 | char *name = g_strdup_printf("mps2-irq-splitter%d", i); |
320 | - t->ptimer_wd = ptimer_init(t->bh_wd, PTIMER_POLICY_DEFAULT); | 60 | SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; |
321 | + t->ptimer_t0 = ptimer_init_with_bh(t->bh_t0, PTIMER_POLICY_DEFAULT); | ||
322 | + t->ptimer_t1 = ptimer_init_with_bh(t->bh_t1, PTIMER_POLICY_DEFAULT); | ||
323 | + t->ptimer_wd = ptimer_init_with_bh(t->bh_wd, PTIMER_POLICY_DEFAULT); | ||
324 | |||
325 | sysbus_init_irq(sbd, &t->irq); | ||
326 | sysbus_init_irq(sbd, &t->nmi); | ||
327 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | ||
328 | index XXXXXXX..XXXXXXX 100644 | ||
329 | --- a/hw/timer/exynos4210_mct.c | ||
330 | +++ b/hw/timer/exynos4210_mct.c | ||
331 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_init(Object *obj) | ||
332 | |||
333 | /* Global timer */ | ||
334 | bh[0] = qemu_bh_new(exynos4210_gfrc_event, s); | ||
335 | - s->g_timer.ptimer_frc = ptimer_init(bh[0], PTIMER_POLICY_DEFAULT); | ||
336 | + s->g_timer.ptimer_frc = ptimer_init_with_bh(bh[0], PTIMER_POLICY_DEFAULT); | ||
337 | memset(&s->g_timer.reg, 0, sizeof(struct gregs)); | ||
338 | |||
339 | /* Local timers */ | ||
340 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_init(Object *obj) | ||
341 | bh[0] = qemu_bh_new(exynos4210_ltick_event, &s->l_timer[i]); | ||
342 | bh[1] = qemu_bh_new(exynos4210_lfrc_event, &s->l_timer[i]); | ||
343 | s->l_timer[i].tick_timer.ptimer_tick = | ||
344 | - ptimer_init(bh[0], PTIMER_POLICY_DEFAULT); | ||
345 | - s->l_timer[i].ptimer_frc = ptimer_init(bh[1], PTIMER_POLICY_DEFAULT); | ||
346 | + ptimer_init_with_bh(bh[0], PTIMER_POLICY_DEFAULT); | ||
347 | + s->l_timer[i].ptimer_frc = | ||
348 | + ptimer_init_with_bh(bh[1], PTIMER_POLICY_DEFAULT); | ||
349 | s->l_timer[i].id = i; | ||
350 | } | ||
351 | |||
352 | diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c | ||
353 | index XXXXXXX..XXXXXXX 100644 | ||
354 | --- a/hw/timer/exynos4210_pwm.c | ||
355 | +++ b/hw/timer/exynos4210_pwm.c | ||
356 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_init(Object *obj) | ||
357 | for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { | ||
358 | bh = qemu_bh_new(exynos4210_pwm_tick, &s->timer[i]); | ||
359 | sysbus_init_irq(dev, &s->timer[i].irq); | ||
360 | - s->timer[i].ptimer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
361 | + s->timer[i].ptimer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
362 | s->timer[i].id = i; | ||
363 | s->timer[i].parent = s; | ||
364 | } | ||
365 | diff --git a/hw/timer/exynos4210_rtc.c b/hw/timer/exynos4210_rtc.c | ||
366 | index XXXXXXX..XXXXXXX 100644 | ||
367 | --- a/hw/timer/exynos4210_rtc.c | ||
368 | +++ b/hw/timer/exynos4210_rtc.c | ||
369 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_init(Object *obj) | ||
370 | QEMUBH *bh; | ||
371 | |||
372 | bh = qemu_bh_new(exynos4210_rtc_tick, s); | ||
373 | - s->ptimer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
374 | + s->ptimer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
375 | ptimer_set_freq(s->ptimer, RTC_BASE_FREQ); | ||
376 | exynos4210_rtc_update_freq(s, 0); | ||
377 | |||
378 | bh = qemu_bh_new(exynos4210_rtc_1Hz_tick, s); | ||
379 | - s->ptimer_1Hz = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
380 | + s->ptimer_1Hz = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
381 | ptimer_set_freq(s->ptimer_1Hz, RTC_BASE_FREQ); | ||
382 | |||
383 | sysbus_init_irq(dev, &s->alm_irq); | ||
384 | diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c | ||
385 | index XXXXXXX..XXXXXXX 100644 | ||
386 | --- a/hw/timer/grlib_gptimer.c | ||
387 | +++ b/hw/timer/grlib_gptimer.c | ||
388 | @@ -XXX,XX +XXX,XX @@ static void grlib_gptimer_realize(DeviceState *dev, Error **errp) | ||
389 | |||
390 | timer->unit = unit; | ||
391 | timer->bh = qemu_bh_new(grlib_gptimer_hit, timer); | ||
392 | - timer->ptimer = ptimer_init(timer->bh, PTIMER_POLICY_DEFAULT); | ||
393 | + timer->ptimer = ptimer_init_with_bh(timer->bh, PTIMER_POLICY_DEFAULT); | ||
394 | timer->id = i; | ||
395 | |||
396 | /* One IRQ line for each timer */ | ||
397 | diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c | ||
398 | index XXXXXXX..XXXXXXX 100644 | ||
399 | --- a/hw/timer/imx_epit.c | ||
400 | +++ b/hw/timer/imx_epit.c | ||
401 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_realize(DeviceState *dev, Error **errp) | ||
402 | 0x00001000); | ||
403 | sysbus_init_mmio(sbd, &s->iomem); | ||
404 | |||
405 | - s->timer_reload = ptimer_init(NULL, PTIMER_POLICY_DEFAULT); | ||
406 | + s->timer_reload = ptimer_init_with_bh(NULL, PTIMER_POLICY_DEFAULT); | ||
407 | |||
408 | bh = qemu_bh_new(imx_epit_cmp, s); | ||
409 | - s->timer_cmp = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
410 | + s->timer_cmp = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
411 | } | ||
412 | |||
413 | static void imx_epit_class_init(ObjectClass *klass, void *data) | ||
414 | diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c | ||
415 | index XXXXXXX..XXXXXXX 100644 | ||
416 | --- a/hw/timer/imx_gpt.c | ||
417 | +++ b/hw/timer/imx_gpt.c | ||
418 | @@ -XXX,XX +XXX,XX @@ static void imx_gpt_realize(DeviceState *dev, Error **errp) | ||
419 | sysbus_init_mmio(sbd, &s->iomem); | ||
420 | |||
421 | bh = qemu_bh_new(imx_gpt_timeout, s); | ||
422 | - s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
423 | + s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
424 | } | ||
425 | |||
426 | static void imx_gpt_class_init(ObjectClass *klass, void *data) | ||
427 | diff --git a/hw/timer/lm32_timer.c b/hw/timer/lm32_timer.c | ||
428 | index XXXXXXX..XXXXXXX 100644 | ||
429 | --- a/hw/timer/lm32_timer.c | ||
430 | +++ b/hw/timer/lm32_timer.c | ||
431 | @@ -XXX,XX +XXX,XX @@ static void lm32_timer_realize(DeviceState *dev, Error **errp) | ||
432 | LM32TimerState *s = LM32_TIMER(dev); | ||
433 | |||
434 | s->bh = qemu_bh_new(timer_hit, s); | ||
435 | - s->ptimer = ptimer_init(s->bh, PTIMER_POLICY_DEFAULT); | ||
436 | + s->ptimer = ptimer_init_with_bh(s->bh, PTIMER_POLICY_DEFAULT); | ||
437 | |||
438 | ptimer_set_freq(s->ptimer, s->freq_hz); | ||
439 | } | ||
440 | diff --git a/hw/timer/milkymist-sysctl.c b/hw/timer/milkymist-sysctl.c | ||
441 | index XXXXXXX..XXXXXXX 100644 | ||
442 | --- a/hw/timer/milkymist-sysctl.c | ||
443 | +++ b/hw/timer/milkymist-sysctl.c | ||
444 | @@ -XXX,XX +XXX,XX @@ static void milkymist_sysctl_realize(DeviceState *dev, Error **errp) | ||
445 | |||
446 | s->bh0 = qemu_bh_new(timer0_hit, s); | ||
447 | s->bh1 = qemu_bh_new(timer1_hit, s); | ||
448 | - s->ptimer0 = ptimer_init(s->bh0, PTIMER_POLICY_DEFAULT); | ||
449 | - s->ptimer1 = ptimer_init(s->bh1, PTIMER_POLICY_DEFAULT); | ||
450 | + s->ptimer0 = ptimer_init_with_bh(s->bh0, PTIMER_POLICY_DEFAULT); | ||
451 | + s->ptimer1 = ptimer_init_with_bh(s->bh1, PTIMER_POLICY_DEFAULT); | ||
452 | |||
453 | ptimer_set_freq(s->ptimer0, s->freq_hz); | ||
454 | ptimer_set_freq(s->ptimer1, s->freq_hz); | ||
455 | diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c | ||
456 | index XXXXXXX..XXXXXXX 100644 | ||
457 | --- a/hw/timer/mss-timer.c | ||
458 | +++ b/hw/timer/mss-timer.c | ||
459 | @@ -XXX,XX +XXX,XX @@ static void mss_timer_init(Object *obj) | ||
460 | struct Msf2Timer *st = &t->timers[i]; | ||
461 | |||
462 | st->bh = qemu_bh_new(timer_hit, st); | ||
463 | - st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT); | ||
464 | + st->ptimer = ptimer_init_with_bh(st->bh, PTIMER_POLICY_DEFAULT); | ||
465 | ptimer_set_freq(st->ptimer, t->freq_hz); | ||
466 | sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq); | ||
467 | } | ||
468 | diff --git a/hw/timer/puv3_ost.c b/hw/timer/puv3_ost.c | ||
469 | index XXXXXXX..XXXXXXX 100644 | ||
470 | --- a/hw/timer/puv3_ost.c | ||
471 | +++ b/hw/timer/puv3_ost.c | ||
472 | @@ -XXX,XX +XXX,XX @@ static void puv3_ost_realize(DeviceState *dev, Error **errp) | ||
473 | sysbus_init_irq(sbd, &s->irq); | ||
474 | |||
475 | s->bh = qemu_bh_new(puv3_ost_tick, s); | ||
476 | - s->ptimer = ptimer_init(s->bh, PTIMER_POLICY_DEFAULT); | ||
477 | + s->ptimer = ptimer_init_with_bh(s->bh, PTIMER_POLICY_DEFAULT); | ||
478 | ptimer_set_freq(s->ptimer, 50 * 1000 * 1000); | ||
479 | |||
480 | memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost", | ||
481 | diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c | ||
482 | index XXXXXXX..XXXXXXX 100644 | ||
483 | --- a/hw/timer/sh_timer.c | ||
484 | +++ b/hw/timer/sh_timer.c | ||
485 | @@ -XXX,XX +XXX,XX @@ static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq) | ||
486 | s->irq = irq; | ||
487 | |||
488 | bh = qemu_bh_new(sh_timer_tick, s); | ||
489 | - s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
490 | + s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
491 | |||
492 | sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor); | ||
493 | sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt); | ||
494 | diff --git a/hw/timer/slavio_timer.c b/hw/timer/slavio_timer.c | ||
495 | index XXXXXXX..XXXXXXX 100644 | ||
496 | --- a/hw/timer/slavio_timer.c | ||
497 | +++ b/hw/timer/slavio_timer.c | ||
498 | @@ -XXX,XX +XXX,XX @@ static void slavio_timer_init(Object *obj) | ||
499 | tc->timer_index = i; | ||
500 | |||
501 | bh = qemu_bh_new(slavio_timer_irq, tc); | ||
502 | - s->cputimer[i].timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); | ||
503 | + s->cputimer[i].timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
504 | ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD); | ||
505 | |||
506 | size = i == 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE; | ||
507 | diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c | ||
508 | index XXXXXXX..XXXXXXX 100644 | ||
509 | --- a/hw/timer/xilinx_timer.c | ||
510 | +++ b/hw/timer/xilinx_timer.c | ||
511 | @@ -XXX,XX +XXX,XX @@ static void xilinx_timer_realize(DeviceState *dev, Error **errp) | ||
512 | xt->parent = t; | ||
513 | xt->nr = i; | ||
514 | xt->bh = qemu_bh_new(timer_hit, xt); | ||
515 | - xt->ptimer = ptimer_init(xt->bh, PTIMER_POLICY_DEFAULT); | ||
516 | + xt->ptimer = ptimer_init_with_bh(xt->bh, PTIMER_POLICY_DEFAULT); | ||
517 | ptimer_set_freq(xt->ptimer, t->freq_hz); | ||
518 | } | ||
519 | |||
520 | diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c | ||
521 | index XXXXXXX..XXXXXXX 100644 | ||
522 | --- a/hw/watchdog/cmsdk-apb-watchdog.c | ||
523 | +++ b/hw/watchdog/cmsdk-apb-watchdog.c | ||
524 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) | ||
525 | } | ||
526 | |||
527 | bh = qemu_bh_new(cmsdk_apb_watchdog_tick, s); | ||
528 | - s->timer = ptimer_init(bh, | ||
529 | + s->timer = ptimer_init_with_bh(bh, | ||
530 | PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | | ||
531 | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | | ||
532 | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | | ||
533 | diff --git a/tests/ptimer-test.c b/tests/ptimer-test.c | ||
534 | index XXXXXXX..XXXXXXX 100644 | ||
535 | --- a/tests/ptimer-test.c | ||
536 | +++ b/tests/ptimer-test.c | ||
537 | @@ -XXX,XX +XXX,XX @@ static void check_set_count(gconstpointer arg) | ||
538 | { | ||
539 | const uint8_t *policy = arg; | ||
540 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
541 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
542 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
543 | |||
544 | triggered = false; | ||
545 | |||
546 | @@ -XXX,XX +XXX,XX @@ static void check_set_limit(gconstpointer arg) | ||
547 | { | ||
548 | const uint8_t *policy = arg; | ||
549 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
550 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
551 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
552 | |||
553 | triggered = false; | ||
554 | |||
555 | @@ -XXX,XX +XXX,XX @@ static void check_oneshot(gconstpointer arg) | ||
556 | { | ||
557 | const uint8_t *policy = arg; | ||
558 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
559 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
560 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
561 | bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | ||
562 | |||
563 | triggered = false; | ||
564 | @@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg) | ||
565 | { | ||
566 | const uint8_t *policy = arg; | ||
567 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
568 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
569 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
570 | bool wrap_policy = (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); | ||
571 | bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); | ||
572 | bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD); | ||
573 | @@ -XXX,XX +XXX,XX @@ static void check_on_the_fly_mode_change(gconstpointer arg) | ||
574 | { | ||
575 | const uint8_t *policy = arg; | ||
576 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
577 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
578 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
579 | bool wrap_policy = (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); | ||
580 | bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | ||
581 | |||
582 | @@ -XXX,XX +XXX,XX @@ static void check_on_the_fly_period_change(gconstpointer arg) | ||
583 | { | ||
584 | const uint8_t *policy = arg; | ||
585 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
586 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
587 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
588 | bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | ||
589 | |||
590 | triggered = false; | ||
591 | @@ -XXX,XX +XXX,XX @@ static void check_on_the_fly_freq_change(gconstpointer arg) | ||
592 | { | ||
593 | const uint8_t *policy = arg; | ||
594 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
595 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
596 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
597 | bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | ||
598 | |||
599 | triggered = false; | ||
600 | @@ -XXX,XX +XXX,XX @@ static void check_run_with_period_0(gconstpointer arg) | ||
601 | { | ||
602 | const uint8_t *policy = arg; | ||
603 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
604 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
605 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
606 | |||
607 | triggered = false; | ||
608 | |||
609 | @@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg) | ||
610 | { | ||
611 | const uint8_t *policy = arg; | ||
612 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
613 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
614 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
615 | bool wrap_policy = (*policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD); | ||
616 | bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); | ||
617 | bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD); | ||
618 | @@ -XXX,XX +XXX,XX @@ static void check_periodic_with_load_0(gconstpointer arg) | ||
619 | { | ||
620 | const uint8_t *policy = arg; | ||
621 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
622 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
623 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
624 | bool continuous_trigger = (*policy & PTIMER_POLICY_CONTINUOUS_TRIGGER); | ||
625 | bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); | ||
626 | bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT); | ||
627 | @@ -XXX,XX +XXX,XX @@ static void check_oneshot_with_load_0(gconstpointer arg) | ||
628 | { | ||
629 | const uint8_t *policy = arg; | ||
630 | QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL); | ||
631 | - ptimer_state *ptimer = ptimer_init(bh, *policy); | ||
632 | + ptimer_state *ptimer = ptimer_init_with_bh(bh, *policy); | ||
633 | bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER); | ||
634 | bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT); | ||
635 | |||
636 | -- | 61 | -- |
637 | 2.20.1 | 62 | 2.20.1 |
638 | 63 | ||
639 | 64 | diff view generated by jsdifflib |
1 | Factor out the implementation of SYS_FLEN via the new | 1 | The AN524 has more interrupt lines than the AN505 and AN521; make |
---|---|---|---|
2 | function tables. | 2 | numirq board-specific rather than a compile-time constant. |
3 | |||
4 | Since the difference is small (92 on the current boards and 95 on the | ||
5 | new one) we don't dynamically allocate the cpu_irq_splitter[] array | ||
6 | but leave it as a fixed length array whose size is the maximum needed | ||
7 | for any of the boards. | ||
3 | 8 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
6 | Message-id: 20190916141544.17540-13-peter.maydell@linaro.org | 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
12 | Message-id: 20210215115138.20465-10-peter.maydell@linaro.org | ||
7 | --- | 13 | --- |
8 | target/arm/arm-semi.c | 32 ++++++++++++++++++++++---------- | 14 | hw/arm/mps2-tz.c | 15 ++++++++++----- |
9 | 1 file changed, 22 insertions(+), 10 deletions(-) | 15 | 1 file changed, 10 insertions(+), 5 deletions(-) |
10 | 16 | ||
11 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 17 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
12 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/arm-semi.c | 19 | --- a/hw/arm/mps2-tz.c |
14 | +++ b/target/arm/arm-semi.c | 20 | +++ b/hw/arm/mps2-tz.c |
15 | @@ -XXX,XX +XXX,XX @@ typedef uint32_t sys_readfn(ARMCPU *cpu, GuestFD *gf, | 21 | @@ -XXX,XX +XXX,XX @@ |
16 | typedef uint32_t sys_isattyfn(ARMCPU *cpu, GuestFD *gf); | 22 | #include "hw/qdev-clock.h" |
17 | typedef uint32_t sys_seekfn(ARMCPU *cpu, GuestFD *gf, | 23 | #include "qom/object.h" |
18 | target_ulong offset); | 24 | |
19 | +typedef uint32_t sys_flenfn(ARMCPU *cpu, GuestFD *gf); | 25 | -#define MPS2TZ_NUMIRQ 92 |
20 | 26 | +#define MPS2TZ_NUMIRQ_MAX 92 | |
21 | static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) | 27 | |
28 | typedef enum MPS2TZFPGAType { | ||
29 | FPGA_AN505, | ||
30 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass { | ||
31 | const uint32_t *oscclk; | ||
32 | uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ | ||
33 | bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ | ||
34 | + int numirq; /* Number of external interrupts */ | ||
35 | const char *armsse_type; | ||
36 | }; | ||
37 | |||
38 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState { | ||
39 | SplitIRQ sec_resp_splitter; | ||
40 | qemu_or_irq uart_irq_orgate; | ||
41 | DeviceState *lan9118; | ||
42 | - SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ]; | ||
43 | + SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; | ||
44 | Clock *sysclk; | ||
45 | Clock *s32kclk; | ||
46 | }; | ||
47 | @@ -XXX,XX +XXX,XX @@ static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) | ||
22 | { | 48 | { |
23 | @@ -XXX,XX +XXX,XX @@ static uint32_t host_seekfn(ARMCPU *cpu, GuestFD *gf, target_ulong offset) | 49 | /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ |
24 | return 0; | 50 | MachineClass *mc = MACHINE_GET_CLASS(mms); |
51 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); | ||
52 | |||
53 | - assert(irqno < MPS2TZ_NUMIRQ); | ||
54 | + assert(irqno < mmc->numirq); | ||
55 | |||
56 | if (mc->max_cpus > 1) { | ||
57 | return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); | ||
58 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) | ||
59 | iotkitdev = DEVICE(&mms->iotkit); | ||
60 | object_property_set_link(OBJECT(&mms->iotkit), "memory", | ||
61 | OBJECT(system_memory), &error_abort); | ||
62 | - qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); | ||
63 | + qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); | ||
64 | qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); | ||
65 | qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); | ||
66 | sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); | ||
67 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) | ||
68 | * board. If there is only one CPU, we can just wire the device IRQ | ||
69 | * directly to the SSE's IRQ input. | ||
70 | */ | ||
71 | + assert(mmc->numirq <= MPS2TZ_NUMIRQ_MAX); | ||
72 | if (mc->max_cpus > 1) { | ||
73 | - for (i = 0; i < MPS2TZ_NUMIRQ; i++) { | ||
74 | + for (i = 0; i < mmc->numirq; i++) { | ||
75 | char *name = g_strdup_printf("mps2-irq-splitter%d", i); | ||
76 | SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; | ||
77 | |||
78 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) | ||
79 | mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); | ||
80 | mmc->fpgaio_num_leds = 2; | ||
81 | mmc->fpgaio_has_switches = false; | ||
82 | + mmc->numirq = 92; | ||
83 | mmc->armsse_type = TYPE_IOTKIT; | ||
25 | } | 84 | } |
26 | 85 | ||
27 | +static uint32_t host_flenfn(ARMCPU *cpu, GuestFD *gf) | 86 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) |
28 | +{ | 87 | mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); |
29 | + CPUARMState *env = &cpu->env; | 88 | mmc->fpgaio_num_leds = 2; |
30 | + struct stat buf; | 89 | mmc->fpgaio_has_switches = false; |
31 | + uint32_t ret = set_swi_errno(env, fstat(gf->hostfd, &buf)); | 90 | + mmc->numirq = 92; |
32 | + if (ret == (uint32_t)-1) { | 91 | mmc->armsse_type = TYPE_SSE200; |
33 | + return -1; | ||
34 | + } | ||
35 | + return buf.st_size; | ||
36 | +} | ||
37 | + | ||
38 | static uint32_t gdb_closefn(ARMCPU *cpu, GuestFD *gf) | ||
39 | { | ||
40 | return arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); | ||
41 | @@ -XXX,XX +XXX,XX @@ static uint32_t gdb_seekfn(ARMCPU *cpu, GuestFD *gf, target_ulong offset) | ||
42 | gf->hostfd, offset); | ||
43 | } | 92 | } |
44 | 93 | ||
45 | +static uint32_t gdb_flenfn(ARMCPU *cpu, GuestFD *gf) | ||
46 | +{ | ||
47 | + return arm_gdb_syscall(cpu, arm_semi_flen_cb, "fstat,%x,%x", | ||
48 | + gf->hostfd, arm_flen_buf(cpu)); | ||
49 | +} | ||
50 | + | ||
51 | typedef struct GuestFDFunctions { | ||
52 | sys_closefn *closefn; | ||
53 | sys_writefn *writefn; | ||
54 | sys_readfn *readfn; | ||
55 | sys_isattyfn *isattyfn; | ||
56 | sys_seekfn *seekfn; | ||
57 | + sys_flenfn *flenfn; | ||
58 | } GuestFDFunctions; | ||
59 | |||
60 | static const GuestFDFunctions guestfd_fns[] = { | ||
61 | @@ -XXX,XX +XXX,XX @@ static const GuestFDFunctions guestfd_fns[] = { | ||
62 | .readfn = host_readfn, | ||
63 | .isattyfn = host_isattyfn, | ||
64 | .seekfn = host_seekfn, | ||
65 | + .flenfn = host_flenfn, | ||
66 | }, | ||
67 | [GuestFDGDB] = { | ||
68 | .closefn = gdb_closefn, | ||
69 | @@ -XXX,XX +XXX,XX @@ static const GuestFDFunctions guestfd_fns[] = { | ||
70 | .readfn = gdb_readfn, | ||
71 | .isattyfn = gdb_isattyfn, | ||
72 | .seekfn = gdb_seekfn, | ||
73 | + .flenfn = gdb_flenfn, | ||
74 | }, | ||
75 | }; | ||
76 | |||
77 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
78 | return set_swi_errno(env, -1); | ||
79 | } | ||
80 | |||
81 | - if (use_gdb_syscalls()) { | ||
82 | - return arm_gdb_syscall(cpu, arm_semi_flen_cb, "fstat,%x,%x", | ||
83 | - gf->hostfd, arm_flen_buf(cpu)); | ||
84 | - } else { | ||
85 | - struct stat buf; | ||
86 | - ret = set_swi_errno(env, fstat(gf->hostfd, &buf)); | ||
87 | - if (ret == (uint32_t)-1) | ||
88 | - return -1; | ||
89 | - return buf.st_size; | ||
90 | - } | ||
91 | + return guestfd_fns[gf->type].flenfn(cpu, gf); | ||
92 | case TARGET_SYS_TMPNAM: | ||
93 | qemu_log_mask(LOG_UNIMP, "%s: SYS_TMPNAM not implemented", __func__); | ||
94 | return -1; | ||
95 | -- | 94 | -- |
96 | 2.20.1 | 95 | 2.20.1 |
97 | 96 | ||
98 | 97 | diff view generated by jsdifflib |
1 | Switch the digic-timer.c code away from bottom-half based ptimers to | 1 | The AN524 version of the SCC interface has different behaviour for |
---|---|---|---|
2 | the new transaction-based ptimer API. This just requires adding | 2 | some of the CFG registers; implement it. |
3 | begin/commit calls around the various places that modify the ptimer | 3 | |
4 | state, and using the new ptimer_init() function to create the timer. | 4 | Each board in this family can have minor differences in the meaning |
5 | of the CFG registers, so rather than trying to specify all the | ||
6 | possible semantics via individual device properties, we make the | ||
7 | behaviour conditional on the part-number field of the SCC_ID register | ||
8 | which the board code already passes us. | ||
9 | |||
10 | For the AN524, the differences are: | ||
11 | * CFG3 is reserved rather than being board switches | ||
12 | * CFG5 is a new register ("ACLK Frequency in Hz") | ||
13 | * CFG6 is a new register ("Clock divider for BRAM") | ||
14 | |||
15 | We implement both of the new registers as reads-as-written. | ||
5 | 16 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20191008171740.9679-11-peter.maydell@linaro.org | 19 | Message-id: 20210215115138.20465-11-peter.maydell@linaro.org |
9 | --- | 20 | --- |
10 | hw/timer/digic-timer.c | 16 ++++++++++++++-- | 21 | include/hw/misc/mps2-scc.h | 3 ++ |
11 | 1 file changed, 14 insertions(+), 2 deletions(-) | 22 | hw/misc/mps2-scc.c | 71 ++++++++++++++++++++++++++++++++++++-- |
23 | 2 files changed, 72 insertions(+), 2 deletions(-) | ||
12 | 24 | ||
13 | diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c | 25 | diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h |
14 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/timer/digic-timer.c | 27 | --- a/include/hw/misc/mps2-scc.h |
16 | +++ b/hw/timer/digic-timer.c | 28 | +++ b/include/hw/misc/mps2-scc.h |
29 | @@ -XXX,XX +XXX,XX @@ struct MPS2SCC { | ||
30 | |||
31 | uint32_t cfg0; | ||
32 | uint32_t cfg1; | ||
33 | + uint32_t cfg2; | ||
34 | uint32_t cfg4; | ||
35 | + uint32_t cfg5; | ||
36 | + uint32_t cfg6; | ||
37 | uint32_t cfgdata_rtn; | ||
38 | uint32_t cfgdata_out; | ||
39 | uint32_t cfgctrl; | ||
40 | diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/hw/misc/mps2-scc.c | ||
43 | +++ b/hw/misc/mps2-scc.c | ||
17 | @@ -XXX,XX +XXX,XX @@ | 44 | @@ -XXX,XX +XXX,XX @@ |
18 | #include "qemu/osdep.h" | 45 | |
19 | #include "hw/sysbus.h" | 46 | REG32(CFG0, 0) |
20 | #include "hw/ptimer.h" | 47 | REG32(CFG1, 4) |
21 | -#include "qemu/main-loop.h" | 48 | +REG32(CFG2, 8) |
22 | #include "qemu/module.h" | 49 | REG32(CFG3, 0xc) |
23 | #include "qemu/log.h" | 50 | REG32(CFG4, 0x10) |
24 | 51 | +REG32(CFG5, 0x14) | |
25 | @@ -XXX,XX +XXX,XX @@ static void digic_timer_reset(DeviceState *dev) | 52 | +REG32(CFG6, 0x18) |
26 | { | 53 | REG32(CFGDATA_RTN, 0xa0) |
27 | DigicTimerState *s = DIGIC_TIMER(dev); | 54 | REG32(CFGDATA_OUT, 0xa4) |
28 | 55 | REG32(CFGCTRL, 0xa8) | |
29 | + ptimer_transaction_begin(s->ptimer); | 56 | @@ -XXX,XX +XXX,XX @@ REG32(DLL, 0x100) |
30 | ptimer_stop(s->ptimer); | 57 | REG32(AID, 0xFF8) |
31 | + ptimer_transaction_commit(s->ptimer); | 58 | REG32(ID, 0xFFC) |
32 | s->control = 0; | 59 | |
33 | s->relvalue = 0; | 60 | +static int scc_partno(MPS2SCC *s) |
34 | } | ||
35 | @@ -XXX,XX +XXX,XX @@ static void digic_timer_write(void *opaque, hwaddr offset, | ||
36 | break; | ||
37 | } | ||
38 | |||
39 | + ptimer_transaction_begin(s->ptimer); | ||
40 | if (value & DIGIC_TIMER_CONTROL_EN) { | ||
41 | ptimer_run(s->ptimer, 0); | ||
42 | } | ||
43 | |||
44 | s->control = (uint32_t)value; | ||
45 | + ptimer_transaction_commit(s->ptimer); | ||
46 | break; | ||
47 | |||
48 | case DIGIC_TIMER_RELVALUE: | ||
49 | s->relvalue = extract32(value, 0, 16); | ||
50 | + ptimer_transaction_begin(s->ptimer); | ||
51 | ptimer_set_limit(s->ptimer, s->relvalue, 1); | ||
52 | + ptimer_transaction_commit(s->ptimer); | ||
53 | break; | ||
54 | |||
55 | case DIGIC_TIMER_VALUE: | ||
56 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps digic_timer_ops = { | ||
57 | .endianness = DEVICE_NATIVE_ENDIAN, | ||
58 | }; | ||
59 | |||
60 | +static void digic_timer_tick(void *opaque) | ||
61 | +{ | 61 | +{ |
62 | + /* Nothing to do on timer rollover */ | 62 | + /* Return the partno field of the SCC_ID (0x524, 0x511, etc) */ |
63 | + return extract32(s->id, 4, 8); | ||
63 | +} | 64 | +} |
64 | + | 65 | + |
65 | static void digic_timer_init(Object *obj) | 66 | /* Handle a write via the SYS_CFG channel to the specified function/device. |
66 | { | 67 | * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit). |
67 | DigicTimerState *s = DIGIC_TIMER(obj); | 68 | */ |
68 | 69 | @@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) | |
69 | - s->ptimer = ptimer_init_with_bh(NULL, PTIMER_POLICY_DEFAULT); | 70 | case A_CFG1: |
70 | + s->ptimer = ptimer_init(digic_timer_tick, NULL, PTIMER_POLICY_DEFAULT); | 71 | r = s->cfg1; |
71 | 72 | break; | |
72 | /* | 73 | + case A_CFG2: |
73 | * FIXME: there is no documentation on Digic timer | 74 | + if (scc_partno(s) != 0x524) { |
74 | * frequency setup so let it always run at 1 MHz | 75 | + /* CFG2 reserved on other boards */ |
75 | */ | 76 | + goto bad_offset; |
76 | + ptimer_transaction_begin(s->ptimer); | 77 | + } |
77 | ptimer_set_freq(s->ptimer, 1 * 1000 * 1000); | 78 | + r = s->cfg2; |
78 | + ptimer_transaction_commit(s->ptimer); | 79 | + break; |
79 | 80 | case A_CFG3: | |
80 | memory_region_init_io(&s->iomem, OBJECT(s), &digic_timer_ops, s, | 81 | + if (scc_partno(s) == 0x524) { |
81 | TYPE_DIGIC_TIMER, 0x100); | 82 | + /* CFG3 reserved on AN524 */ |
83 | + goto bad_offset; | ||
84 | + } | ||
85 | /* These are user-settable DIP switches on the board. We don't | ||
86 | * model that, so just return zeroes. | ||
87 | */ | ||
88 | @@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) | ||
89 | case A_CFG4: | ||
90 | r = s->cfg4; | ||
91 | break; | ||
92 | + case A_CFG5: | ||
93 | + if (scc_partno(s) != 0x524) { | ||
94 | + /* CFG5 reserved on other boards */ | ||
95 | + goto bad_offset; | ||
96 | + } | ||
97 | + r = s->cfg5; | ||
98 | + break; | ||
99 | + case A_CFG6: | ||
100 | + if (scc_partno(s) != 0x524) { | ||
101 | + /* CFG6 reserved on other boards */ | ||
102 | + goto bad_offset; | ||
103 | + } | ||
104 | + r = s->cfg6; | ||
105 | + break; | ||
106 | case A_CFGDATA_RTN: | ||
107 | r = s->cfgdata_rtn; | ||
108 | break; | ||
109 | @@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) | ||
110 | r = s->id; | ||
111 | break; | ||
112 | default: | ||
113 | + bad_offset: | ||
114 | qemu_log_mask(LOG_GUEST_ERROR, | ||
115 | "MPS2 SCC read: bad offset %x\n", (int) offset); | ||
116 | r = 0; | ||
117 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, | ||
118 | led_set_state(s->led[i], extract32(value, i, 1)); | ||
119 | } | ||
120 | break; | ||
121 | + case A_CFG2: | ||
122 | + if (scc_partno(s) != 0x524) { | ||
123 | + /* CFG2 reserved on other boards */ | ||
124 | + goto bad_offset; | ||
125 | + } | ||
126 | + /* AN524: QSPI Select signal */ | ||
127 | + s->cfg2 = value; | ||
128 | + break; | ||
129 | + case A_CFG5: | ||
130 | + if (scc_partno(s) != 0x524) { | ||
131 | + /* CFG5 reserved on other boards */ | ||
132 | + goto bad_offset; | ||
133 | + } | ||
134 | + /* AN524: ACLK frequency in Hz */ | ||
135 | + s->cfg5 = value; | ||
136 | + break; | ||
137 | + case A_CFG6: | ||
138 | + if (scc_partno(s) != 0x524) { | ||
139 | + /* CFG6 reserved on other boards */ | ||
140 | + goto bad_offset; | ||
141 | + } | ||
142 | + /* AN524: Clock divider for BRAM */ | ||
143 | + s->cfg6 = value; | ||
144 | + break; | ||
145 | case A_CFGDATA_OUT: | ||
146 | s->cfgdata_out = value; | ||
147 | break; | ||
148 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, | ||
149 | s->dll = deposit32(s->dll, 24, 8, extract32(value, 24, 8)); | ||
150 | break; | ||
151 | default: | ||
152 | + bad_offset: | ||
153 | qemu_log_mask(LOG_GUEST_ERROR, | ||
154 | "MPS2 SCC write: bad offset 0x%x\n", (int) offset); | ||
155 | break; | ||
156 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_reset(DeviceState *dev) | ||
157 | trace_mps2_scc_reset(); | ||
158 | s->cfg0 = 0; | ||
159 | s->cfg1 = 0; | ||
160 | + s->cfg2 = 0; | ||
161 | + s->cfg5 = 0; | ||
162 | + s->cfg6 = 0; | ||
163 | s->cfgdata_rtn = 0; | ||
164 | s->cfgdata_out = 0; | ||
165 | s->cfgctrl = 0x100000; | ||
166 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_realize(DeviceState *dev, Error **errp) | ||
167 | |||
168 | static const VMStateDescription mps2_scc_vmstate = { | ||
169 | .name = "mps2-scc", | ||
170 | - .version_id = 2, | ||
171 | - .minimum_version_id = 2, | ||
172 | + .version_id = 3, | ||
173 | + .minimum_version_id = 3, | ||
174 | .fields = (VMStateField[]) { | ||
175 | VMSTATE_UINT32(cfg0, MPS2SCC), | ||
176 | VMSTATE_UINT32(cfg1, MPS2SCC), | ||
177 | + VMSTATE_UINT32(cfg2, MPS2SCC), | ||
178 | + /* cfg3, cfg4 are read-only so need not be migrated */ | ||
179 | + VMSTATE_UINT32(cfg5, MPS2SCC), | ||
180 | + VMSTATE_UINT32(cfg6, MPS2SCC), | ||
181 | VMSTATE_UINT32(cfgdata_rtn, MPS2SCC), | ||
182 | VMSTATE_UINT32(cfgdata_out, MPS2SCC), | ||
183 | VMSTATE_UINT32(cfgctrl, MPS2SCC), | ||
82 | -- | 184 | -- |
83 | 2.20.1 | 185 | 2.20.1 |
84 | 186 | ||
85 | 187 | diff view generated by jsdifflib |
1 | Switch the cmsdk-apb-watchdog code away from bottom-half based | 1 | On the MPS2 boards, the first 32 interrupt lines are entirely |
---|---|---|---|
2 | ptimers to the new transaction-based ptimer API. This just requires | 2 | internal to the SSE; interrupt lines for devices outside the SSE |
3 | adding begin/commit calls around the various places that modify the | 3 | start at 32. In the application notes that document each FPGA image, |
4 | ptimer state, and using the new ptimer_init() function to create the | 4 | the interrupt wiring is documented from the point of view of the CPU, |
5 | timer. | 5 | so '0' is the first of the SSE's interrupts and the devices in the |
6 | FPGA image itself are '32' and up: so the UART 0 Receive interrupt is | ||
7 | 32, the SPI #0 interrupt is 51, and so on. | ||
8 | |||
9 | Within our implementation, because the external interrupts must be | ||
10 | connected to the EXP_IRQ[0...n] lines of the SSE object, we made the | ||
11 | get_sse_irq_in() function take an irqno whose values start at 0 for | ||
12 | the first FPGA device interrupt. In this numbering scheme the UART 0 | ||
13 | Receive interrupt is 0, the SPI #0 interrupt is 19, and so on. | ||
14 | |||
15 | The result of these two different numbering schemes has been that | ||
16 | half of the devices were wired up to the wrong IRQs: the UART IRQs | ||
17 | are wired up correctly, but the DMA and SPI devices were passing | ||
18 | start-at-32 values to get_sse_irq_in() and so being mis-connected. | ||
19 | |||
20 | Fix the bug by making get_sse_irq_in() take values specified with the | ||
21 | same scheme that the hardware manuals use, to avoid confusion. | ||
6 | 22 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 24 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20191008171740.9679-22-peter.maydell@linaro.org | 25 | Message-id: 20210215115138.20465-12-peter.maydell@linaro.org |
10 | --- | 26 | --- |
11 | hw/net/lan9118.c | 11 +++++++---- | 27 | hw/arm/mps2-tz.c | 24 +++++++++++++++++------- |
12 | 1 file changed, 7 insertions(+), 4 deletions(-) | 28 | 1 file changed, 17 insertions(+), 7 deletions(-) |
13 | 29 | ||
14 | diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c | 30 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
15 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/net/lan9118.c | 32 | --- a/hw/arm/mps2-tz.c |
17 | +++ b/hw/net/lan9118.c | 33 | +++ b/hw/arm/mps2-tz.c |
18 | @@ -XXX,XX +XXX,XX @@ | 34 | @@ -XXX,XX +XXX,XX @@ static void make_ram_alias(MemoryRegion *mr, const char *name, |
19 | #include "hw/ptimer.h" | 35 | |
20 | #include "hw/qdev-properties.h" | 36 | static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) |
21 | #include "qemu/log.h" | ||
22 | -#include "qemu/main-loop.h" | ||
23 | #include "qemu/module.h" | ||
24 | /* For crc32 */ | ||
25 | #include <zlib.h> | ||
26 | @@ -XXX,XX +XXX,XX @@ static void lan9118_reset(DeviceState *d) | ||
27 | s->e2p_data = 0; | ||
28 | s->free_timer_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 40; | ||
29 | |||
30 | + ptimer_transaction_begin(s->timer); | ||
31 | ptimer_stop(s->timer); | ||
32 | ptimer_set_count(s->timer, 0xffff); | ||
33 | + ptimer_transaction_commit(s->timer); | ||
34 | s->gpt_cfg = 0xffff; | ||
35 | |||
36 | s->mac_cr = MAC_CR_PRMS; | ||
37 | @@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset, | ||
38 | break; | ||
39 | case CSR_GPT_CFG: | ||
40 | if ((s->gpt_cfg ^ val) & GPT_TIMER_EN) { | ||
41 | + ptimer_transaction_begin(s->timer); | ||
42 | if (val & GPT_TIMER_EN) { | ||
43 | ptimer_set_count(s->timer, val & 0xffff); | ||
44 | ptimer_run(s->timer, 0); | ||
45 | @@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset, | ||
46 | ptimer_stop(s->timer); | ||
47 | ptimer_set_count(s->timer, 0xffff); | ||
48 | } | ||
49 | + ptimer_transaction_commit(s->timer); | ||
50 | } | ||
51 | s->gpt_cfg = val & (GPT_TIMER_EN | 0xffff); | ||
52 | break; | ||
53 | @@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp) | ||
54 | { | 37 | { |
55 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | 38 | - /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ |
56 | lan9118_state *s = LAN9118(dev); | 39 | + /* |
57 | - QEMUBH *bh; | 40 | + * Return a qemu_irq which will signal IRQ n to all CPUs in the |
58 | int i; | 41 | + * SSE. The irqno should be as the CPU sees it, so the first |
59 | const MemoryRegionOps *mem_ops = | 42 | + * external-to-the-SSE interrupt is 32. |
60 | s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops; | 43 | + */ |
61 | @@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp) | 44 | MachineClass *mc = MACHINE_GET_CLASS(mms); |
62 | s->pmt_ctrl = 1; | 45 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
63 | s->txp = &s->tx_packet; | 46 | |
64 | 47 | - assert(irqno < mmc->numirq); | |
65 | - bh = qemu_bh_new(lan9118_tick, s); | 48 | + assert(irqno >= 32 && irqno < (mmc->numirq + 32)); |
66 | - s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | 49 | + |
67 | + s->timer = ptimer_init(lan9118_tick, s, PTIMER_POLICY_DEFAULT); | 50 | + /* |
68 | + ptimer_transaction_begin(s->timer); | 51 | + * Convert from "CPU irq number" (as listed in the FPGA image |
69 | ptimer_set_freq(s->timer, 10000); | 52 | + * documentation) to the SSE external-interrupt number. |
70 | ptimer_set_limit(s->timer, 0xffff, 1); | 53 | + */ |
71 | + ptimer_transaction_commit(s->timer); | 54 | + irqno -= 32; |
55 | |||
56 | if (mc->max_cpus > 1) { | ||
57 | return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); | ||
58 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, | ||
59 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); | ||
60 | CMSDKAPBUART *uart = opaque; | ||
61 | int i = uart - &mms->uart[0]; | ||
62 | - int rxirqno = i * 2; | ||
63 | - int txirqno = i * 2 + 1; | ||
64 | - int combirqno = i + 10; | ||
65 | + int rxirqno = i * 2 + 32; | ||
66 | + int txirqno = i * 2 + 33; | ||
67 | + int combirqno = i + 42; | ||
68 | SysBusDevice *s; | ||
69 | DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); | ||
70 | |||
71 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, | ||
72 | |||
73 | s = SYS_BUS_DEVICE(mms->lan9118); | ||
74 | sysbus_realize_and_unref(s, &error_fatal); | ||
75 | - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16)); | ||
76 | + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 48)); | ||
77 | return sysbus_mmio_get_region(s, 0); | ||
72 | } | 78 | } |
73 | 79 | ||
74 | static Property lan9118_properties[] = { | 80 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) |
81 | &error_fatal); | ||
82 | qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); | ||
83 | qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, | ||
84 | - get_sse_irq_in(mms, 15)); | ||
85 | + get_sse_irq_in(mms, 47)); | ||
86 | |||
87 | /* Most of the devices in the FPGA are behind Peripheral Protection | ||
88 | * Controllers. The required order for initializing things is: | ||
75 | -- | 89 | -- |
76 | 2.20.1 | 90 | 2.20.1 |
77 | 91 | ||
78 | 92 | diff view generated by jsdifflib |
1 | Switch the imx_epit.c code away from bottom-half based ptimers to | 1 | The mps2-tz code uses PPCPortInfo data structures to define what |
---|---|---|---|
2 | the new transaction-based ptimer API. This just requires adding | 2 | devices are present and how they are wired up. Currently we use |
3 | begin/commit calls around the various places that modify the ptimer | 3 | these to specify device types and addresses, but hard-code the |
4 | state, and using the new ptimer_init() function to create the timer. | 4 | interrupt line wiring in each make_* helper function. This works for |
5 | the two boards we have at the moment, but the AN524 has some devices | ||
6 | with different interrupt assignments. | ||
7 | |||
8 | This commit adds the framework to allow PPCPortInfo structures to | ||
9 | specify interrupt numbers. We add an array of interrupt numbers to | ||
10 | the PPCPortInfo struct, and pass it through to the make_* helpers. | ||
11 | The following commit will change the make_* helpers over to using the | ||
12 | framework. | ||
5 | 13 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 15 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20191008171740.9679-18-peter.maydell@linaro.org | 16 | Message-id: 20210215115138.20465-13-peter.maydell@linaro.org |
9 | --- | 17 | --- |
10 | hw/timer/imx_epit.c | 32 +++++++++++++++++++++++++++----- | 18 | hw/arm/mps2-tz.c | 36 ++++++++++++++++++++++++------------ |
11 | 1 file changed, 27 insertions(+), 5 deletions(-) | 19 | 1 file changed, 24 insertions(+), 12 deletions(-) |
12 | 20 | ||
13 | diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c | 21 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
14 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/timer/imx_epit.c | 23 | --- a/hw/arm/mps2-tz.c |
16 | +++ b/hw/timer/imx_epit.c | 24 | +++ b/hw/arm/mps2-tz.c |
17 | @@ -XXX,XX +XXX,XX @@ | 25 | @@ -XXX,XX +XXX,XX @@ static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) |
18 | #include "migration/vmstate.h" | 26 | * needs to be plugged into the downstream end of the PPC port. |
19 | #include "hw/irq.h" | 27 | */ |
20 | #include "hw/misc/imx_ccm.h" | 28 | typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, |
21 | -#include "qemu/main-loop.h" | 29 | - const char *name, hwaddr size); |
22 | #include "qemu/module.h" | 30 | + const char *name, hwaddr size, |
23 | #include "qemu/log.h" | 31 | + const int *irqs); |
24 | 32 | ||
25 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_update_int(IMXEPITState *s) | 33 | typedef struct PPCPortInfo { |
26 | } | 34 | const char *name; |
35 | @@ -XXX,XX +XXX,XX @@ typedef struct PPCPortInfo { | ||
36 | void *opaque; | ||
37 | hwaddr addr; | ||
38 | hwaddr size; | ||
39 | + int irqs[3]; /* currently no device needs more IRQ lines than this */ | ||
40 | } PPCPortInfo; | ||
41 | |||
42 | typedef struct PPCInfo { | ||
43 | @@ -XXX,XX +XXX,XX @@ typedef struct PPCInfo { | ||
44 | } PPCInfo; | ||
45 | |||
46 | static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, | ||
47 | - void *opaque, | ||
48 | - const char *name, hwaddr size) | ||
49 | + void *opaque, | ||
50 | + const char *name, hwaddr size, | ||
51 | + const int *irqs) | ||
52 | { | ||
53 | /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, | ||
54 | * and return a pointer to its MemoryRegion. | ||
55 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, | ||
27 | } | 56 | } |
28 | 57 | ||
29 | +/* | 58 | static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, |
30 | + * Must be called from within a ptimer_transaction_begin/commit block | 59 | - const char *name, hwaddr size) |
31 | + * for both s->timer_cmp and s->timer_reload. | 60 | + const char *name, hwaddr size, |
32 | + */ | 61 | + const int *irqs) |
33 | static void imx_epit_set_freq(IMXEPITState *s) | ||
34 | { | 62 | { |
35 | uint32_t clksrc; | 63 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
36 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_reset(DeviceState *dev) | 64 | CMSDKAPBUART *uart = opaque; |
37 | s->lr = EPIT_TIMER_MAX; | 65 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, |
38 | s->cmp = 0; | ||
39 | s->cnt = 0; | ||
40 | + ptimer_transaction_begin(s->timer_cmp); | ||
41 | + ptimer_transaction_begin(s->timer_reload); | ||
42 | /* stop both timers */ | ||
43 | ptimer_stop(s->timer_cmp); | ||
44 | ptimer_stop(s->timer_reload); | ||
45 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_reset(DeviceState *dev) | ||
46 | /* if the timer is still enabled, restart it */ | ||
47 | ptimer_run(s->timer_reload, 0); | ||
48 | } | ||
49 | + ptimer_transaction_commit(s->timer_cmp); | ||
50 | + ptimer_transaction_commit(s->timer_reload); | ||
51 | } | 66 | } |
52 | 67 | ||
53 | static uint32_t imx_epit_update_count(IMXEPITState *s) | 68 | static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, |
54 | @@ -XXX,XX +XXX,XX @@ static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size) | 69 | - const char *name, hwaddr size) |
55 | return reg_value; | 70 | + const char *name, hwaddr size, |
71 | + const int *irqs) | ||
72 | { | ||
73 | MPS2SCC *scc = opaque; | ||
74 | DeviceState *sccdev; | ||
75 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, | ||
56 | } | 76 | } |
57 | 77 | ||
58 | +/* Must be called from ptimer_transaction_begin/commit block for s->timer_cmp */ | 78 | static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, |
59 | static void imx_epit_reload_compare_timer(IMXEPITState *s) | 79 | - const char *name, hwaddr size) |
80 | + const char *name, hwaddr size, | ||
81 | + const int *irqs) | ||
60 | { | 82 | { |
61 | if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) { | 83 | MPS2FPGAIO *fpgaio = opaque; |
62 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, | 84 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
63 | 85 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, | |
64 | switch (offset >> 2) { | ||
65 | case 0: /* CR */ | ||
66 | + ptimer_transaction_begin(s->timer_cmp); | ||
67 | + ptimer_transaction_begin(s->timer_reload); | ||
68 | |||
69 | oldcr = s->cr; | ||
70 | s->cr = value & 0x03ffffff; | ||
71 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, | ||
72 | } else { | ||
73 | ptimer_stop(s->timer_cmp); | ||
74 | } | ||
75 | + | ||
76 | + ptimer_transaction_commit(s->timer_cmp); | ||
77 | + ptimer_transaction_commit(s->timer_reload); | ||
78 | break; | ||
79 | |||
80 | case 1: /* SR - ACK*/ | ||
81 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, | ||
82 | case 2: /* LR - set ticks */ | ||
83 | s->lr = value; | ||
84 | |||
85 | + ptimer_transaction_begin(s->timer_cmp); | ||
86 | + ptimer_transaction_begin(s->timer_reload); | ||
87 | if (s->cr & CR_RLD) { | ||
88 | /* Also set the limit if the LRD bit is set */ | ||
89 | /* If IOVW bit is set then set the timer value */ | ||
90 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, | ||
91 | } | ||
92 | |||
93 | imx_epit_reload_compare_timer(s); | ||
94 | + ptimer_transaction_commit(s->timer_cmp); | ||
95 | + ptimer_transaction_commit(s->timer_reload); | ||
96 | break; | ||
97 | |||
98 | case 3: /* CMP */ | ||
99 | s->cmp = value; | ||
100 | |||
101 | + ptimer_transaction_begin(s->timer_cmp); | ||
102 | imx_epit_reload_compare_timer(s); | ||
103 | + ptimer_transaction_commit(s->timer_cmp); | ||
104 | |||
105 | break; | ||
106 | |||
107 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_cmp(void *opaque) | ||
108 | imx_epit_update_int(s); | ||
109 | } | 86 | } |
110 | 87 | ||
111 | +static void imx_epit_reload(void *opaque) | 88 | static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, |
112 | +{ | 89 | - const char *name, hwaddr size) |
113 | + /* No action required on rollover of timer_reload */ | 90 | + const char *name, hwaddr size, |
114 | +} | 91 | + const int *irqs) |
115 | + | ||
116 | static const MemoryRegionOps imx_epit_ops = { | ||
117 | .read = imx_epit_read, | ||
118 | .write = imx_epit_write, | ||
119 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_realize(DeviceState *dev, Error **errp) | ||
120 | { | 92 | { |
121 | IMXEPITState *s = IMX_EPIT(dev); | 93 | SysBusDevice *s; |
122 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | 94 | NICInfo *nd = &nd_table[0]; |
123 | - QEMUBH *bh; | 95 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, |
124 | |||
125 | DPRINTF("\n"); | ||
126 | |||
127 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_realize(DeviceState *dev, Error **errp) | ||
128 | 0x00001000); | ||
129 | sysbus_init_mmio(sbd, &s->iomem); | ||
130 | |||
131 | - s->timer_reload = ptimer_init_with_bh(NULL, PTIMER_POLICY_DEFAULT); | ||
132 | + s->timer_reload = ptimer_init(imx_epit_reload, s, PTIMER_POLICY_DEFAULT); | ||
133 | |||
134 | - bh = qemu_bh_new(imx_epit_cmp, s); | ||
135 | - s->timer_cmp = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
136 | + s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_DEFAULT); | ||
137 | } | 96 | } |
138 | 97 | ||
139 | static void imx_epit_class_init(ObjectClass *klass, void *data) | 98 | static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, |
99 | - const char *name, hwaddr size) | ||
100 | + const char *name, hwaddr size, | ||
101 | + const int *irqs) | ||
102 | { | ||
103 | TZMPC *mpc = opaque; | ||
104 | int i = mpc - &mms->ssram_mpc[0]; | ||
105 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, | ||
106 | } | ||
107 | |||
108 | static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, | ||
109 | - const char *name, hwaddr size) | ||
110 | + const char *name, hwaddr size, | ||
111 | + const int *irqs) | ||
112 | { | ||
113 | PL080State *dma = opaque; | ||
114 | int i = dma - &mms->dma[0]; | ||
115 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, | ||
116 | } | ||
117 | |||
118 | static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, | ||
119 | - const char *name, hwaddr size) | ||
120 | + const char *name, hwaddr size, | ||
121 | + const int *irqs) | ||
122 | { | ||
123 | /* | ||
124 | * The AN505 has five PL022 SPI controllers. | ||
125 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, | ||
126 | } | ||
127 | |||
128 | static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, | ||
129 | - const char *name, hwaddr size) | ||
130 | + const char *name, hwaddr size, | ||
131 | + const int *irqs) | ||
132 | { | ||
133 | ArmSbconI2CState *i2c = opaque; | ||
134 | SysBusDevice *s; | ||
135 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) | ||
136 | continue; | ||
137 | } | ||
138 | |||
139 | - mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); | ||
140 | + mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size, | ||
141 | + pinfo->irqs); | ||
142 | portname = g_strdup_printf("port[%d]", port); | ||
143 | object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), | ||
144 | &error_fatal); | ||
140 | -- | 145 | -- |
141 | 2.20.1 | 146 | 2.20.1 |
142 | 147 | ||
143 | 148 | diff view generated by jsdifflib |
1 | Switch the cmsdk-apb-timer code away from bottom-half based ptimers | 1 | Move the specification of the IRQ information for the uart, ethernet, |
---|---|---|---|
2 | to the new transaction-based ptimer API. This just requires adding | 2 | dma and spi devices to the data structures. (The other devices |
3 | begin/commit calls around the various places that modify the ptimer | 3 | handled by the PPCPortInfo structures don't have any interrupt lines |
4 | state, and using the new ptimer_init() function to create the timer. | 4 | we need to wire up.) |
5 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20191008171740.9679-10-peter.maydell@linaro.org | 8 | Message-id: 20210215115138.20465-14-peter.maydell@linaro.org |
9 | --- | 9 | --- |
10 | hw/timer/cmsdk-apb-timer.c | 15 +++++++++++---- | 10 | hw/arm/mps2-tz.c | 52 +++++++++++++++++++++++------------------------- |
11 | 1 file changed, 11 insertions(+), 4 deletions(-) | 11 | 1 file changed, 25 insertions(+), 27 deletions(-) |
12 | 12 | ||
13 | diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c | 13 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
14 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/timer/cmsdk-apb-timer.c | 15 | --- a/hw/arm/mps2-tz.c |
16 | +++ b/hw/timer/cmsdk-apb-timer.c | 16 | +++ b/hw/arm/mps2-tz.c |
17 | @@ -XXX,XX +XXX,XX @@ | 17 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, |
18 | 18 | const char *name, hwaddr size, | |
19 | #include "qemu/osdep.h" | 19 | const int *irqs) |
20 | #include "qemu/log.h" | 20 | { |
21 | -#include "qemu/main-loop.h" | 21 | + /* The irq[] array is tx, rx, combined, in that order */ |
22 | #include "qemu/module.h" | 22 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
23 | #include "qapi/error.h" | 23 | CMSDKAPBUART *uart = opaque; |
24 | #include "trace.h" | 24 | int i = uart - &mms->uart[0]; |
25 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value, | 25 | - int rxirqno = i * 2 + 32; |
26 | "CMSDK APB timer: EXTIN input not supported\n"); | 26 | - int txirqno = i * 2 + 33; |
27 | } | 27 | - int combirqno = i + 42; |
28 | s->ctrl = value & 0xf; | 28 | SysBusDevice *s; |
29 | + ptimer_transaction_begin(s->timer); | 29 | DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); |
30 | if (s->ctrl & R_CTRL_EN_MASK) { | 30 | |
31 | ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0); | 31 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, |
32 | } else { | 32 | qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->sysclk_frq); |
33 | ptimer_stop(s->timer); | 33 | sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); |
34 | } | 34 | s = SYS_BUS_DEVICE(uart); |
35 | + ptimer_transaction_commit(s->timer); | 35 | - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno)); |
36 | break; | 36 | - sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno)); |
37 | case A_RELOAD: | 37 | + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); |
38 | /* Writing to reload also sets the current timer value */ | 38 | + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); |
39 | + ptimer_transaction_begin(s->timer); | 39 | sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); |
40 | if (!value) { | 40 | sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); |
41 | ptimer_stop(s->timer); | 41 | - sysbus_connect_irq(s, 4, get_sse_irq_in(mms, combirqno)); |
42 | } | 42 | + sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2])); |
43 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value, | 43 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); |
44 | */ | ||
45 | ptimer_run(s->timer, 0); | ||
46 | } | ||
47 | + ptimer_transaction_commit(s->timer); | ||
48 | break; | ||
49 | case A_VALUE: | ||
50 | + ptimer_transaction_begin(s->timer); | ||
51 | if (!value && !ptimer_get_limit(s->timer)) { | ||
52 | ptimer_stop(s->timer); | ||
53 | } | ||
54 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value, | ||
55 | if (value && (s->ctrl & R_CTRL_EN_MASK)) { | ||
56 | ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0); | ||
57 | } | ||
58 | + ptimer_transaction_commit(s->timer); | ||
59 | break; | ||
60 | case A_INTSTATUS: | ||
61 | /* Just one bit, which is W1C. */ | ||
62 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_reset(DeviceState *dev) | ||
63 | trace_cmsdk_apb_timer_reset(); | ||
64 | s->ctrl = 0; | ||
65 | s->intstatus = 0; | ||
66 | + ptimer_transaction_begin(s->timer); | ||
67 | ptimer_stop(s->timer); | ||
68 | /* Set the limit and the count */ | ||
69 | ptimer_set_limit(s->timer, 0, 1); | ||
70 | + ptimer_transaction_commit(s->timer); | ||
71 | } | 44 | } |
72 | 45 | ||
73 | static void cmsdk_apb_timer_init(Object *obj) | 46 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, |
74 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_init(Object *obj) | 47 | |
75 | static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) | 48 | s = SYS_BUS_DEVICE(mms->lan9118); |
49 | sysbus_realize_and_unref(s, &error_fatal); | ||
50 | - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 48)); | ||
51 | + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); | ||
52 | return sysbus_mmio_get_region(s, 0); | ||
53 | } | ||
54 | |||
55 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, | ||
56 | const char *name, hwaddr size, | ||
57 | const int *irqs) | ||
76 | { | 58 | { |
77 | CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev); | 59 | + /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */ |
78 | - QEMUBH *bh; | 60 | PL080State *dma = opaque; |
79 | 61 | int i = dma - &mms->dma[0]; | |
80 | if (s->pclk_frq == 0) { | 62 | SysBusDevice *s; |
81 | error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); | 63 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, |
82 | return; | 64 | |
83 | } | 65 | s = SYS_BUS_DEVICE(dma); |
84 | 66 | /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ | |
85 | - bh = qemu_bh_new(cmsdk_apb_timer_tick, s); | 67 | - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 58 + i * 3)); |
86 | - s->timer = ptimer_init_with_bh(bh, | 68 | - sysbus_connect_irq(s, 1, get_sse_irq_in(mms, 56 + i * 3)); |
87 | + s->timer = ptimer_init(cmsdk_apb_timer_tick, s, | 69 | - sysbus_connect_irq(s, 2, get_sse_irq_in(mms, 57 + i * 3)); |
88 | PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | | 70 | + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); |
89 | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | | 71 | + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); |
90 | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | | 72 | + sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqs[2])); |
91 | PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | 73 | |
92 | 74 | g_free(mscname); | |
93 | + ptimer_transaction_begin(s->timer); | 75 | return sysbus_mmio_get_region(s, 0); |
94 | ptimer_set_freq(s->timer, s->pclk_frq); | 76 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, |
95 | + ptimer_transaction_commit(s->timer); | 77 | * lines are set via the "MISC" register in the MPS2 FPGAIO device. |
78 | */ | ||
79 | PL022State *spi = opaque; | ||
80 | - int i = spi - &mms->spi[0]; | ||
81 | SysBusDevice *s; | ||
82 | |||
83 | object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022); | ||
84 | sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal); | ||
85 | s = SYS_BUS_DEVICE(spi); | ||
86 | - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i)); | ||
87 | + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); | ||
88 | return sysbus_mmio_get_region(s, 0); | ||
96 | } | 89 | } |
97 | 90 | ||
98 | static const VMStateDescription cmsdk_apb_timer_vmstate = { | 91 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) |
92 | }, { | ||
93 | .name = "apb_ppcexp1", | ||
94 | .ports = { | ||
95 | - { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000 }, | ||
96 | - { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000 }, | ||
97 | - { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000 }, | ||
98 | - { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000 }, | ||
99 | - { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000 }, | ||
100 | - { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 }, | ||
101 | - { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 }, | ||
102 | - { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, | ||
103 | - { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, | ||
104 | - { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, | ||
105 | + { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000, { 51 } }, | ||
106 | + { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000, { 52 } }, | ||
107 | + { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000, { 53 } }, | ||
108 | + { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000, { 54 } }, | ||
109 | + { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000, { 55 } }, | ||
110 | + { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000, { 32, 33, 42 } }, | ||
111 | + { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000, { 34, 35, 43 } }, | ||
112 | + { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000, { 36, 37, 44 } }, | ||
113 | + { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000, { 38, 39, 45 } }, | ||
114 | + { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000, { 40, 41, 46 } }, | ||
115 | { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 }, | ||
116 | { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 }, | ||
117 | { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 }, | ||
118 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) | ||
119 | { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, | ||
120 | { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, | ||
121 | { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, | ||
122 | - { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 }, | ||
123 | + { "eth", make_eth_dev, NULL, 0x42000000, 0x100000, { 48 } }, | ||
124 | }, | ||
125 | }, { | ||
126 | .name = "ahb_ppcexp1", | ||
127 | .ports = { | ||
128 | - { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000 }, | ||
129 | - { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000 }, | ||
130 | - { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000 }, | ||
131 | - { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000 }, | ||
132 | + { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000, { 58, 56, 57 } }, | ||
133 | + { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000, { 61, 59, 60 } }, | ||
134 | + { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000, { 64, 62, 63 } }, | ||
135 | + { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000, { 67, 65, 66 } }, | ||
136 | }, | ||
137 | }, | ||
138 | }; | ||
99 | -- | 139 | -- |
100 | 2.20.1 | 140 | 2.20.1 |
101 | 141 | ||
102 | 142 | diff view generated by jsdifflib |
1 | In arm_gdb_syscall() we have a comment suggesting a race | 1 | We create an OR gate to wire together the overflow IRQs for all the |
---|---|---|---|
2 | because the syscall completion callback might not happen | 2 | UARTs on the board; this has to have twice the number of inputs as |
3 | before the gdb_do_syscallv() call returns. The comment is | 3 | there are UARTs, since each UART feeds it a TX overflow and an RX |
4 | correct that the callback may not happen but incorrect about | 4 | overflow interrupt line. Replace the hardcoded '10' with a |
5 | the effects. Correct it and note the important caveat that | 5 | calculation based on the size of the uart[] array in the |
6 | callers must never do any work of any kind after return from | 6 | MPS2TZMachineState. (We rely on OR gate inputs that are never wired |
7 | arm_gdb_syscall() that depends on its return value. | 7 | up or asserted being treated as always-zero.) |
8 | 8 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Message-id: 20190916141544.17540-4-peter.maydell@linaro.org | 11 | Message-id: 20210215115138.20465-15-peter.maydell@linaro.org |
12 | --- | 12 | --- |
13 | target/arm/arm-semi.c | 19 +++++++++++++++---- | 13 | hw/arm/mps2-tz.c | 11 ++++++++--- |
14 | 1 file changed, 15 insertions(+), 4 deletions(-) | 14 | 1 file changed, 8 insertions(+), 3 deletions(-) |
15 | 15 | ||
16 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 16 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/arm-semi.c | 18 | --- a/hw/arm/mps2-tz.c |
19 | +++ b/target/arm/arm-semi.c | 19 | +++ b/hw/arm/mps2-tz.c |
20 | @@ -XXX,XX +XXX,XX @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, | 20 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) |
21 | gdb_do_syscallv(cb, fmt, va); | 21 | */ |
22 | va_end(va); | 22 | memory_region_add_subregion(system_memory, 0x80000000, machine->ram); |
23 | 23 | ||
24 | - /* FIXME: we are implicitly relying on the syscall completing | 24 | - /* The overflow IRQs for all UARTs are ORed together. |
25 | - * before this point, which is not guaranteed. We should | ||
26 | - * put in an explicit synchronization between this and | ||
27 | - * the callback function. | ||
28 | + /* | 25 | + /* |
29 | + * FIXME: in softmmu mode, the gdbstub will schedule our callback | 26 | + * The overflow IRQs for all UARTs are ORed together. |
30 | + * to occur, but will not actually call it to complete the syscall | 27 | * Tx, Rx and "combined" IRQs are sent to the NVIC separately. |
31 | + * until after this function has returned and we are back in the | 28 | - * Create the OR gate for this. |
32 | + * CPU main loop. Therefore callers to this function must not | 29 | + * Create the OR gate for this: it has one input for the TX overflow |
33 | + * do anything with its return value, because it is not necessarily | 30 | + * and one for the RX overflow for each UART we might have. |
34 | + * the result of the syscall, but could just be the old value of X0. | 31 | + * (If the board has fewer than the maximum possible number of UARTs |
35 | + * The only thing safe to do with this is that the callers of | 32 | + * those inputs are never wired up and are treated as always-zero.) |
36 | + * do_arm_semihosting() will write it straight back into X0. | ||
37 | + * (In linux-user mode, the callback will have happened before | ||
38 | + * gdb_do_syscallv() returns.) | ||
39 | + * | ||
40 | + * We should tidy this up so neither this function nor | ||
41 | + * do_arm_semihosting() return a value, so the mistake of | ||
42 | + * doing something with the return value is not possible to make. | ||
43 | */ | 33 | */ |
44 | 34 | object_initialize_child(OBJECT(mms), "uart-irq-orgate", | |
45 | return is_a64(env) ? env->xregs[0] : env->regs[0]; | 35 | &mms->uart_irq_orgate, TYPE_OR_IRQ); |
36 | - object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", 10, | ||
37 | + object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", | ||
38 | + 2 * ARRAY_SIZE(mms->uart), | ||
39 | &error_fatal); | ||
40 | qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); | ||
41 | qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, | ||
46 | -- | 42 | -- |
47 | 2.20.1 | 43 | 2.20.1 |
48 | 44 | ||
49 | 45 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | The AN505 and AN521 have the same device layout, but the AN524 is |
---|---|---|---|
2 | somewhat different. Allow for more than one PPCInfo array, which can | ||
3 | be selected based on the board type. | ||
2 | 4 | ||
3 | The AST2600 SoC has an extra controller to set the PHY registers. | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20210215115138.20465-16-peter.maydell@linaro.org | ||
8 | --- | ||
9 | hw/arm/mps2-tz.c | 16 ++++++++++++++-- | ||
10 | 1 file changed, 14 insertions(+), 2 deletions(-) | ||
4 | 11 | ||
5 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 12 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
6 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
7 | Message-id: 20190925143248.10000-23-clg@kaod.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | include/hw/arm/aspeed_soc.h | 5 ++ | ||
11 | include/hw/net/ftgmac100.h | 17 ++++ | ||
12 | hw/arm/aspeed_ast2600.c | 20 +++++ | ||
13 | hw/net/ftgmac100.c | 162 ++++++++++++++++++++++++++++++++++++ | ||
14 | 4 files changed, 204 insertions(+) | ||
15 | |||
16 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/aspeed_soc.h | 14 | --- a/hw/arm/mps2-tz.c |
19 | +++ b/include/hw/arm/aspeed_soc.h | 15 | +++ b/hw/arm/mps2-tz.c |
20 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState { | 16 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) |
21 | AspeedSDMCState sdmc; | 17 | MemoryRegion *system_memory = get_system_memory(); |
22 | AspeedWDTState wdt[ASPEED_WDTS_NUM]; | 18 | DeviceState *iotkitdev; |
23 | FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; | 19 | DeviceState *dev_splitter; |
24 | + AspeedMiiState mii[ASPEED_MACS_NUM]; | 20 | + const PPCInfo *ppcs; |
25 | AspeedGPIOState gpio; | 21 | + int num_ppcs; |
26 | AspeedGPIOState gpio_1_8v; | 22 | int i; |
27 | AspeedSDHCIState sdhci; | 23 | |
28 | @@ -XXX,XX +XXX,XX @@ enum { | 24 | if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { |
29 | ASPEED_ETH2, | 25 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) |
30 | ASPEED_ETH3, | 26 | * + wire up the PPC's control lines to the IoTKit object |
31 | ASPEED_ETH4, | 27 | */ |
32 | + ASPEED_MII1, | 28 | |
33 | + ASPEED_MII2, | 29 | - const PPCInfo ppcs[] = { { |
34 | + ASPEED_MII3, | 30 | + const PPCInfo an505_ppcs[] = { { |
35 | + ASPEED_MII4, | 31 | .name = "apb_ppcexp0", |
36 | ASPEED_SDRAM, | 32 | .ports = { |
37 | ASPEED_XDMA, | 33 | { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 }, |
38 | }; | 34 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) |
39 | diff --git a/include/hw/net/ftgmac100.h b/include/hw/net/ftgmac100.h | 35 | }, |
40 | index XXXXXXX..XXXXXXX 100644 | 36 | }; |
41 | --- a/include/hw/net/ftgmac100.h | 37 | |
42 | +++ b/include/hw/net/ftgmac100.h | 38 | - for (i = 0; i < ARRAY_SIZE(ppcs); i++) { |
43 | @@ -XXX,XX +XXX,XX @@ typedef struct FTGMAC100State { | 39 | + switch (mmc->fpga_type) { |
44 | uint32_t rxdes0_edorr; | 40 | + case FPGA_AN505: |
45 | } FTGMAC100State; | 41 | + case FPGA_AN521: |
46 | 42 | + ppcs = an505_ppcs; | |
47 | +#define TYPE_ASPEED_MII "aspeed-mmi" | 43 | + num_ppcs = ARRAY_SIZE(an505_ppcs); |
48 | +#define ASPEED_MII(obj) OBJECT_CHECK(AspeedMiiState, (obj), TYPE_ASPEED_MII) | ||
49 | + | ||
50 | +/* | ||
51 | + * AST2600 MII controller | ||
52 | + */ | ||
53 | +typedef struct AspeedMiiState { | ||
54 | + /*< private >*/ | ||
55 | + SysBusDevice parent_obj; | ||
56 | + | ||
57 | + FTGMAC100State *nic; | ||
58 | + | ||
59 | + MemoryRegion iomem; | ||
60 | + uint32_t phycr; | ||
61 | + uint32_t phydata; | ||
62 | +} AspeedMiiState; | ||
63 | + | ||
64 | #endif | ||
65 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c | ||
66 | index XXXXXXX..XXXXXXX 100644 | ||
67 | --- a/hw/arm/aspeed_ast2600.c | ||
68 | +++ b/hw/arm/aspeed_ast2600.c | ||
69 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { | ||
70 | [ASPEED_FMC] = 0x1E620000, | ||
71 | [ASPEED_SPI1] = 0x1E630000, | ||
72 | [ASPEED_SPI2] = 0x1E641000, | ||
73 | + [ASPEED_MII1] = 0x1E650000, | ||
74 | + [ASPEED_MII2] = 0x1E650008, | ||
75 | + [ASPEED_MII3] = 0x1E650010, | ||
76 | + [ASPEED_MII4] = 0x1E650018, | ||
77 | [ASPEED_ETH1] = 0x1E660000, | ||
78 | [ASPEED_ETH3] = 0x1E670000, | ||
79 | [ASPEED_ETH2] = 0x1E680000, | ||
80 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj) | ||
81 | for (i = 0; i < sc->macs_num; i++) { | ||
82 | sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]), | ||
83 | sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); | ||
84 | + | ||
85 | + sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]), | ||
86 | + TYPE_ASPEED_MII); | ||
87 | + object_property_add_const_link(OBJECT(&s->mii[i]), "nic", | ||
88 | + OBJECT(&s->ftgmac100[i]), | ||
89 | + &error_abort); | ||
90 | } | ||
91 | |||
92 | sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma), | ||
93 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | ||
94 | sc->memmap[ASPEED_ETH1 + i]); | ||
95 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | ||
96 | aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); | ||
97 | + | ||
98 | + object_property_set_bool(OBJECT(&s->mii[i]), true, "realized", | ||
99 | + &err); | ||
100 | + if (err) { | ||
101 | + error_propagate(errp, err); | ||
102 | + return; | ||
103 | + } | ||
104 | + | ||
105 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, | ||
106 | + sc->memmap[ASPEED_MII1 + i]); | ||
107 | } | ||
108 | |||
109 | /* XDMA */ | ||
110 | diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c | ||
111 | index XXXXXXX..XXXXXXX 100644 | ||
112 | --- a/hw/net/ftgmac100.c | ||
113 | +++ b/hw/net/ftgmac100.c | ||
114 | @@ -XXX,XX +XXX,XX @@ | ||
115 | #include "hw/irq.h" | ||
116 | #include "hw/net/ftgmac100.h" | ||
117 | #include "sysemu/dma.h" | ||
118 | +#include "qapi/error.h" | ||
119 | #include "qemu/log.h" | ||
120 | #include "qemu/module.h" | ||
121 | #include "net/checksum.h" | ||
122 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo ftgmac100_info = { | ||
123 | .class_init = ftgmac100_class_init, | ||
124 | }; | ||
125 | |||
126 | +/* | ||
127 | + * AST2600 MII controller | ||
128 | + */ | ||
129 | +#define ASPEED_MII_PHYCR_FIRE BIT(31) | ||
130 | +#define ASPEED_MII_PHYCR_ST_22 BIT(28) | ||
131 | +#define ASPEED_MII_PHYCR_OP(x) ((x) & (ASPEED_MII_PHYCR_OP_WRITE | \ | ||
132 | + ASPEED_MII_PHYCR_OP_READ)) | ||
133 | +#define ASPEED_MII_PHYCR_OP_WRITE BIT(26) | ||
134 | +#define ASPEED_MII_PHYCR_OP_READ BIT(27) | ||
135 | +#define ASPEED_MII_PHYCR_DATA(x) (x & 0xffff) | ||
136 | +#define ASPEED_MII_PHYCR_PHY(x) (((x) >> 21) & 0x1f) | ||
137 | +#define ASPEED_MII_PHYCR_REG(x) (((x) >> 16) & 0x1f) | ||
138 | + | ||
139 | +#define ASPEED_MII_PHYDATA_IDLE BIT(16) | ||
140 | + | ||
141 | +static void aspeed_mii_transition(AspeedMiiState *s, bool fire) | ||
142 | +{ | ||
143 | + if (fire) { | ||
144 | + s->phycr |= ASPEED_MII_PHYCR_FIRE; | ||
145 | + s->phydata &= ~ASPEED_MII_PHYDATA_IDLE; | ||
146 | + } else { | ||
147 | + s->phycr &= ~ASPEED_MII_PHYCR_FIRE; | ||
148 | + s->phydata |= ASPEED_MII_PHYDATA_IDLE; | ||
149 | + } | ||
150 | +} | ||
151 | + | ||
152 | +static void aspeed_mii_do_phy_ctl(AspeedMiiState *s) | ||
153 | +{ | ||
154 | + uint8_t reg; | ||
155 | + uint16_t data; | ||
156 | + | ||
157 | + if (!(s->phycr & ASPEED_MII_PHYCR_ST_22)) { | ||
158 | + aspeed_mii_transition(s, !ASPEED_MII_PHYCR_FIRE); | ||
159 | + qemu_log_mask(LOG_UNIMP, "%s: unsupported ST code\n", __func__); | ||
160 | + return; | ||
161 | + } | ||
162 | + | ||
163 | + /* Nothing to do */ | ||
164 | + if (!(s->phycr & ASPEED_MII_PHYCR_FIRE)) { | ||
165 | + return; | ||
166 | + } | ||
167 | + | ||
168 | + reg = ASPEED_MII_PHYCR_REG(s->phycr); | ||
169 | + data = ASPEED_MII_PHYCR_DATA(s->phycr); | ||
170 | + | ||
171 | + switch (ASPEED_MII_PHYCR_OP(s->phycr)) { | ||
172 | + case ASPEED_MII_PHYCR_OP_WRITE: | ||
173 | + do_phy_write(s->nic, reg, data); | ||
174 | + break; | ||
175 | + case ASPEED_MII_PHYCR_OP_READ: | ||
176 | + s->phydata = (s->phydata & ~0xffff) | do_phy_read(s->nic, reg); | ||
177 | + break; | ||
178 | + default: | ||
179 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid OP code %08x\n", | ||
180 | + __func__, s->phycr); | ||
181 | + } | ||
182 | + | ||
183 | + aspeed_mii_transition(s, !ASPEED_MII_PHYCR_FIRE); | ||
184 | +} | ||
185 | + | ||
186 | +static uint64_t aspeed_mii_read(void *opaque, hwaddr addr, unsigned size) | ||
187 | +{ | ||
188 | + AspeedMiiState *s = ASPEED_MII(opaque); | ||
189 | + | ||
190 | + switch (addr) { | ||
191 | + case 0x0: | ||
192 | + return s->phycr; | ||
193 | + case 0x4: | ||
194 | + return s->phydata; | ||
195 | + default: | ||
196 | + g_assert_not_reached(); | ||
197 | + } | ||
198 | +} | ||
199 | + | ||
200 | +static void aspeed_mii_write(void *opaque, hwaddr addr, | ||
201 | + uint64_t value, unsigned size) | ||
202 | +{ | ||
203 | + AspeedMiiState *s = ASPEED_MII(opaque); | ||
204 | + | ||
205 | + switch (addr) { | ||
206 | + case 0x0: | ||
207 | + s->phycr = value & ~(s->phycr & ASPEED_MII_PHYCR_FIRE); | ||
208 | + break; | ||
209 | + case 0x4: | ||
210 | + s->phydata = value & ~(0xffff | ASPEED_MII_PHYDATA_IDLE); | ||
211 | + break; | 44 | + break; |
212 | + default: | 45 | + default: |
213 | + g_assert_not_reached(); | 46 | + g_assert_not_reached(); |
214 | + } | 47 | + } |
215 | + | 48 | + |
216 | + aspeed_mii_transition(s, !!(s->phycr & ASPEED_MII_PHYCR_FIRE)); | 49 | + for (i = 0; i < num_ppcs; i++) { |
217 | + aspeed_mii_do_phy_ctl(s); | 50 | const PPCInfo *ppcinfo = &ppcs[i]; |
218 | +} | 51 | TZPPC *ppc = &mms->ppc[i]; |
219 | + | 52 | DeviceState *ppcdev; |
220 | +static const MemoryRegionOps aspeed_mii_ops = { | ||
221 | + .read = aspeed_mii_read, | ||
222 | + .write = aspeed_mii_write, | ||
223 | + .valid.min_access_size = 4, | ||
224 | + .valid.max_access_size = 4, | ||
225 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
226 | +}; | ||
227 | + | ||
228 | +static void aspeed_mii_reset(DeviceState *dev) | ||
229 | +{ | ||
230 | + AspeedMiiState *s = ASPEED_MII(dev); | ||
231 | + | ||
232 | + s->phycr = 0; | ||
233 | + s->phydata = 0; | ||
234 | + | ||
235 | + aspeed_mii_transition(s, !!(s->phycr & ASPEED_MII_PHYCR_FIRE)); | ||
236 | +}; | ||
237 | + | ||
238 | +static void aspeed_mii_realize(DeviceState *dev, Error **errp) | ||
239 | +{ | ||
240 | + AspeedMiiState *s = ASPEED_MII(dev); | ||
241 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
242 | + Object *obj; | ||
243 | + Error *local_err = NULL; | ||
244 | + | ||
245 | + obj = object_property_get_link(OBJECT(dev), "nic", &local_err); | ||
246 | + if (!obj) { | ||
247 | + error_propagate(errp, local_err); | ||
248 | + error_prepend(errp, "required link 'nic' not found: "); | ||
249 | + return; | ||
250 | + } | ||
251 | + | ||
252 | + s->nic = FTGMAC100(obj); | ||
253 | + | ||
254 | + memory_region_init_io(&s->iomem, OBJECT(dev), &aspeed_mii_ops, s, | ||
255 | + TYPE_ASPEED_MII, 0x8); | ||
256 | + sysbus_init_mmio(sbd, &s->iomem); | ||
257 | +} | ||
258 | + | ||
259 | +static const VMStateDescription vmstate_aspeed_mii = { | ||
260 | + .name = TYPE_ASPEED_MII, | ||
261 | + .version_id = 1, | ||
262 | + .minimum_version_id = 1, | ||
263 | + .fields = (VMStateField[]) { | ||
264 | + VMSTATE_UINT32(phycr, FTGMAC100State), | ||
265 | + VMSTATE_UINT32(phydata, FTGMAC100State), | ||
266 | + VMSTATE_END_OF_LIST() | ||
267 | + } | ||
268 | +}; | ||
269 | +static void aspeed_mii_class_init(ObjectClass *klass, void *data) | ||
270 | +{ | ||
271 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
272 | + | ||
273 | + dc->vmsd = &vmstate_aspeed_mii; | ||
274 | + dc->reset = aspeed_mii_reset; | ||
275 | + dc->realize = aspeed_mii_realize; | ||
276 | + dc->desc = "Aspeed MII controller"; | ||
277 | +} | ||
278 | + | ||
279 | +static const TypeInfo aspeed_mii_info = { | ||
280 | + .name = TYPE_ASPEED_MII, | ||
281 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
282 | + .instance_size = sizeof(AspeedMiiState), | ||
283 | + .class_init = aspeed_mii_class_init, | ||
284 | +}; | ||
285 | + | ||
286 | static void ftgmac100_register_types(void) | ||
287 | { | ||
288 | type_register_static(&ftgmac100_info); | ||
289 | + type_register_static(&aspeed_mii_info); | ||
290 | } | ||
291 | |||
292 | type_init(ftgmac100_register_types) | ||
293 | -- | 53 | -- |
294 | 2.20.1 | 54 | 2.20.1 |
295 | 55 | ||
296 | 56 | diff view generated by jsdifflib |
1 | Currently the Arm semihosting code returns the guest file descriptors | 1 | The AN505 and AN521 have the same layout of RAM; the AN524 does not. |
---|---|---|---|
2 | (handles) which are simply the fd values from the host OS or the | 2 | Replace the current hard-coding of where the RAM is and which parts |
3 | remote gdbstub. Part of the semihosting 2.0 specification requires | 3 | of it are behind which MPCs with a data-driven approach. |
4 | that we implement special handling of opening a ":semihosting-features" | ||
5 | filename. Guest fds which result from opening the special file | ||
6 | won't correspond to host fds, so to ensure that we don't end up | ||
7 | with duplicate fds we need to have QEMU code control the allocation | ||
8 | of the fd values we give the guest. | ||
9 | |||
10 | Add in an abstraction layer which lets us allocate new guest FD | ||
11 | values, and translate from a guest FD value back to the host one. | ||
12 | This also fixes an odd hole where a semihosting guest could | ||
13 | use the semihosting API to read, write or close file descriptors | ||
14 | that it had never allocated but which were being used by QEMU itself. | ||
15 | (This isn't a security hole, because enabling semihosting permits | ||
16 | the guest to do arbitrary file access to the whole host filesystem, | ||
17 | and so should only be done if the guest is completely trusted.) | ||
18 | |||
19 | Currently the only kind of guest fd is one which maps to a | ||
20 | host fd, but in a following commit we will add one which maps | ||
21 | to the :semihosting-features magic data. | ||
22 | |||
23 | If the guest is migrated with an open semihosting file descriptor | ||
24 | then subsequent attempts to use the fd will all fail; this is | ||
25 | not a change from the previous situation (where the host fd | ||
26 | being used on the source end would not be re-opened on the | ||
27 | destination end). | ||
28 | 4 | ||
29 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
30 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
31 | Message-id: 20190916141544.17540-5-peter.maydell@linaro.org | 7 | Message-id: 20210215115138.20465-17-peter.maydell@linaro.org |
32 | --- | 8 | --- |
33 | target/arm/arm-semi.c | 232 +++++++++++++++++++++++++++++++++++++++--- | 9 | hw/arm/mps2-tz.c | 175 +++++++++++++++++++++++++++++++++++++---------- |
34 | 1 file changed, 216 insertions(+), 16 deletions(-) | 10 | 1 file changed, 138 insertions(+), 37 deletions(-) |
35 | 11 | ||
36 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 12 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
37 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/target/arm/arm-semi.c | 14 | --- a/hw/arm/mps2-tz.c |
39 | +++ b/target/arm/arm-semi.c | 15 | +++ b/hw/arm/mps2-tz.c |
40 | @@ -XXX,XX +XXX,XX @@ static int open_modeflags[12] = { | 16 | @@ -XXX,XX +XXX,XX @@ |
41 | O_RDWR | O_CREAT | O_APPEND | O_BINARY | 17 | #include "qom/object.h" |
18 | |||
19 | #define MPS2TZ_NUMIRQ_MAX 92 | ||
20 | +#define MPS2TZ_RAM_MAX 4 | ||
21 | |||
22 | typedef enum MPS2TZFPGAType { | ||
23 | FPGA_AN505, | ||
24 | FPGA_AN521, | ||
25 | } MPS2TZFPGAType; | ||
26 | |||
27 | +/* | ||
28 | + * Define the layout of RAM in a board, including which parts are | ||
29 | + * behind which MPCs. | ||
30 | + * mrindex specifies the index into mms->ram[] to use for the backing RAM; | ||
31 | + * -1 means "use the system RAM". | ||
32 | + */ | ||
33 | +typedef struct RAMInfo { | ||
34 | + const char *name; | ||
35 | + uint32_t base; | ||
36 | + uint32_t size; | ||
37 | + int mpc; /* MPC number, -1 for "not behind an MPC" */ | ||
38 | + int mrindex; | ||
39 | + int flags; | ||
40 | +} RAMInfo; | ||
41 | + | ||
42 | +/* | ||
43 | + * Flag values: | ||
44 | + * IS_ALIAS: this RAM area is an alias to the upstream end of the | ||
45 | + * MPC specified by its .mpc value | ||
46 | + */ | ||
47 | +#define IS_ALIAS 1 | ||
48 | + | ||
49 | struct MPS2TZMachineClass { | ||
50 | MachineClass parent; | ||
51 | MPS2TZFPGAType fpga_type; | ||
52 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass { | ||
53 | uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ | ||
54 | bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ | ||
55 | int numirq; /* Number of external interrupts */ | ||
56 | + const RAMInfo *raminfo; | ||
57 | const char *armsse_type; | ||
42 | }; | 58 | }; |
43 | 59 | ||
44 | +typedef enum GuestFDType { | 60 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState { |
45 | + GuestFDUnused = 0, | 61 | MachineState parent; |
46 | + GuestFDHost = 1, | 62 | |
47 | +} GuestFDType; | 63 | ARMSSE iotkit; |
48 | + | 64 | - MemoryRegion ssram[3]; |
49 | +/* | 65 | - MemoryRegion ssram1_m; |
50 | + * Guest file descriptors are integer indexes into an array of | 66 | + MemoryRegion ram[MPS2TZ_RAM_MAX]; |
51 | + * these structures (we will dynamically resize as necessary). | 67 | MPS2SCC scc; |
52 | + */ | 68 | MPS2FPGAIO fpgaio; |
53 | +typedef struct GuestFD { | 69 | TZPPC ppc[5]; |
54 | + GuestFDType type; | 70 | - TZMPC ssram_mpc[3]; |
55 | + int hostfd; | 71 | + TZMPC mpc[3]; |
56 | +} GuestFD; | 72 | PL022State spi[5]; |
57 | + | 73 | ArmSbconI2CState i2c[4]; |
58 | +static GArray *guestfd_array; | 74 | UnimplementedDeviceState i2s_audio; |
59 | + | 75 | @@ -XXX,XX +XXX,XX @@ static const uint32_t an505_oscclk[] = { |
60 | +/* | 76 | 25000000, |
61 | + * Allocate a new guest file descriptor and return it; if we | 77 | }; |
62 | + * couldn't allocate a new fd then return -1. | 78 | |
63 | + * This is a fairly simplistic implementation because we don't | 79 | +static const RAMInfo an505_raminfo[] = { { |
64 | + * expect that most semihosting guest programs will make very | 80 | + .name = "ssram-0", |
65 | + * heavy use of opening and closing fds. | 81 | + .base = 0x00000000, |
66 | + */ | 82 | + .size = 0x00400000, |
67 | +static int alloc_guestfd(void) | 83 | + .mpc = 0, |
84 | + .mrindex = 0, | ||
85 | + }, { | ||
86 | + .name = "ssram-1", | ||
87 | + .base = 0x28000000, | ||
88 | + .size = 0x00200000, | ||
89 | + .mpc = 1, | ||
90 | + .mrindex = 1, | ||
91 | + }, { | ||
92 | + .name = "ssram-2", | ||
93 | + .base = 0x28200000, | ||
94 | + .size = 0x00200000, | ||
95 | + .mpc = 2, | ||
96 | + .mrindex = 2, | ||
97 | + }, { | ||
98 | + .name = "ssram-0-alias", | ||
99 | + .base = 0x00400000, | ||
100 | + .size = 0x00400000, | ||
101 | + .mpc = 0, | ||
102 | + .mrindex = 3, | ||
103 | + .flags = IS_ALIAS, | ||
104 | + }, { | ||
105 | + /* Use the largest bit of contiguous RAM as our "system memory" */ | ||
106 | + .name = "mps.ram", | ||
107 | + .base = 0x80000000, | ||
108 | + .size = 16 * MiB, | ||
109 | + .mpc = -1, | ||
110 | + .mrindex = -1, | ||
111 | + }, { | ||
112 | + .name = NULL, | ||
113 | + }, | ||
114 | +}; | ||
115 | + | ||
116 | +static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc) | ||
68 | +{ | 117 | +{ |
69 | + guint i; | 118 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
70 | + | 119 | + const RAMInfo *p; |
71 | + if (!guestfd_array) { | 120 | + |
72 | + /* New entries zero-initialized, i.e. type GuestFDUnused */ | 121 | + for (p = mmc->raminfo; p->name; p++) { |
73 | + guestfd_array = g_array_new(FALSE, TRUE, sizeof(GuestFD)); | 122 | + if (p->mpc == mpc && !(p->flags & IS_ALIAS)) { |
74 | + } | 123 | + return p; |
75 | + | ||
76 | + for (i = 0; i < guestfd_array->len; i++) { | ||
77 | + GuestFD *gf = &g_array_index(guestfd_array, GuestFD, i); | ||
78 | + | ||
79 | + if (gf->type == GuestFDUnused) { | ||
80 | + return i; | ||
81 | + } | 124 | + } |
82 | + } | 125 | + } |
83 | + | 126 | + /* if raminfo array doesn't have an entry for each MPC this is a bug */ |
84 | + /* All elements already in use: expand the array */ | 127 | + g_assert_not_reached(); |
85 | + g_array_set_size(guestfd_array, i + 1); | ||
86 | + return i; | ||
87 | +} | 128 | +} |
88 | + | 129 | + |
89 | +/* | 130 | +static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms, |
90 | + * Look up the guestfd in the data structure; return NULL | 131 | + const RAMInfo *raminfo) |
91 | + * for out of bounds, but don't check whether the slot is unused. | ||
92 | + * This is used internally by the other guestfd functions. | ||
93 | + */ | ||
94 | +static GuestFD *do_get_guestfd(int guestfd) | ||
95 | +{ | 132 | +{ |
96 | + if (!guestfd_array) { | 133 | + /* Return an initialized MemoryRegion for the RAMInfo. */ |
97 | + return NULL; | 134 | + MemoryRegion *ram; |
135 | + | ||
136 | + if (raminfo->mrindex < 0) { | ||
137 | + /* Means this RAMInfo is for QEMU's "system memory" */ | ||
138 | + MachineState *machine = MACHINE(mms); | ||
139 | + return machine->ram; | ||
98 | + } | 140 | + } |
99 | + | 141 | + |
100 | + if (guestfd < 0 || guestfd >= guestfd_array->len) { | 142 | + assert(raminfo->mrindex < MPS2TZ_RAM_MAX); |
101 | + return NULL; | 143 | + ram = &mms->ram[raminfo->mrindex]; |
102 | + } | 144 | + |
103 | + | 145 | + memory_region_init_ram(ram, NULL, raminfo->name, |
104 | + return &g_array_index(guestfd_array, GuestFD, guestfd); | 146 | + raminfo->size, &error_fatal); |
147 | + return ram; | ||
105 | +} | 148 | +} |
106 | + | 149 | + |
107 | +/* | 150 | /* Create an alias of an entire original MemoryRegion @orig |
108 | + * Associate the specified guest fd (which must have been | 151 | * located at @base in the memory map. |
109 | + * allocated via alloc_fd() and not previously used) with | 152 | */ |
110 | + * the specified host fd. | 153 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, |
111 | + */ | 154 | const int *irqs) |
112 | +static void associate_guestfd(int guestfd, int hostfd) | 155 | { |
156 | TZMPC *mpc = opaque; | ||
157 | - int i = mpc - &mms->ssram_mpc[0]; | ||
158 | - MemoryRegion *ssram = &mms->ssram[i]; | ||
159 | + int i = mpc - &mms->mpc[0]; | ||
160 | MemoryRegion *upstream; | ||
161 | - char *mpcname = g_strdup_printf("%s-mpc", name); | ||
162 | - static uint32_t ramsize[] = { 0x00400000, 0x00200000, 0x00200000 }; | ||
163 | - static uint32_t rambase[] = { 0x00000000, 0x28000000, 0x28200000 }; | ||
164 | + const RAMInfo *raminfo = find_raminfo_for_mpc(mms, i); | ||
165 | + MemoryRegion *ram = mr_for_raminfo(mms, raminfo); | ||
166 | |||
167 | - memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal); | ||
168 | - | ||
169 | - object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC); | ||
170 | - object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ssram), | ||
171 | + object_initialize_child(OBJECT(mms), name, mpc, TYPE_TZ_MPC); | ||
172 | + object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ram), | ||
173 | &error_fatal); | ||
174 | sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); | ||
175 | /* Map the upstream end of the MPC into system memory */ | ||
176 | upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); | ||
177 | - memory_region_add_subregion(get_system_memory(), rambase[i], upstream); | ||
178 | + memory_region_add_subregion(get_system_memory(), raminfo->base, upstream); | ||
179 | /* and connect its interrupt to the IoTKit */ | ||
180 | qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, | ||
181 | qdev_get_gpio_in_named(DEVICE(&mms->iotkit), | ||
182 | "mpcexp_status", i)); | ||
183 | |||
184 | - /* The first SSRAM is a special case as it has an alias; accesses to | ||
185 | - * the alias region at 0x00400000 must also go to the MPC upstream. | ||
186 | - */ | ||
187 | - if (i == 0) { | ||
188 | - make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x00400000); | ||
189 | - } | ||
190 | - | ||
191 | - g_free(mpcname); | ||
192 | /* Return the register interface MR for our caller to map behind the PPC */ | ||
193 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); | ||
194 | } | ||
195 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, | ||
196 | return sysbus_mmio_get_region(s, 0); | ||
197 | } | ||
198 | |||
199 | +static void create_non_mpc_ram(MPS2TZMachineState *mms) | ||
113 | +{ | 200 | +{ |
114 | + GuestFD *gf = do_get_guestfd(guestfd); | 201 | + /* |
115 | + | 202 | + * Handle the RAMs which are either not behind MPCs or which are |
116 | + assert(gf); | 203 | + * aliases to another MPC. |
117 | + gf->type = GuestFDHost; | 204 | + */ |
118 | + gf->hostfd = hostfd; | 205 | + const RAMInfo *p; |
119 | +} | 206 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
120 | + | 207 | + |
121 | +/* | 208 | + for (p = mmc->raminfo; p->name; p++) { |
122 | + * Deallocate the specified guest file descriptor. This doesn't | 209 | + if (p->flags & IS_ALIAS) { |
123 | + * close the host fd, it merely undoes the work of alloc_fd(). | 210 | + SysBusDevice *mpc_sbd = SYS_BUS_DEVICE(&mms->mpc[p->mpc]); |
124 | + */ | 211 | + MemoryRegion *upstream = sysbus_mmio_get_region(mpc_sbd, 1); |
125 | +static void dealloc_guestfd(int guestfd) | 212 | + make_ram_alias(&mms->ram[p->mrindex], p->name, upstream, p->base); |
126 | +{ | 213 | + } else if (p->mpc == -1) { |
127 | + GuestFD *gf = do_get_guestfd(guestfd); | 214 | + /* RAM not behind an MPC */ |
128 | + | 215 | + MemoryRegion *mr = mr_for_raminfo(mms, p); |
129 | + assert(gf); | 216 | + memory_region_add_subregion(get_system_memory(), p->base, mr); |
130 | + gf->type = GuestFDUnused; | 217 | + } |
131 | +} | ||
132 | + | ||
133 | +/* | ||
134 | + * Given a guest file descriptor, get the associated struct. | ||
135 | + * If the fd is not valid, return NULL. This is the function | ||
136 | + * used by the various semihosting calls to validate a handle | ||
137 | + * from the guest. | ||
138 | + * Note: calling alloc_guestfd() or dealloc_guestfd() will | ||
139 | + * invalidate any GuestFD* obtained by calling this function. | ||
140 | + */ | ||
141 | +static GuestFD *get_guestfd(int guestfd) | ||
142 | +{ | ||
143 | + GuestFD *gf = do_get_guestfd(guestfd); | ||
144 | + | ||
145 | + if (!gf || gf->type == GuestFDUnused) { | ||
146 | + return NULL; | ||
147 | + } | ||
148 | + return gf; | ||
149 | +} | ||
150 | + | ||
151 | #ifdef CONFIG_USER_ONLY | ||
152 | static inline uint32_t set_swi_errno(TaskState *ts, uint32_t code) | ||
153 | { | ||
154 | @@ -XXX,XX +XXX,XX @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) | ||
155 | #endif | ||
156 | } | ||
157 | |||
158 | +static int arm_semi_open_guestfd; | ||
159 | + | ||
160 | +static void arm_semi_open_cb(CPUState *cs, target_ulong ret, target_ulong err) | ||
161 | +{ | ||
162 | + ARMCPU *cpu = ARM_CPU(cs); | ||
163 | + CPUARMState *env = &cpu->env; | ||
164 | +#ifdef CONFIG_USER_ONLY | ||
165 | + TaskState *ts = cs->opaque; | ||
166 | +#endif | ||
167 | + if (ret == (target_ulong)-1) { | ||
168 | +#ifdef CONFIG_USER_ONLY | ||
169 | + ts->swi_errno = err; | ||
170 | +#else | ||
171 | + syscall_err = err; | ||
172 | +#endif | ||
173 | + dealloc_guestfd(arm_semi_open_guestfd); | ||
174 | + } else { | ||
175 | + associate_guestfd(arm_semi_open_guestfd, ret); | ||
176 | + ret = arm_semi_open_guestfd; | ||
177 | + } | ||
178 | + | ||
179 | + if (is_a64(env)) { | ||
180 | + env->xregs[0] = ret; | ||
181 | + } else { | ||
182 | + env->regs[0] = ret; | ||
183 | + } | 218 | + } |
184 | +} | 219 | +} |
185 | + | 220 | + |
186 | static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, | 221 | static void mps2tz_common_init(MachineState *machine) |
187 | const char *fmt, ...) | ||
188 | { | 222 | { |
189 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | 223 | MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); |
190 | #else | 224 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) |
191 | CPUARMState *ts = env; | 225 | qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, |
192 | #endif | 226 | qdev_get_gpio_in(dev_splitter, 0)); |
193 | + GuestFD *gf; | 227 | |
194 | 228 | - /* The IoTKit sets up much of the memory layout, including | |
195 | if (is_a64(env)) { | 229 | + /* |
196 | /* Note that the syscall number is in W0, not X0 */ | 230 | + * The IoTKit sets up much of the memory layout, including |
197 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | 231 | * the aliases between secure and non-secure regions in the |
198 | 232 | - * address space. The FPGA itself contains: | |
199 | switch (nr) { | 233 | - * |
200 | case TARGET_SYS_OPEN: | 234 | - * 0x00000000..0x003fffff SSRAM1 |
201 | + { | 235 | - * 0x00400000..0x007fffff alias of SSRAM1 |
202 | + int guestfd; | 236 | - * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3 |
203 | + | 237 | - * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices |
204 | GET_ARG(0); | 238 | - * 0x80000000..0x80ffffff 16MB PSRAM |
205 | GET_ARG(1); | 239 | - */ |
206 | GET_ARG(2); | 240 | - |
207 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | 241 | - /* The FPGA images have an odd combination of different RAMs, |
208 | errno = EINVAL; | 242 | + * address space, and also most of the devices in the system. |
209 | return set_swi_errno(ts, -1); | 243 | + * The FPGA itself contains various RAMs and some additional devices. |
210 | } | 244 | + * The FPGA images have an odd combination of different RAMs, |
211 | + | 245 | * because in hardware they are different implementations and |
212 | + guestfd = alloc_guestfd(); | 246 | * connected to different buses, giving varying performance/size |
213 | + if (guestfd < 0) { | 247 | * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily |
214 | + unlock_user(s, arg0, 0); | 248 | - * call the 16MB our "system memory", as it's the largest lump. |
215 | + errno = EMFILE; | 249 | + * call the largest lump our "system memory". |
216 | + return set_swi_errno(ts, -1); | 250 | */ |
217 | + } | 251 | - memory_region_add_subregion(system_memory, 0x80000000, machine->ram); |
218 | + | 252 | |
219 | if (strcmp(s, ":tt") == 0) { | 253 | /* |
220 | int result_fileno = arg1 < 4 ? STDIN_FILENO : STDOUT_FILENO; | 254 | * The overflow IRQs for all UARTs are ORed together. |
221 | + associate_guestfd(guestfd, result_fileno); | 255 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) |
222 | unlock_user(s, arg0, 0); | 256 | const PPCInfo an505_ppcs[] = { { |
223 | - return result_fileno; | 257 | .name = "apb_ppcexp0", |
224 | + return guestfd; | 258 | .ports = { |
225 | } | 259 | - { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 }, |
226 | if (use_gdb_syscalls()) { | 260 | - { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1000 }, |
227 | - ret = arm_gdb_syscall(cpu, arm_semi_cb, "open,%s,%x,1a4", arg0, | 261 | - { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1000 }, |
228 | + arm_semi_open_guestfd = guestfd; | 262 | + { "ssram-0-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, |
229 | + ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0, | 263 | + { "ssram-1-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, |
230 | (int)arg2+1, gdb_open_modeflags[arg1]); | 264 | + { "ssram-2-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, |
231 | } else { | 265 | }, |
232 | ret = set_swi_errno(ts, open(s, open_modeflags[arg1], 0644)); | 266 | }, { |
233 | + if (ret == (uint32_t)-1) { | 267 | .name = "apb_ppcexp1", |
234 | + dealloc_guestfd(guestfd); | 268 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) |
235 | + } else { | 269 | |
236 | + associate_guestfd(guestfd, ret); | 270 | create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); |
237 | + ret = guestfd; | 271 | |
238 | + } | 272 | + create_non_mpc_ram(mms); |
239 | } | 273 | + |
240 | unlock_user(s, arg0, 0); | 274 | armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); |
241 | return ret; | 275 | } |
242 | + } | 276 | |
243 | case TARGET_SYS_CLOSE: | 277 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) |
244 | GET_ARG(0); | 278 | mmc->fpgaio_num_leds = 2; |
245 | - if (use_gdb_syscalls()) { | 279 | mmc->fpgaio_has_switches = false; |
246 | - return arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", arg0); | 280 | mmc->numirq = 92; |
247 | - } else { | 281 | + mmc->raminfo = an505_raminfo; |
248 | - return set_swi_errno(ts, close(arg0)); | 282 | mmc->armsse_type = TYPE_IOTKIT; |
249 | + | 283 | } |
250 | + gf = get_guestfd(arg0); | 284 | |
251 | + if (!gf) { | 285 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) |
252 | + errno = EBADF; | 286 | mmc->fpgaio_num_leds = 2; |
253 | + return set_swi_errno(ts, -1); | 287 | mmc->fpgaio_has_switches = false; |
254 | } | 288 | mmc->numirq = 92; |
255 | + | 289 | + mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */ |
256 | + if (use_gdb_syscalls()) { | 290 | mmc->armsse_type = TYPE_SSE200; |
257 | + ret = arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); | 291 | } |
258 | + } else { | 292 | |
259 | + ret = set_swi_errno(ts, close(gf->hostfd)); | ||
260 | + } | ||
261 | + dealloc_guestfd(arg0); | ||
262 | + return ret; | ||
263 | case TARGET_SYS_WRITEC: | ||
264 | qemu_semihosting_console_outc(env, args); | ||
265 | return 0xdeadbeef; | ||
266 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
267 | GET_ARG(1); | ||
268 | GET_ARG(2); | ||
269 | len = arg2; | ||
270 | + | ||
271 | + gf = get_guestfd(arg0); | ||
272 | + if (!gf) { | ||
273 | + errno = EBADF; | ||
274 | + return set_swi_errno(ts, -1); | ||
275 | + } | ||
276 | + | ||
277 | if (use_gdb_syscalls()) { | ||
278 | arm_semi_syscall_len = len; | ||
279 | return arm_gdb_syscall(cpu, arm_semi_cb, "write,%x,%x,%x", | ||
280 | - arg0, arg1, len); | ||
281 | + gf->hostfd, arg1, len); | ||
282 | } else { | ||
283 | s = lock_user(VERIFY_READ, arg1, len, 1); | ||
284 | if (!s) { | ||
285 | /* Return bytes not written on error */ | ||
286 | return len; | ||
287 | } | ||
288 | - ret = set_swi_errno(ts, write(arg0, s, len)); | ||
289 | + ret = set_swi_errno(ts, write(gf->hostfd, s, len)); | ||
290 | unlock_user(s, arg1, 0); | ||
291 | if (ret == (uint32_t)-1) { | ||
292 | ret = 0; | ||
293 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
294 | GET_ARG(1); | ||
295 | GET_ARG(2); | ||
296 | len = arg2; | ||
297 | + | ||
298 | + gf = get_guestfd(arg0); | ||
299 | + if (!gf) { | ||
300 | + errno = EBADF; | ||
301 | + return set_swi_errno(ts, -1); | ||
302 | + } | ||
303 | + | ||
304 | if (use_gdb_syscalls()) { | ||
305 | arm_semi_syscall_len = len; | ||
306 | return arm_gdb_syscall(cpu, arm_semi_cb, "read,%x,%x,%x", | ||
307 | - arg0, arg1, len); | ||
308 | + gf->hostfd, arg1, len); | ||
309 | } else { | ||
310 | s = lock_user(VERIFY_WRITE, arg1, len, 0); | ||
311 | if (!s) { | ||
312 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
313 | return len; | ||
314 | } | ||
315 | do { | ||
316 | - ret = set_swi_errno(ts, read(arg0, s, len)); | ||
317 | + ret = set_swi_errno(ts, read(gf->hostfd, s, len)); | ||
318 | } while (ret == -1 && errno == EINTR); | ||
319 | unlock_user(s, arg1, len); | ||
320 | if (ret == (uint32_t)-1) { | ||
321 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
322 | return 0; | ||
323 | case TARGET_SYS_ISTTY: | ||
324 | GET_ARG(0); | ||
325 | + | ||
326 | + gf = get_guestfd(arg0); | ||
327 | + if (!gf) { | ||
328 | + errno = EBADF; | ||
329 | + return set_swi_errno(ts, -1); | ||
330 | + } | ||
331 | + | ||
332 | if (use_gdb_syscalls()) { | ||
333 | - return arm_gdb_syscall(cpu, arm_semi_cb, "isatty,%x", arg0); | ||
334 | + return arm_gdb_syscall(cpu, arm_semi_cb, "isatty,%x", gf->hostfd); | ||
335 | } else { | ||
336 | - return isatty(arg0); | ||
337 | + return isatty(gf->hostfd); | ||
338 | } | ||
339 | case TARGET_SYS_SEEK: | ||
340 | GET_ARG(0); | ||
341 | GET_ARG(1); | ||
342 | + | ||
343 | + gf = get_guestfd(arg0); | ||
344 | + if (!gf) { | ||
345 | + errno = EBADF; | ||
346 | + return set_swi_errno(ts, -1); | ||
347 | + } | ||
348 | + | ||
349 | if (use_gdb_syscalls()) { | ||
350 | return arm_gdb_syscall(cpu, arm_semi_cb, "lseek,%x,%x,0", | ||
351 | - arg0, arg1); | ||
352 | + gf->hostfd, arg1); | ||
353 | } else { | ||
354 | - ret = set_swi_errno(ts, lseek(arg0, arg1, SEEK_SET)); | ||
355 | + ret = set_swi_errno(ts, lseek(gf->hostfd, arg1, SEEK_SET)); | ||
356 | if (ret == (uint32_t)-1) | ||
357 | return -1; | ||
358 | return 0; | ||
359 | } | ||
360 | case TARGET_SYS_FLEN: | ||
361 | GET_ARG(0); | ||
362 | + | ||
363 | + gf = get_guestfd(arg0); | ||
364 | + if (!gf) { | ||
365 | + errno = EBADF; | ||
366 | + return set_swi_errno(ts, -1); | ||
367 | + } | ||
368 | + | ||
369 | if (use_gdb_syscalls()) { | ||
370 | return arm_gdb_syscall(cpu, arm_semi_flen_cb, "fstat,%x,%x", | ||
371 | - arg0, arm_flen_buf(cpu)); | ||
372 | + gf->hostfd, arm_flen_buf(cpu)); | ||
373 | } else { | ||
374 | struct stat buf; | ||
375 | - ret = set_swi_errno(ts, fstat(arg0, &buf)); | ||
376 | + ret = set_swi_errno(ts, fstat(gf->hostfd, &buf)); | ||
377 | if (ret == (uint32_t)-1) | ||
378 | return -1; | ||
379 | return buf.st_size; | ||
380 | -- | 293 | -- |
381 | 2.20.1 | 294 | 2.20.1 |
382 | 295 | ||
383 | 296 | diff view generated by jsdifflib |
1 | Switch the arm_mptimer.c code away from bottom-half based ptimers to | 1 | Instead of hardcoding the MachineClass default_ram_size and |
---|---|---|---|
2 | the new transaction-based ptimer API. This just requires adding | 2 | default_ram_id fields, set them on class creation by finding the |
3 | begin/commit calls around the various places that modify the ptimer | 3 | entry in the RAMInfo array which is marked as being the QEMU system |
4 | state, and using the new ptimer_init() function to create the timer. | 4 | RAM. |
5 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20191008171740.9679-8-peter.maydell@linaro.org | 8 | Message-id: 20210215115138.20465-18-peter.maydell@linaro.org |
9 | --- | 9 | --- |
10 | hw/timer/arm_mptimer.c | 14 +++++++++++--- | 10 | hw/arm/mps2-tz.c | 24 ++++++++++++++++++++++-- |
11 | 1 file changed, 11 insertions(+), 3 deletions(-) | 11 | 1 file changed, 22 insertions(+), 2 deletions(-) |
12 | 12 | ||
13 | diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c | 13 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
14 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/timer/arm_mptimer.c | 15 | --- a/hw/arm/mps2-tz.c |
16 | +++ b/hw/timer/arm_mptimer.c | 16 | +++ b/hw/arm/mps2-tz.c |
17 | @@ -XXX,XX +XXX,XX @@ | 17 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data) |
18 | #include "hw/timer/arm_mptimer.h" | 18 | |
19 | #include "migration/vmstate.h" | 19 | mc->init = mps2tz_common_init; |
20 | #include "qapi/error.h" | 20 | iic->check = mps2_tz_idau_check; |
21 | -#include "qemu/main-loop.h" | 21 | - mc->default_ram_size = 16 * MiB; |
22 | #include "qemu/module.h" | 22 | - mc->default_ram_id = "mps.ram"; |
23 | #include "hw/core/cpu.h" | 23 | +} |
24 | 24 | + | |
25 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t timerblock_scale(uint32_t control) | 25 | +static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc) |
26 | return (((control >> 8) & 0xff) + 1) * 10; | 26 | +{ |
27 | + /* | ||
28 | + * Set mc->default_ram_size and default_ram_id from the | ||
29 | + * information in mmc->raminfo. | ||
30 | + */ | ||
31 | + MachineClass *mc = MACHINE_CLASS(mmc); | ||
32 | + const RAMInfo *p; | ||
33 | + | ||
34 | + for (p = mmc->raminfo; p->name; p++) { | ||
35 | + if (p->mrindex < 0) { | ||
36 | + /* Found the entry for "system memory" */ | ||
37 | + mc->default_ram_size = p->size; | ||
38 | + mc->default_ram_id = p->name; | ||
39 | + return; | ||
40 | + } | ||
41 | + } | ||
42 | + g_assert_not_reached(); | ||
27 | } | 43 | } |
28 | 44 | ||
29 | +/* Must be called within a ptimer transaction block */ | 45 | static void mps2tz_an505_class_init(ObjectClass *oc, void *data) |
30 | static inline void timerblock_set_count(struct ptimer_state *timer, | 46 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) |
31 | uint32_t control, uint64_t *count) | 47 | mmc->numirq = 92; |
32 | { | 48 | mmc->raminfo = an505_raminfo; |
33 | @@ -XXX,XX +XXX,XX @@ static inline void timerblock_set_count(struct ptimer_state *timer, | 49 | mmc->armsse_type = TYPE_IOTKIT; |
34 | ptimer_set_count(timer, *count); | 50 | + mps2tz_set_default_ram_info(mmc); |
35 | } | 51 | } |
36 | 52 | ||
37 | +/* Must be called within a ptimer transaction block */ | 53 | static void mps2tz_an521_class_init(ObjectClass *oc, void *data) |
38 | static inline void timerblock_run(struct ptimer_state *timer, | 54 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) |
39 | uint32_t control, uint32_t load) | 55 | mmc->numirq = 92; |
40 | { | 56 | mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */ |
41 | @@ -XXX,XX +XXX,XX @@ static void timerblock_write(void *opaque, hwaddr addr, | 57 | mmc->armsse_type = TYPE_SSE200; |
42 | uint32_t control = tb->control; | 58 | + mps2tz_set_default_ram_info(mmc); |
43 | switch (addr) { | ||
44 | case 0: /* Load */ | ||
45 | + ptimer_transaction_begin(tb->timer); | ||
46 | /* Setting load to 0 stops the timer without doing the tick if | ||
47 | * prescaler = 0. | ||
48 | */ | ||
49 | @@ -XXX,XX +XXX,XX @@ static void timerblock_write(void *opaque, hwaddr addr, | ||
50 | } | ||
51 | ptimer_set_limit(tb->timer, value, 1); | ||
52 | timerblock_run(tb->timer, control, value); | ||
53 | + ptimer_transaction_commit(tb->timer); | ||
54 | break; | ||
55 | case 4: /* Counter. */ | ||
56 | + ptimer_transaction_begin(tb->timer); | ||
57 | /* Setting counter to 0 stops the one-shot timer, or periodic with | ||
58 | * load = 0, without doing the tick if prescaler = 0. | ||
59 | */ | ||
60 | @@ -XXX,XX +XXX,XX @@ static void timerblock_write(void *opaque, hwaddr addr, | ||
61 | } | ||
62 | timerblock_set_count(tb->timer, control, &value); | ||
63 | timerblock_run(tb->timer, control, value); | ||
64 | + ptimer_transaction_commit(tb->timer); | ||
65 | break; | ||
66 | case 8: /* Control. */ | ||
67 | + ptimer_transaction_begin(tb->timer); | ||
68 | if ((control & 3) != (value & 3)) { | ||
69 | ptimer_stop(tb->timer); | ||
70 | } | ||
71 | @@ -XXX,XX +XXX,XX @@ static void timerblock_write(void *opaque, hwaddr addr, | ||
72 | timerblock_run(tb->timer, value, count); | ||
73 | } | ||
74 | tb->control = value; | ||
75 | + ptimer_transaction_commit(tb->timer); | ||
76 | break; | ||
77 | case 12: /* Interrupt status. */ | ||
78 | tb->status &= ~value; | ||
79 | @@ -XXX,XX +XXX,XX @@ static void timerblock_reset(TimerBlock *tb) | ||
80 | tb->control = 0; | ||
81 | tb->status = 0; | ||
82 | if (tb->timer) { | ||
83 | + ptimer_transaction_begin(tb->timer); | ||
84 | ptimer_stop(tb->timer); | ||
85 | ptimer_set_limit(tb->timer, 0, 1); | ||
86 | ptimer_set_period(tb->timer, timerblock_scale(0)); | ||
87 | + ptimer_transaction_commit(tb->timer); | ||
88 | } | ||
89 | } | 59 | } |
90 | 60 | ||
91 | @@ -XXX,XX +XXX,XX @@ static void arm_mptimer_realize(DeviceState *dev, Error **errp) | 61 | static const TypeInfo mps2tz_info = { |
92 | */ | ||
93 | for (i = 0; i < s->num_cpu; i++) { | ||
94 | TimerBlock *tb = &s->timerblock[i]; | ||
95 | - QEMUBH *bh = qemu_bh_new(timerblock_tick, tb); | ||
96 | - tb->timer = ptimer_init_with_bh(bh, PTIMER_POLICY); | ||
97 | + tb->timer = ptimer_init(timerblock_tick, tb, PTIMER_POLICY); | ||
98 | sysbus_init_irq(sbd, &tb->irq); | ||
99 | memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, | ||
100 | "arm_mptimer_timerblock", 0x20); | ||
101 | -- | 62 | -- |
102 | 2.20.1 | 63 | 2.20.1 |
103 | 64 | ||
104 | 65 | diff view generated by jsdifflib |
1 | Switch the cmsdk-apb-dualtimer code away from bottom-half based | 1 | The AN505 and AN521 don't have any read-only memory, but the AN524 |
---|---|---|---|
2 | ptimers to the new transaction-based ptimer API. This just requires | 2 | does; add a flag to ROMInfo to mark a region as ROM. |
3 | adding begin/commit calls around the various places that modify the | ||
4 | ptimer state, and using the new ptimer_init() function to create the | ||
5 | timer. | ||
6 | 3 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20191008171740.9679-9-peter.maydell@linaro.org | 6 | Message-id: 20210215115138.20465-19-peter.maydell@linaro.org |
10 | --- | 7 | --- |
11 | hw/timer/cmsdk-apb-dualtimer.c | 14 +++++++++++--- | 8 | hw/arm/mps2-tz.c | 6 ++++++ |
12 | 1 file changed, 11 insertions(+), 3 deletions(-) | 9 | 1 file changed, 6 insertions(+) |
13 | 10 | ||
14 | diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c | 11 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
15 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/timer/cmsdk-apb-dualtimer.c | 13 | --- a/hw/arm/mps2-tz.c |
17 | +++ b/hw/timer/cmsdk-apb-dualtimer.c | 14 | +++ b/hw/arm/mps2-tz.c |
18 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo { |
19 | #include "qemu/log.h" | 16 | * Flag values: |
20 | #include "trace.h" | 17 | * IS_ALIAS: this RAM area is an alias to the upstream end of the |
21 | #include "qapi/error.h" | 18 | * MPC specified by its .mpc value |
22 | -#include "qemu/main-loop.h" | 19 | + * IS_ROM: this RAM area is read-only |
23 | #include "qemu/module.h" | 20 | */ |
24 | #include "hw/sysbus.h" | 21 | #define IS_ALIAS 1 |
25 | #include "hw/irq.h" | 22 | +#define IS_ROM 2 |
26 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m, | 23 | |
27 | /* Handle a write to the CONTROL register */ | 24 | struct MPS2TZMachineClass { |
28 | uint32_t changed; | 25 | MachineClass parent; |
29 | 26 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms, | |
30 | + ptimer_transaction_begin(m->timer); | 27 | if (raminfo->mrindex < 0) { |
31 | + | 28 | /* Means this RAMInfo is for QEMU's "system memory" */ |
32 | newctrl &= R_CONTROL_VALID_MASK; | 29 | MachineState *machine = MACHINE(mms); |
33 | 30 | + assert(!(raminfo->flags & IS_ROM)); | |
34 | changed = m->control ^ newctrl; | 31 | return machine->ram; |
35 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m, | ||
36 | } | 32 | } |
37 | 33 | ||
38 | m->control = newctrl; | 34 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms, |
39 | + | 35 | |
40 | + ptimer_transaction_commit(m->timer); | 36 | memory_region_init_ram(ram, NULL, raminfo->name, |
37 | raminfo->size, &error_fatal); | ||
38 | + if (raminfo->flags & IS_ROM) { | ||
39 | + memory_region_set_readonly(ram, true); | ||
40 | + } | ||
41 | return ram; | ||
41 | } | 42 | } |
42 | 43 | ||
43 | static uint64_t cmsdk_apb_dualtimer_read(void *opaque, hwaddr offset, | ||
44 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_write(void *opaque, hwaddr offset, | ||
45 | if (!(m->control & R_CONTROL_SIZE_MASK)) { | ||
46 | value &= 0xffff; | ||
47 | } | ||
48 | + ptimer_transaction_begin(m->timer); | ||
49 | if (!(m->control & R_CONTROL_MODE_MASK)) { | ||
50 | /* | ||
51 | * In free-running mode this won't set the limit but will | ||
52 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_write(void *opaque, hwaddr offset, | ||
53 | ptimer_run(m->timer, 1); | ||
54 | } | ||
55 | } | ||
56 | + ptimer_transaction_commit(m->timer); | ||
57 | break; | ||
58 | case A_TIMER1BGLOAD: | ||
59 | /* Set the limit, but not the current count */ | ||
60 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_write(void *opaque, hwaddr offset, | ||
61 | if (!(m->control & R_CONTROL_SIZE_MASK)) { | ||
62 | value &= 0xffff; | ||
63 | } | ||
64 | + ptimer_transaction_begin(m->timer); | ||
65 | ptimer_set_limit(m->timer, value, 0); | ||
66 | + ptimer_transaction_commit(m->timer); | ||
67 | break; | ||
68 | case A_TIMER1CONTROL: | ||
69 | cmsdk_dualtimermod_write_control(m, value); | ||
70 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_dualtimermod_reset(CMSDKAPBDualTimerModule *m) | ||
71 | m->intstatus = 0; | ||
72 | m->load = 0; | ||
73 | m->value = 0xffffffff; | ||
74 | + ptimer_transaction_begin(m->timer); | ||
75 | ptimer_stop(m->timer); | ||
76 | /* | ||
77 | * We start in free-running mode, with VALUE at 0xffffffff, and | ||
78 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_dualtimermod_reset(CMSDKAPBDualTimerModule *m) | ||
79 | */ | ||
80 | ptimer_set_limit(m->timer, 0xffff, 1); | ||
81 | ptimer_set_freq(m->timer, m->parent->pclk_frq); | ||
82 | + ptimer_transaction_commit(m->timer); | ||
83 | } | ||
84 | |||
85 | static void cmsdk_apb_dualtimer_reset(DeviceState *dev) | ||
86 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp) | ||
87 | |||
88 | for (i = 0; i < ARRAY_SIZE(s->timermod); i++) { | ||
89 | CMSDKAPBDualTimerModule *m = &s->timermod[i]; | ||
90 | - QEMUBH *bh = qemu_bh_new(cmsdk_dualtimermod_tick, m); | ||
91 | |||
92 | m->parent = s; | ||
93 | - m->timer = ptimer_init_with_bh(bh, | ||
94 | + m->timer = ptimer_init(cmsdk_dualtimermod_tick, m, | ||
95 | PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | | ||
96 | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | | ||
97 | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | | ||
98 | -- | 44 | -- |
99 | 2.20.1 | 45 | 2.20.1 |
100 | 46 | ||
101 | 47 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | The armv7m_load_kernel() function takes a mem_size argument which it |
---|---|---|---|
2 | expects to be the size of the memory region at guest address 0. (It | ||
3 | uses this argument only as a limit on how large a raw image file it | ||
4 | can load at address zero). | ||
2 | 5 | ||
3 | The AST2600 timer has a third control register that is used to | 6 | Instead of hardcoding this value, find the RAMInfo corresponding to |
4 | implement a set-to-clear feature for the main control register. | 7 | the 0 address and extract its size. |
5 | 8 | ||
6 | On the AST2600, it is not configurable via 0x38 (control register 3) | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | as it is on the AST2500. | 10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20210215115138.20465-20-peter.maydell@linaro.org | ||
13 | --- | ||
14 | hw/arm/mps2-tz.c | 17 ++++++++++++++++- | ||
15 | 1 file changed, 16 insertions(+), 1 deletion(-) | ||
8 | 16 | ||
9 | Based on previous work from Joel Stanley. | 17 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
10 | |||
11 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
12 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
13 | Message-id: 20190925143248.10000-7-clg@kaod.org | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | include/hw/timer/aspeed_timer.h | 1 + | ||
17 | hw/timer/aspeed_timer.c | 51 +++++++++++++++++++++++++++++++++ | ||
18 | 2 files changed, 52 insertions(+) | ||
19 | |||
20 | diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h | ||
21 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/include/hw/timer/aspeed_timer.h | 19 | --- a/hw/arm/mps2-tz.c |
23 | +++ b/include/hw/timer/aspeed_timer.h | 20 | +++ b/hw/arm/mps2-tz.c |
24 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ static void create_non_mpc_ram(MPS2TZMachineState *mms) |
25 | #define TYPE_ASPEED_TIMER "aspeed.timer" | ||
26 | #define TYPE_ASPEED_2400_TIMER TYPE_ASPEED_TIMER "-ast2400" | ||
27 | #define TYPE_ASPEED_2500_TIMER TYPE_ASPEED_TIMER "-ast2500" | ||
28 | +#define TYPE_ASPEED_2600_TIMER TYPE_ASPEED_TIMER "-ast2600" | ||
29 | |||
30 | #define ASPEED_TIMER_NR_TIMERS 8 | ||
31 | |||
32 | diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/hw/timer/aspeed_timer.c | ||
35 | +++ b/hw/timer/aspeed_timer.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static void aspeed_2500_timer_write(AspeedTimerCtrlState *s, hwaddr offset, | ||
37 | } | 22 | } |
38 | } | 23 | } |
39 | 24 | ||
40 | +static uint64_t aspeed_2600_timer_read(AspeedTimerCtrlState *s, hwaddr offset) | 25 | +static uint32_t boot_ram_size(MPS2TZMachineState *mms) |
41 | +{ | 26 | +{ |
42 | + uint64_t value; | 27 | + /* Return the size of the RAM block at guest address zero */ |
28 | + const RAMInfo *p; | ||
29 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); | ||
43 | + | 30 | + |
44 | + switch (offset) { | 31 | + for (p = mmc->raminfo; p->name; p++) { |
45 | + case 0x38: | 32 | + if (p->base == 0) { |
46 | + case 0x3C: | 33 | + return p->size; |
47 | + default: | 34 | + } |
48 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | ||
49 | + __func__, offset); | ||
50 | + value = 0; | ||
51 | + break; | ||
52 | + } | 35 | + } |
53 | + return value; | 36 | + g_assert_not_reached(); |
54 | +} | 37 | +} |
55 | + | 38 | + |
56 | +static void aspeed_2600_timer_write(AspeedTimerCtrlState *s, hwaddr offset, | 39 | static void mps2tz_common_init(MachineState *machine) |
57 | + uint64_t value) | ||
58 | +{ | ||
59 | + const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF); | ||
60 | + | ||
61 | + switch (offset) { | ||
62 | + case 0x3C: | ||
63 | + aspeed_timer_set_ctrl(s, s->ctrl & ~tv); | ||
64 | + break; | ||
65 | + | ||
66 | + case 0x38: | ||
67 | + default: | ||
68 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | ||
69 | + __func__, offset); | ||
70 | + break; | ||
71 | + } | ||
72 | +} | ||
73 | + | ||
74 | static void aspeed_init_one_timer(AspeedTimerCtrlState *s, uint8_t id) | ||
75 | { | 40 | { |
76 | AspeedTimer *t = &s->timers[id]; | 41 | MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); |
77 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_2500_timer_info = { | 42 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) |
78 | .class_init = aspeed_2500_timer_class_init, | 43 | |
79 | }; | 44 | create_non_mpc_ram(mms); |
80 | 45 | ||
81 | +static void aspeed_2600_timer_class_init(ObjectClass *klass, void *data) | 46 | - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); |
82 | +{ | 47 | + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, |
83 | + DeviceClass *dc = DEVICE_CLASS(klass); | 48 | + boot_ram_size(mms)); |
84 | + AspeedTimerClass *awc = ASPEED_TIMER_CLASS(klass); | ||
85 | + | ||
86 | + dc->desc = "ASPEED 2600 Timer"; | ||
87 | + awc->read = aspeed_2600_timer_read; | ||
88 | + awc->write = aspeed_2600_timer_write; | ||
89 | +} | ||
90 | + | ||
91 | +static const TypeInfo aspeed_2600_timer_info = { | ||
92 | + .name = TYPE_ASPEED_2600_TIMER, | ||
93 | + .parent = TYPE_ASPEED_TIMER, | ||
94 | + .class_init = aspeed_2600_timer_class_init, | ||
95 | +}; | ||
96 | + | ||
97 | static void aspeed_timer_register_types(void) | ||
98 | { | ||
99 | type_register_static(&aspeed_timer_info); | ||
100 | type_register_static(&aspeed_2400_timer_info); | ||
101 | type_register_static(&aspeed_2500_timer_info); | ||
102 | + type_register_static(&aspeed_2600_timer_info); | ||
103 | } | 49 | } |
104 | 50 | ||
105 | type_init(aspeed_timer_register_types) | 51 | static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, |
106 | -- | 52 | -- |
107 | 2.20.1 | 53 | 2.20.1 |
108 | 54 | ||
109 | 55 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | Add support for the mps3-an524 board; this is an SSE-200 based FPGA |
---|---|---|---|
2 | 2 | image, like the existing mps2-an521. It has a usefully larger amount | |
3 | Update the headers against commit: | 3 | of RAM, and a PL031 RTC, as well as some more minor differences. |
4 | 0f1a7b3fac05 ("timer-of: don't use conditional expression | 4 | |
5 | with mixed 'void' types") | 5 | In real hardware this image runs on a newer generation of the FPGA |
6 | 6 | board, the MPS3 rather than the older MPS2. Architecturally the two | |
7 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 7 | boards are similar, so we implement the MPS3 boards in the mps2-tz.c |
8 | Acked-by: Marc Zyngier <maz@kernel.org> | 8 | file as variations of the existing MPS2 boards. |
9 | Message-id: 20191003154640.22451-2-eric.auger@redhat.com | 9 | |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20210215115138.20465-21-peter.maydell@linaro.org | ||
11 | --- | 13 | --- |
12 | include/standard-headers/asm-x86/bootparam.h | 2 + | 14 | hw/arm/mps2-tz.c | 139 +++++++++++++++++++++++++++++++++++++++++++++-- |
13 | include/standard-headers/asm-x86/kvm_para.h | 1 + | 15 | 1 file changed, 135 insertions(+), 4 deletions(-) |
14 | include/standard-headers/linux/ethtool.h | 24 +++ | 16 | |
15 | include/standard-headers/linux/pci_regs.h | 19 +- | 17 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
16 | include/standard-headers/linux/virtio_fs.h | 19 ++ | ||
17 | include/standard-headers/linux/virtio_ids.h | 2 + | ||
18 | include/standard-headers/linux/virtio_iommu.h | 165 ++++++++++++++++++ | ||
19 | include/standard-headers/linux/virtio_pmem.h | 6 +- | ||
20 | linux-headers/asm-arm/kvm.h | 16 +- | ||
21 | linux-headers/asm-arm/unistd-common.h | 2 + | ||
22 | linux-headers/asm-arm64/kvm.h | 21 ++- | ||
23 | linux-headers/asm-generic/mman-common.h | 18 +- | ||
24 | linux-headers/asm-generic/mman.h | 10 +- | ||
25 | linux-headers/asm-generic/unistd.h | 10 +- | ||
26 | linux-headers/asm-mips/mman.h | 3 + | ||
27 | linux-headers/asm-mips/unistd_n32.h | 1 + | ||
28 | linux-headers/asm-mips/unistd_n64.h | 1 + | ||
29 | linux-headers/asm-mips/unistd_o32.h | 1 + | ||
30 | linux-headers/asm-powerpc/mman.h | 6 +- | ||
31 | linux-headers/asm-powerpc/unistd_32.h | 2 + | ||
32 | linux-headers/asm-powerpc/unistd_64.h | 2 + | ||
33 | linux-headers/asm-s390/kvm.h | 6 + | ||
34 | linux-headers/asm-s390/unistd_32.h | 2 + | ||
35 | linux-headers/asm-s390/unistd_64.h | 2 + | ||
36 | linux-headers/asm-x86/kvm.h | 28 ++- | ||
37 | linux-headers/asm-x86/unistd.h | 2 +- | ||
38 | linux-headers/asm-x86/unistd_32.h | 2 + | ||
39 | linux-headers/asm-x86/unistd_64.h | 2 + | ||
40 | linux-headers/asm-x86/unistd_x32.h | 2 + | ||
41 | linux-headers/linux/kvm.h | 12 +- | ||
42 | linux-headers/linux/psp-sev.h | 5 +- | ||
43 | linux-headers/linux/vfio.h | 71 +++++--- | ||
44 | 32 files changed, 406 insertions(+), 59 deletions(-) | ||
45 | create mode 100644 include/standard-headers/linux/virtio_fs.h | ||
46 | create mode 100644 include/standard-headers/linux/virtio_iommu.h | ||
47 | |||
48 | diff --git a/include/standard-headers/asm-x86/bootparam.h b/include/standard-headers/asm-x86/bootparam.h | ||
49 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
50 | --- a/include/standard-headers/asm-x86/bootparam.h | 19 | --- a/hw/arm/mps2-tz.c |
51 | +++ b/include/standard-headers/asm-x86/bootparam.h | 20 | +++ b/hw/arm/mps2-tz.c |
52 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ |
53 | #define XLF_EFI_HANDOVER_32 (1<<2) | 22 | * This source file covers the following FPGA images, for TrustZone cores: |
54 | #define XLF_EFI_HANDOVER_64 (1<<3) | 23 | * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 |
55 | #define XLF_EFI_KEXEC (1<<4) | 24 | * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 |
56 | +#define XLF_5LEVEL (1<<5) | 25 | + * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524 |
57 | +#define XLF_5LEVEL_ENABLED (1<<6) | 26 | * |
58 | 27 | * Links to the TRM for the board itself and to the various Application | |
59 | 28 | * Notes which document the FPGA images can be found here: | |
60 | #endif /* _ASM_X86_BOOTPARAM_H */ | ||
61 | diff --git a/include/standard-headers/asm-x86/kvm_para.h b/include/standard-headers/asm-x86/kvm_para.h | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/include/standard-headers/asm-x86/kvm_para.h | ||
64 | +++ b/include/standard-headers/asm-x86/kvm_para.h | ||
65 | @@ -XXX,XX +XXX,XX @@ | 29 | @@ -XXX,XX +XXX,XX @@ |
66 | #define KVM_FEATURE_ASYNC_PF_VMEXIT 10 | 30 | * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html |
67 | #define KVM_FEATURE_PV_SEND_IPI 11 | 31 | * Application Note AN521: |
68 | #define KVM_FEATURE_POLL_CONTROL 12 | 32 | * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html |
69 | +#define KVM_FEATURE_PV_SCHED_YIELD 13 | 33 | + * Application Note AN524: |
70 | 34 | + * https://developer.arm.com/documentation/dai0524/latest/ | |
71 | #define KVM_HINTS_REALTIME 0 | 35 | * |
72 | 36 | * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide | |
73 | diff --git a/include/standard-headers/linux/ethtool.h b/include/standard-headers/linux/ethtool.h | 37 | * (ARM ECM0601256) for the details of some of the device layout: |
74 | index XXXXXXX..XXXXXXX 100644 | 38 | * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html |
75 | --- a/include/standard-headers/linux/ethtool.h | 39 | - * Similarly, the AN521 uses the SSE-200, and the SSE-200 TRM defines |
76 | +++ b/include/standard-headers/linux/ethtool.h | 40 | + * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines |
77 | @@ -XXX,XX +XXX,XX @@ struct ethtool_tunable { | 41 | * most of the device layout: |
78 | #define ETHTOOL_PHY_FAST_LINK_DOWN_ON 0 | 42 | * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf |
79 | #define ETHTOOL_PHY_FAST_LINK_DOWN_OFF 0xff | ||
80 | |||
81 | +/* Energy Detect Power Down (EDPD) is a feature supported by some PHYs, where | ||
82 | + * the PHY's RX & TX blocks are put into a low-power mode when there is no | ||
83 | + * link detected (typically cable is un-plugged). For RX, only a minimal | ||
84 | + * link-detection is available, and for TX the PHY wakes up to send link pulses | ||
85 | + * to avoid any lock-ups in case the peer PHY may also be running in EDPD mode. | ||
86 | + * | ||
87 | + * Some PHYs may support configuration of the wake-up interval for TX pulses, | ||
88 | + * and some PHYs may support only disabling TX pulses entirely. For the latter | ||
89 | + * a special value is required (ETHTOOL_PHY_EDPD_NO_TX) so that this can be | ||
90 | + * configured from userspace (should the user want it). | ||
91 | + * | ||
92 | + * The interval units for TX wake-up are in milliseconds, since this should | ||
93 | + * cover a reasonable range of intervals: | ||
94 | + * - from 1 millisecond, which does not sound like much of a power-saver | ||
95 | + * - to ~65 seconds which is quite a lot to wait for a link to come up when | ||
96 | + * plugging a cable | ||
97 | + */ | ||
98 | +#define ETHTOOL_PHY_EDPD_DFLT_TX_MSECS 0xffff | ||
99 | +#define ETHTOOL_PHY_EDPD_NO_TX 0xfffe | ||
100 | +#define ETHTOOL_PHY_EDPD_DISABLE 0 | ||
101 | + | ||
102 | enum phy_tunable_id { | ||
103 | ETHTOOL_PHY_ID_UNSPEC, | ||
104 | ETHTOOL_PHY_DOWNSHIFT, | ||
105 | ETHTOOL_PHY_FAST_LINK_DOWN, | ||
106 | + ETHTOOL_PHY_EDPD, | ||
107 | /* | ||
108 | * Add your fresh new phy tunable attribute above and remember to update | ||
109 | * phy_tunable_strings[] in net/core/ethtool.c | ||
110 | @@ -XXX,XX +XXX,XX @@ enum ethtool_link_mode_bit_indices { | ||
111 | ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT = 64, | ||
112 | ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT = 65, | ||
113 | ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66, | ||
114 | + ETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67, | ||
115 | + ETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68, | ||
116 | |||
117 | /* must be last entry */ | ||
118 | __ETHTOOL_LINK_MODE_MASK_NBITS | ||
119 | diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h | ||
120 | index XXXXXXX..XXXXXXX 100644 | ||
121 | --- a/include/standard-headers/linux/pci_regs.h | ||
122 | +++ b/include/standard-headers/linux/pci_regs.h | ||
123 | @@ -XXX,XX +XXX,XX @@ | ||
124 | #define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */ | ||
125 | #define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */ | ||
126 | #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */ | ||
127 | +#define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */ | ||
128 | #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ | ||
129 | #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ | ||
130 | #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ | ||
131 | @@ -XXX,XX +XXX,XX @@ | ||
132 | #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ | ||
133 | #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ | ||
134 | #define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */ | ||
135 | +#define PCI_EXP_LNKSTA_CLS_32_0GB 0x0005 /* Current Link Speed 32.0GT/s */ | ||
136 | #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ | ||
137 | #define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */ | ||
138 | #define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */ | ||
139 | @@ -XXX,XX +XXX,XX @@ | ||
140 | #define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */ | ||
141 | #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */ | ||
142 | #define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */ | ||
143 | +#define PCI_EXP_SLTCTL_ATTN_IND_SHIFT 6 /* Attention Indicator shift */ | ||
144 | #define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 /* Attention Indicator on */ | ||
145 | #define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */ | ||
146 | #define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 /* Attention Indicator off */ | ||
147 | @@ -XXX,XX +XXX,XX @@ | ||
148 | #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */ | ||
149 | #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */ | ||
150 | #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ | ||
151 | +#define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020 /* Supported Speed 32GT/s */ | ||
152 | #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ | ||
153 | #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ | ||
154 | #define PCI_EXP_LNKCTL2_TLS 0x000f | ||
155 | @@ -XXX,XX +XXX,XX @@ | ||
156 | #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ | ||
157 | #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ | ||
158 | #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ | ||
159 | +#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ | ||
160 | #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ | ||
161 | #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ | ||
162 | #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ | ||
163 | @@ -XXX,XX +XXX,XX @@ | ||
164 | #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ | ||
165 | #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ | ||
166 | #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ | ||
167 | -#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM | ||
168 | +#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ | ||
169 | +#define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ | ||
170 | +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT | ||
171 | |||
172 | #define PCI_EXT_CAP_DSN_SIZEOF 12 | ||
173 | #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 | ||
174 | @@ -XXX,XX +XXX,XX @@ | ||
175 | #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ | ||
176 | #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ | ||
177 | |||
178 | +/* Data Link Feature */ | ||
179 | +#define PCI_DLF_CAP 0x04 /* Capabilities Register */ | ||
180 | +#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ | ||
181 | + | ||
182 | +/* Physical Layer 16.0 GT/s */ | ||
183 | +#define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ | ||
184 | +#define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F | ||
185 | +#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 | ||
186 | +#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 | ||
187 | + | ||
188 | #endif /* LINUX_PCI_REGS_H */ | ||
189 | diff --git a/include/standard-headers/linux/virtio_fs.h b/include/standard-headers/linux/virtio_fs.h | ||
190 | new file mode 100644 | ||
191 | index XXXXXXX..XXXXXXX | ||
192 | --- /dev/null | ||
193 | +++ b/include/standard-headers/linux/virtio_fs.h | ||
194 | @@ -XXX,XX +XXX,XX @@ | ||
195 | +/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */ | ||
196 | + | ||
197 | +#ifndef _LINUX_VIRTIO_FS_H | ||
198 | +#define _LINUX_VIRTIO_FS_H | ||
199 | + | ||
200 | +#include "standard-headers/linux/types.h" | ||
201 | +#include "standard-headers/linux/virtio_ids.h" | ||
202 | +#include "standard-headers/linux/virtio_config.h" | ||
203 | +#include "standard-headers/linux/virtio_types.h" | ||
204 | + | ||
205 | +struct virtio_fs_config { | ||
206 | + /* Filesystem name (UTF-8, not NUL-terminated, padded with NULs) */ | ||
207 | + uint8_t tag[36]; | ||
208 | + | ||
209 | + /* Number of request queues */ | ||
210 | + uint32_t num_request_queues; | ||
211 | +} QEMU_PACKED; | ||
212 | + | ||
213 | +#endif /* _LINUX_VIRTIO_FS_H */ | ||
214 | diff --git a/include/standard-headers/linux/virtio_ids.h b/include/standard-headers/linux/virtio_ids.h | ||
215 | index XXXXXXX..XXXXXXX 100644 | ||
216 | --- a/include/standard-headers/linux/virtio_ids.h | ||
217 | +++ b/include/standard-headers/linux/virtio_ids.h | ||
218 | @@ -XXX,XX +XXX,XX @@ | ||
219 | #define VIRTIO_ID_INPUT 18 /* virtio input */ | ||
220 | #define VIRTIO_ID_VSOCK 19 /* virtio vsock transport */ | ||
221 | #define VIRTIO_ID_CRYPTO 20 /* virtio crypto */ | ||
222 | +#define VIRTIO_ID_IOMMU 23 /* virtio IOMMU */ | ||
223 | +#define VIRTIO_ID_FS 26 /* virtio filesystem */ | ||
224 | #define VIRTIO_ID_PMEM 27 /* virtio pmem */ | ||
225 | |||
226 | #endif /* _LINUX_VIRTIO_IDS_H */ | ||
227 | diff --git a/include/standard-headers/linux/virtio_iommu.h b/include/standard-headers/linux/virtio_iommu.h | ||
228 | new file mode 100644 | ||
229 | index XXXXXXX..XXXXXXX | ||
230 | --- /dev/null | ||
231 | +++ b/include/standard-headers/linux/virtio_iommu.h | ||
232 | @@ -XXX,XX +XXX,XX @@ | ||
233 | +/* SPDX-License-Identifier: BSD-3-Clause */ | ||
234 | +/* | ||
235 | + * Virtio-iommu definition v0.12 | ||
236 | + * | ||
237 | + * Copyright (C) 2019 Arm Ltd. | ||
238 | + */ | ||
239 | +#ifndef _LINUX_VIRTIO_IOMMU_H | ||
240 | +#define _LINUX_VIRTIO_IOMMU_H | ||
241 | + | ||
242 | +#include "standard-headers/linux/types.h" | ||
243 | + | ||
244 | +/* Feature bits */ | ||
245 | +#define VIRTIO_IOMMU_F_INPUT_RANGE 0 | ||
246 | +#define VIRTIO_IOMMU_F_DOMAIN_RANGE 1 | ||
247 | +#define VIRTIO_IOMMU_F_MAP_UNMAP 2 | ||
248 | +#define VIRTIO_IOMMU_F_BYPASS 3 | ||
249 | +#define VIRTIO_IOMMU_F_PROBE 4 | ||
250 | +#define VIRTIO_IOMMU_F_MMIO 5 | ||
251 | + | ||
252 | +struct virtio_iommu_range_64 { | ||
253 | + uint64_t start; | ||
254 | + uint64_t end; | ||
255 | +}; | ||
256 | + | ||
257 | +struct virtio_iommu_range_32 { | ||
258 | + uint32_t start; | ||
259 | + uint32_t end; | ||
260 | +}; | ||
261 | + | ||
262 | +struct virtio_iommu_config { | ||
263 | + /* Supported page sizes */ | ||
264 | + uint64_t page_size_mask; | ||
265 | + /* Supported IOVA range */ | ||
266 | + struct virtio_iommu_range_64 input_range; | ||
267 | + /* Max domain ID size */ | ||
268 | + struct virtio_iommu_range_32 domain_range; | ||
269 | + /* Probe buffer size */ | ||
270 | + uint32_t probe_size; | ||
271 | +}; | ||
272 | + | ||
273 | +/* Request types */ | ||
274 | +#define VIRTIO_IOMMU_T_ATTACH 0x01 | ||
275 | +#define VIRTIO_IOMMU_T_DETACH 0x02 | ||
276 | +#define VIRTIO_IOMMU_T_MAP 0x03 | ||
277 | +#define VIRTIO_IOMMU_T_UNMAP 0x04 | ||
278 | +#define VIRTIO_IOMMU_T_PROBE 0x05 | ||
279 | + | ||
280 | +/* Status types */ | ||
281 | +#define VIRTIO_IOMMU_S_OK 0x00 | ||
282 | +#define VIRTIO_IOMMU_S_IOERR 0x01 | ||
283 | +#define VIRTIO_IOMMU_S_UNSUPP 0x02 | ||
284 | +#define VIRTIO_IOMMU_S_DEVERR 0x03 | ||
285 | +#define VIRTIO_IOMMU_S_INVAL 0x04 | ||
286 | +#define VIRTIO_IOMMU_S_RANGE 0x05 | ||
287 | +#define VIRTIO_IOMMU_S_NOENT 0x06 | ||
288 | +#define VIRTIO_IOMMU_S_FAULT 0x07 | ||
289 | +#define VIRTIO_IOMMU_S_NOMEM 0x08 | ||
290 | + | ||
291 | +struct virtio_iommu_req_head { | ||
292 | + uint8_t type; | ||
293 | + uint8_t reserved[3]; | ||
294 | +}; | ||
295 | + | ||
296 | +struct virtio_iommu_req_tail { | ||
297 | + uint8_t status; | ||
298 | + uint8_t reserved[3]; | ||
299 | +}; | ||
300 | + | ||
301 | +struct virtio_iommu_req_attach { | ||
302 | + struct virtio_iommu_req_head head; | ||
303 | + uint32_t domain; | ||
304 | + uint32_t endpoint; | ||
305 | + uint8_t reserved[8]; | ||
306 | + struct virtio_iommu_req_tail tail; | ||
307 | +}; | ||
308 | + | ||
309 | +struct virtio_iommu_req_detach { | ||
310 | + struct virtio_iommu_req_head head; | ||
311 | + uint32_t domain; | ||
312 | + uint32_t endpoint; | ||
313 | + uint8_t reserved[8]; | ||
314 | + struct virtio_iommu_req_tail tail; | ||
315 | +}; | ||
316 | + | ||
317 | +#define VIRTIO_IOMMU_MAP_F_READ (1 << 0) | ||
318 | +#define VIRTIO_IOMMU_MAP_F_WRITE (1 << 1) | ||
319 | +#define VIRTIO_IOMMU_MAP_F_MMIO (1 << 2) | ||
320 | + | ||
321 | +#define VIRTIO_IOMMU_MAP_F_MASK (VIRTIO_IOMMU_MAP_F_READ | \ | ||
322 | + VIRTIO_IOMMU_MAP_F_WRITE | \ | ||
323 | + VIRTIO_IOMMU_MAP_F_MMIO) | ||
324 | + | ||
325 | +struct virtio_iommu_req_map { | ||
326 | + struct virtio_iommu_req_head head; | ||
327 | + uint32_t domain; | ||
328 | + uint64_t virt_start; | ||
329 | + uint64_t virt_end; | ||
330 | + uint64_t phys_start; | ||
331 | + uint32_t flags; | ||
332 | + struct virtio_iommu_req_tail tail; | ||
333 | +}; | ||
334 | + | ||
335 | +struct virtio_iommu_req_unmap { | ||
336 | + struct virtio_iommu_req_head head; | ||
337 | + uint32_t domain; | ||
338 | + uint64_t virt_start; | ||
339 | + uint64_t virt_end; | ||
340 | + uint8_t reserved[4]; | ||
341 | + struct virtio_iommu_req_tail tail; | ||
342 | +}; | ||
343 | + | ||
344 | +#define VIRTIO_IOMMU_PROBE_T_NONE 0 | ||
345 | +#define VIRTIO_IOMMU_PROBE_T_RESV_MEM 1 | ||
346 | + | ||
347 | +#define VIRTIO_IOMMU_PROBE_T_MASK 0xfff | ||
348 | + | ||
349 | +struct virtio_iommu_probe_property { | ||
350 | + uint16_t type; | ||
351 | + uint16_t length; | ||
352 | +}; | ||
353 | + | ||
354 | +#define VIRTIO_IOMMU_RESV_MEM_T_RESERVED 0 | ||
355 | +#define VIRTIO_IOMMU_RESV_MEM_T_MSI 1 | ||
356 | + | ||
357 | +struct virtio_iommu_probe_resv_mem { | ||
358 | + struct virtio_iommu_probe_property head; | ||
359 | + uint8_t subtype; | ||
360 | + uint8_t reserved[3]; | ||
361 | + uint64_t start; | ||
362 | + uint64_t end; | ||
363 | +}; | ||
364 | + | ||
365 | +struct virtio_iommu_req_probe { | ||
366 | + struct virtio_iommu_req_head head; | ||
367 | + uint32_t endpoint; | ||
368 | + uint8_t reserved[64]; | ||
369 | + | ||
370 | + uint8_t properties[]; | ||
371 | + | ||
372 | + /* | ||
373 | + * Tail follows the variable-length properties array. No padding, | ||
374 | + * property lengths are all aligned on 8 bytes. | ||
375 | + */ | ||
376 | +}; | ||
377 | + | ||
378 | +/* Fault types */ | ||
379 | +#define VIRTIO_IOMMU_FAULT_R_UNKNOWN 0 | ||
380 | +#define VIRTIO_IOMMU_FAULT_R_DOMAIN 1 | ||
381 | +#define VIRTIO_IOMMU_FAULT_R_MAPPING 2 | ||
382 | + | ||
383 | +#define VIRTIO_IOMMU_FAULT_F_READ (1 << 0) | ||
384 | +#define VIRTIO_IOMMU_FAULT_F_WRITE (1 << 1) | ||
385 | +#define VIRTIO_IOMMU_FAULT_F_EXEC (1 << 2) | ||
386 | +#define VIRTIO_IOMMU_FAULT_F_ADDRESS (1 << 8) | ||
387 | + | ||
388 | +struct virtio_iommu_fault { | ||
389 | + uint8_t reason; | ||
390 | + uint8_t reserved[3]; | ||
391 | + uint32_t flags; | ||
392 | + uint32_t endpoint; | ||
393 | + uint8_t reserved2[4]; | ||
394 | + uint64_t address; | ||
395 | +}; | ||
396 | + | ||
397 | +#endif | ||
398 | diff --git a/include/standard-headers/linux/virtio_pmem.h b/include/standard-headers/linux/virtio_pmem.h | ||
399 | index XXXXXXX..XXXXXXX 100644 | ||
400 | --- a/include/standard-headers/linux/virtio_pmem.h | ||
401 | +++ b/include/standard-headers/linux/virtio_pmem.h | ||
402 | @@ -XXX,XX +XXX,XX @@ | ||
403 | -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ | ||
404 | +/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause */ | ||
405 | /* | ||
406 | * Definitions for virtio-pmem devices. | ||
407 | * | 43 | * |
408 | @@ -XXX,XX +XXX,XX @@ | 44 | @@ -XXX,XX +XXX,XX @@ |
409 | * Author(s): Pankaj Gupta <pagupta@redhat.com> | 45 | #include "hw/qdev-clock.h" |
410 | */ | 46 | #include "qom/object.h" |
411 | 47 | ||
412 | -#ifndef _UAPI_LINUX_VIRTIO_PMEM_H | 48 | -#define MPS2TZ_NUMIRQ_MAX 92 |
413 | -#define _UAPI_LINUX_VIRTIO_PMEM_H | 49 | +#define MPS2TZ_NUMIRQ_MAX 95 |
414 | +#ifndef _LINUX_VIRTIO_PMEM_H | 50 | #define MPS2TZ_RAM_MAX 4 |
415 | +#define _LINUX_VIRTIO_PMEM_H | 51 | |
416 | 52 | typedef enum MPS2TZFPGAType { | |
417 | #include "standard-headers/linux/types.h" | 53 | FPGA_AN505, |
418 | #include "standard-headers/linux/virtio_ids.h" | 54 | FPGA_AN521, |
419 | diff --git a/linux-headers/asm-arm/kvm.h b/linux-headers/asm-arm/kvm.h | 55 | + FPGA_AN524, |
420 | index XXXXXXX..XXXXXXX 100644 | 56 | } MPS2TZFPGAType; |
421 | --- a/linux-headers/asm-arm/kvm.h | 57 | |
422 | +++ b/linux-headers/asm-arm/kvm.h | ||
423 | @@ -XXX,XX +XXX,XX @@ struct kvm_vcpu_events { | ||
424 | #define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM | KVM_REG_SIZE_U64 | \ | ||
425 | KVM_REG_ARM_FW | ((r) & 0xffff)) | ||
426 | #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) | ||
427 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1) | ||
428 | + /* Higher values mean better protection. */ | ||
429 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0 | ||
430 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1 | ||
431 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2 | ||
432 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2) | ||
433 | + /* Higher values mean better protection. */ | ||
434 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0 | ||
435 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1 | ||
436 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2 | ||
437 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3 | ||
438 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4) | ||
439 | |||
440 | /* Device Control API: ARM VGIC */ | ||
441 | #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 | ||
442 | @@ -XXX,XX +XXX,XX @@ struct kvm_vcpu_events { | ||
443 | #define KVM_DEV_ARM_ITS_CTRL_RESET 4 | ||
444 | |||
445 | /* KVM_IRQ_LINE irq field index values */ | ||
446 | +#define KVM_ARM_IRQ_VCPU2_SHIFT 28 | ||
447 | +#define KVM_ARM_IRQ_VCPU2_MASK 0xf | ||
448 | #define KVM_ARM_IRQ_TYPE_SHIFT 24 | ||
449 | -#define KVM_ARM_IRQ_TYPE_MASK 0xff | ||
450 | +#define KVM_ARM_IRQ_TYPE_MASK 0xf | ||
451 | #define KVM_ARM_IRQ_VCPU_SHIFT 16 | ||
452 | #define KVM_ARM_IRQ_VCPU_MASK 0xff | ||
453 | #define KVM_ARM_IRQ_NUM_SHIFT 0 | ||
454 | diff --git a/linux-headers/asm-arm/unistd-common.h b/linux-headers/asm-arm/unistd-common.h | ||
455 | index XXXXXXX..XXXXXXX 100644 | ||
456 | --- a/linux-headers/asm-arm/unistd-common.h | ||
457 | +++ b/linux-headers/asm-arm/unistd-common.h | ||
458 | @@ -XXX,XX +XXX,XX @@ | ||
459 | #define __NR_fsconfig (__NR_SYSCALL_BASE + 431) | ||
460 | #define __NR_fsmount (__NR_SYSCALL_BASE + 432) | ||
461 | #define __NR_fspick (__NR_SYSCALL_BASE + 433) | ||
462 | +#define __NR_pidfd_open (__NR_SYSCALL_BASE + 434) | ||
463 | +#define __NR_clone3 (__NR_SYSCALL_BASE + 435) | ||
464 | |||
465 | #endif /* _ASM_ARM_UNISTD_COMMON_H */ | ||
466 | diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h | ||
467 | index XXXXXXX..XXXXXXX 100644 | ||
468 | --- a/linux-headers/asm-arm64/kvm.h | ||
469 | +++ b/linux-headers/asm-arm64/kvm.h | ||
470 | @@ -XXX,XX +XXX,XX @@ struct kvm_vcpu_events { | ||
471 | #define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ | ||
472 | KVM_REG_ARM_FW | ((r) & 0xffff)) | ||
473 | #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) | ||
474 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1) | ||
475 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0 | ||
476 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1 | ||
477 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2 | ||
478 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2) | ||
479 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0 | ||
480 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1 | ||
481 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2 | ||
482 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3 | ||
483 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4) | ||
484 | |||
485 | /* SVE registers */ | ||
486 | #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) | ||
487 | @@ -XXX,XX +XXX,XX @@ struct kvm_vcpu_events { | ||
488 | KVM_REG_SIZE_U256 | \ | ||
489 | ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) | ||
490 | |||
491 | +/* | ||
492 | + * Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and | ||
493 | + * KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness- | ||
494 | + * invariant layout which differs from the layout used for the FPSIMD | ||
495 | + * V-registers on big-endian systems: see sigcontext.h for more explanation. | ||
496 | + */ | ||
497 | + | ||
498 | #define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN | ||
499 | #define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX | ||
500 | |||
501 | @@ -XXX,XX +XXX,XX @@ struct kvm_vcpu_events { | ||
502 | #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 | ||
503 | |||
504 | /* KVM_IRQ_LINE irq field index values */ | ||
505 | +#define KVM_ARM_IRQ_VCPU2_SHIFT 28 | ||
506 | +#define KVM_ARM_IRQ_VCPU2_MASK 0xf | ||
507 | #define KVM_ARM_IRQ_TYPE_SHIFT 24 | ||
508 | -#define KVM_ARM_IRQ_TYPE_MASK 0xff | ||
509 | +#define KVM_ARM_IRQ_TYPE_MASK 0xf | ||
510 | #define KVM_ARM_IRQ_VCPU_SHIFT 16 | ||
511 | #define KVM_ARM_IRQ_VCPU_MASK 0xff | ||
512 | #define KVM_ARM_IRQ_NUM_SHIFT 0 | ||
513 | diff --git a/linux-headers/asm-generic/mman-common.h b/linux-headers/asm-generic/mman-common.h | ||
514 | index XXXXXXX..XXXXXXX 100644 | ||
515 | --- a/linux-headers/asm-generic/mman-common.h | ||
516 | +++ b/linux-headers/asm-generic/mman-common.h | ||
517 | @@ -XXX,XX +XXX,XX @@ | ||
518 | #define MAP_TYPE 0x0f /* Mask for type of mapping */ | ||
519 | #define MAP_FIXED 0x10 /* Interpret addr exactly */ | ||
520 | #define MAP_ANONYMOUS 0x20 /* don't use a file */ | ||
521 | -#ifdef CONFIG_MMAP_ALLOW_UNINITIALIZED | ||
522 | -# define MAP_UNINITIALIZED 0x4000000 /* For anonymous mmap, memory could be uninitialized */ | ||
523 | -#else | ||
524 | -# define MAP_UNINITIALIZED 0x0 /* Don't support this flag */ | ||
525 | -#endif | ||
526 | |||
527 | -/* 0x0100 - 0x80000 flags are defined in asm-generic/mman.h */ | ||
528 | +/* 0x0100 - 0x4000 flags are defined in asm-generic/mman.h */ | ||
529 | +#define MAP_POPULATE 0x008000 /* populate (prefault) pagetables */ | ||
530 | +#define MAP_NONBLOCK 0x010000 /* do not block on IO */ | ||
531 | +#define MAP_STACK 0x020000 /* give out an address that is best suited for process/thread stacks */ | ||
532 | +#define MAP_HUGETLB 0x040000 /* create a huge page mapping */ | ||
533 | +#define MAP_SYNC 0x080000 /* perform synchronous page faults for the mapping */ | ||
534 | #define MAP_FIXED_NOREPLACE 0x100000 /* MAP_FIXED which doesn't unmap underlying mapping */ | ||
535 | |||
536 | +#define MAP_UNINITIALIZED 0x4000000 /* For anonymous mmap, memory could be | ||
537 | + * uninitialized */ | ||
538 | + | ||
539 | /* | 58 | /* |
540 | * Flags for mlock | 59 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState { |
541 | */ | 60 | TZPPC ppc[5]; |
542 | @@ -XXX,XX +XXX,XX @@ | 61 | TZMPC mpc[3]; |
543 | #define MADV_WIPEONFORK 18 /* Zero memory on fork, child only */ | 62 | PL022State spi[5]; |
544 | #define MADV_KEEPONFORK 19 /* Undo MADV_WIPEONFORK */ | 63 | - ArmSbconI2CState i2c[4]; |
545 | 64 | + ArmSbconI2CState i2c[5]; | |
546 | +#define MADV_COLD 20 /* deactivate these pages */ | 65 | UnimplementedDeviceState i2s_audio; |
547 | +#define MADV_PAGEOUT 21 /* reclaim these pages */ | 66 | UnimplementedDeviceState gpio[4]; |
548 | + | 67 | UnimplementedDeviceState gfx; |
549 | /* compatibility flags */ | 68 | + UnimplementedDeviceState cldc; |
550 | #define MAP_FILE 0 | 69 | + UnimplementedDeviceState rtc; |
551 | 70 | PL080State dma[4]; | |
552 | diff --git a/linux-headers/asm-generic/mman.h b/linux-headers/asm-generic/mman.h | 71 | TZMSC msc[4]; |
553 | index XXXXXXX..XXXXXXX 100644 | 72 | - CMSDKAPBUART uart[5]; |
554 | --- a/linux-headers/asm-generic/mman.h | 73 | + CMSDKAPBUART uart[6]; |
555 | +++ b/linux-headers/asm-generic/mman.h | 74 | SplitIRQ sec_resp_splitter; |
556 | @@ -XXX,XX +XXX,XX @@ | 75 | qemu_or_irq uart_irq_orgate; |
557 | #define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ | 76 | DeviceState *lan9118; |
558 | #define MAP_LOCKED 0x2000 /* pages are locked */ | 77 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState { |
559 | #define MAP_NORESERVE 0x4000 /* don't check for reservations */ | 78 | #define TYPE_MPS2TZ_MACHINE "mps2tz" |
560 | -#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ | 79 | #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") |
561 | -#define MAP_NONBLOCK 0x10000 /* do not block on IO */ | 80 | #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") |
562 | -#define MAP_STACK 0x20000 /* give out an address that is best suited for process/thread stacks */ | 81 | +#define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524") |
563 | -#define MAP_HUGETLB 0x40000 /* create a huge page mapping */ | 82 | |
564 | -#define MAP_SYNC 0x80000 /* perform synchronous page faults for the mapping */ | 83 | OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) |
565 | 84 | ||
566 | -/* Bits [26:31] are reserved, see mman-common.h for MAP_HUGETLB usage */ | 85 | @@ -XXX,XX +XXX,XX @@ static const uint32_t an505_oscclk[] = { |
567 | +/* | 86 | 25000000, |
568 | + * Bits [26:31] are reserved, see asm-generic/hugetlb_encode.h | ||
569 | + * for MAP_HUGETLB usage | ||
570 | + */ | ||
571 | |||
572 | #define MCL_CURRENT 1 /* lock all current mappings */ | ||
573 | #define MCL_FUTURE 2 /* lock all future mappings */ | ||
574 | diff --git a/linux-headers/asm-generic/unistd.h b/linux-headers/asm-generic/unistd.h | ||
575 | index XXXXXXX..XXXXXXX 100644 | ||
576 | --- a/linux-headers/asm-generic/unistd.h | ||
577 | +++ b/linux-headers/asm-generic/unistd.h | ||
578 | @@ -XXX,XX +XXX,XX @@ __SYSCALL(__NR_semget, sys_semget) | ||
579 | __SC_COMP(__NR_semctl, sys_semctl, compat_sys_semctl) | ||
580 | #if defined(__ARCH_WANT_TIME32_SYSCALLS) || __BITS_PER_LONG != 32 | ||
581 | #define __NR_semtimedop 192 | ||
582 | -__SC_COMP(__NR_semtimedop, sys_semtimedop, sys_semtimedop_time32) | ||
583 | +__SC_3264(__NR_semtimedop, sys_semtimedop_time32, sys_semtimedop) | ||
584 | #endif | ||
585 | #define __NR_semop 193 | ||
586 | __SYSCALL(__NR_semop, sys_semop) | ||
587 | @@ -XXX,XX +XXX,XX @@ __SYSCALL(__NR_fsconfig, sys_fsconfig) | ||
588 | __SYSCALL(__NR_fsmount, sys_fsmount) | ||
589 | #define __NR_fspick 433 | ||
590 | __SYSCALL(__NR_fspick, sys_fspick) | ||
591 | +#define __NR_pidfd_open 434 | ||
592 | +__SYSCALL(__NR_pidfd_open, sys_pidfd_open) | ||
593 | +#ifdef __ARCH_WANT_SYS_CLONE3 | ||
594 | +#define __NR_clone3 435 | ||
595 | +__SYSCALL(__NR_clone3, sys_clone3) | ||
596 | +#endif | ||
597 | |||
598 | #undef __NR_syscalls | ||
599 | -#define __NR_syscalls 434 | ||
600 | +#define __NR_syscalls 436 | ||
601 | |||
602 | /* | ||
603 | * 32 bit systems traditionally used different | ||
604 | diff --git a/linux-headers/asm-mips/mman.h b/linux-headers/asm-mips/mman.h | ||
605 | index XXXXXXX..XXXXXXX 100644 | ||
606 | --- a/linux-headers/asm-mips/mman.h | ||
607 | +++ b/linux-headers/asm-mips/mman.h | ||
608 | @@ -XXX,XX +XXX,XX @@ | ||
609 | #define MADV_WIPEONFORK 18 /* Zero memory on fork, child only */ | ||
610 | #define MADV_KEEPONFORK 19 /* Undo MADV_WIPEONFORK */ | ||
611 | |||
612 | +#define MADV_COLD 20 /* deactivate these pages */ | ||
613 | +#define MADV_PAGEOUT 21 /* reclaim these pages */ | ||
614 | + | ||
615 | /* compatibility flags */ | ||
616 | #define MAP_FILE 0 | ||
617 | |||
618 | diff --git a/linux-headers/asm-mips/unistd_n32.h b/linux-headers/asm-mips/unistd_n32.h | ||
619 | index XXXXXXX..XXXXXXX 100644 | ||
620 | --- a/linux-headers/asm-mips/unistd_n32.h | ||
621 | +++ b/linux-headers/asm-mips/unistd_n32.h | ||
622 | @@ -XXX,XX +XXX,XX @@ | ||
623 | #define __NR_fsconfig (__NR_Linux + 431) | ||
624 | #define __NR_fsmount (__NR_Linux + 432) | ||
625 | #define __NR_fspick (__NR_Linux + 433) | ||
626 | +#define __NR_pidfd_open (__NR_Linux + 434) | ||
627 | |||
628 | |||
629 | #endif /* _ASM_MIPS_UNISTD_N32_H */ | ||
630 | diff --git a/linux-headers/asm-mips/unistd_n64.h b/linux-headers/asm-mips/unistd_n64.h | ||
631 | index XXXXXXX..XXXXXXX 100644 | ||
632 | --- a/linux-headers/asm-mips/unistd_n64.h | ||
633 | +++ b/linux-headers/asm-mips/unistd_n64.h | ||
634 | @@ -XXX,XX +XXX,XX @@ | ||
635 | #define __NR_fsconfig (__NR_Linux + 431) | ||
636 | #define __NR_fsmount (__NR_Linux + 432) | ||
637 | #define __NR_fspick (__NR_Linux + 433) | ||
638 | +#define __NR_pidfd_open (__NR_Linux + 434) | ||
639 | |||
640 | |||
641 | #endif /* _ASM_MIPS_UNISTD_N64_H */ | ||
642 | diff --git a/linux-headers/asm-mips/unistd_o32.h b/linux-headers/asm-mips/unistd_o32.h | ||
643 | index XXXXXXX..XXXXXXX 100644 | ||
644 | --- a/linux-headers/asm-mips/unistd_o32.h | ||
645 | +++ b/linux-headers/asm-mips/unistd_o32.h | ||
646 | @@ -XXX,XX +XXX,XX @@ | ||
647 | #define __NR_fsconfig (__NR_Linux + 431) | ||
648 | #define __NR_fsmount (__NR_Linux + 432) | ||
649 | #define __NR_fspick (__NR_Linux + 433) | ||
650 | +#define __NR_pidfd_open (__NR_Linux + 434) | ||
651 | |||
652 | |||
653 | #endif /* _ASM_MIPS_UNISTD_O32_H */ | ||
654 | diff --git a/linux-headers/asm-powerpc/mman.h b/linux-headers/asm-powerpc/mman.h | ||
655 | index XXXXXXX..XXXXXXX 100644 | ||
656 | --- a/linux-headers/asm-powerpc/mman.h | ||
657 | +++ b/linux-headers/asm-powerpc/mman.h | ||
658 | @@ -XXX,XX +XXX,XX @@ | ||
659 | #define MAP_DENYWRITE 0x0800 /* ETXTBSY */ | ||
660 | #define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ | ||
661 | |||
662 | + | ||
663 | #define MCL_CURRENT 0x2000 /* lock all currently mapped pages */ | ||
664 | #define MCL_FUTURE 0x4000 /* lock all additions to address space */ | ||
665 | #define MCL_ONFAULT 0x8000 /* lock all pages that are faulted in */ | ||
666 | |||
667 | -#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ | ||
668 | -#define MAP_NONBLOCK 0x10000 /* do not block on IO */ | ||
669 | -#define MAP_STACK 0x20000 /* give out an address that is best suited for process/thread stacks */ | ||
670 | -#define MAP_HUGETLB 0x40000 /* create a huge page mapping */ | ||
671 | - | ||
672 | /* Override any generic PKEY permission defines */ | ||
673 | #define PKEY_DISABLE_EXECUTE 0x4 | ||
674 | #undef PKEY_ACCESS_MASK | ||
675 | diff --git a/linux-headers/asm-powerpc/unistd_32.h b/linux-headers/asm-powerpc/unistd_32.h | ||
676 | index XXXXXXX..XXXXXXX 100644 | ||
677 | --- a/linux-headers/asm-powerpc/unistd_32.h | ||
678 | +++ b/linux-headers/asm-powerpc/unistd_32.h | ||
679 | @@ -XXX,XX +XXX,XX @@ | ||
680 | #define __NR_fsconfig 431 | ||
681 | #define __NR_fsmount 432 | ||
682 | #define __NR_fspick 433 | ||
683 | +#define __NR_pidfd_open 434 | ||
684 | +#define __NR_clone3 435 | ||
685 | |||
686 | |||
687 | #endif /* _ASM_POWERPC_UNISTD_32_H */ | ||
688 | diff --git a/linux-headers/asm-powerpc/unistd_64.h b/linux-headers/asm-powerpc/unistd_64.h | ||
689 | index XXXXXXX..XXXXXXX 100644 | ||
690 | --- a/linux-headers/asm-powerpc/unistd_64.h | ||
691 | +++ b/linux-headers/asm-powerpc/unistd_64.h | ||
692 | @@ -XXX,XX +XXX,XX @@ | ||
693 | #define __NR_fsconfig 431 | ||
694 | #define __NR_fsmount 432 | ||
695 | #define __NR_fspick 433 | ||
696 | +#define __NR_pidfd_open 434 | ||
697 | +#define __NR_clone3 435 | ||
698 | |||
699 | |||
700 | #endif /* _ASM_POWERPC_UNISTD_64_H */ | ||
701 | diff --git a/linux-headers/asm-s390/kvm.h b/linux-headers/asm-s390/kvm.h | ||
702 | index XXXXXXX..XXXXXXX 100644 | ||
703 | --- a/linux-headers/asm-s390/kvm.h | ||
704 | +++ b/linux-headers/asm-s390/kvm.h | ||
705 | @@ -XXX,XX +XXX,XX @@ struct kvm_guest_debug_arch { | ||
706 | #define KVM_SYNC_GSCB (1UL << 9) | ||
707 | #define KVM_SYNC_BPBC (1UL << 10) | ||
708 | #define KVM_SYNC_ETOKEN (1UL << 11) | ||
709 | + | ||
710 | +#define KVM_SYNC_S390_VALID_FIELDS \ | ||
711 | + (KVM_SYNC_PREFIX | KVM_SYNC_GPRS | KVM_SYNC_ACRS | KVM_SYNC_CRS | \ | ||
712 | + KVM_SYNC_ARCH0 | KVM_SYNC_PFAULT | KVM_SYNC_VRS | KVM_SYNC_RICCB | \ | ||
713 | + KVM_SYNC_FPRS | KVM_SYNC_GSCB | KVM_SYNC_BPBC | KVM_SYNC_ETOKEN) | ||
714 | + | ||
715 | /* length and alignment of the sdnx as a power of two */ | ||
716 | #define SDNXC 8 | ||
717 | #define SDNXL (1UL << SDNXC) | ||
718 | diff --git a/linux-headers/asm-s390/unistd_32.h b/linux-headers/asm-s390/unistd_32.h | ||
719 | index XXXXXXX..XXXXXXX 100644 | ||
720 | --- a/linux-headers/asm-s390/unistd_32.h | ||
721 | +++ b/linux-headers/asm-s390/unistd_32.h | ||
722 | @@ -XXX,XX +XXX,XX @@ | ||
723 | #define __NR_fsconfig 431 | ||
724 | #define __NR_fsmount 432 | ||
725 | #define __NR_fspick 433 | ||
726 | +#define __NR_pidfd_open 434 | ||
727 | +#define __NR_clone3 435 | ||
728 | |||
729 | #endif /* _ASM_S390_UNISTD_32_H */ | ||
730 | diff --git a/linux-headers/asm-s390/unistd_64.h b/linux-headers/asm-s390/unistd_64.h | ||
731 | index XXXXXXX..XXXXXXX 100644 | ||
732 | --- a/linux-headers/asm-s390/unistd_64.h | ||
733 | +++ b/linux-headers/asm-s390/unistd_64.h | ||
734 | @@ -XXX,XX +XXX,XX @@ | ||
735 | #define __NR_fsconfig 431 | ||
736 | #define __NR_fsmount 432 | ||
737 | #define __NR_fspick 433 | ||
738 | +#define __NR_pidfd_open 434 | ||
739 | +#define __NR_clone3 435 | ||
740 | |||
741 | #endif /* _ASM_S390_UNISTD_64_H */ | ||
742 | diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h | ||
743 | index XXXXXXX..XXXXXXX 100644 | ||
744 | --- a/linux-headers/asm-x86/kvm.h | ||
745 | +++ b/linux-headers/asm-x86/kvm.h | ||
746 | @@ -XXX,XX +XXX,XX @@ struct kvm_sync_regs { | ||
747 | struct kvm_vcpu_events events; | ||
748 | }; | 87 | }; |
749 | 88 | ||
750 | -#define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0) | 89 | +static const uint32_t an524_oscclk[] = { |
751 | -#define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1) | 90 | + 24000000, |
752 | -#define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2) | 91 | + 32000000, |
753 | -#define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3) | 92 | + 50000000, |
754 | +#define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0) | 93 | + 50000000, |
755 | +#define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1) | 94 | + 24576000, |
756 | +#define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2) | 95 | + 23750000, |
757 | +#define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3) | 96 | +}; |
758 | +#define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT (1 << 4) | 97 | + |
759 | 98 | static const RAMInfo an505_raminfo[] = { { | |
760 | #define KVM_STATE_NESTED_FORMAT_VMX 0 | 99 | .name = "ssram-0", |
761 | -#define KVM_STATE_NESTED_FORMAT_SVM 1 | 100 | .base = 0x00000000, |
762 | +#define KVM_STATE_NESTED_FORMAT_SVM 1 /* unused */ | 101 | @@ -XXX,XX +XXX,XX @@ static const RAMInfo an505_raminfo[] = { { |
763 | 102 | }, | |
764 | #define KVM_STATE_NESTED_GUEST_MODE 0x00000001 | ||
765 | #define KVM_STATE_NESTED_RUN_PENDING 0x00000002 | ||
766 | #define KVM_STATE_NESTED_EVMCS 0x00000004 | ||
767 | |||
768 | -#define KVM_STATE_NESTED_VMX_VMCS_SIZE 0x1000 | ||
769 | - | ||
770 | #define KVM_STATE_NESTED_SMM_GUEST_MODE 0x00000001 | ||
771 | #define KVM_STATE_NESTED_SMM_VMXON 0x00000002 | ||
772 | |||
773 | +#define KVM_STATE_NESTED_VMX_VMCS_SIZE 0x1000 | ||
774 | + | ||
775 | struct kvm_vmx_nested_state_data { | ||
776 | __u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; | ||
777 | __u8 shadow_vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; | ||
778 | @@ -XXX,XX +XXX,XX @@ struct kvm_nested_state { | ||
779 | } data; | ||
780 | }; | 103 | }; |
781 | 104 | ||
782 | +/* for KVM_CAP_PMU_EVENT_FILTER */ | 105 | +static const RAMInfo an524_raminfo[] = { { |
783 | +struct kvm_pmu_event_filter { | 106 | + .name = "bram", |
784 | + __u32 action; | 107 | + .base = 0x00000000, |
785 | + __u32 nevents; | 108 | + .size = 512 * KiB, |
786 | + __u32 fixed_counter_bitmap; | 109 | + .mpc = 0, |
787 | + __u32 flags; | 110 | + .mrindex = 0, |
788 | + __u32 pad[4]; | 111 | + }, { |
789 | + __u64 events[0]; | 112 | + .name = "sram", |
113 | + .base = 0x20000000, | ||
114 | + .size = 32 * 4 * KiB, | ||
115 | + .mpc = 1, | ||
116 | + .mrindex = 1, | ||
117 | + }, { | ||
118 | + /* We don't model QSPI flash yet; for now expose it as simple ROM */ | ||
119 | + .name = "QSPI", | ||
120 | + .base = 0x28000000, | ||
121 | + .size = 8 * MiB, | ||
122 | + .mpc = 1, | ||
123 | + .mrindex = 2, | ||
124 | + .flags = IS_ROM, | ||
125 | + }, { | ||
126 | + .name = "DDR", | ||
127 | + .base = 0x60000000, | ||
128 | + .size = 2 * GiB, | ||
129 | + .mpc = 2, | ||
130 | + .mrindex = -1, | ||
131 | + }, { | ||
132 | + .name = NULL, | ||
133 | + }, | ||
790 | +}; | 134 | +}; |
791 | + | 135 | + |
792 | +#define KVM_PMU_EVENT_ALLOW 0 | 136 | static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc) |
793 | +#define KVM_PMU_EVENT_DENY 1 | 137 | { |
794 | + | 138 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
795 | #endif /* _ASM_X86_KVM_H */ | 139 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) |
796 | diff --git a/linux-headers/asm-x86/unistd.h b/linux-headers/asm-x86/unistd.h | 140 | }, |
797 | index XXXXXXX..XXXXXXX 100644 | 141 | }; |
798 | --- a/linux-headers/asm-x86/unistd.h | 142 | |
799 | +++ b/linux-headers/asm-x86/unistd.h | 143 | + const PPCInfo an524_ppcs[] = { { |
800 | @@ -XXX,XX +XXX,XX @@ | 144 | + .name = "apb_ppcexp0", |
801 | #define _ASM_X86_UNISTD_H | 145 | + .ports = { |
802 | 146 | + { "bram-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, | |
803 | /* x32 syscall flag bit */ | 147 | + { "qspi-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, |
804 | -#define __X32_SYSCALL_BIT 0x40000000 | 148 | + { "ddr-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, |
805 | +#define __X32_SYSCALL_BIT 0x40000000UL | 149 | + }, |
806 | 150 | + }, { | |
807 | # ifdef __i386__ | 151 | + .name = "apb_ppcexp1", |
808 | # include <asm/unistd_32.h> | 152 | + .ports = { |
809 | diff --git a/linux-headers/asm-x86/unistd_32.h b/linux-headers/asm-x86/unistd_32.h | 153 | + { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000 }, |
810 | index XXXXXXX..XXXXXXX 100644 | 154 | + { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000 }, |
811 | --- a/linux-headers/asm-x86/unistd_32.h | 155 | + { "spi0", make_spi, &mms->spi[0], 0x41202000, 0x1000, { 52 } }, |
812 | +++ b/linux-headers/asm-x86/unistd_32.h | 156 | + { "spi1", make_spi, &mms->spi[1], 0x41203000, 0x1000, { 53 } }, |
813 | @@ -XXX,XX +XXX,XX @@ | 157 | + { "spi2", make_spi, &mms->spi[2], 0x41204000, 0x1000, { 54 } }, |
814 | #define __NR_fsconfig 431 | 158 | + { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000 }, |
815 | #define __NR_fsmount 432 | 159 | + { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000 }, |
816 | #define __NR_fspick 433 | 160 | + { /* port 7 reserved */ }, |
817 | +#define __NR_pidfd_open 434 | 161 | + { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000 }, |
818 | +#define __NR_clone3 435 | 162 | + }, |
819 | 163 | + }, { | |
820 | #endif /* _ASM_X86_UNISTD_32_H */ | 164 | + .name = "apb_ppcexp2", |
821 | diff --git a/linux-headers/asm-x86/unistd_64.h b/linux-headers/asm-x86/unistd_64.h | 165 | + .ports = { |
822 | index XXXXXXX..XXXXXXX 100644 | 166 | + { "scc", make_scc, &mms->scc, 0x41300000, 0x1000 }, |
823 | --- a/linux-headers/asm-x86/unistd_64.h | 167 | + { "i2s-audio", make_unimp_dev, &mms->i2s_audio, |
824 | +++ b/linux-headers/asm-x86/unistd_64.h | 168 | + 0x41301000, 0x1000 }, |
825 | @@ -XXX,XX +XXX,XX @@ | 169 | + { "fpgaio", make_fpgaio, &mms->fpgaio, 0x41302000, 0x1000 }, |
826 | #define __NR_fsconfig 431 | 170 | + { "uart0", make_uart, &mms->uart[0], 0x41303000, 0x1000, { 32, 33, 42 } }, |
827 | #define __NR_fsmount 432 | 171 | + { "uart1", make_uart, &mms->uart[1], 0x41304000, 0x1000, { 34, 35, 43 } }, |
828 | #define __NR_fspick 433 | 172 | + { "uart2", make_uart, &mms->uart[2], 0x41305000, 0x1000, { 36, 37, 44 } }, |
829 | +#define __NR_pidfd_open 434 | 173 | + { "uart3", make_uart, &mms->uart[3], 0x41306000, 0x1000, { 38, 39, 45 } }, |
830 | +#define __NR_clone3 435 | 174 | + { "uart4", make_uart, &mms->uart[4], 0x41307000, 0x1000, { 40, 41, 46 } }, |
831 | 175 | + { "uart5", make_uart, &mms->uart[5], 0x41308000, 0x1000, { 124, 125, 126 } }, | |
832 | #endif /* _ASM_X86_UNISTD_64_H */ | 176 | + |
833 | diff --git a/linux-headers/asm-x86/unistd_x32.h b/linux-headers/asm-x86/unistd_x32.h | 177 | + { /* port 9 reserved */ }, |
834 | index XXXXXXX..XXXXXXX 100644 | 178 | + { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, |
835 | --- a/linux-headers/asm-x86/unistd_x32.h | 179 | + { "rtc", make_unimp_dev, &mms->rtc, 0x4130b000, 0x1000 }, |
836 | +++ b/linux-headers/asm-x86/unistd_x32.h | 180 | + }, |
837 | @@ -XXX,XX +XXX,XX @@ | 181 | + }, { |
838 | #define __NR_fsconfig (__X32_SYSCALL_BIT + 431) | 182 | + .name = "ahb_ppcexp0", |
839 | #define __NR_fsmount (__X32_SYSCALL_BIT + 432) | 183 | + .ports = { |
840 | #define __NR_fspick (__X32_SYSCALL_BIT + 433) | 184 | + { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 }, |
841 | +#define __NR_pidfd_open (__X32_SYSCALL_BIT + 434) | 185 | + { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, |
842 | +#define __NR_clone3 (__X32_SYSCALL_BIT + 435) | 186 | + { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, |
843 | #define __NR_rt_sigaction (__X32_SYSCALL_BIT + 512) | 187 | + { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, |
844 | #define __NR_rt_sigreturn (__X32_SYSCALL_BIT + 513) | 188 | + { "eth", make_eth_dev, NULL, 0x41400000, 0x100000, { 48 } }, |
845 | #define __NR_ioctl (__X32_SYSCALL_BIT + 514) | 189 | + }, |
846 | diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h | 190 | + }, |
847 | index XXXXXXX..XXXXXXX 100644 | 191 | + }; |
848 | --- a/linux-headers/linux/kvm.h | 192 | + |
849 | +++ b/linux-headers/linux/kvm.h | 193 | switch (mmc->fpga_type) { |
850 | @@ -XXX,XX +XXX,XX @@ struct kvm_irq_level { | 194 | case FPGA_AN505: |
851 | * ACPI gsi notion of irq. | 195 | case FPGA_AN521: |
852 | * For IA-64 (APIC model) IOAPIC0: irq 0-23; IOAPIC1: irq 24-47.. | 196 | ppcs = an505_ppcs; |
853 | * For X86 (standard AT mode) PIC0/1: irq 0-15. IOAPIC0: 0-23.. | 197 | num_ppcs = ARRAY_SIZE(an505_ppcs); |
854 | - * For ARM: See Documentation/virtual/kvm/api.txt | 198 | break; |
855 | + * For ARM: See Documentation/virt/kvm/api.txt | 199 | + case FPGA_AN524: |
856 | */ | 200 | + ppcs = an524_ppcs; |
857 | union { | 201 | + num_ppcs = ARRAY_SIZE(an524_ppcs); |
858 | __u32 irq; | 202 | + break; |
859 | @@ -XXX,XX +XXX,XX @@ struct kvm_hyperv_exit { | 203 | default: |
860 | #define KVM_INTERNAL_ERROR_SIMUL_EX 2 | 204 | g_assert_not_reached(); |
861 | /* Encounter unexpected vm-exit due to delivery event. */ | 205 | } |
862 | #define KVM_INTERNAL_ERROR_DELIVERY_EV 3 | 206 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) |
863 | +/* Encounter unexpected vm-exit reason */ | 207 | mps2tz_set_default_ram_info(mmc); |
864 | +#define KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON 4 | 208 | } |
865 | 209 | ||
866 | /* for KVM_RUN, returned by mmap(vcpu_fd, offset=0) */ | 210 | +static void mps3tz_an524_class_init(ObjectClass *oc, void *data) |
867 | struct kvm_run { | 211 | +{ |
868 | @@ -XXX,XX +XXX,XX @@ struct kvm_ppc_resize_hpt { | 212 | + MachineClass *mc = MACHINE_CLASS(oc); |
869 | #define KVM_CAP_ARM_SVE 170 | 213 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); |
870 | #define KVM_CAP_ARM_PTRAUTH_ADDRESS 171 | 214 | + |
871 | #define KVM_CAP_ARM_PTRAUTH_GENERIC 172 | 215 | + mc->desc = "ARM MPS3 with AN524 FPGA image for dual Cortex-M33"; |
872 | +#define KVM_CAP_PMU_EVENT_FILTER 173 | 216 | + mc->default_cpus = 2; |
873 | +#define KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 174 | 217 | + mc->min_cpus = mc->default_cpus; |
874 | +#define KVM_CAP_HYPERV_DIRECT_TLBFLUSH 175 | 218 | + mc->max_cpus = mc->default_cpus; |
875 | 219 | + mmc->fpga_type = FPGA_AN524; | |
876 | #ifdef KVM_CAP_IRQ_ROUTING | 220 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); |
877 | 221 | + mmc->scc_id = 0x41045240; | |
878 | @@ -XXX,XX +XXX,XX @@ struct kvm_xen_hvm_config { | 222 | + mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ |
879 | * | 223 | + mmc->oscclk = an524_oscclk; |
880 | * KVM_IRQFD_FLAG_RESAMPLE indicates resamplefd is valid and specifies | 224 | + mmc->len_oscclk = ARRAY_SIZE(an524_oscclk); |
881 | * the irqfd to operate in resampling mode for level triggered interrupt | 225 | + mmc->fpgaio_num_leds = 10; |
882 | - * emulation. See Documentation/virtual/kvm/api.txt. | 226 | + mmc->fpgaio_has_switches = true; |
883 | + * emulation. See Documentation/virt/kvm/api.txt. | 227 | + mmc->numirq = 95; |
884 | */ | 228 | + mmc->raminfo = an524_raminfo; |
885 | #define KVM_IRQFD_FLAG_RESAMPLE (1 << 1) | 229 | + mmc->armsse_type = TYPE_SSE200; |
886 | 230 | + mps2tz_set_default_ram_info(mmc); | |
887 | @@ -XXX,XX +XXX,XX @@ struct kvm_dirty_tlb { | 231 | +} |
888 | #define KVM_REG_S390 0x5000000000000000ULL | 232 | + |
889 | #define KVM_REG_ARM64 0x6000000000000000ULL | 233 | static const TypeInfo mps2tz_info = { |
890 | #define KVM_REG_MIPS 0x7000000000000000ULL | 234 | .name = TYPE_MPS2TZ_MACHINE, |
891 | +#define KVM_REG_RISCV 0x8000000000000000ULL | 235 | .parent = TYPE_MACHINE, |
892 | 236 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo mps2tz_an521_info = { | |
893 | #define KVM_REG_SIZE_SHIFT 52 | 237 | .class_init = mps2tz_an521_class_init, |
894 | #define KVM_REG_SIZE_MASK 0x00f0000000000000ULL | ||
895 | @@ -XXX,XX +XXX,XX @@ struct kvm_s390_ucas_mapping { | ||
896 | #define KVM_PPC_GET_RMMU_INFO _IOW(KVMIO, 0xb0, struct kvm_ppc_rmmu_info) | ||
897 | /* Available with KVM_CAP_PPC_GET_CPU_CHAR */ | ||
898 | #define KVM_PPC_GET_CPU_CHAR _IOR(KVMIO, 0xb1, struct kvm_ppc_cpu_char) | ||
899 | +/* Available with KVM_CAP_PMU_EVENT_FILTER */ | ||
900 | +#define KVM_SET_PMU_EVENT_FILTER _IOW(KVMIO, 0xb2, struct kvm_pmu_event_filter) | ||
901 | |||
902 | /* ioctl for vm fd */ | ||
903 | #define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device) | ||
904 | diff --git a/linux-headers/linux/psp-sev.h b/linux-headers/linux/psp-sev.h | ||
905 | index XXXXXXX..XXXXXXX 100644 | ||
906 | --- a/linux-headers/linux/psp-sev.h | ||
907 | +++ b/linux-headers/linux/psp-sev.h | ||
908 | @@ -XXX,XX +XXX,XX @@ | ||
909 | +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ | ||
910 | /* | ||
911 | * Userspace interface for AMD Secure Encrypted Virtualization (SEV) | ||
912 | * platform management commands. | ||
913 | @@ -XXX,XX +XXX,XX @@ | ||
914 | * Author: Brijesh Singh <brijesh.singh@amd.com> | ||
915 | * | ||
916 | * SEV API specification is available at: https://developer.amd.com/sev/ | ||
917 | - * | ||
918 | - * This program is free software; you can redistribute it and/or modify | ||
919 | - * it under the terms of the GNU General Public License version 2 as | ||
920 | - * published by the Free Software Foundation. | ||
921 | */ | ||
922 | |||
923 | #ifndef __PSP_SEV_USER_H__ | ||
924 | diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h | ||
925 | index XXXXXXX..XXXXXXX 100644 | ||
926 | --- a/linux-headers/linux/vfio.h | ||
927 | +++ b/linux-headers/linux/vfio.h | ||
928 | @@ -XXX,XX +XXX,XX @@ struct vfio_region_info_cap_type { | ||
929 | __u32 subtype; /* type specific */ | ||
930 | }; | 238 | }; |
931 | 239 | ||
932 | +/* | 240 | +static const TypeInfo mps3tz_an524_info = { |
933 | + * List of region types, global per bus driver. | 241 | + .name = TYPE_MPS3TZ_AN524_MACHINE, |
934 | + * If you introduce a new type, please add it here. | 242 | + .parent = TYPE_MPS2TZ_MACHINE, |
935 | + */ | 243 | + .class_init = mps3tz_an524_class_init, |
936 | + | ||
937 | +/* PCI region type containing a PCI vendor part */ | ||
938 | #define VFIO_REGION_TYPE_PCI_VENDOR_TYPE (1 << 31) | ||
939 | #define VFIO_REGION_TYPE_PCI_VENDOR_MASK (0xffff) | ||
940 | +#define VFIO_REGION_TYPE_GFX (1) | ||
941 | +#define VFIO_REGION_TYPE_CCW (2) | ||
942 | |||
943 | -/* 8086 Vendor sub-types */ | ||
944 | +/* sub-types for VFIO_REGION_TYPE_PCI_* */ | ||
945 | + | ||
946 | +/* 8086 vendor PCI sub-types */ | ||
947 | #define VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION (1) | ||
948 | #define VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG (2) | ||
949 | #define VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG (3) | ||
950 | |||
951 | -#define VFIO_REGION_TYPE_GFX (1) | ||
952 | +/* 10de vendor PCI sub-types */ | ||
953 | +/* | ||
954 | + * NVIDIA GPU NVlink2 RAM is coherent RAM mapped onto the host address space. | ||
955 | + */ | ||
956 | +#define VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM (1) | ||
957 | + | ||
958 | +/* 1014 vendor PCI sub-types */ | ||
959 | +/* | ||
960 | + * IBM NPU NVlink2 ATSD (Address Translation Shootdown) register of NPU | ||
961 | + * to do TLB invalidation on a GPU. | ||
962 | + */ | ||
963 | +#define VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD (1) | ||
964 | + | ||
965 | +/* sub-types for VFIO_REGION_TYPE_GFX */ | ||
966 | #define VFIO_REGION_SUBTYPE_GFX_EDID (1) | ||
967 | |||
968 | /** | ||
969 | @@ -XXX,XX +XXX,XX @@ struct vfio_region_gfx_edid { | ||
970 | #define VFIO_DEVICE_GFX_LINK_STATE_DOWN 2 | ||
971 | }; | ||
972 | |||
973 | -#define VFIO_REGION_TYPE_CCW (2) | ||
974 | -/* ccw sub-types */ | ||
975 | +/* sub-types for VFIO_REGION_TYPE_CCW */ | ||
976 | #define VFIO_REGION_SUBTYPE_CCW_ASYNC_CMD (1) | ||
977 | |||
978 | -/* | ||
979 | - * 10de vendor sub-type | ||
980 | - * | ||
981 | - * NVIDIA GPU NVlink2 RAM is coherent RAM mapped onto the host address space. | ||
982 | - */ | ||
983 | -#define VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM (1) | ||
984 | - | ||
985 | -/* | ||
986 | - * 1014 vendor sub-type | ||
987 | - * | ||
988 | - * IBM NPU NVlink2 ATSD (Address Translation Shootdown) register of NPU | ||
989 | - * to do TLB invalidation on a GPU. | ||
990 | - */ | ||
991 | -#define VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD (1) | ||
992 | - | ||
993 | /* | ||
994 | * The MSIX mappable capability informs that MSIX data of a BAR can be mmapped | ||
995 | * which allows direct access to non-MSIX registers which happened to be within | ||
996 | @@ -XXX,XX +XXX,XX @@ struct vfio_iommu_type1_info { | ||
997 | __u32 argsz; | ||
998 | __u32 flags; | ||
999 | #define VFIO_IOMMU_INFO_PGSIZES (1 << 0) /* supported page sizes info */ | ||
1000 | - __u64 iova_pgsizes; /* Bitmap of supported page sizes */ | ||
1001 | +#define VFIO_IOMMU_INFO_CAPS (1 << 1) /* Info supports caps */ | ||
1002 | + __u64 iova_pgsizes; /* Bitmap of supported page sizes */ | ||
1003 | + __u32 cap_offset; /* Offset within info struct of first cap */ | ||
1004 | +}; | 244 | +}; |
1005 | + | 245 | + |
1006 | +/* | 246 | static void mps2tz_machine_init(void) |
1007 | + * The IOVA capability allows to report the valid IOVA range(s) | 247 | { |
1008 | + * excluding any non-relaxable reserved regions exposed by | 248 | type_register_static(&mps2tz_info); |
1009 | + * devices attached to the container. Any DMA map attempt | 249 | type_register_static(&mps2tz_an505_info); |
1010 | + * outside the valid iova range will return error. | 250 | type_register_static(&mps2tz_an521_info); |
1011 | + * | 251 | + type_register_static(&mps3tz_an524_info); |
1012 | + * The structures below define version 1 of this capability. | 252 | } |
1013 | + */ | 253 | |
1014 | +#define VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE 1 | 254 | type_init(mps2tz_machine_init); |
1015 | + | ||
1016 | +struct vfio_iova_range { | ||
1017 | + __u64 start; | ||
1018 | + __u64 end; | ||
1019 | +}; | ||
1020 | + | ||
1021 | +struct vfio_iommu_type1_info_cap_iova_range { | ||
1022 | + struct vfio_info_cap_header header; | ||
1023 | + __u32 nr_iovas; | ||
1024 | + __u32 reserved; | ||
1025 | + struct vfio_iova_range iova_ranges[]; | ||
1026 | }; | ||
1027 | |||
1028 | #define VFIO_IOMMU_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12) | ||
1029 | -- | 255 | -- |
1030 | 2.20.1 | 256 | 2.20.1 |
1031 | 257 | ||
1032 | 258 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Eric Auger <eric.auger@redhat.com> | ||
2 | 1 | ||
3 | Host kernel within [4.18, 5.3] report an erroneous KVM_MAX_VCPUS=512 | ||
4 | for ARM. The actual capability to instantiate more than 256 vcpus | ||
5 | was fixed in 5.4 with the upgrade of the KVM_IRQ_LINE ABI to support | ||
6 | vcpu id encoded on 12 bits instead of 8 and a redistributor consuming | ||
7 | a single KVM IO device instead of 2. | ||
8 | |||
9 | So let's check this capability when attempting to use more than 256 | ||
10 | vcpus within any ARM kvm accelerated machine. | ||
11 | |||
12 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Reviewed-by: Andrew Jones <drjones@redhat.com> | ||
15 | Acked-by: Marc Zyngier <maz@kernel.org> | ||
16 | Message-id: 20191003154640.22451-4-eric.auger@redhat.com | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | --- | ||
19 | target/arm/kvm.c | 10 +++++++++- | ||
20 | 1 file changed, 9 insertions(+), 1 deletion(-) | ||
21 | |||
22 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/target/arm/kvm.c | ||
25 | +++ b/target/arm/kvm.c | ||
26 | @@ -XXX,XX +XXX,XX @@ int kvm_arm_get_max_vm_ipa_size(MachineState *ms) | ||
27 | |||
28 | int kvm_arch_init(MachineState *ms, KVMState *s) | ||
29 | { | ||
30 | + int ret = 0; | ||
31 | /* For ARM interrupt delivery is always asynchronous, | ||
32 | * whether we are using an in-kernel VGIC or not. | ||
33 | */ | ||
34 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s) | ||
35 | |||
36 | cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); | ||
37 | |||
38 | - return 0; | ||
39 | + if (ms->smp.cpus > 256 && | ||
40 | + !kvm_check_extension(s, KVM_CAP_ARM_IRQ_LINE_LAYOUT_2)) { | ||
41 | + error_report("Using more than 256 vcpus requires a host kernel " | ||
42 | + "with KVM_CAP_ARM_IRQ_LINE_LAYOUT_2"); | ||
43 | + ret = -EINVAL; | ||
44 | + } | ||
45 | + | ||
46 | + return ret; | ||
47 | } | ||
48 | |||
49 | unsigned long kvm_arch_vcpu_id(CPUState *cpu) | ||
50 | -- | ||
51 | 2.20.1 | ||
52 | |||
53 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Switch the ltick ptimer over to the ptimer transaction API. | ||
2 | 1 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20191008171740.9679-14-peter.maydell@linaro.org | ||
6 | --- | ||
7 | hw/timer/exynos4210_mct.c | 31 +++++++++++++++++++++++++------ | ||
8 | 1 file changed, 25 insertions(+), 6 deletions(-) | ||
9 | |||
10 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/hw/timer/exynos4210_mct.c | ||
13 | +++ b/hw/timer/exynos4210_mct.c | ||
14 | @@ -XXX,XX +XXX,XX @@ | ||
15 | #include "hw/sysbus.h" | ||
16 | #include "migration/vmstate.h" | ||
17 | #include "qemu/timer.h" | ||
18 | -#include "qemu/main-loop.h" | ||
19 | #include "qemu/module.h" | ||
20 | #include "hw/ptimer.h" | ||
21 | |||
22 | @@ -XXX,XX +XXX,XX @@ static uint32_t exynos4210_ltick_int_get_cnto(struct tick_timer *s) | ||
23 | |||
24 | /* | ||
25 | * Start local tick cnt timer. | ||
26 | + * Must be called within exynos4210_ltick_tx_begin/commit block. | ||
27 | */ | ||
28 | static void exynos4210_ltick_cnt_start(struct tick_timer *s) | ||
29 | { | ||
30 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_ltick_cnt_start(struct tick_timer *s) | ||
31 | |||
32 | /* | ||
33 | * Stop local tick cnt timer. | ||
34 | + * Must be called within exynos4210_ltick_tx_begin/commit block. | ||
35 | */ | ||
36 | static void exynos4210_ltick_cnt_stop(struct tick_timer *s) | ||
37 | { | ||
38 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_ltick_cnt_stop(struct tick_timer *s) | ||
39 | } | ||
40 | } | ||
41 | |||
42 | +/* Start ptimer transaction for local tick timer */ | ||
43 | +static void exynos4210_ltick_tx_begin(struct tick_timer *s) | ||
44 | +{ | ||
45 | + ptimer_transaction_begin(s->ptimer_tick); | ||
46 | +} | ||
47 | + | ||
48 | +/* Commit ptimer transaction for local tick timer */ | ||
49 | +static void exynos4210_ltick_tx_commit(struct tick_timer *s) | ||
50 | +{ | ||
51 | + ptimer_transaction_commit(s->ptimer_tick); | ||
52 | +} | ||
53 | + | ||
54 | /* | ||
55 | * Get counter for CNT timer | ||
56 | */ | ||
57 | @@ -XXX,XX +XXX,XX @@ static uint32_t exynos4210_ltick_cnt_get_cnto(struct tick_timer *s) | ||
58 | |||
59 | /* | ||
60 | * Set new values of counters for CNT and INT timers | ||
61 | + * Must be called within exynos4210_ltick_tx_begin/commit block. | ||
62 | */ | ||
63 | static void exynos4210_ltick_set_cntb(struct tick_timer *s, uint32_t new_cnt, | ||
64 | uint32_t new_int) | ||
65 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_ltick_recalc_count(struct tick_timer *s) | ||
66 | static void exynos4210_ltick_timer_init(struct tick_timer *s) | ||
67 | { | ||
68 | exynos4210_ltick_int_stop(s); | ||
69 | + exynos4210_ltick_tx_begin(s); | ||
70 | exynos4210_ltick_cnt_stop(s); | ||
71 | + exynos4210_ltick_tx_commit(s); | ||
72 | |||
73 | s->count = 0; | ||
74 | s->distance = 0; | ||
75 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s) | ||
76 | tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq); | ||
77 | |||
78 | /* local timer */ | ||
79 | - ptimer_set_freq(s->l_timer[0].tick_timer.ptimer_tick, s->freq); | ||
80 | + tx_ptimer_set_freq(s->l_timer[0].tick_timer.ptimer_tick, s->freq); | ||
81 | tx_ptimer_set_freq(s->l_timer[0].ptimer_frc, s->freq); | ||
82 | - ptimer_set_freq(s->l_timer[1].tick_timer.ptimer_tick, s->freq); | ||
83 | + tx_ptimer_set_freq(s->l_timer[1].tick_timer.ptimer_tick, s->freq); | ||
84 | tx_ptimer_set_freq(s->l_timer[1].ptimer_frc, s->freq); | ||
85 | } | ||
86 | } | ||
87 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
88 | s->l_timer[lt_i].reg.wstat |= L_WSTAT_TCON_WRITE; | ||
89 | s->l_timer[lt_i].reg.tcon = value; | ||
90 | |||
91 | + exynos4210_ltick_tx_begin(&s->l_timer[lt_i].tick_timer); | ||
92 | /* Stop local CNT */ | ||
93 | if ((value & L_TCON_TICK_START) < | ||
94 | (old_val & L_TCON_TICK_START)) { | ||
95 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
96 | DPRINTF("local timer[%d] start int\n", lt_i); | ||
97 | exynos4210_ltick_int_start(&s->l_timer[lt_i].tick_timer); | ||
98 | } | ||
99 | + exynos4210_ltick_tx_commit(&s->l_timer[lt_i].tick_timer); | ||
100 | |||
101 | /* Start or Stop local FRC if TCON changed */ | ||
102 | exynos4210_lfrc_tx_begin(&s->l_timer[lt_i]); | ||
103 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
104 | * Due to this we should reload timer to nearest moment when CNT is | ||
105 | * expired and then in event handler update tcntb to new TCNTB value. | ||
106 | */ | ||
107 | + exynos4210_ltick_tx_begin(&s->l_timer[lt_i].tick_timer); | ||
108 | exynos4210_ltick_set_cntb(&s->l_timer[lt_i].tick_timer, value, | ||
109 | s->l_timer[lt_i].tick_timer.icntb); | ||
110 | + exynos4210_ltick_tx_commit(&s->l_timer[lt_i].tick_timer); | ||
111 | |||
112 | s->l_timer[lt_i].reg.wstat |= L_WSTAT_TCNTB_WRITE; | ||
113 | s->l_timer[lt_i].reg.cnt[L_REG_CNT_TCNTB] = value; | ||
114 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_init(Object *obj) | ||
115 | int i; | ||
116 | Exynos4210MCTState *s = EXYNOS4210_MCT(obj); | ||
117 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | ||
118 | - QEMUBH *bh[2]; | ||
119 | |||
120 | /* Global timer */ | ||
121 | s->g_timer.ptimer_frc = ptimer_init(exynos4210_gfrc_event, s, | ||
122 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_init(Object *obj) | ||
123 | |||
124 | /* Local timers */ | ||
125 | for (i = 0; i < 2; i++) { | ||
126 | - bh[0] = qemu_bh_new(exynos4210_ltick_event, &s->l_timer[i]); | ||
127 | s->l_timer[i].tick_timer.ptimer_tick = | ||
128 | - ptimer_init_with_bh(bh[0], PTIMER_POLICY_DEFAULT); | ||
129 | + ptimer_init(exynos4210_ltick_event, &s->l_timer[i], | ||
130 | + PTIMER_POLICY_DEFAULT); | ||
131 | s->l_timer[i].ptimer_frc = | ||
132 | ptimer_init(exynos4210_lfrc_event, &s->l_timer[i], | ||
133 | PTIMER_POLICY_DEFAULT); | ||
134 | -- | ||
135 | 2.20.1 | ||
136 | |||
137 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Switch the exynos4210_pwm code away from bottom-half based ptimers to | ||
2 | the new transaction-based ptimer API. This just requires adding | ||
3 | begin/commit calls around the various places that modify the ptimer | ||
4 | state, and using the new ptimer_init() function to create the timer. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20191008171740.9679-15-peter.maydell@linaro.org | ||
9 | --- | ||
10 | hw/timer/exynos4210_pwm.c | 17 ++++++++++++----- | ||
11 | 1 file changed, 12 insertions(+), 5 deletions(-) | ||
12 | |||
13 | diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/hw/timer/exynos4210_pwm.c | ||
16 | +++ b/hw/timer/exynos4210_pwm.c | ||
17 | @@ -XXX,XX +XXX,XX @@ | ||
18 | #include "hw/sysbus.h" | ||
19 | #include "migration/vmstate.h" | ||
20 | #include "qemu/timer.h" | ||
21 | -#include "qemu/main-loop.h" | ||
22 | #include "qemu/module.h" | ||
23 | #include "hw/ptimer.h" | ||
24 | |||
25 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_exynos4210_pwm_state = { | ||
26 | }; | ||
27 | |||
28 | /* | ||
29 | - * PWM update frequency | ||
30 | + * PWM update frequency. | ||
31 | + * Must be called within a ptimer_transaction_begin/commit block | ||
32 | + * for s->timer[id].ptimer. | ||
33 | */ | ||
34 | static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id) | ||
35 | { | ||
36 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_write(void *opaque, hwaddr offset, | ||
37 | |||
38 | /* update timers frequencies */ | ||
39 | for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { | ||
40 | + ptimer_transaction_begin(s->timer[i].ptimer); | ||
41 | exynos4210_pwm_update_freq(s, s->timer[i].id); | ||
42 | + ptimer_transaction_commit(s->timer[i].ptimer); | ||
43 | } | ||
44 | break; | ||
45 | |||
46 | case TCON: | ||
47 | for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { | ||
48 | + ptimer_transaction_begin(s->timer[i].ptimer); | ||
49 | if ((value & TCON_TIMER_MANUAL_UPD(i)) > | ||
50 | (s->reg_tcon & TCON_TIMER_MANUAL_UPD(i))) { | ||
51 | /* | ||
52 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_write(void *opaque, hwaddr offset, | ||
53 | ptimer_stop(s->timer[i].ptimer); | ||
54 | DPRINTF("stop timer %d\n", i); | ||
55 | } | ||
56 | + ptimer_transaction_commit(s->timer[i].ptimer); | ||
57 | } | ||
58 | s->reg_tcon = value; | ||
59 | break; | ||
60 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_reset(DeviceState *d) | ||
61 | s->timer[i].reg_tcmpb = 0; | ||
62 | s->timer[i].reg_tcntb = 0; | ||
63 | |||
64 | + ptimer_transaction_begin(s->timer[i].ptimer); | ||
65 | exynos4210_pwm_update_freq(s, s->timer[i].id); | ||
66 | ptimer_stop(s->timer[i].ptimer); | ||
67 | + ptimer_transaction_commit(s->timer[i].ptimer); | ||
68 | } | ||
69 | } | ||
70 | |||
71 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_init(Object *obj) | ||
72 | Exynos4210PWMState *s = EXYNOS4210_PWM(obj); | ||
73 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | ||
74 | int i; | ||
75 | - QEMUBH *bh; | ||
76 | |||
77 | for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { | ||
78 | - bh = qemu_bh_new(exynos4210_pwm_tick, &s->timer[i]); | ||
79 | sysbus_init_irq(dev, &s->timer[i].irq); | ||
80 | - s->timer[i].ptimer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
81 | + s->timer[i].ptimer = ptimer_init(exynos4210_pwm_tick, | ||
82 | + &s->timer[i], | ||
83 | + PTIMER_POLICY_DEFAULT); | ||
84 | s->timer[i].id = i; | ||
85 | s->timer[i].parent = s; | ||
86 | } | ||
87 | -- | ||
88 | 2.20.1 | ||
89 | |||
90 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Switch the exynos41210_rtc 1Hz ptimer over to the transaction-based | ||
2 | API. (We will switch the other ptimer used by this device in a | ||
3 | separate commit.) | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20191008171740.9679-16-peter.maydell@linaro.org | ||
8 | --- | ||
9 | hw/timer/exynos4210_rtc.c | 10 ++++++++-- | ||
10 | 1 file changed, 8 insertions(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/hw/timer/exynos4210_rtc.c b/hw/timer/exynos4210_rtc.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/hw/timer/exynos4210_rtc.c | ||
15 | +++ b/hw/timer/exynos4210_rtc.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset, | ||
17 | } | ||
18 | break; | ||
19 | case RTCCON: | ||
20 | + ptimer_transaction_begin(s->ptimer_1Hz); | ||
21 | if (value & RTC_ENABLE) { | ||
22 | exynos4210_rtc_update_freq(s, value); | ||
23 | } | ||
24 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset, | ||
25 | ptimer_stop(s->ptimer); | ||
26 | } | ||
27 | } | ||
28 | + ptimer_transaction_commit(s->ptimer_1Hz); | ||
29 | s->reg_rtccon = value; | ||
30 | break; | ||
31 | case TICCNT: | ||
32 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_reset(DeviceState *d) | ||
33 | |||
34 | exynos4210_rtc_update_freq(s, s->reg_rtccon); | ||
35 | ptimer_stop(s->ptimer); | ||
36 | + ptimer_transaction_begin(s->ptimer_1Hz); | ||
37 | ptimer_stop(s->ptimer_1Hz); | ||
38 | + ptimer_transaction_commit(s->ptimer_1Hz); | ||
39 | } | ||
40 | |||
41 | static const MemoryRegionOps exynos4210_rtc_ops = { | ||
42 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_init(Object *obj) | ||
43 | ptimer_set_freq(s->ptimer, RTC_BASE_FREQ); | ||
44 | exynos4210_rtc_update_freq(s, 0); | ||
45 | |||
46 | - bh = qemu_bh_new(exynos4210_rtc_1Hz_tick, s); | ||
47 | - s->ptimer_1Hz = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
48 | + s->ptimer_1Hz = ptimer_init(exynos4210_rtc_1Hz_tick, | ||
49 | + s, PTIMER_POLICY_DEFAULT); | ||
50 | + ptimer_transaction_begin(s->ptimer_1Hz); | ||
51 | ptimer_set_freq(s->ptimer_1Hz, RTC_BASE_FREQ); | ||
52 | + ptimer_transaction_commit(s->ptimer_1Hz); | ||
53 | |||
54 | sysbus_init_irq(dev, &s->alm_irq); | ||
55 | sysbus_init_irq(dev, &s->tick_irq); | ||
56 | -- | ||
57 | 2.20.1 | ||
58 | |||
59 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Switch the exynos41210_rtc main ptimer over to the transaction-based | ||
2 | API, completing the transition for this device. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20191008171740.9679-17-peter.maydell@linaro.org | ||
7 | --- | ||
8 | hw/timer/exynos4210_rtc.c | 12 ++++++++---- | ||
9 | 1 file changed, 8 insertions(+), 4 deletions(-) | ||
10 | |||
11 | diff --git a/hw/timer/exynos4210_rtc.c b/hw/timer/exynos4210_rtc.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/hw/timer/exynos4210_rtc.c | ||
14 | +++ b/hw/timer/exynos4210_rtc.c | ||
15 | @@ -XXX,XX +XXX,XX @@ | ||
16 | #include "qemu/osdep.h" | ||
17 | #include "qemu-common.h" | ||
18 | #include "qemu/log.h" | ||
19 | -#include "qemu/main-loop.h" | ||
20 | #include "qemu/module.h" | ||
21 | #include "hw/sysbus.h" | ||
22 | #include "migration/vmstate.h" | ||
23 | @@ -XXX,XX +XXX,XX @@ static void check_alarm_raise(Exynos4210RTCState *s) | ||
24 | * RTC update frequency | ||
25 | * Parameters: | ||
26 | * reg_value - current RTCCON register or his new value | ||
27 | + * Must be called within a ptimer_transaction_begin/commit block for s->ptimer. | ||
28 | */ | ||
29 | static void exynos4210_rtc_update_freq(Exynos4210RTCState *s, | ||
30 | uint32_t reg_value) | ||
31 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset, | ||
32 | break; | ||
33 | case RTCCON: | ||
34 | ptimer_transaction_begin(s->ptimer_1Hz); | ||
35 | + ptimer_transaction_begin(s->ptimer); | ||
36 | if (value & RTC_ENABLE) { | ||
37 | exynos4210_rtc_update_freq(s, value); | ||
38 | } | ||
39 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset, | ||
40 | } | ||
41 | } | ||
42 | ptimer_transaction_commit(s->ptimer_1Hz); | ||
43 | + ptimer_transaction_commit(s->ptimer); | ||
44 | s->reg_rtccon = value; | ||
45 | break; | ||
46 | case TICCNT: | ||
47 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_reset(DeviceState *d) | ||
48 | |||
49 | s->reg_curticcnt = 0; | ||
50 | |||
51 | + ptimer_transaction_begin(s->ptimer); | ||
52 | exynos4210_rtc_update_freq(s, s->reg_rtccon); | ||
53 | ptimer_stop(s->ptimer); | ||
54 | + ptimer_transaction_commit(s->ptimer); | ||
55 | ptimer_transaction_begin(s->ptimer_1Hz); | ||
56 | ptimer_stop(s->ptimer_1Hz); | ||
57 | ptimer_transaction_commit(s->ptimer_1Hz); | ||
58 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_init(Object *obj) | ||
59 | { | ||
60 | Exynos4210RTCState *s = EXYNOS4210_RTC(obj); | ||
61 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | ||
62 | - QEMUBH *bh; | ||
63 | |||
64 | - bh = qemu_bh_new(exynos4210_rtc_tick, s); | ||
65 | - s->ptimer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); | ||
66 | + s->ptimer = ptimer_init(exynos4210_rtc_tick, s, PTIMER_POLICY_DEFAULT); | ||
67 | + ptimer_transaction_begin(s->ptimer); | ||
68 | ptimer_set_freq(s->ptimer, RTC_BASE_FREQ); | ||
69 | exynos4210_rtc_update_freq(s, 0); | ||
70 | + ptimer_transaction_commit(s->ptimer); | ||
71 | |||
72 | s->ptimer_1Hz = ptimer_init(exynos4210_rtc_1Hz_tick, | ||
73 | s, PTIMER_POLICY_DEFAULT); | ||
74 | -- | ||
75 | 2.20.1 | ||
76 | |||
77 | diff view generated by jsdifflib |
1 | Factor out the implementation of SYS_SEEK via the new function | 1 | The AN524 has a USB controller (an ISP1763); we don't have a model of |
---|---|---|---|
2 | tables. | 2 | it but we should provide a stub "unimplemented-device" for it. This |
3 | is slightly complicated because the USB controller shares a PPC port | ||
4 | with the ethernet controller. | ||
5 | |||
6 | Implement a make_* function which provides creates a container | ||
7 | MemoryRegion with both the ethernet controller and an | ||
8 | unimplemented-device stub for the USB controller. | ||
3 | 9 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 11 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
6 | Message-id: 20190916141544.17540-12-peter.maydell@linaro.org | 12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
13 | Message-id: 20210215115138.20465-22-peter.maydell@linaro.org | ||
7 | --- | 14 | --- |
8 | target/arm/arm-semi.c | 31 ++++++++++++++++++++++--------- | 15 | hw/arm/mps2-tz.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++- |
9 | 1 file changed, 22 insertions(+), 9 deletions(-) | 16 | 1 file changed, 47 insertions(+), 1 deletion(-) |
10 | 17 | ||
11 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 18 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
12 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/arm-semi.c | 20 | --- a/hw/arm/mps2-tz.c |
14 | +++ b/target/arm/arm-semi.c | 21 | +++ b/hw/arm/mps2-tz.c |
15 | @@ -XXX,XX +XXX,XX @@ typedef uint32_t sys_writefn(ARMCPU *cpu, GuestFD *gf, | 22 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState { |
16 | typedef uint32_t sys_readfn(ARMCPU *cpu, GuestFD *gf, | 23 | |
17 | target_ulong buf, uint32_t len); | 24 | ARMSSE iotkit; |
18 | typedef uint32_t sys_isattyfn(ARMCPU *cpu, GuestFD *gf); | 25 | MemoryRegion ram[MPS2TZ_RAM_MAX]; |
19 | +typedef uint32_t sys_seekfn(ARMCPU *cpu, GuestFD *gf, | 26 | + MemoryRegion eth_usb_container; |
20 | + target_ulong offset); | 27 | + |
21 | 28 | MPS2SCC scc; | |
22 | static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) | 29 | MPS2FPGAIO fpgaio; |
23 | { | 30 | TZPPC ppc[5]; |
24 | @@ -XXX,XX +XXX,XX @@ static uint32_t host_isattyfn(ARMCPU *cpu, GuestFD *gf) | 31 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState { |
25 | return isatty(gf->hostfd); | 32 | UnimplementedDeviceState gfx; |
33 | UnimplementedDeviceState cldc; | ||
34 | UnimplementedDeviceState rtc; | ||
35 | + UnimplementedDeviceState usb; | ||
36 | PL080State dma[4]; | ||
37 | TZMSC msc[4]; | ||
38 | CMSDKAPBUART uart[6]; | ||
39 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, | ||
40 | return sysbus_mmio_get_region(s, 0); | ||
26 | } | 41 | } |
27 | 42 | ||
28 | +static uint32_t host_seekfn(ARMCPU *cpu, GuestFD *gf, target_ulong offset) | 43 | +static MemoryRegion *make_eth_usb(MPS2TZMachineState *mms, void *opaque, |
44 | + const char *name, hwaddr size, | ||
45 | + const int *irqs) | ||
29 | +{ | 46 | +{ |
30 | + CPUARMState *env = &cpu->env; | 47 | + /* |
31 | + uint32_t ret = set_swi_errno(env, lseek(gf->hostfd, offset, SEEK_SET)); | 48 | + * The AN524 makes the ethernet and USB share a PPC port. |
32 | + if (ret == (uint32_t)-1) { | 49 | + * irqs[] is the ethernet IRQ. |
33 | + return -1; | 50 | + */ |
34 | + } | 51 | + SysBusDevice *s; |
35 | + return 0; | 52 | + NICInfo *nd = &nd_table[0]; |
53 | + | ||
54 | + memory_region_init(&mms->eth_usb_container, OBJECT(mms), | ||
55 | + "mps2-tz-eth-usb-container", 0x200000); | ||
56 | + | ||
57 | + /* | ||
58 | + * In hardware this is a LAN9220; the LAN9118 is software compatible | ||
59 | + * except that it doesn't support the checksum-offload feature. | ||
60 | + */ | ||
61 | + qemu_check_nic_model(nd, "lan9118"); | ||
62 | + mms->lan9118 = qdev_new(TYPE_LAN9118); | ||
63 | + qdev_set_nic_properties(mms->lan9118, nd); | ||
64 | + | ||
65 | + s = SYS_BUS_DEVICE(mms->lan9118); | ||
66 | + sysbus_realize_and_unref(s, &error_fatal); | ||
67 | + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); | ||
68 | + | ||
69 | + memory_region_add_subregion(&mms->eth_usb_container, | ||
70 | + 0, sysbus_mmio_get_region(s, 0)); | ||
71 | + | ||
72 | + /* The USB OTG controller is an ISP1763; we don't have a model of it. */ | ||
73 | + object_initialize_child(OBJECT(mms), "usb-otg", | ||
74 | + &mms->usb, TYPE_UNIMPLEMENTED_DEVICE); | ||
75 | + qdev_prop_set_string(DEVICE(&mms->usb), "name", "usb-otg"); | ||
76 | + qdev_prop_set_uint64(DEVICE(&mms->usb), "size", 0x100000); | ||
77 | + s = SYS_BUS_DEVICE(&mms->usb); | ||
78 | + sysbus_realize(s, &error_fatal); | ||
79 | + | ||
80 | + memory_region_add_subregion(&mms->eth_usb_container, | ||
81 | + 0x100000, sysbus_mmio_get_region(s, 0)); | ||
82 | + | ||
83 | + return &mms->eth_usb_container; | ||
36 | +} | 84 | +} |
37 | + | 85 | + |
38 | static uint32_t gdb_closefn(ARMCPU *cpu, GuestFD *gf) | 86 | static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, |
39 | { | 87 | const char *name, hwaddr size, |
40 | return arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); | 88 | const int *irqs) |
41 | @@ -XXX,XX +XXX,XX @@ static uint32_t gdb_isattyfn(ARMCPU *cpu, GuestFD *gf) | 89 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) |
42 | return arm_gdb_syscall(cpu, arm_semi_cb, "isatty,%x", gf->hostfd); | 90 | { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, |
43 | } | 91 | { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, |
44 | 92 | { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, | |
45 | +static uint32_t gdb_seekfn(ARMCPU *cpu, GuestFD *gf, target_ulong offset) | 93 | - { "eth", make_eth_dev, NULL, 0x41400000, 0x100000, { 48 } }, |
46 | +{ | 94 | + { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 48 } }, |
47 | + return arm_gdb_syscall(cpu, arm_semi_cb, "lseek,%x,%x,0", | 95 | }, |
48 | + gf->hostfd, offset); | 96 | }, |
49 | +} | 97 | }; |
50 | + | ||
51 | typedef struct GuestFDFunctions { | ||
52 | sys_closefn *closefn; | ||
53 | sys_writefn *writefn; | ||
54 | sys_readfn *readfn; | ||
55 | sys_isattyfn *isattyfn; | ||
56 | + sys_seekfn *seekfn; | ||
57 | } GuestFDFunctions; | ||
58 | |||
59 | static const GuestFDFunctions guestfd_fns[] = { | ||
60 | @@ -XXX,XX +XXX,XX @@ static const GuestFDFunctions guestfd_fns[] = { | ||
61 | .writefn = host_writefn, | ||
62 | .readfn = host_readfn, | ||
63 | .isattyfn = host_isattyfn, | ||
64 | + .seekfn = host_seekfn, | ||
65 | }, | ||
66 | [GuestFDGDB] = { | ||
67 | .closefn = gdb_closefn, | ||
68 | .writefn = gdb_writefn, | ||
69 | .readfn = gdb_readfn, | ||
70 | .isattyfn = gdb_isattyfn, | ||
71 | + .seekfn = gdb_seekfn, | ||
72 | }, | ||
73 | }; | ||
74 | |||
75 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
76 | return set_swi_errno(env, -1); | ||
77 | } | ||
78 | |||
79 | - if (use_gdb_syscalls()) { | ||
80 | - return arm_gdb_syscall(cpu, arm_semi_cb, "lseek,%x,%x,0", | ||
81 | - gf->hostfd, arg1); | ||
82 | - } else { | ||
83 | - ret = set_swi_errno(env, lseek(gf->hostfd, arg1, SEEK_SET)); | ||
84 | - if (ret == (uint32_t)-1) | ||
85 | - return -1; | ||
86 | - return 0; | ||
87 | - } | ||
88 | + return guestfd_fns[gf->type].seekfn(cpu, gf, arg1); | ||
89 | case TARGET_SYS_FLEN: | ||
90 | GET_ARG(0); | ||
91 | |||
92 | -- | 98 | -- |
93 | 2.20.1 | 99 | 2.20.1 |
94 | 100 | ||
95 | 101 | diff view generated by jsdifflib |
1 | Version 2.0 of the semihosting specification added support for | 1 | The AN524 has a PL031 RTC, which we have a model of; provide it |
---|---|---|---|
2 | allowing a guest to detect whether the implementation supported | 2 | rather than an unimplemented-device stub. |
3 | particular features. This works by the guest opening a magic | ||
4 | file ":semihosting-features", which contains a fixed set of | ||
5 | data with some magic numbers followed by a sequence of bytes | ||
6 | with feature flags. The file is expected to behave sensibly | ||
7 | for the various semihosting calls which operate on files | ||
8 | (SYS_FLEN, SYS_SEEK, etc). | ||
9 | |||
10 | Implement this as another kind of guest FD using our function | ||
11 | table dispatch mechanism. Initially we report no extended | ||
12 | features, so we have just one feature flag byte which is zero. | ||
13 | 3 | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
16 | Message-id: 20190916141544.17540-14-peter.maydell@linaro.org | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20210215115138.20465-23-peter.maydell@linaro.org | ||
17 | --- | 8 | --- |
18 | target/arm/arm-semi.c | 109 +++++++++++++++++++++++++++++++++++++++++- | 9 | hw/arm/mps2-tz.c | 22 ++++++++++++++++++++-- |
19 | 1 file changed, 108 insertions(+), 1 deletion(-) | 10 | 1 file changed, 20 insertions(+), 2 deletions(-) |
20 | 11 | ||
21 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 12 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
22 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/target/arm/arm-semi.c | 14 | --- a/hw/arm/mps2-tz.c |
24 | +++ b/target/arm/arm-semi.c | 15 | +++ b/hw/arm/mps2-tz.c |
25 | @@ -XXX,XX +XXX,XX @@ typedef enum GuestFDType { | 16 | @@ -XXX,XX +XXX,XX @@ |
26 | GuestFDUnused = 0, | 17 | #include "hw/misc/tz-msc.h" |
27 | GuestFDHost = 1, | 18 | #include "hw/arm/armsse.h" |
28 | GuestFDGDB = 2, | 19 | #include "hw/dma/pl080.h" |
29 | + GuestFDFeatureFile = 3, | 20 | +#include "hw/rtc/pl031.h" |
30 | } GuestFDType; | 21 | #include "hw/ssi/pl022.h" |
31 | 22 | #include "hw/i2c/arm_sbcon_i2c.h" | |
32 | /* | 23 | #include "hw/net/lan9118.h" |
33 | @@ -XXX,XX +XXX,XX @@ typedef enum GuestFDType { | 24 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState { |
34 | */ | 25 | UnimplementedDeviceState gpio[4]; |
35 | typedef struct GuestFD { | 26 | UnimplementedDeviceState gfx; |
36 | GuestFDType type; | 27 | UnimplementedDeviceState cldc; |
37 | - int hostfd; | 28 | - UnimplementedDeviceState rtc; |
38 | + union { | 29 | UnimplementedDeviceState usb; |
39 | + int hostfd; | 30 | + PL031State rtc; |
40 | + target_ulong featurefile_offset; | 31 | PL080State dma[4]; |
41 | + }; | 32 | TZMSC msc[4]; |
42 | } GuestFD; | 33 | CMSDKAPBUART uart[6]; |
43 | 34 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, | |
44 | static GArray *guestfd_array; | 35 | return sysbus_mmio_get_region(s, 0); |
45 | @@ -XXX,XX +XXX,XX @@ static uint32_t gdb_flenfn(ARMCPU *cpu, GuestFD *gf) | ||
46 | gf->hostfd, arm_flen_buf(cpu)); | ||
47 | } | 36 | } |
48 | 37 | ||
49 | +#define SHFB_MAGIC_0 0x53 | 38 | +static MemoryRegion *make_rtc(MPS2TZMachineState *mms, void *opaque, |
50 | +#define SHFB_MAGIC_1 0x48 | 39 | + const char *name, hwaddr size, |
51 | +#define SHFB_MAGIC_2 0x46 | 40 | + const int *irqs) |
52 | +#define SHFB_MAGIC_3 0x42 | 41 | +{ |
42 | + PL031State *pl031 = opaque; | ||
43 | + SysBusDevice *s; | ||
53 | + | 44 | + |
54 | +static const uint8_t featurefile_data[] = { | 45 | + object_initialize_child(OBJECT(mms), name, pl031, TYPE_PL031); |
55 | + SHFB_MAGIC_0, | 46 | + s = SYS_BUS_DEVICE(pl031); |
56 | + SHFB_MAGIC_1, | 47 | + sysbus_realize(s, &error_fatal); |
57 | + SHFB_MAGIC_2, | 48 | + /* |
58 | + SHFB_MAGIC_3, | 49 | + * The board docs don't give an IRQ number for the PL031, so |
59 | + 0, /* Feature byte 0 */ | 50 | + * presumably it is not connected. |
60 | +}; | 51 | + */ |
61 | + | 52 | + return sysbus_mmio_get_region(s, 0); |
62 | +static void init_featurefile_guestfd(int guestfd) | ||
63 | +{ | ||
64 | + GuestFD *gf = do_get_guestfd(guestfd); | ||
65 | + | ||
66 | + assert(gf); | ||
67 | + gf->type = GuestFDFeatureFile; | ||
68 | + gf->featurefile_offset = 0; | ||
69 | +} | 53 | +} |
70 | + | 54 | + |
71 | +static uint32_t featurefile_closefn(ARMCPU *cpu, GuestFD *gf) | 55 | static void create_non_mpc_ram(MPS2TZMachineState *mms) |
72 | +{ | 56 | { |
73 | + /* Nothing to do */ | 57 | /* |
74 | + return 0; | 58 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) |
75 | +} | 59 | |
76 | + | 60 | { /* port 9 reserved */ }, |
77 | +static uint32_t featurefile_writefn(ARMCPU *cpu, GuestFD *gf, | 61 | { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, |
78 | + target_ulong buf, uint32_t len) | 62 | - { "rtc", make_unimp_dev, &mms->rtc, 0x4130b000, 0x1000 }, |
79 | +{ | 63 | + { "rtc", make_rtc, &mms->rtc, 0x4130b000, 0x1000 }, |
80 | + /* This fd can never be open for writing */ | 64 | }, |
81 | + CPUARMState *env = &cpu->env; | 65 | }, { |
82 | + | 66 | .name = "ahb_ppcexp0", |
83 | + errno = EBADF; | ||
84 | + return set_swi_errno(env, -1); | ||
85 | +} | ||
86 | + | ||
87 | +static uint32_t featurefile_readfn(ARMCPU *cpu, GuestFD *gf, | ||
88 | + target_ulong buf, uint32_t len) | ||
89 | +{ | ||
90 | + uint32_t i; | ||
91 | +#ifndef CONFIG_USER_ONLY | ||
92 | + CPUARMState *env = &cpu->env; | ||
93 | +#endif | ||
94 | + char *s; | ||
95 | + | ||
96 | + s = lock_user(VERIFY_WRITE, buf, len, 0); | ||
97 | + if (!s) { | ||
98 | + return len; | ||
99 | + } | ||
100 | + | ||
101 | + for (i = 0; i < len; i++) { | ||
102 | + if (gf->featurefile_offset >= sizeof(featurefile_data)) { | ||
103 | + break; | ||
104 | + } | ||
105 | + s[i] = featurefile_data[gf->featurefile_offset]; | ||
106 | + gf->featurefile_offset++; | ||
107 | + } | ||
108 | + | ||
109 | + unlock_user(s, buf, len); | ||
110 | + | ||
111 | + /* Return number of bytes not read */ | ||
112 | + return len - i; | ||
113 | +} | ||
114 | + | ||
115 | +static uint32_t featurefile_isattyfn(ARMCPU *cpu, GuestFD *gf) | ||
116 | +{ | ||
117 | + return 0; | ||
118 | +} | ||
119 | + | ||
120 | +static uint32_t featurefile_seekfn(ARMCPU *cpu, GuestFD *gf, | ||
121 | + target_ulong offset) | ||
122 | +{ | ||
123 | + gf->featurefile_offset = offset; | ||
124 | + return 0; | ||
125 | +} | ||
126 | + | ||
127 | +static uint32_t featurefile_flenfn(ARMCPU *cpu, GuestFD *gf) | ||
128 | +{ | ||
129 | + return sizeof(featurefile_data); | ||
130 | +} | ||
131 | + | ||
132 | typedef struct GuestFDFunctions { | ||
133 | sys_closefn *closefn; | ||
134 | sys_writefn *writefn; | ||
135 | @@ -XXX,XX +XXX,XX @@ static const GuestFDFunctions guestfd_fns[] = { | ||
136 | .seekfn = gdb_seekfn, | ||
137 | .flenfn = gdb_flenfn, | ||
138 | }, | ||
139 | + [GuestFDFeatureFile] = { | ||
140 | + .closefn = featurefile_closefn, | ||
141 | + .writefn = featurefile_writefn, | ||
142 | + .readfn = featurefile_readfn, | ||
143 | + .isattyfn = featurefile_isattyfn, | ||
144 | + .seekfn = featurefile_seekfn, | ||
145 | + .flenfn = featurefile_flenfn, | ||
146 | + }, | ||
147 | }; | ||
148 | |||
149 | /* Read the input value from the argument block; fail the semihosting | ||
150 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
151 | unlock_user(s, arg0, 0); | ||
152 | return guestfd; | ||
153 | } | ||
154 | + if (strcmp(s, ":semihosting-features") == 0) { | ||
155 | + unlock_user(s, arg0, 0); | ||
156 | + /* We must fail opens for modes other than 0 ('r') or 1 ('rb') */ | ||
157 | + if (arg1 != 0 && arg1 != 1) { | ||
158 | + dealloc_guestfd(guestfd); | ||
159 | + errno = EACCES; | ||
160 | + return set_swi_errno(env, -1); | ||
161 | + } | ||
162 | + init_featurefile_guestfd(guestfd); | ||
163 | + return guestfd; | ||
164 | + } | ||
165 | + | ||
166 | if (use_gdb_syscalls()) { | ||
167 | arm_semi_open_guestfd = guestfd; | ||
168 | ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0, | ||
169 | -- | 67 | -- |
170 | 2.20.1 | 68 | 2.20.1 |
171 | 69 | ||
172 | 70 | diff view generated by jsdifflib |
1 | SH_EXT_EXIT_EXTENDED is a v2.0 semihosting extension: it | 1 | Add brief documentation of the new mps3-an524 board. |
---|---|---|---|
2 | indicates that the implementation supports the SYS_EXIT_EXTENDED | ||
3 | function. This function allows both A64 and A32/T32 guests to | ||
4 | exit with a specified exit status, unlike the older SYS_EXIT | ||
5 | function which only allowed this for A64 guests. Implement | ||
6 | this extension. | ||
7 | 2 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
10 | Message-id: 20190916141544.17540-15-peter.maydell@linaro.org | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 20210215115138.20465-24-peter.maydell@linaro.org | ||
11 | --- | 7 | --- |
12 | target/arm/arm-semi.c | 19 ++++++++++++++----- | 8 | docs/system/arm/mps2.rst | 24 ++++++++++++++++++------ |
13 | 1 file changed, 14 insertions(+), 5 deletions(-) | 9 | 1 file changed, 18 insertions(+), 6 deletions(-) |
14 | 10 | ||
15 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 11 | diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst |
16 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/arm-semi.c | 13 | --- a/docs/system/arm/mps2.rst |
18 | +++ b/target/arm/arm-semi.c | 14 | +++ b/docs/system/arm/mps2.rst |
19 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ |
20 | #define TARGET_SYS_HEAPINFO 0x16 | 16 | -Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``) |
21 | #define TARGET_SYS_EXIT 0x18 | 17 | -================================================================================================================ |
22 | #define TARGET_SYS_SYNCCACHE 0x19 | 18 | +Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``) |
23 | +#define TARGET_SYS_EXIT_EXTENDED 0x20 | 19 | +========================================================================================================================================= |
24 | 20 | ||
25 | /* ADP_Stopped_ApplicationExit is used for exit(0), | 21 | These board models all use Arm M-profile CPUs. |
26 | * anything else is implemented as exit(1) */ | 22 | |
27 | @@ -XXX,XX +XXX,XX @@ static uint32_t gdb_flenfn(ARMCPU *cpu, GuestFD *gf) | 23 | -The Arm MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger |
28 | #define SHFB_MAGIC_2 0x46 | 24 | -FPGA but is otherwise the same as the 2). Since the CPU itself |
29 | #define SHFB_MAGIC_3 0x42 | 25 | -and most of the devices are in the FPGA, the details of the board |
30 | 26 | -as seen by the guest depend significantly on the FPGA image. | |
31 | +/* Feature bits reportable in feature byte 0 */ | 27 | +The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a |
32 | +#define SH_EXT_EXIT_EXTENDED (1 << 0) | 28 | +bigger FPGA but is otherwise the same as the 2; the 3 has a bigger |
29 | +FPGA again, can handle 4GB of RAM and has a USB controller and QSPI flash). | ||
33 | + | 30 | + |
34 | static const uint8_t featurefile_data[] = { | 31 | +Since the CPU itself and most of the devices are in the FPGA, the |
35 | SHFB_MAGIC_0, | 32 | +details of the board as seen by the guest depend significantly on the |
36 | SHFB_MAGIC_1, | 33 | +FPGA image. |
37 | SHFB_MAGIC_2, | 34 | |
38 | SHFB_MAGIC_3, | 35 | QEMU models the following FPGA images: |
39 | - 0, /* Feature byte 0 */ | 36 | |
40 | + SH_EXT_EXIT_EXTENDED, /* Feature byte 0 */ | 37 | @@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images: |
41 | }; | 38 | Cortex-M3 'DesignStart' as documented in Arm Application Note AN511 |
42 | 39 | ``mps2-an521`` | |
43 | static void init_featurefile_guestfd(int guestfd) | 40 | Dual Cortex-M33 as documented in Arm Application Note AN521 |
44 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | 41 | +``mps3-an524`` |
45 | return 0; | 42 | + Dual Cortex-M33 on an MPS3, as documented in Arm Application Note AN524 |
46 | } | 43 | |
47 | case TARGET_SYS_EXIT: | 44 | Differences between QEMU and real hardware: |
48 | - if (is_a64(env)) { | 45 | |
49 | + case TARGET_SYS_EXIT_EXTENDED: | 46 | - AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to |
50 | + if (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(env)) { | 47 | block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as |
51 | /* | 48 | if zbt_boot_ctrl is always zero) |
52 | - * The A64 version of this call takes a parameter block, | 49 | +- AN524 remapping of low memory to either BRAM or to QSPI flash is |
53 | + * The A64 version of SYS_EXIT takes a parameter block, | 50 | + unimplemented (QEMU always maps this to BRAM, ignoring the |
54 | * so the application-exit type can return a subcode which | 51 | + SCC CFG_REG0 memory-remap bit) |
55 | * is the exit status code from the application. | 52 | - QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest |
56 | + * SYS_EXIT_EXTENDED is an a new-in-v2.0 optional function | 53 | visible difference is that the LAN9118 doesn't support checksum |
57 | + * which allows A32/T32 guests to also provide a status code. | 54 | offloading |
58 | */ | 55 | +- QEMU does not model the QSPI flash in MPS3 boards as real QSPI |
59 | GET_ARG(0); | 56 | + flash, but only as simple ROM, so attempting to rewrite the flash |
60 | GET_ARG(1); | 57 | + from the guest will fail |
61 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | 58 | +- QEMU does not model the USB controller in MPS3 boards |
62 | } | ||
63 | } else { | ||
64 | /* | ||
65 | - * ARM specifies only Stopped_ApplicationExit as normal | ||
66 | - * exit, everything else is considered an error | ||
67 | + * The A32/T32 version of SYS_EXIT specifies only | ||
68 | + * Stopped_ApplicationExit as normal exit, but does not | ||
69 | + * allow the guest to specify the exit status code. | ||
70 | + * Everything else is considered an error. | ||
71 | */ | ||
72 | ret = (args == ADP_Stopped_ApplicationExit) ? 0 : 1; | ||
73 | } | ||
74 | -- | 59 | -- |
75 | 2.20.1 | 60 | 2.20.1 |
76 | 61 | ||
77 | 62 | diff view generated by jsdifflib |
1 | Switch the mss-timer code away from bottom-half based ptimers to | 1 | Update old infocenter.arm.com URLs to the equivalent developer.arm.com |
---|---|---|---|
2 | the new transaction-based ptimer API. This just requires adding | 2 | ones (the old URLs should redirect, but we might as well avoid the |
3 | begin/commit calls around the various places that modify the ptimer | 3 | redirection notice, and the new URLs are pleasantly shorter). |
4 | state, and using the new ptimer_init() function to create the timer. | 4 | |
5 | This commit covers the links to the MPS2 board TRM, the various | ||
6 | Application Notes, the IoTKit and SSE-200 documents. | ||
5 | 7 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20191008171740.9679-20-peter.maydell@linaro.org | 10 | Message-id: 20210215115138.20465-25-peter.maydell@linaro.org |
9 | --- | 11 | --- |
10 | include/hw/timer/mss-timer.h | 1 - | 12 | include/hw/arm/armsse.h | 4 ++-- |
11 | hw/timer/mss-timer.c | 11 ++++++++--- | 13 | include/hw/misc/armsse-cpuid.h | 2 +- |
12 | 2 files changed, 8 insertions(+), 4 deletions(-) | 14 | include/hw/misc/armsse-mhu.h | 2 +- |
13 | 15 | include/hw/misc/iotkit-secctl.h | 2 +- | |
14 | diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h | 16 | include/hw/misc/iotkit-sysctl.h | 2 +- |
15 | index XXXXXXX..XXXXXXX 100644 | 17 | include/hw/misc/iotkit-sysinfo.h | 2 +- |
16 | --- a/include/hw/timer/mss-timer.h | 18 | include/hw/misc/mps2-fpgaio.h | 2 +- |
17 | +++ b/include/hw/timer/mss-timer.h | 19 | hw/arm/mps2-tz.c | 11 +++++------ |
18 | @@ -XXX,XX +XXX,XX @@ | 20 | hw/misc/armsse-cpuid.c | 2 +- |
19 | #define R_TIM1_MAX 6 | 21 | hw/misc/armsse-mhu.c | 2 +- |
20 | 22 | hw/misc/iotkit-sysctl.c | 2 +- | |
21 | struct Msf2Timer { | 23 | hw/misc/iotkit-sysinfo.c | 2 +- |
22 | - QEMUBH *bh; | 24 | hw/misc/mps2-fpgaio.c | 2 +- |
23 | ptimer_state *ptimer; | 25 | hw/misc/mps2-scc.c | 2 +- |
24 | 26 | 14 files changed, 19 insertions(+), 20 deletions(-) | |
25 | uint32_t regs[R_TIM1_MAX]; | 27 | |
26 | diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c | 28 | diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h |
27 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/hw/timer/mss-timer.c | 30 | --- a/include/hw/arm/armsse.h |
29 | +++ b/hw/timer/mss-timer.c | 31 | +++ b/include/hw/arm/armsse.h |
30 | @@ -XXX,XX +XXX,XX @@ | 32 | @@ -XXX,XX +XXX,XX @@ |
31 | */ | 33 | * hardware, which include the IoT Kit and the SSE-050, SSE-100 and |
34 | * SSE-200. Currently we model: | ||
35 | * - the Arm IoT Kit which is documented in | ||
36 | - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | ||
37 | + * https://developer.arm.com/documentation/ecm0601256/latest | ||
38 | * - the SSE-200 which is documented in | ||
39 | - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf | ||
40 | + * https://developer.arm.com/documentation/101104/latest/ | ||
41 | * | ||
42 | * The IoTKit contains: | ||
43 | * a Cortex-M33 | ||
44 | diff --git a/include/hw/misc/armsse-cpuid.h b/include/hw/misc/armsse-cpuid.h | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/include/hw/misc/armsse-cpuid.h | ||
47 | +++ b/include/hw/misc/armsse-cpuid.h | ||
48 | @@ -XXX,XX +XXX,XX @@ | ||
49 | /* | ||
50 | * This is a model of the "CPU_IDENTITY" register block which is part of the | ||
51 | * Arm SSE-200 and documented in | ||
52 | - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf | ||
53 | + * https://developer.arm.com/documentation/101104/latest/ | ||
54 | * | ||
55 | * QEMU interface: | ||
56 | * + QOM property "CPUID": the value to use for the CPUID register | ||
57 | diff --git a/include/hw/misc/armsse-mhu.h b/include/hw/misc/armsse-mhu.h | ||
58 | index XXXXXXX..XXXXXXX 100644 | ||
59 | --- a/include/hw/misc/armsse-mhu.h | ||
60 | +++ b/include/hw/misc/armsse-mhu.h | ||
61 | @@ -XXX,XX +XXX,XX @@ | ||
62 | /* | ||
63 | * This is a model of the Message Handling Unit (MHU) which is part of the | ||
64 | * Arm SSE-200 and documented in | ||
65 | - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf | ||
66 | + * https://developer.arm.com/documentation/101104/latest/ | ||
67 | * | ||
68 | * QEMU interface: | ||
69 | * + sysbus MMIO region 0: the system information register bank | ||
70 | diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h | ||
71 | index XXXXXXX..XXXXXXX 100644 | ||
72 | --- a/include/hw/misc/iotkit-secctl.h | ||
73 | +++ b/include/hw/misc/iotkit-secctl.h | ||
74 | @@ -XXX,XX +XXX,XX @@ | ||
75 | |||
76 | /* This is a model of the security controller which is part of the | ||
77 | * Arm IoT Kit and documented in | ||
78 | - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | ||
79 | + * https://developer.arm.com/documentation/ecm0601256/latest | ||
80 | * | ||
81 | * QEMU interface: | ||
82 | * + sysbus MMIO region 0 is the "secure privilege control block" registers | ||
83 | diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h | ||
84 | index XXXXXXX..XXXXXXX 100644 | ||
85 | --- a/include/hw/misc/iotkit-sysctl.h | ||
86 | +++ b/include/hw/misc/iotkit-sysctl.h | ||
87 | @@ -XXX,XX +XXX,XX @@ | ||
88 | /* | ||
89 | * This is a model of the "system control element" which is part of the | ||
90 | * Arm IoTKit and documented in | ||
91 | - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | ||
92 | + * https://developer.arm.com/documentation/ecm0601256/latest | ||
93 | * Specifically, it implements the "system information block" and | ||
94 | * "system control register" blocks. | ||
95 | * | ||
96 | diff --git a/include/hw/misc/iotkit-sysinfo.h b/include/hw/misc/iotkit-sysinfo.h | ||
97 | index XXXXXXX..XXXXXXX 100644 | ||
98 | --- a/include/hw/misc/iotkit-sysinfo.h | ||
99 | +++ b/include/hw/misc/iotkit-sysinfo.h | ||
100 | @@ -XXX,XX +XXX,XX @@ | ||
101 | /* | ||
102 | * This is a model of the "system information block" which is part of the | ||
103 | * Arm IoTKit and documented in | ||
104 | - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | ||
105 | + * https://developer.arm.com/documentation/ecm0601256/latest | ||
106 | * QEMU interface: | ||
107 | * + QOM property "SYS_VERSION": value to use for SYS_VERSION register | ||
108 | * + QOM property "SYS_CONFIG": value to use for SYS_CONFIG register | ||
109 | diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h | ||
110 | index XXXXXXX..XXXXXXX 100644 | ||
111 | --- a/include/hw/misc/mps2-fpgaio.h | ||
112 | +++ b/include/hw/misc/mps2-fpgaio.h | ||
113 | @@ -XXX,XX +XXX,XX @@ | ||
114 | /* This is a model of the FPGAIO register block in the AN505 | ||
115 | * FPGA image for the MPS2 dev board; it is documented in the | ||
116 | * application note: | ||
117 | - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html | ||
118 | + * https://developer.arm.com/documentation/dai0505/latest/ | ||
119 | * | ||
120 | * QEMU interface: | ||
121 | * + sysbus MMIO region 0: the register bank | ||
122 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c | ||
123 | index XXXXXXX..XXXXXXX 100644 | ||
124 | --- a/hw/arm/mps2-tz.c | ||
125 | +++ b/hw/arm/mps2-tz.c | ||
126 | @@ -XXX,XX +XXX,XX @@ | ||
127 | * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 | ||
128 | * | ||
129 | * Board TRM: | ||
130 | - * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf | ||
131 | + * https://developer.arm.com/documentation/100112/latest/ | ||
132 | * Application Note AN505: | ||
133 | - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html | ||
134 | + * https://developer.arm.com/documentation/dai0505/latest/ | ||
135 | * Application Note AN521: | ||
136 | - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html | ||
137 | + * https://developer.arm.com/documentation/dai0521/latest/ | ||
138 | * Application Note AN524: | ||
139 | * https://developer.arm.com/documentation/dai0524/latest/ | ||
140 | * | ||
141 | * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide | ||
142 | * (ARM ECM0601256) for the details of some of the device layout: | ||
143 | - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | ||
144 | + * https://developer.arm.com/documentation/ecm0601256/latest | ||
145 | * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines | ||
146 | * most of the device layout: | ||
147 | - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf | ||
148 | - * | ||
149 | + * https://developer.arm.com/documentation/101104/latest/ | ||
150 | */ | ||
32 | 151 | ||
33 | #include "qemu/osdep.h" | 152 | #include "qemu/osdep.h" |
34 | -#include "qemu/main-loop.h" | 153 | diff --git a/hw/misc/armsse-cpuid.c b/hw/misc/armsse-cpuid.c |
35 | #include "qemu/module.h" | 154 | index XXXXXXX..XXXXXXX 100644 |
36 | #include "qemu/log.h" | 155 | --- a/hw/misc/armsse-cpuid.c |
37 | #include "hw/irq.h" | 156 | +++ b/hw/misc/armsse-cpuid.c |
38 | @@ -XXX,XX +XXX,XX @@ static void timer_update_irq(struct Msf2Timer *st) | 157 | @@ -XXX,XX +XXX,XX @@ |
39 | qemu_set_irq(st->irq, (ier && isr)); | 158 | /* |
40 | } | 159 | * This is a model of the "CPU_IDENTITY" register block which is part of the |
41 | 160 | * Arm SSE-200 and documented in | |
42 | +/* Must be called from within a ptimer_transaction_begin/commit block */ | 161 | - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf |
43 | static void timer_update(struct Msf2Timer *st) | 162 | + * https://developer.arm.com/documentation/101104/latest/ |
44 | { | 163 | * |
45 | uint64_t count; | 164 | * It consists of one read-only CPUID register (set by QOM property), plus the |
46 | @@ -XXX,XX +XXX,XX @@ timer_write(void *opaque, hwaddr offset, | 165 | * usual ID registers. |
47 | switch (addr) { | 166 | diff --git a/hw/misc/armsse-mhu.c b/hw/misc/armsse-mhu.c |
48 | case R_TIM_CTRL: | 167 | index XXXXXXX..XXXXXXX 100644 |
49 | st->regs[R_TIM_CTRL] = value; | 168 | --- a/hw/misc/armsse-mhu.c |
50 | + ptimer_transaction_begin(st->ptimer); | 169 | +++ b/hw/misc/armsse-mhu.c |
51 | timer_update(st); | 170 | @@ -XXX,XX +XXX,XX @@ |
52 | + ptimer_transaction_commit(st->ptimer); | 171 | /* |
53 | break; | 172 | * This is a model of the Message Handling Unit (MHU) which is part of the |
54 | 173 | * Arm SSE-200 and documented in | |
55 | case R_TIM_RIS: | 174 | - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf |
56 | @@ -XXX,XX +XXX,XX @@ timer_write(void *opaque, hwaddr offset, | 175 | + * https://developer.arm.com/documentation/101104/latest/ |
57 | case R_TIM_LOADVAL: | 176 | */ |
58 | st->regs[R_TIM_LOADVAL] = value; | 177 | |
59 | if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) { | 178 | #include "qemu/osdep.h" |
60 | + ptimer_transaction_begin(st->ptimer); | 179 | diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c |
61 | timer_update(st); | 180 | index XXXXXXX..XXXXXXX 100644 |
62 | + ptimer_transaction_commit(st->ptimer); | 181 | --- a/hw/misc/iotkit-sysctl.c |
63 | } | 182 | +++ b/hw/misc/iotkit-sysctl.c |
64 | break; | 183 | @@ -XXX,XX +XXX,XX @@ |
65 | 184 | /* | |
66 | @@ -XXX,XX +XXX,XX @@ static void mss_timer_init(Object *obj) | 185 | * This is a model of the "system control element" which is part of the |
67 | for (i = 0; i < NUM_TIMERS; i++) { | 186 | * Arm IoTKit and documented in |
68 | struct Msf2Timer *st = &t->timers[i]; | 187 | - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html |
69 | 188 | + * https://developer.arm.com/documentation/ecm0601256/latest | |
70 | - st->bh = qemu_bh_new(timer_hit, st); | 189 | * Specifically, it implements the "system control register" blocks. |
71 | - st->ptimer = ptimer_init_with_bh(st->bh, PTIMER_POLICY_DEFAULT); | 190 | */ |
72 | + st->ptimer = ptimer_init(timer_hit, st, PTIMER_POLICY_DEFAULT); | 191 | |
73 | + ptimer_transaction_begin(st->ptimer); | 192 | diff --git a/hw/misc/iotkit-sysinfo.c b/hw/misc/iotkit-sysinfo.c |
74 | ptimer_set_freq(st->ptimer, t->freq_hz); | 193 | index XXXXXXX..XXXXXXX 100644 |
75 | + ptimer_transaction_commit(st->ptimer); | 194 | --- a/hw/misc/iotkit-sysinfo.c |
76 | sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq); | 195 | +++ b/hw/misc/iotkit-sysinfo.c |
77 | } | 196 | @@ -XXX,XX +XXX,XX @@ |
197 | /* | ||
198 | * This is a model of the "system information block" which is part of the | ||
199 | * Arm IoTKit and documented in | ||
200 | - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | ||
201 | + * https://developer.arm.com/documentation/ecm0601256/latest | ||
202 | * It consists of 2 read-only version/config registers, plus the | ||
203 | * usual ID registers. | ||
204 | */ | ||
205 | diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c | ||
206 | index XXXXXXX..XXXXXXX 100644 | ||
207 | --- a/hw/misc/mps2-fpgaio.c | ||
208 | +++ b/hw/misc/mps2-fpgaio.c | ||
209 | @@ -XXX,XX +XXX,XX @@ | ||
210 | /* This is a model of the "FPGA system control and I/O" block found | ||
211 | * in the AN505 FPGA image for the MPS2 devboard. | ||
212 | * It is documented in AN505: | ||
213 | - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html | ||
214 | + * https://developer.arm.com/documentation/dai0505/latest/ | ||
215 | */ | ||
216 | |||
217 | #include "qemu/osdep.h" | ||
218 | diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c | ||
219 | index XXXXXXX..XXXXXXX 100644 | ||
220 | --- a/hw/misc/mps2-scc.c | ||
221 | +++ b/hw/misc/mps2-scc.c | ||
222 | @@ -XXX,XX +XXX,XX @@ | ||
223 | * found in the FPGA images of MPS2 development boards. | ||
224 | * | ||
225 | * Documentation of it can be found in the MPS2 TRM: | ||
226 | - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100112_0100_03_en/index.html | ||
227 | + * https://developer.arm.com/documentation/100112/latest/ | ||
228 | * and also in the Application Notes documenting individual FPGA images. | ||
229 | */ | ||
78 | 230 | ||
79 | -- | 231 | -- |
80 | 2.20.1 | 232 | 2.20.1 |
81 | 233 | ||
82 | 234 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The set_swi_errno() function is called to capture the errno | ||
2 | from a host system call, so that we can return -1 from the | ||
3 | semihosting function and later allow the guest to get a more | ||
4 | specific error code with the SYS_ERRNO function. It comes in | ||
5 | two versions, one for user-only and one for softmmu. We forgot | ||
6 | to capture the errno in the softmmu version; fix the error. | ||
7 | 1 | ||
8 | (Semihosting calls directed to gdb are unaffected because | ||
9 | they go through a different code path that captures the | ||
10 | error return from the gdbstub call in arm_semi_cb() or | ||
11 | arm_semi_flen_cb().) | ||
12 | |||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
15 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
16 | Message-id: 20190916141544.17540-2-peter.maydell@linaro.org | ||
17 | --- | ||
18 | target/arm/arm-semi.c | 9 +++++---- | ||
19 | 1 file changed, 5 insertions(+), 4 deletions(-) | ||
20 | |||
21 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/target/arm/arm-semi.c | ||
24 | +++ b/target/arm/arm-semi.c | ||
25 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t set_swi_errno(TaskState *ts, uint32_t code) | ||
26 | return code; | ||
27 | } | ||
28 | #else | ||
29 | +static target_ulong syscall_err; | ||
30 | + | ||
31 | static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code) | ||
32 | { | ||
33 | + if (code == (uint32_t)-1) { | ||
34 | + syscall_err = errno; | ||
35 | + } | ||
36 | return code; | ||
37 | } | ||
38 | |||
39 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code) | ||
40 | |||
41 | static target_ulong arm_semi_syscall_len; | ||
42 | |||
43 | -#if !defined(CONFIG_USER_ONLY) | ||
44 | -static target_ulong syscall_err; | ||
45 | -#endif | ||
46 | - | ||
47 | static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) | ||
48 | { | ||
49 | ARMCPU *cpu = ARM_CPU(cs); | ||
50 | -- | ||
51 | 2.20.1 | ||
52 | |||
53 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | If we fail a semihosting call we should always set the | ||
2 | semihosting errno to something; we were failing to do | ||
3 | this for some of the "check inputs for sanity" cases. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20190916141544.17540-3-peter.maydell@linaro.org | ||
10 | --- | ||
11 | target/arm/arm-semi.c | 45 ++++++++++++++++++++++++++----------------- | ||
12 | 1 file changed, 27 insertions(+), 18 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/arm-semi.c | ||
17 | +++ b/target/arm/arm-semi.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, | ||
19 | #define GET_ARG(n) do { \ | ||
20 | if (is_a64(env)) { \ | ||
21 | if (get_user_u64(arg ## n, args + (n) * 8)) { \ | ||
22 | - return -1; \ | ||
23 | + errno = EFAULT; \ | ||
24 | + return set_swi_errno(ts, -1); \ | ||
25 | } \ | ||
26 | } else { \ | ||
27 | if (get_user_u32(arg ## n, args + (n) * 4)) { \ | ||
28 | - return -1; \ | ||
29 | + errno = EFAULT; \ | ||
30 | + return set_swi_errno(ts, -1); \ | ||
31 | } \ | ||
32 | } \ | ||
33 | } while (0) | ||
34 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
35 | GET_ARG(2); | ||
36 | s = lock_user_string(arg0); | ||
37 | if (!s) { | ||
38 | - /* FIXME - should this error code be -TARGET_EFAULT ? */ | ||
39 | - return (uint32_t)-1; | ||
40 | + errno = EFAULT; | ||
41 | + return set_swi_errno(ts, -1); | ||
42 | } | ||
43 | if (arg1 >= 12) { | ||
44 | unlock_user(s, arg0, 0); | ||
45 | - return (uint32_t)-1; | ||
46 | + errno = EINVAL; | ||
47 | + return set_swi_errno(ts, -1); | ||
48 | } | ||
49 | if (strcmp(s, ":tt") == 0) { | ||
50 | int result_fileno = arg1 < 4 ? STDIN_FILENO : STDOUT_FILENO; | ||
51 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
52 | } else { | ||
53 | s = lock_user_string(arg0); | ||
54 | if (!s) { | ||
55 | - /* FIXME - should this error code be -TARGET_EFAULT ? */ | ||
56 | - return (uint32_t)-1; | ||
57 | + errno = EFAULT; | ||
58 | + return set_swi_errno(ts, -1); | ||
59 | } | ||
60 | ret = set_swi_errno(ts, remove(s)); | ||
61 | unlock_user(s, arg0, 0); | ||
62 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
63 | char *s2; | ||
64 | s = lock_user_string(arg0); | ||
65 | s2 = lock_user_string(arg2); | ||
66 | - if (!s || !s2) | ||
67 | - /* FIXME - should this error code be -TARGET_EFAULT ? */ | ||
68 | - ret = (uint32_t)-1; | ||
69 | - else | ||
70 | + if (!s || !s2) { | ||
71 | + errno = EFAULT; | ||
72 | + ret = set_swi_errno(ts, -1); | ||
73 | + } else { | ||
74 | ret = set_swi_errno(ts, rename(s, s2)); | ||
75 | + } | ||
76 | if (s2) | ||
77 | unlock_user(s2, arg2, 0); | ||
78 | if (s) | ||
79 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
80 | } else { | ||
81 | s = lock_user_string(arg0); | ||
82 | if (!s) { | ||
83 | - /* FIXME - should this error code be -TARGET_EFAULT ? */ | ||
84 | - return (uint32_t)-1; | ||
85 | + errno = EFAULT; | ||
86 | + return set_swi_errno(ts, -1); | ||
87 | } | ||
88 | ret = set_swi_errno(ts, system(s)); | ||
89 | unlock_user(s, arg0, 0); | ||
90 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
91 | |||
92 | if (output_size > input_size) { | ||
93 | /* Not enough space to store command-line arguments. */ | ||
94 | - return -1; | ||
95 | + errno = E2BIG; | ||
96 | + return set_swi_errno(ts, -1); | ||
97 | } | ||
98 | |||
99 | /* Adjust the command-line length. */ | ||
100 | if (SET_ARG(1, output_size - 1)) { | ||
101 | /* Couldn't write back to argument block */ | ||
102 | - return -1; | ||
103 | + errno = EFAULT; | ||
104 | + return set_swi_errno(ts, -1); | ||
105 | } | ||
106 | |||
107 | /* Lock the buffer on the ARM side. */ | ||
108 | output_buffer = lock_user(VERIFY_WRITE, arg0, output_size, 0); | ||
109 | if (!output_buffer) { | ||
110 | - return -1; | ||
111 | + errno = EFAULT; | ||
112 | + return set_swi_errno(ts, -1); | ||
113 | } | ||
114 | |||
115 | /* Copy the command-line arguments. */ | ||
116 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
117 | |||
118 | if (copy_from_user(output_buffer, ts->info->arg_start, | ||
119 | output_size)) { | ||
120 | - status = -1; | ||
121 | + errno = EFAULT; | ||
122 | + status = set_swi_errno(ts, -1); | ||
123 | goto out; | ||
124 | } | ||
125 | |||
126 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
127 | |||
128 | if (fail) { | ||
129 | /* Couldn't write back to argument block */ | ||
130 | - return -1; | ||
131 | + errno = EFAULT; | ||
132 | + return set_swi_errno(ts, -1); | ||
133 | } | ||
134 | } | ||
135 | return 0; | ||
136 | -- | ||
137 | 2.20.1 | ||
138 | |||
139 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | When we are routing semihosting operations through the gdbstub, the | ||
2 | work of sorting out the return value and setting errno if necessary | ||
3 | is done by callback functions which are invoked by the gdbstub code. | ||
4 | Clean up some ifdeffery in those functions by having them call | ||
5 | set_swi_errno() to set the semihosting errno. | ||
6 | 1 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20190916141544.17540-7-peter.maydell@linaro.org | ||
11 | --- | ||
12 | target/arm/arm-semi.c | 27 ++++++--------------------- | ||
13 | 1 file changed, 6 insertions(+), 21 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/arm-semi.c | ||
18 | +++ b/target/arm/arm-semi.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) | ||
20 | { | ||
21 | ARMCPU *cpu = ARM_CPU(cs); | ||
22 | CPUARMState *env = &cpu->env; | ||
23 | -#ifdef CONFIG_USER_ONLY | ||
24 | - TaskState *ts = cs->opaque; | ||
25 | -#endif | ||
26 | target_ulong reg0 = is_a64(env) ? env->xregs[0] : env->regs[0]; | ||
27 | |||
28 | if (ret == (target_ulong)-1) { | ||
29 | -#ifdef CONFIG_USER_ONLY | ||
30 | - ts->swi_errno = err; | ||
31 | -#else | ||
32 | - syscall_err = err; | ||
33 | -#endif | ||
34 | + errno = err; | ||
35 | + set_swi_errno(env, -1); | ||
36 | reg0 = ret; | ||
37 | } else { | ||
38 | /* Fixup syscalls that use nonstardard return conventions. */ | ||
39 | @@ -XXX,XX +XXX,XX @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) | ||
40 | } else { | ||
41 | env->regs[0] = size; | ||
42 | } | ||
43 | -#ifdef CONFIG_USER_ONLY | ||
44 | - ((TaskState *)cs->opaque)->swi_errno = err; | ||
45 | -#else | ||
46 | - syscall_err = err; | ||
47 | -#endif | ||
48 | + errno = err; | ||
49 | + set_swi_errno(env, -1); | ||
50 | } | ||
51 | |||
52 | static int arm_semi_open_guestfd; | ||
53 | @@ -XXX,XX +XXX,XX @@ static void arm_semi_open_cb(CPUState *cs, target_ulong ret, target_ulong err) | ||
54 | { | ||
55 | ARMCPU *cpu = ARM_CPU(cs); | ||
56 | CPUARMState *env = &cpu->env; | ||
57 | -#ifdef CONFIG_USER_ONLY | ||
58 | - TaskState *ts = cs->opaque; | ||
59 | -#endif | ||
60 | if (ret == (target_ulong)-1) { | ||
61 | -#ifdef CONFIG_USER_ONLY | ||
62 | - ts->swi_errno = err; | ||
63 | -#else | ||
64 | - syscall_err = err; | ||
65 | -#endif | ||
66 | + errno = err; | ||
67 | + set_swi_errno(env, -1); | ||
68 | dealloc_guestfd(arm_semi_open_guestfd); | ||
69 | } else { | ||
70 | associate_guestfd(arm_semi_open_guestfd, ret); | ||
71 | -- | ||
72 | 2.20.1 | ||
73 | |||
74 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Factor out the implementation of SYS_WRITE via the | ||
2 | new function tables. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20190916141544.17540-9-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/arm-semi.c | 51 ++++++++++++++++++++++++++++--------------- | ||
10 | 1 file changed, 33 insertions(+), 18 deletions(-) | ||
11 | |||
12 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/arm-semi.c | ||
15 | +++ b/target/arm/arm-semi.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, | ||
17 | * setting the guest errno if appropriate. | ||
18 | */ | ||
19 | typedef uint32_t sys_closefn(ARMCPU *cpu, GuestFD *gf); | ||
20 | +typedef uint32_t sys_writefn(ARMCPU *cpu, GuestFD *gf, | ||
21 | + target_ulong buf, uint32_t len); | ||
22 | |||
23 | static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) | ||
24 | { | ||
25 | @@ -XXX,XX +XXX,XX @@ static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) | ||
26 | return set_swi_errno(env, close(gf->hostfd)); | ||
27 | } | ||
28 | |||
29 | +static uint32_t host_writefn(ARMCPU *cpu, GuestFD *gf, | ||
30 | + target_ulong buf, uint32_t len) | ||
31 | +{ | ||
32 | + uint32_t ret; | ||
33 | + CPUARMState *env = &cpu->env; | ||
34 | + char *s = lock_user(VERIFY_READ, buf, len, 1); | ||
35 | + if (!s) { | ||
36 | + /* Return bytes not written on error */ | ||
37 | + return len; | ||
38 | + } | ||
39 | + ret = set_swi_errno(env, write(gf->hostfd, s, len)); | ||
40 | + unlock_user(s, buf, 0); | ||
41 | + if (ret == (uint32_t)-1) { | ||
42 | + ret = 0; | ||
43 | + } | ||
44 | + /* Return bytes not written */ | ||
45 | + return len - ret; | ||
46 | +} | ||
47 | + | ||
48 | static uint32_t gdb_closefn(ARMCPU *cpu, GuestFD *gf) | ||
49 | { | ||
50 | return arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); | ||
51 | } | ||
52 | |||
53 | +static uint32_t gdb_writefn(ARMCPU *cpu, GuestFD *gf, | ||
54 | + target_ulong buf, uint32_t len) | ||
55 | +{ | ||
56 | + arm_semi_syscall_len = len; | ||
57 | + return arm_gdb_syscall(cpu, arm_semi_cb, "write,%x,%x,%x", | ||
58 | + gf->hostfd, buf, len); | ||
59 | +} | ||
60 | + | ||
61 | typedef struct GuestFDFunctions { | ||
62 | sys_closefn *closefn; | ||
63 | + sys_writefn *writefn; | ||
64 | } GuestFDFunctions; | ||
65 | |||
66 | static const GuestFDFunctions guestfd_fns[] = { | ||
67 | [GuestFDHost] = { | ||
68 | .closefn = host_closefn, | ||
69 | + .writefn = host_writefn, | ||
70 | }, | ||
71 | [GuestFDGDB] = { | ||
72 | .closefn = gdb_closefn, | ||
73 | + .writefn = gdb_writefn, | ||
74 | }, | ||
75 | }; | ||
76 | |||
77 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
78 | return set_swi_errno(env, -1); | ||
79 | } | ||
80 | |||
81 | - if (use_gdb_syscalls()) { | ||
82 | - arm_semi_syscall_len = len; | ||
83 | - return arm_gdb_syscall(cpu, arm_semi_cb, "write,%x,%x,%x", | ||
84 | - gf->hostfd, arg1, len); | ||
85 | - } else { | ||
86 | - s = lock_user(VERIFY_READ, arg1, len, 1); | ||
87 | - if (!s) { | ||
88 | - /* Return bytes not written on error */ | ||
89 | - return len; | ||
90 | - } | ||
91 | - ret = set_swi_errno(env, write(gf->hostfd, s, len)); | ||
92 | - unlock_user(s, arg1, 0); | ||
93 | - if (ret == (uint32_t)-1) { | ||
94 | - ret = 0; | ||
95 | - } | ||
96 | - /* Return bytes not written */ | ||
97 | - return len - ret; | ||
98 | - } | ||
99 | + return guestfd_fns[gf->type].writefn(cpu, gf, arg1, len); | ||
100 | case TARGET_SYS_READ: | ||
101 | GET_ARG(0); | ||
102 | GET_ARG(1); | ||
103 | -- | ||
104 | 2.20.1 | ||
105 | |||
106 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Factor out the implementation of SYS_READ via the | ||
2 | new function tables. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
6 | Message-id: 20190916141544.17540-10-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/arm-semi.c | 55 +++++++++++++++++++++++++++---------------- | ||
9 | 1 file changed, 35 insertions(+), 20 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/arm-semi.c | ||
14 | +++ b/target/arm/arm-semi.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, | ||
16 | typedef uint32_t sys_closefn(ARMCPU *cpu, GuestFD *gf); | ||
17 | typedef uint32_t sys_writefn(ARMCPU *cpu, GuestFD *gf, | ||
18 | target_ulong buf, uint32_t len); | ||
19 | +typedef uint32_t sys_readfn(ARMCPU *cpu, GuestFD *gf, | ||
20 | + target_ulong buf, uint32_t len); | ||
21 | |||
22 | static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) | ||
23 | { | ||
24 | @@ -XXX,XX +XXX,XX @@ static uint32_t host_writefn(ARMCPU *cpu, GuestFD *gf, | ||
25 | return len - ret; | ||
26 | } | ||
27 | |||
28 | +static uint32_t host_readfn(ARMCPU *cpu, GuestFD *gf, | ||
29 | + target_ulong buf, uint32_t len) | ||
30 | +{ | ||
31 | + uint32_t ret; | ||
32 | + CPUARMState *env = &cpu->env; | ||
33 | + char *s = lock_user(VERIFY_WRITE, buf, len, 0); | ||
34 | + if (!s) { | ||
35 | + /* return bytes not read */ | ||
36 | + return len; | ||
37 | + } | ||
38 | + do { | ||
39 | + ret = set_swi_errno(env, read(gf->hostfd, s, len)); | ||
40 | + } while (ret == -1 && errno == EINTR); | ||
41 | + unlock_user(s, buf, len); | ||
42 | + if (ret == (uint32_t)-1) { | ||
43 | + ret = 0; | ||
44 | + } | ||
45 | + /* Return bytes not read */ | ||
46 | + return len - ret; | ||
47 | +} | ||
48 | + | ||
49 | static uint32_t gdb_closefn(ARMCPU *cpu, GuestFD *gf) | ||
50 | { | ||
51 | return arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); | ||
52 | @@ -XXX,XX +XXX,XX @@ static uint32_t gdb_writefn(ARMCPU *cpu, GuestFD *gf, | ||
53 | gf->hostfd, buf, len); | ||
54 | } | ||
55 | |||
56 | +static uint32_t gdb_readfn(ARMCPU *cpu, GuestFD *gf, | ||
57 | + target_ulong buf, uint32_t len) | ||
58 | +{ | ||
59 | + arm_semi_syscall_len = len; | ||
60 | + return arm_gdb_syscall(cpu, arm_semi_cb, "read,%x,%x,%x", | ||
61 | + gf->hostfd, buf, len); | ||
62 | +} | ||
63 | + | ||
64 | typedef struct GuestFDFunctions { | ||
65 | sys_closefn *closefn; | ||
66 | sys_writefn *writefn; | ||
67 | + sys_readfn *readfn; | ||
68 | } GuestFDFunctions; | ||
69 | |||
70 | static const GuestFDFunctions guestfd_fns[] = { | ||
71 | [GuestFDHost] = { | ||
72 | .closefn = host_closefn, | ||
73 | .writefn = host_writefn, | ||
74 | + .readfn = host_readfn, | ||
75 | }, | ||
76 | [GuestFDGDB] = { | ||
77 | .closefn = gdb_closefn, | ||
78 | .writefn = gdb_writefn, | ||
79 | + .readfn = gdb_readfn, | ||
80 | }, | ||
81 | }; | ||
82 | |||
83 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
84 | return set_swi_errno(env, -1); | ||
85 | } | ||
86 | |||
87 | - if (use_gdb_syscalls()) { | ||
88 | - arm_semi_syscall_len = len; | ||
89 | - return arm_gdb_syscall(cpu, arm_semi_cb, "read,%x,%x,%x", | ||
90 | - gf->hostfd, arg1, len); | ||
91 | - } else { | ||
92 | - s = lock_user(VERIFY_WRITE, arg1, len, 0); | ||
93 | - if (!s) { | ||
94 | - /* return bytes not read */ | ||
95 | - return len; | ||
96 | - } | ||
97 | - do { | ||
98 | - ret = set_swi_errno(env, read(gf->hostfd, s, len)); | ||
99 | - } while (ret == -1 && errno == EINTR); | ||
100 | - unlock_user(s, arg1, len); | ||
101 | - if (ret == (uint32_t)-1) { | ||
102 | - ret = 0; | ||
103 | - } | ||
104 | - /* Return bytes not read */ | ||
105 | - return len - ret; | ||
106 | - } | ||
107 | + return guestfd_fns[gf->type].readfn(cpu, gf, arg1, len); | ||
108 | case TARGET_SYS_READC: | ||
109 | qemu_log_mask(LOG_UNIMP, "%s: SYS_READC not implemented", __func__); | ||
110 | return 0; | ||
111 | -- | ||
112 | 2.20.1 | ||
113 | |||
114 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Amithash Prasad <amithash@fb.com> | ||
2 | 1 | ||
3 | When WDT_RESTART is written, the data is not the contents | ||
4 | of the WDT_CTRL register. Hence ensure we are looking at | ||
5 | WDT_CTRL to check if bit WDT_CTRL_1MHZ_CLK is set or not. | ||
6 | |||
7 | Signed-off-by: Amithash Prasad <amithash@fb.com> | ||
8 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
9 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
10 | Message-id: 20190925143248.10000-2-clg@kaod.org | ||
11 | [clg: improved Suject prefix ] | ||
12 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
13 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
14 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | --- | ||
17 | hw/watchdog/wdt_aspeed.c | 2 +- | ||
18 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
19 | |||
20 | diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/hw/watchdog/wdt_aspeed.c | ||
23 | +++ b/hw/watchdog/wdt_aspeed.c | ||
24 | @@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, | ||
25 | case WDT_RESTART: | ||
26 | if ((data & 0xFFFF) == WDT_RESTART_MAGIC) { | ||
27 | s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE]; | ||
28 | - aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK)); | ||
29 | + aspeed_wdt_reload(s, !(s->regs[WDT_CTRL] & WDT_CTRL_1MHZ_CLK)); | ||
30 | } | ||
31 | break; | ||
32 | case WDT_CTRL: | ||
33 | -- | ||
34 | 2.20.1 | ||
35 | |||
36 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Cédric Le Goater <clg@kaod.org> | ||
2 | 1 | ||
3 | The most important changes will be on the register range 0x34 - 0x3C | ||
4 | memops. Introduce class read/write operations to handle the | ||
5 | differences between SoCs. | ||
6 | |||
7 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
8 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
9 | Message-id: 20190925143248.10000-5-clg@kaod.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/timer/aspeed_timer.h | 15 +++++ | ||
13 | hw/arm/aspeed_soc.c | 3 +- | ||
14 | hw/timer/aspeed_timer.c | 107 ++++++++++++++++++++++++++++---- | ||
15 | 3 files changed, 113 insertions(+), 12 deletions(-) | ||
16 | |||
17 | diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/include/hw/timer/aspeed_timer.h | ||
20 | +++ b/include/hw/timer/aspeed_timer.h | ||
21 | @@ -XXX,XX +XXX,XX @@ | ||
22 | #define ASPEED_TIMER(obj) \ | ||
23 | OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER); | ||
24 | #define TYPE_ASPEED_TIMER "aspeed.timer" | ||
25 | +#define TYPE_ASPEED_2400_TIMER TYPE_ASPEED_TIMER "-ast2400" | ||
26 | +#define TYPE_ASPEED_2500_TIMER TYPE_ASPEED_TIMER "-ast2500" | ||
27 | + | ||
28 | #define ASPEED_TIMER_NR_TIMERS 8 | ||
29 | |||
30 | typedef struct AspeedTimer { | ||
31 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedTimerCtrlState { | ||
32 | AspeedSCUState *scu; | ||
33 | } AspeedTimerCtrlState; | ||
34 | |||
35 | +#define ASPEED_TIMER_CLASS(klass) \ | ||
36 | + OBJECT_CLASS_CHECK(AspeedTimerClass, (klass), TYPE_ASPEED_TIMER) | ||
37 | +#define ASPEED_TIMER_GET_CLASS(obj) \ | ||
38 | + OBJECT_GET_CLASS(AspeedTimerClass, (obj), TYPE_ASPEED_TIMER) | ||
39 | + | ||
40 | +typedef struct AspeedTimerClass { | ||
41 | + SysBusDeviceClass parent_class; | ||
42 | + | ||
43 | + uint64_t (*read)(AspeedTimerCtrlState *s, hwaddr offset); | ||
44 | + void (*write)(AspeedTimerCtrlState *s, hwaddr offset, uint64_t value); | ||
45 | +} AspeedTimerClass; | ||
46 | + | ||
47 | #endif /* ASPEED_TIMER_H */ | ||
48 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/hw/arm/aspeed_soc.c | ||
51 | +++ b/hw/arm/aspeed_soc.c | ||
52 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | ||
53 | sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc), | ||
54 | TYPE_ASPEED_RTC); | ||
55 | |||
56 | + snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); | ||
57 | sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl), | ||
58 | - sizeof(s->timerctrl), TYPE_ASPEED_TIMER); | ||
59 | + sizeof(s->timerctrl), typename); | ||
60 | object_property_add_const_link(OBJECT(&s->timerctrl), "scu", | ||
61 | OBJECT(&s->scu), &error_abort); | ||
62 | |||
63 | diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c | ||
64 | index XXXXXXX..XXXXXXX 100644 | ||
65 | --- a/hw/timer/aspeed_timer.c | ||
66 | +++ b/hw/timer/aspeed_timer.c | ||
67 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_timer_read(void *opaque, hwaddr offset, unsigned size) | ||
68 | case 0x40 ... 0x8c: /* Timers 5 - 8 */ | ||
69 | value = aspeed_timer_get_value(&s->timers[(offset >> 4) - 1], reg); | ||
70 | break; | ||
71 | - /* Illegal */ | ||
72 | - case 0x38: | ||
73 | - case 0x3C: | ||
74 | default: | ||
75 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | ||
76 | - __func__, offset); | ||
77 | - value = 0; | ||
78 | + value = ASPEED_TIMER_GET_CLASS(s)->read(s, offset); | ||
79 | break; | ||
80 | } | ||
81 | trace_aspeed_timer_read(offset, size, value); | ||
82 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_write(void *opaque, hwaddr offset, uint64_t value, | ||
83 | case 0x40 ... 0x8c: | ||
84 | aspeed_timer_set_value(s, (offset >> TIMER_NR_REGS) - 1, reg, tv); | ||
85 | break; | ||
86 | - /* Illegal */ | ||
87 | - case 0x38: | ||
88 | - case 0x3C: | ||
89 | default: | ||
90 | - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | ||
91 | - __func__, offset); | ||
92 | + ASPEED_TIMER_GET_CLASS(s)->write(s, offset, value); | ||
93 | break; | ||
94 | } | ||
95 | } | ||
96 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_timer_ops = { | ||
97 | .valid.unaligned = false, | ||
98 | }; | ||
99 | |||
100 | +static uint64_t aspeed_2400_timer_read(AspeedTimerCtrlState *s, hwaddr offset) | ||
101 | +{ | ||
102 | + uint64_t value; | ||
103 | + | ||
104 | + switch (offset) { | ||
105 | + case 0x38: | ||
106 | + case 0x3C: | ||
107 | + default: | ||
108 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | ||
109 | + __func__, offset); | ||
110 | + value = 0; | ||
111 | + break; | ||
112 | + } | ||
113 | + return value; | ||
114 | +} | ||
115 | + | ||
116 | +static void aspeed_2400_timer_write(AspeedTimerCtrlState *s, hwaddr offset, | ||
117 | + uint64_t value) | ||
118 | +{ | ||
119 | + switch (offset) { | ||
120 | + case 0x38: | ||
121 | + case 0x3C: | ||
122 | + default: | ||
123 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | ||
124 | + __func__, offset); | ||
125 | + break; | ||
126 | + } | ||
127 | +} | ||
128 | + | ||
129 | +static uint64_t aspeed_2500_timer_read(AspeedTimerCtrlState *s, hwaddr offset) | ||
130 | +{ | ||
131 | + uint64_t value; | ||
132 | + | ||
133 | + switch (offset) { | ||
134 | + case 0x38: | ||
135 | + case 0x3C: | ||
136 | + default: | ||
137 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | ||
138 | + __func__, offset); | ||
139 | + value = 0; | ||
140 | + break; | ||
141 | + } | ||
142 | + return value; | ||
143 | +} | ||
144 | + | ||
145 | +static void aspeed_2500_timer_write(AspeedTimerCtrlState *s, hwaddr offset, | ||
146 | + uint64_t value) | ||
147 | +{ | ||
148 | + switch (offset) { | ||
149 | + case 0x38: | ||
150 | + case 0x3C: | ||
151 | + default: | ||
152 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | ||
153 | + __func__, offset); | ||
154 | + break; | ||
155 | + } | ||
156 | +} | ||
157 | + | ||
158 | static void aspeed_init_one_timer(AspeedTimerCtrlState *s, uint8_t id) | ||
159 | { | ||
160 | AspeedTimer *t = &s->timers[id]; | ||
161 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_timer_info = { | ||
162 | .parent = TYPE_SYS_BUS_DEVICE, | ||
163 | .instance_size = sizeof(AspeedTimerCtrlState), | ||
164 | .class_init = timer_class_init, | ||
165 | + .class_size = sizeof(AspeedTimerClass), | ||
166 | + .abstract = true, | ||
167 | +}; | ||
168 | + | ||
169 | +static void aspeed_2400_timer_class_init(ObjectClass *klass, void *data) | ||
170 | +{ | ||
171 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
172 | + AspeedTimerClass *awc = ASPEED_TIMER_CLASS(klass); | ||
173 | + | ||
174 | + dc->desc = "ASPEED 2400 Timer"; | ||
175 | + awc->read = aspeed_2400_timer_read; | ||
176 | + awc->write = aspeed_2400_timer_write; | ||
177 | +} | ||
178 | + | ||
179 | +static const TypeInfo aspeed_2400_timer_info = { | ||
180 | + .name = TYPE_ASPEED_2400_TIMER, | ||
181 | + .parent = TYPE_ASPEED_TIMER, | ||
182 | + .class_init = aspeed_2400_timer_class_init, | ||
183 | +}; | ||
184 | + | ||
185 | +static void aspeed_2500_timer_class_init(ObjectClass *klass, void *data) | ||
186 | +{ | ||
187 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
188 | + AspeedTimerClass *awc = ASPEED_TIMER_CLASS(klass); | ||
189 | + | ||
190 | + dc->desc = "ASPEED 2500 Timer"; | ||
191 | + awc->read = aspeed_2500_timer_read; | ||
192 | + awc->write = aspeed_2500_timer_write; | ||
193 | +} | ||
194 | + | ||
195 | +static const TypeInfo aspeed_2500_timer_info = { | ||
196 | + .name = TYPE_ASPEED_2500_TIMER, | ||
197 | + .parent = TYPE_ASPEED_TIMER, | ||
198 | + .class_init = aspeed_2500_timer_class_init, | ||
199 | }; | ||
200 | |||
201 | static void aspeed_timer_register_types(void) | ||
202 | { | ||
203 | type_register_static(&aspeed_timer_info); | ||
204 | + type_register_static(&aspeed_2400_timer_info); | ||
205 | + type_register_static(&aspeed_2500_timer_info); | ||
206 | } | ||
207 | |||
208 | type_init(aspeed_timer_register_types) | ||
209 | -- | ||
210 | 2.20.1 | ||
211 | |||
212 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Cédric Le Goater <clg@kaod.org> | ||
2 | 1 | ||
3 | The AST2500 timer has a third control register that is used to | ||
4 | implement a set-to-clear feature for the main control register. | ||
5 | |||
6 | This models the behaviour expected by the AST2500 while maintaining | ||
7 | the same behaviour for the AST2400. | ||
8 | |||
9 | The vmstate version is not increased yet because the structure is | ||
10 | modified again in the following patches. | ||
11 | |||
12 | Based on previous work from Joel Stanley. | ||
13 | |||
14 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
15 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
16 | Message-id: 20190925143248.10000-6-clg@kaod.org | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | --- | ||
19 | include/hw/timer/aspeed_timer.h | 1 + | ||
20 | hw/timer/aspeed_timer.c | 19 +++++++++++++++++++ | ||
21 | 2 files changed, 20 insertions(+) | ||
22 | |||
23 | diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h | ||
24 | index XXXXXXX..XXXXXXX 100644 | ||
25 | --- a/include/hw/timer/aspeed_timer.h | ||
26 | +++ b/include/hw/timer/aspeed_timer.h | ||
27 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedTimerCtrlState { | ||
28 | |||
29 | uint32_t ctrl; | ||
30 | uint32_t ctrl2; | ||
31 | + uint32_t ctrl3; | ||
32 | AspeedTimer timers[ASPEED_TIMER_NR_TIMERS]; | ||
33 | |||
34 | AspeedSCUState *scu; | ||
35 | diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/hw/timer/aspeed_timer.c | ||
38 | +++ b/hw/timer/aspeed_timer.c | ||
39 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_2500_timer_read(AspeedTimerCtrlState *s, hwaddr offset) | ||
40 | |||
41 | switch (offset) { | ||
42 | case 0x38: | ||
43 | + value = s->ctrl3 & BIT(0); | ||
44 | + break; | ||
45 | case 0x3C: | ||
46 | default: | ||
47 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | ||
48 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_2500_timer_read(AspeedTimerCtrlState *s, hwaddr offset) | ||
49 | static void aspeed_2500_timer_write(AspeedTimerCtrlState *s, hwaddr offset, | ||
50 | uint64_t value) | ||
51 | { | ||
52 | + const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF); | ||
53 | + uint8_t command; | ||
54 | + | ||
55 | switch (offset) { | ||
56 | case 0x38: | ||
57 | + command = (value >> 1) & 0xFF; | ||
58 | + if (command == 0xAE) { | ||
59 | + s->ctrl3 = 0x1; | ||
60 | + } else if (command == 0xEA) { | ||
61 | + s->ctrl3 = 0x0; | ||
62 | + } | ||
63 | + break; | ||
64 | case 0x3C: | ||
65 | + if (s->ctrl3 & BIT(0)) { | ||
66 | + aspeed_timer_set_ctrl(s, s->ctrl & ~tv); | ||
67 | + } | ||
68 | + break; | ||
69 | + | ||
70 | default: | ||
71 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", | ||
72 | __func__, offset); | ||
73 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_reset(DeviceState *dev) | ||
74 | } | ||
75 | s->ctrl = 0; | ||
76 | s->ctrl2 = 0; | ||
77 | + s->ctrl3 = 0; | ||
78 | } | ||
79 | |||
80 | static const VMStateDescription vmstate_aspeed_timer = { | ||
81 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_timer_state = { | ||
82 | .fields = (VMStateField[]) { | ||
83 | VMSTATE_UINT32(ctrl, AspeedTimerCtrlState), | ||
84 | VMSTATE_UINT32(ctrl2, AspeedTimerCtrlState), | ||
85 | + VMSTATE_UINT32(ctrl3, AspeedTimerCtrlState), | ||
86 | VMSTATE_STRUCT_ARRAY(timers, AspeedTimerCtrlState, | ||
87 | ASPEED_TIMER_NR_TIMERS, 1, vmstate_aspeed_timer, | ||
88 | AspeedTimer), | ||
89 | -- | ||
90 | 2.20.1 | ||
91 | |||
92 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Cédric Le Goater <clg@kaod.org> | ||
2 | 1 | ||
3 | It cleanups the current models for the Aspeed AST2400 and AST2500 SoCs | ||
4 | and prepares ground for future SoCs. | ||
5 | |||
6 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
7 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
8 | Message-id: 20190925143248.10000-11-clg@kaod.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | include/hw/watchdog/wdt_aspeed.h | 18 ++++- | ||
12 | hw/arm/aspeed_soc.c | 9 ++- | ||
13 | hw/watchdog/wdt_aspeed.c | 122 ++++++++++++++++--------------- | ||
14 | 3 files changed, 86 insertions(+), 63 deletions(-) | ||
15 | |||
16 | diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/include/hw/watchdog/wdt_aspeed.h | ||
19 | +++ b/include/hw/watchdog/wdt_aspeed.h | ||
20 | @@ -XXX,XX +XXX,XX @@ | ||
21 | #define TYPE_ASPEED_WDT "aspeed.wdt" | ||
22 | #define ASPEED_WDT(obj) \ | ||
23 | OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT) | ||
24 | +#define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400" | ||
25 | +#define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500" | ||
26 | |||
27 | #define ASPEED_WDT_REGS_MAX (0x20 / 4) | ||
28 | |||
29 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedWDTState { | ||
30 | |||
31 | AspeedSCUState *scu; | ||
32 | uint32_t pclk_freq; | ||
33 | - uint32_t silicon_rev; | ||
34 | - uint32_t ext_pulse_width_mask; | ||
35 | } AspeedWDTState; | ||
36 | |||
37 | +#define ASPEED_WDT_CLASS(klass) \ | ||
38 | + OBJECT_CLASS_CHECK(AspeedWDTClass, (klass), TYPE_ASPEED_WDT) | ||
39 | +#define ASPEED_WDT_GET_CLASS(obj) \ | ||
40 | + OBJECT_GET_CLASS(AspeedWDTClass, (obj), TYPE_ASPEED_WDT) | ||
41 | + | ||
42 | +typedef struct AspeedWDTClass { | ||
43 | + SysBusDeviceClass parent_class; | ||
44 | + | ||
45 | + uint32_t offset; | ||
46 | + uint32_t ext_pulse_width_mask; | ||
47 | + uint32_t reset_ctrl_reg; | ||
48 | + void (*reset_pulse)(AspeedWDTState *s, uint32_t property); | ||
49 | +} AspeedWDTClass; | ||
50 | + | ||
51 | #endif /* WDT_ASPEED_H */ | ||
52 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/hw/arm/aspeed_soc.c | ||
55 | +++ b/hw/arm/aspeed_soc.c | ||
56 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | ||
57 | "max-ram-size", &error_abort); | ||
58 | |||
59 | for (i = 0; i < sc->info->wdts_num; i++) { | ||
60 | + snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); | ||
61 | sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]), | ||
62 | - sizeof(s->wdt[i]), TYPE_ASPEED_WDT); | ||
63 | - qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev", | ||
64 | - sc->info->silicon_rev); | ||
65 | + sizeof(s->wdt[i]), typename); | ||
66 | object_property_add_const_link(OBJECT(&s->wdt[i]), "scu", | ||
67 | OBJECT(&s->scu), &error_abort); | ||
68 | } | ||
69 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
70 | |||
71 | /* Watch dog */ | ||
72 | for (i = 0; i < sc->info->wdts_num; i++) { | ||
73 | + AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); | ||
74 | + | ||
75 | object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); | ||
76 | if (err) { | ||
77 | error_propagate(errp, err); | ||
78 | return; | ||
79 | } | ||
80 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | ||
81 | - sc->info->memmap[ASPEED_WDT] + i * 0x20); | ||
82 | + sc->info->memmap[ASPEED_WDT] + i * awc->offset); | ||
83 | } | ||
84 | |||
85 | /* Net */ | ||
86 | diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c | ||
87 | index XXXXXXX..XXXXXXX 100644 | ||
88 | --- a/hw/watchdog/wdt_aspeed.c | ||
89 | +++ b/hw/watchdog/wdt_aspeed.c | ||
90 | @@ -XXX,XX +XXX,XX @@ static bool aspeed_wdt_is_enabled(const AspeedWDTState *s) | ||
91 | return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE; | ||
92 | } | ||
93 | |||
94 | -static bool is_ast2500(const AspeedWDTState *s) | ||
95 | -{ | ||
96 | - switch (s->silicon_rev) { | ||
97 | - case AST2500_A0_SILICON_REV: | ||
98 | - case AST2500_A1_SILICON_REV: | ||
99 | - return true; | ||
100 | - case AST2400_A0_SILICON_REV: | ||
101 | - case AST2400_A1_SILICON_REV: | ||
102 | - default: | ||
103 | - break; | ||
104 | - } | ||
105 | - | ||
106 | - return false; | ||
107 | -} | ||
108 | - | ||
109 | static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) | ||
110 | { | ||
111 | AspeedWDTState *s = ASPEED_WDT(opaque); | ||
112 | @@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, | ||
113 | unsigned size) | ||
114 | { | ||
115 | AspeedWDTState *s = ASPEED_WDT(opaque); | ||
116 | + AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s); | ||
117 | bool enable = data & WDT_CTRL_ENABLE; | ||
118 | |||
119 | offset >>= 2; | ||
120 | @@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, | ||
121 | } | ||
122 | break; | ||
123 | case WDT_RESET_WIDTH: | ||
124 | - { | ||
125 | - uint32_t property = data & WDT_POLARITY_MASK; | ||
126 | - | ||
127 | - if (property && is_ast2500(s)) { | ||
128 | - if (property == WDT_ACTIVE_HIGH_MAGIC) { | ||
129 | - s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH; | ||
130 | - } else if (property == WDT_ACTIVE_LOW_MAGIC) { | ||
131 | - s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH; | ||
132 | - } else if (property == WDT_PUSH_PULL_MAGIC) { | ||
133 | - s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL; | ||
134 | - } else if (property == WDT_OPEN_DRAIN_MAGIC) { | ||
135 | - s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL; | ||
136 | - } | ||
137 | + if (awc->reset_pulse) { | ||
138 | + awc->reset_pulse(s, data & WDT_POLARITY_MASK); | ||
139 | } | ||
140 | - s->regs[WDT_RESET_WIDTH] &= ~s->ext_pulse_width_mask; | ||
141 | - s->regs[WDT_RESET_WIDTH] |= data & s->ext_pulse_width_mask; | ||
142 | + s->regs[WDT_RESET_WIDTH] &= ~awc->ext_pulse_width_mask; | ||
143 | + s->regs[WDT_RESET_WIDTH] |= data & awc->ext_pulse_width_mask; | ||
144 | break; | ||
145 | - } | ||
146 | + | ||
147 | case WDT_TIMEOUT_STATUS: | ||
148 | case WDT_TIMEOUT_CLEAR: | ||
149 | qemu_log_mask(LOG_UNIMP, | ||
150 | @@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_reset(DeviceState *dev) | ||
151 | static void aspeed_wdt_timer_expired(void *dev) | ||
152 | { | ||
153 | AspeedWDTState *s = ASPEED_WDT(dev); | ||
154 | + uint32_t reset_ctrl_reg = ASPEED_WDT_GET_CLASS(s)->reset_ctrl_reg; | ||
155 | |||
156 | /* Do not reset on SDRAM controller reset */ | ||
157 | - if (s->scu->regs[SCU_RESET_CONTROL1] & SCU_RESET_SDRAM) { | ||
158 | + if (s->scu->regs[reset_ctrl_reg] & SCU_RESET_SDRAM) { | ||
159 | timer_del(s->timer); | ||
160 | s->regs[WDT_CTRL] = 0; | ||
161 | return; | ||
162 | @@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp) | ||
163 | } | ||
164 | s->scu = ASPEED_SCU(obj); | ||
165 | |||
166 | - if (!is_supported_silicon_rev(s->silicon_rev)) { | ||
167 | - error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, | ||
168 | - s->silicon_rev); | ||
169 | - return; | ||
170 | - } | ||
171 | - | ||
172 | - switch (s->silicon_rev) { | ||
173 | - case AST2400_A0_SILICON_REV: | ||
174 | - case AST2400_A1_SILICON_REV: | ||
175 | - s->ext_pulse_width_mask = 0xff; | ||
176 | - break; | ||
177 | - case AST2500_A0_SILICON_REV: | ||
178 | - case AST2500_A1_SILICON_REV: | ||
179 | - s->ext_pulse_width_mask = 0xfffff; | ||
180 | - break; | ||
181 | - default: | ||
182 | - g_assert_not_reached(); | ||
183 | - } | ||
184 | - | ||
185 | s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev); | ||
186 | |||
187 | /* FIXME: This setting should be derived from the SCU hw strapping | ||
188 | @@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp) | ||
189 | sysbus_init_mmio(sbd, &s->iomem); | ||
190 | } | ||
191 | |||
192 | -static Property aspeed_wdt_properties[] = { | ||
193 | - DEFINE_PROP_UINT32("silicon-rev", AspeedWDTState, silicon_rev, 0), | ||
194 | - DEFINE_PROP_END_OF_LIST(), | ||
195 | -}; | ||
196 | - | ||
197 | static void aspeed_wdt_class_init(ObjectClass *klass, void *data) | ||
198 | { | ||
199 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
200 | |||
201 | + dc->desc = "ASPEED Watchdog Controller"; | ||
202 | dc->realize = aspeed_wdt_realize; | ||
203 | dc->reset = aspeed_wdt_reset; | ||
204 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
205 | dc->vmsd = &vmstate_aspeed_wdt; | ||
206 | - dc->props = aspeed_wdt_properties; | ||
207 | } | ||
208 | |||
209 | static const TypeInfo aspeed_wdt_info = { | ||
210 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_wdt_info = { | ||
211 | .name = TYPE_ASPEED_WDT, | ||
212 | .instance_size = sizeof(AspeedWDTState), | ||
213 | .class_init = aspeed_wdt_class_init, | ||
214 | + .class_size = sizeof(AspeedWDTClass), | ||
215 | + .abstract = true, | ||
216 | +}; | ||
217 | + | ||
218 | +static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data) | ||
219 | +{ | ||
220 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
221 | + AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); | ||
222 | + | ||
223 | + dc->desc = "ASPEED 2400 Watchdog Controller"; | ||
224 | + awc->offset = 0x20; | ||
225 | + awc->ext_pulse_width_mask = 0xff; | ||
226 | + awc->reset_ctrl_reg = SCU_RESET_CONTROL1; | ||
227 | +} | ||
228 | + | ||
229 | +static const TypeInfo aspeed_2400_wdt_info = { | ||
230 | + .name = TYPE_ASPEED_2400_WDT, | ||
231 | + .parent = TYPE_ASPEED_WDT, | ||
232 | + .instance_size = sizeof(AspeedWDTState), | ||
233 | + .class_init = aspeed_2400_wdt_class_init, | ||
234 | +}; | ||
235 | + | ||
236 | +static void aspeed_2500_wdt_reset_pulse(AspeedWDTState *s, uint32_t property) | ||
237 | +{ | ||
238 | + if (property) { | ||
239 | + if (property == WDT_ACTIVE_HIGH_MAGIC) { | ||
240 | + s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH; | ||
241 | + } else if (property == WDT_ACTIVE_LOW_MAGIC) { | ||
242 | + s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH; | ||
243 | + } else if (property == WDT_PUSH_PULL_MAGIC) { | ||
244 | + s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL; | ||
245 | + } else if (property == WDT_OPEN_DRAIN_MAGIC) { | ||
246 | + s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL; | ||
247 | + } | ||
248 | + } | ||
249 | +} | ||
250 | + | ||
251 | +static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data) | ||
252 | +{ | ||
253 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
254 | + AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); | ||
255 | + | ||
256 | + dc->desc = "ASPEED 2500 Watchdog Controller"; | ||
257 | + awc->offset = 0x20; | ||
258 | + awc->ext_pulse_width_mask = 0xfffff; | ||
259 | + awc->reset_ctrl_reg = SCU_RESET_CONTROL1; | ||
260 | + awc->reset_pulse = aspeed_2500_wdt_reset_pulse; | ||
261 | +} | ||
262 | + | ||
263 | +static const TypeInfo aspeed_2500_wdt_info = { | ||
264 | + .name = TYPE_ASPEED_2500_WDT, | ||
265 | + .parent = TYPE_ASPEED_WDT, | ||
266 | + .instance_size = sizeof(AspeedWDTState), | ||
267 | + .class_init = aspeed_2500_wdt_class_init, | ||
268 | }; | ||
269 | |||
270 | static void wdt_aspeed_register_types(void) | ||
271 | { | ||
272 | watchdog_add_model(&model); | ||
273 | type_register_static(&aspeed_wdt_info); | ||
274 | + type_register_static(&aspeed_2400_wdt_info); | ||
275 | + type_register_static(&aspeed_2500_wdt_info); | ||
276 | } | ||
277 | |||
278 | type_init(wdt_aspeed_register_types) | ||
279 | -- | ||
280 | 2.20.1 | ||
281 | |||
282 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Joel Stanley <joel@jms.id.au> | ||
2 | 1 | ||
3 | The AST2600 has four watchdogs, and they each have a 0x40 of registers. | ||
4 | |||
5 | When running as part of an ast2600 system we must check a different | ||
6 | offset for the system reset control register in the SCU. | ||
7 | |||
8 | Signed-off-by: Joel Stanley <joel@jms.id.au> | ||
9 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
10 | Message-id: 20190925143248.10000-12-clg@kaod.org | ||
11 | [clg: - reworked model integration into new object class ] | ||
12 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | include/hw/arm/aspeed_soc.h | 2 +- | ||
16 | include/hw/watchdog/wdt_aspeed.h | 1 + | ||
17 | hw/watchdog/wdt_aspeed.c | 29 +++++++++++++++++++++++++++++ | ||
18 | 3 files changed, 31 insertions(+), 1 deletion(-) | ||
19 | |||
20 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/include/hw/arm/aspeed_soc.h | ||
23 | +++ b/include/hw/arm/aspeed_soc.h | ||
24 | @@ -XXX,XX +XXX,XX @@ | ||
25 | #include "hw/sd/aspeed_sdhci.h" | ||
26 | |||
27 | #define ASPEED_SPIS_NUM 2 | ||
28 | -#define ASPEED_WDTS_NUM 3 | ||
29 | +#define ASPEED_WDTS_NUM 4 | ||
30 | #define ASPEED_CPUS_NUM 2 | ||
31 | #define ASPEED_MACS_NUM 2 | ||
32 | |||
33 | diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/include/hw/watchdog/wdt_aspeed.h | ||
36 | +++ b/include/hw/watchdog/wdt_aspeed.h | ||
37 | @@ -XXX,XX +XXX,XX @@ | ||
38 | OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT) | ||
39 | #define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400" | ||
40 | #define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500" | ||
41 | +#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600" | ||
42 | |||
43 | #define ASPEED_WDT_REGS_MAX (0x20 / 4) | ||
44 | |||
45 | diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/hw/watchdog/wdt_aspeed.c | ||
48 | +++ b/hw/watchdog/wdt_aspeed.c | ||
49 | @@ -XXX,XX +XXX,XX @@ | ||
50 | #define WDT_DRIVE_TYPE_MASK (0xFF << 24) | ||
51 | #define WDT_PUSH_PULL_MAGIC (0xA8 << 24) | ||
52 | #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) | ||
53 | +#define WDT_RESET_MASK1 (0x1c / 4) | ||
54 | |||
55 | #define WDT_TIMEOUT_STATUS (0x10 / 4) | ||
56 | #define WDT_TIMEOUT_CLEAR (0x14 / 4) | ||
57 | |||
58 | #define WDT_RESTART_MAGIC 0x4755 | ||
59 | |||
60 | +#define AST2600_SCU_RESET_CONTROL1 (0x40 / 4) | ||
61 | #define SCU_RESET_CONTROL1 (0x04 / 4) | ||
62 | #define SCU_RESET_SDRAM BIT(0) | ||
63 | |||
64 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) | ||
65 | return s->regs[WDT_CTRL]; | ||
66 | case WDT_RESET_WIDTH: | ||
67 | return s->regs[WDT_RESET_WIDTH]; | ||
68 | + case WDT_RESET_MASK1: | ||
69 | + return s->regs[WDT_RESET_MASK1]; | ||
70 | case WDT_TIMEOUT_STATUS: | ||
71 | case WDT_TIMEOUT_CLEAR: | ||
72 | qemu_log_mask(LOG_UNIMP, | ||
73 | @@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, | ||
74 | s->regs[WDT_RESET_WIDTH] |= data & awc->ext_pulse_width_mask; | ||
75 | break; | ||
76 | |||
77 | + case WDT_RESET_MASK1: | ||
78 | + /* TODO: implement */ | ||
79 | + s->regs[WDT_RESET_MASK1] = data; | ||
80 | + break; | ||
81 | + | ||
82 | case WDT_TIMEOUT_STATUS: | ||
83 | case WDT_TIMEOUT_CLEAR: | ||
84 | qemu_log_mask(LOG_UNIMP, | ||
85 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_2500_wdt_info = { | ||
86 | .class_init = aspeed_2500_wdt_class_init, | ||
87 | }; | ||
88 | |||
89 | +static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data) | ||
90 | +{ | ||
91 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
92 | + AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); | ||
93 | + | ||
94 | + dc->desc = "ASPEED 2600 Watchdog Controller"; | ||
95 | + awc->offset = 0x40; | ||
96 | + awc->ext_pulse_width_mask = 0xfffff; /* TODO */ | ||
97 | + awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1; | ||
98 | + awc->reset_pulse = aspeed_2500_wdt_reset_pulse; | ||
99 | +} | ||
100 | + | ||
101 | +static const TypeInfo aspeed_2600_wdt_info = { | ||
102 | + .name = TYPE_ASPEED_2600_WDT, | ||
103 | + .parent = TYPE_ASPEED_WDT, | ||
104 | + .instance_size = sizeof(AspeedWDTState), | ||
105 | + .class_init = aspeed_2600_wdt_class_init, | ||
106 | +}; | ||
107 | + | ||
108 | static void wdt_aspeed_register_types(void) | ||
109 | { | ||
110 | watchdog_add_model(&model); | ||
111 | type_register_static(&aspeed_wdt_info); | ||
112 | type_register_static(&aspeed_2400_wdt_info); | ||
113 | type_register_static(&aspeed_2500_wdt_info); | ||
114 | + type_register_static(&aspeed_2600_wdt_info); | ||
115 | } | ||
116 | |||
117 | type_init(wdt_aspeed_register_types) | ||
118 | -- | ||
119 | 2.20.1 | ||
120 | |||
121 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Cédric Le Goater <clg@kaod.org> | ||
2 | 1 | ||
3 | AST2600 will use a different encoding for the addresses defined in the | ||
4 | Segment Register. | ||
5 | |||
6 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
7 | Acked-by: Joel Stanley <joel@jms.id.au> | ||
8 | Message-id: 20190925143248.10000-13-clg@kaod.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | include/hw/ssi/aspeed_smc.h | 4 ++++ | ||
12 | hw/ssi/aspeed_smc.c | 45 ++++++++++++++++++++++++------------- | ||
13 | 2 files changed, 34 insertions(+), 15 deletions(-) | ||
14 | |||
15 | diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/hw/ssi/aspeed_smc.h | ||
18 | +++ b/include/hw/ssi/aspeed_smc.h | ||
19 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSMCController { | ||
20 | hwaddr dma_flash_mask; | ||
21 | hwaddr dma_dram_mask; | ||
22 | uint32_t nregs; | ||
23 | + uint32_t (*segment_to_reg)(const struct AspeedSMCState *s, | ||
24 | + const AspeedSegments *seg); | ||
25 | + void (*reg_to_segment)(const struct AspeedSMCState *s, uint32_t reg, | ||
26 | + AspeedSegments *seg); | ||
27 | } AspeedSMCController; | ||
28 | |||
29 | typedef struct AspeedSMCFlash { | ||
30 | diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/hw/ssi/aspeed_smc.c | ||
33 | +++ b/hw/ssi/aspeed_smc.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static const AspeedSegments aspeed_segments_ast2500_spi2[] = { | ||
35 | { 0x38000000, 32 * 1024 * 1024 }, /* start address is readonly */ | ||
36 | { 0x3A000000, 96 * 1024 * 1024 }, /* end address is readonly */ | ||
37 | }; | ||
38 | +static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s, | ||
39 | + const AspeedSegments *seg); | ||
40 | +static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, uint32_t reg, | ||
41 | + AspeedSegments *seg); | ||
42 | |||
43 | static const AspeedSMCController controllers[] = { | ||
44 | { | ||
45 | @@ -XXX,XX +XXX,XX @@ static const AspeedSMCController controllers[] = { | ||
46 | .flash_window_size = 0x6000000, | ||
47 | .has_dma = false, | ||
48 | .nregs = ASPEED_SMC_R_SMC_MAX, | ||
49 | + .segment_to_reg = aspeed_smc_segment_to_reg, | ||
50 | + .reg_to_segment = aspeed_smc_reg_to_segment, | ||
51 | }, { | ||
52 | .name = "aspeed.fmc-ast2400", | ||
53 | .r_conf = R_CONF, | ||
54 | @@ -XXX,XX +XXX,XX @@ static const AspeedSMCController controllers[] = { | ||
55 | .dma_flash_mask = 0x0FFFFFFC, | ||
56 | .dma_dram_mask = 0x1FFFFFFC, | ||
57 | .nregs = ASPEED_SMC_R_MAX, | ||
58 | + .segment_to_reg = aspeed_smc_segment_to_reg, | ||
59 | + .reg_to_segment = aspeed_smc_reg_to_segment, | ||
60 | }, { | ||
61 | .name = "aspeed.spi1-ast2400", | ||
62 | .r_conf = R_SPI_CONF, | ||
63 | @@ -XXX,XX +XXX,XX @@ static const AspeedSMCController controllers[] = { | ||
64 | .flash_window_size = 0x10000000, | ||
65 | .has_dma = false, | ||
66 | .nregs = ASPEED_SMC_R_SPI_MAX, | ||
67 | + .segment_to_reg = aspeed_smc_segment_to_reg, | ||
68 | + .reg_to_segment = aspeed_smc_reg_to_segment, | ||
69 | }, { | ||
70 | .name = "aspeed.fmc-ast2500", | ||
71 | .r_conf = R_CONF, | ||
72 | @@ -XXX,XX +XXX,XX @@ static const AspeedSMCController controllers[] = { | ||
73 | .dma_flash_mask = 0x0FFFFFFC, | ||
74 | .dma_dram_mask = 0x3FFFFFFC, | ||
75 | .nregs = ASPEED_SMC_R_MAX, | ||
76 | + .segment_to_reg = aspeed_smc_segment_to_reg, | ||
77 | + .reg_to_segment = aspeed_smc_reg_to_segment, | ||
78 | }, { | ||
79 | .name = "aspeed.spi1-ast2500", | ||
80 | .r_conf = R_CONF, | ||
81 | @@ -XXX,XX +XXX,XX @@ static const AspeedSMCController controllers[] = { | ||
82 | .flash_window_size = 0x8000000, | ||
83 | .has_dma = false, | ||
84 | .nregs = ASPEED_SMC_R_MAX, | ||
85 | + .segment_to_reg = aspeed_smc_segment_to_reg, | ||
86 | + .reg_to_segment = aspeed_smc_reg_to_segment, | ||
87 | }, { | ||
88 | .name = "aspeed.spi2-ast2500", | ||
89 | .r_conf = R_CONF, | ||
90 | @@ -XXX,XX +XXX,XX @@ static const AspeedSMCController controllers[] = { | ||
91 | .flash_window_size = 0x8000000, | ||
92 | .has_dma = false, | ||
93 | .nregs = ASPEED_SMC_R_MAX, | ||
94 | + .segment_to_reg = aspeed_smc_segment_to_reg, | ||
95 | + .reg_to_segment = aspeed_smc_reg_to_segment, | ||
96 | }, | ||
97 | }; | ||
98 | |||
99 | /* | ||
100 | - * The Segment Register uses a 8MB unit to encode the start address | ||
101 | - * and the end address of the mapping window of a flash SPI slave : | ||
102 | - * | ||
103 | - * | byte 1 | byte 2 | byte 3 | byte 4 | | ||
104 | - * +--------+--------+--------+--------+ | ||
105 | - * | end | start | 0 | 0 | | ||
106 | - * | ||
107 | + * The Segment Registers of the AST2400 and AST2500 have a 8MB | ||
108 | + * unit. The address range of a flash SPI slave is encoded with | ||
109 | + * absolute addresses which should be part of the overall controller | ||
110 | + * window. | ||
111 | */ | ||
112 | -static inline uint32_t aspeed_smc_segment_to_reg(const AspeedSegments *seg) | ||
113 | +static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s, | ||
114 | + const AspeedSegments *seg) | ||
115 | { | ||
116 | uint32_t reg = 0; | ||
117 | reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT; | ||
118 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t aspeed_smc_segment_to_reg(const AspeedSegments *seg) | ||
119 | return reg; | ||
120 | } | ||
121 | |||
122 | -static inline void aspeed_smc_reg_to_segment(uint32_t reg, AspeedSegments *seg) | ||
123 | +static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, | ||
124 | + uint32_t reg, AspeedSegments *seg) | ||
125 | { | ||
126 | seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23; | ||
127 | seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr; | ||
128 | @@ -XXX,XX +XXX,XX @@ static bool aspeed_smc_flash_overlap(const AspeedSMCState *s, | ||
129 | continue; | ||
130 | } | ||
131 | |||
132 | - aspeed_smc_reg_to_segment(s->regs[R_SEG_ADDR0 + i], &seg); | ||
133 | + s->ctrl->reg_to_segment(s, s->regs[R_SEG_ADDR0 + i], &seg); | ||
134 | |||
135 | if (new->addr + new->size > seg.addr && | ||
136 | new->addr < seg.addr + seg.size) { | ||
137 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, | ||
138 | AspeedSMCFlash *fl = &s->flashes[cs]; | ||
139 | AspeedSegments seg; | ||
140 | |||
141 | - aspeed_smc_reg_to_segment(new, &seg); | ||
142 | + s->ctrl->reg_to_segment(s, new, &seg); | ||
143 | |||
144 | /* The start address of CS0 is read-only */ | ||
145 | if (cs == 0 && seg.addr != s->ctrl->flash_window_base) { | ||
146 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, | ||
147 | "%s: Tried to change CS0 start address to 0x%" | ||
148 | HWADDR_PRIx "\n", s->ctrl->name, seg.addr); | ||
149 | seg.addr = s->ctrl->flash_window_base; | ||
150 | - new = aspeed_smc_segment_to_reg(&seg); | ||
151 | + new = s->ctrl->segment_to_reg(s, &seg); | ||
152 | } | ||
153 | |||
154 | /* | ||
155 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, | ||
156 | HWADDR_PRIx "\n", s->ctrl->name, cs, seg.addr + seg.size); | ||
157 | seg.size = s->ctrl->segments[cs].addr + s->ctrl->segments[cs].size - | ||
158 | seg.addr; | ||
159 | - new = aspeed_smc_segment_to_reg(&seg); | ||
160 | + new = s->ctrl->segment_to_reg(s, &seg); | ||
161 | } | ||
162 | |||
163 | /* Keep the segment in the overall flash window */ | ||
164 | @@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl, | ||
165 | const AspeedSMCState *s = fl->controller; | ||
166 | AspeedSegments seg; | ||
167 | |||
168 | - aspeed_smc_reg_to_segment(s->regs[R_SEG_ADDR0 + fl->id], &seg); | ||
169 | + s->ctrl->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->id], &seg); | ||
170 | if ((addr % seg.size) != addr) { | ||
171 | qemu_log_mask(LOG_GUEST_ERROR, | ||
172 | "%s: invalid address 0x%08x for CS%d segment : " | ||
173 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_reset(DeviceState *d) | ||
174 | /* setup default segment register values for all */ | ||
175 | for (i = 0; i < s->ctrl->max_slaves; ++i) { | ||
176 | s->regs[R_SEG_ADDR0 + i] = | ||
177 | - aspeed_smc_segment_to_reg(&s->ctrl->segments[i]); | ||
178 | + s->ctrl->segment_to_reg(s, &s->ctrl->segments[i]); | ||
179 | } | ||
180 | |||
181 | /* HW strapping flash type for FMC controllers */ | ||
182 | -- | ||
183 | 2.20.1 | ||
184 | |||
185 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Cédric Le Goater <clg@kaod.org> | ||
2 | 1 | ||
3 | It prepares ground for register differences between SoCs. | ||
4 | |||
5 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
6 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
7 | Message-id: 20190925143248.10000-16-clg@kaod.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | include/hw/i2c/aspeed_i2c.h | 15 ++++++++++ | ||
11 | hw/arm/aspeed_soc.c | 3 +- | ||
12 | hw/i2c/aspeed_i2c.c | 60 ++++++++++++++++++++++++++++++++----- | ||
13 | 3 files changed, 69 insertions(+), 9 deletions(-) | ||
14 | |||
15 | diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/hw/i2c/aspeed_i2c.h | ||
18 | +++ b/include/hw/i2c/aspeed_i2c.h | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | #include "hw/sysbus.h" | ||
21 | |||
22 | #define TYPE_ASPEED_I2C "aspeed.i2c" | ||
23 | +#define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400" | ||
24 | +#define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500" | ||
25 | #define ASPEED_I2C(obj) \ | ||
26 | OBJECT_CHECK(AspeedI2CState, (obj), TYPE_ASPEED_I2C) | ||
27 | |||
28 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedI2CState { | ||
29 | AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES]; | ||
30 | } AspeedI2CState; | ||
31 | |||
32 | +#define ASPEED_I2C_CLASS(klass) \ | ||
33 | + OBJECT_CLASS_CHECK(AspeedI2CClass, (klass), TYPE_ASPEED_I2C) | ||
34 | +#define ASPEED_I2C_GET_CLASS(obj) \ | ||
35 | + OBJECT_GET_CLASS(AspeedI2CClass, (obj), TYPE_ASPEED_I2C) | ||
36 | + | ||
37 | +typedef struct AspeedI2CClass { | ||
38 | + SysBusDeviceClass parent_class; | ||
39 | + | ||
40 | + uint8_t num_busses; | ||
41 | + uint8_t reg_size; | ||
42 | + uint8_t gap; | ||
43 | +} AspeedI2CClass; | ||
44 | + | ||
45 | I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr); | ||
46 | |||
47 | #endif /* ASPEED_I2C_H */ | ||
48 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/hw/arm/aspeed_soc.c | ||
51 | +++ b/hw/arm/aspeed_soc.c | ||
52 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | ||
53 | object_property_add_const_link(OBJECT(&s->timerctrl), "scu", | ||
54 | OBJECT(&s->scu), &error_abort); | ||
55 | |||
56 | + snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); | ||
57 | sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c), | ||
58 | - TYPE_ASPEED_I2C); | ||
59 | + typename); | ||
60 | |||
61 | snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); | ||
62 | sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc), | ||
63 | diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c | ||
64 | index XXXXXXX..XXXXXXX 100644 | ||
65 | --- a/hw/i2c/aspeed_i2c.c | ||
66 | +++ b/hw/i2c/aspeed_i2c.c | ||
67 | @@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_reset(DeviceState *dev) | ||
68 | { | ||
69 | int i; | ||
70 | AspeedI2CState *s = ASPEED_I2C(dev); | ||
71 | + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); | ||
72 | |||
73 | s->intr_status = 0; | ||
74 | |||
75 | - for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) { | ||
76 | + for (i = 0; i < aic->num_busses; i++) { | ||
77 | s->busses[i].intr_ctrl = 0; | ||
78 | s->busses[i].intr_status = 0; | ||
79 | s->busses[i].cmd = 0; | ||
80 | @@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_reset(DeviceState *dev) | ||
81 | } | ||
82 | |||
83 | /* | ||
84 | - * Address Definitions | ||
85 | + * Address Definitions (AST2400 and AST2500) | ||
86 | * | ||
87 | * 0x000 ... 0x03F: Global Register | ||
88 | * 0x040 ... 0x07F: Device 1 | ||
89 | @@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp) | ||
90 | int i; | ||
91 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
92 | AspeedI2CState *s = ASPEED_I2C(dev); | ||
93 | + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); | ||
94 | |||
95 | sysbus_init_irq(sbd, &s->irq); | ||
96 | memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s, | ||
97 | "aspeed.i2c", 0x1000); | ||
98 | sysbus_init_mmio(sbd, &s->iomem); | ||
99 | |||
100 | - for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) { | ||
101 | - char name[16]; | ||
102 | - int offset = i < 7 ? 1 : 5; | ||
103 | + for (i = 0; i < aic->num_busses; i++) { | ||
104 | + char name[32]; | ||
105 | + int offset = i < aic->gap ? 1 : 5; | ||
106 | snprintf(name, sizeof(name), "aspeed.i2c.%d", i); | ||
107 | s->busses[i].controller = s; | ||
108 | s->busses[i].id = i; | ||
109 | s->busses[i].bus = i2c_init_bus(dev, name); | ||
110 | memory_region_init_io(&s->busses[i].mr, OBJECT(dev), | ||
111 | - &aspeed_i2c_bus_ops, &s->busses[i], name, 0x40); | ||
112 | - memory_region_add_subregion(&s->iomem, 0x40 * (i + offset), | ||
113 | + &aspeed_i2c_bus_ops, &s->busses[i], name, | ||
114 | + aic->reg_size); | ||
115 | + memory_region_add_subregion(&s->iomem, aic->reg_size * (i + offset), | ||
116 | &s->busses[i].mr); | ||
117 | } | ||
118 | } | ||
119 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_i2c_info = { | ||
120 | .parent = TYPE_SYS_BUS_DEVICE, | ||
121 | .instance_size = sizeof(AspeedI2CState), | ||
122 | .class_init = aspeed_i2c_class_init, | ||
123 | + .class_size = sizeof(AspeedI2CClass), | ||
124 | + .abstract = true, | ||
125 | +}; | ||
126 | + | ||
127 | +static void aspeed_2400_i2c_class_init(ObjectClass *klass, void *data) | ||
128 | +{ | ||
129 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
130 | + AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); | ||
131 | + | ||
132 | + dc->desc = "ASPEED 2400 I2C Controller"; | ||
133 | + | ||
134 | + aic->num_busses = 14; | ||
135 | + aic->reg_size = 0x40; | ||
136 | + aic->gap = 7; | ||
137 | +} | ||
138 | + | ||
139 | +static const TypeInfo aspeed_2400_i2c_info = { | ||
140 | + .name = TYPE_ASPEED_2400_I2C, | ||
141 | + .parent = TYPE_ASPEED_I2C, | ||
142 | + .class_init = aspeed_2400_i2c_class_init, | ||
143 | +}; | ||
144 | + | ||
145 | +static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data) | ||
146 | +{ | ||
147 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
148 | + AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); | ||
149 | + | ||
150 | + dc->desc = "ASPEED 2500 I2C Controller"; | ||
151 | + | ||
152 | + aic->num_busses = 14; | ||
153 | + aic->reg_size = 0x40; | ||
154 | + aic->gap = 7; | ||
155 | +} | ||
156 | + | ||
157 | +static const TypeInfo aspeed_2500_i2c_info = { | ||
158 | + .name = TYPE_ASPEED_2500_I2C, | ||
159 | + .parent = TYPE_ASPEED_I2C, | ||
160 | + .class_init = aspeed_2500_i2c_class_init, | ||
161 | }; | ||
162 | |||
163 | static void aspeed_i2c_register_types(void) | ||
164 | { | ||
165 | type_register_static(&aspeed_i2c_info); | ||
166 | + type_register_static(&aspeed_2400_i2c_info); | ||
167 | + type_register_static(&aspeed_2500_i2c_info); | ||
168 | } | ||
169 | |||
170 | type_init(aspeed_i2c_register_types) | ||
171 | @@ -XXX,XX +XXX,XX @@ type_init(aspeed_i2c_register_types) | ||
172 | I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr) | ||
173 | { | ||
174 | AspeedI2CState *s = ASPEED_I2C(dev); | ||
175 | + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); | ||
176 | I2CBus *bus = NULL; | ||
177 | |||
178 | - if (busnr >= 0 && busnr < ASPEED_I2C_NR_BUSSES) { | ||
179 | + if (busnr >= 0 && busnr < aic->num_busses) { | ||
180 | bus = s->busses[busnr].bus; | ||
181 | } | ||
182 | |||
183 | -- | ||
184 | 2.20.1 | ||
185 | |||
186 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Joel Stanley <joel@jms.id.au> | ||
2 | 1 | ||
3 | To support the ast2600's four MACs allow SoCs to specify the number | ||
4 | they have, and create that many. | ||
5 | |||
6 | Signed-off-by: Joel Stanley <joel@jms.id.au> | ||
7 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
8 | Message-id: 20190925143248.10000-22-clg@kaod.org | ||
9 | [clg: - included a check on sc->macs_num when realizing the macs | ||
10 | - included interrupt definitions for the AST2600 ] | ||
11 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | include/hw/arm/aspeed_soc.h | 5 ++++- | ||
15 | hw/arm/aspeed_ast2600.c | 10 ++++++++-- | ||
16 | hw/arm/aspeed_soc.c | 6 ++++-- | ||
17 | 3 files changed, 16 insertions(+), 5 deletions(-) | ||
18 | |||
19 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/include/hw/arm/aspeed_soc.h | ||
22 | +++ b/include/hw/arm/aspeed_soc.h | ||
23 | @@ -XXX,XX +XXX,XX @@ | ||
24 | #define ASPEED_SPIS_NUM 2 | ||
25 | #define ASPEED_WDTS_NUM 4 | ||
26 | #define ASPEED_CPUS_NUM 2 | ||
27 | -#define ASPEED_MACS_NUM 2 | ||
28 | +#define ASPEED_MACS_NUM 4 | ||
29 | |||
30 | typedef struct AspeedSoCState { | ||
31 | /*< private >*/ | ||
32 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCClass { | ||
33 | uint64_t sram_size; | ||
34 | int spis_num; | ||
35 | int wdts_num; | ||
36 | + int macs_num; | ||
37 | const int *irqmap; | ||
38 | const hwaddr *memmap; | ||
39 | uint32_t num_cpus; | ||
40 | @@ -XXX,XX +XXX,XX @@ enum { | ||
41 | ASPEED_I2C, | ||
42 | ASPEED_ETH1, | ||
43 | ASPEED_ETH2, | ||
44 | + ASPEED_ETH3, | ||
45 | + ASPEED_ETH4, | ||
46 | ASPEED_SDRAM, | ||
47 | ASPEED_XDMA, | ||
48 | }; | ||
49 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/hw/arm/aspeed_ast2600.c | ||
52 | +++ b/hw/arm/aspeed_ast2600.c | ||
53 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { | ||
54 | [ASPEED_SPI1] = 0x1E630000, | ||
55 | [ASPEED_SPI2] = 0x1E641000, | ||
56 | [ASPEED_ETH1] = 0x1E660000, | ||
57 | + [ASPEED_ETH3] = 0x1E670000, | ||
58 | [ASPEED_ETH2] = 0x1E680000, | ||
59 | + [ASPEED_ETH4] = 0x1E690000, | ||
60 | [ASPEED_VIC] = 0x1E6C0000, | ||
61 | [ASPEED_SDMC] = 0x1E6E0000, | ||
62 | [ASPEED_SCU] = 0x1E6E2000, | ||
63 | @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = { | ||
64 | [ASPEED_I2C] = 110, /* 110 -> 125 */ | ||
65 | [ASPEED_ETH1] = 2, | ||
66 | [ASPEED_ETH2] = 3, | ||
67 | + [ASPEED_ETH3] = 32, | ||
68 | + [ASPEED_ETH4] = 33, | ||
69 | + | ||
70 | }; | ||
71 | |||
72 | static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) | ||
73 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj) | ||
74 | OBJECT(&s->scu), &error_abort); | ||
75 | } | ||
76 | |||
77 | - for (i = 0; i < ASPEED_MACS_NUM; i++) { | ||
78 | + for (i = 0; i < sc->macs_num; i++) { | ||
79 | sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]), | ||
80 | sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); | ||
81 | } | ||
82 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | ||
83 | } | ||
84 | |||
85 | /* Net */ | ||
86 | - for (i = 0; i < nb_nics; i++) { | ||
87 | + for (i = 0; i < nb_nics && i < sc->macs_num; i++) { | ||
88 | qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]); | ||
89 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", | ||
90 | &err); | ||
91 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) | ||
92 | sc->sram_size = 0x10000; | ||
93 | sc->spis_num = 2; | ||
94 | sc->wdts_num = 4; | ||
95 | + sc->macs_num = 4; | ||
96 | sc->irqmap = aspeed_soc_ast2600_irqmap; | ||
97 | sc->memmap = aspeed_soc_ast2600_memmap; | ||
98 | sc->num_cpus = 2; | ||
99 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
100 | index XXXXXXX..XXXXXXX 100644 | ||
101 | --- a/hw/arm/aspeed_soc.c | ||
102 | +++ b/hw/arm/aspeed_soc.c | ||
103 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | ||
104 | OBJECT(&s->scu), &error_abort); | ||
105 | } | ||
106 | |||
107 | - for (i = 0; i < ASPEED_MACS_NUM; i++) { | ||
108 | + for (i = 0; i < sc->macs_num; i++) { | ||
109 | sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]), | ||
110 | sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); | ||
111 | } | ||
112 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
113 | } | ||
114 | |||
115 | /* Net */ | ||
116 | - for (i = 0; i < nb_nics; i++) { | ||
117 | + for (i = 0; i < nb_nics && i < sc->macs_num; i++) { | ||
118 | qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]); | ||
119 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", | ||
120 | &err); | ||
121 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) | ||
122 | sc->sram_size = 0x8000; | ||
123 | sc->spis_num = 1; | ||
124 | sc->wdts_num = 2; | ||
125 | + sc->macs_num = 2; | ||
126 | sc->irqmap = aspeed_soc_ast2400_irqmap; | ||
127 | sc->memmap = aspeed_soc_ast2400_memmap; | ||
128 | sc->num_cpus = 1; | ||
129 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) | ||
130 | sc->sram_size = 0x9000; | ||
131 | sc->spis_num = 2; | ||
132 | sc->wdts_num = 3; | ||
133 | + sc->macs_num = 2; | ||
134 | sc->irqmap = aspeed_soc_ast2500_irqmap; | ||
135 | sc->memmap = aspeed_soc_ast2500_memmap; | ||
136 | sc->num_cpus = 1; | ||
137 | -- | ||
138 | 2.20.1 | ||
139 | |||
140 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Joel Stanley <joel@jms.id.au> | ||
2 | 1 | ||
3 | Signed-off-by: Joel Stanley <joel@jms.id.au> | ||
4 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
5 | Message-id: 20190925143248.10000-24-clg@kaod.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | include/hw/arm/aspeed_soc.h | 1 + | ||
9 | hw/arm/aspeed_ast2600.c | 5 +++++ | ||
10 | hw/arm/aspeed_soc.c | 6 ++++++ | ||
11 | 3 files changed, 12 insertions(+) | ||
12 | |||
13 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/include/hw/arm/aspeed_soc.h | ||
16 | +++ b/include/hw/arm/aspeed_soc.h | ||
17 | @@ -XXX,XX +XXX,XX @@ enum { | ||
18 | ASPEED_SDMC, | ||
19 | ASPEED_SCU, | ||
20 | ASPEED_ADC, | ||
21 | + ASPEED_VIDEO, | ||
22 | ASPEED_SRAM, | ||
23 | ASPEED_SDHCI, | ||
24 | ASPEED_GPIO, | ||
25 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/hw/arm/aspeed_ast2600.c | ||
28 | +++ b/hw/arm/aspeed_ast2600.c | ||
29 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { | ||
30 | [ASPEED_SCU] = 0x1E6E2000, | ||
31 | [ASPEED_XDMA] = 0x1E6E7000, | ||
32 | [ASPEED_ADC] = 0x1E6E9000, | ||
33 | + [ASPEED_VIDEO] = 0x1E700000, | ||
34 | [ASPEED_SDHCI] = 0x1E740000, | ||
35 | [ASPEED_GPIO] = 0x1E780000, | ||
36 | [ASPEED_GPIO_1_8V] = 0x1E780800, | ||
37 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | ||
38 | create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], | ||
39 | ASPEED_SOC_IOMEM_SIZE); | ||
40 | |||
41 | + /* Video engine stub */ | ||
42 | + create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO], | ||
43 | + 0x1000); | ||
44 | + | ||
45 | if (s->num_cpus > sc->num_cpus) { | ||
46 | warn_report("%s: invalid number of CPUs %d, using default %d", | ||
47 | sc->name, s->num_cpus, sc->num_cpus); | ||
48 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/hw/arm/aspeed_soc.c | ||
51 | +++ b/hw/arm/aspeed_soc.c | ||
52 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2400_memmap[] = { | ||
53 | [ASPEED_SDMC] = 0x1E6E0000, | ||
54 | [ASPEED_SCU] = 0x1E6E2000, | ||
55 | [ASPEED_XDMA] = 0x1E6E7000, | ||
56 | + [ASPEED_VIDEO] = 0x1E700000, | ||
57 | [ASPEED_ADC] = 0x1E6E9000, | ||
58 | [ASPEED_SRAM] = 0x1E720000, | ||
59 | [ASPEED_SDHCI] = 0x1E740000, | ||
60 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2500_memmap[] = { | ||
61 | [ASPEED_SCU] = 0x1E6E2000, | ||
62 | [ASPEED_XDMA] = 0x1E6E7000, | ||
63 | [ASPEED_ADC] = 0x1E6E9000, | ||
64 | + [ASPEED_VIDEO] = 0x1E700000, | ||
65 | [ASPEED_SRAM] = 0x1E720000, | ||
66 | [ASPEED_SDHCI] = 0x1E740000, | ||
67 | [ASPEED_GPIO] = 0x1E780000, | ||
68 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
69 | create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], | ||
70 | ASPEED_SOC_IOMEM_SIZE); | ||
71 | |||
72 | + /* Video engine stub */ | ||
73 | + create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO], | ||
74 | + 0x1000); | ||
75 | + | ||
76 | if (s->num_cpus > sc->num_cpus) { | ||
77 | warn_report("%s: invalid number of CPUs %d, using default %d", | ||
78 | sc->name, s->num_cpus, sc->num_cpus); | ||
79 | -- | ||
80 | 2.20.1 | ||
81 | |||
82 | diff view generated by jsdifflib |