hw/i386/intel_iommu.c | 12 ++++++++---- hw/i386/intel_iommu_internal.h | 17 +++++++++++++---- 2 files changed, 21 insertions(+), 8 deletions(-)
From: "Zhang, Qi" <qi1.zhang@intel.com>
When dt is supported, TM field should not be Reserved(0).
Refer to VT-d Spec 9.8
Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
Signed-off-by: Qi, Yadong <yadong.qi@intel.com>
---
hw/i386/intel_iommu.c | 12 ++++++++----
hw/i386/intel_iommu_internal.h | 17 +++++++++++++----
2 files changed, 21 insertions(+), 8 deletions(-)
---
Changelog V2:
move dt_supported flag to VTD_SPTE_PAGE_LX_RSVD_MASK and VTD_SPTE_LPAGE_LX_RSVD_MASK
Changelog V3:
based on the change to split the arrays into two ones
Changelog V4:
style error check
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index a118efaeaf..d62604ece3 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3549,15 +3549,19 @@ static void vtd_init(IntelIOMMUState *s)
* Rsvd field masks for spte
*/
vtd_spte_rsvd[0] = ~0ULL;
- vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
vtd_spte_rsvd_large[0] = ~0ULL;
- vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
- vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
+ vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
+ vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
vtd_spte_rsvd_large[4] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
if (x86_iommu_ir_supported(x86_iommu)) {
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index c1235a7063..3a839a8925 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -387,7 +387,9 @@ typedef union VTDInvDesc VTDInvDesc;
#define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8
/* Rsvd field masks for spte */
-#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \
+#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
#define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
@@ -395,11 +397,17 @@ typedef union VTDInvDesc VTDInvDesc;
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
#define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
(0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw) \
+#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \
+#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \
+#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
#define VTD_SPTE_LPAGE_L4_RSVD_MASK(aw) \
(0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
@@ -506,5 +514,6 @@ typedef struct VTDRootEntry VTDRootEntry;
#define VTD_SL_W (1ULL << 1)
#define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))
#define VTD_SL_IGN_COM 0xbff0000000000000ULL
+#define VTD_SL_TM (1ULL << 62)
#endif
--
2.20.1
On Mon, Sep 30, 2019 at 01:04:51PM +0800, qi1.zhang@intel.com wrote: > From: "Zhang, Qi" <qi1.zhang@intel.com> > > When dt is supported, TM field should not be Reserved(0). > > Refer to VT-d Spec 9.8 > > Signed-off-by: Zhang, Qi <qi1.zhang@intel.com> > Signed-off-by: Qi, Yadong <yadong.qi@intel.com> I am guessing this is really a 2 patch series right? So you need to format it as such with git format-patch --cover-letter --thread=shallow > --- > hw/i386/intel_iommu.c | 12 ++++++++---- > hw/i386/intel_iommu_internal.h | 17 +++++++++++++---- > 2 files changed, 21 insertions(+), 8 deletions(-) > --- > Changelog V2: > move dt_supported flag to VTD_SPTE_PAGE_LX_RSVD_MASK and VTD_SPTE_LPAGE_LX_RSVD_MASK > Changelog V3: > based on the change to split the arrays into two ones > Changelog V4: > style error check > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index a118efaeaf..d62604ece3 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -3549,15 +3549,19 @@ static void vtd_init(IntelIOMMUState *s) > * Rsvd field masks for spte > */ > vtd_spte_rsvd[0] = ~0ULL; > - vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits); > + vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits, > + x86_iommu->dt_supported); > vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); > vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); > vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); > > vtd_spte_rsvd_large[0] = ~0ULL; > - vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits); > - vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits); > - vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits); > + vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits, > + x86_iommu->dt_supported); > + vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits, > + x86_iommu->dt_supported); > + vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, > + x86_iommu->dt_supported); > vtd_spte_rsvd_large[4] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits); > > if (x86_iommu_ir_supported(x86_iommu)) { > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h > index c1235a7063..3a839a8925 100644 > --- a/hw/i386/intel_iommu_internal.h > +++ b/hw/i386/intel_iommu_internal.h > @@ -387,7 +387,9 @@ typedef union VTDInvDesc VTDInvDesc; > #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8 > > /* Rsvd field masks for spte */ > -#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \ > +#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \ > + dt_supported ? \ > + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ > (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > #define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \ > (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > @@ -395,11 +397,17 @@ typedef union VTDInvDesc VTDInvDesc; > (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > #define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \ > (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > -#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw) \ > +#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw, dt_supported) \ > + dt_supported ? \ > + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ > (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > -#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \ > +#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \ > + dt_supported ? \ > + (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ > (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > -#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \ > +#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \ > + dt_supported ? \ > + (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ > (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > #define VTD_SPTE_LPAGE_L4_RSVD_MASK(aw) \ > (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > @@ -506,5 +514,6 @@ typedef struct VTDRootEntry VTDRootEntry; > #define VTD_SL_W (1ULL << 1) > #define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw)) > #define VTD_SL_IGN_COM 0xbff0000000000000ULL > +#define VTD_SL_TM (1ULL << 62) > > #endif > -- > 2.20.1
Thank you! I formatted the patch with cover-letter and submitted them again. > -----Original Message----- > From: Michael S. Tsirkin <mst@redhat.com> > Sent: Sunday, October 6, 2019 5:50 AM > To: Zhang, Qi1 <qi1.zhang@intel.com> > Cc: qemu-devel@nongnu.org; marcel.apfelbaum@gmail.com; > pbonzini@redhat.com; rth@twiddle.net; ehabkost@redhat.com; Qi, Yadong > <yadong.qi@intel.com> > Subject: Re: [PATCH v4] intel_iommu: TM field should not be in reserved bits > > On Mon, Sep 30, 2019 at 01:04:51PM +0800, qi1.zhang@intel.com wrote: > > From: "Zhang, Qi" <qi1.zhang@intel.com> > > > > When dt is supported, TM field should not be Reserved(0). > > > > Refer to VT-d Spec 9.8 > > > > Signed-off-by: Zhang, Qi <qi1.zhang@intel.com> > > Signed-off-by: Qi, Yadong <yadong.qi@intel.com> > > I am guessing this is really a 2 patch series right? > So you need to format it as such with > git format-patch --cover-letter --thread=shallow > > > --- > > hw/i386/intel_iommu.c | 12 ++++++++---- > > hw/i386/intel_iommu_internal.h | 17 +++++++++++++---- > > 2 files changed, 21 insertions(+), 8 deletions(-) > > --- > > Changelog V2: > > move dt_supported flag to VTD_SPTE_PAGE_LX_RSVD_MASK and > > VTD_SPTE_LPAGE_LX_RSVD_MASK Changelog V3: > > based on the change to split the arrays into two ones Changelog V4: > > style error check > > > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index > > a118efaeaf..d62604ece3 100644 > > --- a/hw/i386/intel_iommu.c > > +++ b/hw/i386/intel_iommu.c > > @@ -3549,15 +3549,19 @@ static void vtd_init(IntelIOMMUState *s) > > * Rsvd field masks for spte > > */ > > vtd_spte_rsvd[0] = ~0ULL; > > - vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits); > > + vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits, > > + > > + x86_iommu->dt_supported); > > vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); > > vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); > > vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); > > > > vtd_spte_rsvd_large[0] = ~0ULL; > > - vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s- > >aw_bits); > > - vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s- > >aw_bits); > > - vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s- > >aw_bits); > > + vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s- > >aw_bits, > > + x86_iommu->dt_supported); > > + vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s- > >aw_bits, > > + x86_iommu->dt_supported); > > + vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s- > >aw_bits, > > + > > + x86_iommu->dt_supported); > > vtd_spte_rsvd_large[4] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s- > >aw_bits); > > > > if (x86_iommu_ir_supported(x86_iommu)) { diff --git > > a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h > > index c1235a7063..3a839a8925 100644 > > --- a/hw/i386/intel_iommu_internal.h > > +++ b/hw/i386/intel_iommu_internal.h > > @@ -387,7 +387,9 @@ typedef union VTDInvDesc VTDInvDesc; #define > > VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8 > > > > /* Rsvd field masks for spte */ > > -#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \ > > +#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \ > > + dt_supported ? \ > > + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | > VTD_SL_TM)) > > +: \ > > (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) #define > > VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \ > > (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) @@ - > 395,11 > > +397,17 @@ typedef union VTDInvDesc VTDInvDesc; > > (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) #define > > VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \ > > (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) -#define > > VTD_SPTE_LPAGE_L1_RSVD_MASK(aw) \ > > +#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw, dt_supported) \ > > + dt_supported ? \ > > + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | > VTD_SL_TM)) > > +: \ > > (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) -#define > > VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \ > > +#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \ > > + dt_supported ? \ > > + (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | > > +VTD_SL_TM)) : \ > > (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) - > #define > > VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \ > > +#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \ > > + dt_supported ? \ > > + (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | > > +VTD_SL_TM)) : \ > > (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > > #define VTD_SPTE_LPAGE_L4_RSVD_MASK(aw) \ > > (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) @@ - > 506,5 > > +514,6 @@ typedef struct VTDRootEntry VTDRootEntry; > > #define VTD_SL_W (1ULL << 1) > > #define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & > VTD_HAW_MASK(aw)) > > #define VTD_SL_IGN_COM 0xbff0000000000000ULL > > +#define VTD_SL_TM (1ULL << 62) > > > > #endif > > -- > > 2.20.1
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