Hi; here's the first target-arm pullreq for the 8.1 cycle.

Nothing particularly huge in here, just the various things

that had accumulated during the freeze.

The following changes since commit 2d82c32b2ceaca3dc3da5e36e10976f34bfcb598:

Open 8.1 development tree (2023-04-20 10:05:25 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230420

for you to fetch changes up to 1ed1f338520cda0574b7e04f5e8e85e049740548:

arm/mcimx7d-sabre: Set fec2-phy-connected property to false (2023-04-20 10:46:43 +0100)

* hw/arm: Fix some typos in comments (most found by codespell)

* exynos: Fix out-of-bounds access in exynos4210_gcomp_find debug printf

* Orangepi-PC, Cubieboard: add Allwinner WDT watchdog emulation

* tests/avocado: Add reboot tests to Cubieboard

* hw/timer/imx_epit: Fix bugs in timer limit checking

* target/arm: Remove KVM AArch32 CPU definitions

* hw/arm/virt: Restrict Cortex-A7 check to TCG

* target/arm: Initialize debug capabilities only once

* target/arm: Implement FEAT_PAN3

* docs/devel/kconfig.rst: Fix incorrect markup

* target/arm: Report pauth information to gdb as 'pauth_v2'

* mcimxd7-sabre, mcimx6ul-evk: Correctly model the way the PHY

on the second ethernet device must be configured via the

first one

Akihiko Odaki (1):

target/arm: Initialize debug capabilities only once

Axel Heider (2):

hw/timer/imx_epit: don't shadow variable

hw/timer/imx_epit: fix limit check

Feng Jiang (1):

exynos: Fix out-of-bounds access in exynos4210_gcomp_find debug printf

Guenter Roeck (5):

hw/net/imx_fec: Support two Ethernet interfaces connected to single MDIO bus

fsl-imx6ul: Add fec[12]-phy-connected properties

arm/mcimx6ul-evk: Set fec1-phy-connected property to false

fsl-imx7: Add fec[12]-phy-connected properties

arm/mcimx7d-sabre: Set fec2-phy-connected property to false

Peter Maydell (5):

target/arm: Pass ARMMMUFaultInfo to merge_syn_data_abort()

target/arm: Don't set ISV when reporting stage 1 faults in ESR_EL2

target/arm: Implement FEAT_PAN3

docs/devel/kconfig.rst: Fix incorrect markup

target/arm: Report pauth information to gdb as 'pauth_v2'

From: Stefan Weil <sw@weilnetz.de>

Signed-off-by: Stefan Weil <sw@weilnetz.de>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Message-id: 20230409200526.1156456-1-sw@weilnetz.de

hw/arm/exynos4210.c | 4 ++--

hw/arm/musicpal.c | 2 +-

hw/arm/omap1.c | 2 +-

hw/arm/omap2.c | 2 +-

hw/arm/virt-acpi-build.c | 2 +-

hw/arm/virt.c | 2 +-

hw/arm/xlnx-versal-virt.c | 2 +-

hw/arm/Kconfig | 2 +-

8 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c

--- a/hw/arm/exynos4210.c

+++ b/hw/arm/exynos4210.c

@@ -XXX,XX +XXX,XX @@ static int mapline_size(const int *mapline)

/*

* Initialize board IRQs.

- * These IRQs contain splitted Int/External Combiner and External Gic IRQs.

+ * These IRQs contain split Int/External Combiner and External Gic IRQs.

*/

static void exynos4210_init_board_irqs(Exynos4210State *s)

{

@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)

* - SDMA

* - ADMA2

*

- * As this part of the Exynos4210 is not publically available,

+ * As this part of the Exynos4210 is not publicly available,

* we used the "HS-MMC Controller S3C2416X RISC Microprocessor"

* public datasheet which is very similar (implementing

* MMC Specification Version 4.0 being the only difference noted)

diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c

--- a/hw/arm/musicpal.c

+++ b/hw/arm/musicpal.c

@@ -XXX,XX +XXX,XX @@

#define MP_LCD_SPI_CMD 0x00104011

#define MP_LCD_SPI_INVALID 0x00000000

-/* Commmands */

+/* Commands */

#define MP_LCD_INST_SETPAGE0 0xB0

/* ... */

#define MP_LCD_INST_SETPAGE7 0xB7

diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/omap1.c

+++ b/hw/arm/omap1.c

@@ -XXX,XX +XXX,XX @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,

s->led[1] = omap_lpg_init(system_memory,

0xfffbd800, omap_findclk(s, "clk32-kHz"));

- /* Register mappings not currenlty implemented:

+ /* Register mappings not currently implemented:

* MCSI2 Comm    fffb2000 - fffb27ff (not mapped on OMAP310)

* MCSI1 Bluetooth    fffb2800 - fffb2fff (not mapped on OMAP310)

* USB W2FC        fffb4000 - fffb47ff

diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/omap2.c

+++ b/hw/arm/omap2.c

@@ -XXX,XX +XXX,XX @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,

omap_findclk(s, "func_96m_clk"),

omap_findclk(s, "core_l4_iclk"));

- /* All register mappings (includin those not currenlty implemented):

+ /* All register mappings (including those not currently implemented):

* SystemControlMod    48000000 - 48000fff

* SystemControlL4    48001000 - 48001fff

* 32kHz Timer Mod    48004000 - 48004fff

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/virt-acpi-build.c

+++ b/hw/arm/virt-acpi-build.c

@@ -XXX,XX +XXX,XX @@ static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size)

build_append_int_noprefix(table_data, 0xE, 1); /* Type */

build_append_int_noprefix(table_data, 16, 1); /* Length */

build_append_int_noprefix(table_data, 0, 2); /* Reserved */

- /* Discovery Range Base Addres */

+ /* Discovery Range Base Address */

build_append_int_noprefix(table_data, base, 8);

build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */

}

diff --git a/hw/arm/virt.c b/hw/arm/virt.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/virt.c

+++ b/hw/arm/virt.c

@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)

int pa_bits;

/*

- * Instanciate a temporary CPU object to find out about what

+ * Instantiate a temporary CPU object to find out about what

* we are about to deal with. Once this is done, get rid of

* the object.

*/

diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/xlnx-versal-virt.c

+++ b/hw/arm/xlnx-versal-virt.c

@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)

fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);

/* Make the APU cpu address space visible to virtio and other

- * modules unaware of muliple address-spaces. */

+ * modules unaware of multiple address-spaces. */

memory_region_add_subregion_overlap(get_system_memory(),

0, &s->soc.fpd.apu.mr, 0);

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/Kconfig

+++ b/hw/arm/Kconfig

@@ -XXX,XX +XXX,XX @@ config OLIMEX_STM32_H405

config NSERIES

bool

select OMAP

- select TMP105 # tempature sensor

+ select TMP105 # temperature sensor

select BLIZZARD # LCD/TV controller

select ONENAND

select TSC210X # touchscreen/sensors/audio

2.34.1

From: Strahinja Jankovic <strahinjapjankovic@gmail.com>

This patch adds basic support for Allwinner WDT.

Both sun4i and sun6i variants are supported.

However, interrupt generation is not supported, so WDT can be used only to trigger system reset.

Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>

Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>

Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>

Message-id: 20230326202256.22980-2-strahinja.p.jankovic@gmail.com

include/hw/watchdog/allwinner-wdt.h | 123 ++++++++

hw/watchdog/allwinner-wdt.c | 416 ++++++++++++++++++++++++++++

hw/watchdog/Kconfig | 4 +

hw/watchdog/meson.build | 1 +

hw/watchdog/trace-events | 7 +

5 files changed, 551 insertions(+)

create mode 100644 include/hw/watchdog/allwinner-wdt.h

create mode 100644 hw/watchdog/allwinner-wdt.c

diff --git a/include/hw/watchdog/allwinner-wdt.h b/include/hw/watchdog/allwinner-wdt.h

+++ b/include/hw/watchdog/allwinner-wdt.h

+ * Allwinner Watchdog emulation

+ *

+ * Copyright (C) 2023 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>

+ *

+ * This file is derived from Allwinner RTC,

+ * by Niek Linnenbank.

+ *

+ * This program is free software: you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License as published by

+ * the Free Software Foundation, either version 2 of the License, or

+ * (at your option) any later version.

+ *

+ * This program is distributed in the hope that it will be useful,

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

+ * GNU General Public License for more details.

+ *

+ * You should have received a copy of the GNU General Public License

+ * along with this program. If not, see <http://www.gnu.org/licenses/>.

+#ifndef HW_WATCHDOG_ALLWINNER_WDT_H

+#define HW_WATCHDOG_ALLWINNER_WDT_H

+

+#include "qom/object.h"

+#include "hw/ptimer.h"

+#include "hw/sysbus.h"

+

+/*

+ * This is a model of the Allwinner watchdog.

+ * Since watchdog registers belong to the timer module (and are shared with the

+ * RTC module), the interrupt line from watchdog is not handled right now.

+ * In QEMU, we just wire up the watchdog reset to watchdog_perform_action(),

+ * at least for the moment.

+ */

+

+#define TYPE_AW_WDT "allwinner-wdt"

+

+/** Allwinner WDT sun4i family (A10, A12), also sun7i (A20) */

+#define TYPE_AW_WDT_SUN4I TYPE_AW_WDT "-sun4i"

+

+/** Allwinner WDT sun6i family and newer (A31, H2+, H3, etc) */

+#define TYPE_AW_WDT_SUN6I TYPE_AW_WDT "-sun6i"

+

+/** Number of WDT registers */

+#define AW_WDT_REGS_NUM (5)

+

+OBJECT_DECLARE_TYPE(AwWdtState, AwWdtClass, AW_WDT)

+

+/**

+ * Allwinner WDT object instance state.

+ */

+struct AwWdtState {

+ /*< private >*/

+ SysBusDevice parent_obj;

+

+ /*< public >*/

+ MemoryRegion iomem;

+ struct ptimer_state *timer;

+

+ uint32_t regs[AW_WDT_REGS_NUM];

+};

+

+/**

+ * Allwinner WDT class-level struct.

+ *

+ * This struct is filled by each sunxi device specific code

+ * such that the generic code can use this struct to support

+ * all devices.

+ */

+struct AwWdtClass {

+ /*< private >*/

+ SysBusDeviceClass parent_class;

+ /*< public >*/

+

+ /** Defines device specific register map */

+ const uint8_t *regmap;

+

+ /** Size of the regmap in bytes */

+ size_t regmap_size;

+

+ /**

+ * Read device specific register

+ *

+ * @offset: register offset to read

+ * @return true if register read successful, false otherwise

+ */

+ bool (*read)(AwWdtState *s, uint32_t offset);

+

+ /**

+ * Write device specific register

+ *

+ * @offset: register offset to write

+ * @data: value to set in register

+ * @return true if register write successful, false otherwise

+ */

+ bool (*write)(AwWdtState *s, uint32_t offset, uint32_t data);

+

+ /**

+ * Check if watchdog can generate system reset

+ *

+ * @return true if watchdog can generate system reset

+ */

+ bool (*can_reset_system)(AwWdtState *s);

+

+ /**

+ * Check if provided key is valid

+ *

+ * @value: value written to register

+ * @return true if key is valid, false otherwise

+ */

+ bool (*is_key_valid)(AwWdtState *s, uint32_t val);

+

+ /**

+ * Get current INTV_VALUE setting

+ *

+ * @return current INTV_VALUE (0-15)

+ */

+ uint8_t (*get_intv_value)(AwWdtState *s);

+};

+

+#endif /* HW_WATCHDOG_ALLWINNER_WDT_H */

diff --git a/hw/watchdog/allwinner-wdt.c b/hw/watchdog/allwinner-wdt.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/watchdog/allwinner-wdt.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * Allwinner Watchdog emulation

+ *

+ * Copyright (C) 2023 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>

+ *

+ * This file is derived from Allwinner RTC,

+ * by Niek Linnenbank.

+ *

+ * This program is free software: you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License as published by

+ * the Free Software Foundation, either version 2 of the License, or

+ * (at your option) any later version.

+ *

+ * This program is distributed in the hope that it will be useful,

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

+ * GNU General Public License for more details.

+ *

+ * You should have received a copy of the GNU General Public License

+ * along with this program. If not, see <http://www.gnu.org/licenses/>.

+ */

+

+#include "qemu/osdep.h"

+#include "qemu/log.h"

+#include "qemu/units.h"

+#include "qemu/module.h"

+#include "trace.h"

+#include "hw/sysbus.h"

+#include "hw/registerfields.h"

+#include "hw/watchdog/allwinner-wdt.h"

+#include "sysemu/watchdog.h"

+#include "migration/vmstate.h"

+

+/* WDT registers */

+enum {

+ REG_IRQ_EN = 0, /* Watchdog interrupt enable */

+ REG_IRQ_STA, /* Watchdog interrupt status */

+ REG_CTRL, /* Watchdog control register */

+ REG_CFG, /* Watchdog configuration register */

+ REG_MODE, /* Watchdog mode register */

+};

+

+/* Universal WDT register flags */

+#define WDT_RESTART_MASK (1 << 0)

+#define WDT_EN_MASK (1 << 0)

+

+/* sun4i specific WDT register flags */

+#define RST_EN_SUN4I_MASK (1 << 1)

+#define INTV_VALUE_SUN4I_SHIFT (3)

+#define INTV_VALUE_SUN4I_MASK (0xfu << INTV_VALUE_SUN4I_SHIFT)

+

+/* sun6i specific WDT register flags */

+#define RST_EN_SUN6I_MASK (1 << 0)

+#define KEY_FIELD_SUN6I_SHIFT (1)

+#define KEY_FIELD_SUN6I_MASK (0xfffu << KEY_FIELD_SUN6I_SHIFT)

+#define KEY_FIELD_SUN6I (0xA57u)

+#define INTV_VALUE_SUN6I_SHIFT (4)

+#define INTV_VALUE_SUN6I_MASK (0xfu << INTV_VALUE_SUN6I_SHIFT)

+

+/* Map of INTV_VALUE to 0.5s units. */

+static const uint8_t allwinner_wdt_count_map[] = {

+ 1,

+ 2,

+ 4,

+ 6,

+ 8,

+ 10,

+ 12,

+ 16,

+ 20,

+ 24,

+ 28,

+ 32

+};

+

+/* WDT sun4i register map (offset to name) */

+const uint8_t allwinner_wdt_sun4i_regmap[] = {

+ [0x0000] = REG_CTRL,

+ [0x0004] = REG_MODE,

+};

+

+/* WDT sun6i register map (offset to name) */

+const uint8_t allwinner_wdt_sun6i_regmap[] = {

+ [0x0000] = REG_IRQ_EN,

+ [0x0004] = REG_IRQ_STA,

+ [0x0010] = REG_CTRL,

+ [0x0014] = REG_CFG,

+ [0x0018] = REG_MODE,

+};

+

+static bool allwinner_wdt_sun4i_read(AwWdtState *s, uint32_t offset)

+{

+ /* no sun4i specific registers currently implemented */

+ return false;

+}

+

+static bool allwinner_wdt_sun4i_write(AwWdtState *s, uint32_t offset,

+ uint32_t data)

+{

+ /* no sun4i specific registers currently implemented */

+ return false;

+}

+

+static bool allwinner_wdt_sun4i_can_reset_system(AwWdtState *s)

+{

+ if (s->regs[REG_MODE] & RST_EN_SUN4I_MASK) {

+ return true;

+ } else {

+ return false;

+ }

+}

+

+static bool allwinner_wdt_sun4i_is_key_valid(AwWdtState *s, uint32_t val)

+{

+ /* sun4i has no key */

+ return true;

+}

+

+static uint8_t allwinner_wdt_sun4i_get_intv_value(AwWdtState *s)

+{

+ return ((s->regs[REG_MODE] & INTV_VALUE_SUN4I_MASK) >>

+ INTV_VALUE_SUN4I_SHIFT);

+}

+

+static bool allwinner_wdt_sun6i_read(AwWdtState *s, uint32_t offset)

+{

+ const AwWdtClass *c = AW_WDT_GET_CLASS(s);

+

+ switch (c->regmap[offset]) {

+ case REG_IRQ_EN:

+ case REG_IRQ_STA:

+ case REG_CFG:

+ return true;

+ default:

+ break;

+ }

+ return false;

+}

+

+static bool allwinner_wdt_sun6i_write(AwWdtState *s, uint32_t offset,

+ uint32_t data)

+{

+ const AwWdtClass *c = AW_WDT_GET_CLASS(s);

+

+ switch (c->regmap[offset]) {

+ case REG_IRQ_EN:

+ case REG_IRQ_STA:

+ case REG_CFG:

+ return true;

+ default:

+ break;

+ }

+ return false;

+}

+

+static bool allwinner_wdt_sun6i_can_reset_system(AwWdtState *s)

+{

+ if (s->regs[REG_CFG] & RST_EN_SUN6I_MASK) {

+ return true;

+ } else {

+ return false;

+ }

+}

+

+static bool allwinner_wdt_sun6i_is_key_valid(AwWdtState *s, uint32_t val)

+{

+ uint16_t key = (val & KEY_FIELD_SUN6I_MASK) >> KEY_FIELD_SUN6I_SHIFT;

+ return (key == KEY_FIELD_SUN6I);

+}

+

+static uint8_t allwinner_wdt_sun6i_get_intv_value(AwWdtState *s)

+{

+ return ((s->regs[REG_MODE] & INTV_VALUE_SUN6I_MASK) >>

+ INTV_VALUE_SUN6I_SHIFT);

+}

+

+static void allwinner_wdt_update_timer(AwWdtState *s)

+{

+ const AwWdtClass *c = AW_WDT_GET_CLASS(s);

+ uint8_t count = c->get_intv_value(s);

+

+ ptimer_transaction_begin(s->timer);

+ ptimer_stop(s->timer);

+

+ /* Use map to convert. */

+ if (count < sizeof(allwinner_wdt_count_map)) {

+ ptimer_set_count(s->timer, allwinner_wdt_count_map[count]);

+ } else {

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: incorrect INTV_VALUE 0x%02x\n",

+ __func__, count);

+ }

+

+ ptimer_run(s->timer, 1);

+ ptimer_transaction_commit(s->timer);

+

+ trace_allwinner_wdt_update_timer(count);

+}

+

+static uint64_t allwinner_wdt_read(void *opaque, hwaddr offset,

+ unsigned size)

+{

+ AwWdtState *s = AW_WDT(opaque);

+ const AwWdtClass *c = AW_WDT_GET_CLASS(s);

+ uint64_t r;

+

+ if (offset >= c->regmap_size) {

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",

+ __func__, (uint32_t)offset);

+ return 0;

+ }

+

+ switch (c->regmap[offset]) {

+ case REG_CTRL:

+ case REG_MODE:

+ r = s->regs[c->regmap[offset]];

+ break;

+ default:

+ if (!c->read(s, offset)) {

+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",

+ __func__, (uint32_t)offset);

+ return 0;

+ }

+ r = s->regs[c->regmap[offset]];

+ break;

+ }

+

+ trace_allwinner_wdt_read(offset, r, size);

+

+ return r;

+}

+

+static void allwinner_wdt_write(void *opaque, hwaddr offset,

+ uint64_t val, unsigned size)

+{

+ AwWdtState *s = AW_WDT(opaque);

+ const AwWdtClass *c = AW_WDT_GET_CLASS(s);

+ uint32_t old_val;

+

+ if (offset >= c->regmap_size) {

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",

+ __func__, (uint32_t)offset);

+ return;

+ }

+

+ trace_allwinner_wdt_write(offset, val, size);

+

+ switch (c->regmap[offset]) {

+ case REG_CTRL:

+ if (c->is_key_valid(s, val)) {

+ if (val & WDT_RESTART_MASK) {

+ /* Kick timer */

+ allwinner_wdt_update_timer(s);

+ }

+ }

+ break;

+ case REG_MODE:

+ old_val = s->regs[REG_MODE];

+ s->regs[REG_MODE] = (uint32_t)val;

+

+ /* Check for rising edge on WDOG_MODE_EN */

+ if ((s->regs[REG_MODE] & ~old_val) & WDT_EN_MASK) {

+ allwinner_wdt_update_timer(s);

+ }

+ break;

+ default:

+ if (!c->write(s, offset, val)) {

+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",

+ __func__, (uint32_t)offset);

+ }

+ s->regs[c->regmap[offset]] = (uint32_t)val;

+ break;

+ }

+}

+

+static const MemoryRegionOps allwinner_wdt_ops = {

+ .read = allwinner_wdt_read,

+ .write = allwinner_wdt_write,

+ .endianness = DEVICE_NATIVE_ENDIAN,

+ .valid = {

+ .min_access_size = 4,

+ .max_access_size = 4,

+ },

+ .impl.min_access_size = 4,

+};

+

+static void allwinner_wdt_expired(void *opaque)

+{

+ AwWdtState *s = AW_WDT(opaque);

+ const AwWdtClass *c = AW_WDT_GET_CLASS(s);

+

+ bool enabled = s->regs[REG_MODE] & WDT_EN_MASK;

+ bool reset_enabled = c->can_reset_system(s);

+

+ trace_allwinner_wdt_expired(enabled, reset_enabled);

+

+ /* Perform watchdog action if watchdog is enabled and can trigger reset */

+ if (enabled && reset_enabled) {

+ watchdog_perform_action();

+ }

+}

+

+static void allwinner_wdt_reset_enter(Object *obj, ResetType type)

+{

+ AwWdtState *s = AW_WDT(obj);

+

+ trace_allwinner_wdt_reset_enter();

+

+ /* Clear registers */

+ memset(s->regs, 0, sizeof(s->regs));

+}

+

+static const VMStateDescription allwinner_wdt_vmstate = {

+ .name = "allwinner-wdt",

+ .version_id = 1,

+ .minimum_version_id = 1,

+ .fields = (VMStateField[]) {

+ VMSTATE_PTIMER(timer, AwWdtState),

+ VMSTATE_UINT32_ARRAY(regs, AwWdtState, AW_WDT_REGS_NUM),

+ VMSTATE_END_OF_LIST()

+ }

+};

+

+static void allwinner_wdt_init(Object *obj)

+{

+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

+ AwWdtState *s = AW_WDT(obj);

+ const AwWdtClass *c = AW_WDT_GET_CLASS(s);

+

+ /* Memory mapping */

+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_wdt_ops, s,

+ TYPE_AW_WDT, c->regmap_size * 4);

+ sysbus_init_mmio(sbd, &s->iomem);

+}

+

+static void allwinner_wdt_realize(DeviceState *dev, Error **errp)

+{

+ AwWdtState *s = AW_WDT(dev);

+

+ s->timer = ptimer_init(allwinner_wdt_expired, s,

+ PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |

+ PTIMER_POLICY_NO_IMMEDIATE_RELOAD |

+ PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);

+

+ ptimer_transaction_begin(s->timer);

+ /* Set to 2Hz (0.5s period); other periods are multiples of 0.5s. */

+ ptimer_set_freq(s->timer, 2);

+ ptimer_set_limit(s->timer, 0xff, 1);

+ ptimer_transaction_commit(s->timer);

+}

+

+static void allwinner_wdt_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+ ResettableClass *rc = RESETTABLE_CLASS(klass);

+

+ rc->phases.enter = allwinner_wdt_reset_enter;

+ dc->realize = allwinner_wdt_realize;

+ dc->vmsd = &allwinner_wdt_vmstate;

+}

+

+static void allwinner_wdt_sun4i_class_init(ObjectClass *klass, void *data)

+{

+ AwWdtClass *awc = AW_WDT_CLASS(klass);

+

+ awc->regmap = allwinner_wdt_sun4i_regmap;

+ awc->regmap_size = sizeof(allwinner_wdt_sun4i_regmap);

+ awc->read = allwinner_wdt_sun4i_read;

+ awc->write = allwinner_wdt_sun4i_write;

+ awc->can_reset_system = allwinner_wdt_sun4i_can_reset_system;

+ awc->is_key_valid = allwinner_wdt_sun4i_is_key_valid;

+ awc->get_intv_value = allwinner_wdt_sun4i_get_intv_value;

+}

+

+static void allwinner_wdt_sun6i_class_init(ObjectClass *klass, void *data)

+{

+ AwWdtClass *awc = AW_WDT_CLASS(klass);

+

+ awc->regmap = allwinner_wdt_sun6i_regmap;

+ awc->regmap_size = sizeof(allwinner_wdt_sun6i_regmap);

+ awc->read = allwinner_wdt_sun6i_read;

+ awc->write = allwinner_wdt_sun6i_write;

+ awc->can_reset_system = allwinner_wdt_sun6i_can_reset_system;

+ awc->is_key_valid = allwinner_wdt_sun6i_is_key_valid;

+ awc->get_intv_value = allwinner_wdt_sun6i_get_intv_value;

+}

+

+static const TypeInfo allwinner_wdt_info = {

+ .name = TYPE_AW_WDT,

+ .parent = TYPE_SYS_BUS_DEVICE,

+ .instance_init = allwinner_wdt_init,

+ .instance_size = sizeof(AwWdtState),

+ .class_init = allwinner_wdt_class_init,

+ .class_size = sizeof(AwWdtClass),

+ .abstract = true,

+};

+

+static const TypeInfo allwinner_wdt_sun4i_info = {

+ .name = TYPE_AW_WDT_SUN4I,

+ .parent = TYPE_AW_WDT,

+ .class_init = allwinner_wdt_sun4i_class_init,

+};

+

+static const TypeInfo allwinner_wdt_sun6i_info = {

+ .name = TYPE_AW_WDT_SUN6I,

+ .parent = TYPE_AW_WDT,

+ .class_init = allwinner_wdt_sun6i_class_init,

+};

+

+static void allwinner_wdt_register(void)

+{

+ type_register_static(&allwinner_wdt_info);

+ type_register_static(&allwinner_wdt_sun4i_info);

+ type_register_static(&allwinner_wdt_sun6i_info);

+}

+

+type_init(allwinner_wdt_register)

diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig

index XXXXXXX..XXXXXXX 100644

--- a/hw/watchdog/Kconfig

+++ b/hw/watchdog/Kconfig

@@ -XXX,XX +XXX,XX @@ config WDT_IMX2

config WDT_SBSA

bool

+

+config ALLWINNER_WDT

+ bool

+ select PTIMER

diff --git a/hw/watchdog/meson.build b/hw/watchdog/meson.build

index XXXXXXX..XXXXXXX 100644

--- a/hw/watchdog/meson.build

+++ b/hw/watchdog/meson.build

@@ -XXX,XX +XXX,XX @@

softmmu_ss.add(files('watchdog.c'))

+softmmu_ss.add(when: 'CONFIG_ALLWINNER_WDT', if_true: files('allwinner-wdt.c'))

softmmu_ss.add(when: 'CONFIG_CMSDK_APB_WATCHDOG', if_true: files('cmsdk-apb-watchdog.c'))

softmmu_ss.add(when: 'CONFIG_WDT_IB6300ESB', if_true: files('wdt_i6300esb.c'))

softmmu_ss.add(when: 'CONFIG_WDT_IB700', if_true: files('wdt_ib700.c'))

diff --git a/hw/watchdog/trace-events b/hw/watchdog/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/watchdog/trace-events

+++ b/hw/watchdog/trace-events

@@ -XXX,XX +XXX,XX @@

# See docs/devel/tracing.rst for syntax documentation.

+# allwinner-wdt.c

+allwinner_wdt_read(uint64_t offset, uint64_t data, unsigned size) "Allwinner watchdog read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"

+allwinner_wdt_write(uint64_t offset, uint64_t data, unsigned size) "Allwinner watchdog write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"

+allwinner_wdt_reset_enter(void) "Allwinner watchdog: reset"

+allwinner_wdt_update_timer(uint8_t count) "Allwinner watchdog: count %" PRIu8

+allwinner_wdt_expired(bool enabled, bool reset_enabled) "Allwinner watchdog: enabled %u reset_enabled %u"

+

# cmsdk-apb-watchdog.c

cmsdk_apb_watchdog_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"

cmsdk_apb_watchdog_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"

2.34.1

From: Strahinja Jankovic <strahinjapjankovic@gmail.com>

This patch adds WDT to Allwinner-A10 and Cubieboard.

WDT is added as an overlay to the Timer module memory map.

Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>

Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>

Message-id: 20230326202256.22980-3-strahinja.p.jankovic@gmail.com

docs/system/arm/cubieboard.rst | 1 +

include/hw/arm/allwinner-a10.h | 2 ++

hw/arm/allwinner-a10.c | 7 +++++++

hw/arm/Kconfig | 1 +

4 files changed, 11 insertions(+)

diff --git a/docs/system/arm/cubieboard.rst b/docs/system/arm/cubieboard.rst

--- a/docs/system/arm/cubieboard.rst

+++ b/docs/system/arm/cubieboard.rst

@@ -XXX,XX +XXX,XX @@ Emulated devices:

- USB controller

- SATA controller

- TWI (I2C) controller

+- Watchdog timer

diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/arm/allwinner-a10.h

+++ b/include/hw/arm/allwinner-a10.h

@@ -XXX,XX +XXX,XX @@

#include "hw/misc/allwinner-a10-ccm.h"

#include "hw/misc/allwinner-a10-dramc.h"

#include "hw/i2c/allwinner-i2c.h"

+#include "hw/watchdog/allwinner-wdt.h"

#include "sysemu/block-backend.h"

#include "target/arm/cpu.h"

@@ -XXX,XX +XXX,XX @@ struct AwA10State {

AwSdHostState mmc0;

AWI2CState i2c0;

AwRtcState rtc;

+ AwWdtState wdt;

MemoryRegion sram_a;

EHCISysBusState ehci[AW_A10_NUM_USB];

OHCISysBusState ohci[AW_A10_NUM_USB];

diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/allwinner-a10.c

+++ b/hw/arm/allwinner-a10.c

@@ -XXX,XX +XXX,XX @@

#define AW_A10_EHCI_BASE 0x01c14000

#define AW_A10_OHCI_BASE 0x01c14400

#define AW_A10_SATA_BASE 0x01c18000

+#define AW_A10_WDT_BASE 0x01c20c90

#define AW_A10_RTC_BASE 0x01c20d00

#define AW_A10_I2C0_BASE 0x01c2ac00

@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)

object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I);

object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN4I);

+

+ object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN4I);

static void aw_a10_realize(DeviceState *dev, Error **errp)

@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)

sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);

sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, AW_A10_I2C0_BASE);

sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, qdev_get_gpio_in(dev, 7));

+ /* WDT */

+ sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal);

+ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0, AW_A10_WDT_BASE, 1);

2.34.1