[PULL 0/9] target-arm queue
[PULL v2 00/57] target-arm queue
1
target-arm queue: nothing major here, but no point
1
Squashed in a trivial fix for 32-bit hosts:
2
sitting on them waiting for more stuff to come along.
3
2
4
thanks
3
--- a/target/arm/mve_helper.c
4
+++ b/target/arm/mve_helper.c
5
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
6
acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
7
m[H##ESIZE(e)])); \
8
} \
9
- acc = int128_add(acc, 1 << 7); \
10
+ acc = int128_add(acc, int128_make64(1 << 7)); \
11
} \
12
} \
13
mve_advance_vpt(env); \
14
5
-- PMM
15
-- PMM
6
16
7
The following changes since commit 1329132d28bf14b9508f7a1f04a2c63422bc3f99:
17
The following changes since commit 53f306f316549d20c76886903181413d20842423:
8
18
9
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2019-09-26 16:14:03 +0100)
19
Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
10
20
11
are available in the Git repository at:
21
are available in the Git repository at:
12
22
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190927
23
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
14
24
15
for you to fetch changes up to e4e34855e658b78ecac50a651cc847662ff02cfd:
25
for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
16
26
17
hw/arm/boot: Use the IEC binary prefix definitions (2019-09-27 11:44:39 +0100)
27
docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
18
28
19
----------------------------------------------------------------
29
----------------------------------------------------------------
20
target-arm queue:
30
target-arm queue:
21
* Fix the CBAR register implementation for Cortex-A53,
31
* Don't require 'virt' board to be compiled in for ACPI GHES code
22
Cortex-A57, Cortex-A72
32
* docs: Document which architecture extensions we emulate
23
* Fix direct booting of Linux kernels on emulated CPUs
33
* Fix bugs in M-profile FPCXT_NS accesses
24
which have an AArch32 EL3 (incorrect NSACR settings
34
* First slice of MVE patches
25
meant they could not access the FPU)
35
* Implement MTE3
26
* semihosting cleanup: do more work at translate time
36
* docs/system: arm: Add nRF boards description
27
and less work at runtime
28
37
29
----------------------------------------------------------------
38
----------------------------------------------------------------
30
Alex Bennée (6):
39
Alexandre Iooss (1):
31
tests/tcg: clean-up some comments after the de-tangling
40
docs/system: arm: Add nRF boards description
32
target/arm: handle M-profile semihosting at translate time
33
target/arm: handle A-profile semihosting at translate time
34
target/arm: remove run time semihosting checks
35
target/arm: remove run-time semihosting checks for linux-user
36
tests/tcg: add linux-user semihosting smoke test for ARM
37
41
38
Luc Michel (1):
42
Peter Collingbourne (1):
39
target/arm: fix CBAR register for AArch64 CPUs
43
target/arm: Implement MTE3
40
44
41
Peter Maydell (1):
45
Peter Maydell (55):
42
hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots
46
hw/acpi: Provide stub version of acpi_ghes_record_errors()
47
hw/acpi: Provide function acpi_ghes_present()
48
target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
49
docs/system/arm: Document which architecture extensions we emulate
50
target/arm/translate-vfp.c: Whitespace fixes
51
target/arm: Handle FPU being disabled in FPCXT_NS accesses
52
target/arm: Don't NOCP fault for FPCXT_NS accesses
53
target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
54
target/arm: Factor FP context update code out into helper function
55
target/arm: Split vfp_access_check() into A and M versions
56
target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
57
target/arm: Implement MVE VLDR/VSTR (non-widening forms)
58
target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
59
target/arm: Implement MVE VCLZ
60
target/arm: Implement MVE VCLS
61
target/arm: Implement MVE VREV16, VREV32, VREV64
62
target/arm: Implement MVE VMVN (register)
63
target/arm: Implement MVE VABS
64
target/arm: Implement MVE VNEG
65
tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
66
target/arm: Implement MVE VDUP
67
target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
68
target/arm: Implement MVE VADD, VSUB, VMUL
69
target/arm: Implement MVE VMULH
70
target/arm: Implement MVE VRMULH
71
target/arm: Implement MVE VMAX, VMIN
72
target/arm: Implement MVE VABD
73
target/arm: Implement MVE VHADD, VHSUB
74
target/arm: Implement MVE VMULL
75
target/arm: Implement MVE VMLALDAV
76
target/arm: Implement MVE VMLSLDAV
77
target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
78
target/arm: Implement MVE VADD (scalar)
79
target/arm: Implement MVE VSUB, VMUL (scalar)
80
target/arm: Implement MVE VHADD, VHSUB (scalar)
81
target/arm: Implement MVE VBRSR
82
target/arm: Implement MVE VPST
83
target/arm: Implement MVE VQADD and VQSUB
84
target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
85
target/arm: Implement MVE VQDMULL scalar
86
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
87
target/arm: Implement MVE VQADD, VQSUB (vector)
88
target/arm: Implement MVE VQSHL (vector)
89
target/arm: Implement MVE VQRSHL
90
target/arm: Implement MVE VSHL insn
91
target/arm: Implement MVE VRSHL
92
target/arm: Implement MVE VQDMLADH and VQRDMLADH
93
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
94
target/arm: Implement MVE VQDMULL (vector)
95
target/arm: Implement MVE VRHADD
96
target/arm: Implement MVE VADC, VSBC
97
target/arm: Implement MVE VCADD
98
target/arm: Implement MVE VHCADD
99
target/arm: Implement MVE VADDV
100
target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
43
101
44
Philippe Mathieu-Daudé (1):
102
docs/system/arm/emulation.rst | 103 ++++
45
hw/arm/boot: Use the IEC binary prefix definitions
103
docs/system/arm/nrf.rst | 51 ++
104
docs/system/target-arm.rst | 7 +
105
include/hw/acpi/ghes.h | 9 +
106
include/tcg/tcg-op.h | 8 +
107
include/tcg/tcg.h | 1 -
108
target/arm/helper-mve.h | 357 +++++++++++++
109
target/arm/helper.h | 2 +
110
target/arm/internals.h | 11 +
111
target/arm/translate-a32.h | 3 +
112
target/arm/translate.h | 10 +
113
target/arm/m-nocp.decode | 24 +
114
target/arm/mve.decode | 240 +++++++++
115
target/arm/vfp.decode | 14 -
116
hw/acpi/ghes-stub.c | 22 +
117
hw/acpi/ghes.c | 17 +
118
target/arm/cpu64.c | 2 +-
119
target/arm/kvm64.c | 6 +-
120
target/arm/mte_helper.c | 82 +--
121
target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++
122
target/arm/translate-m-nocp.c | 550 +++++++++++++++++++
123
target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++
124
target/arm/translate-vfp.c | 741 +++++++-------------------
125
tcg/tcg-op-gvec.c | 20 +-
126
MAINTAINERS | 1 +
127
hw/acpi/meson.build | 6 +-
128
target/arm/meson.build | 1 +
129
27 files changed, 3578 insertions(+), 629 deletions(-)
130
create mode 100644 docs/system/arm/emulation.rst
131
create mode 100644 docs/system/arm/nrf.rst
132
create mode 100644 target/arm/helper-mve.h
133
create mode 100644 hw/acpi/ghes-stub.c
134
create mode 100644 target/arm/mve_helper.c
46
135
47
tests/tcg/Makefile.target | 7 ++-
48
tests/tcg/aarch64/Makefile.target | 8 ++-
49
tests/tcg/arm/Makefile.target | 20 ++++---
50
linux-user/arm/target_syscall.h | 3 -
51
hw/arm/boot.c | 12 ++--
52
linux-user/arm/cpu_loop.c | 3 -
53
target/arm/helper.c | 115 +++++++++++++-------------------------
54
target/arm/m_helper.c | 18 ++----
55
target/arm/translate.c | 30 ++++++++--
56
tests/tcg/arm/semihosting.c | 45 +++++++++++++++
57
10 files changed, 146 insertions(+), 115 deletions(-)
58
create mode 100644 tests/tcg/arm/semihosting.c
59
diff view generated by jsdifflib
[PULL 1/9] target/arm: fix CBAR register for AArch64 CPUs
Deleted patch
1
From: Luc Michel <luc.michel@greensocs.com>
2
1
3
For AArch64 CPUs with a CBAR register, we have two views for it:
4
- in AArch64 state, the CBAR_EL1 register (S3_1_C15_C3_0), returns the
5
full 64 bits CBAR value
6
- in AArch32 state, the CBAR register (cp15, opc1=1, CRn=15, CRm=3, opc2=0)
7
returns a 32 bits view such that:
8
CBAR = CBAR_EL1[31:18] 0..0 CBAR_EL1[43:32]
9
10
This commit fixes the current implementation where:
11
- CBAR_EL1 was returning the 32 bits view instead of the full 64 bits
12
value,
13
- CBAR was returning a truncated 32 bits version of the full 64 bits
14
one, instead of the 32 bits view
15
- CBAR was declared as cp15, opc1=4, CRn=15, CRm=0, opc2=0, which is
16
the CBAR register found in the ARMv7 Cortex-Ax CPUs, but not in
17
ARMv8 CPUs.
18
19
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
20
Message-id: 20190912110103.1417887-1-luc.michel@greensocs.com
21
[PMM: Added a comment about the two different kinds of CBAR]
22
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
---
25
target/arm/helper.c | 19 ++++++++++++++++---
26
1 file changed, 16 insertions(+), 3 deletions(-)
27
28
diff --git a/target/arm/helper.c b/target/arm/helper.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/helper.c
31
+++ b/target/arm/helper.c
32
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
33
}
34
35
if (arm_feature(env, ARM_FEATURE_CBAR)) {
36
+ /*
37
+ * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
38
+ * There are two flavours:
39
+ * (1) older 32-bit only cores have a simple 32-bit CBAR
40
+ * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
41
+ * 32-bit register visible to AArch32 at a different encoding
42
+ * to the "flavour 1" register and with the bits rearranged to
43
+ * be able to squash a 64-bit address into the 32-bit view.
44
+ * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
45
+ * in future if we support AArch32-only configs of some of the
46
+ * AArch64 cores we might need to add a specific feature flag
47
+ * to indicate cores with "flavour 2" CBAR.
48
+ */
49
if (arm_feature(env, ARM_FEATURE_AARCH64)) {
50
/* 32 bit view is [31:18] 0...0 [43:32]. */
51
uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
52
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
53
ARMCPRegInfo cbar_reginfo[] = {
54
{ .name = "CBAR",
55
.type = ARM_CP_CONST,
56
- .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
57
- .access = PL1_R, .resetvalue = cpu->reset_cbar },
58
+ .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0,
59
+ .access = PL1_R, .resetvalue = cbar32 },
60
{ .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
61
.type = ARM_CP_CONST,
62
.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
63
- .access = PL1_R, .resetvalue = cbar32 },
64
+ .access = PL1_R, .resetvalue = cpu->reset_cbar },
65
REGINFO_SENTINEL
66
};
67
/* We don't implement a r/w 64 bit CBAR currently */
68
--
69
2.20.1
70
71
diff view generated by jsdifflib
[PULL 2/9] tests/tcg: clean-up some comments after the de-tangling
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
These were missed in the recent de-tangling so have been updated to be
4
more actuate. I've also built up ARM_TESTS in a manner similar to
5
AARCH64_TESTS for better consistency.
6
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20190913151845.12582-2-alex.bennee@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
tests/tcg/Makefile.target | 7 +++++--
13
tests/tcg/aarch64/Makefile.target | 3 ++-
14
tests/tcg/arm/Makefile.target | 15 ++++++++-------
15
3 files changed, 15 insertions(+), 10 deletions(-)
16
17
diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
18
index XXXXXXX..XXXXXXX 100644
19
--- a/tests/tcg/Makefile.target
20
+++ b/tests/tcg/Makefile.target
21
@@ -XXX,XX +XXX,XX @@ TIMEOUT=15
22
endif
23
24
ifdef CONFIG_USER_ONLY
25
-# The order we include is important. We include multiarch, base arch
26
-# and finally arch if it's not the same as base arch.
27
+# The order we include is important. We include multiarch first and
28
+# then the target. If there are common tests shared between
29
+# sub-targets (e.g. ARM & AArch64) then it is up to
30
+# $(TARGET_NAME)/Makefile.target to include the common parent
31
+# architecture in its VPATH.
32
-include $(SRC_PATH)/tests/tcg/multiarch/Makefile.target
33
-include $(SRC_PATH)/tests/tcg/$(TARGET_NAME)/Makefile.target
34
35
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
36
index XXXXXXX..XXXXXXX 100644
37
--- a/tests/tcg/aarch64/Makefile.target
38
+++ b/tests/tcg/aarch64/Makefile.target
39
@@ -XXX,XX +XXX,XX @@ VPATH         += $(ARM_SRC)
40
AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64
41
VPATH         += $(AARCH64_SRC)
42
43
-# we don't build any other ARM test
44
+# Float-convert Tests
45
AARCH64_TESTS=fcvt
46
47
fcvt: LDFLAGS+=-lm
48
@@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt
49
    $(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)")
50
    $(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref)
51
52
+# Pauth Tests
53
AARCH64_TESTS += pauth-1 pauth-2
54
run-pauth-%: QEMU_OPTS += -cpu max
55
56
diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target
57
index XXXXXXX..XXXXXXX 100644
58
--- a/tests/tcg/arm/Makefile.target
59
+++ b/tests/tcg/arm/Makefile.target
60
@@ -XXX,XX +XXX,XX @@ ARM_SRC=$(SRC_PATH)/tests/tcg/arm
61
# Set search path for all sources
62
VPATH         += $(ARM_SRC)
63
64
-ARM_TESTS=hello-arm test-arm-iwmmxt
65
-
66
-TESTS += $(ARM_TESTS) fcvt
67
-
68
+# Basic Hello World
69
+ARM_TESTS = hello-arm
70
hello-arm: CFLAGS+=-marm -ffreestanding
71
hello-arm: LDFLAGS+=-nostdlib
72
73
+# IWMXT floating point extensions
74
+ARM_TESTS += test-arm-iwmmxt
75
test-arm-iwmmxt: CFLAGS+=-marm -march=iwmmxt -mabi=aapcs -mfpu=fpv4-sp-d16
76
test-arm-iwmmxt: test-arm-iwmmxt.S
77
    $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS)
78
79
-ifeq ($(TARGET_NAME), arm)
80
+# Float-convert Tests
81
+ARM_TESTS += fcvt
82
fcvt: LDFLAGS+=-lm
83
# fcvt: CFLAGS+=-march=armv8.2-a+fp16 -mfpu=neon-fp-armv8
84
-
85
run-fcvt: fcvt
86
    $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)")
87
    $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref)
88
-endif
89
+
90
+TESTS += $(ARM_TESTS)
91
92
# On ARM Linux only supports 4k pages
93
EXTRA_RUNS+=run-test-mmap-4096
94
--
95
2.20.1
96
97
diff view generated by jsdifflib
[PULL 3/9] target/arm: handle M-profile semihosting at translate time
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
We do this for other semihosting calls so we might as well do it for
4
M-profile as well.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20190913151845.12582-3-alex.bennee@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/m_helper.c | 18 ++++++------------
13
target/arm/translate.c | 11 ++++++++++-
14
2 files changed, 16 insertions(+), 13 deletions(-)
15
16
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/m_helper.c
19
+++ b/target/arm/m_helper.c
20
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
21
break;
22
}
23
break;
24
+ case EXCP_SEMIHOST:
25
+ qemu_log_mask(CPU_LOG_INT,
26
+ "...handling as semihosting call 0x%x\n",
27
+ env->regs[0]);
28
+ env->regs[0] = do_arm_semihosting(env);
29
+ return;
30
case EXCP_BKPT:
31
- if (semihosting_enabled()) {
32
- int nr;
33
- nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff;
34
- if (nr == 0xab) {
35
- env->regs[15] += 2;
36
- qemu_log_mask(CPU_LOG_INT,
37
- "...handling as semihosting call 0x%x\n",
38
- env->regs[0]);
39
- env->regs[0] = do_arm_semihosting(env);
40
- return;
41
- }
42
- }
43
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false);
44
break;
45
case EXCP_IRQ:
46
diff --git a/target/arm/translate.c b/target/arm/translate.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/translate.c
49
+++ b/target/arm/translate.c
50
@@ -XXX,XX +XXX,XX @@ static bool trans_BKPT(DisasContext *s, arg_BKPT *a)
51
if (!ENABLE_ARCH_5) {
52
return false;
53
}
54
- gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false));
55
+ if (arm_dc_feature(s, ARM_FEATURE_M) &&
56
+ semihosting_enabled() &&
57
+#ifndef CONFIG_USER_ONLY
58
+ !IS_USER(s) &&
59
+#endif
60
+ (a->imm == 0xab)) {
61
+ gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST);
62
+ } else {
63
+ gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false));
64
+ }
65
return true;
66
}
67
68
--
69
2.20.1
70
71
diff view generated by jsdifflib
[PULL 4/9] target/arm: handle A-profile semihosting at translate time
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
As for the other semihosting calls we can resolve this at translate
4
time.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20190913151845.12582-4-alex.bennee@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate.c | 19 +++++++++++++++----
12
1 file changed, 15 insertions(+), 4 deletions(-)
13
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
17
+++ b/target/arm/translate.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a)
19
}
20
21
/*
22
- * Supervisor call
23
+ * Supervisor call - both T32 & A32 come here so we need to check
24
+ * which mode we are in when checking for semihosting.
25
*/
26
27
static bool trans_SVC(DisasContext *s, arg_SVC *a)
28
{
29
- gen_set_pc_im(s, s->base.pc_next);
30
- s->svc_imm = a->imm;
31
- s->base.is_jmp = DISAS_SWI;
32
+ const uint32_t semihost_imm = s->thumb ? 0xab : 0x123456;
33
+
34
+ if (!arm_dc_feature(s, ARM_FEATURE_M) && semihosting_enabled() &&
35
+#ifndef CONFIG_USER_ONLY
36
+ !IS_USER(s) &&
37
+#endif
38
+ (a->imm == semihost_imm)) {
39
+ gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST);
40
+ } else {
41
+ gen_set_pc_im(s, s->base.pc_next);
42
+ s->svc_imm = a->imm;
43
+ s->base.is_jmp = DISAS_SWI;
44
+ }
45
return true;
46
}
47
48
--
49
2.20.1
50
51
diff view generated by jsdifflib
[PULL 5/9] target/arm: remove run time semihosting checks
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
Now we do all our checking and use a common EXCP_SEMIHOST for
4
semihosting operations we can make helper code a lot simpler.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20190913151845.12582-5-alex.bennee@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/helper.c | 96 +++++++++++----------------------------------
12
1 file changed, 22 insertions(+), 74 deletions(-)
13
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
17
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
19
new_el, env->pc, pstate_read(env));
20
}
21
22
-static inline bool check_for_semihosting(CPUState *cs)
23
-{
24
+/*
25
+ * Do semihosting call and set the appropriate return value. All the
26
+ * permission and validity checks have been done at translate time.
27
+ *
28
+ * We only see semihosting exceptions in TCG only as they are not
29
+ * trapped to the hypervisor in KVM.
30
+ */
31
#ifdef CONFIG_TCG
32
- /* Check whether this exception is a semihosting call; if so
33
- * then handle it and return true; otherwise return false.
34
- */
35
+static void handle_semihosting(CPUState *cs)
36
+{
37
ARMCPU *cpu = ARM_CPU(cs);
38
CPUARMState *env = &cpu->env;
39
40
if (is_a64(env)) {
41
- if (cs->exception_index == EXCP_SEMIHOST) {
42
- /* This is always the 64-bit semihosting exception.
43
- * The "is this usermode" and "is semihosting enabled"
44
- * checks have been done at translate time.
45
- */
46
- qemu_log_mask(CPU_LOG_INT,
47
- "...handling as semihosting call 0x%" PRIx64 "\n",
48
- env->xregs[0]);
49
- env->xregs[0] = do_arm_semihosting(env);
50
- return true;
51
- }
52
- return false;
53
+ qemu_log_mask(CPU_LOG_INT,
54
+ "...handling as semihosting call 0x%" PRIx64 "\n",
55
+ env->xregs[0]);
56
+ env->xregs[0] = do_arm_semihosting(env);
57
} else {
58
- uint32_t imm;
59
-
60
- /* Only intercept calls from privileged modes, to provide some
61
- * semblance of security.
62
- */
63
- if (cs->exception_index != EXCP_SEMIHOST &&
64
- (!semihosting_enabled() ||
65
- ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) {
66
- return false;
67
- }
68
-
69
- switch (cs->exception_index) {
70
- case EXCP_SEMIHOST:
71
- /* This is always a semihosting call; the "is this usermode"
72
- * and "is semihosting enabled" checks have been done at
73
- * translate time.
74
- */
75
- break;
76
- case EXCP_SWI:
77
- /* Check for semihosting interrupt. */
78
- if (env->thumb) {
79
- imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env))
80
- & 0xff;
81
- if (imm == 0xab) {
82
- break;
83
- }
84
- } else {
85
- imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env))
86
- & 0xffffff;
87
- if (imm == 0x123456) {
88
- break;
89
- }
90
- }
91
- return false;
92
- case EXCP_BKPT:
93
- /* See if this is a semihosting syscall. */
94
- if (env->thumb) {
95
- imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env))
96
- & 0xff;
97
- if (imm == 0xab) {
98
- env->regs[15] += 2;
99
- break;
100
- }
101
- }
102
- return false;
103
- default:
104
- return false;
105
- }
106
-
107
qemu_log_mask(CPU_LOG_INT,
108
"...handling as semihosting call 0x%x\n",
109
env->regs[0]);
110
env->regs[0] = do_arm_semihosting(env);
111
- return true;
112
}
113
-#else
114
- return false;
115
-#endif
116
}
117
+#endif
118
119
/* Handle a CPU exception for A and R profile CPUs.
120
* Do any appropriate logging, handle PSCI calls, and then hand off
121
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
122
return;
123
}
124
125
- /* Semihosting semantics depend on the register width of the
126
- * code that caused the exception, not the target exception level,
127
- * so must be handled here.
128
+ /*
129
+ * Semihosting semantics depend on the register width of the code
130
+ * that caused the exception, not the target exception level, so
131
+ * must be handled here.
132
*/
133
- if (check_for_semihosting(cs)) {
134
+#ifdef CONFIG_TCG
135
+ if (cs->exception_index == EXCP_SEMIHOST) {
136
+ handle_semihosting(cs);
137
return;
138
}
139
+#endif
140
141
/* Hooks may change global state so BQL should be held, also the
142
* BQL needs to be held for any modification of
143
--
144
2.20.1
145
146
diff view generated by jsdifflib
[PULL 6/9] target/arm: remove run-time semihosting checks for linux-user
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
Now we do all our checking at translate time we can make cpu_loop a
4
little bit simpler. We also introduce a simple linux-user semihosting
5
test case to defend the functionality. The out-of-tree softmmu based
6
semihosting tests are still more comprehensive.
7
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20190913151845.12582-6-alex.bennee@linaro.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
linux-user/arm/target_syscall.h | 3 ---
14
linux-user/arm/cpu_loop.c | 3 ---
15
2 files changed, 6 deletions(-)
16
17
diff --git a/linux-user/arm/target_syscall.h b/linux-user/arm/target_syscall.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/linux-user/arm/target_syscall.h
20
+++ b/linux-user/arm/target_syscall.h
21
@@ -XXX,XX +XXX,XX @@ struct target_pt_regs {
22
#define ARM_NR_set_tls     (ARM_NR_BASE + 5)
23
#define ARM_NR_get_tls (ARM_NR_BASE + 6)
24
25
-#define ARM_NR_semihosting     0x123456
26
-#define ARM_NR_thumb_semihosting 0xAB
27
-
28
#if defined(TARGET_WORDS_BIGENDIAN)
29
#define UNAME_MACHINE "armv5teb"
30
#else
31
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/linux-user/arm/cpu_loop.c
34
+++ b/linux-user/arm/cpu_loop.c
35
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
36
37
if (n == ARM_NR_cacheflush) {
38
/* nop */
39
- } else if (n == ARM_NR_semihosting
40
- || n == ARM_NR_thumb_semihosting) {
41
- env->regs[0] = do_arm_semihosting (env);
42
} else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
43
/* linux syscall */
44
if (env->thumb || n == 0) {
45
--
46
2.20.1
47
48
diff view generated by jsdifflib
[PULL 7/9] tests/tcg: add linux-user semihosting smoke test for ARM
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
We already use semihosting for the system stuff so this is a simple
4
smoke test to ensure we are working OK on linux-user.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20190913151845.12582-7-alex.bennee@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
tests/tcg/aarch64/Makefile.target | 5 ++++
12
tests/tcg/arm/Makefile.target | 5 ++++
13
tests/tcg/arm/semihosting.c | 45 +++++++++++++++++++++++++++++++
14
3 files changed, 55 insertions(+)
15
create mode 100644 tests/tcg/arm/semihosting.c
16
17
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
18
index XXXXXXX..XXXXXXX 100644
19
--- a/tests/tcg/aarch64/Makefile.target
20
+++ b/tests/tcg/aarch64/Makefile.target
21
@@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt
22
AARCH64_TESTS += pauth-1 pauth-2
23
run-pauth-%: QEMU_OPTS += -cpu max
24
25
+# Semihosting smoke test for linux-user
26
+AARCH64_TESTS += semihosting
27
+run-semihosting: semihosting
28
+    $(call run-test,$<,$(QEMU) $< 2> $<.err, "$< on $(TARGET_NAME)")
29
+
30
TESTS += $(AARCH64_TESTS)
31
diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target
32
index XXXXXXX..XXXXXXX 100644
33
--- a/tests/tcg/arm/Makefile.target
34
+++ b/tests/tcg/arm/Makefile.target
35
@@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt
36
    $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)")
37
    $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref)
38
39
+# Semihosting smoke test for linux-user
40
+ARM_TESTS += semihosting
41
+run-semihosting: semihosting
42
+    $(call run-test,$<,$(QEMU) $< 2> $<.err, "$< on $(TARGET_NAME)")
43
+
44
TESTS += $(ARM_TESTS)
45
46
# On ARM Linux only supports 4k pages
47
diff --git a/tests/tcg/arm/semihosting.c b/tests/tcg/arm/semihosting.c
48
new file mode 100644
49
index XXXXXXX..XXXXXXX
50
--- /dev/null
51
+++ b/tests/tcg/arm/semihosting.c
52
@@ -XXX,XX +XXX,XX @@
53
+/*
54
+ * linux-user semihosting checks
55
+ *
56
+ * Copyright (c) 2019
57
+ * Written by Alex Bennée <alex.bennee@linaro.org>
58
+ *
59
+ * SPDX-License-Identifier: GPL-3.0-or-later
60
+ */
61
+
62
+#include <stdint.h>
63
+
64
+#define SYS_WRITE0 0x04
65
+#define SYS_REPORTEXC 0x18
66
+
67
+void __semi_call(uintptr_t type, uintptr_t arg0)
68
+{
69
+#if defined(__arm__)
70
+ register uintptr_t t asm("r0") = type;
71
+ register uintptr_t a0 asm("r1") = arg0;
72
+ asm("svc 0xab"
73
+ : /* no return */
74
+ : "r" (t), "r" (a0));
75
+#else
76
+ register uintptr_t t asm("x0") = type;
77
+ register uintptr_t a0 asm("x1") = arg0;
78
+ asm("hlt 0xf000"
79
+ : /* no return */
80
+ : "r" (t), "r" (a0));
81
+#endif
82
+}
83
+
84
+int main(int argc, char *argv[argc])
85
+{
86
+#if defined(__arm__)
87
+ uintptr_t exit_code = 0x20026;
88
+#else
89
+ uintptr_t exit_block[2] = {0x20026, 0};
90
+ uintptr_t exit_code = (uintptr_t) &exit_block;
91
+#endif
92
+
93
+ __semi_call(SYS_WRITE0, (uintptr_t) "Hello World");
94
+ __semi_call(SYS_REPORTEXC, exit_code);
95
+ /* if we get here we failed */
96
+ return -1;
97
+}
98
--
99
2.20.1
100
101
diff view generated by jsdifflib
[PULL 8/9] hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots
Deleted patch
1
If we're booting a Linux kernel directly into Non-Secure
2
state on a CPU which has Secure state, then make sure we
3
set the NSACR CP11 and CP10 bits, so that Non-Secure is allowed
4
to access the FPU. Otherwise an AArch32 kernel will UNDEF as
5
soon as it tries to use the FPU.
6
1
7
It used to not matter that we didn't do this until commit
8
fc1120a7f5f2d4b6, where we implemented actually honouring
9
these NSACR bits.
10
11
The problem only exists for CPUs where EL3 is AArch32; the
12
equivalent AArch64 trap bits are in CPTR_EL3 and are "0 to
13
not trap, 1 to trap", so the reset value of the register
14
permits NS access, unlike NSACR.
15
16
Fixes: fc1120a7f5
17
Fixes: https://bugs.launchpad.net/qemu/+bug/1844597
18
Cc: qemu-stable@nongnu.org
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 20190920174039.3916-1-peter.maydell@linaro.org
22
---
23
hw/arm/boot.c | 2 ++
24
1 file changed, 2 insertions(+)
25
26
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/arm/boot.c
29
+++ b/hw/arm/boot.c
30
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
31
(cs != first_cpu || !info->secure_board_setup)) {
32
/* Linux expects non-secure state */
33
env->cp15.scr_el3 |= SCR_NS;
34
+ /* Set NSACR.{CP11,CP10} so NS can access the FPU */
35
+ env->cp15.nsacr |= 3 << 10;
36
}
37
}
38
39
--
40
2.20.1
41
42
diff view generated by jsdifflib
[PULL 9/9] hw/arm/boot: Use the IEC binary prefix definitions
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
IEC binary prefixes ease code review: the unit is explicit.
4
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
7
Reviewed-by: Thomas Huth <thuth@redhat.com>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190923131108.21459-1-philmd@redhat.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/boot.c | 10 +++++-----
13
1 file changed, 5 insertions(+), 5 deletions(-)
14
15
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/boot.c
18
+++ b/hw/arm/boot.c
19
@@ -XXX,XX +XXX,XX @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
20
goto fail;
21
}
22
23
- if (scells < 2 && binfo->ram_size >= (1ULL << 32)) {
24
+ if (scells < 2 && binfo->ram_size >= 4 * GiB) {
25
/* This is user error so deserves a friendlier error message
26
* than the failure of setprop_sized_cells would provide
27
*/
28
@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
29
* we might still make a bad choice here.
30
*/
31
info->initrd_start = info->loader_start +
32
- MIN(info->ram_size / 2, 128 * 1024 * 1024);
33
+ MIN(info->ram_size / 2, 128 * MiB);
34
if (image_high_addr) {
35
info->initrd_start = MAX(info->initrd_start, image_high_addr);
36
}
37
@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
38
*
39
* Let's play safe and prealign it to 2MB to give us some space.
40
*/
41
- align = 2 * 1024 * 1024;
42
+ align = 2 * MiB;
43
} else {
44
/*
45
* Some 32bit kernels will trash anything in the 4K page the
46
* initrd ends in, so make sure the DTB isn't caught up in that.
47
*/
48
- align = 4096;
49
+ align = 4 * KiB;
50
}
51
52
/* Place the DTB after the initrd in memory with alignment. */
53
@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
54
info->loader_start + KERNEL_ARGS_ADDR;
55
fixupcontext[FIXUP_ARGPTR_HI] =
56
(info->loader_start + KERNEL_ARGS_ADDR) >> 32;
57
- if (info->ram_size >= (1ULL << 32)) {
58
+ if (info->ram_size >= 4 * GiB) {
59
error_report("RAM size must be less than 4GB to boot"
60
" Linux kernel using ATAGS (try passing a device tree"
61
" using -dtb)");
62
--
63
2.20.1
64
65
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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