1 | target-arm queue: nothing major here, but no point | 1 | Arm queue; bugfixes only. |
---|---|---|---|
2 | sitting on them waiting for more stuff to come along. | ||
3 | 2 | ||
4 | thanks | 3 | thanks |
5 | -- PMM | 4 | -- PMM |
6 | 5 | ||
7 | The following changes since commit 1329132d28bf14b9508f7a1f04a2c63422bc3f99: | 6 | The following changes since commit 48aa8f0ac536db3550a35c295ff7de94e4c33739: |
8 | 7 | ||
9 | Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2019-09-26 16:14:03 +0100) | 8 | Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2020-11-16' into staging (2020-11-17 11:07:00 +0000) |
10 | 9 | ||
11 | are available in the Git repository at: | 10 | are available in the Git repository at: |
12 | 11 | ||
13 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190927 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201117 |
14 | 13 | ||
15 | for you to fetch changes up to e4e34855e658b78ecac50a651cc847662ff02cfd: | 14 | for you to fetch changes up to ab135622cf478585bdfcb68b85e4a817d74a0c42: |
16 | 15 | ||
17 | hw/arm/boot: Use the IEC binary prefix definitions (2019-09-27 11:44:39 +0100) | 16 | tmp105: Correct handling of temperature limit checks (2020-11-17 12:56:33 +0000) |
18 | 17 | ||
19 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
20 | target-arm queue: | 19 | target-arm queue: |
21 | * Fix the CBAR register implementation for Cortex-A53, | 20 | * hw/arm/virt: ARM_VIRT must select ARM_GIC |
22 | Cortex-A57, Cortex-A72 | 21 | * exynos: Fix bad printf format specifiers |
23 | * Fix direct booting of Linux kernels on emulated CPUs | 22 | * hw/input/ps2.c: Remove remnants of printf debug |
24 | which have an AArch32 EL3 (incorrect NSACR settings | 23 | * target/openrisc: Remove dead code attempting to check "is timer disabled" |
25 | meant they could not access the FPU) | 24 | * register: Remove unnecessary NULL check |
26 | * semihosting cleanup: do more work at translate time | 25 | * util/cutils: Fix Coverity array overrun in freq_to_str() |
27 | and less work at runtime | 26 | * configure: Make "does libgio work" test pull in some actual functions |
27 | * tmp105: reset the T_low and T_High registers | ||
28 | * tmp105: Correct handling of temperature limit checks | ||
28 | 29 | ||
29 | ---------------------------------------------------------------- | 30 | ---------------------------------------------------------------- |
30 | Alex Bennée (6): | 31 | Alex Chen (1): |
31 | tests/tcg: clean-up some comments after the de-tangling | 32 | exynos: Fix bad printf format specifiers |
32 | target/arm: handle M-profile semihosting at translate time | ||
33 | target/arm: handle A-profile semihosting at translate time | ||
34 | target/arm: remove run time semihosting checks | ||
35 | target/arm: remove run-time semihosting checks for linux-user | ||
36 | tests/tcg: add linux-user semihosting smoke test for ARM | ||
37 | 33 | ||
38 | Luc Michel (1): | 34 | Alistair Francis (1): |
39 | target/arm: fix CBAR register for AArch64 CPUs | 35 | register: Remove unnecessary NULL check |
40 | 36 | ||
41 | Peter Maydell (1): | 37 | Andrew Jones (1): |
42 | hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots | 38 | hw/arm/virt: ARM_VIRT must select ARM_GIC |
39 | |||
40 | Peter Maydell (5): | ||
41 | hw/input/ps2.c: Remove remnants of printf debug | ||
42 | target/openrisc: Remove dead code attempting to check "is timer disabled" | ||
43 | configure: Make "does libgio work" test pull in some actual functions | ||
44 | hw/misc/tmp105: reset the T_low and T_High registers | ||
45 | tmp105: Correct handling of temperature limit checks | ||
43 | 46 | ||
44 | Philippe Mathieu-Daudé (1): | 47 | Philippe Mathieu-Daudé (1): |
45 | hw/arm/boot: Use the IEC binary prefix definitions | 48 | util/cutils: Fix Coverity array overrun in freq_to_str() |
46 | 49 | ||
47 | tests/tcg/Makefile.target | 7 ++- | 50 | configure | 11 +++++-- |
48 | tests/tcg/aarch64/Makefile.target | 8 ++- | 51 | hw/misc/tmp105.h | 7 +++++ |
49 | tests/tcg/arm/Makefile.target | 20 ++++--- | 52 | hw/core/register.c | 4 --- |
50 | linux-user/arm/target_syscall.h | 3 - | 53 | hw/input/ps2.c | 9 ------ |
51 | hw/arm/boot.c | 12 ++-- | 54 | hw/misc/tmp105.c | 73 ++++++++++++++++++++++++++++++++++++++------ |
52 | linux-user/arm/cpu_loop.c | 3 - | 55 | hw/timer/exynos4210_mct.c | 4 +-- |
53 | target/arm/helper.c | 115 +++++++++++++------------------------- | 56 | hw/timer/exynos4210_pwm.c | 8 ++--- |
54 | target/arm/m_helper.c | 18 ++---- | 57 | target/openrisc/sys_helper.c | 3 -- |
55 | target/arm/translate.c | 30 ++++++++-- | 58 | util/cutils.c | 3 +- |
56 | tests/tcg/arm/semihosting.c | 45 +++++++++++++++ | 59 | hw/arm/Kconfig | 1 + |
57 | 10 files changed, 146 insertions(+), 115 deletions(-) | 60 | 10 files changed, 89 insertions(+), 34 deletions(-) |
58 | create mode 100644 tests/tcg/arm/semihosting.c | ||
59 | 61 | diff view generated by jsdifflib |
1 | From: Alex Bennée <alex.bennee@linaro.org> | 1 | From: Andrew Jones <drjones@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | We already use semihosting for the system stuff so this is a simple | 3 | The removal of the selection of A15MPCORE from ARM_VIRT also |
4 | smoke test to ensure we are working OK on linux-user. | 4 | removed what A15MPCORE selects, ARM_GIC. We still need ARM_GIC. |
5 | 5 | ||
6 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | 6 | Fixes: bec3c97e0cf9 ("hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals") |
7 | Message-id: 20190913151845.12582-7-alex.bennee@linaro.org | 7 | Reported-by: Miroslav Rezanina <mrezanin@redhat.com> |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Andrew Jones <drjones@redhat.com> |
9 | Reviewed-by: Miroslav Rezanina <mrezanin@redhat.com> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
11 | Message-id: 20201111143440.112763-1-drjones@redhat.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 13 | --- |
11 | tests/tcg/aarch64/Makefile.target | 5 ++++ | 14 | hw/arm/Kconfig | 1 + |
12 | tests/tcg/arm/Makefile.target | 5 ++++ | 15 | 1 file changed, 1 insertion(+) |
13 | tests/tcg/arm/semihosting.c | 45 +++++++++++++++++++++++++++++++ | ||
14 | 3 files changed, 55 insertions(+) | ||
15 | create mode 100644 tests/tcg/arm/semihosting.c | ||
16 | 16 | ||
17 | diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target | 17 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig |
18 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/tests/tcg/aarch64/Makefile.target | 19 | --- a/hw/arm/Kconfig |
20 | +++ b/tests/tcg/aarch64/Makefile.target | 20 | +++ b/hw/arm/Kconfig |
21 | @@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt | 21 | @@ -XXX,XX +XXX,XX @@ config ARM_VIRT |
22 | AARCH64_TESTS += pauth-1 pauth-2 | 22 | imply VFIO_PLATFORM |
23 | run-pauth-%: QEMU_OPTS += -cpu max | 23 | imply VFIO_XGMAC |
24 | 24 | imply TPM_TIS_SYSBUS | |
25 | +# Semihosting smoke test for linux-user | 25 | + select ARM_GIC |
26 | +AARCH64_TESTS += semihosting | 26 | select ACPI |
27 | +run-semihosting: semihosting | 27 | select ARM_SMMUV3 |
28 | + $(call run-test,$<,$(QEMU) $< 2> $<.err, "$< on $(TARGET_NAME)") | 28 | select GPIO_KEY |
29 | + | ||
30 | TESTS += $(AARCH64_TESTS) | ||
31 | diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/tests/tcg/arm/Makefile.target | ||
34 | +++ b/tests/tcg/arm/Makefile.target | ||
35 | @@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt | ||
36 | $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") | ||
37 | $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) | ||
38 | |||
39 | +# Semihosting smoke test for linux-user | ||
40 | +ARM_TESTS += semihosting | ||
41 | +run-semihosting: semihosting | ||
42 | + $(call run-test,$<,$(QEMU) $< 2> $<.err, "$< on $(TARGET_NAME)") | ||
43 | + | ||
44 | TESTS += $(ARM_TESTS) | ||
45 | |||
46 | # On ARM Linux only supports 4k pages | ||
47 | diff --git a/tests/tcg/arm/semihosting.c b/tests/tcg/arm/semihosting.c | ||
48 | new file mode 100644 | ||
49 | index XXXXXXX..XXXXXXX | ||
50 | --- /dev/null | ||
51 | +++ b/tests/tcg/arm/semihosting.c | ||
52 | @@ -XXX,XX +XXX,XX @@ | ||
53 | +/* | ||
54 | + * linux-user semihosting checks | ||
55 | + * | ||
56 | + * Copyright (c) 2019 | ||
57 | + * Written by Alex Bennée <alex.bennee@linaro.org> | ||
58 | + * | ||
59 | + * SPDX-License-Identifier: GPL-3.0-or-later | ||
60 | + */ | ||
61 | + | ||
62 | +#include <stdint.h> | ||
63 | + | ||
64 | +#define SYS_WRITE0 0x04 | ||
65 | +#define SYS_REPORTEXC 0x18 | ||
66 | + | ||
67 | +void __semi_call(uintptr_t type, uintptr_t arg0) | ||
68 | +{ | ||
69 | +#if defined(__arm__) | ||
70 | + register uintptr_t t asm("r0") = type; | ||
71 | + register uintptr_t a0 asm("r1") = arg0; | ||
72 | + asm("svc 0xab" | ||
73 | + : /* no return */ | ||
74 | + : "r" (t), "r" (a0)); | ||
75 | +#else | ||
76 | + register uintptr_t t asm("x0") = type; | ||
77 | + register uintptr_t a0 asm("x1") = arg0; | ||
78 | + asm("hlt 0xf000" | ||
79 | + : /* no return */ | ||
80 | + : "r" (t), "r" (a0)); | ||
81 | +#endif | ||
82 | +} | ||
83 | + | ||
84 | +int main(int argc, char *argv[argc]) | ||
85 | +{ | ||
86 | +#if defined(__arm__) | ||
87 | + uintptr_t exit_code = 0x20026; | ||
88 | +#else | ||
89 | + uintptr_t exit_block[2] = {0x20026, 0}; | ||
90 | + uintptr_t exit_code = (uintptr_t) &exit_block; | ||
91 | +#endif | ||
92 | + | ||
93 | + __semi_call(SYS_WRITE0, (uintptr_t) "Hello World"); | ||
94 | + __semi_call(SYS_REPORTEXC, exit_code); | ||
95 | + /* if we get here we failed */ | ||
96 | + return -1; | ||
97 | +} | ||
98 | -- | 29 | -- |
99 | 2.20.1 | 30 | 2.20.1 |
100 | 31 | ||
101 | 32 | diff view generated by jsdifflib |
1 | From: Alex Bennée <alex.bennee@linaro.org> | 1 | From: Alex Chen <alex.chen@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | Now we do all our checking at translate time we can make cpu_loop a | 3 | We should use printf format specifier "%u" instead of "%d" for |
4 | little bit simpler. We also introduce a simple linux-user semihosting | 4 | argument of type "unsigned int". |
5 | test case to defend the functionality. The out-of-tree softmmu based | ||
6 | semihosting tests are still more comprehensive. | ||
7 | 5 | ||
8 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | 6 | Reported-by: Euler Robot <euler.robot@huawei.com> |
9 | Message-id: 20190913151845.12582-6-alex.bennee@linaro.org | 7 | Signed-off-by: Alex Chen <alex.chen@huawei.com> |
8 | Message-id: 20201111073651.72804-1-alex.chen@huawei.com | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 11 | --- |
13 | linux-user/arm/target_syscall.h | 3 --- | 12 | hw/timer/exynos4210_mct.c | 4 ++-- |
14 | linux-user/arm/cpu_loop.c | 3 --- | 13 | hw/timer/exynos4210_pwm.c | 8 ++++---- |
15 | 2 files changed, 6 deletions(-) | 14 | 2 files changed, 6 insertions(+), 6 deletions(-) |
16 | 15 | ||
17 | diff --git a/linux-user/arm/target_syscall.h b/linux-user/arm/target_syscall.h | 16 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c |
18 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/linux-user/arm/target_syscall.h | 18 | --- a/hw/timer/exynos4210_mct.c |
20 | +++ b/linux-user/arm/target_syscall.h | 19 | +++ b/hw/timer/exynos4210_mct.c |
21 | @@ -XXX,XX +XXX,XX @@ struct target_pt_regs { | 20 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gcomp_raise_irq(void *opaque, uint32_t id) |
22 | #define ARM_NR_set_tls (ARM_NR_BASE + 5) | 21 | /* If CSTAT is pending and IRQ is enabled */ |
23 | #define ARM_NR_get_tls (ARM_NR_BASE + 6) | 22 | if ((s->reg.int_cstat & G_INT_CSTAT_COMP(id)) && |
24 | 23 | (s->reg.int_enb & G_INT_ENABLE(id))) { | |
25 | -#define ARM_NR_semihosting 0x123456 | 24 | - DPRINTF("gcmp timer[%d] IRQ\n", id); |
26 | -#define ARM_NR_thumb_semihosting 0xAB | 25 | + DPRINTF("gcmp timer[%u] IRQ\n", id); |
27 | - | 26 | qemu_irq_raise(s->irq[id]); |
28 | #if defined(TARGET_WORDS_BIGENDIAN) | 27 | } |
29 | #define UNAME_MACHINE "armv5teb" | 28 | } |
30 | #else | 29 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s) |
31 | diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c | 30 | MCT_CFG_GET_DIVIDER(s->reg_mct_cfg)); |
31 | |||
32 | if (freq != s->freq) { | ||
33 | - DPRINTF("freq=%dHz\n", s->freq); | ||
34 | + DPRINTF("freq=%uHz\n", s->freq); | ||
35 | |||
36 | /* global timer */ | ||
37 | tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq); | ||
38 | diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | 39 | index XXXXXXX..XXXXXXX 100644 |
33 | --- a/linux-user/arm/cpu_loop.c | 40 | --- a/hw/timer/exynos4210_pwm.c |
34 | +++ b/linux-user/arm/cpu_loop.c | 41 | +++ b/hw/timer/exynos4210_pwm.c |
35 | @@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env) | 42 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id) |
36 | 43 | ||
37 | if (n == ARM_NR_cacheflush) { | 44 | if (freq != s->timer[id].freq) { |
38 | /* nop */ | 45 | ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq); |
39 | - } else if (n == ARM_NR_semihosting | 46 | - DPRINTF("freq=%dHz\n", s->timer[id].freq); |
40 | - || n == ARM_NR_thumb_semihosting) { | 47 | + DPRINTF("freq=%uHz\n", s->timer[id].freq); |
41 | - env->regs[0] = do_arm_semihosting (env); | 48 | } |
42 | } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) { | 49 | } |
43 | /* linux syscall */ | 50 | |
44 | if (env->thumb || n == 0) { | 51 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque) |
52 | uint32_t id = s->id; | ||
53 | bool cmp; | ||
54 | |||
55 | - DPRINTF("timer %d tick\n", id); | ||
56 | + DPRINTF("timer %u tick\n", id); | ||
57 | |||
58 | /* set irq status */ | ||
59 | p->reg_tint_cstat |= TINT_CSTAT_STATUS(id); | ||
60 | |||
61 | /* raise IRQ */ | ||
62 | if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) { | ||
63 | - DPRINTF("timer %d IRQ\n", id); | ||
64 | + DPRINTF("timer %u IRQ\n", id); | ||
65 | qemu_irq_raise(p->timer[id].irq); | ||
66 | } | ||
67 | |||
68 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque) | ||
69 | } | ||
70 | |||
71 | if (cmp) { | ||
72 | - DPRINTF("auto reload timer %d count to %x\n", id, | ||
73 | + DPRINTF("auto reload timer %u count to %x\n", id, | ||
74 | p->timer[id].reg_tcntb); | ||
75 | ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb); | ||
76 | ptimer_run(p->timer[id].ptimer, 1); | ||
45 | -- | 77 | -- |
46 | 2.20.1 | 78 | 2.20.1 |
47 | 79 | ||
48 | 80 | diff view generated by jsdifflib |
1 | From: Alex Bennée <alex.bennee@linaro.org> | 1 | In commit 5edab03d4040 we added tracepoints to the ps2 keyboard |
---|---|---|---|
2 | and mouse emulation. However we didn't remove all the debug-by-printf | ||
3 | support. In fact there is only one printf() remaining, and it is | ||
4 | redundant with the trace_ps2_write_mouse() event next to it. | ||
5 | Remove the printf() and the now-unused DEBUG* macros. | ||
2 | 6 | ||
3 | Now we do all our checking and use a common EXCP_SEMIHOST for | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | semihosting operations we can make helper code a lot simpler. | 8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
9 | Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> | ||
10 | Message-id: 20201101133258.4240-1-peter.maydell@linaro.org | ||
11 | --- | ||
12 | hw/input/ps2.c | 9 --------- | ||
13 | 1 file changed, 9 deletions(-) | ||
5 | 14 | ||
6 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | 15 | diff --git a/hw/input/ps2.c b/hw/input/ps2.c |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20190913151845.12582-5-alex.bennee@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/helper.c | 96 +++++++++++---------------------------------- | ||
12 | 1 file changed, 22 insertions(+), 74 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper.c | 17 | --- a/hw/input/ps2.c |
17 | +++ b/target/arm/helper.c | 18 | +++ b/hw/input/ps2.c |
18 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | 19 | @@ -XXX,XX +XXX,XX @@ |
19 | new_el, env->pc, pstate_read(env)); | 20 | |
20 | } | 21 | #include "trace.h" |
21 | 22 | ||
22 | -static inline bool check_for_semihosting(CPUState *cs) | 23 | -/* debug PC keyboard */ |
23 | -{ | 24 | -//#define DEBUG_KBD |
24 | +/* | ||
25 | + * Do semihosting call and set the appropriate return value. All the | ||
26 | + * permission and validity checks have been done at translate time. | ||
27 | + * | ||
28 | + * We only see semihosting exceptions in TCG only as they are not | ||
29 | + * trapped to the hypervisor in KVM. | ||
30 | + */ | ||
31 | #ifdef CONFIG_TCG | ||
32 | - /* Check whether this exception is a semihosting call; if so | ||
33 | - * then handle it and return true; otherwise return false. | ||
34 | - */ | ||
35 | +static void handle_semihosting(CPUState *cs) | ||
36 | +{ | ||
37 | ARMCPU *cpu = ARM_CPU(cs); | ||
38 | CPUARMState *env = &cpu->env; | ||
39 | |||
40 | if (is_a64(env)) { | ||
41 | - if (cs->exception_index == EXCP_SEMIHOST) { | ||
42 | - /* This is always the 64-bit semihosting exception. | ||
43 | - * The "is this usermode" and "is semihosting enabled" | ||
44 | - * checks have been done at translate time. | ||
45 | - */ | ||
46 | - qemu_log_mask(CPU_LOG_INT, | ||
47 | - "...handling as semihosting call 0x%" PRIx64 "\n", | ||
48 | - env->xregs[0]); | ||
49 | - env->xregs[0] = do_arm_semihosting(env); | ||
50 | - return true; | ||
51 | - } | ||
52 | - return false; | ||
53 | + qemu_log_mask(CPU_LOG_INT, | ||
54 | + "...handling as semihosting call 0x%" PRIx64 "\n", | ||
55 | + env->xregs[0]); | ||
56 | + env->xregs[0] = do_arm_semihosting(env); | ||
57 | } else { | ||
58 | - uint32_t imm; | ||
59 | - | 25 | - |
60 | - /* Only intercept calls from privileged modes, to provide some | 26 | -/* debug PC keyboard : only mouse */ |
61 | - * semblance of security. | 27 | -//#define DEBUG_MOUSE |
62 | - */ | ||
63 | - if (cs->exception_index != EXCP_SEMIHOST && | ||
64 | - (!semihosting_enabled() || | ||
65 | - ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) { | ||
66 | - return false; | ||
67 | - } | ||
68 | - | 28 | - |
69 | - switch (cs->exception_index) { | 29 | /* Keyboard Commands */ |
70 | - case EXCP_SEMIHOST: | 30 | #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ |
71 | - /* This is always a semihosting call; the "is this usermode" | 31 | #define KBD_CMD_ECHO 0xEE |
72 | - * and "is semihosting enabled" checks have been done at | 32 | @@ -XXX,XX +XXX,XX @@ void ps2_write_mouse(void *opaque, int val) |
73 | - * translate time. | 33 | PS2MouseState *s = (PS2MouseState *)opaque; |
74 | - */ | 34 | |
75 | - break; | 35 | trace_ps2_write_mouse(opaque, val); |
76 | - case EXCP_SWI: | 36 | -#ifdef DEBUG_MOUSE |
77 | - /* Check for semihosting interrupt. */ | 37 | - printf("kbd: write mouse 0x%02x\n", val); |
78 | - if (env->thumb) { | ||
79 | - imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env)) | ||
80 | - & 0xff; | ||
81 | - if (imm == 0xab) { | ||
82 | - break; | ||
83 | - } | ||
84 | - } else { | ||
85 | - imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env)) | ||
86 | - & 0xffffff; | ||
87 | - if (imm == 0x123456) { | ||
88 | - break; | ||
89 | - } | ||
90 | - } | ||
91 | - return false; | ||
92 | - case EXCP_BKPT: | ||
93 | - /* See if this is a semihosting syscall. */ | ||
94 | - if (env->thumb) { | ||
95 | - imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) | ||
96 | - & 0xff; | ||
97 | - if (imm == 0xab) { | ||
98 | - env->regs[15] += 2; | ||
99 | - break; | ||
100 | - } | ||
101 | - } | ||
102 | - return false; | ||
103 | - default: | ||
104 | - return false; | ||
105 | - } | ||
106 | - | ||
107 | qemu_log_mask(CPU_LOG_INT, | ||
108 | "...handling as semihosting call 0x%x\n", | ||
109 | env->regs[0]); | ||
110 | env->regs[0] = do_arm_semihosting(env); | ||
111 | - return true; | ||
112 | } | ||
113 | -#else | ||
114 | - return false; | ||
115 | -#endif | 38 | -#endif |
116 | } | 39 | switch(s->common.write_cmd) { |
117 | +#endif | 40 | default: |
118 | 41 | case -1: | |
119 | /* Handle a CPU exception for A and R profile CPUs. | ||
120 | * Do any appropriate logging, handle PSCI calls, and then hand off | ||
121 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs) | ||
122 | return; | ||
123 | } | ||
124 | |||
125 | - /* Semihosting semantics depend on the register width of the | ||
126 | - * code that caused the exception, not the target exception level, | ||
127 | - * so must be handled here. | ||
128 | + /* | ||
129 | + * Semihosting semantics depend on the register width of the code | ||
130 | + * that caused the exception, not the target exception level, so | ||
131 | + * must be handled here. | ||
132 | */ | ||
133 | - if (check_for_semihosting(cs)) { | ||
134 | +#ifdef CONFIG_TCG | ||
135 | + if (cs->exception_index == EXCP_SEMIHOST) { | ||
136 | + handle_semihosting(cs); | ||
137 | return; | ||
138 | } | ||
139 | +#endif | ||
140 | |||
141 | /* Hooks may change global state so BQL should be held, also the | ||
142 | * BQL needs to be held for any modification of | ||
143 | -- | 42 | -- |
144 | 2.20.1 | 43 | 2.20.1 |
145 | 44 | ||
146 | 45 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | In the mtspr helper we attempt to check for "is the timer disabled" |
---|---|---|---|
2 | with "if (env->ttmr & TIMER_NONE)". This is wrong because TIMER_NONE | ||
3 | is zero and the condition is always false (Coverity complains about | ||
4 | the dead code.) | ||
2 | 5 | ||
3 | IEC binary prefixes ease code review: the unit is explicit. | 6 | The correct check would be to test whether the TTMR_M field in the |
7 | register is equal to TIMER_NONE instead. However, the | ||
8 | cpu_openrisc_timer_update() function checks whether the timer is | ||
9 | enabled (it looks at cpu->env.is_counting, which is set to 0 via | ||
10 | cpu_openrisc_count_stop() when the TTMR_M field is set to | ||
11 | TIMER_NONE), so there's no need to check for "timer disabled" in the | ||
12 | target/openrisc code. Instead, simply remove the dead code. | ||
4 | 13 | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 14 | Fixes: Coverity CID 1005812 |
6 | Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> | ||
7 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
8 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
9 | Message-id: 20190923131108.21459-1-philmd@redhat.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Acked-by: Stafford Horne <shorne@gmail.com> | ||
17 | Message-id: 20201103114654.18540-1-peter.maydell@linaro.org | ||
11 | --- | 18 | --- |
12 | hw/arm/boot.c | 10 +++++----- | 19 | target/openrisc/sys_helper.c | 3 --- |
13 | 1 file changed, 5 insertions(+), 5 deletions(-) | 20 | 1 file changed, 3 deletions(-) |
14 | 21 | ||
15 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | 22 | diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c |
16 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/boot.c | 24 | --- a/target/openrisc/sys_helper.c |
18 | +++ b/hw/arm/boot.c | 25 | +++ b/target/openrisc/sys_helper.c |
19 | @@ -XXX,XX +XXX,XX @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, | 26 | @@ -XXX,XX +XXX,XX @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) |
20 | goto fail; | 27 | |
21 | } | 28 | case TO_SPR(10, 1): /* TTCR */ |
22 | 29 | cpu_openrisc_count_set(cpu, rb); | |
23 | - if (scells < 2 && binfo->ram_size >= (1ULL << 32)) { | 30 | - if (env->ttmr & TIMER_NONE) { |
24 | + if (scells < 2 && binfo->ram_size >= 4 * GiB) { | 31 | - return; |
25 | /* This is user error so deserves a friendlier error message | 32 | - } |
26 | * than the failure of setprop_sized_cells would provide | 33 | cpu_openrisc_timer_update(cpu); |
27 | */ | 34 | break; |
28 | @@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, | 35 | #endif |
29 | * we might still make a bad choice here. | ||
30 | */ | ||
31 | info->initrd_start = info->loader_start + | ||
32 | - MIN(info->ram_size / 2, 128 * 1024 * 1024); | ||
33 | + MIN(info->ram_size / 2, 128 * MiB); | ||
34 | if (image_high_addr) { | ||
35 | info->initrd_start = MAX(info->initrd_start, image_high_addr); | ||
36 | } | ||
37 | @@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, | ||
38 | * | ||
39 | * Let's play safe and prealign it to 2MB to give us some space. | ||
40 | */ | ||
41 | - align = 2 * 1024 * 1024; | ||
42 | + align = 2 * MiB; | ||
43 | } else { | ||
44 | /* | ||
45 | * Some 32bit kernels will trash anything in the 4K page the | ||
46 | * initrd ends in, so make sure the DTB isn't caught up in that. | ||
47 | */ | ||
48 | - align = 4096; | ||
49 | + align = 4 * KiB; | ||
50 | } | ||
51 | |||
52 | /* Place the DTB after the initrd in memory with alignment. */ | ||
53 | @@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, | ||
54 | info->loader_start + KERNEL_ARGS_ADDR; | ||
55 | fixupcontext[FIXUP_ARGPTR_HI] = | ||
56 | (info->loader_start + KERNEL_ARGS_ADDR) >> 32; | ||
57 | - if (info->ram_size >= (1ULL << 32)) { | ||
58 | + if (info->ram_size >= 4 * GiB) { | ||
59 | error_report("RAM size must be less than 4GB to boot" | ||
60 | " Linux kernel using ATAGS (try passing a device tree" | ||
61 | " using -dtb)"); | ||
62 | -- | 36 | -- |
63 | 2.20.1 | 37 | 2.20.1 |
64 | 38 | ||
65 | 39 | diff view generated by jsdifflib |
1 | From: Alex Bennée <alex.bennee@linaro.org> | 1 | From: Alistair Francis <alistair.francis@wdc.com> |
---|---|---|---|
2 | 2 | ||
3 | We do this for other semihosting calls so we might as well do it for | 3 | This patch fixes CID 1432800 by removing an unnecessary check. |
4 | M-profile as well. | ||
5 | 4 | ||
6 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | 5 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20190913151845.12582-3-alex.bennee@linaro.org | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 8 | --- |
12 | target/arm/m_helper.c | 18 ++++++------------ | 9 | hw/core/register.c | 4 ---- |
13 | target/arm/translate.c | 11 ++++++++++- | 10 | 1 file changed, 4 deletions(-) |
14 | 2 files changed, 16 insertions(+), 13 deletions(-) | ||
15 | 11 | ||
16 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | 12 | diff --git a/hw/core/register.c b/hw/core/register.c |
17 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/m_helper.c | 14 | --- a/hw/core/register.c |
19 | +++ b/target/arm/m_helper.c | 15 | +++ b/hw/core/register.c |
20 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | 16 | @@ -XXX,XX +XXX,XX @@ static RegisterInfoArray *register_init_block(DeviceState *owner, |
21 | break; | 17 | int index = rae[i].addr / data_size; |
22 | } | 18 | RegisterInfo *r = &ri[index]; |
23 | break; | 19 | |
24 | + case EXCP_SEMIHOST: | 20 | - if (data + data_size * index == 0 || !&rae[i]) { |
25 | + qemu_log_mask(CPU_LOG_INT, | 21 | - continue; |
26 | + "...handling as semihosting call 0x%x\n", | ||
27 | + env->regs[0]); | ||
28 | + env->regs[0] = do_arm_semihosting(env); | ||
29 | + return; | ||
30 | case EXCP_BKPT: | ||
31 | - if (semihosting_enabled()) { | ||
32 | - int nr; | ||
33 | - nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff; | ||
34 | - if (nr == 0xab) { | ||
35 | - env->regs[15] += 2; | ||
36 | - qemu_log_mask(CPU_LOG_INT, | ||
37 | - "...handling as semihosting call 0x%x\n", | ||
38 | - env->regs[0]); | ||
39 | - env->regs[0] = do_arm_semihosting(env); | ||
40 | - return; | ||
41 | - } | ||
42 | - } | 22 | - } |
43 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false); | 23 | - |
44 | break; | 24 | /* Init the register, this will zero it. */ |
45 | case EXCP_IRQ: | 25 | object_initialize((void *)r, sizeof(*r), TYPE_REGISTER); |
46 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/translate.c | ||
49 | +++ b/target/arm/translate.c | ||
50 | @@ -XXX,XX +XXX,XX @@ static bool trans_BKPT(DisasContext *s, arg_BKPT *a) | ||
51 | if (!ENABLE_ARCH_5) { | ||
52 | return false; | ||
53 | } | ||
54 | - gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); | ||
55 | + if (arm_dc_feature(s, ARM_FEATURE_M) && | ||
56 | + semihosting_enabled() && | ||
57 | +#ifndef CONFIG_USER_ONLY | ||
58 | + !IS_USER(s) && | ||
59 | +#endif | ||
60 | + (a->imm == 0xab)) { | ||
61 | + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); | ||
62 | + } else { | ||
63 | + gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); | ||
64 | + } | ||
65 | return true; | ||
66 | } | ||
67 | 26 | ||
68 | -- | 27 | -- |
69 | 2.20.1 | 28 | 2.20.1 |
70 | 29 | ||
71 | 30 | diff view generated by jsdifflib |
1 | From: Alex Bennée <alex.bennee@linaro.org> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | As for the other semihosting calls we can resolve this at translate | 3 | Fix Coverity CID 1435957: Memory - illegal accesses (OVERRUN): |
4 | time. | ||
5 | 4 | ||
6 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | 5 | >>> Overrunning array "suffixes" of 7 8-byte elements at element |
6 | index 7 (byte offset 63) using index "idx" (which evaluates to 7). | ||
7 | |||
8 | Note, the biggest input value freq_to_str() can accept is UINT64_MAX, | ||
9 | which is ~18.446 EHz, less than 1000 EHz. | ||
10 | |||
11 | Reported-by: Eduardo Habkost <ehabkost@redhat.com> | ||
12 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Message-id: 20190913151845.12582-4-alex.bennee@linaro.org | 14 | Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> |
15 | Reviewed-by: Luc Michel <luc@lmichel.fr> | ||
16 | Message-id: 20201101215755.2021421-1-f4bug@amsat.org | ||
17 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 20 | --- |
11 | target/arm/translate.c | 19 +++++++++++++++---- | 21 | util/cutils.c | 3 ++- |
12 | 1 file changed, 15 insertions(+), 4 deletions(-) | 22 | 1 file changed, 2 insertions(+), 1 deletion(-) |
13 | 23 | ||
14 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 24 | diff --git a/util/cutils.c b/util/cutils.c |
15 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/translate.c | 26 | --- a/util/cutils.c |
17 | +++ b/target/arm/translate.c | 27 | +++ b/util/cutils.c |
18 | @@ -XXX,XX +XXX,XX @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a) | 28 | @@ -XXX,XX +XXX,XX @@ char *freq_to_str(uint64_t freq_hz) |
29 | double freq = freq_hz; | ||
30 | size_t idx = 0; | ||
31 | |||
32 | - while (freq >= 1000.0 && idx < ARRAY_SIZE(suffixes)) { | ||
33 | + while (freq >= 1000.0) { | ||
34 | freq /= 1000.0; | ||
35 | idx++; | ||
36 | } | ||
37 | + assert(idx < ARRAY_SIZE(suffixes)); | ||
38 | |||
39 | return g_strdup_printf("%0.3g %sHz", freq, suffixes[idx]); | ||
19 | } | 40 | } |
20 | |||
21 | /* | ||
22 | - * Supervisor call | ||
23 | + * Supervisor call - both T32 & A32 come here so we need to check | ||
24 | + * which mode we are in when checking for semihosting. | ||
25 | */ | ||
26 | |||
27 | static bool trans_SVC(DisasContext *s, arg_SVC *a) | ||
28 | { | ||
29 | - gen_set_pc_im(s, s->base.pc_next); | ||
30 | - s->svc_imm = a->imm; | ||
31 | - s->base.is_jmp = DISAS_SWI; | ||
32 | + const uint32_t semihost_imm = s->thumb ? 0xab : 0x123456; | ||
33 | + | ||
34 | + if (!arm_dc_feature(s, ARM_FEATURE_M) && semihosting_enabled() && | ||
35 | +#ifndef CONFIG_USER_ONLY | ||
36 | + !IS_USER(s) && | ||
37 | +#endif | ||
38 | + (a->imm == semihost_imm)) { | ||
39 | + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); | ||
40 | + } else { | ||
41 | + gen_set_pc_im(s, s->base.pc_next); | ||
42 | + s->svc_imm = a->imm; | ||
43 | + s->base.is_jmp = DISAS_SWI; | ||
44 | + } | ||
45 | return true; | ||
46 | } | ||
47 | |||
48 | -- | 41 | -- |
49 | 2.20.1 | 42 | 2.20.1 |
50 | 43 | ||
51 | 44 | diff view generated by jsdifflib |
1 | From: Alex Bennée <alex.bennee@linaro.org> | 1 | In commit 76346b6264a9b01979 we tried to add a configure check that |
---|---|---|---|
2 | the libgio pkg-config data was correct, which builds an executable | ||
3 | linked against it. Unfortunately this doesn't catch the problem | ||
4 | (missing static library dependency info), because a "do nothing" test | ||
5 | source file doesn't have any symbol references that cause the linker | ||
6 | to pull in .o files from libgio.a, and so we don't see the "missing | ||
7 | symbols from libmount" error that a full QEMU link triggers. | ||
2 | 8 | ||
3 | These were missed in the recent de-tangling so have been updated to be | 9 | (The ineffective test went unnoticed because of a typo that |
4 | more actuate. I've also built up ARM_TESTS in a manner similar to | 10 | effectively disabled libgio unconditionally, but after commit |
5 | AARCH64_TESTS for better consistency. | 11 | 3569a5dfc11f2 fixed that, a static link of the system emulator on |
12 | Ubuntu stopped working again.) | ||
6 | 13 | ||
7 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | 14 | Improve the gio test by having the test source fragment reference a |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 15 | g_dbus function (which is what is indirectly causing us to end up |
9 | Message-id: 20190913151845.12582-2-alex.bennee@linaro.org | 16 | wanting functions from libmount). |
17 | |||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> | ||
20 | Message-id: 20201116104617.18333-1-peter.maydell@linaro.org | ||
11 | --- | 21 | --- |
12 | tests/tcg/Makefile.target | 7 +++++-- | 22 | configure | 11 +++++++++-- |
13 | tests/tcg/aarch64/Makefile.target | 3 ++- | 23 | 1 file changed, 9 insertions(+), 2 deletions(-) |
14 | tests/tcg/arm/Makefile.target | 15 ++++++++------- | ||
15 | 3 files changed, 15 insertions(+), 10 deletions(-) | ||
16 | 24 | ||
17 | diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target | 25 | diff --git a/configure b/configure |
18 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100755 |
19 | --- a/tests/tcg/Makefile.target | 27 | --- a/configure |
20 | +++ b/tests/tcg/Makefile.target | 28 | +++ b/configure |
21 | @@ -XXX,XX +XXX,XX @@ TIMEOUT=15 | 29 | @@ -XXX,XX +XXX,XX @@ if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then |
22 | endif | 30 | # Check that the libraries actually work -- Ubuntu 18.04 ships |
23 | 31 | # with pkg-config --static --libs data for gio-2.0 that is missing | |
24 | ifdef CONFIG_USER_ONLY | 32 | # -lblkid and will give a link error. |
25 | -# The order we include is important. We include multiarch, base arch | 33 | - write_c_skeleton |
26 | -# and finally arch if it's not the same as base arch. | 34 | - if compile_prog "" "$gio_libs" ; then |
27 | +# The order we include is important. We include multiarch first and | 35 | + cat > $TMPC <<EOF |
28 | +# then the target. If there are common tests shared between | 36 | +#include <gio/gio.h> |
29 | +# sub-targets (e.g. ARM & AArch64) then it is up to | 37 | +int main(void) |
30 | +# $(TARGET_NAME)/Makefile.target to include the common parent | 38 | +{ |
31 | +# architecture in its VPATH. | 39 | + g_dbus_proxy_new_sync(0, 0, 0, 0, 0, 0, 0, 0); |
32 | -include $(SRC_PATH)/tests/tcg/multiarch/Makefile.target | 40 | + return 0; |
33 | -include $(SRC_PATH)/tests/tcg/$(TARGET_NAME)/Makefile.target | 41 | +} |
34 | 42 | +EOF | |
35 | diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target | 43 | + if compile_prog "$gio_cflags" "$gio_libs" ; then |
36 | index XXXXXXX..XXXXXXX 100644 | 44 | gio=yes |
37 | --- a/tests/tcg/aarch64/Makefile.target | 45 | else |
38 | +++ b/tests/tcg/aarch64/Makefile.target | 46 | gio=no |
39 | @@ -XXX,XX +XXX,XX @@ VPATH += $(ARM_SRC) | ||
40 | AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64 | ||
41 | VPATH += $(AARCH64_SRC) | ||
42 | |||
43 | -# we don't build any other ARM test | ||
44 | +# Float-convert Tests | ||
45 | AARCH64_TESTS=fcvt | ||
46 | |||
47 | fcvt: LDFLAGS+=-lm | ||
48 | @@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt | ||
49 | $(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)") | ||
50 | $(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref) | ||
51 | |||
52 | +# Pauth Tests | ||
53 | AARCH64_TESTS += pauth-1 pauth-2 | ||
54 | run-pauth-%: QEMU_OPTS += -cpu max | ||
55 | |||
56 | diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/tests/tcg/arm/Makefile.target | ||
59 | +++ b/tests/tcg/arm/Makefile.target | ||
60 | @@ -XXX,XX +XXX,XX @@ ARM_SRC=$(SRC_PATH)/tests/tcg/arm | ||
61 | # Set search path for all sources | ||
62 | VPATH += $(ARM_SRC) | ||
63 | |||
64 | -ARM_TESTS=hello-arm test-arm-iwmmxt | ||
65 | - | ||
66 | -TESTS += $(ARM_TESTS) fcvt | ||
67 | - | ||
68 | +# Basic Hello World | ||
69 | +ARM_TESTS = hello-arm | ||
70 | hello-arm: CFLAGS+=-marm -ffreestanding | ||
71 | hello-arm: LDFLAGS+=-nostdlib | ||
72 | |||
73 | +# IWMXT floating point extensions | ||
74 | +ARM_TESTS += test-arm-iwmmxt | ||
75 | test-arm-iwmmxt: CFLAGS+=-marm -march=iwmmxt -mabi=aapcs -mfpu=fpv4-sp-d16 | ||
76 | test-arm-iwmmxt: test-arm-iwmmxt.S | ||
77 | $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS) | ||
78 | |||
79 | -ifeq ($(TARGET_NAME), arm) | ||
80 | +# Float-convert Tests | ||
81 | +ARM_TESTS += fcvt | ||
82 | fcvt: LDFLAGS+=-lm | ||
83 | # fcvt: CFLAGS+=-march=armv8.2-a+fp16 -mfpu=neon-fp-armv8 | ||
84 | - | ||
85 | run-fcvt: fcvt | ||
86 | $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") | ||
87 | $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) | ||
88 | -endif | ||
89 | + | ||
90 | +TESTS += $(ARM_TESTS) | ||
91 | |||
92 | # On ARM Linux only supports 4k pages | ||
93 | EXTRA_RUNS+=run-test-mmap-4096 | ||
94 | -- | 47 | -- |
95 | 2.20.1 | 48 | 2.20.1 |
96 | 49 | ||
97 | 50 | diff view generated by jsdifflib |
1 | If we're booting a Linux kernel directly into Non-Secure | 1 | The TMP105 datasheet (https://www.ti.com/lit/gpn/tmp105) says that the |
---|---|---|---|
2 | state on a CPU which has Secure state, then make sure we | 2 | power-up reset values for the T_low and T_high registers are 80 degrees C |
3 | set the NSACR CP11 and CP10 bits, so that Non-Secure is allowed | 3 | and 75 degrees C, which are 0x500 and 0x4B0 hex according to table 5. These |
4 | to access the FPU. Otherwise an AArch32 kernel will UNDEF as | 4 | values are then shifted right by four bits to give the register reset |
5 | soon as it tries to use the FPU. | 5 | values, since both registers store the 12 bits of temperature data in bits |
6 | [15..4] of a 16 bit register. | ||
6 | 7 | ||
7 | It used to not matter that we didn't do this until commit | 8 | We were resetting these registers to zero, which is problematic for Linux |
8 | fc1120a7f5f2d4b6, where we implemented actually honouring | 9 | guests which enable the alert interrupt and then immediately take an |
9 | these NSACR bits. | 10 | unexpected overtemperature alert because the current temperature is above |
11 | freezing... | ||
10 | 12 | ||
11 | The problem only exists for CPUs where EL3 is AArch32; the | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | equivalent AArch64 trap bits are in CPTR_EL3 and are "0 to | 14 | Reviewed-by: Cédric Le Goater <clg@kaod.org> |
13 | not trap, 1 to trap", so the reset value of the register | 15 | Message-id: 20201110150023.25533-2-peter.maydell@linaro.org |
14 | permits NS access, unlike NSACR. | 16 | --- |
17 | hw/misc/tmp105.c | 3 +++ | ||
18 | 1 file changed, 3 insertions(+) | ||
15 | 19 | ||
16 | Fixes: fc1120a7f5 | 20 | diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c |
17 | Fixes: https://bugs.launchpad.net/qemu/+bug/1844597 | ||
18 | Cc: qemu-stable@nongnu.org | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
21 | Message-id: 20190920174039.3916-1-peter.maydell@linaro.org | ||
22 | --- | ||
23 | hw/arm/boot.c | 2 ++ | ||
24 | 1 file changed, 2 insertions(+) | ||
25 | |||
26 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/hw/arm/boot.c | 22 | --- a/hw/misc/tmp105.c |
29 | +++ b/hw/arm/boot.c | 23 | +++ b/hw/misc/tmp105.c |
30 | @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) | 24 | @@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c) |
31 | (cs != first_cpu || !info->secure_board_setup)) { | 25 | s->faults = tmp105_faultq[(s->config >> 3) & 3]; |
32 | /* Linux expects non-secure state */ | 26 | s->alarm = 0; |
33 | env->cp15.scr_el3 |= SCR_NS; | 27 | |
34 | + /* Set NSACR.{CP11,CP10} so NS can access the FPU */ | 28 | + s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */ |
35 | + env->cp15.nsacr |= 3 << 10; | 29 | + s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */ |
36 | } | 30 | + |
37 | } | 31 | tmp105_interrupt_update(s); |
32 | } | ||
38 | 33 | ||
39 | -- | 34 | -- |
40 | 2.20.1 | 35 | 2.20.1 |
41 | 36 | ||
42 | 37 | diff view generated by jsdifflib |
1 | From: Luc Michel <luc.michel@greensocs.com> | 1 | The TMP105 datasheet says that in Interrupt Mode (when TM==1) the device |
---|---|---|---|
2 | signals an alert when the temperature equals or exceeds the T_high value and | ||
3 | then remains high until a device register is read or the device responds to | ||
4 | the SMBUS Alert Response address, or the device is put into Shutdown Mode. | ||
5 | Thereafter the Alert pin will only be re-signalled when temperature falls | ||
6 | below T_low; alert can then be cleared in the same set of ways, and the | ||
7 | device returns to its initial "alert when temperature goes above T_high" | ||
8 | mode. (If this textual description is confusing, see figure 3 in the | ||
9 | TI datasheet at https://www.ti.com/lit/gpn/tmp105 .) | ||
2 | 10 | ||
3 | For AArch64 CPUs with a CBAR register, we have two views for it: | 11 | We were misimplementing this as a simple "always alert if temperature is |
4 | - in AArch64 state, the CBAR_EL1 register (S3_1_C15_C3_0), returns the | 12 | above T_high or below T_low" condition, which gives a spurious alert on |
5 | full 64 bits CBAR value | 13 | startup if using the "T_high = 80 degrees C, T_low = 75 degrees C" reset |
6 | - in AArch32 state, the CBAR register (cp15, opc1=1, CRn=15, CRm=3, opc2=0) | 14 | limit values. |
7 | returns a 32 bits view such that: | ||
8 | CBAR = CBAR_EL1[31:18] 0..0 CBAR_EL1[43:32] | ||
9 | 15 | ||
10 | This commit fixes the current implementation where: | 16 | Implement the correct (hysteresis) behaviour by tracking whether we |
11 | - CBAR_EL1 was returning the 32 bits view instead of the full 64 bits | 17 | are currently looking for the temperature to rise over T_high or |
12 | value, | 18 | for it to fall below T_low. Our implementation of the comparator |
13 | - CBAR was returning a truncated 32 bits version of the full 64 bits | 19 | mode (TM==0) wasn't wrong, but rephrase it to match the way that |
14 | one, instead of the 32 bits view | 20 | interrupt mode is now handled for clarity. |
15 | - CBAR was declared as cp15, opc1=4, CRn=15, CRm=0, opc2=0, which is | ||
16 | the CBAR register found in the ARMv7 Cortex-Ax CPUs, but not in | ||
17 | ARMv8 CPUs. | ||
18 | 21 | ||
19 | Signed-off-by: Luc Michel <luc.michel@greensocs.com> | ||
20 | Message-id: 20190912110103.1417887-1-luc.michel@greensocs.com | ||
21 | [PMM: Added a comment about the two different kinds of CBAR] | ||
22 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
23 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
24 | Message-id: 20201110150023.25533-3-peter.maydell@linaro.org | ||
24 | --- | 25 | --- |
25 | target/arm/helper.c | 19 ++++++++++++++++--- | 26 | hw/misc/tmp105.h | 7 +++++ |
26 | 1 file changed, 16 insertions(+), 3 deletions(-) | 27 | hw/misc/tmp105.c | 70 +++++++++++++++++++++++++++++++++++++++++------- |
28 | 2 files changed, 68 insertions(+), 9 deletions(-) | ||
27 | 29 | ||
28 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 30 | diff --git a/hw/misc/tmp105.h b/hw/misc/tmp105.h |
29 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/target/arm/helper.c | 32 | --- a/hw/misc/tmp105.h |
31 | +++ b/target/arm/helper.c | 33 | +++ b/hw/misc/tmp105.h |
32 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | 34 | @@ -XXX,XX +XXX,XX @@ struct TMP105State { |
35 | int16_t limit[2]; | ||
36 | int faults; | ||
37 | uint8_t alarm; | ||
38 | + /* | ||
39 | + * The TMP105 initially looks for a temperature rising above T_high; | ||
40 | + * once this is detected, the condition it looks for next is the | ||
41 | + * temperature falling below T_low. This flag is false when initially | ||
42 | + * looking for T_high, true when looking for T_low. | ||
43 | + */ | ||
44 | + bool detect_falling; | ||
45 | }; | ||
46 | |||
47 | #endif | ||
48 | diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/hw/misc/tmp105.c | ||
51 | +++ b/hw/misc/tmp105.c | ||
52 | @@ -XXX,XX +XXX,XX @@ static void tmp105_alarm_update(TMP105State *s) | ||
53 | return; | ||
33 | } | 54 | } |
34 | 55 | ||
35 | if (arm_feature(env, ARM_FEATURE_CBAR)) { | 56 | - if ((s->config >> 1) & 1) { /* TM */ |
57 | - if (s->temperature >= s->limit[1]) | ||
58 | - s->alarm = 1; | ||
59 | - else if (s->temperature < s->limit[0]) | ||
60 | - s->alarm = 1; | ||
61 | + if (s->config >> 1 & 1) { | ||
36 | + /* | 62 | + /* |
37 | + * CBAR is IMPDEF, but common on Arm Cortex-A implementations. | 63 | + * TM == 1 : Interrupt mode. We signal Alert when the |
38 | + * There are two flavours: | 64 | + * temperature rises above T_high, and expect the guest to clear |
39 | + * (1) older 32-bit only cores have a simple 32-bit CBAR | 65 | + * it (eg by reading a device register). |
40 | + * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a | ||
41 | + * 32-bit register visible to AArch32 at a different encoding | ||
42 | + * to the "flavour 1" register and with the bits rearranged to | ||
43 | + * be able to squash a 64-bit address into the 32-bit view. | ||
44 | + * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but | ||
45 | + * in future if we support AArch32-only configs of some of the | ||
46 | + * AArch64 cores we might need to add a specific feature flag | ||
47 | + * to indicate cores with "flavour 2" CBAR. | ||
48 | + */ | 66 | + */ |
49 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | 67 | + if (s->detect_falling) { |
50 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | 68 | + if (s->temperature < s->limit[0]) { |
51 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | 69 | + s->alarm = 1; |
52 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | 70 | + s->detect_falling = false; |
53 | ARMCPRegInfo cbar_reginfo[] = { | 71 | + } |
54 | { .name = "CBAR", | 72 | + } else { |
55 | .type = ARM_CP_CONST, | 73 | + if (s->temperature >= s->limit[1]) { |
56 | - .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | 74 | + s->alarm = 1; |
57 | - .access = PL1_R, .resetvalue = cpu->reset_cbar }, | 75 | + s->detect_falling = true; |
58 | + .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0, | 76 | + } |
59 | + .access = PL1_R, .resetvalue = cbar32 }, | 77 | + } |
60 | { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, | 78 | } else { |
61 | .type = ARM_CP_CONST, | 79 | - if (s->temperature >= s->limit[1]) |
62 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | 80 | - s->alarm = 1; |
63 | - .access = PL1_R, .resetvalue = cbar32 }, | 81 | - else if (s->temperature < s->limit[0]) |
64 | + .access = PL1_R, .resetvalue = cpu->reset_cbar }, | 82 | - s->alarm = 0; |
65 | REGINFO_SENTINEL | 83 | + /* |
66 | }; | 84 | + * TM == 0 : Comparator mode. We signal Alert when the temperature |
67 | /* We don't implement a r/w 64 bit CBAR currently */ | 85 | + * rises above T_high, and stop signalling it when the temperature |
86 | + * falls below T_low. | ||
87 | + */ | ||
88 | + if (s->detect_falling) { | ||
89 | + if (s->temperature < s->limit[0]) { | ||
90 | + s->alarm = 0; | ||
91 | + s->detect_falling = false; | ||
92 | + } | ||
93 | + } else { | ||
94 | + if (s->temperature >= s->limit[1]) { | ||
95 | + s->alarm = 1; | ||
96 | + s->detect_falling = true; | ||
97 | + } | ||
98 | + } | ||
99 | } | ||
100 | |||
101 | tmp105_interrupt_update(s); | ||
102 | @@ -XXX,XX +XXX,XX @@ static int tmp105_post_load(void *opaque, int version_id) | ||
103 | return 0; | ||
104 | } | ||
105 | |||
106 | +static bool detect_falling_needed(void *opaque) | ||
107 | +{ | ||
108 | + TMP105State *s = opaque; | ||
109 | + | ||
110 | + /* | ||
111 | + * We only need to migrate the detect_falling bool if it's set; | ||
112 | + * for migration from older machines we assume that it is false | ||
113 | + * (ie temperature is not out of range). | ||
114 | + */ | ||
115 | + return s->detect_falling; | ||
116 | +} | ||
117 | + | ||
118 | +static const VMStateDescription vmstate_tmp105_detect_falling = { | ||
119 | + .name = "TMP105/detect-falling", | ||
120 | + .version_id = 1, | ||
121 | + .minimum_version_id = 1, | ||
122 | + .needed = detect_falling_needed, | ||
123 | + .fields = (VMStateField[]) { | ||
124 | + VMSTATE_BOOL(detect_falling, TMP105State), | ||
125 | + VMSTATE_END_OF_LIST() | ||
126 | + } | ||
127 | +}; | ||
128 | + | ||
129 | static const VMStateDescription vmstate_tmp105 = { | ||
130 | .name = "TMP105", | ||
131 | .version_id = 0, | ||
132 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_tmp105 = { | ||
133 | VMSTATE_UINT8(alarm, TMP105State), | ||
134 | VMSTATE_I2C_SLAVE(i2c, TMP105State), | ||
135 | VMSTATE_END_OF_LIST() | ||
136 | + }, | ||
137 | + .subsections = (const VMStateDescription*[]) { | ||
138 | + &vmstate_tmp105_detect_falling, | ||
139 | + NULL | ||
140 | } | ||
141 | }; | ||
142 | |||
143 | @@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c) | ||
144 | s->config = 0; | ||
145 | s->faults = tmp105_faultq[(s->config >> 3) & 3]; | ||
146 | s->alarm = 0; | ||
147 | + s->detect_falling = false; | ||
148 | |||
149 | s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */ | ||
150 | s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */ | ||
68 | -- | 151 | -- |
69 | 2.20.1 | 152 | 2.20.1 |
70 | 153 | ||
71 | 154 | diff view generated by jsdifflib |