target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-)
The CPUID bits CLZERO and XSAVEERPTR are availble on AMD's ZEN platform
and could be passed to the guest.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
I tweaked the kernel to expose these flags and figured out that this is
also missing in order see those bits in the guest.
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index fbed2eb804e32..e00ef3c917391 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1113,7 +1113,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_8000_0008_EBX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
- NULL, NULL, NULL, NULL,
+ "clzero", NULL, "xsaveerptr", NULL,
NULL, NULL, NULL, NULL,
NULL, "wbnoinvd", NULL, NULL,
"ibpb", NULL, NULL, NULL,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 0732e059ec989..cc475c703fc4d 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -689,6 +689,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/
#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */
+#define CPUD_800_008_EBX_CLZERO (1U << 0) /* CLZERO instruction */
+#define CPUD_800_008_EBX_XSAVEERPTR (1U << 2) /* Always save/restore FP error pointers */
#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and
do not invalidate cache */
#define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */
--
2.23.0
On 25/09/19 23:49, Sebastian Andrzej Siewior wrote: > The CPUID bits CLZERO and XSAVEERPTR are availble on AMD's ZEN platform > and could be passed to the guest. > > Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> > --- > > I tweaked the kernel to expose these flags and figured out that this is > also missing in order see those bits in the guest. > > target/i386/cpu.c | 2 +- > target/i386/cpu.h | 2 ++ > 2 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index fbed2eb804e32..e00ef3c917391 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -1113,7 +1113,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { > [FEAT_8000_0008_EBX] = { > .type = CPUID_FEATURE_WORD, > .feat_names = { > - NULL, NULL, NULL, NULL, > + "clzero", NULL, "xsaveerptr", NULL, > NULL, NULL, NULL, NULL, > NULL, "wbnoinvd", NULL, NULL, > "ibpb", NULL, NULL, NULL, > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index 0732e059ec989..cc475c703fc4d 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -689,6 +689,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; > #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/ > #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ > > +#define CPUD_800_008_EBX_CLZERO (1U << 0) /* CLZERO instruction */ > +#define CPUD_800_008_EBX_XSAVEERPTR (1U << 2) /* Always save/restore FP error pointers */ > #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and > do not invalidate cache */ > #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ > Yup, queued this one. Paolo
On 25/09/19 23:49, Sebastian Andrzej Siewior wrote: > #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ > > +#define CPUD_800_008_EBX_CLZERO (1U << 0) /* CLZERO instruction */ > +#define CPUD_800_008_EBX_XSAVEERPTR (1U << 2) /* Always save/restore FP error pointers */ > #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and Well, there are obvious typos here but I can fix them for you. Which processors have these? Paolo
On 2019-09-26 13:06:34 [+0200], Paolo Bonzini wrote: > On 25/09/19 23:49, Sebastian Andrzej Siewior wrote: > > #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ > > > > +#define CPUD_800_008_EBX_CLZERO (1U << 0) /* CLZERO instruction */ > > +#define CPUD_800_008_EBX_XSAVEERPTR (1U << 2) /* Always save/restore FP error pointers */ > > #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and > > Well, there are obvious typos here but I can fix them for you. Sorry for the missing I. > Which processors have these? There are mention in AMD document [0]. I *think* there were introduced in Zen, see them on a Ryzen and Epyc. [0] https://www.amd.com/system/files/TechDocs/24594.pdf > Paolo Sebastian
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