On 03/10/2019 04:12, David Gibson wrote:
> On Wed, Sep 18, 2019 at 06:06:34PM +0200, Cédric Le Goater wrote:
>> The NVT space is 19 bits wide, giving a maximum of 512K per chip. When
>> dispatched on a HW thread, the NVT identifier of a vCPU is pushed/stored
>> in the CAM line (word2) of the thread interrupt context.
>
> Ok, that's interesting, but how does it lead to this patch? Connect
> the dots, please.
ok. These are helpers for the next patch. It's a clarification of the
values also.
When a vPCU is dispatched on a HW thread, the NVT identifier is pushed
in the CAM line (QW1W2). This identifier is used to fetch a NVT structure,
in the presenter subengine, which might contain pending interrupts that
need a resend. So we will use these helpers to do :
xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)
xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4)
and notify a cpu.
C.
>
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> include/hw/ppc/xive.h | 5 -----
>> include/hw/ppc/xive_regs.h | 21 +++++++++++++++++++++
>> 2 files changed, 21 insertions(+), 5 deletions(-)
>>
>> diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
>> index a461753f5da5..794dfcaae0f8 100644
>> --- a/include/hw/ppc/xive.h
>> +++ b/include/hw/ppc/xive.h
>> @@ -469,11 +469,6 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
>> Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp);
>> void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb);
>>
>> -static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx)
>> -{
>> - return (nvt_blk << 19) | nvt_idx;
>> -}
>> -
>> /*
>> * KVM XIVE device helpers
>> */
>> diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h
>> index 08c8bf7172e2..3d7b6fd09664 100644
>> --- a/include/hw/ppc/xive_regs.h
>> +++ b/include/hw/ppc/xive_regs.h
>> @@ -251,4 +251,25 @@ typedef struct XiveNVT {
>>
>> #define xive_nvt_is_valid(nvt) (be32_to_cpu((nvt)->w0) & NVT_W0_VALID)
>>
>> +/*
>> + * The VP number space in a block is defined by the END_W6_NVT_INDEX
>> + * field of the XIVE END
>> + */
>> +#define XIVE_NVT_SHIFT 19
>> +
>> +static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx)
>> +{
>> + return (nvt_blk << XIVE_NVT_SHIFT) | nvt_idx;
>> +}
>> +
>> +static inline uint32_t xive_nvt_idx(uint32_t cam_line)
>> +{
>> + return cam_line & ((1 << XIVE_NVT_SHIFT) - 1);
>> +}
>> +
>> +static inline uint32_t xive_nvt_blk(uint32_t cam_line)
>> +{
>> + return (cam_line >> XIVE_NVT_SHIFT) & 0xf;
>> +}
>> +
>> #endif /* PPC_XIVE_REGS_H */
>