[v2] cputlb: Adjust tlb bswap implementation

[Qemu-devel] [PATCH v2 0/3] cputlb: Adjust tlb bswap implementation

Richard Henderson posted 3 patches 4 years, 7 months ago

Diff against v1
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Test docker-quick@centos7 passed

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20190912195934.13502-1-richard.henderson@linaro.org

Maintainers: Paolo Bonzini <pbonzini@redhat.com>, Richard Henderson <rth@twiddle.net>

include/exec/cpu-all.h  |   2 +
include/qemu/compiler.h |  11 ++
accel/tcg/cputlb.c      | 235 ++++++++++++++++++++--------------------
3 files changed, 132 insertions(+), 116 deletions(-)

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[Qemu-devel] [PATCH v2 0/3] cputlb: Adjust tlb bswap implementation

Posted by Richard Henderson 4 years, 7 months ago

Changes from v1:
  * Move QEMU_ALWAYS_INLINE to qemu/compiler.h.
  * Rename some inline wrapper functions.
  * Don't break TLB_NOTDIRTY in patch 3.

Blurb from v1:

The version that Tony came up with, and I reviewed, doesn't actually
work when applied to RAM.  It only worked for i/o memory.  This was
the root cause for

https://lists.gnu.org/archive/html/qemu-devel/2019-09/msg00036.html

I tried a couple of different approaches in load/store_helper, but
this is the one that didn't affect the normal case -- a simple tlb
miss against (non-swapped) ram.


r~


Richard Henderson (3):
  cputlb: Disable __always_inline__ without optimization
  cputlb: Replace switches in load/store_helper with callback
  cputlb: Introduce TLB_BSWAP

 include/exec/cpu-all.h  |   2 +
 include/qemu/compiler.h |  11 ++
 accel/tcg/cputlb.c      | 235 ++++++++++++++++++++--------------------
 3 files changed, 132 insertions(+), 116 deletions(-)

-- 
2.17.1