hw/ppc/Makefile.objs | 1 + hw/ppc/pnv.c | 87 ++++++++++++--- hw/ppc/pnv_homer.c | 272 +++++++++++++++++++++++++++++++++++++++++++++ hw/ppc/pnv_occ.c | 78 +++++++++++++ hw/ppc/pnv_xscom.c | 34 +++++- include/hw/ppc/pnv.h | 21 ++++ include/hw/ppc/pnv_homer.h | 53 +++++++++ include/hw/ppc/pnv_occ.h | 3 + 8 files changed, 528 insertions(+), 21 deletions(-) create mode 100644 hw/ppc/pnv_homer.c create mode 100644 include/hw/ppc/pnv_homer.h
Hi All,
This is follow-up patch that implements HOMER and OCC SRAM device
models to emulate homer memory and occ common area access for pstate
table, occ sensors, runtime data and slw.
Currently skiboot disables the homer/occ code path with `QUIRK_NO_PBA`,
this quirk have to be removed in skiboot for it to use HOMER and OCC
SRAM device models along with a bug fix,
https://github.com/balamuruhans/skiboot/commit/a655514d2a730e0372a2faee277d1cf01f71a524
https://github.com/balamuruhans/skiboot/commit/fd3d93d92ec66a7494346d6d24ced7b48264c9a0
This version fixes a review comment from Cedric in previous version,
changes in v3:
* pass on PnvHomer *homer directly to core_max_array() function
from the caller.
v2 patchset:
https://lists.gnu.org/archive/html/qemu-devel/2019-09/msg02231.html
changes in v2:
* change to PnvHomer/PnvHomerClass instead of PnvHOMER/PnvHOMERClass
for better code readabililty.
* fabric link to chip to use `nr_cores` from PnvChip struct for
core_max_array() as we need to consider active cores in chip and not
whole machine.
* declare variable well ahead instead in for() loop syntax to make
all compilers happy.
* change to shorter variable name to `hmrc` instead of `homer_class`.
* remove `homer_` prefix for regs as it is not useful.
* have separate commit for checkpatch.pl coding style warnings.
v1 patchset:
https://lists.gnu.org/archive/html/qemu-devel/2019-09/msg01610.html
changes in v1:
* breaks it to have separate patch series for Homer and OCC
emulation.
* reuse PnvOCC device model to implement SRAM device.
* implement PnvHomer as separate device model.
* have core max base address as part of PnvHOMERClass.
* reuse PNV_CHIP_INDEX() instead of introducing new `chip_num`.
* define all the memory ops access address as macros.
* few coding style warnings given by checkpatch.pl.
rfc patchset:
https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg00979.html
I request for review, comments and suggestions for the changes.
Balamuruhan S (4):
hw/ppc/pnv_xscom: retrieve homer/occ base address from PBA BARs
hw/ppc/pnv_occ: add sram device model for occ common area
hw/ppc/pnv_homer: add PowerNV homer device model
hw/ppc/pnv: fix checkpatch.pl coding style warnings
hw/ppc/Makefile.objs | 1 +
hw/ppc/pnv.c | 87 ++++++++++++---
hw/ppc/pnv_homer.c | 272 +++++++++++++++++++++++++++++++++++++++++++++
hw/ppc/pnv_occ.c | 78 +++++++++++++
hw/ppc/pnv_xscom.c | 34 +++++-
include/hw/ppc/pnv.h | 21 ++++
include/hw/ppc/pnv_homer.h | 53 +++++++++
include/hw/ppc/pnv_occ.h | 3 +
8 files changed, 528 insertions(+), 21 deletions(-)
create mode 100644 hw/ppc/pnv_homer.c
create mode 100644 include/hw/ppc/pnv_homer.h
--
2.14.5
On 12/09/2019 11:30, Balamuruhan S wrote: > Hi All, > > This is follow-up patch that implements HOMER and OCC SRAM device > models to emulate homer memory and occ common area access for pstate > table, occ sensors, runtime data and slw. So, now, we can write directly to the OCC SRAM memory region from the QEMU monitor. How will skiboot pick up the changes ? C. > > Currently skiboot disables the homer/occ code path with `QUIRK_NO_PBA`, > this quirk have to be removed in skiboot for it to use HOMER and OCC > SRAM device models along with a bug fix, > > https://github.com/balamuruhans/skiboot/commit/a655514d2a730e0372a2faee277d1cf01f71a524 > https://github.com/balamuruhans/skiboot/commit/fd3d93d92ec66a7494346d6d24ced7b48264c9a0 > > This version fixes a review comment from Cedric in previous version, > > changes in v3: > * pass on PnvHomer *homer directly to core_max_array() function > from the caller. > > v2 patchset: > https://lists.gnu.org/archive/html/qemu-devel/2019-09/msg02231.html > > changes in v2: > * change to PnvHomer/PnvHomerClass instead of PnvHOMER/PnvHOMERClass > for better code readabililty. > * fabric link to chip to use `nr_cores` from PnvChip struct for > core_max_array() as we need to consider active cores in chip and not > whole machine. > * declare variable well ahead instead in for() loop syntax to make > all compilers happy. > * change to shorter variable name to `hmrc` instead of `homer_class`. > * remove `homer_` prefix for regs as it is not useful. > * have separate commit for checkpatch.pl coding style warnings. > > v1 patchset: > https://lists.gnu.org/archive/html/qemu-devel/2019-09/msg01610.html > > changes in v1: > * breaks it to have separate patch series for Homer and OCC > emulation. > * reuse PnvOCC device model to implement SRAM device. > * implement PnvHomer as separate device model. > * have core max base address as part of PnvHOMERClass. > * reuse PNV_CHIP_INDEX() instead of introducing new `chip_num`. > * define all the memory ops access address as macros. > * few coding style warnings given by checkpatch.pl. > > rfc patchset: > https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg00979.html > > I request for review, comments and suggestions for the changes. > > Balamuruhan S (4): > hw/ppc/pnv_xscom: retrieve homer/occ base address from PBA BARs > hw/ppc/pnv_occ: add sram device model for occ common area > hw/ppc/pnv_homer: add PowerNV homer device model > hw/ppc/pnv: fix checkpatch.pl coding style warnings > > hw/ppc/Makefile.objs | 1 + > hw/ppc/pnv.c | 87 ++++++++++++--- > hw/ppc/pnv_homer.c | 272 +++++++++++++++++++++++++++++++++++++++++++++ > hw/ppc/pnv_occ.c | 78 +++++++++++++ > hw/ppc/pnv_xscom.c | 34 +++++- > include/hw/ppc/pnv.h | 21 ++++ > include/hw/ppc/pnv_homer.h | 53 +++++++++ > include/hw/ppc/pnv_occ.h | 3 + > 8 files changed, 528 insertions(+), 21 deletions(-) > create mode 100644 hw/ppc/pnv_homer.c > create mode 100644 include/hw/ppc/pnv_homer.h >
On Thu, Sep 12, 2019 at 11:54:00AM +0200, Cédric Le Goater wrote: > On 12/09/2019 11:30, Balamuruhan S wrote: > > Hi All, > > > > This is follow-up patch that implements HOMER and OCC SRAM device > > models to emulate homer memory and occ common area access for pstate > > table, occ sensors, runtime data and slw. > > So, now, we can write directly to the OCC SRAM memory region from the I think you are referring to the other part of RFC where we can feed/ write data dynamically to the memory region with Qemu monitor interface that you have suggested to adopt instead of python API interface. I am working with Hariharan to enable it and I would need some time for it. > QEMU monitor. How will skiboot pick up the changes ? with current changes, we do create device tree with the base address of Homer and OCC region and skiboot picks up, initializes it during PowerNV emulated host boots up and tries to start dereferring the pstate table, occ sensor data, runtime data etc., with offsets for which we have defined in Qemu and Qemu returns some default value so that skiboot doesn't invalidate/error it. Additionally once we get this patchset merged we should get the skiboot patches in for enabling the code path of homer/occ if skiboot detects Qemu. For reference we can see below boot log of Qemu emulated PowerNV host, [ 0.029304612,5] OPAL 165b3829-root-dirty-d7b62c6 starting... [ 0.030088822,7] initial console log level: memory 7, driver 5 [ 0.030147011,6] CPU: P9 generation processor (max 4 threads/core) [ 0.030178089,7] CPU: Boot CPU PIR is 0x0000 PVR is 0x004e1200 [ 0.030367773,7] OPAL table: 0x30106930 .. 0x30106ea0, branch table: 0x30002000 [ 0.030639657,7] Assigning physical memory map table for nimbus [ 0.030954762,7] FDT: Parsing fdt @0x1000000 [ 0.034344285,5] CHIP: Detected Qemu simulator [ 0.034586944,6] CHIP: Initialised chip 0 from xscom@603fc00000000 [ 0.035083506,6] P9 DD2.00 detected [ 0.035109773,5] CHIP: Chip ID 0000 type: P9N DD2.00 [ 0.035126551,7] XSCOM: Base address: 0x603fc00000000 [ 0.035161363,7] XSTOP: ibm,sw-checkstop-fir prop not found [ 0.035274093,6] MFSI 0:0: Initialized [ 0.035291808,6] MFSI 0:2: Initialized [ 0.035308832,6] MFSI 0:1: Initialized [ 0.036009709,6] LPC: LPC[000]: Initialized [ 0.036024631,7] LPC: access via MMIO @0x6030000000000 [ 0.036075678,7] LPC: Default bus on chip 0x0 [ 0.036201881,7] CPU: New max PIR set to 0x3 [ 0.036901816,7] MEM: parsing reserved memory from reserved-names/-ranges properties [ 0.037012392,7] HOMER: Init chip 0 [ 0.037060772,7] PBA BAR0 : 0x0000203ffd800000 [ 0.037076462,7] PBA MASK0: 0x0000000000300000 [ 0.037121097,7] HOMER Image at 0x203ffd800000 size 4MB [ 0.037192576,4] HOMER image is not reserved! Reserving [ 0.037269907,7] PBA BAR2 : 0x0000203fff800000 [ 0.037280977,7] PBA MASK2: 0x0000000000700000 [ 0.037301135,7] OCC Common Area at 0x203fff800000 size 8MB [ 0.037351959,4] OCC common area is not reserved! Reserving ::: ::: [ 0.109004331,5] OCC: All Chip Rdy after 0 ms ::: ::: [ 0.297195] cpuidle: using governor menu ::: ::: [ 0.337736] cpuidle-powernv: Default stop: psscr = 0x0000000000000330,mask=0x00000000003003ff [ 0.338393] cpuidle-powernv: Deepest stop: psscr = 0x0000000000300331,mask=0x00000000003003ff [ 0.339000] cpuidle-powernv: Requested Level (RL) value of first deep stop = 0xf ::: ::: [ 1.617017] powernv-cpufreq: cpufreq pstate min 0x2 nominal 0x1 max 0x0 [ 1.617523] powernv-cpufreq: Workload Optimized Frequency is enabled in the platform [ 1.620734] freq_table: Duplicate freq-table entries: 3000 [ 1.622298] powernv-cpufreq: Failed to register the cpufreq driver (-19) [ 1.623088] powernv-cpufreq: Platform driver disabled. System does not support PState control ::: ::: -- Bala > > > C. > > > > > Currently skiboot disables the homer/occ code path with `QUIRK_NO_PBA`, > > this quirk have to be removed in skiboot for it to use HOMER and OCC > > SRAM device models along with a bug fix, > > > > https://github.com/balamuruhans/skiboot/commit/a655514d2a730e0372a2faee277d1cf01f71a524 > > https://github.com/balamuruhans/skiboot/commit/fd3d93d92ec66a7494346d6d24ced7b48264c9a0 > > > > This version fixes a review comment from Cedric in previous version, > > > > changes in v3: > > * pass on PnvHomer *homer directly to core_max_array() function > > from the caller. > > > > v2 patchset: > > https://lists.gnu.org/archive/html/qemu-devel/2019-09/msg02231.html > > > > changes in v2: > > * change to PnvHomer/PnvHomerClass instead of PnvHOMER/PnvHOMERClass > > for better code readabililty. > > * fabric link to chip to use `nr_cores` from PnvChip struct for > > core_max_array() as we need to consider active cores in chip and not > > whole machine. > > * declare variable well ahead instead in for() loop syntax to make > > all compilers happy. > > * change to shorter variable name to `hmrc` instead of `homer_class`. > > * remove `homer_` prefix for regs as it is not useful. > > * have separate commit for checkpatch.pl coding style warnings. > > > > v1 patchset: > > https://lists.gnu.org/archive/html/qemu-devel/2019-09/msg01610.html > > > > changes in v1: > > * breaks it to have separate patch series for Homer and OCC > > emulation. > > * reuse PnvOCC device model to implement SRAM device. > > * implement PnvHomer as separate device model. > > * have core max base address as part of PnvHOMERClass. > > * reuse PNV_CHIP_INDEX() instead of introducing new `chip_num`. > > * define all the memory ops access address as macros. > > * few coding style warnings given by checkpatch.pl. > > > > rfc patchset: > > https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg00979.html > > > > I request for review, comments and suggestions for the changes. > > > > Balamuruhan S (4): > > hw/ppc/pnv_xscom: retrieve homer/occ base address from PBA BARs > > hw/ppc/pnv_occ: add sram device model for occ common area > > hw/ppc/pnv_homer: add PowerNV homer device model > > hw/ppc/pnv: fix checkpatch.pl coding style warnings > > > > hw/ppc/Makefile.objs | 1 + > > hw/ppc/pnv.c | 87 ++++++++++++--- > > hw/ppc/pnv_homer.c | 272 +++++++++++++++++++++++++++++++++++++++++++++ > > hw/ppc/pnv_occ.c | 78 +++++++++++++ > > hw/ppc/pnv_xscom.c | 34 +++++- > > include/hw/ppc/pnv.h | 21 ++++ > > include/hw/ppc/pnv_homer.h | 53 +++++++++ > > include/hw/ppc/pnv_occ.h | 3 + > > 8 files changed, 528 insertions(+), 21 deletions(-) > > create mode 100644 hw/ppc/pnv_homer.c > > create mode 100644 include/hw/ppc/pnv_homer.h > > >
On Thu, Sep 12, 2019 at 03:00:51PM +0530, Balamuruhan S wrote: > Hi All, > > This is follow-up patch that implements HOMER and OCC SRAM device > models to emulate homer memory and occ common area access for pstate > table, occ sensors, runtime data and slw. > > Currently skiboot disables the homer/occ code path with `QUIRK_NO_PBA`, > this quirk have to be removed in skiboot for it to use HOMER and OCC > SRAM device models along with a bug fix, > > https://github.com/balamuruhans/skiboot/commit/a655514d2a730e0372a2faee277d1cf01f71a524 > https://github.com/balamuruhans/skiboot/commit/fd3d93d92ec66a7494346d6d24ced7b48264c9a0 > > This version fixes a review comment from Cedric in previous version, Applied to ppc-for-4.2, thanks. > > changes in v3: > * pass on PnvHomer *homer directly to core_max_array() function > from the caller. > > v2 patchset: > https://lists.gnu.org/archive/html/qemu-devel/2019-09/msg02231.html > > changes in v2: > * change to PnvHomer/PnvHomerClass instead of PnvHOMER/PnvHOMERClass > for better code readabililty. > * fabric link to chip to use `nr_cores` from PnvChip struct for > core_max_array() as we need to consider active cores in chip and not > whole machine. > * declare variable well ahead instead in for() loop syntax to make > all compilers happy. > * change to shorter variable name to `hmrc` instead of `homer_class`. > * remove `homer_` prefix for regs as it is not useful. > * have separate commit for checkpatch.pl coding style warnings. > > v1 patchset: > https://lists.gnu.org/archive/html/qemu-devel/2019-09/msg01610.html > > changes in v1: > * breaks it to have separate patch series for Homer and OCC > emulation. > * reuse PnvOCC device model to implement SRAM device. > * implement PnvHomer as separate device model. > * have core max base address as part of PnvHOMERClass. > * reuse PNV_CHIP_INDEX() instead of introducing new `chip_num`. > * define all the memory ops access address as macros. > * few coding style warnings given by checkpatch.pl. > > rfc patchset: > https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg00979.html > > I request for review, comments and suggestions for the changes. > > Balamuruhan S (4): > hw/ppc/pnv_xscom: retrieve homer/occ base address from PBA BARs > hw/ppc/pnv_occ: add sram device model for occ common area > hw/ppc/pnv_homer: add PowerNV homer device model > hw/ppc/pnv: fix checkpatch.pl coding style warnings > > hw/ppc/Makefile.objs | 1 + > hw/ppc/pnv.c | 87 ++++++++++++--- > hw/ppc/pnv_homer.c | 272 +++++++++++++++++++++++++++++++++++++++++++++ > hw/ppc/pnv_occ.c | 78 +++++++++++++ > hw/ppc/pnv_xscom.c | 34 +++++- > include/hw/ppc/pnv.h | 21 ++++ > include/hw/ppc/pnv_homer.h | 53 +++++++++ > include/hw/ppc/pnv_occ.h | 3 + > 8 files changed, 528 insertions(+), 21 deletions(-) > create mode 100644 hw/ppc/pnv_homer.c > create mode 100644 include/hw/ppc/pnv_homer.h > -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson
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