[Qemu-devel] [PULL 00/21] target-arm queue
[PULL 00/35] target-arm queue
1
target-arm queue: this time around is all small fixes
1
The following changes since commit 5767815218efd3cbfd409505ed824d5f356044ae:
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and changes.
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2
4
thanks
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Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2024-02-14 15:45:52 +0000)
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-- PMM
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7
The following changes since commit fec105c2abda8567ec15230429c41429b5ee307c:
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9
Merge remote-tracking branch 'remotes/kraxel/tags/audio-20190828-pull-request' into staging (2019-09-03 14:03:15 +0100)
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4
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are available in the Git repository at:
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are available in the Git repository at:
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13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190903
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240215
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8
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for you to fetch changes up to 5e5584c89f36b302c666bc6db535fd3f7ff35ad2:
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for you to fetch changes up to f780e63fe731b058fe52d43653600d8729a1b5f2:
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target/arm: Don't abort on M-profile exception return in linux-user mode (2019-09-03 16:20:35 +0100)
11
docs: Add documentation for the mps3-an536 board (2024-02-15 14:32:39 +0000)
18
12
19
----------------------------------------------------------------
13
----------------------------------------------------------------
20
target-arm queue:
14
target-arm queue:
21
* Revert and correctly fix refactoring of unallocated_encoding()
15
* hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
22
* Take exceptions on ATS instructions when needed
16
* linux-user/aarch64: Choose SYNC as the preferred MTE mode
23
* aspeed/timer: Provide back-pressure information for short periods
17
* Fix some errors in SVE/SME handling of MTE tags
24
* memory: Remove unused memory_region_iommu_replay_all()
18
* hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
25
* hw/arm/smmuv3: Log a guest error when decoding an invalid STE
19
* hw/block/tc58128: Don't emit deprecation warning under qtest
26
* hw/arm/smmuv3: Remove spurious error messages on IOVA invalidations
20
* tests/qtest: Fix handling of npcm7xx and GMAC tests
27
* target/arm: Fix SMMLS argument order
21
* hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
28
* hw/arm: Use ARM_CPU_TYPE_NAME() macro when appropriate
22
* tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
29
* hw/arm: Correct reference counting for creation of various objects
23
* Don't assert on vmload/vmsave of M-profile CPUs
30
* includes: remove stale [smp|max]_cpus externs
24
* hw/arm/smmuv3: add support for stage 1 access fault
31
* tcg/README: fix typo
25
* hw/arm/stellaris: QOM cleanups
32
* atomic_template: fix indentation in GEN_ATOMIC_HELPER
26
* Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
33
* include/exec/cpu-defs.h: fix typo
27
* Improve Cortex_R52 IMPDEF sysreg modelling
34
* target/arm: Free TCG temps in trans_VMOV_64_sp()
28
* Allow access to SPSR_hyp from hyp mode
35
* target/arm: Don't abort on M-profile exception return in linux-user mode
29
* New board model mps3-an536 (Cortex-R52)
36
30
37
----------------------------------------------------------------
31
----------------------------------------------------------------
38
Alex Bennée (2):
32
Luc Michel (1):
39
includes: remove stale [smp|max]_cpus externs
33
hw/arm/smmuv3: add support for stage 1 access fault
40
include/exec/cpu-defs.h: fix typo
41
34
42
Andrew Jeffery (1):
35
Nabih Estefan (1):
43
aspeed/timer: Provide back-pressure information for short periods
36
tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
44
37
45
Emilio G. Cota (2):
38
Peter Maydell (22):
46
tcg/README: fix typo s/afterwise/afterwards/
39
hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
47
atomic_template: fix indentation in GEN_ATOMIC_HELPER
40
hw/block/tc58128: Don't emit deprecation warning under qtest
41
tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
42
tests/qtest/bios-tables-test: Allow changes to virt GTDT
43
hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
44
tests/qtest/bios-tables-tests: Update virt golden reference
45
hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
46
tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
47
target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
48
target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
49
target/arm: The Cortex-R52 has a read-only CBAR
50
target/arm: Add Cortex-R52 IMPDEF sysregs
51
target/arm: Allow access to SPSR_hyp from hyp mode
52
hw/misc/mps2-scc: Fix condition for CFG3 register
53
hw/misc/mps2-scc: Factor out which-board conditionals
54
hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
55
hw/arm/mps3r: Initial skeleton for mps3-an536 board
56
hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
57
hw/arm/mps3r: Add UARTs
58
hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
59
hw/arm/mps3r: Add remaining devices
60
docs: Add documentation for the mps3-an536 board
48
61
49
Eric Auger (3):
62
Philippe Mathieu-Daudé (5):
50
memory: Remove unused memory_region_iommu_replay_all()
63
hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
51
hw/arm/smmuv3: Log a guest error when decoding an invalid STE
64
hw/arm/stellaris: Convert ADC controller to Resettable interface
52
hw/arm/smmuv3: Remove spurious error messages on IOVA invalidations
65
hw/arm/stellaris: Convert I2C controller to Resettable interface
66
hw/arm/stellaris: Add missing QOM 'machine' parent
67
hw/arm/stellaris: Add missing QOM 'SoC' parent
53
68
54
Peter Maydell (4):
69
Richard Henderson (6):
55
target/arm: Allow ARMCPRegInfo read/write functions to throw exceptions
70
linux-user/aarch64: Choose SYNC as the preferred MTE mode
56
target/arm: Take exceptions on ATS instructions when needed
71
target/arm: Fix nregs computation in do_{ld,st}_zpa
57
target/arm: Free TCG temps in trans_VMOV_64_sp()
72
target/arm: Adjust and validate mtedesc sizem1
58
target/arm: Don't abort on M-profile exception return in linux-user mode
73
target/arm: Split out make_svemte_desc
74
target/arm: Handle mte in do_ldrq, do_ldro
75
target/arm: Fix SVE/SME gross MTE suppression checks
59
76
60
Philippe Mathieu-Daudé (6):
77
MAINTAINERS | 3 +-
61
hw/arm: Use ARM_CPU_TYPE_NAME() macro when appropriate
78
docs/system/arm/mps2.rst | 37 +-
62
hw/arm: Use object_initialize_child for correct reference counting
79
configs/devices/arm-softmmu/default.mak | 1 +
63
hw/arm: Use sysbus_init_child_obj for correct reference counting
80
hw/arm/smmuv3-internal.h | 1 +
64
hw/arm/fsl-imx: Add the cpu as child of the SoC object
81
include/hw/arm/smmu-common.h | 1 +
65
hw/dma/xilinx_axi: Use object_initialize_child for correct ref. counting
82
include/hw/arm/virt.h | 2 +
66
hw/net/xilinx_axi: Use object_initialize_child for correct ref. counting
83
include/hw/misc/mps2-scc.h | 1 +
84
linux-user/aarch64/target_prctl.h | 29 +-
85
target/arm/internals.h | 2 +-
86
target/arm/tcg/translate-a64.h | 2 +
87
hw/arm/mps3r.c | 640 ++++++++++++++++++++++++++++++++
88
hw/arm/npcm7xx.c | 1 +
89
hw/arm/smmu-common.c | 11 +
90
hw/arm/smmuv3.c | 1 +
91
hw/arm/stellaris.c | 47 ++-
92
hw/arm/virt-acpi-build.c | 20 +-
93
hw/arm/virt.c | 60 ++-
94
hw/arm/xilinx_zynq.c | 2 +
95
hw/block/tc58128.c | 4 +-
96
hw/misc/mps2-scc.c | 138 ++++++-
97
hw/pci-host/raven.c | 1 +
98
target/arm/helper.c | 14 +-
99
target/arm/tcg/cpu32.c | 109 ++++++
100
target/arm/tcg/op_helper.c | 43 ++-
101
target/arm/tcg/sme_helper.c | 8 +-
102
target/arm/tcg/sve_helper.c | 12 +-
103
target/arm/tcg/translate-sme.c | 15 +-
104
target/arm/tcg/translate-sve.c | 83 +++--
105
target/arm/tcg/translate.c | 19 +-
106
tests/qtest/npcm7xx_emc-test.c | 5 +-
107
tests/qtest/npcm_gmac-test.c | 84 +----
108
hw/arm/Kconfig | 5 +
109
hw/arm/meson.build | 1 +
110
tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes
111
tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes
112
tests/qtest/meson.build | 4 +-
113
36 files changed, 1184 insertions(+), 222 deletions(-)
114
create mode 100644 hw/arm/mps3r.c
67
115
68
Richard Henderson (3):
69
Revert "target/arm: Use unallocated_encoding for aarch32"
70
target/arm: Factor out unallocated_encoding for aarch32
71
target/arm: Fix SMMLS argument order
72
73
accel/tcg/atomic_template.h | 2 +-
74
hw/arm/smmuv3-internal.h | 1 +
75
include/exec/cpu-defs.h | 2 +-
76
include/exec/memory.h | 10 ----
77
include/sysemu/sysemu.h | 2 -
78
target/arm/cpu.h | 6 ++-
79
target/arm/translate-a64.h | 2 +
80
target/arm/translate.h | 2 -
81
hw/arm/allwinner-a10.c | 3 +-
82
hw/arm/cubieboard.c | 3 +-
83
hw/arm/digic.c | 3 +-
84
hw/arm/exynos4_boards.c | 4 +-
85
hw/arm/fsl-imx25.c | 4 +-
86
hw/arm/fsl-imx31.c | 4 +-
87
hw/arm/fsl-imx6.c | 3 +-
88
hw/arm/fsl-imx6ul.c | 2 +-
89
hw/arm/mcimx7d-sabre.c | 9 ++--
90
hw/arm/mps2-tz.c | 15 +++---
91
hw/arm/musca.c | 9 ++--
92
hw/arm/smmuv3.c | 18 ++++---
93
hw/arm/xlnx-zynqmp.c | 8 +--
94
hw/dma/xilinx_axidma.c | 16 +++---
95
hw/net/xilinx_axienet.c | 17 +++----
96
hw/timer/aspeed_timer.c | 17 ++++++-
97
memory.c | 9 ----
98
target/arm/helper.c | 107 +++++++++++++++++++++++++++++++++++------
99
target/arm/translate-a64.c | 13 +++++
100
target/arm/translate-vfp.inc.c | 2 +
101
target/arm/translate.c | 50 +++++++++++++++++--
102
tcg/README | 2 +-
103
30 files changed, 244 insertions(+), 101 deletions(-)
104
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/21] tcg/README: fix typo s/afterwise/afterwards/
[PULL 01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
1
From: "Emilio G. Cota" <cota@braap.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Afterwise is "wise after the fact", as in "hindsight".
3
Similarly to commits dadbb58f59..5ae79fe825 for other ARM boards,
4
Here we meant "afterwards" (as in "subsequently"). Fix it.
4
connect FIQ output of the GIC CPU interfaces to the CPU.
5
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Signed-off-by: Emilio G. Cota <cota@braap.org>
7
Message-id: 20240130152548.17855-1-philmd@linaro.org
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20190828165307.18321-7-alex.bennee@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
tcg/README | 2 +-
11
hw/arm/xilinx_zynq.c | 2 ++
15
1 file changed, 1 insertion(+), 1 deletion(-)
12
1 file changed, 2 insertions(+)
16
13
17
diff --git a/tcg/README b/tcg/README
14
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/tcg/README
16
--- a/hw/arm/xilinx_zynq.c
20
+++ b/tcg/README
17
+++ b/hw/arm/xilinx_zynq.c
21
@@ -XXX,XX +XXX,XX @@ This can be overridden using the following function modifiers:
18
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
22
canonical locations before calling the helper.
19
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
23
- TCG_CALL_NO_WRITE_GLOBALS means that the helper does not modify any globals.
20
sysbus_connect_irq(busdev, 0,
24
They will only be saved to their canonical location before calling helpers,
21
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
25
- but they won't be reloaded afterwise.
22
+ sysbus_connect_irq(busdev, 1,
26
+ but they won't be reloaded afterwards.
23
+ qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ));
27
- TCG_CALL_NO_SIDE_EFFECTS means that the call to the function is removed if
24
28
the return value is not used.
25
for (n = 0; n < 64; n++) {
29
26
pic[n] = qdev_get_gpio_in(dev, n);
30
--
27
--
31
2.20.1
28
2.34.1
32
29
33
30
diff view generated by jsdifflib
New patch
[PULL 02/35] linux-user/aarch64: Choose SYNC as the preferred MTE mode
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The API does not generate an error for setting ASYNC | SYNC; that merely
4
constrains the selection vs the per-cpu default. For qemu linux-user,
5
choose SYNC as the default.
6
7
Cc: qemu-stable@nongnu.org
8
Reported-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
11
Message-id: 20240207025210.8837-2-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
linux-user/aarch64/target_prctl.h | 29 +++++++++++++++++------------
15
1 file changed, 17 insertions(+), 12 deletions(-)
16
17
diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/linux-user/aarch64/target_prctl.h
20
+++ b/linux-user/aarch64/target_prctl.h
21
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
22
env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;
23
24
if (cpu_isar_feature(aa64_mte, cpu)) {
25
- switch (arg2 & PR_MTE_TCF_MASK) {
26
- case PR_MTE_TCF_NONE:
27
- case PR_MTE_TCF_SYNC:
28
- case PR_MTE_TCF_ASYNC:
29
- break;
30
- default:
31
- return -EINVAL;
32
- }
33
-
34
/*
35
* Write PR_MTE_TCF to SCTLR_EL1[TCF0].
36
- * Note that the syscall values are consistent with hw.
37
+ *
38
+ * The kernel has a per-cpu configuration for the sysadmin,
39
+ * /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred,
40
+ * which qemu does not implement.
41
+ *
42
+ * Because there is no performance difference between the modes, and
43
+ * because SYNC is most useful for debugging MTE errors, choose SYNC
44
+ * as the preferred mode. With this preference, and the way the API
45
+ * uses only two bits, there is no way for the program to select
46
+ * ASYMM mode.
47
*/
48
- env->cp15.sctlr_el[1] =
49
- deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHIFT);
50
+ unsigned tcf = 0;
51
+ if (arg2 & PR_MTE_TCF_SYNC) {
52
+ tcf = 1;
53
+ } else if (arg2 & PR_MTE_TCF_ASYNC) {
54
+ tcf = 2;
55
+ }
56
+ env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf);
57
58
/*
59
* Write PR_MTE_TAG to GCR_EL1[Exclude].
60
--
61
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/21] target/arm: Don't abort on M-profile exception return in linux-user mode
[PULL 03/35] target/arm: Fix nregs computation in do_{ld,st}_zpa
1
An attempt to do an exception-return (branch to one of the magic
1
From: Richard Henderson <richard.henderson@linaro.org>
2
addresses) in linux-user mode for M-profile should behave like
3
a normal branch, because linux-user mode is always going to be
4
in 'handler' mode. This used to work, but we broke it when we added
5
support for the M-profile security extension in commit d02a8698d7ae2bfed.
6
2
7
In that commit we allowed even handler-mode calls to magic return
3
The field is encoded as [0-3], which is convenient for
8
values to be checked for and dealt with by causing an
4
indexing our array of function pointers, but the true
9
EXCP_EXCEPTION_EXIT exception to be taken, because this is
5
value is [1-4]. Adjust before calling do_mem_zpa.
10
needed for the FNC_RETURN return-from-non-secure-function-call
11
handling. For system mode we added a check in do_v7m_exception_exit()
12
to make any spurious calls from Handler mode behave correctly, but
13
forgot that linux-user mode would also be affected.
14
6
15
How an attempted return-from-non-secure-function-call in linux-user
7
Add an assert, and move the comment re passing ZT to
16
mode should be handled is not clear -- on real hardware it would
8
the helper back next to the relevant code.
17
result in return to secure code (not to the Linux kernel) which
18
could then handle the error in any way it chose. For QEMU we take
19
the simple approach of treating this erroneous return the same way
20
it would be handled on a CPU without the security extensions --
21
treat it as a normal branch.
22
23
The upshot of all this is that for linux-user mode we should never
24
do any of the bx_excret magic, so the code change is simple.
25
26
This ought to be a weird corner case that only affects broken guest
27
code (because Linux user processes should never be attempting to do
28
exception returns or NS function returns), except that the code that
29
assigns addresses in RAM for the process and stack in our linux-user
30
code does not attempt to avoid this magic address range, so
31
legitimate code attempting to return to a trampoline routine on the
32
stack can fall into this case. This change fixes those programs,
33
but we should also look at restricting the range of memory we
34
use for M-profile linux-user guests to the area that would be
35
real RAM in hardware.
36
9
37
Cc: qemu-stable@nongnu.org
10
Cc: qemu-stable@nongnu.org
38
Reported-by: Christophe Lyon <christophe.lyon@linaro.org>
11
Fixes: 206adacfb8d ("target/arm: Add mte helpers for sve scalar + int loads")
39
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
40
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
41
Message-id: 20190822131534.16602-1-peter.maydell@linaro.org
14
Message-id: 20240207025210.8837-3-richard.henderson@linaro.org
42
Fixes: https://bugs.launchpad.net/qemu/+bug/1840922
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
43
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
44
---
17
---
45
target/arm/translate.c | 21 ++++++++++++++++++++-
18
target/arm/tcg/translate-sve.c | 16 ++++++++--------
46
1 file changed, 20 insertions(+), 1 deletion(-)
19
1 file changed, 8 insertions(+), 8 deletions(-)
47
20
48
diff --git a/target/arm/translate.c b/target/arm/translate.c
21
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
49
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/translate.c
23
--- a/target/arm/tcg/translate-sve.c
51
+++ b/target/arm/translate.c
24
+++ b/target/arm/tcg/translate-sve.c
52
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx(DisasContext *s, TCGv_i32 var)
25
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
53
store_cpu_field(var, thumb);
26
TCGv_ptr t_pg;
27
int desc = 0;
28
29
- /*
30
- * For e.g. LD4, there are not enough arguments to pass all 4
31
- * registers as pointers, so encode the regno into the data field.
32
- * For consistency, do this even for LD1.
33
- */
34
+ assert(mte_n >= 1 && mte_n <= 4);
35
if (s->mte_active[0]) {
36
int msz = dtype_msz(dtype);
37
38
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
39
addr = clean_data_tbi(s, addr);
40
}
41
42
+ /*
43
+ * For e.g. LD4, there are not enough arguments to pass all 4
44
+ * registers as pointers, so encode the regno into the data field.
45
+ * For consistency, do this even for LD1.
46
+ */
47
desc = simd_desc(vsz, vsz, zt | desc);
48
t_pg = tcg_temp_new_ptr();
49
50
@@ -XXX,XX +XXX,XX @@ static void do_ld_zpa(DisasContext *s, int zt, int pg,
51
* accessible via the instruction encoding.
52
*/
53
assert(fn != NULL);
54
- do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn);
55
+ do_mem_zpa(s, zt, pg, addr, dtype, nreg + 1, false, fn);
54
}
56
}
55
57
56
-/* Set PC and Thumb state from var. var is marked as dead.
58
static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a)
57
+/*
59
@@ -XXX,XX +XXX,XX @@ static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
58
+ * Set PC and Thumb state from var. var is marked as dead.
60
if (nreg == 0) {
59
* For M-profile CPUs, include logic to detect exception-return
61
/* ST1 */
60
* branches and handle them. This is needed for Thumb POP/LDM to PC, LDR to PC,
62
fn = fn_single[s->mte_active[0]][be][msz][esz];
61
* and BX reg, and no others, and happens only for code in Handler mode.
63
- nreg = 1;
62
+ * The Security Extension also requires us to check for the FNC_RETURN
64
} else {
63
+ * which signals a function return from non-secure state; this can happen
65
/* ST2, ST3, ST4 -- msz == esz, enforced by encoding */
64
+ * in both Handler and Thread mode.
66
assert(msz == esz);
65
+ * To avoid having to do multiple comparisons in inline generated code,
67
fn = fn_multiple[s->mte_active[0]][be][nreg - 1][msz];
66
+ * we make the check we do here loose, so it will match for EXC_RETURN
67
+ * in Thread mode. For system emulation do_v7m_exception_exit() checks
68
+ * for these spurious cases and returns without doing anything (giving
69
+ * the same behaviour as for a branch to a non-magic address).
70
+ *
71
+ * In linux-user mode it is unclear what the right behaviour for an
72
+ * attempted FNC_RETURN should be, because in real hardware this will go
73
+ * directly to Secure code (ie not the Linux kernel) which will then treat
74
+ * the error in any way it chooses. For QEMU we opt to make the FNC_RETURN
75
+ * attempt behave the way it would on a CPU without the security extension,
76
+ * which is to say "like a normal branch". That means we can simply treat
77
+ * all branches as normal with no magic address behaviour.
78
*/
79
static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var)
80
{
81
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var)
82
* s->base.is_jmp that we need to do the rest of the work later.
83
*/
84
gen_bx(s, var);
85
+#ifndef CONFIG_USER_ONLY
86
if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY) ||
87
(s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M))) {
88
s->base.is_jmp = DISAS_BX_EXCRET;
89
}
68
}
90
+#endif
69
assert(fn != NULL);
70
- do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg, true, fn);
71
+ do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg + 1, true, fn);
91
}
72
}
92
73
93
static inline void gen_bx_excret_final_code(DisasContext *s)
74
static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a)
94
--
75
--
95
2.20.1
76
2.34.1
96
97
diff view generated by jsdifflib
New patch
[PULL 04/35] target/arm: Adjust and validate mtedesc sizem1
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
When we added SVE_MTEDESC_SHIFT, we effectively limited the
4
maximum size of MTEDESC. Adjust SIZEM1 to consume the remaining
5
bits (32 - 10 - 5 - 12 == 5). Assert that the data to be stored
6
fits within the field (expecting 8 * 4 - 1 == 31, exact fit).
7
8
Cc: qemu-stable@nongnu.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
12
Message-id: 20240207025210.8837-4-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/internals.h | 2 +-
16
target/arm/tcg/translate-sve.c | 7 ++++---
17
2 files changed, 5 insertions(+), 4 deletions(-)
18
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/internals.h
22
+++ b/target/arm/internals.h
23
@@ -XXX,XX +XXX,XX @@ FIELD(MTEDESC, TBI, 4, 2)
24
FIELD(MTEDESC, TCMA, 6, 2)
25
FIELD(MTEDESC, WRITE, 8, 1)
26
FIELD(MTEDESC, ALIGN, 9, 3)
27
-FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - 12) /* size - 1 */
28
+FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - SVE_MTEDESC_SHIFT - 12) /* size - 1 */
29
30
bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr);
31
uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra);
32
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/tcg/translate-sve.c
35
+++ b/target/arm/tcg/translate-sve.c
36
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
37
{
38
unsigned vsz = vec_full_reg_size(s);
39
TCGv_ptr t_pg;
40
+ uint32_t sizem1;
41
int desc = 0;
42
43
assert(mte_n >= 1 && mte_n <= 4);
44
+ sizem1 = (mte_n << dtype_msz(dtype)) - 1;
45
+ assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
46
if (s->mte_active[0]) {
47
- int msz = dtype_msz(dtype);
48
-
49
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
50
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
51
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
52
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
53
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (mte_n << msz) - 1);
54
+ desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
55
desc <<= SVE_MTEDESC_SHIFT;
56
} else {
57
addr = clean_data_tbi(s, addr);
58
--
59
2.34.1
diff view generated by jsdifflib
New patch
[PULL 05/35] target/arm: Split out make_svemte_desc
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Share code that creates mtedesc and embeds within simd_desc.
4
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Message-id: 20240207025210.8837-5-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/tcg/translate-a64.h | 2 ++
13
target/arm/tcg/translate-sme.c | 15 +++--------
14
target/arm/tcg/translate-sve.c | 47 ++++++++++++++++++----------------
15
3 files changed, 31 insertions(+), 33 deletions(-)
16
17
diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/tcg/translate-a64.h
20
+++ b/target/arm/tcg/translate-a64.h
21
@@ -XXX,XX +XXX,XX @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
22
bool sve_access_check(DisasContext *s);
23
bool sme_enabled_check(DisasContext *s);
24
bool sme_enabled_check_with_svcr(DisasContext *s, unsigned);
25
+uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
26
+ uint32_t msz, bool is_write, uint32_t data);
27
28
/* This function corresponds to CheckStreamingSVEEnabled. */
29
static inline bool sme_sm_enabled_check(DisasContext *s)
30
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/tcg/translate-sme.c
33
+++ b/target/arm/tcg/translate-sme.c
34
@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
35
36
TCGv_ptr t_za, t_pg;
37
TCGv_i64 addr;
38
- int svl, desc = 0;
39
+ uint32_t desc;
40
bool be = s->be_data == MO_BE;
41
bool mte = s->mte_active[0];
42
43
@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
44
tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz);
45
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
46
47
- if (mte) {
48
- desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
49
- desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
50
- desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
51
- desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st);
52
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1);
53
- desc <<= SVE_MTEDESC_SHIFT;
54
- } else {
55
+ if (!mte) {
56
addr = clean_data_tbi(s, addr);
57
}
58
- svl = streaming_vec_reg_size(s);
59
- desc = simd_desc(svl, svl, desc);
60
+
61
+ desc = make_svemte_desc(s, streaming_vec_reg_size(s), 1, a->esz, a->st, 0);
62
63
fns[a->esz][be][a->v][mte][a->st](tcg_env, t_za, t_pg, addr,
64
tcg_constant_i32(desc));
65
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/target/arm/tcg/translate-sve.c
68
+++ b/target/arm/tcg/translate-sve.c
69
@@ -XXX,XX +XXX,XX @@ static const uint8_t dtype_esz[16] = {
70
3, 2, 1, 3
71
};
72
73
-static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
74
- int dtype, uint32_t mte_n, bool is_write,
75
- gen_helper_gvec_mem *fn)
76
+uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
77
+ uint32_t msz, bool is_write, uint32_t data)
78
{
79
- unsigned vsz = vec_full_reg_size(s);
80
- TCGv_ptr t_pg;
81
uint32_t sizem1;
82
- int desc = 0;
83
+ uint32_t desc = 0;
84
85
- assert(mte_n >= 1 && mte_n <= 4);
86
- sizem1 = (mte_n << dtype_msz(dtype)) - 1;
87
+ /* Assert all of the data fits, with or without MTE enabled. */
88
+ assert(nregs >= 1 && nregs <= 4);
89
+ sizem1 = (nregs << msz) - 1;
90
assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
91
+ assert(data < 1u << SVE_MTEDESC_SHIFT);
92
+
93
if (s->mte_active[0]) {
94
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
95
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
96
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
97
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
98
desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
99
desc <<= SVE_MTEDESC_SHIFT;
100
- } else {
101
+ }
102
+ return simd_desc(vsz, vsz, desc | data);
103
+}
104
+
105
+static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
106
+ int dtype, uint32_t nregs, bool is_write,
107
+ gen_helper_gvec_mem *fn)
108
+{
109
+ TCGv_ptr t_pg;
110
+ uint32_t desc;
111
+
112
+ if (!s->mte_active[0]) {
113
addr = clean_data_tbi(s, addr);
114
}
115
116
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
117
* registers as pointers, so encode the regno into the data field.
118
* For consistency, do this even for LD1.
119
*/
120
- desc = simd_desc(vsz, vsz, zt | desc);
121
+ desc = make_svemte_desc(s, vec_full_reg_size(s), nregs,
122
+ dtype_msz(dtype), is_write, zt);
123
t_pg = tcg_temp_new_ptr();
124
125
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
126
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
127
int scale, TCGv_i64 scalar, int msz, bool is_write,
128
gen_helper_gvec_mem_scatter *fn)
129
{
130
- unsigned vsz = vec_full_reg_size(s);
131
TCGv_ptr t_zm = tcg_temp_new_ptr();
132
TCGv_ptr t_pg = tcg_temp_new_ptr();
133
TCGv_ptr t_zt = tcg_temp_new_ptr();
134
- int desc = 0;
135
-
136
- if (s->mte_active[0]) {
137
- desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
138
- desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
139
- desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
140
- desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
141
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1);
142
- desc <<= SVE_MTEDESC_SHIFT;
143
- }
144
- desc = simd_desc(vsz, vsz, desc | scale);
145
+ uint32_t desc;
146
147
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
148
tcg_gen_addi_ptr(t_zm, tcg_env, vec_full_reg_offset(s, zm));
149
tcg_gen_addi_ptr(t_zt, tcg_env, vec_full_reg_offset(s, zt));
150
+
151
+ desc = make_svemte_desc(s, vec_full_reg_size(s), 1, msz, is_write, scale);
152
fn(tcg_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc));
153
}
154
155
--
156
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/21] target/arm: Fix SMMLS argument order
[PULL 06/35] target/arm: Handle mte in do_ldrq, do_ldro
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The previous simplification got the order of operands to the
3
These functions "use the standard load helpers", but
4
subtraction wrong. Since the 64-bit product is the subtrahend,
4
fail to clean_data_tbi or populate mtedesc.
5
we must use a 64-bit subtract to properly compute the borrow
6
from the low-part of the product.
7
5
8
Fixes: 5f8cd06ebcf5 ("target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR")
6
Cc: qemu-stable@nongnu.org
9
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
9
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
12
Message-id: 20190829013258.16102-1-richard.henderson@linaro.org
10
Message-id: 20240207025210.8837-6-richard.henderson@linaro.org
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
12
---
16
target/arm/translate.c | 20 ++++++++++++++++++--
13
target/arm/tcg/translate-sve.c | 15 +++++++++++++--
17
1 file changed, 18 insertions(+), 2 deletions(-)
14
1 file changed, 13 insertions(+), 2 deletions(-)
18
15
19
diff --git a/target/arm/translate.c b/target/arm/translate.c
16
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
20
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/translate.c
18
--- a/target/arm/tcg/translate-sve.c
22
+++ b/target/arm/translate.c
19
+++ b/target/arm/tcg/translate-sve.c
23
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
20
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
24
if (rd != 15) {
21
unsigned vsz = vec_full_reg_size(s);
25
tmp3 = load_reg(s, rd);
22
TCGv_ptr t_pg;
26
if (insn & (1 << 6)) {
23
int poff;
27
- tcg_gen_sub_i32(tmp, tmp, tmp3);
24
+ uint32_t desc;
28
+ /*
25
29
+ * For SMMLS, we need a 64-bit subtract.
26
/* Load the first quadword using the normal predicated load helpers. */
30
+ * Borrow caused by a non-zero multiplicand
27
+ if (!s->mte_active[0]) {
31
+ * lowpart, and the correct result lowpart
28
+ addr = clean_data_tbi(s, addr);
32
+ * for rounding.
29
+ }
33
+ */
30
+
34
+ TCGv_i32 zero = tcg_const_i32(0);
31
poff = pred_full_reg_offset(s, pg);
35
+ tcg_gen_sub2_i32(tmp2, tmp, zero, tmp3,
32
if (vsz > 16) {
36
+ tmp2, tmp);
33
/*
37
+ tcg_temp_free_i32(zero);
34
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
38
} else {
35
39
tcg_gen_add_i32(tmp, tmp, tmp3);
36
gen_helper_gvec_mem *fn
40
}
37
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
41
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
38
- fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt)));
42
if (insn & (1 << 20)) {
39
+ desc = make_svemte_desc(s, 16, 1, dtype_msz(dtype), false, zt);
43
tcg_gen_add_i32(tmp, tmp, tmp3);
40
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
44
} else {
41
45
- tcg_gen_sub_i32(tmp, tmp, tmp3);
42
/* Replicate that first quadword. */
46
+ /*
43
if (vsz > 16) {
47
+ * For SMMLS, we need a 64-bit subtract.
44
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
48
+ * Borrow caused by a non-zero multiplicand lowpart,
45
unsigned vsz_r32;
49
+ * and the correct result lowpart for rounding.
46
TCGv_ptr t_pg;
50
+ */
47
int poff, doff;
51
+ TCGv_i32 zero = tcg_const_i32(0);
48
+ uint32_t desc;
52
+ tcg_gen_sub2_i32(tmp2, tmp, zero, tmp3, tmp2, tmp);
49
53
+ tcg_temp_free_i32(zero);
50
if (vsz < 32) {
54
}
51
/*
55
tcg_temp_free_i32(tmp3);
52
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
56
}
53
}
54
55
/* Load the first octaword using the normal predicated load helpers. */
56
+ if (!s->mte_active[0]) {
57
+ addr = clean_data_tbi(s, addr);
58
+ }
59
60
poff = pred_full_reg_offset(s, pg);
61
if (vsz > 32) {
62
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
63
64
gen_helper_gvec_mem *fn
65
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
66
- fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt)));
67
+ desc = make_svemte_desc(s, 32, 1, dtype_msz(dtype), false, zt);
68
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
69
70
/*
71
* Replicate that first octaword.
57
--
72
--
58
2.20.1
73
2.34.1
59
60
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/21] target/arm: Factor out unallocated_encoding for aarch32
[PULL 07/35] target/arm: Fix SVE/SME gross MTE suppression checks
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Make this a static function private to translate.c.
3
The TBI and TCMA bits are located within mtedesc, not desc.
4
Thus we can use the same idiom between aarch64 and aarch32
5
without actually sharing function implementations.
6
4
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Message-id: 20190826151536.6771-3-richard.henderson@linaro.org
9
Message-id: 20240207025210.8837-7-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
target/arm/translate-vfp.inc.c | 3 +--
12
target/arm/tcg/sme_helper.c | 8 ++++----
13
target/arm/translate.c | 22 ++++++++++++----------
13
target/arm/tcg/sve_helper.c | 12 ++++++------
14
2 files changed, 13 insertions(+), 12 deletions(-)
14
2 files changed, 10 insertions(+), 10 deletions(-)
15
15
16
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
16
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-vfp.inc.c
18
--- a/target/arm/tcg/sme_helper.c
19
+++ b/target/arm/translate-vfp.inc.c
19
+++ b/target/arm/tcg/sme_helper.c
20
@@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
20
@@ -XXX,XX +XXX,XX @@ void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg,
21
21
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
22
if (!s->vfp_enabled && !ignore_vfp_enabled) {
22
23
assert(!arm_dc_feature(s, ARM_FEATURE_M));
23
/* Perform gross MTE suppression early. */
24
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
24
- if (!tbi_check(desc, bit55) ||
25
- default_exception_el(s));
25
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
26
+ unallocated_encoding(s);
26
+ if (!tbi_check(mtedesc, bit55) ||
27
return false;
27
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
28
mtedesc = 0;
28
}
29
}
29
30
30
diff --git a/target/arm/translate.c b/target/arm/translate.c
31
@@ -XXX,XX +XXX,XX @@ void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong addr,
32
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
33
34
/* Perform gross MTE suppression early. */
35
- if (!tbi_check(desc, bit55) ||
36
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
37
+ if (!tbi_check(mtedesc, bit55) ||
38
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
39
mtedesc = 0;
40
}
41
42
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
31
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/translate.c
44
--- a/target/arm/tcg/sve_helper.c
33
+++ b/target/arm/translate.c
45
+++ b/target/arm/tcg/sve_helper.c
34
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
46
@@ -XXX,XX +XXX,XX @@ void sve_ldN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
35
s->base.is_jmp = DISAS_NORETURN;
47
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
36
}
48
37
49
/* Perform gross MTE suppression early. */
38
+static void unallocated_encoding(DisasContext *s)
50
- if (!tbi_check(desc, bit55) ||
39
+{
51
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
40
+ /* Unallocated and reserved encodings are uncategorized */
52
+ if (!tbi_check(mtedesc, bit55) ||
41
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
53
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
42
+ default_exception_el(s));
54
mtedesc = 0;
43
+}
44
+
45
/* Force a TB lookup after an instruction that changes the CPU state. */
46
static inline void gen_lookup_tb(DisasContext *s)
47
{
48
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
49
return;
50
}
55
}
51
56
52
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
57
@@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r_mte(CPUARMState *env, void *vg, target_ulong addr,
53
- default_exception_el(s));
58
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
54
+ unallocated_encoding(s);
59
55
}
60
/* Perform gross MTE suppression early. */
56
61
- if (!tbi_check(desc, bit55) ||
57
static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
62
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
58
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
63
+ if (!tbi_check(mtedesc, bit55) ||
64
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
65
mtedesc = 0;
59
}
66
}
60
67
61
if (undef) {
68
@@ -XXX,XX +XXX,XX @@ void sve_stN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
62
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
69
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
63
- default_exception_el(s));
70
64
+ unallocated_encoding(s);
71
/* Perform gross MTE suppression early. */
65
return;
72
- if (!tbi_check(desc, bit55) ||
73
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
74
+ if (!tbi_check(mtedesc, bit55) ||
75
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
76
mtedesc = 0;
66
}
77
}
67
78
68
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
69
break;
70
default:
71
illegal_op:
72
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
73
- default_exception_el(s));
74
+ unallocated_encoding(s);
75
break;
76
}
77
}
78
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
79
}
80
return;
81
illegal_op:
82
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
83
- default_exception_el(s));
84
+ unallocated_encoding(s);
85
}
86
87
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
88
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
89
return;
90
illegal_op:
91
undef:
92
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
93
- default_exception_el(s));
94
+ unallocated_encoding(s);
95
}
96
97
static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
98
--
79
--
99
2.20.1
80
2.34.1
100
101
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/21] hw/arm/smmuv3: Log a guest error when decoding an invalid STE
[PULL 08/35] hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
1
From: Eric Auger <eric.auger@redhat.com>
1
The raven_io_ops MemoryRegionOps is the only one in the source tree
2
which sets .valid.unaligned to indicate that it should support
3
unaligned accesses and which does not also set .impl.unaligned to
4
indicate that its read and write functions can do the unaligned
5
handling themselves. This is a problem, because at the moment the
6
core memory system does not implement the support for handling
7
unaligned accesses by doing a series of aligned accesses and
8
combining them (system/memory.c:access_with_adjusted_size() has a
9
TODO comment noting this).
2
10
3
Log a guest error when encountering an invalid STE.
11
Fortunately raven_io_read() and raven_io_write() will correctly deal
12
with the case of being passed an unaligned address, so we can fix the
13
missing unaligned access support by setting .impl.unaligned in the
14
MemoryRegionOps struct.
4
15
5
Signed-off-by: Eric Auger <eric.auger@redhat.com>
16
Fixes: 9a1839164c9c8f06 ("raven: Implement non-contiguous I/O region")
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-id: 20190822172350.12008-5-eric.auger@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Tested-by: Cédric Le Goater <clg@redhat.com>
19
Reviewed-by: Cédric Le Goater <clg@redhat.com>
20
Message-id: 20240112134640.1775041-1-peter.maydell@linaro.org
9
---
21
---
10
hw/arm/smmuv3.c | 1 +
22
hw/pci-host/raven.c | 1 +
11
1 file changed, 1 insertion(+)
23
1 file changed, 1 insertion(+)
12
24
13
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
25
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
14
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/smmuv3.c
27
--- a/hw/pci-host/raven.c
16
+++ b/hw/arm/smmuv3.c
28
+++ b/hw/pci-host/raven.c
17
@@ -XXX,XX +XXX,XX @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,
29
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps raven_io_ops = {
18
uint32_t config;
30
.write = raven_io_write,
19
31
.endianness = DEVICE_LITTLE_ENDIAN,
20
if (!STE_VALID(ste)) {
32
.impl.max_access_size = 4,
21
+ qemu_log_mask(LOG_GUEST_ERROR, "invalid STE\n");
33
+ .impl.unaligned = true,
22
goto bad_ste;
34
.valid.unaligned = true,
23
}
35
};
24
36
25
--
37
--
26
2.20.1
38
2.34.1
27
39
28
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/21] include/exec/cpu-defs.h: fix typo
[PULL 09/35] hw/block/tc58128: Don't emit deprecation warning under qtest
1
From: Alex Bennée <alex.bennee@linaro.org>
1
Suppress the deprecation warning when we're running under qtest,
2
to avoid "make check" including warning messages in its output.
2
3
3
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-id: 20190828165307.18321-10-alex.bennee@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Message-id: 20240206154151.155620-1-peter.maydell@linaro.org
9
---
7
---
10
include/exec/cpu-defs.h | 2 +-
8
hw/block/tc58128.c | 4 +++-
11
1 file changed, 1 insertion(+), 1 deletion(-)
9
1 file changed, 3 insertions(+), 1 deletion(-)
12
10
13
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
11
diff --git a/hw/block/tc58128.c b/hw/block/tc58128.c
14
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
15
--- a/include/exec/cpu-defs.h
13
--- a/hw/block/tc58128.c
16
+++ b/include/exec/cpu-defs.h
14
+++ b/hw/block/tc58128.c
17
@@ -XXX,XX +XXX,XX @@ typedef struct CPUTLB { } CPUTLB;
15
@@ -XXX,XX +XXX,XX @@ static sh7750_io_device tc58128 = {
18
#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
16
19
17
int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2)
20
/*
18
{
21
- * This structure must be placed in ArchCPU immedately
19
- warn_report_once("The TC58128 flash device is deprecated");
22
+ * This structure must be placed in ArchCPU immediately
20
+ if (!qtest_enabled()) {
23
* before CPUArchState, as a field named "neg".
21
+ warn_report_once("The TC58128 flash device is deprecated");
24
*/
22
+ }
25
typedef struct CPUNegativeOffsetState {
23
init_dev(&tc58128_devs[0], zone1);
24
init_dev(&tc58128_devs[1], zone2);
25
return sh7750_register_io_device(s, &tc58128);
26
--
26
--
27
2.20.1
27
2.34.1
28
28
29
29
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/21] includes: remove stale [smp|max]_cpus externs
[PULL 10/35] tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
1
From: Alex Bennée <alex.bennee@linaro.org>
1
We deliberately don't include qtests_npcm7xx in qtests_aarch64,
2
because we already get the coverage of those tests via qtests_arm,
3
and we don't want to use extra CI minutes testing them twice.
2
4
3
Commit a5e0b3311 removed these in favour of querying machine
5
In commit 327b680877b79c4b we added it to qtests_aarch64; revert
4
properties. Remove the extern declarations as well.
6
that change.
5
7
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Fixes: 327b680877b79c4b ("tests/qtest: Creating qtest for GMAC Module")
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20190828165307.18321-6-alex.bennee@linaro.org
10
Cc: Like Xu <like.xu@linux.intel.com>
11
Message-Id: <20190711130546.18578-1-alex.bennee@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-id: 20240206163043.315535-1-peter.maydell@linaro.org
13
---
12
---
14
include/sysemu/sysemu.h | 2 --
13
tests/qtest/meson.build | 1 -
15
1 file changed, 2 deletions(-)
14
1 file changed, 1 deletion(-)
16
15
17
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
16
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
18
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
19
--- a/include/sysemu/sysemu.h
18
--- a/tests/qtest/meson.build
20
+++ b/include/sysemu/sysemu.h
19
+++ b/tests/qtest/meson.build
21
@@ -XXX,XX +XXX,XX @@ extern const char *keyboard_layout;
20
@@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \
22
extern int win2k_install_hack;
21
(config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
23
extern int alt_grab;
22
(config_all_accel.has_key('CONFIG_TCG') and \
24
extern int ctrl_grab;
23
config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
25
-extern int smp_cpus;
24
- (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
26
-extern unsigned int max_cpus;
25
['arm-cpu-features',
27
extern int cursor_hide;
26
'numa-test',
28
extern int graphic_rotate;
27
'boot-serial-test',
29
extern int no_quit;
30
--
28
--
31
2.20.1
29
2.34.1
32
30
33
31
diff view generated by jsdifflib
New patch
[PULL 11/35] tests/qtest/bios-tables-test: Allow changes to virt GTDT
1
Allow changes to the virt GTDT -- we are going to add the IRQ
2
entry for a new timer to it.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
6
Message-id: 20240122143537.233498-2-peter.maydell@linaro.org
7
---
8
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
9
1 file changed, 2 insertions(+)
10
11
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tests/qtest/bios-tables-test-allowed-diff.h
14
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
15
@@ -1 +1,3 @@
16
/* List of comma-separated changed AML files to ignore */
17
+"tests/data/acpi/virt/FACP",
18
+"tests/data/acpi/virt/GTDT",
19
--
20
2.34.1
diff view generated by jsdifflib
New patch
[PULL 12/35] hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
1
1
Armv8.1+ CPUs have the Virtual Host Extension (VHE) which adds a
2
non-secure EL2 virtual timer. We implemented the timer itself in the
3
CPU model, but never wired up its IRQ line to the GIC.
4
5
Wire up the IRQ line (this is always safe whether the CPU has the
6
interrupt or not, since it always creates the outbound IRQ line).
7
Report it to the guest via dtb and ACPI if the CPU has the feature.
8
9
The DTB binding is documented in the kernel's
10
Documentation/devicetree/bindings/timer/arm\,arch_timer.yaml
11
and the ACPI table entries are documented in the ACPI specification
12
version 6.3 or later.
13
14
Because the IRQ line ACPI binding is new in 6.3, we need to bump the
15
FADT table rev to show that we might be using 6.3 features.
16
17
Note that exposing this IRQ in the DTB will trigger a bug in EDK2
18
versions prior to edk2-stable202311, for users who use the virt board
19
with 'virtualization=on' to enable EL2 emulation and are booting an
20
EDK2 guest BIOS, if that EDK2 has assertions enabled. The effect is
21
that EDK2 will assert on bootup:
22
23
ASSERT [ArmTimerDxe] /home/kraxel/projects/qemu/roms/edk2/ArmVirtPkg/Library/ArmVirtTimerFdtClientLib/ArmVirtTimerFdtClientLib.c(72): PropSize == 36 || PropSize == 48
24
25
If you see that assertion you should do one of:
26
* update your EDK2 binaries to edk2-stable202311 or newer
27
* use the 'virt-8.2' versioned machine type
28
* not use 'virtualization=on'
29
30
(The versions shipped with QEMU itself have the fix.)
31
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
34
Message-id: 20240122143537.233498-3-peter.maydell@linaro.org
35
---
36
include/hw/arm/virt.h | 2 ++
37
hw/arm/virt-acpi-build.c | 20 ++++++++++----
38
hw/arm/virt.c | 60 ++++++++++++++++++++++++++++++++++------
39
3 files changed, 67 insertions(+), 15 deletions(-)
40
41
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
42
index XXXXXXX..XXXXXXX 100644
43
--- a/include/hw/arm/virt.h
44
+++ b/include/hw/arm/virt.h
45
@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
46
/* Machines < 6.2 have no support for describing cpu topology to guest */
47
bool no_cpu_topology;
48
bool no_tcg_lpa2;
49
+ bool no_ns_el2_virt_timer_irq;
50
};
51
52
struct VirtMachineState {
53
@@ -XXX,XX +XXX,XX @@ struct VirtMachineState {
54
PCIBus *bus;
55
char *oem_id;
56
char *oem_table_id;
57
+ bool ns_el2_virt_timer_irq;
58
};
59
60
#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
61
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/hw/arm/virt-acpi-build.c
64
+++ b/hw/arm/virt-acpi-build.c
65
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
66
}
67
68
/*
69
- * ACPI spec, Revision 5.1
70
- * 5.2.24 Generic Timer Description Table (GTDT)
71
+ * ACPI spec, Revision 6.5
72
+ * 5.2.25 Generic Timer Description Table (GTDT)
73
*/
74
static void
75
build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
76
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
77
uint32_t irqflags = vmc->claim_edge_triggered_timers ?
78
1 : /* Interrupt is Edge triggered */
79
0; /* Interrupt is Level triggered */
80
- AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id,
81
+ AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id,
82
.oem_table_id = vms->oem_table_id };
83
84
acpi_table_begin(&table, table_data);
85
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
86
build_append_int_noprefix(table_data, 0, 4);
87
/* Platform Timer Offset */
88
build_append_int_noprefix(table_data, 0, 4);
89
-
90
+ if (vms->ns_el2_virt_timer_irq) {
91
+ /* Virtual EL2 Timer GSIV */
92
+ build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4);
93
+ /* Virtual EL2 Timer Flags */
94
+ build_append_int_noprefix(table_data, irqflags, 4);
95
+ } else {
96
+ build_append_int_noprefix(table_data, 0, 4);
97
+ build_append_int_noprefix(table_data, 0, 4);
98
+ }
99
acpi_table_end(linker, &table);
100
}
101
102
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
103
static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker,
104
VirtMachineState *vms, unsigned dsdt_tbl_offset)
105
{
106
- /* ACPI v6.0 */
107
+ /* ACPI v6.3 */
108
AcpiFadtData fadt = {
109
.rev = 6,
110
- .minor_ver = 0,
111
+ .minor_ver = 3,
112
.flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
113
.xdsdt_tbl_offset = &dsdt_tbl_offset,
114
};
115
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
116
index XXXXXXX..XXXXXXX 100644
117
--- a/hw/arm/virt.c
118
+++ b/hw/arm/virt.c
119
@@ -XXX,XX +XXX,XX @@ static void create_randomness(MachineState *ms, const char *node)
120
qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
121
}
122
123
+/*
124
+ * The CPU object always exposes the NS EL2 virt timer IRQ line,
125
+ * but we don't want to advertise it to the guest in the dtb or ACPI
126
+ * table unless it's really going to do something.
127
+ */
128
+static bool ns_el2_virt_timer_present(void)
129
+{
130
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
131
+ CPUARMState *env = &cpu->env;
132
+
133
+ return arm_feature(env, ARM_FEATURE_AARCH64) &&
134
+ arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu);
135
+}
136
+
137
static void create_fdt(VirtMachineState *vms)
138
{
139
MachineState *ms = MACHINE(vms);
140
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
141
"arm,armv7-timer");
142
}
143
qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
144
- qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
145
- GIC_FDT_IRQ_TYPE_PPI,
146
- INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
147
- GIC_FDT_IRQ_TYPE_PPI,
148
- INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
149
- GIC_FDT_IRQ_TYPE_PPI,
150
- INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
151
- GIC_FDT_IRQ_TYPE_PPI,
152
- INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
153
+ if (vms->ns_el2_virt_timer_irq) {
154
+ qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
155
+ GIC_FDT_IRQ_TYPE_PPI,
156
+ INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
157
+ GIC_FDT_IRQ_TYPE_PPI,
158
+ INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
159
+ GIC_FDT_IRQ_TYPE_PPI,
160
+ INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
161
+ GIC_FDT_IRQ_TYPE_PPI,
162
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags,
163
+ GIC_FDT_IRQ_TYPE_PPI,
164
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags);
165
+ } else {
166
+ qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
167
+ GIC_FDT_IRQ_TYPE_PPI,
168
+ INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
169
+ GIC_FDT_IRQ_TYPE_PPI,
170
+ INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
171
+ GIC_FDT_IRQ_TYPE_PPI,
172
+ INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
173
+ GIC_FDT_IRQ_TYPE_PPI,
174
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
175
+ }
176
}
177
178
static void fdt_add_cpu_nodes(const VirtMachineState *vms)
179
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
180
[GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
181
[GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
182
[GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
183
+ [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
184
};
185
186
for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
187
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
188
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
189
object_unref(cpuobj);
190
}
191
+
192
+ /* Now we've created the CPUs we can see if they have the hypvirt timer */
193
+ vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() &&
194
+ !vmc->no_ns_el2_virt_timer_irq;
195
+
196
fdt_add_timer_nodes(vms);
197
fdt_add_cpu_nodes(vms);
198
199
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(9, 0)
200
201
static void virt_machine_8_2_options(MachineClass *mc)
202
{
203
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
204
+
205
virt_machine_9_0_options(mc);
206
compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
207
+ /*
208
+ * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and
209
+ * earlier machines. (Exposing it tickles a bug in older EDK2
210
+ * guest BIOS binaries.)
211
+ */
212
+ vmc->no_ns_el2_virt_timer_irq = true;
213
}
214
DEFINE_VIRT_MACHINE(8, 2)
215
216
--
217
2.34.1
diff view generated by jsdifflib
New patch
[PULL 13/35] tests/qtest/bios-tables-tests: Update virt golden reference
1
1
Update the virt golden reference files to say that the FACP is ACPI
2
v6.3, and the GTDT table is a revision 3 table with space for the
3
virtual EL2 timer.
4
5
Diffs from iasl:
6
7
@@ -XXX,XX +XXX,XX @@
8
/*
9
* Intel ACPI Component Architecture
10
* AML/ASL+ Disassembler version 20200925 (64-bit version)
11
* Copyright (c) 2000 - 2020 Intel Corporation
12
*
13
- * Disassembly of tests/data/acpi/virt/FACP, Mon Jan 22 13:48:40 2024
14
+ * Disassembly of /tmp/aml-W8RZH2, Mon Jan 22 13:48:40 2024
15
*
16
* ACPI Data Table [FACP]
17
*
18
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
19
*/
20
21
[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
22
[004h 0004 4] Table Length : 00000114
23
[008h 0008 1] Revision : 06
24
-[009h 0009 1] Checksum : 15
25
+[009h 0009 1] Checksum : 12
26
[00Ah 0010 6] Oem ID : "BOCHS "
27
[010h 0016 8] Oem Table ID : "BXPC "
28
[018h 0024 4] Oem Revision : 00000001
29
[01Ch 0028 4] Asl Compiler ID : "BXPC"
30
[020h 0032 4] Asl Compiler Revision : 00000001
31
32
[024h 0036 4] FACS Address : 00000000
33
[028h 0040 4] DSDT Address : 00000000
34
[02Ch 0044 1] Model : 00
35
[02Dh 0045 1] PM Profile : 00 [Unspecified]
36
[02Eh 0046 2] SCI Interrupt : 0000
37
[030h 0048 4] SMI Command Port : 00000000
38
[034h 0052 1] ACPI Enable Value : 00
39
[035h 0053 1] ACPI Disable Value : 00
40
[036h 0054 1] S4BIOS Command : 00
41
[037h 0055 1] P-State Control : 00
42
@@ -XXX,XX +XXX,XX @@
43
Use APIC Physical Destination Mode (V4) : 0
44
Hardware Reduced (V5) : 1
45
Low Power S0 Idle (V5) : 0
46
47
[074h 0116 12] Reset Register : [Generic Address Structure]
48
[074h 0116 1] Space ID : 00 [SystemMemory]
49
[075h 0117 1] Bit Width : 00
50
[076h 0118 1] Bit Offset : 00
51
[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
52
[078h 0120 8] Address : 0000000000000000
53
54
[080h 0128 1] Value to cause reset : 00
55
[081h 0129 2] ARM Flags (decoded below) : 0003
56
PSCI Compliant : 1
57
Must use HVC for PSCI : 1
58
59
-[083h 0131 1] FADT Minor Revision : 00
60
+[083h 0131 1] FADT Minor Revision : 03
61
[084h 0132 8] FACS Address : 0000000000000000
62
[08Ch 0140 8] DSDT Address : 0000000000000000
63
[094h 0148 12] PM1A Event Block : [Generic Address Structure]
64
[094h 0148 1] Space ID : 00 [SystemMemory]
65
[095h 0149 1] Bit Width : 00
66
[096h 0150 1] Bit Offset : 00
67
[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
68
[098h 0152 8] Address : 0000000000000000
69
70
[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
71
[0A0h 0160 1] Space ID : 00 [SystemMemory]
72
[0A1h 0161 1] Bit Width : 00
73
[0A2h 0162 1] Bit Offset : 00
74
[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
75
[0A4h 0164 8] Address : 0000000000000000
76
77
@@ -XXX,XX +XXX,XX @@
78
[0F5h 0245 1] Bit Width : 00
79
[0F6h 0246 1] Bit Offset : 00
80
[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy]
81
[0F8h 0248 8] Address : 0000000000000000
82
83
[100h 0256 12] Sleep Status Register : [Generic Address Structure]
84
[100h 0256 1] Space ID : 00 [SystemMemory]
85
[101h 0257 1] Bit Width : 00
86
[102h 0258 1] Bit Offset : 00
87
[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy]
88
[104h 0260 8] Address : 0000000000000000
89
90
[10Ch 0268 8] Hypervisor ID : 00000000554D4551
91
92
Raw Table Data: Length 276 (0x114)
93
94
- 0000: 46 41 43 50 14 01 00 00 06 15 42 4F 43 48 53 20 // FACP......BOCHS
95
+ 0000: 46 41 43 50 14 01 00 00 06 12 42 4F 43 48 53 20 // FACP......BOCHS
96
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
97
0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
98
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
99
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
100
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
101
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
102
0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
103
- 0080: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
104
+ 0080: 00 03 00 03 00 00 00 00 00 00 00 00 00 00 00 00 // ................
105
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
106
00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
107
00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
108
00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
109
00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
110
00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
111
00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
112
0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // ............QEMU
113
0110: 00 00 00 00 // ....
114
115
@@ -XXX,XX +XXX,XX @@
116
/*
117
* Intel ACPI Component Architecture
118
* AML/ASL+ Disassembler version 20200925 (64-bit version)
119
* Copyright (c) 2000 - 2020 Intel Corporation
120
*
121
- * Disassembly of tests/data/acpi/virt/GTDT, Mon Jan 22 13:48:40 2024
122
+ * Disassembly of /tmp/aml-XDSZH2, Mon Jan 22 13:48:40 2024
123
*
124
* ACPI Data Table [GTDT]
125
*
126
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
127
*/
128
129
[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table]
130
-[004h 0004 4] Table Length : 00000060
131
-[008h 0008 1] Revision : 02
132
-[009h 0009 1] Checksum : 9C
133
+[004h 0004 4] Table Length : 00000068
134
+[008h 0008 1] Revision : 03
135
+[009h 0009 1] Checksum : 93
136
[00Ah 0010 6] Oem ID : "BOCHS "
137
[010h 0016 8] Oem Table ID : "BXPC "
138
[018h 0024 4] Oem Revision : 00000001
139
[01Ch 0028 4] Asl Compiler ID : "BXPC"
140
[020h 0032 4] Asl Compiler Revision : 00000001
141
142
[024h 0036 8] Counter Block Address : FFFFFFFFFFFFFFFF
143
[02Ch 0044 4] Reserved : 00000000
144
145
[030h 0048 4] Secure EL1 Interrupt : 0000001D
146
[034h 0052 4] EL1 Flags (decoded below) : 00000000
147
Trigger Mode : 0
148
Polarity : 0
149
Always On : 0
150
151
[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E
152
@@ -XXX,XX +XXX,XX @@
153
154
[040h 0064 4] Virtual Timer Interrupt : 0000001B
155
[044h 0068 4] VT Flags (decoded below) : 00000000
156
Trigger Mode : 0
157
Polarity : 0
158
Always On : 0
159
160
[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A
161
[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000
162
Trigger Mode : 0
163
Polarity : 0
164
Always On : 0
165
[050h 0080 8] Counter Read Block Address : FFFFFFFFFFFFFFFF
166
167
[058h 0088 4] Platform Timer Count : 00000000
168
[05Ch 0092 4] Platform Timer Offset : 00000000
169
+[060h 0096 4] Virtual EL2 Timer GSIV : 00000000
170
+[064h 0100 4] Virtual EL2 Timer Flags : 00000000
171
172
-Raw Table Data: Length 96 (0x60)
173
+Raw Table Data: Length 104 (0x68)
174
175
- 0000: 47 54 44 54 60 00 00 00 02 9C 42 4F 43 48 53 20 // GTDT`.....BOCHS
176
+ 0000: 47 54 44 54 68 00 00 00 03 93 42 4F 43 48 53 20 // GTDTh.....BOCHS
177
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
178
0020: 01 00 00 00 FF FF FF FF FF FF FF FF 00 00 00 00 // ................
179
0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................
180
0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................
181
0050: FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 // ................
182
+ 0060: 00 00 00 00 00 00 00 00 // ........
183
184
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
185
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
186
Message-id: 20240122143537.233498-4-peter.maydell@linaro.org
187
---
188
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
189
tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes
190
tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes
191
3 files changed, 2 deletions(-)
192
193
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
194
index XXXXXXX..XXXXXXX 100644
195
--- a/tests/qtest/bios-tables-test-allowed-diff.h
196
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
197
@@ -1,3 +1 @@
198
/* List of comma-separated changed AML files to ignore */
199
-"tests/data/acpi/virt/FACP",
200
-"tests/data/acpi/virt/GTDT",
201
diff --git a/tests/data/acpi/virt/FACP b/tests/data/acpi/virt/FACP
202
index XXXXXXX..XXXXXXX 100644
203
GIT binary patch
204
delta 25
205
gcmbQjG=+)F&CxkPgpq-PO=u!l<;2F$$vli407<0<)c^nh
206
207
delta 28
208
kcmbQjG=+)F&CxkPgpq-PO>`nx<-|!<6Akz$^DuG%0AAS!ssI20
209
210
diff --git a/tests/data/acpi/virt/GTDT b/tests/data/acpi/virt/GTDT
211
index XXXXXXX..XXXXXXX 100644
212
GIT binary patch
213
delta 25
214
bcmYeu;BpUf3CUn!U|^m+kt>V?$N&QXMtB4L
215
216
delta 16
217
Xcmc~u;BpUf2}xjJU|^avkt+-UB60)u
218
219
--
220
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/35] hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
1
The patchset adding the GMAC ethernet to this SoC crossed in the
2
mail with the patchset cleaning up the NIC handling. When we
3
create the GMAC modules we must call qemu_configure_nic_device()
4
so that the user has the opportunity to use the -nic commandline
5
option to create a network backend and connect it to the GMACs.
1
6
7
Add the missing call.
8
9
Fixes: 21e5326a7c ("hw/arm: Add GMAC devices to NPCM7XX SoC")
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
12
Message-id: 20240206171231.396392-2-peter.maydell@linaro.org
13
---
14
hw/arm/npcm7xx.c | 1 +
15
1 file changed, 1 insertion(+)
16
17
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/npcm7xx.c
20
+++ b/hw/arm/npcm7xx.c
21
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
22
for (i = 0; i < ARRAY_SIZE(s->gmac); i++) {
23
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->gmac[i]);
24
25
+ qemu_configure_nic_device(DEVICE(sbd), false, NULL);
26
/*
27
* The device exists regardless of whether it's connected to a QEMU
28
* netdev backend. So always instantiate it even if there is no
29
--
30
2.34.1
diff view generated by jsdifflib
New patch
[PULL 15/35] tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
1
Currently QEMU will warn if there is a NIC on the board that
2
is not connected to a backend. By default the '-nic user' will
3
get used for all NICs, but if you manually connect a specific
4
NIC to a specific backend, then the other NICs on the board
5
have no backend and will be warned about:
1
6
7
qemu-system-arm: warning: nic npcm7xx-emc.1 has no peer
8
qemu-system-arm: warning: nic npcm-gmac.0 has no peer
9
qemu-system-arm: warning: nic npcm-gmac.1 has no peer
10
11
So suppress those warnings by manually connecting every NIC
12
on the board to some backend.
13
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
16
Reviewed-by: Thomas Huth <thuth@redhat.com>
17
Message-id: 20240206171231.396392-3-peter.maydell@linaro.org
18
---
19
tests/qtest/npcm7xx_emc-test.c | 5 ++++-
20
1 file changed, 4 insertions(+), 1 deletion(-)
21
22
diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/tests/qtest/npcm7xx_emc-test.c
25
+++ b/tests/qtest/npcm7xx_emc-test.c
26
@@ -XXX,XX +XXX,XX @@ static int *packet_test_init(int module_num, GString *cmd_line)
27
* KISS and use -nic. The driver accepts 'emc0' and 'emc1' as aliases
28
* in the 'model' field to specify the device to match.
29
*/
30
- g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d ",
31
+ g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d "
32
+ "-nic user,model=npcm7xx-emc "
33
+ "-nic user,model=npcm-gmac "
34
+ "-nic user,model=npcm-gmac",
35
test_sockets[1], module_num);
36
37
g_test_queue_destroy(packet_test_clear, test_sockets);
38
--
39
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/21] target/arm: Free TCG temps in trans_VMOV_64_sp()
[PULL 16/35] target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
1
The function neon_store_reg32() doesn't free the TCG temp that it
1
It doesn't make sense to read the value of MDCR_EL2 on a non-A-profile
2
is passed, so the caller must do that. We got this right in most
2
CPU, and in fact if you try to do it we will assert:
3
places but forgot to free the TCG temps in trans_VMOV_64_sp().
3
4
#6 0x00007ffff4b95e96 in __GI___assert_fail
5
(assertion=0x5555565a8c70 "!arm_feature(env, ARM_FEATURE_M)", file=0x5555565a6e5c "../../target/arm/helper.c", line=12600, function=0x5555565a9560 <__PRETTY_FUNCTION__.0> "arm_security_space_below_el3") at ./assert/assert.c:101
6
#7 0x0000555555ebf412 in arm_security_space_below_el3 (env=0x555557bc8190) at ../../target/arm/helper.c:12600
7
#8 0x0000555555ea6f89 in arm_is_el2_enabled (env=0x555557bc8190) at ../../target/arm/cpu.h:2595
8
#9 0x0000555555ea942f in arm_mdcr_el2_eff (env=0x555557bc8190) at ../../target/arm/internals.h:1512
9
10
We might call pmu_counter_enabled() on an M-profile CPU (for example
11
from the migration pre/post hooks in machine.c); this should always
12
return false because these CPUs don't set ARM_FEATURE_PMU.
13
14
Avoid the assertion by not calling arm_mdcr_el2_eff() before we
15
have done the early return for "PMU not present".
16
17
This fixes an assertion failure if you try to do a loadvm or
18
savevm for an M-profile board.
4
19
5
Cc: qemu-stable@nongnu.org
20
Cc: qemu-stable@nongnu.org
21
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2155
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
25
Message-id: 20240208153346.970021-1-peter.maydell@linaro.org
9
Message-id: 20190827121931.26836-1-peter.maydell@linaro.org
10
---
26
---
11
target/arm/translate-vfp.inc.c | 2 ++
27
target/arm/helper.c | 12 ++++++++++--
12
1 file changed, 2 insertions(+)
28
1 file changed, 10 insertions(+), 2 deletions(-)
13
29
14
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-vfp.inc.c
32
--- a/target/arm/helper.c
17
+++ b/target/arm/translate-vfp.inc.c
33
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a)
34
@@ -XXX,XX +XXX,XX @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
19
/* gpreg to fpreg */
35
bool enabled, prohibited = false, filtered;
20
tmp = load_reg(s, a->rt);
36
bool secure = arm_is_secure(env);
21
neon_store_reg32(tmp, a->vm);
37
int el = arm_current_el(env);
22
+ tcg_temp_free_i32(tmp);
38
- uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
23
tmp = load_reg(s, a->rt2);
39
- uint8_t hpmn = mdcr_el2 & MDCR_HPMN;
24
neon_store_reg32(tmp, a->vm + 1);
40
+ uint64_t mdcr_el2;
25
+ tcg_temp_free_i32(tmp);
41
+ uint8_t hpmn;
42
43
+ /*
44
+ * We might be called for M-profile cores where MDCR_EL2 doesn't
45
+ * exist and arm_mdcr_el2_eff() will assert, so this early-exit check
46
+ * must be before we read that value.
47
+ */
48
if (!arm_feature(env, ARM_FEATURE_PMU)) {
49
return false;
26
}
50
}
27
51
28
return true;
52
+ mdcr_el2 = arm_mdcr_el2_eff(env);
53
+ hpmn = mdcr_el2 & MDCR_HPMN;
54
+
55
if (!arm_feature(env, ARM_FEATURE_EL2) ||
56
(counter < hpmn || counter == 31)) {
57
e = env->cp15.c9_pmcr & PMCRE;
29
--
58
--
30
2.20.1
59
2.34.1
31
60
32
61
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/21] memory: Remove unused memory_region_iommu_replay_all()
[PULL 17/35] tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Nabih Estefan <nabihestefan@google.com>
2
2
3
memory_region_iommu_replay_all is not used. Remove it.
3
Fix the nocm_gmac-test.c file to run on a nuvoton 7xx machine instead
4
of 8xx. Also fix comments referencing this and values expecting 8xx.
4
5
5
Signed-off-by: Eric Auger <eric.auger@redhat.com>
6
Change-Id: Iabd0fba14910c3f1e883c4a9521350f3db9ffab8
6
Reported-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-Off-By: Nabih Estefan <nabihestefan@google.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
8
Reviewed-by: Peter Xu <peterx@redhat.com>
9
Message-id: 20240208194759.2858582-2-nabihestefan@google.com
9
Message-id: 20190822172350.12008-2-eric.auger@redhat.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: commit message tweaks]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
include/exec/memory.h | 10 ----------
14
tests/qtest/npcm_gmac-test.c | 84 +-----------------------------------
13
memory.c | 9 ---------
15
tests/qtest/meson.build | 3 +-
14
2 files changed, 19 deletions(-)
16
2 files changed, 4 insertions(+), 83 deletions(-)
15
17
16
diff --git a/include/exec/memory.h b/include/exec/memory.h
18
diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c
17
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
18
--- a/include/exec/memory.h
20
--- a/tests/qtest/npcm_gmac-test.c
19
+++ b/include/exec/memory.h
21
+++ b/tests/qtest/npcm_gmac-test.c
20
@@ -XXX,XX +XXX,XX @@ void memory_region_register_iommu_notifier(MemoryRegion *mr,
22
@@ -XXX,XX +XXX,XX @@ typedef struct TestData {
21
*/
23
const GMACModule *module;
22
void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n);
24
} TestData;
23
25
24
-/**
26
-/* Values extracted from hw/arm/npcm8xx.c */
25
- * memory_region_iommu_replay_all: replay existing IOMMU translations
27
+/* Values extracted from hw/arm/npcm7xx.c */
26
- * to all the notifiers registered.
28
static const GMACModule gmac_module_list[] = {
27
- *
29
{
28
- * Note: this is not related to record-and-replay functionality.
30
.irq = 14,
29
- *
31
@@ -XXX,XX +XXX,XX @@ static const GMACModule gmac_module_list[] = {
30
- * @iommu_mr: the memory region to observe
32
.irq = 15,
31
- */
33
.base_addr = 0xf0804000
32
-void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr);
34
},
33
-
35
- {
34
/**
36
- .irq = 16,
35
* memory_region_unregister_iommu_notifier: unregister a notifier for
37
- .base_addr = 0xf0806000
36
* changes to IOMMU translation entries.
38
- },
37
diff --git a/memory.c b/memory.c
39
- {
38
index XXXXXXX..XXXXXXX 100644
40
- .irq = 17,
39
--- a/memory.c
41
- .base_addr = 0xf0808000
40
+++ b/memory.c
42
- }
41
@@ -XXX,XX +XXX,XX @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
43
};
42
}
44
45
/* Returns the index of the GMAC module. */
46
@@ -XXX,XX +XXX,XX @@ static uint32_t gmac_read(QTestState *qts, const GMACModule *mod,
47
return qtest_readl(qts, mod->base_addr + regno);
43
}
48
}
44
49
45
-void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
50
-static uint16_t pcs_read(QTestState *qts, const GMACModule *mod,
51
- NPCMRegister regno)
46
-{
52
-{
47
- IOMMUNotifier *notifier;
53
- uint32_t write_value = (regno & 0x3ffe00) >> 9;
48
-
54
- qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value);
49
- IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
55
- uint32_t read_offset = regno & 0x1ff;
50
- memory_region_iommu_replay(iommu_mr, notifier);
56
- return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset);
51
- }
52
-}
57
-}
53
-
58
-
54
void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
59
/* Check that GMAC registers are reset to default value */
55
IOMMUNotifier *n)
60
static void test_init(gconstpointer test_data)
56
{
61
{
62
const TestData *td = test_data;
63
const GMACModule *mod = td->module;
64
- QTestState *qts = qtest_init("-machine npcm845-evb");
65
+ QTestState *qts = qtest_init("-machine npcm750-evb");
66
67
#define CHECK_REG32(regno, value) \
68
do { \
69
g_assert_cmphex(gmac_read(qts, mod, (regno)), ==, (value)); \
70
} while (0)
71
72
-#define CHECK_REG_PCS(regno, value) \
73
- do { \
74
- g_assert_cmphex(pcs_read(qts, mod, (regno)), ==, (value)); \
75
- } while (0)
76
-
77
CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100);
78
CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0);
79
CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0);
80
@@ -XXX,XX +XXX,XX @@ static void test_init(gconstpointer test_data)
81
CHECK_REG32(NPCM_GMAC_PTP_TAR, 0);
82
CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0);
83
84
- /* TODO Add registers PCS */
85
- if (mod->base_addr == 0xf0802000) {
86
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e);
87
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0);
88
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000);
89
-
90
- CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140);
91
- CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109);
92
- CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e);
93
- CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0);
94
- CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020);
95
- CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0);
96
- CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0);
97
- CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000);
98
-
99
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003);
100
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038);
101
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0);
102
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038);
103
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0);
104
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058);
105
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0);
106
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048);
107
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0);
108
-
109
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400);
110
- CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0);
111
- CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a);
112
- CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0);
113
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0);
114
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c);
115
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0);
116
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0);
117
- CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0);
118
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0);
119
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010);
120
- CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0);
121
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0);
122
- CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0);
123
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a);
124
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f);
125
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001);
126
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0);
127
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0);
128
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100);
129
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100);
130
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e);
131
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100);
132
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032);
133
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001);
134
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0);
135
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019);
136
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0);
137
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0);
138
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0);
139
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0);
140
- }
141
-
142
qtest_quit(qts);
143
}
144
145
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
146
index XXXXXXX..XXXXXXX 100644
147
--- a/tests/qtest/meson.build
148
+++ b/tests/qtest/meson.build
149
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
150
'npcm7xx_sdhci-test',
151
'npcm7xx_smbus-test',
152
'npcm7xx_timer-test',
153
- 'npcm7xx_watchdog_timer-test'] + \
154
+ 'npcm7xx_watchdog_timer-test',
155
+ 'npcm_gmac-test'] + \
156
(slirp.found() ? ['npcm7xx_emc-test'] : [])
157
qtests_aspeed = \
158
['aspeed_hace-test',
57
--
159
--
58
2.20.1
160
2.34.1
59
60
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/21] hw/arm/smmuv3: Remove spurious error messages on IOVA invalidations
[PULL 18/35] hw/arm/smmuv3: add support for stage 1 access fault
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Luc Michel <luc.michel@amd.com>
2
2
3
An IOVA/ASID invalidation is notified to all IOMMU Memory Regions
3
An access fault is raised when the Access Flag is not set in the
4
through smmuv3_inv_notifiers_iova/smmuv3_notify_iova.
4
looked-up PTE and the AFFD field is not set in the corresponding context
5
descriptor. This was already implemented for stage 2. Implement it for
6
stage 1 as well.
5
7
6
When the notification occurs it is possible that some of the
8
Signed-off-by: Luc Michel <luc.michel@amd.com>
7
PCIe devices associated to the notified regions do not have a
9
Reviewed-by: Mostafa Saleh <smostafa@google.com>
8
valid stream table entry. In that case we output a LOG_GUEST_ERROR
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
message, for example:
11
Tested-by: Mostafa Saleh <smostafa@google.com>
10
12
Message-id: 20240213082211.3330400-1-luc.michel@amd.com
11
invalid sid=<SID> (L1STD span=0)
13
[PMM: tweaked comment text]
12
"smmuv3_notify_iova error decoding the configuration for iommu mr=<MR>
13
14
This is unfortunate as the user gets the impression that there
15
are some translation decoding errors whereas there are not.
16
17
This patch adds a new field in SMMUEventInfo that tells whether
18
the detection of an invalid STE must lead to an error report.
19
invalid_ste_allowed is set before doing the invalidations and
20
kept unset on actual translation.
21
22
The other configuration decoding error messages are kept since if the
23
STE is valid then the rest of the config must be correct.
24
25
Signed-off-by: Eric Auger <eric.auger@redhat.com>
26
Message-id: 20190822172350.12008-6-eric.auger@redhat.com
27
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
---
15
---
30
hw/arm/smmuv3-internal.h | 1 +
16
hw/arm/smmuv3-internal.h | 1 +
31
hw/arm/smmuv3.c | 19 +++++++++++--------
17
include/hw/arm/smmu-common.h | 1 +
32
2 files changed, 12 insertions(+), 8 deletions(-)
18
hw/arm/smmu-common.c | 11 +++++++++++
19
hw/arm/smmuv3.c | 1 +
20
4 files changed, 14 insertions(+)
33
21
34
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
22
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
35
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/arm/smmuv3-internal.h
24
--- a/hw/arm/smmuv3-internal.h
37
+++ b/hw/arm/smmuv3-internal.h
25
+++ b/hw/arm/smmuv3-internal.h
38
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUEventInfo {
26
@@ -XXX,XX +XXX,XX @@ static inline int pa_range(STE *ste)
39
uint32_t sid;
27
#define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1)
40
bool recorded;
28
#define CD_ENDI(x) extract32((x)->word[0], 15, 1)
41
bool record_trans_faults;
29
#define CD_IPS(x) extract32((x)->word[1], 0 , 3)
42
+ bool inval_ste_allowed;
30
+#define CD_AFFD(x) extract32((x)->word[1], 3 , 1)
43
union {
31
#define CD_TBI(x) extract32((x)->word[1], 6 , 2)
44
struct {
32
#define CD_HD(x) extract32((x)->word[1], 10 , 1)
45
uint32_t ssid;
33
#define CD_HA(x) extract32((x)->word[1], 11 , 1)
34
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
35
index XXXXXXX..XXXXXXX 100644
36
--- a/include/hw/arm/smmu-common.h
37
+++ b/include/hw/arm/smmu-common.h
38
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg {
39
bool disabled; /* smmu is disabled */
40
bool bypassed; /* translation is bypassed */
41
bool aborted; /* translation is aborted */
42
+ bool affd; /* AF fault disable */
43
uint32_t iotlb_hits; /* counts IOTLB hits */
44
uint32_t iotlb_misses; /* counts IOTLB misses*/
45
/* Used by stage-1 only. */
46
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/smmu-common.c
49
+++ b/hw/arm/smmu-common.c
50
@@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg,
51
pte_addr, pte, iova, gpa,
52
block_size >> 20);
53
}
54
+
55
+ /*
56
+ * QEMU does not currently implement HTTU, so if AFFD and PTE.AF
57
+ * are 0 we take an Access flag fault. (5.4. Context Descriptor)
58
+ * An Access flag fault takes priority over a Permission fault.
59
+ */
60
+ if (!PTE_AF(pte) && !cfg->affd) {
61
+ info->type = SMMU_PTW_ERR_ACCESS;
62
+ goto error;
63
+ }
64
+
65
ap = PTE_AP(pte);
66
if (is_permission_fault(ap, perm)) {
67
info->type = SMMU_PTW_ERR_PERMISSION;
46
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
68
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
47
index XXXXXXX..XXXXXXX 100644
69
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/smmuv3.c
70
--- a/hw/arm/smmuv3.c
49
+++ b/hw/arm/smmuv3.c
71
+++ b/hw/arm/smmuv3.c
50
@@ -XXX,XX +XXX,XX @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,
72
@@ -XXX,XX +XXX,XX @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
51
uint32_t config;
73
cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas);
52
74
cfg->tbi = CD_TBI(cd);
53
if (!STE_VALID(ste)) {
75
cfg->asid = CD_ASID(cd);
54
- qemu_log_mask(LOG_GUEST_ERROR, "invalid STE\n");
76
+ cfg->affd = CD_AFFD(cd);
55
+ if (!event->inval_ste_allowed) {
77
56
+ qemu_log_mask(LOG_GUEST_ERROR, "invalid STE\n");
78
trace_smmuv3_decode_cd(cfg->oas);
57
+ }
58
goto bad_ste;
59
}
60
61
@@ -XXX,XX +XXX,XX @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste,
62
63
if (!span) {
64
/* l2ptr is not valid */
65
- qemu_log_mask(LOG_GUEST_ERROR,
66
- "invalid sid=%d (L1STD span=0)\n", sid);
67
+ if (!event->inval_ste_allowed) {
68
+ qemu_log_mask(LOG_GUEST_ERROR,
69
+ "invalid sid=%d (L1STD span=0)\n", sid);
70
+ }
71
event->type = SMMU_EVT_C_BAD_STREAMID;
72
return -EINVAL;
73
}
74
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
75
SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
76
SMMUv3State *s = sdev->smmu;
77
uint32_t sid = smmu_get_sid(sdev);
78
- SMMUEventInfo event = {.type = SMMU_EVT_NONE, .sid = sid};
79
+ SMMUEventInfo event = {.type = SMMU_EVT_NONE,
80
+ .sid = sid,
81
+ .inval_ste_allowed = false};
82
SMMUPTWEventInfo ptw_info = {};
83
SMMUTranslationStatus status;
84
SMMUState *bs = ARM_SMMU(s);
85
@@ -XXX,XX +XXX,XX @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
86
dma_addr_t iova)
87
{
88
SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
89
- SMMUEventInfo event = {};
90
+ SMMUEventInfo event = {.inval_ste_allowed = true};
91
SMMUTransTableInfo *tt;
92
SMMUTransCfg *cfg;
93
IOMMUTLBEntry entry;
94
95
cfg = smmuv3_get_config(sdev, &event);
96
if (!cfg) {
97
- qemu_log_mask(LOG_GUEST_ERROR,
98
- "%s error decoding the configuration for iommu mr=%s\n",
99
- __func__, mr->parent_obj.name);
100
return;
101
}
102
79
103
--
80
--
104
2.20.1
81
2.34.1
105
106
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/21] Revert "target/arm: Use unallocated_encoding for aarch32"
[PULL 19/35] hw/arm/stellaris: Convert ADC controller to Resettable interface
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
This reverts commit 3cb36637157088892e9e33ddb1034bffd1251d3b.
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Despite the fact that the text for the call to gen_exception_insn
5
Message-id: 20240213155214.13619-2-philmd@linaro.org
6
is identical for aarch64 and aarch32, the implementation inside
7
gen_exception_insn is totally different.
8
9
This fixes exceptions raised from aarch64.
10
11
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
14
Message-id: 20190826151536.6771-2-richard.henderson@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
7
---
17
target/arm/translate-a64.h | 2 ++
8
hw/arm/stellaris.c | 6 ++++--
18
target/arm/translate.h | 2 --
9
1 file changed, 4 insertions(+), 2 deletions(-)
19
target/arm/translate-a64.c | 7 +++++++
20
target/arm/translate-vfp.inc.c | 3 ++-
21
target/arm/translate.c | 22 ++++++++++------------
22
5 files changed, 21 insertions(+), 15 deletions(-)
23
10
24
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
11
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
25
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/translate-a64.h
13
--- a/hw/arm/stellaris.c
27
+++ b/target/arm/translate-a64.h
14
+++ b/hw/arm/stellaris.c
28
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_trigger(void *opaque, int irq, int level)
29
#ifndef TARGET_ARM_TRANSLATE_A64_H
30
#define TARGET_ARM_TRANSLATE_A64_H
31
32
+void unallocated_encoding(DisasContext *s);
33
+
34
#define unsupported_encoding(s, insn) \
35
do { \
36
qemu_log_mask(LOG_UNIMP, \
37
diff --git a/target/arm/translate.h b/target/arm/translate.h
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/translate.h
40
+++ b/target/arm/translate.h
41
@@ -XXX,XX +XXX,XX @@ typedef struct DisasCompare {
42
bool value_global;
43
} DisasCompare;
44
45
-void unallocated_encoding(DisasContext *s);
46
-
47
/* Share the TCG temporaries common between 32 and 64 bit modes. */
48
extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
49
extern TCGv_i64 cpu_exclusive_addr;
50
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/target/arm/translate-a64.c
53
+++ b/target/arm/translate-a64.c
54
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
55
}
16
}
56
}
17
}
57
18
58
+void unallocated_encoding(DisasContext *s)
19
-static void stellaris_adc_reset(StellarisADCState *s)
59
+{
20
+static void stellaris_adc_reset_hold(Object *obj)
60
+ /* Unallocated and reserved encodings are uncategorized */
61
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
62
+ default_exception_el(s));
63
+}
64
+
65
static void init_tmp_a64_array(DisasContext *s)
66
{
21
{
67
#ifdef CONFIG_DEBUG_TCG
22
+ StellarisADCState *s = STELLARIS_ADC(obj);
68
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
23
int n;
69
index XXXXXXX..XXXXXXX 100644
24
70
--- a/target/arm/translate-vfp.inc.c
25
for (n = 0; n < 4; n++) {
71
+++ b/target/arm/translate-vfp.inc.c
26
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj)
72
@@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
27
memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
73
28
"adc", 0x1000);
74
if (!s->vfp_enabled && !ignore_vfp_enabled) {
29
sysbus_init_mmio(sbd, &s->iomem);
75
assert(!arm_dc_feature(s, ARM_FEATURE_M));
30
- stellaris_adc_reset(s);
76
- unallocated_encoding(s);
31
qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
77
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
78
+ default_exception_el(s));
79
return false;
80
}
81
82
diff --git a/target/arm/translate.c b/target/arm/translate.c
83
index XXXXXXX..XXXXXXX 100644
84
--- a/target/arm/translate.c
85
+++ b/target/arm/translate.c
86
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
87
s->base.is_jmp = DISAS_NORETURN;
88
}
32
}
89
33
90
-void unallocated_encoding(DisasContext *s)
34
@@ -XXX,XX +XXX,XX @@ static const TypeInfo stellaris_i2c_info = {
91
-{
35
static void stellaris_adc_class_init(ObjectClass *klass, void *data)
92
- /* Unallocated and reserved encodings are uncategorized */
93
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
94
- default_exception_el(s));
95
-}
96
-
97
/* Force a TB lookup after an instruction that changes the CPU state. */
98
static inline void gen_lookup_tb(DisasContext *s)
99
{
36
{
100
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
37
DeviceClass *dc = DEVICE_CLASS(klass);
101
return;
38
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
102
}
39
103
40
+ rc->phases.hold = stellaris_adc_reset_hold;
104
- unallocated_encoding(s);
41
dc->vmsd = &vmstate_stellaris_adc;
105
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
106
+ default_exception_el(s));
107
}
42
}
108
43
109
static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
110
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
111
}
112
113
if (undef) {
114
- unallocated_encoding(s);
115
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
116
+ default_exception_el(s));
117
return;
118
}
119
120
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
121
break;
122
default:
123
illegal_op:
124
- unallocated_encoding(s);
125
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
126
+ default_exception_el(s));
127
break;
128
}
129
}
130
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
131
}
132
return;
133
illegal_op:
134
- unallocated_encoding(s);
135
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
136
+ default_exception_el(s));
137
}
138
139
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
140
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
141
return;
142
illegal_op:
143
undef:
144
- unallocated_encoding(s);
145
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
146
+ default_exception_el(s));
147
}
148
149
static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
150
--
44
--
151
2.20.1
45
2.34.1
152
46
153
47
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/21] hw/arm: Use sysbus_init_child_obj for correct reference counting
[PULL 20/35] hw/arm/stellaris: Convert I2C controller to Resettable interface
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Both object_initialize() and qdev_set_parent_bus() increase the
3
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
4
reference counter of the new object, so one of the references has
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
to be dropped afterwards to get the reference counting right.
5
Message-id: 20240213155214.13619-3-philmd@linaro.org
6
In machine model code this refcount leak is not particularly
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
problematic because (unlike devices) machines will never be
8
created on demand via QMP, and they are never destroyed.
9
But in any case let's use the new sysbus_init_child_obj() instead
10
to get the reference counting here right.
11
12
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20190823143249.8096-4-philmd@redhat.com
15
[PMM: rewrote commit message]
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
8
---
18
hw/arm/exynos4_boards.c | 4 ++--
9
hw/arm/stellaris.c | 26 ++++++++++++++++++++++----
19
1 file changed, 2 insertions(+), 2 deletions(-)
10
1 file changed, 22 insertions(+), 4 deletions(-)
20
11
21
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
12
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
22
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/exynos4_boards.c
14
--- a/hw/arm/stellaris.c
24
+++ b/hw/arm/exynos4_boards.c
15
+++ b/hw/arm/stellaris.c
25
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
16
@@ -XXX,XX +XXX,XX @@ static void stellaris_sys_instance_init(Object *obj)
26
exynos4_boards_init_ram(s, get_system_memory(),
17
s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
27
exynos4_board_ram_size[board_type]);
18
}
28
19
29
- object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
20
-/* I2C controller. */
30
- qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default());
21
+/*
31
+ sysbus_init_child_obj(OBJECT(machine), "soc",
22
+ * I2C controller.
32
+ &s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
23
+ * ??? For now we only implement the master interface.
33
object_property_set_bool(OBJECT(&s->soc), true, "realized",
24
+ */
34
&error_fatal);
25
26
#define TYPE_STELLARIS_I2C "stellaris-i2c"
27
OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
28
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_write(void *opaque, hwaddr offset,
29
stellaris_i2c_update(s);
30
}
31
32
-static void stellaris_i2c_reset(stellaris_i2c_state *s)
33
+static void stellaris_i2c_reset_enter(Object *obj, ResetType type)
34
{
35
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
36
+
37
if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
38
i2c_end_transfer(s->bus);
39
+}
40
+
41
+static void stellaris_i2c_reset_hold(Object *obj)
42
+{
43
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
44
45
s->msa = 0;
46
s->mcs = 0;
47
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_reset(stellaris_i2c_state *s)
48
s->mimr = 0;
49
s->mris = 0;
50
s->mcr = 0;
51
+}
52
+
53
+static void stellaris_i2c_reset_exit(Object *obj)
54
+{
55
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
56
+
57
stellaris_i2c_update(s);
58
}
59
60
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_init(Object *obj)
61
memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
62
"i2c", 0x1000);
63
sysbus_init_mmio(sbd, &s->iomem);
64
- /* ??? For now we only implement the master interface. */
65
- stellaris_i2c_reset(s);
66
}
67
68
/* Analogue to Digital Converter. This is only partially implemented,
69
@@ -XXX,XX +XXX,XX @@ type_init(stellaris_machine_init)
70
static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
71
{
72
DeviceClass *dc = DEVICE_CLASS(klass);
73
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
74
75
+ rc->phases.enter = stellaris_i2c_reset_enter;
76
+ rc->phases.hold = stellaris_i2c_reset_hold;
77
+ rc->phases.exit = stellaris_i2c_reset_exit;
78
dc->vmsd = &vmstate_stellaris_i2c;
79
}
35
80
36
--
81
--
37
2.20.1
82
2.34.1
38
83
39
84
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/21] hw/net/xilinx_axi: Use object_initialize_child for correct ref. counting
[PULL 21/35] hw/arm/stellaris: Add missing QOM 'machine' parent
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
As explained in commit aff39be0ed97:
3
QDev objects created with qdev_new() need to manually add
4
their parent relationship with object_property_add_child().
4
5
5
Both functions, object_initialize() and object_property_add_child()
6
This commit plug the devices which aren't part of the SoC;
6
increase the reference counter of the new object, so one of the
7
they will be plugged into a SoC container in the next one.
7
references has to be dropped afterwards to get the reference
8
counting right. Otherwise the child object will not be properly
9
cleaned up when the parent gets destroyed.
10
Thus let's use now object_initialize_child() instead to get the
11
reference counting here right.
12
8
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Thomas Huth <thuth@redhat.com>
11
Message-id: 20240213155214.13619-4-philmd@linaro.org
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20190823143249.8096-7-philmd@redhat.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
13
---
20
hw/net/xilinx_axienet.c | 17 ++++++++---------
14
hw/arm/stellaris.c | 4 ++++
21
1 file changed, 8 insertions(+), 9 deletions(-)
15
1 file changed, 4 insertions(+)
22
16
23
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
17
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
24
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/net/xilinx_axienet.c
19
--- a/hw/arm/stellaris.c
26
+++ b/hw/net/xilinx_axienet.c
20
+++ b/hw/arm/stellaris.c
27
@@ -XXX,XX +XXX,XX @@ static void xilinx_enet_init(Object *obj)
21
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
28
XilinxAXIEnet *s = XILINX_AXI_ENET(obj);
22
&error_fatal);
29
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
23
30
24
ssddev = qdev_new("ssd0323");
31
- object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev),
25
+ object_property_add_child(OBJECT(ms), "oled", OBJECT(ssddev));
32
- TYPE_XILINX_AXI_ENET_DATA_STREAM);
26
qdev_prop_set_uint8(ssddev, "cs", 1);
33
- object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev),
27
qdev_realize_and_unref(ssddev, bus, &error_fatal);
34
- TYPE_XILINX_AXI_ENET_CONTROL_STREAM);
28
35
- object_property_add_child(OBJECT(s), "axistream-connected-target",
29
gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ);
36
- (Object *)&s->rx_data_dev, &error_abort);
30
+ object_property_add_child(OBJECT(ms), "splitter",
37
- object_property_add_child(OBJECT(s), "axistream-control-connected-target",
31
+ OBJECT(gpio_d_splitter));
38
- (Object *)&s->rx_control_dev, &error_abort);
32
qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2);
39
-
33
qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal);
40
+ object_initialize_child(OBJECT(s), "axistream-connected-target",
34
qdev_connect_gpio_out(
41
+ &s->rx_data_dev, sizeof(s->rx_data_dev),
35
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
42
+ TYPE_XILINX_AXI_ENET_DATA_STREAM, &error_abort,
36
DeviceState *gpad;
43
+ NULL);
37
44
+ object_initialize_child(OBJECT(s), "axistream-control-connected-target",
38
gpad = qdev_new(TYPE_STELLARIS_GAMEPAD);
45
+ &s->rx_control_dev, sizeof(s->rx_control_dev),
39
+ object_property_add_child(OBJECT(ms), "gamepad", OBJECT(gpad));
46
+ TYPE_XILINX_AXI_ENET_CONTROL_STREAM, &error_abort,
40
for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) {
47
+ NULL);
41
qlist_append_int(gpad_keycode_list, gpad_keycode[i]);
48
sysbus_init_irq(sbd, &s->irq);
42
}
49
50
memory_region_init_io(&s->iomem, OBJECT(s), &enet_ops, s, "enet", 0x40000);
51
--
43
--
52
2.20.1
44
2.34.1
53
45
54
46
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/21] hw/dma/xilinx_axi: Use object_initialize_child for correct ref. counting
[PULL 22/35] hw/arm/stellaris: Add missing QOM 'SoC' parent
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
As explained in commit aff39be0ed97:
3
QDev objects created with qdev_new() need to manually add
4
their parent relationship with object_property_add_child().
4
5
5
Both functions, object_initialize() and object_property_add_child()
6
Since we don't model the SoC, just use a QOM container.
6
increase the reference counter of the new object, so one of the
7
references has to be dropped afterwards to get the reference
8
counting right. Otherwise the child object will not be properly
9
cleaned up when the parent gets destroyed.
10
Thus let's use now object_initialize_child() instead to get the
11
reference counting here right.
12
7
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Thomas Huth <thuth@redhat.com>
10
Message-id: 20240213155214.13619-5-philmd@linaro.org
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20190823143249.8096-6-philmd@redhat.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
12
---
20
hw/dma/xilinx_axidma.c | 16 ++++++++--------
13
hw/arm/stellaris.c | 11 ++++++++++-
21
1 file changed, 8 insertions(+), 8 deletions(-)
14
1 file changed, 10 insertions(+), 1 deletion(-)
22
15
23
diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
16
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
24
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/dma/xilinx_axidma.c
18
--- a/hw/arm/stellaris.c
26
+++ b/hw/dma/xilinx_axidma.c
19
+++ b/hw/arm/stellaris.c
27
@@ -XXX,XX +XXX,XX @@ static void xilinx_axidma_init(Object *obj)
20
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
28
XilinxAXIDMA *s = XILINX_AXI_DMA(obj);
21
* 400fe000 system control
29
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
22
*/
30
23
31
- object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev),
24
+ Object *soc_container;
32
- TYPE_XILINX_AXI_DMA_DATA_STREAM);
25
DeviceState *gpio_dev[7], *nvic;
33
- object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev),
26
qemu_irq gpio_in[7][8];
34
- TYPE_XILINX_AXI_DMA_CONTROL_STREAM);
27
qemu_irq gpio_out[7][8];
35
- object_property_add_child(OBJECT(s), "axistream-connected-target",
28
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
36
- (Object *)&s->rx_data_dev, &error_abort);
29
flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
37
- object_property_add_child(OBJECT(s), "axistream-control-connected-target",
30
sram_size = ((board->dc0 >> 18) + 1) * 1024;
38
- (Object *)&s->rx_control_dev, &error_abort);
31
39
+ object_initialize_child(OBJECT(s), "axistream-connected-target",
32
+ soc_container = object_new("container");
40
+ &s->rx_data_dev, sizeof(s->rx_data_dev),
33
+ object_property_add_child(OBJECT(ms), "soc", soc_container);
41
+ TYPE_XILINX_AXI_DMA_DATA_STREAM, &error_abort,
34
+
42
+ NULL);
35
/* Flash programming is done via the SCU, so pretend it is ROM. */
43
+ object_initialize_child(OBJECT(s), "axistream-control-connected-target",
36
memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
44
+ &s->rx_control_dev, sizeof(s->rx_control_dev),
37
&error_fatal);
45
+ TYPE_XILINX_AXI_DMA_CONTROL_STREAM, &error_abort,
38
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
46
+ NULL);
39
* need its sysclk output.
47
40
*/
48
sysbus_init_irq(sbd, &s->streams[0].irq);
41
ssys_dev = qdev_new(TYPE_STELLARIS_SYS);
49
sysbus_init_irq(sbd, &s->streams[1].irq);
42
+ object_property_add_child(soc_container, "sys", OBJECT(ssys_dev));
43
44
/*
45
* Most devices come preprogrammed with a MAC address in the user data.
46
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
47
sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
48
49
nvic = qdev_new(TYPE_ARMV7M);
50
+ object_property_add_child(soc_container, "v7m", OBJECT(nvic));
51
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
52
qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS);
53
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
54
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
55
56
dev = qdev_new(TYPE_STELLARIS_GPTM);
57
sbd = SYS_BUS_DEVICE(dev);
58
+ object_property_add_child(soc_container, "gptm[*]", OBJECT(dev));
59
qdev_connect_clock_in(dev, "clk",
60
qdev_get_clock_out(ssys_dev, "SYSCLK"));
61
sysbus_realize_and_unref(sbd, &error_fatal);
62
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
63
64
if (board->dc1 & (1 << 3)) { /* watchdog present */
65
dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
66
-
67
+ object_property_add_child(soc_container, "wdg", OBJECT(dev));
68
qdev_connect_clock_in(dev, "WDOGCLK",
69
qdev_get_clock_out(ssys_dev, "SYSCLK"));
70
71
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
72
SysBusDevice *sbd;
73
74
dev = qdev_new("pl011_luminary");
75
+ object_property_add_child(soc_container, "uart[*]", OBJECT(dev));
76
sbd = SYS_BUS_DEVICE(dev);
77
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
78
sysbus_realize_and_unref(sbd, &error_fatal);
79
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
80
DeviceState *enet;
81
82
enet = qdev_new("stellaris_enet");
83
+ object_property_add_child(soc_container, "enet", OBJECT(enet));
84
if (nd) {
85
qdev_set_nic_properties(enet, nd);
86
} else {
50
--
87
--
51
2.20.1
88
2.34.1
52
89
53
90
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/21] target/arm: Take exceptions on ATS instructions when needed
[PULL 23/35] target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
1
The translation table walk for an ATS instruction can result in
1
We support two different encodings for the AArch32 IMPDEF
2
various faults. In general these are just reported back via the
2
CBAR register -- older cores like the Cortex A9, A7, A15
3
PAR_EL1 fault status fields, but in some cases the architecture
3
have this at 4, c15, c0, 0; newer cores like the
4
requires that the fault is turned into an exception:
4
Cortex A35, A53, A57 and A72 have it at 1 c15 c0 0.
5
* synchronous stage 2 faults of any kind during AT S1E0* and
6
AT S1E1* instructions executed from NS EL1 fault to EL2 or EL3
7
* synchronous external aborts are taken as Data Abort exceptions
8
5
9
(This is documented in the v8A Arm ARM DDI0487A.e D5.2.11 and
6
When we implemented this we picked which encoding to
10
G5.13.4.)
7
use based on whether the CPU set ARM_FEATURE_AARCH64.
8
However this isn't right for three cases:
9
* the qemu-system-arm 'max' CPU, which is supposed to be
10
a variant on a Cortex-A57; it ought to use the same
11
encoding the A57 does and which the AArch64 'max'
12
exposes to AArch32 guest code
13
* the Cortex-R52, which is AArch32-only but has the CBAR
14
at the newer encoding (and where we incorrectly are
15
not yet setting ARM_FEATURE_CBAR_RO anyway)
16
* any possible future support for other v8 AArch32
17
only CPUs, or for supporting "boot the CPU into
18
AArch32 mode" on our existing cores like the A57 etc
19
20
Make the decision of the encoding be based on whether
21
the CPU implements the ARM_FEATURE_V8 flag instead.
22
23
This changes the behaviour only for the qemu-system-arm
24
'-cpu max'. We don't expect anybody to be relying on the
25
old behaviour because:
26
* it's not what the real hardware Cortex-A57 does
27
(and that's what our ID register claims we are)
28
* we don't implement the memory-mapped GICv3 support
29
which is the only thing that exists at the peripheral
30
base address pointed to by the register
11
31
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
33
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
34
Message-id: 20240206132931.38376-2-peter.maydell@linaro.org
15
Message-id: 20190816125802.25877-3-peter.maydell@linaro.org
16
---
35
---
17
target/arm/helper.c | 107 +++++++++++++++++++++++++++++++++++++-------
36
target/arm/helper.c | 2 +-
18
1 file changed, 92 insertions(+), 15 deletions(-)
37
1 file changed, 1 insertion(+), 1 deletion(-)
19
38
20
diff --git a/target/arm/helper.c b/target/arm/helper.c
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
21
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper.c
41
--- a/target/arm/helper.c
23
+++ b/target/arm/helper.c
42
+++ b/target/arm/helper.c
24
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
43
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
25
ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs,
44
* AArch64 cores we might need to add a specific feature flag
26
&prot, &page_size, &fi, &cacheattrs);
45
* to indicate cores with "flavour 2" CBAR.
27
46
*/
28
+ if (ret) {
47
- if (arm_feature(env, ARM_FEATURE_AARCH64)) {
29
+ /*
48
+ if (arm_feature(env, ARM_FEATURE_V8)) {
30
+ * Some kinds of translation fault must cause exceptions rather
49
/* 32 bit view is [31:18] 0...0 [43:32]. */
31
+ * than being reported in the PAR.
50
uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
32
+ */
51
| extract64(cpu->reset_cbar, 32, 12);
33
+ int current_el = arm_current_el(env);
34
+ int target_el;
35
+ uint32_t syn, fsr, fsc;
36
+ bool take_exc = false;
37
+
38
+ if (fi.s1ptw && current_el == 1 && !arm_is_secure(env)
39
+ && (mmu_idx == ARMMMUIdx_S1NSE1 || mmu_idx == ARMMMUIdx_S1NSE0)) {
40
+ /*
41
+ * Synchronous stage 2 fault on an access made as part of the
42
+ * translation table walk for AT S1E0* or AT S1E1* insn
43
+ * executed from NS EL1. If this is a synchronous external abort
44
+ * and SCR_EL3.EA == 1, then we take a synchronous external abort
45
+ * to EL3. Otherwise the fault is taken as an exception to EL2,
46
+ * and HPFAR_EL2 holds the faulting IPA.
47
+ */
48
+ if (fi.type == ARMFault_SyncExternalOnWalk &&
49
+ (env->cp15.scr_el3 & SCR_EA)) {
50
+ target_el = 3;
51
+ } else {
52
+ env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4;
53
+ target_el = 2;
54
+ }
55
+ take_exc = true;
56
+ } else if (fi.type == ARMFault_SyncExternalOnWalk) {
57
+ /*
58
+ * Synchronous external aborts during a translation table walk
59
+ * are taken as Data Abort exceptions.
60
+ */
61
+ if (fi.stage2) {
62
+ if (current_el == 3) {
63
+ target_el = 3;
64
+ } else {
65
+ target_el = 2;
66
+ }
67
+ } else {
68
+ target_el = exception_target_el(env);
69
+ }
70
+ take_exc = true;
71
+ }
72
+
73
+ if (take_exc) {
74
+ /* Construct FSR and FSC using same logic as arm_deliver_fault() */
75
+ if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
76
+ arm_s1_regime_using_lpae_format(env, mmu_idx)) {
77
+ fsr = arm_fi_to_lfsc(&fi);
78
+ fsc = extract32(fsr, 0, 6);
79
+ } else {
80
+ fsr = arm_fi_to_sfsc(&fi);
81
+ fsc = 0x3f;
82
+ }
83
+ /*
84
+ * Report exception with ESR indicating a fault due to a
85
+ * translation table walk for a cache maintenance instruction.
86
+ */
87
+ syn = syn_data_abort_no_iss(current_el == target_el,
88
+ fi.ea, 1, fi.s1ptw, 1, fsc);
89
+ env->exception.vaddress = value;
90
+ env->exception.fsr = fsr;
91
+ raise_exception(env, EXCP_DATA_ABORT, syn, target_el);
92
+ }
93
+ }
94
+
95
if (is_a64(env)) {
96
format64 = true;
97
} else if (arm_feature(env, ARM_FEATURE_LPAE)) {
98
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vapa_cp_reginfo[] = {
99
/* This underdecoding is safe because the reginfo is NO_RAW. */
100
{ .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
101
.access = PL1_W, .accessfn = ats_access,
102
- .writefn = ats_write, .type = ARM_CP_NO_RAW },
103
+ .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
104
#endif
105
REGINFO_SENTINEL
106
};
107
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
108
/* 64 bit address translation operations */
109
{ .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
110
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
111
- .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
112
+ .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
113
+ .writefn = ats_write64 },
114
{ .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
115
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
116
- .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
117
+ .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
118
+ .writefn = ats_write64 },
119
{ .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
120
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
121
- .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
122
+ .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
123
+ .writefn = ats_write64 },
124
{ .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
125
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
126
- .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
127
+ .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
128
+ .writefn = ats_write64 },
129
{ .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
130
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
131
- .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
132
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
133
+ .writefn = ats_write64 },
134
{ .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
135
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5,
136
- .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
137
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
138
+ .writefn = ats_write64 },
139
{ .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
140
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6,
141
- .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
142
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
143
+ .writefn = ats_write64 },
144
{ .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
145
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
146
- .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
147
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
148
+ .writefn = ats_write64 },
149
/* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
150
{ .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
151
.opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
152
- .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
153
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
154
+ .writefn = ats_write64 },
155
{ .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
156
.opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
157
- .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
158
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
159
+ .writefn = ats_write64 },
160
{ .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
161
.type = ARM_CP_ALIAS,
162
.opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
163
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
164
{ .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
165
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
166
.access = PL2_W, .accessfn = at_s1e2_access,
167
- .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
168
+ .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
169
{ .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
170
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
171
.access = PL2_W, .accessfn = at_s1e2_access,
172
- .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
173
+ .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
174
/* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
175
* if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
176
* with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
177
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
178
*/
179
{ .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
180
.access = PL2_W,
181
- .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
182
+ .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
183
{ .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
184
.access = PL2_W,
185
- .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
186
+ .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
187
{ .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
188
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
189
/* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
190
--
52
--
191
2.20.1
53
2.34.1
192
193
diff view generated by jsdifflib
New patch
[PULL 24/35] target/arm: The Cortex-R52 has a read-only CBAR
1
The Cortex-R52 implements the Configuration Base Address Register
2
(CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU
3
type, so that our implementation provides the register and the
4
associated qdev property.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20240206132931.38376-3-peter.maydell@linaro.org
9
---
10
target/arm/tcg/cpu32.c | 1 +
11
1 file changed, 1 insertion(+)
12
13
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/tcg/cpu32.c
16
+++ b/target/arm/tcg/cpu32.c
17
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
18
set_feature(&cpu->env, ARM_FEATURE_PMSA);
19
set_feature(&cpu->env, ARM_FEATURE_NEON);
20
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
21
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
22
cpu->midr = 0x411fd133; /* r1p3 */
23
cpu->revidr = 0x00000000;
24
cpu->reset_fpsid = 0x41034023;
25
--
26
2.34.1
diff view generated by jsdifflib
New patch
[PULL 25/35] target/arm: Add Cortex-R52 IMPDEF sysregs
1
Add the Cortex-R52 IMPDEF sysregs, by defining them here and
2
also by enabling the AUXCR feature which defines the ACTLR
3
and HACTLR registers. As is our usual practice, we make these
4
simple reads-as-zero stubs for now.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20240206132931.38376-4-peter.maydell@linaro.org
9
---
10
target/arm/tcg/cpu32.c | 108 +++++++++++++++++++++++++++++++++++++++++
11
1 file changed, 108 insertions(+)
12
13
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/tcg/cpu32.c
16
+++ b/target/arm/tcg/cpu32.c
17
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
18
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
19
}
20
21
+static const ARMCPRegInfo cortex_r52_cp_reginfo[] = {
22
+ { .name = "CPUACTLR", .cp = 15, .opc1 = 0, .crm = 15,
23
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
24
+ { .name = "IMP_ATCMREGIONR",
25
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
26
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
27
+ { .name = "IMP_BTCMREGIONR",
28
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
29
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
30
+ { .name = "IMP_CTCMREGIONR",
31
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2,
32
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
33
+ { .name = "IMP_CSCTLR",
34
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0,
35
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
36
+ { .name = "IMP_BPCTLR",
37
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 1,
38
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
39
+ { .name = "IMP_MEMPROTCLR",
40
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 2,
41
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
42
+ { .name = "IMP_SLAVEPCTLR",
43
+ .cp = 15, .opc1 = 0, .crn = 11, .crm = 0, .opc2 = 0,
44
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
45
+ { .name = "IMP_PERIPHREGIONR",
46
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
47
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
48
+ { .name = "IMP_FLASHIFREGIONR",
49
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1,
50
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
51
+ { .name = "IMP_BUILDOPTR",
52
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
53
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
54
+ { .name = "IMP_PINOPTR",
55
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
56
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
57
+ { .name = "IMP_QOSR",
58
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 1,
59
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
60
+ { .name = "IMP_BUSTIMEOUTR",
61
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 2,
62
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
63
+ { .name = "IMP_INTMONR",
64
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 4,
65
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
66
+ { .name = "IMP_ICERR0",
67
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 0,
68
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
69
+ { .name = "IMP_ICERR1",
70
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 1,
71
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
72
+ { .name = "IMP_DCERR0",
73
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 0,
74
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
75
+ { .name = "IMP_DCERR1",
76
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 1,
77
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
78
+ { .name = "IMP_TCMERR0",
79
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 0,
80
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
81
+ { .name = "IMP_TCMERR1",
82
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 1,
83
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
84
+ { .name = "IMP_TCMSYNDR0",
85
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 2,
86
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
87
+ { .name = "IMP_TCMSYNDR1",
88
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 3,
89
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
90
+ { .name = "IMP_FLASHERR0",
91
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 0,
92
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
93
+ { .name = "IMP_FLASHERR1",
94
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 1,
95
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
96
+ { .name = "IMP_CDBGDR0",
97
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 0,
98
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
99
+ { .name = "IMP_CBDGBR1",
100
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 1,
101
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
102
+ { .name = "IMP_TESTR0",
103
+ .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 0,
104
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
105
+ { .name = "IMP_TESTR1",
106
+ .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 1,
107
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
108
+ { .name = "IMP_CDBGDCI",
109
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 15, .opc2 = 0,
110
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
111
+ { .name = "IMP_CDBGDCT",
112
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 0,
113
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
114
+ { .name = "IMP_CDBGICT",
115
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 1,
116
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
117
+ { .name = "IMP_CDBGDCD",
118
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 0,
119
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
120
+ { .name = "IMP_CDBGICD",
121
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 1,
122
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
123
+};
124
+
125
+
126
static void cortex_r52_initfn(Object *obj)
127
{
128
ARMCPU *cpu = ARM_CPU(obj);
129
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
130
set_feature(&cpu->env, ARM_FEATURE_NEON);
131
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
132
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
133
+ set_feature(&cpu->env, ARM_FEATURE_AUXCR);
134
cpu->midr = 0x411fd133; /* r1p3 */
135
cpu->revidr = 0x00000000;
136
cpu->reset_fpsid = 0x41034023;
137
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
138
139
cpu->pmsav7_dregion = 16;
140
cpu->pmsav8r_hdregion = 16;
141
+
142
+ define_arm_cp_regs(cpu, cortex_r52_cp_reginfo);
143
}
144
145
static void cortex_r5f_initfn(Object *obj)
146
--
147
2.34.1
diff view generated by jsdifflib
New patch
[PULL 26/35] target/arm: Allow access to SPSR_hyp from hyp mode
1
Architecturally, the AArch32 MSR/MRS to/from banked register
2
instructions are UNPREDICTABLE for attempts to access a banked
3
register that the guest could access in a more direct way (e.g.
4
using this insn to access r8_fiq when already in FIQ mode). QEMU has
5
chosen to UNDEF on all of these.
1
6
7
However, for the case of accessing SPSR_hyp from hyp mode, it turns
8
out that real hardware permits this, with the same effect as if the
9
guest had directly written to SPSR. Further, there is some
10
guest code out there that assumes it can do this, because it
11
happens to work on hardware: an example Cortex-R52 startup code
12
fragment uses this, and it got copied into various other places,
13
including Zephyr. Zephyr was fixed to not use this:
14
https://github.com/zephyrproject-rtos/zephyr/issues/47330
15
but other examples are still out there, like the selftest
16
binary for the MPS3-AN536.
17
18
For convenience of being able to run guest code, permit
19
this UNPREDICTABLE access instead of UNDEFing it.
20
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Message-id: 20240206132931.38376-5-peter.maydell@linaro.org
24
---
25
target/arm/tcg/op_helper.c | 43 ++++++++++++++++++++++++++------------
26
target/arm/tcg/translate.c | 19 +++++++++++------
27
2 files changed, 43 insertions(+), 19 deletions(-)
28
29
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/tcg/op_helper.c
32
+++ b/target/arm/tcg/op_helper.c
33
@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
34
*/
35
int curmode = env->uncached_cpsr & CPSR_M;
36
37
- if (regno == 17) {
38
- /* ELR_Hyp: a special case because access from tgtmode is OK */
39
- if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
40
- goto undef;
41
+ if (tgtmode == ARM_CPU_MODE_HYP) {
42
+ /*
43
+ * Handle Hyp target regs first because some are special cases
44
+ * which don't want the usual "not accessible from tgtmode" check.
45
+ */
46
+ switch (regno) {
47
+ case 16 ... 17: /* ELR_Hyp, SPSR_Hyp */
48
+ if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
49
+ goto undef;
50
+ }
51
+ break;
52
+ case 13:
53
+ if (curmode != ARM_CPU_MODE_MON) {
54
+ goto undef;
55
+ }
56
+ break;
57
+ default:
58
+ g_assert_not_reached();
59
}
60
return;
61
}
62
@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
63
}
64
}
65
66
- if (tgtmode == ARM_CPU_MODE_HYP) {
67
- /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */
68
- if (curmode != ARM_CPU_MODE_MON) {
69
- goto undef;
70
- }
71
- }
72
-
73
return;
74
75
undef:
76
@@ -XXX,XX +XXX,XX @@ void HELPER(msr_banked)(CPUARMState *env, uint32_t value, uint32_t tgtmode,
77
78
switch (regno) {
79
case 16: /* SPSRs */
80
- env->banked_spsr[bank_number(tgtmode)] = value;
81
+ if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
82
+ /* Only happens for SPSR_Hyp access in Hyp mode */
83
+ env->spsr = value;
84
+ } else {
85
+ env->banked_spsr[bank_number(tgtmode)] = value;
86
+ }
87
break;
88
case 17: /* ELR_Hyp */
89
env->elr_el[2] = value;
90
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno)
91
92
switch (regno) {
93
case 16: /* SPSRs */
94
- return env->banked_spsr[bank_number(tgtmode)];
95
+ if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
96
+ /* Only happens for SPSR_Hyp access in Hyp mode */
97
+ return env->spsr;
98
+ } else {
99
+ return env->banked_spsr[bank_number(tgtmode)];
100
+ }
101
case 17: /* ELR_Hyp */
102
return env->elr_el[2];
103
case 13:
104
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/target/arm/tcg/translate.c
107
+++ b/target/arm/tcg/translate.c
108
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
109
break;
110
case ARM_CPU_MODE_HYP:
111
/*
112
- * SPSR_hyp and r13_hyp can only be accessed from Monitor mode
113
- * (and so we can forbid accesses from EL2 or below). elr_hyp
114
- * can be accessed also from Hyp mode, so forbid accesses from
115
- * EL0 or EL1.
116
+ * r13_hyp can only be accessed from Monitor mode, and so we
117
+ * can forbid accesses from EL2 or below.
118
+ * elr_hyp can be accessed also from Hyp mode, so forbid
119
+ * accesses from EL0 or EL1.
120
+ * SPSR_hyp is supposed to be in the same category as r13_hyp
121
+ * and UNPREDICTABLE if accessed from anything except Monitor
122
+ * mode. However there is some real-world code that will do
123
+ * it because at least some hardware happens to permit the
124
+ * access. (Notably a standard Cortex-R52 startup code fragment
125
+ * does this.) So we permit SPSR_hyp from Hyp mode also, to allow
126
+ * this (incorrect) guest code to run.
127
*/
128
- if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2 ||
129
- (s->current_el < 3 && *regno != 17)) {
130
+ if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2
131
+ || (s->current_el < 3 && *regno != 16 && *regno != 17)) {
132
goto undef;
133
}
134
break;
135
--
136
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/21] atomic_template: fix indentation in GEN_ATOMIC_HELPER
[PULL 27/35] hw/misc/mps2-scc: Fix condition for CFG3 register
1
From: "Emilio G. Cota" <cota@braap.org>
1
We currently guard the CFG3 register read with
2
(scc_partno(s) == 0x524 && scc_partno(s) == 0x547)
3
which is clearly wrong as it is never true.
2
4
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
This register is present on all board types except AN524
4
Signed-off-by: Emilio G. Cota <cota@braap.org>
6
and AN527; correct the condition.
7
8
Fixes: 6ac80818941829c0 ("hw/misc/mps2-scc: Implement changes for AN547")
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 20240206132931.38376-6-peter.maydell@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20190828165307.18321-8-alex.bennee@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
13
---
11
accel/tcg/atomic_template.h | 2 +-
14
hw/misc/mps2-scc.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
15
1 file changed, 1 insertion(+), 1 deletion(-)
13
16
14
diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
17
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/accel/tcg/atomic_template.h
19
--- a/hw/misc/mps2-scc.c
17
+++ b/accel/tcg/atomic_template.h
20
+++ b/hw/misc/mps2-scc.c
18
@@ -XXX,XX +XXX,XX @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr,
21
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
19
22
r = s->cfg2;
20
#define GEN_ATOMIC_HELPER(X) \
23
break;
21
ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
24
case A_CFG3:
22
- ABI_TYPE val EXTRA_ARGS) \
25
- if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) {
23
+ ABI_TYPE val EXTRA_ARGS) \
26
+ if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
24
{ \
27
/* CFG3 reserved on AN524 */
25
ATOMIC_MMU_DECLS; \
28
goto bad_offset;
26
DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; \
29
}
27
--
30
--
28
2.20.1
31
2.34.1
29
32
30
33
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/21] hw/arm/fsl-imx: Add the cpu as child of the SoC object
[PULL 28/35] hw/misc/mps2-scc: Factor out which-board conditionals
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
The MPS SCC device has a lot of different flavours for the various
2
different MPS FPGA images, which look mostly similar but have
3
differences in how particular registers are handled. Currently we
4
deal with this with a lot of open-coded checks on scc_partno(), but
5
as we add more board types this is getting a bit hard to read.
2
6
3
Child properties form the composition tree. All objects need to be
7
Factor out the conditions into some functions which we can
4
a child of another object. Objects can only be a child of one object.
8
give more descriptive names to.
5
9
6
Respect this with the i.MX SoC, to get a cleaner composition tree.
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20240206132931.38376-7-peter.maydell@linaro.org
14
---
15
hw/misc/mps2-scc.c | 45 +++++++++++++++++++++++++++++++--------------
16
1 file changed, 31 insertions(+), 14 deletions(-)
7
17
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
18
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20190823143249.8096-5-philmd@redhat.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/fsl-imx25.c | 4 +++-
14
hw/arm/fsl-imx31.c | 4 +++-
15
2 files changed, 6 insertions(+), 2 deletions(-)
16
17
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
18
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/fsl-imx25.c
20
--- a/hw/misc/mps2-scc.c
20
+++ b/hw/arm/fsl-imx25.c
21
+++ b/hw/misc/mps2-scc.c
21
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
22
@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
22
FslIMX25State *s = FSL_IMX25(obj);
23
return extract32(s->id, 4, 8);
23
int i;
24
}
24
25
25
- object_initialize(&s->cpu, sizeof(s->cpu), ARM_CPU_TYPE_NAME("arm926"));
26
+/* Is CFG_REG2 present? */
26
+ object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
27
+static bool have_cfg2(MPS2SCC *s)
27
+ ARM_CPU_TYPE_NAME("arm926"),
28
+{
28
+ &error_abort, NULL);
29
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
29
30
+}
30
sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
31
+
31
TYPE_IMX_AVIC);
32
+/* Is CFG_REG3 present? */
32
diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c
33
+static bool have_cfg3(MPS2SCC *s)
33
index XXXXXXX..XXXXXXX 100644
34
+{
34
--- a/hw/arm/fsl-imx31.c
35
+ return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
35
+++ b/hw/arm/fsl-imx31.c
36
+}
36
@@ -XXX,XX +XXX,XX @@ static void fsl_imx31_init(Object *obj)
37
+
37
FslIMX31State *s = FSL_IMX31(obj);
38
+/* Is CFG_REG5 present? */
38
int i;
39
+static bool have_cfg5(MPS2SCC *s)
39
40
+{
40
- object_initialize(&s->cpu, sizeof(s->cpu), ARM_CPU_TYPE_NAME("arm1136"));
41
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
41
+ object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
42
+}
42
+ ARM_CPU_TYPE_NAME("arm1136"),
43
+
43
+ &error_abort, NULL);
44
+/* Is CFG_REG6 present? */
44
45
+static bool have_cfg6(MPS2SCC *s)
45
sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
46
+{
46
TYPE_IMX_AVIC);
47
+ return scc_partno(s) == 0x524;
48
+}
49
+
50
/* Handle a write via the SYS_CFG channel to the specified function/device.
51
* Return false on error (reported to guest via SYS_CFGCTRL ERROR bit).
52
*/
53
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
54
r = s->cfg1;
55
break;
56
case A_CFG2:
57
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
58
- /* CFG2 reserved on other boards */
59
+ if (!have_cfg2(s)) {
60
goto bad_offset;
61
}
62
r = s->cfg2;
63
break;
64
case A_CFG3:
65
- if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
66
- /* CFG3 reserved on AN524 */
67
+ if (!have_cfg3(s)) {
68
goto bad_offset;
69
}
70
/* These are user-settable DIP switches on the board. We don't
71
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
72
r = s->cfg4;
73
break;
74
case A_CFG5:
75
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
76
- /* CFG5 reserved on other boards */
77
+ if (!have_cfg5(s)) {
78
goto bad_offset;
79
}
80
r = s->cfg5;
81
break;
82
case A_CFG6:
83
- if (scc_partno(s) != 0x524) {
84
- /* CFG6 reserved on other boards */
85
+ if (!have_cfg6(s)) {
86
goto bad_offset;
87
}
88
r = s->cfg6;
89
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
90
}
91
break;
92
case A_CFG2:
93
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
94
- /* CFG2 reserved on other boards */
95
+ if (!have_cfg2(s)) {
96
goto bad_offset;
97
}
98
/* AN524: QSPI Select signal */
99
s->cfg2 = value;
100
break;
101
case A_CFG5:
102
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
103
- /* CFG5 reserved on other boards */
104
+ if (!have_cfg5(s)) {
105
goto bad_offset;
106
}
107
/* AN524: ACLK frequency in Hz */
108
s->cfg5 = value;
109
break;
110
case A_CFG6:
111
- if (scc_partno(s) != 0x524) {
112
- /* CFG6 reserved on other boards */
113
+ if (!have_cfg6(s)) {
114
goto bad_offset;
115
}
116
/* AN524: Clock divider for BRAM */
47
--
117
--
48
2.20.1
118
2.34.1
49
119
50
120
diff view generated by jsdifflib
New patch
[PULL 29/35] hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
1
1
The MPS2 SCC device is broadly the same for all FPGA images, but has
2
minor differences in the behaviour of the CFG registers depending on
3
the image. In many cases we don't really care about the functionality
4
controlled by these registers and a reads-as-written or similar
5
behaviour is sufficient for the moment.
6
7
For the AN536 the required behaviour is:
8
9
* A_CFG0 has CPU reset and halt bits
10
- implement as reads-as-written for the moment
11
* A_CFG1 has flash or ATCM address 0 remap handling
12
- QEMU doesn't model this; implement as reads-as-written
13
* A_CFG2 has QSPI select (like AN524)
14
- implemented (no behaviour, as with AN524)
15
* A_CFG3 is MCC_MSB_ADDR "additional MCC addressing bits"
16
- QEMU doesn't care about these, so use the existing
17
RAZ behaviour for convenience
18
* A_CFG4 is board rev (like all other images)
19
- no change needed
20
* A_CFG5 is ACLK frq in hz (like AN524)
21
- implemented as reads-as-written, as for other boards
22
* A_CFG6 is core 0 vector table base address
23
- implemented as reads-as-written for the moment
24
* A_CFG7 is core 1 vector table base address
25
- implemented as reads-as-written for the moment
26
27
Make the changes necessary for this; leave TODO comments where
28
appropriate to indicate where we might want to come back and
29
implement things like CPU reset.
30
31
The other aspects of the device specific to this FPGA image (like the
32
values of the board ID and similar registers) will be set via the
33
device's qdev properties.
34
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
36
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
37
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
38
Message-id: 20240206132931.38376-8-peter.maydell@linaro.org
39
---
40
include/hw/misc/mps2-scc.h | 1 +
41
hw/misc/mps2-scc.c | 101 +++++++++++++++++++++++++++++++++----
42
2 files changed, 92 insertions(+), 10 deletions(-)
43
44
diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h
45
index XXXXXXX..XXXXXXX 100644
46
--- a/include/hw/misc/mps2-scc.h
47
+++ b/include/hw/misc/mps2-scc.h
48
@@ -XXX,XX +XXX,XX @@ struct MPS2SCC {
49
uint32_t cfg4;
50
uint32_t cfg5;
51
uint32_t cfg6;
52
+ uint32_t cfg7;
53
uint32_t cfgdata_rtn;
54
uint32_t cfgdata_out;
55
uint32_t cfgctrl;
56
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/misc/mps2-scc.c
59
+++ b/hw/misc/mps2-scc.c
60
@@ -XXX,XX +XXX,XX @@ REG32(CFG3, 0xc)
61
REG32(CFG4, 0x10)
62
REG32(CFG5, 0x14)
63
REG32(CFG6, 0x18)
64
+REG32(CFG7, 0x1c)
65
REG32(CFGDATA_RTN, 0xa0)
66
REG32(CFGDATA_OUT, 0xa4)
67
REG32(CFGCTRL, 0xa8)
68
@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
69
/* Is CFG_REG2 present? */
70
static bool have_cfg2(MPS2SCC *s)
71
{
72
- return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
73
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
74
+ scc_partno(s) == 0x536;
75
}
76
77
/* Is CFG_REG3 present? */
78
static bool have_cfg3(MPS2SCC *s)
79
{
80
- return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
81
+ return scc_partno(s) != 0x524 && scc_partno(s) != 0x547 &&
82
+ scc_partno(s) != 0x536;
83
}
84
85
/* Is CFG_REG5 present? */
86
static bool have_cfg5(MPS2SCC *s)
87
{
88
- return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
89
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
90
+ scc_partno(s) == 0x536;
91
}
92
93
/* Is CFG_REG6 present? */
94
static bool have_cfg6(MPS2SCC *s)
95
{
96
- return scc_partno(s) == 0x524;
97
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x536;
98
+}
99
+
100
+/* Is CFG_REG7 present? */
101
+static bool have_cfg7(MPS2SCC *s)
102
+{
103
+ return scc_partno(s) == 0x536;
104
+}
105
+
106
+/* Does CFG_REG0 drive the 'remap' GPIO output? */
107
+static bool cfg0_is_remap(MPS2SCC *s)
108
+{
109
+ return scc_partno(s) != 0x536;
110
+}
111
+
112
+/* Is CFG_REG1 driving a set of LEDs? */
113
+static bool cfg1_is_leds(MPS2SCC *s)
114
+{
115
+ return scc_partno(s) != 0x536;
116
}
117
118
/* Handle a write via the SYS_CFG channel to the specified function/device.
119
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
120
if (!have_cfg3(s)) {
121
goto bad_offset;
122
}
123
- /* These are user-settable DIP switches on the board. We don't
124
+ /*
125
+ * These are user-settable DIP switches on the board. We don't
126
* model that, so just return zeroes.
127
+ *
128
+ * TODO: for AN536 this is MCC_MSB_ADDR "additional MCC addressing
129
+ * bits". These change which part of the DDR4 the motherboard
130
+ * configuration controller can see in its memory map (see the
131
+ * appnote section 2.4). QEMU doesn't model the MCC at all, so these
132
+ * bits are not interesting to us; read-as-zero is as good as anything
133
+ * else.
134
*/
135
r = 0;
136
break;
137
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
138
}
139
r = s->cfg6;
140
break;
141
+ case A_CFG7:
142
+ if (!have_cfg7(s)) {
143
+ goto bad_offset;
144
+ }
145
+ r = s->cfg7;
146
+ break;
147
case A_CFGDATA_RTN:
148
r = s->cfgdata_rtn;
149
break;
150
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
151
* we always reflect bit 0 in the 'remap' GPIO output line,
152
* and let the board wire it up or not as it chooses.
153
* TODO on some boards bit 1 is CPU_WAIT.
154
+ *
155
+ * TODO: on the AN536 this register controls reset and halt
156
+ * for both CPUs. For the moment we don't implement this, so the
157
+ * register just reads as written.
158
*/
159
s->cfg0 = value;
160
- qemu_set_irq(s->remap, s->cfg0 & 1);
161
+ if (cfg0_is_remap(s)) {
162
+ qemu_set_irq(s->remap, s->cfg0 & 1);
163
+ }
164
break;
165
case A_CFG1:
166
s->cfg1 = value;
167
- for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
168
- led_set_state(s->led[i], extract32(value, i, 1));
169
+ /*
170
+ * On most boards this register drives LEDs.
171
+ *
172
+ * TODO: for AN536 this controls whether flash and ATCM are
173
+ * enabled or disabled on reset. QEMU doesn't model this, and
174
+ * always wires up RAM in the ATCM area and ROM in the flash area.
175
+ */
176
+ if (cfg1_is_leds(s)) {
177
+ for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
178
+ led_set_state(s->led[i], extract32(value, i, 1));
179
+ }
180
}
181
break;
182
case A_CFG2:
183
if (!have_cfg2(s)) {
184
goto bad_offset;
185
}
186
- /* AN524: QSPI Select signal */
187
+ /* AN524, AN536: QSPI Select signal */
188
s->cfg2 = value;
189
break;
190
case A_CFG5:
191
if (!have_cfg5(s)) {
192
goto bad_offset;
193
}
194
- /* AN524: ACLK frequency in Hz */
195
+ /* AN524, AN536: ACLK frequency in Hz */
196
s->cfg5 = value;
197
break;
198
case A_CFG6:
199
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
200
goto bad_offset;
201
}
202
/* AN524: Clock divider for BRAM */
203
+ /* AN536: Core 0 vector table base address */
204
+ s->cfg6 = value;
205
+ break;
206
+ case A_CFG7:
207
+ if (!have_cfg7(s)) {
208
+ goto bad_offset;
209
+ }
210
+ /* AN536: Core 1 vector table base address */
211
s->cfg6 = value;
212
break;
213
case A_CFGDATA_OUT:
214
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_finalize(Object *obj)
215
g_free(s->oscclk_reset);
216
}
217
218
+static bool cfg7_needed(void *opaque)
219
+{
220
+ MPS2SCC *s = opaque;
221
+
222
+ return have_cfg7(s);
223
+}
224
+
225
+static const VMStateDescription vmstate_cfg7 = {
226
+ .name = "mps2-scc/cfg7",
227
+ .version_id = 1,
228
+ .minimum_version_id = 1,
229
+ .needed = cfg7_needed,
230
+ .fields = (const VMStateField[]) {
231
+ VMSTATE_UINT32(cfg7, MPS2SCC),
232
+ VMSTATE_END_OF_LIST()
233
+ }
234
+};
235
+
236
static const VMStateDescription mps2_scc_vmstate = {
237
.name = "mps2-scc",
238
.version_id = 3,
239
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription mps2_scc_vmstate = {
240
VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk,
241
0, vmstate_info_uint32, uint32_t),
242
VMSTATE_END_OF_LIST()
243
+ },
244
+ .subsections = (const VMStateDescription * const []) {
245
+ &vmstate_cfg7,
246
+ NULL
247
}
248
};
249
250
--
251
2.34.1
252
253
diff view generated by jsdifflib
New patch
[PULL 30/35] hw/arm/mps3r: Initial skeleton for mps3-an536 board
1
1
The AN536 is another FPGA image for the MPS3 development board. Unlike
2
the existing FPGA images we already model, this board uses a Cortex-R
3
family CPU, and it does not use any equivalent to the M-profile
4
"Subsystem for Embedded" SoC-equivalent that we model in hw/arm/armsse.c.
5
It's therefore more convenient for us to model it as a completely
6
separate C file.
7
8
This commit adds the basic skeleton of the board model, and the
9
code to create all the RAM and ROM. We assume that we're probably
10
going to want to add more images in future, so use the same
11
base class/subclass setup that mps2-tz.c uses, even though at
12
the moment there's only a single subclass.
13
14
Following commits will add the CPUs and the peripherals.
15
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
18
Message-id: 20240206132931.38376-9-peter.maydell@linaro.org
19
---
20
MAINTAINERS | 3 +-
21
configs/devices/arm-softmmu/default.mak | 1 +
22
hw/arm/mps3r.c | 239 ++++++++++++++++++++++++
23
hw/arm/Kconfig | 5 +
24
hw/arm/meson.build | 1 +
25
5 files changed, 248 insertions(+), 1 deletion(-)
26
create mode 100644 hw/arm/mps3r.c
27
28
diff --git a/MAINTAINERS b/MAINTAINERS
29
index XXXXXXX..XXXXXXX 100644
30
--- a/MAINTAINERS
31
+++ b/MAINTAINERS
32
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/imx7_*.h
33
F: hw/pci-host/designware.c
34
F: include/hw/pci-host/designware.h
35
36
-MPS2
37
+MPS2 / MPS3
38
M: Peter Maydell <peter.maydell@linaro.org>
39
L: qemu-arm@nongnu.org
40
S: Maintained
41
F: hw/arm/mps2.c
42
F: hw/arm/mps2-tz.c
43
+F: hw/arm/mps3r.c
44
F: hw/misc/mps2-*.c
45
F: include/hw/misc/mps2-*.h
46
F: hw/arm/armsse.c
47
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
48
index XXXXXXX..XXXXXXX 100644
49
--- a/configs/devices/arm-softmmu/default.mak
50
+++ b/configs/devices/arm-softmmu/default.mak
51
@@ -XXX,XX +XXX,XX @@ CONFIG_ARM_VIRT=y
52
# CONFIG_INTEGRATOR=n
53
# CONFIG_FSL_IMX31=n
54
# CONFIG_MUSICPAL=n
55
+# CONFIG_MPS3R=n
56
# CONFIG_MUSCA=n
57
# CONFIG_CHEETAH=n
58
# CONFIG_SX1=n
59
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
60
new file mode 100644
61
index XXXXXXX..XXXXXXX
62
--- /dev/null
63
+++ b/hw/arm/mps3r.c
64
@@ -XXX,XX +XXX,XX @@
65
+/*
66
+ * Arm MPS3 board emulation for Cortex-R-based FPGA images.
67
+ * (For M-profile images see mps2.c and mps2tz.c.)
68
+ *
69
+ * Copyright (c) 2017 Linaro Limited
70
+ * Written by Peter Maydell
71
+ *
72
+ * This program is free software; you can redistribute it and/or modify
73
+ * it under the terms of the GNU General Public License version 2 or
74
+ * (at your option) any later version.
75
+ */
76
+
77
+/*
78
+ * The MPS3 is an FPGA based dev board. This file handles FPGA images
79
+ * which use the Cortex-R CPUs. We model these separately from the
80
+ * M-profile images, because on M-profile the FPGA image is based on
81
+ * a "Subsystem for Embedded" which is similar to an SoC, whereas
82
+ * the R-profile FPGA images don't have that abstraction layer.
83
+ *
84
+ * We model the following FPGA images here:
85
+ * "mps3-an536" -- dual Cortex-R52 as documented in Arm Application Note AN536
86
+ *
87
+ * Application Note AN536:
88
+ * https://developer.arm.com/documentation/dai0536/latest/
89
+ */
90
+
91
+#include "qemu/osdep.h"
92
+#include "qemu/units.h"
93
+#include "qapi/error.h"
94
+#include "exec/address-spaces.h"
95
+#include "cpu.h"
96
+#include "hw/boards.h"
97
+#include "hw/arm/boot.h"
98
+
99
+/* Define the layout of RAM and ROM in a board */
100
+typedef struct RAMInfo {
101
+ const char *name;
102
+ hwaddr base;
103
+ hwaddr size;
104
+ int mrindex; /* index into rams[]; -1 for the system RAM block */
105
+ int flags;
106
+} RAMInfo;
107
+
108
+/*
109
+ * The MPS3 DDR is 3GiB, but on a 32-bit host QEMU doesn't permit
110
+ * emulation of that much guest RAM, so artificially make it smaller.
111
+ */
112
+#if HOST_LONG_BITS == 32
113
+#define MPS3_DDR_SIZE (1 * GiB)
114
+#else
115
+#define MPS3_DDR_SIZE (3 * GiB)
116
+#endif
117
+
118
+/*
119
+ * Flag values:
120
+ * IS_MAIN: this is the main machine RAM
121
+ * IS_ROM: this area is read-only
122
+ */
123
+#define IS_MAIN 1
124
+#define IS_ROM 2
125
+
126
+#define MPS3R_RAM_MAX 9
127
+
128
+typedef enum MPS3RFPGAType {
129
+ FPGA_AN536,
130
+} MPS3RFPGAType;
131
+
132
+struct MPS3RMachineClass {
133
+ MachineClass parent;
134
+ MPS3RFPGAType fpga_type;
135
+ const RAMInfo *raminfo;
136
+};
137
+
138
+struct MPS3RMachineState {
139
+ MachineState parent;
140
+ MemoryRegion ram[MPS3R_RAM_MAX];
141
+};
142
+
143
+#define TYPE_MPS3R_MACHINE "mps3r"
144
+#define TYPE_MPS3R_AN536_MACHINE MACHINE_TYPE_NAME("mps3-an536")
145
+
146
+OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
147
+
148
+static const RAMInfo an536_raminfo[] = {
149
+ {
150
+ .name = "ATCM",
151
+ .base = 0x00000000,
152
+ .size = 0x00008000,
153
+ .mrindex = 0,
154
+ }, {
155
+ /* We model the QSPI flash as simple ROM for now */
156
+ .name = "QSPI",
157
+ .base = 0x08000000,
158
+ .size = 0x00800000,
159
+ .flags = IS_ROM,
160
+ .mrindex = 1,
161
+ }, {
162
+ .name = "BRAM",
163
+ .base = 0x10000000,
164
+ .size = 0x00080000,
165
+ .mrindex = 2,
166
+ }, {
167
+ .name = "DDR",
168
+ .base = 0x20000000,
169
+ .size = MPS3_DDR_SIZE,
170
+ .mrindex = -1,
171
+ }, {
172
+ .name = "ATCM0",
173
+ .base = 0xee000000,
174
+ .size = 0x00008000,
175
+ .mrindex = 3,
176
+ }, {
177
+ .name = "BTCM0",
178
+ .base = 0xee100000,
179
+ .size = 0x00008000,
180
+ .mrindex = 4,
181
+ }, {
182
+ .name = "CTCM0",
183
+ .base = 0xee200000,
184
+ .size = 0x00008000,
185
+ .mrindex = 5,
186
+ }, {
187
+ .name = "ATCM1",
188
+ .base = 0xee400000,
189
+ .size = 0x00008000,
190
+ .mrindex = 6,
191
+ }, {
192
+ .name = "BTCM1",
193
+ .base = 0xee500000,
194
+ .size = 0x00008000,
195
+ .mrindex = 7,
196
+ }, {
197
+ .name = "CTCM1",
198
+ .base = 0xee600000,
199
+ .size = 0x00008000,
200
+ .mrindex = 8,
201
+ }, {
202
+ .name = NULL,
203
+ }
204
+};
205
+
206
+static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
207
+ const RAMInfo *raminfo)
208
+{
209
+ /* Return an initialized MemoryRegion for the RAMInfo. */
210
+ MemoryRegion *ram;
211
+
212
+ if (raminfo->mrindex < 0) {
213
+ /* Means this RAMInfo is for QEMU's "system memory" */
214
+ MachineState *machine = MACHINE(mms);
215
+ assert(!(raminfo->flags & IS_ROM));
216
+ return machine->ram;
217
+ }
218
+
219
+ assert(raminfo->mrindex < MPS3R_RAM_MAX);
220
+ ram = &mms->ram[raminfo->mrindex];
221
+
222
+ memory_region_init_ram(ram, NULL, raminfo->name,
223
+ raminfo->size, &error_fatal);
224
+ if (raminfo->flags & IS_ROM) {
225
+ memory_region_set_readonly(ram, true);
226
+ }
227
+ return ram;
228
+}
229
+
230
+static void mps3r_common_init(MachineState *machine)
231
+{
232
+ MPS3RMachineState *mms = MPS3R_MACHINE(machine);
233
+ MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
234
+ MemoryRegion *sysmem = get_system_memory();
235
+
236
+ for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
237
+ MemoryRegion *mr = mr_for_raminfo(mms, ri);
238
+ memory_region_add_subregion(sysmem, ri->base, mr);
239
+ }
240
+}
241
+
242
+static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
243
+{
244
+ /*
245
+ * Set mc->default_ram_size and default_ram_id from the
246
+ * information in mmc->raminfo.
247
+ */
248
+ MachineClass *mc = MACHINE_CLASS(mmc);
249
+ const RAMInfo *p;
250
+
251
+ for (p = mmc->raminfo; p->name; p++) {
252
+ if (p->mrindex < 0) {
253
+ /* Found the entry for "system memory" */
254
+ mc->default_ram_size = p->size;
255
+ mc->default_ram_id = p->name;
256
+ return;
257
+ }
258
+ }
259
+ g_assert_not_reached();
260
+}
261
+
262
+static void mps3r_class_init(ObjectClass *oc, void *data)
263
+{
264
+ MachineClass *mc = MACHINE_CLASS(oc);
265
+
266
+ mc->init = mps3r_common_init;
267
+}
268
+
269
+static void mps3r_an536_class_init(ObjectClass *oc, void *data)
270
+{
271
+ MachineClass *mc = MACHINE_CLASS(oc);
272
+ MPS3RMachineClass *mmc = MPS3R_MACHINE_CLASS(oc);
273
+ static const char * const valid_cpu_types[] = {
274
+ ARM_CPU_TYPE_NAME("cortex-r52"),
275
+ NULL
276
+ };
277
+
278
+ mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
279
+ mc->default_cpus = 2;
280
+ mc->min_cpus = mc->default_cpus;
281
+ mc->max_cpus = mc->default_cpus;
282
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
283
+ mc->valid_cpu_types = valid_cpu_types;
284
+ mmc->raminfo = an536_raminfo;
285
+ mps3r_set_default_ram_info(mmc);
286
+}
287
+
288
+static const TypeInfo mps3r_machine_types[] = {
289
+ {
290
+ .name = TYPE_MPS3R_MACHINE,
291
+ .parent = TYPE_MACHINE,
292
+ .abstract = true,
293
+ .instance_size = sizeof(MPS3RMachineState),
294
+ .class_size = sizeof(MPS3RMachineClass),
295
+ .class_init = mps3r_class_init,
296
+ }, {
297
+ .name = TYPE_MPS3R_AN536_MACHINE,
298
+ .parent = TYPE_MPS3R_MACHINE,
299
+ .class_init = mps3r_an536_class_init,
300
+ },
301
+};
302
+
303
+DEFINE_TYPES(mps3r_machine_types);
304
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
305
index XXXXXXX..XXXXXXX 100644
306
--- a/hw/arm/Kconfig
307
+++ b/hw/arm/Kconfig
308
@@ -XXX,XX +XXX,XX @@ config MAINSTONE
309
select PFLASH_CFI01
310
select SMC91C111
311
312
+config MPS3R
313
+ bool
314
+ default y
315
+ depends on TCG && ARM
316
+
317
config MUSCA
318
bool
319
default y
320
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
321
index XXXXXXX..XXXXXXX 100644
322
--- a/hw/arm/meson.build
323
+++ b/hw/arm/meson.build
324
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
325
arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
326
arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c'))
327
arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
328
+arm_ss.add(when: 'CONFIG_MPS3R', if_true: files('mps3r.c'))
329
arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
330
arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
331
arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
332
--
333
2.34.1
334
335
diff view generated by jsdifflib
New patch
[PULL 31/35] hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
1
Create the CPUs, the GIC, and the per-CPU RAM block for
2
the mps3-an536 board.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20240206132931.38376-10-peter.maydell@linaro.org
6
---
7
hw/arm/mps3r.c | 180 ++++++++++++++++++++++++++++++++++++++++++++++++-
8
1 file changed, 177 insertions(+), 3 deletions(-)
9
10
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/arm/mps3r.c
13
+++ b/hw/arm/mps3r.c
14
@@ -XXX,XX +XXX,XX @@
15
#include "qemu/osdep.h"
16
#include "qemu/units.h"
17
#include "qapi/error.h"
18
+#include "qapi/qmp/qlist.h"
19
#include "exec/address-spaces.h"
20
#include "cpu.h"
21
#include "hw/boards.h"
22
+#include "hw/qdev-properties.h"
23
#include "hw/arm/boot.h"
24
+#include "hw/arm/bsa.h"
25
+#include "hw/intc/arm_gicv3.h"
26
27
/* Define the layout of RAM and ROM in a board */
28
typedef struct RAMInfo {
29
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
30
#define IS_ROM 2
31
32
#define MPS3R_RAM_MAX 9
33
+#define MPS3R_CPU_MAX 2
34
+
35
+#define PERIPHBASE 0xf0000000
36
+#define NUM_SPIS 96
37
38
typedef enum MPS3RFPGAType {
39
FPGA_AN536,
40
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineClass {
41
MachineClass parent;
42
MPS3RFPGAType fpga_type;
43
const RAMInfo *raminfo;
44
+ hwaddr loader_start;
45
};
46
47
struct MPS3RMachineState {
48
MachineState parent;
49
+ struct arm_boot_info bootinfo;
50
MemoryRegion ram[MPS3R_RAM_MAX];
51
+ Object *cpu[MPS3R_CPU_MAX];
52
+ MemoryRegion cpu_sysmem[MPS3R_CPU_MAX];
53
+ MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
54
+ MemoryRegion cpu_ram[MPS3R_CPU_MAX];
55
+ GICv3State gic;
56
};
57
58
#define TYPE_MPS3R_MACHINE "mps3r"
59
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
60
return ram;
61
}
62
63
+/*
64
+ * There is no defined secondary boot protocol for Linux for the AN536,
65
+ * because real hardware has a restriction that atomic operations between
66
+ * the two CPUs do not function correctly, and so true SMP is not
67
+ * possible. Therefore for cases where the user is directly booting
68
+ * a kernel, we treat the system as essentially uniprocessor, and
69
+ * put the secondary CPU into power-off state (as if the user on the
70
+ * real hardware had configured the secondary to be halted via the
71
+ * SCC config registers).
72
+ *
73
+ * Note that the default secondary boot code would not work here anyway
74
+ * as it assumes a GICv2, and we have a GICv3.
75
+ */
76
+static void mps3r_write_secondary_boot(ARMCPU *cpu,
77
+ const struct arm_boot_info *info)
78
+{
79
+ /*
80
+ * Power the secondary CPU off. This means we don't need to write any
81
+ * boot code into guest memory. Note that the 'cpu' argument to this
82
+ * function is the primary CPU we passed to arm_load_kernel(), not
83
+ * the secondary. Loop around all the other CPUs, as the boot.c
84
+ * code does for the "disable secondaries if PSCI is enabled" case.
85
+ */
86
+ for (CPUState *cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
87
+ if (cs != first_cpu) {
88
+ object_property_set_bool(OBJECT(cs), "start-powered-off", true,
89
+ &error_abort);
90
+ }
91
+ }
92
+}
93
+
94
+static void mps3r_secondary_cpu_reset(ARMCPU *cpu,
95
+ const struct arm_boot_info *info)
96
+{
97
+ /* We don't need to do anything here because the CPU will be off */
98
+}
99
+
100
+static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
101
+{
102
+ MachineState *machine = MACHINE(mms);
103
+ DeviceState *gicdev;
104
+ QList *redist_region_count;
105
+
106
+ object_initialize_child(OBJECT(mms), "gic", &mms->gic, TYPE_ARM_GICV3);
107
+ gicdev = DEVICE(&mms->gic);
108
+ qdev_prop_set_uint32(gicdev, "num-cpu", machine->smp.cpus);
109
+ qdev_prop_set_uint32(gicdev, "num-irq", NUM_SPIS + GIC_INTERNAL);
110
+ redist_region_count = qlist_new();
111
+ qlist_append_int(redist_region_count, machine->smp.cpus);
112
+ qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
113
+ object_property_set_link(OBJECT(&mms->gic), "sysmem",
114
+ OBJECT(sysmem), &error_fatal);
115
+ sysbus_realize(SYS_BUS_DEVICE(&mms->gic), &error_fatal);
116
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 0, PERIPHBASE);
117
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 1, PERIPHBASE + 0x100000);
118
+ /*
119
+ * Wire the outputs from each CPU's generic timer and the GICv3
120
+ * maintenance interrupt signal to the appropriate GIC PPI inputs,
121
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
122
+ */
123
+ for (int i = 0; i < machine->smp.cpus; i++) {
124
+ DeviceState *cpudev = DEVICE(mms->cpu[i]);
125
+ SysBusDevice *gicsbd = SYS_BUS_DEVICE(&mms->gic);
126
+ int intidbase = NUM_SPIS + i * GIC_INTERNAL;
127
+ int irq;
128
+ /*
129
+ * Mapping from the output timer irq lines from the CPU to the
130
+ * GIC PPI inputs used for this board. This isn't a BSA board,
131
+ * but it uses the standard convention for the PPI numbers.
132
+ */
133
+ const int timer_irq[] = {
134
+ [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
135
+ [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
136
+ [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
137
+ };
138
+
139
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
140
+ qdev_connect_gpio_out(cpudev, irq,
141
+ qdev_get_gpio_in(gicdev,
142
+ intidbase + timer_irq[irq]));
143
+ }
144
+
145
+ qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
146
+ qdev_get_gpio_in(gicdev,
147
+ intidbase + ARCH_GIC_MAINT_IRQ));
148
+
149
+ qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
150
+ qdev_get_gpio_in(gicdev,
151
+ intidbase + VIRTUAL_PMU_IRQ));
152
+
153
+ sysbus_connect_irq(gicsbd, i,
154
+ qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
155
+ sysbus_connect_irq(gicsbd, i + machine->smp.cpus,
156
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
157
+ sysbus_connect_irq(gicsbd, i + 2 * machine->smp.cpus,
158
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
159
+ sysbus_connect_irq(gicsbd, i + 3 * machine->smp.cpus,
160
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
161
+ }
162
+}
163
+
164
static void mps3r_common_init(MachineState *machine)
165
{
166
MPS3RMachineState *mms = MPS3R_MACHINE(machine);
167
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
168
MemoryRegion *mr = mr_for_raminfo(mms, ri);
169
memory_region_add_subregion(sysmem, ri->base, mr);
170
}
171
+
172
+ assert(machine->smp.cpus <= MPS3R_CPU_MAX);
173
+ for (int i = 0; i < machine->smp.cpus; i++) {
174
+ g_autofree char *sysmem_name = g_strdup_printf("cpu-%d-memory", i);
175
+ g_autofree char *ramname = g_strdup_printf("cpu-%d-memory", i);
176
+ g_autofree char *alias_name = g_strdup_printf("sysmem-alias-%d", i);
177
+
178
+ /*
179
+ * Each CPU has some private RAM/peripherals, so create the container
180
+ * which will house those, with the whole-machine system memory being
181
+ * used where there's no CPU-specific device. Note that we need the
182
+ * sysmem_alias aliases because we can't put one MR (the original
183
+ * 'sysmem') into more than one other MR.
184
+ */
185
+ memory_region_init(&mms->cpu_sysmem[i], OBJECT(machine),
186
+ sysmem_name, UINT64_MAX);
187
+ memory_region_init_alias(&mms->sysmem_alias[i], OBJECT(machine),
188
+ alias_name, sysmem, 0, UINT64_MAX);
189
+ memory_region_add_subregion_overlap(&mms->cpu_sysmem[i], 0,
190
+ &mms->sysmem_alias[i], -1);
191
+
192
+ mms->cpu[i] = object_new(machine->cpu_type);
193
+ object_property_set_link(mms->cpu[i], "memory",
194
+ OBJECT(&mms->cpu_sysmem[i]), &error_abort);
195
+ object_property_set_int(mms->cpu[i], "reset-cbar",
196
+ PERIPHBASE, &error_abort);
197
+ qdev_realize(DEVICE(mms->cpu[i]), NULL, &error_fatal);
198
+ object_unref(mms->cpu[i]);
199
+
200
+ /* Per-CPU RAM */
201
+ memory_region_init_ram(&mms->cpu_ram[i], NULL, ramname,
202
+ 0x1000, &error_fatal);
203
+ memory_region_add_subregion(&mms->cpu_sysmem[i], 0xe7c01000,
204
+ &mms->cpu_ram[i]);
205
+ }
206
+
207
+ create_gic(mms, sysmem);
208
+
209
+ mms->bootinfo.ram_size = machine->ram_size;
210
+ mms->bootinfo.board_id = -1;
211
+ mms->bootinfo.loader_start = mmc->loader_start;
212
+ mms->bootinfo.write_secondary_boot = mps3r_write_secondary_boot;
213
+ mms->bootinfo.secondary_cpu_reset_hook = mps3r_secondary_cpu_reset;
214
+ arm_load_kernel(ARM_CPU(mms->cpu[0]), machine, &mms->bootinfo);
215
}
216
217
static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
218
@@ -XXX,XX +XXX,XX @@ static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
219
/* Found the entry for "system memory" */
220
mc->default_ram_size = p->size;
221
mc->default_ram_id = p->name;
222
+ mmc->loader_start = p->base;
223
return;
224
}
225
}
226
@@ -XXX,XX +XXX,XX @@ static void mps3r_an536_class_init(ObjectClass *oc, void *data)
227
};
228
229
mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
230
- mc->default_cpus = 2;
231
- mc->min_cpus = mc->default_cpus;
232
- mc->max_cpus = mc->default_cpus;
233
+ /*
234
+ * In the real FPGA image there are always two cores, but the standard
235
+ * initial setting for the SCC SYSCON 0x000 register is 0x21, meaning
236
+ * that the second core is held in reset and halted. Many images built for
237
+ * the board do not expect the second core to run at startup (especially
238
+ * since on the real FPGA image it is not possible to use LDREX/STREX
239
+ * in RAM between the two cores, so a true SMP setup isn't supported).
240
+ *
241
+ * As QEMU's equivalent of this, we support both -smp 1 and -smp 2,
242
+ * with the default being -smp 1. This seems a more intuitive UI for
243
+ * QEMU users than, for instance, having a machine property to allow
244
+ * the user to set the initial value of the SYSCON 0x000 register.
245
+ */
246
+ mc->default_cpus = 1;
247
+ mc->min_cpus = 1;
248
+ mc->max_cpus = 2;
249
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
250
mc->valid_cpu_types = valid_cpu_types;
251
mmc->raminfo = an536_raminfo;
252
--
253
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/21] aspeed/timer: Provide back-pressure information for short periods
[PULL 32/35] hw/arm/mps3r: Add UARTs
1
From: Andrew Jeffery <andrew@aj.id.au>
1
This board has a lot of UARTs: there is one UART per CPU in the
2
per-CPU peripheral part of the address map, whose interrupts are
3
connected as per-CPU interrupt lines. Then there are 4 UARTs in the
4
normal part of the peripheral space, whose interrupts are shared
5
peripheral interrupts.
2
6
3
First up: This is not the way the hardware behaves.
7
Connect and wire them all up; this involves some OR gates where
8
multiple overflow interrupts are wired into one GIC input.
4
9
5
However, it helps resolve real-world problems with short periods being
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
used under Linux. Commit 4451d3f59f2a ("clocksource/drivers/fttmr010:
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Fix set_next_event handler") in Linux fixed the timer driver to
12
Message-id: 20240206132931.38376-11-peter.maydell@linaro.org
8
correctly schedule the next event for the Aspeed controller, and in
13
---
9
combination with 5daa8212c08e ("ARM: dts: aspeed: Describe random number
14
hw/arm/mps3r.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++
10
device") Linux will now set a timer with a period as low as 1us.
15
1 file changed, 94 insertions(+)
11
16
12
Configuring a qemu timer with such a short period results in spending
17
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
13
time handling the interrupt in the model rather than executing guest
14
code, leading to noticeable "sticky" behaviour in the guest.
15
16
The behaviour of Linux is correct with respect to the hardware, so we
17
need to improve our handling under emulation. The approach chosen is to
18
provide back-pressure information by calculating an acceptable minimum
19
number of ticks to be set on the model. Under Linux an additional read
20
is added in the timer configuration path to detect back-pressure, which
21
will never occur on hardware. However if back-pressure is observed, the
22
driver alerts the clock event subsystem, which then performs its own
23
next event dilation via a config option - d1748302f70b ("clockevents:
24
Make minimum delay adjustments configurable")
25
26
A minimum period of 5us was experimentally determined on a Lenovo
27
T480s, which I've increased to 20us for "safety".
28
29
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
30
Reviewed-by: Joel Stanley <joel@jms.id.au>
31
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
32
Tested-by: Joel Stanley <joel@jms.id.au>
33
Signed-off-by: Cédric Le Goater <clg@kaod.org>
34
Message-id: 20190704055150.4899-1-clg@kaod.org
35
[clg: - changed the computation of min_ticks to be done each time the
36
timer value is reloaded. It removes the ordering issue of the
37
timer and scu reset handlers but is slightly slower ]
38
- introduced TIMER_MIN_NS
39
- introduced calculate_min_ticks() ]
40
Signed-off-by: Cédric Le Goater <clg@kaod.org>
41
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
42
---
43
hw/timer/aspeed_timer.c | 17 ++++++++++++++++-
44
1 file changed, 16 insertions(+), 1 deletion(-)
45
46
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
47
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/timer/aspeed_timer.c
19
--- a/hw/arm/mps3r.c
49
+++ b/hw/timer/aspeed_timer.c
20
+++ b/hw/arm/mps3r.c
50
@@ -XXX,XX +XXX,XX @@ enum timer_ctrl_op {
21
@@ -XXX,XX +XXX,XX @@
51
op_pulse_enable
22
#include "qapi/qmp/qlist.h"
23
#include "exec/address-spaces.h"
24
#include "cpu.h"
25
+#include "sysemu/sysemu.h"
26
#include "hw/boards.h"
27
+#include "hw/or-irq.h"
28
#include "hw/qdev-properties.h"
29
#include "hw/arm/boot.h"
30
#include "hw/arm/bsa.h"
31
+#include "hw/char/cmsdk-apb-uart.h"
32
#include "hw/intc/arm_gicv3.h"
33
34
/* Define the layout of RAM and ROM in a board */
35
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
36
37
#define MPS3R_RAM_MAX 9
38
#define MPS3R_CPU_MAX 2
39
+#define MPS3R_UART_MAX 4 /* shared UART count */
40
41
#define PERIPHBASE 0xf0000000
42
#define NUM_SPIS 96
43
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
44
MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
45
MemoryRegion cpu_ram[MPS3R_CPU_MAX];
46
GICv3State gic;
47
+ /* per-CPU UARTs followed by the shared UARTs */
48
+ CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
49
+ OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
50
+ OrIRQState uart_oflow;
52
};
51
};
53
52
53
#define TYPE_MPS3R_MACHINE "mps3r"
54
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
55
56
OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
57
54
+/*
58
+/*
55
+ * Minimum value of the reload register to filter out short period
59
+ * Main clock frequency CLK in Hz (50MHz). In the image there are also
56
+ * timers which have a noticeable impact in emulation. 5us should be
60
+ * ACLK, MCLK, GPUCLK and PERIPHCLK at the same frequency; for our
57
+ * enough, use 20us for "safety".
61
+ * model we just roll them all into one.
58
+ */
62
+ */
59
+#define TIMER_MIN_NS (20 * SCALE_US)
63
+#define CLK_FRQ 50000000
60
+
64
+
61
/**
65
static const RAMInfo an536_raminfo[] = {
62
* Avoid mutual references between AspeedTimerCtrlState and AspeedTimer
66
{
63
* structs, as it's a waste of memory. The ptimer BH callback needs to know
67
.name = "ATCM",
64
@@ -XXX,XX +XXX,XX @@ static inline uint32_t calculate_ticks(struct AspeedTimer *t, uint64_t now_ns)
68
@@ -XXX,XX +XXX,XX @@ static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
65
return t->reload - MIN(t->reload, ticks);
69
}
66
}
70
}
67
71
68
+static uint32_t calculate_min_ticks(AspeedTimer *t, uint32_t value)
72
+/*
73
+ * Create UART uartno, and map it into the MemoryRegion mem at address baseaddr.
74
+ * The qemu_irq arguments are where we connect the various IRQs from the UART.
75
+ */
76
+static void create_uart(MPS3RMachineState *mms, int uartno, MemoryRegion *mem,
77
+ hwaddr baseaddr, qemu_irq txirq, qemu_irq rxirq,
78
+ qemu_irq txoverirq, qemu_irq rxoverirq,
79
+ qemu_irq combirq)
69
+{
80
+{
70
+ uint32_t rate = calculate_rate(t);
81
+ g_autofree char *s = g_strdup_printf("uart%d", uartno);
71
+ uint32_t min_ticks = muldiv64(TIMER_MIN_NS, rate, NANOSECONDS_PER_SECOND);
82
+ SysBusDevice *sbd;
72
+
83
+
73
+ return value < min_ticks ? min_ticks : value;
84
+ assert(uartno < ARRAY_SIZE(mms->uart));
85
+ object_initialize_child(OBJECT(mms), s, &mms->uart[uartno],
86
+ TYPE_CMSDK_APB_UART);
87
+ qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ);
88
+ qdev_prop_set_chr(DEVICE(&mms->uart[uartno]), "chardev", serial_hd(uartno));
89
+ sbd = SYS_BUS_DEVICE(&mms->uart[uartno]);
90
+ sysbus_realize(sbd, &error_fatal);
91
+ memory_region_add_subregion(mem, baseaddr,
92
+ sysbus_mmio_get_region(sbd, 0));
93
+ sysbus_connect_irq(sbd, 0, txirq);
94
+ sysbus_connect_irq(sbd, 1, rxirq);
95
+ sysbus_connect_irq(sbd, 2, txoverirq);
96
+ sysbus_connect_irq(sbd, 3, rxoverirq);
97
+ sysbus_connect_irq(sbd, 4, combirq);
74
+}
98
+}
75
+
99
+
76
static inline uint64_t calculate_time(struct AspeedTimer *t, uint32_t ticks)
100
static void mps3r_common_init(MachineState *machine)
77
{
101
{
78
uint64_t delta_ns;
102
MPS3RMachineState *mms = MPS3R_MACHINE(machine);
79
@@ -XXX,XX +XXX,XX @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
103
MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
80
switch (reg) {
104
MemoryRegion *sysmem = get_system_memory();
81
case TIMER_REG_RELOAD:
105
+ DeviceState *gicdev;
82
old_reload = t->reload;
106
83
- t->reload = value;
107
for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
84
+ t->reload = calculate_min_ticks(t, value);
108
MemoryRegion *mr = mr_for_raminfo(mms, ri);
85
109
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
86
/* If the reload value was not previously set, or zero, and
110
}
87
* the current value is valid, try to start the timer if it is
111
112
create_gic(mms, sysmem);
113
+ gicdev = DEVICE(&mms->gic);
114
+
115
+ /*
116
+ * UARTs 0 and 1 are per-CPU; their interrupts are wired to
117
+ * the relevant CPU's PPI 0..3, aka INTID 16..19
118
+ */
119
+ for (int i = 0; i < machine->smp.cpus; i++) {
120
+ int intidbase = NUM_SPIS + i * GIC_INTERNAL;
121
+ g_autofree char *s = g_strdup_printf("cpu-uart-oflow-orgate%d", i);
122
+ DeviceState *orgate;
123
+
124
+ /* The two overflow IRQs from the UART are ORed together into PPI 3 */
125
+ object_initialize_child(OBJECT(mms), s, &mms->cpu_uart_oflow[i],
126
+ TYPE_OR_IRQ);
127
+ orgate = DEVICE(&mms->cpu_uart_oflow[i]);
128
+ qdev_prop_set_uint32(orgate, "num-lines", 2);
129
+ qdev_realize(orgate, NULL, &error_fatal);
130
+ qdev_connect_gpio_out(orgate, 0,
131
+ qdev_get_gpio_in(gicdev, intidbase + 19));
132
+
133
+ create_uart(mms, i, &mms->cpu_sysmem[i], 0xe7c00000,
134
+ qdev_get_gpio_in(gicdev, intidbase + 17), /* tx */
135
+ qdev_get_gpio_in(gicdev, intidbase + 16), /* rx */
136
+ qdev_get_gpio_in(orgate, 0), /* txover */
137
+ qdev_get_gpio_in(orgate, 1), /* rxover */
138
+ qdev_get_gpio_in(gicdev, intidbase + 18) /* combined */);
139
+ }
140
+ /*
141
+ * UARTs 2 to 5 are whole-system; all overflow IRQs are ORed
142
+ * together into IRQ 17
143
+ */
144
+ object_initialize_child(OBJECT(mms), "uart-oflow-orgate",
145
+ &mms->uart_oflow, TYPE_OR_IRQ);
146
+ qdev_prop_set_uint32(DEVICE(&mms->uart_oflow), "num-lines",
147
+ MPS3R_UART_MAX * 2);
148
+ qdev_realize(DEVICE(&mms->uart_oflow), NULL, &error_fatal);
149
+ qdev_connect_gpio_out(DEVICE(&mms->uart_oflow), 0,
150
+ qdev_get_gpio_in(gicdev, 17));
151
+
152
+ for (int i = 0; i < MPS3R_UART_MAX; i++) {
153
+ hwaddr baseaddr = 0xe0205000 + i * 0x1000;
154
+ int rxirq = 5 + i * 2, txirq = 6 + i * 2, combirq = 13 + i;
155
+
156
+ create_uart(mms, i + MPS3R_CPU_MAX, sysmem, baseaddr,
157
+ qdev_get_gpio_in(gicdev, txirq),
158
+ qdev_get_gpio_in(gicdev, rxirq),
159
+ qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2),
160
+ qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2 + 1),
161
+ qdev_get_gpio_in(gicdev, combirq));
162
+ }
163
164
mms->bootinfo.ram_size = machine->ram_size;
165
mms->bootinfo.board_id = -1;
88
--
166
--
89
2.20.1
167
2.34.1
90
168
91
169
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/21] target/arm: Allow ARMCPRegInfo read/write functions to throw exceptions
[PULL 33/35] hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
1
Currently the only part of an ARMCPRegInfo which is allowed to cause
1
Add the GPIO, watchdog, dual-timer and I2C devices to the mps3-an536
2
a CPU exception is the access function, which returns a value indicating
2
board. These are all simple devices that just need to be created and
3
that some flavour of UNDEF should be generated.
3
wired up.
4
5
For the ATS system instructions, we would like to conditionally
6
generate exceptions as part of the writefn, because some faults
7
during the page table walk (like external aborts) should cause
8
an exception to be raised rather than returning a value.
9
10
There are several ways we could do this:
11
* plumb the GETPC() value from the top level set_cp_reg/get_cp_reg
12
helper functions through into the readfn and writefn hooks
13
* add extra readfn_with_ra/writefn_with_ra hooks that take the GETPC()
14
value
15
* require the ATS instructions to provide a dummy accessfn,
16
which serves no purpose except to cause the code generation
17
to emit TCG ops to sync the CPU state
18
* add an ARM_CP_ flag to mark the ARMCPRegInfo as possibly
19
throwing an exception in its read/write hooks, and make the
20
codegen sync the CPU state before calling the hooks if the
21
flag is set
22
23
This patch opts for the last of these, as it is fairly simple
24
to implement and doesn't require invasive changes like updating
25
the readfn/writefn hook function prototype signature.
26
4
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
29
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Message-id: 20240206132931.38376-12-peter.maydell@linaro.org
30
Message-id: 20190816125802.25877-2-peter.maydell@linaro.org
31
---
8
---
32
target/arm/cpu.h | 6 +++++-
9
hw/arm/mps3r.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++
33
target/arm/translate-a64.c | 6 ++++++
10
1 file changed, 59 insertions(+)
34
target/arm/translate.c | 7 +++++++
35
3 files changed, 18 insertions(+), 1 deletion(-)
36
11
37
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
12
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
38
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/cpu.h
14
--- a/hw/arm/mps3r.c
40
+++ b/target/arm/cpu.h
15
+++ b/hw/arm/mps3r.c
41
@@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
16
@@ -XXX,XX +XXX,XX @@
42
* IO indicates that this register does I/O and therefore its accesses
17
#include "sysemu/sysemu.h"
43
* need to be surrounded by gen_io_start()/gen_io_end(). In particular,
18
#include "hw/boards.h"
44
* registers which implement clocks or timers require this.
19
#include "hw/or-irq.h"
45
+ * RAISES_EXC is for when the read or write hook might raise an exception;
20
+#include "hw/qdev-clock.h"
46
+ * the generated code will synchronize the CPU state before calling the hook
21
#include "hw/qdev-properties.h"
47
+ * so that it is safe for the hook to call raise_exception().
22
#include "hw/arm/boot.h"
48
*/
23
#include "hw/arm/bsa.h"
49
#define ARM_CP_SPECIAL 0x0001
24
#include "hw/char/cmsdk-apb-uart.h"
50
#define ARM_CP_CONST 0x0002
25
+#include "hw/i2c/arm_sbcon_i2c.h"
51
@@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
26
#include "hw/intc/arm_gicv3.h"
52
#define ARM_CP_FPU 0x1000
27
+#include "hw/misc/unimp.h"
53
#define ARM_CP_SVE 0x2000
28
+#include "hw/timer/cmsdk-apb-dualtimer.h"
54
#define ARM_CP_NO_GDB 0x4000
29
+#include "hw/watchdog/cmsdk-apb-watchdog.h"
55
+#define ARM_CP_RAISES_EXC 0x8000
30
56
/* Used only as a terminator for ARMCPRegInfo lists */
31
/* Define the layout of RAM and ROM in a board */
57
#define ARM_CP_SENTINEL 0xffff
32
typedef struct RAMInfo {
58
/* Mask of only the flag bits in a type field */
33
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
59
-#define ARM_CP_FLAG_MASK 0x70ff
34
CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
60
+#define ARM_CP_FLAG_MASK 0xf0ff
35
OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
61
36
OrIRQState uart_oflow;
62
/* Valid values for ARMCPRegInfo state field, indicating which of
37
+ CMSDKAPBWatchdog watchdog;
63
* the AArch32 and AArch64 execution states this register is visible in.
38
+ CMSDKAPBDualTimer dualtimer;
64
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
39
+ ArmSbconI2CState i2c[5];
65
index XXXXXXX..XXXXXXX 100644
40
+ Clock *clk;
66
--- a/target/arm/translate-a64.c
41
};
67
+++ b/target/arm/translate-a64.c
42
68
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
43
#define TYPE_MPS3R_MACHINE "mps3r"
69
tcg_temp_free_ptr(tmpptr);
44
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
70
tcg_temp_free_i32(tcg_syn);
45
MemoryRegion *sysmem = get_system_memory();
71
tcg_temp_free_i32(tcg_isread);
46
DeviceState *gicdev;
72
+ } else if (ri->type & ARM_CP_RAISES_EXC) {
47
73
+ /*
48
+ mms->clk = clock_new(OBJECT(machine), "CLK");
74
+ * The readfn or writefn might raise an exception;
49
+ clock_set_hz(mms->clk, CLK_FRQ);
75
+ * synchronize the CPU state in case it does.
50
+
76
+ */
51
for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
77
+ gen_a64_set_pc_im(s->pc_curr);
52
MemoryRegion *mr = mr_for_raminfo(mms, ri);
53
memory_region_add_subregion(sysmem, ri->base, mr);
54
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
55
qdev_get_gpio_in(gicdev, combirq));
78
}
56
}
79
57
80
/* Handle special cases first */
58
+ for (int i = 0; i < 4; i++) {
81
diff --git a/target/arm/translate.c b/target/arm/translate.c
59
+ /* CMSDK GPIO controllers */
82
index XXXXXXX..XXXXXXX 100644
60
+ g_autofree char *s = g_strdup_printf("gpio%d", i);
83
--- a/target/arm/translate.c
61
+ create_unimplemented_device(s, 0xe0000000 + i * 0x1000, 0x1000);
84
+++ b/target/arm/translate.c
62
+ }
85
@@ -XXX,XX +XXX,XX @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
63
+
86
tcg_temp_free_ptr(tmpptr);
64
+ object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
87
tcg_temp_free_i32(tcg_syn);
65
+ TYPE_CMSDK_APB_WATCHDOG);
88
tcg_temp_free_i32(tcg_isread);
66
+ qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->clk);
89
+ } else if (ri->type & ARM_CP_RAISES_EXC) {
67
+ sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
68
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
69
+ qdev_get_gpio_in(gicdev, 0));
70
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0xe0100000);
71
+
72
+ object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
73
+ TYPE_CMSDK_APB_DUALTIMER);
74
+ qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->clk);
75
+ sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
76
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
77
+ qdev_get_gpio_in(gicdev, 3));
78
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 1,
79
+ qdev_get_gpio_in(gicdev, 1));
80
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 2,
81
+ qdev_get_gpio_in(gicdev, 2));
82
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0xe0101000);
83
+
84
+ for (int i = 0; i < ARRAY_SIZE(mms->i2c); i++) {
85
+ static const hwaddr i2cbase[] = {0xe0102000, /* Touch */
86
+ 0xe0103000, /* Audio */
87
+ 0xe0107000, /* Shield0 */
88
+ 0xe0108000, /* Shield1 */
89
+ 0xe0109000}; /* DDR4 EEPROM */
90
+ g_autofree char *s = g_strdup_printf("i2c%d", i);
91
+
92
+ object_initialize_child(OBJECT(mms), s, &mms->i2c[i],
93
+ TYPE_ARM_SBCON_I2C);
94
+ sysbus_realize(SYS_BUS_DEVICE(&mms->i2c[i]), &error_fatal);
95
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->i2c[i]), 0, i2cbase[i]);
96
+ if (i != 2 && i != 3) {
90
+ /*
97
+ /*
91
+ * The readfn or writefn might raise an exception;
98
+ * internal-only bus: mark it full to avoid user-created
92
+ * synchronize the CPU state in case it does.
99
+ * i2c devices being plugged into it.
93
+ */
100
+ */
94
+ gen_set_condexec(s);
101
+ qbus_mark_full(qdev_get_child_bus(DEVICE(&mms->i2c[i]), "i2c"));
95
+ gen_set_pc_im(s, s->pc_curr);
102
+ }
96
}
103
+ }
97
104
+
98
/* Handle special cases first */
105
mms->bootinfo.ram_size = machine->ram_size;
106
mms->bootinfo.board_id = -1;
107
mms->bootinfo.loader_start = mmc->loader_start;
99
--
108
--
100
2.20.1
109
2.34.1
101
110
102
111
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/21] hw/arm: Use ARM_CPU_TYPE_NAME() macro when appropriate
[PULL 34/35] hw/arm/mps3r: Add remaining devices
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Add the remaining devices (or unimplemented-device stubs) for
2
this board: SPI controllers, SCC, FPGAIO, I2S, RTC, the
3
QSPI write-config block, and ethernet.
2
4
3
Commit ba1ba5cca introduce the ARM_CPU_TYPE_NAME() macro.
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Unify the code base by use it in all places.
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20240206132931.38376-13-peter.maydell@linaro.org
8
---
9
hw/arm/mps3r.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++
10
1 file changed, 74 insertions(+)
5
11
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20190823143249.8096-2-philmd@redhat.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/allwinner-a10.c | 3 ++-
13
hw/arm/cubieboard.c | 3 ++-
14
hw/arm/digic.c | 3 ++-
15
hw/arm/fsl-imx25.c | 2 +-
16
hw/arm/fsl-imx31.c | 2 +-
17
hw/arm/fsl-imx6.c | 3 ++-
18
hw/arm/fsl-imx6ul.c | 2 +-
19
hw/arm/xlnx-zynqmp.c | 8 ++++----
20
8 files changed, 15 insertions(+), 11 deletions(-)
21
22
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
23
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/arm/allwinner-a10.c
14
--- a/hw/arm/mps3r.c
25
+++ b/hw/arm/allwinner-a10.c
15
+++ b/hw/arm/mps3r.c
26
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
16
@@ -XXX,XX +XXX,XX @@
27
AwA10State *s = AW_A10(obj);
17
#include "hw/char/cmsdk-apb-uart.h"
28
18
#include "hw/i2c/arm_sbcon_i2c.h"
29
object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
19
#include "hw/intc/arm_gicv3.h"
30
- "cortex-a8-" TYPE_ARM_CPU, &error_abort, NULL);
20
+#include "hw/misc/mps2-scc.h"
31
+ ARM_CPU_TYPE_NAME("cortex-a8"),
21
+#include "hw/misc/mps2-fpgaio.h"
32
+ &error_abort, NULL);
22
#include "hw/misc/unimp.h"
33
23
+#include "hw/net/lan9118.h"
34
sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc),
24
+#include "hw/rtc/pl031.h"
35
TYPE_AW_A10_PIC);
25
+#include "hw/ssi/pl022.h"
36
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
26
#include "hw/timer/cmsdk-apb-dualtimer.h"
37
index XXXXXXX..XXXXXXX 100644
27
#include "hw/watchdog/cmsdk-apb-watchdog.h"
38
--- a/hw/arm/cubieboard.c
28
39
+++ b/hw/arm/cubieboard.c
29
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
40
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
30
CMSDKAPBWatchdog watchdog;
41
31
CMSDKAPBDualTimer dualtimer;
42
static void cubieboard_machine_init(MachineClass *mc)
32
ArmSbconI2CState i2c[5];
33
+ PL022State spi[3];
34
+ MPS2SCC scc;
35
+ MPS2FPGAIO fpgaio;
36
+ UnimplementedDeviceState i2s_audio;
37
+ PL031State rtc;
38
Clock *clk;
39
};
40
41
@@ -XXX,XX +XXX,XX @@ static const RAMInfo an536_raminfo[] = {
42
}
43
};
44
45
+static const int an536_oscclk[] = {
46
+ 24000000, /* 24MHz reference for RTC and timers */
47
+ 50000000, /* 50MHz ACLK */
48
+ 50000000, /* 50MHz MCLK */
49
+ 50000000, /* 50MHz GPUCLK */
50
+ 24576000, /* 24.576MHz AUDCLK */
51
+ 23750000, /* 23.75MHz HDLCDCLK */
52
+ 100000000, /* 100MHz DDR4_REF_CLK */
53
+};
54
+
55
static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
56
const RAMInfo *raminfo)
43
{
57
{
44
- mc->desc = "cubietech cubieboard";
58
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
45
+ mc->desc = "cubietech cubieboard (Cortex-A9)";
59
MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
46
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
60
MemoryRegion *sysmem = get_system_memory();
47
mc->init = cubieboard_init;
61
DeviceState *gicdev;
48
mc->block_default_type = IF_IDE;
62
+ QList *oscclk;
49
mc->units_per_default_bus = 1;
63
50
diff --git a/hw/arm/digic.c b/hw/arm/digic.c
64
mms->clk = clock_new(OBJECT(machine), "CLK");
51
index XXXXXXX..XXXXXXX 100644
65
clock_set_hz(mms->clk, CLK_FRQ);
52
--- a/hw/arm/digic.c
66
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
53
+++ b/hw/arm/digic.c
67
}
54
@@ -XXX,XX +XXX,XX @@ static void digic_init(Object *obj)
55
int i;
56
57
object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
58
- "arm946-" TYPE_ARM_CPU, &error_abort, NULL);
59
+ ARM_CPU_TYPE_NAME("arm946"),
60
+ &error_abort, NULL);
61
62
for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
63
#define DIGIC_TIMER_NAME_MLEN 11
64
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
65
index XXXXXXX..XXXXXXX 100644
66
--- a/hw/arm/fsl-imx25.c
67
+++ b/hw/arm/fsl-imx25.c
68
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
69
FslIMX25State *s = FSL_IMX25(obj);
70
int i;
71
72
- object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU);
73
+ object_initialize(&s->cpu, sizeof(s->cpu), ARM_CPU_TYPE_NAME("arm926"));
74
75
sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
76
TYPE_IMX_AVIC);
77
diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/hw/arm/fsl-imx31.c
80
+++ b/hw/arm/fsl-imx31.c
81
@@ -XXX,XX +XXX,XX @@ static void fsl_imx31_init(Object *obj)
82
FslIMX31State *s = FSL_IMX31(obj);
83
int i;
84
85
- object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU);
86
+ object_initialize(&s->cpu, sizeof(s->cpu), ARM_CPU_TYPE_NAME("arm1136"));
87
88
sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
89
TYPE_IMX_AVIC);
90
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/hw/arm/fsl-imx6.c
93
+++ b/hw/arm/fsl-imx6.c
94
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_init(Object *obj)
95
for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) {
96
snprintf(name, NAME_SIZE, "cpu%d", i);
97
object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
98
- "cortex-a9-" TYPE_ARM_CPU, &error_abort, NULL);
99
+ ARM_CPU_TYPE_NAME("cortex-a9"),
100
+ &error_abort, NULL);
101
}
68
}
102
69
103
sysbus_init_child_obj(obj, "a9mpcore", &s->a9mpcore, sizeof(s->a9mpcore),
70
+ for (int i = 0; i < ARRAY_SIZE(mms->spi); i++) {
104
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
71
+ g_autofree char *s = g_strdup_printf("spi%d", i);
105
index XXXXXXX..XXXXXXX 100644
72
+ hwaddr baseaddr = 0xe0104000 + i * 0x1000;
106
--- a/hw/arm/fsl-imx6ul.c
73
+
107
+++ b/hw/arm/fsl-imx6ul.c
74
+ object_initialize_child(OBJECT(mms), s, &mms->spi[i], TYPE_PL022);
108
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
75
+ sysbus_realize(SYS_BUS_DEVICE(&mms->spi[i]), &error_fatal);
109
int i;
76
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->spi[i]), 0, baseaddr);
110
77
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->spi[i]), 0,
111
object_initialize_child(obj, "cpu0", &s->cpu, sizeof(s->cpu),
78
+ qdev_get_gpio_in(gicdev, 22 + i));
112
- "cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL);
79
+ }
113
+ ARM_CPU_TYPE_NAME("cortex-a7"), &error_abort, NULL);
80
+
114
81
+ object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
115
/*
82
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg0", 0);
116
* A7MPCORE
83
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg4", 0x2);
117
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
84
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-aid", 0x00200008);
118
index XXXXXXX..XXXXXXX 100644
85
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-id", 0x41055360);
119
--- a/hw/arm/xlnx-zynqmp.c
86
+ oscclk = qlist_new();
120
+++ b/hw/arm/xlnx-zynqmp.c
87
+ for (int i = 0; i < ARRAY_SIZE(an536_oscclk); i++) {
121
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
88
+ qlist_append_int(oscclk, an536_oscclk[i]);
122
89
+ }
123
object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]",
90
+ qdev_prop_set_array(DEVICE(&mms->scc), "oscclk", oscclk);
124
&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
91
+ sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
125
- "cortex-r5f-" TYPE_ARM_CPU, &error_abort,
92
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->scc), 0, 0xe0200000);
126
- NULL);
93
+
127
+ ARM_CPU_TYPE_NAME("cortex-r5f"),
94
+ create_unimplemented_device("i2s-audio", 0xe0201000, 0x1000);
128
+ &error_abort, NULL);
95
+
129
96
+ object_initialize_child(OBJECT(mms), "fpgaio", &mms->fpgaio,
130
name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
97
+ TYPE_MPS2_FPGAIO);
131
if (strcmp(name, boot_cpu)) {
98
+ qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", an536_oscclk[1]);
132
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj)
99
+ qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "num-leds", 10);
133
for (i = 0; i < num_apus; i++) {
100
+ qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-switches", true);
134
object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]",
101
+ qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-dbgctrl", false);
135
&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
102
+ sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
136
- "cortex-a53-" TYPE_ARM_CPU, &error_abort,
103
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0xe0202000);
137
- NULL);
104
+
138
+ ARM_CPU_TYPE_NAME("cortex-a53"),
105
+ create_unimplemented_device("clcd", 0xe0209000, 0x1000);
139
+ &error_abort, NULL);
106
+
140
}
107
+ object_initialize_child(OBJECT(mms), "rtc", &mms->rtc, TYPE_PL031);
141
108
+ sysbus_realize(SYS_BUS_DEVICE(&mms->rtc), &error_fatal);
142
sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
109
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->rtc), 0, 0xe020a000);
110
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->rtc), 0,
111
+ qdev_get_gpio_in(gicdev, 4));
112
+
113
+ /*
114
+ * In hardware this is a LAN9220; the LAN9118 is software compatible
115
+ * except that it doesn't support the checksum-offload feature.
116
+ */
117
+ lan9118_init(0xe0300000,
118
+ qdev_get_gpio_in(gicdev, 18));
119
+
120
+ create_unimplemented_device("usb", 0xe0301000, 0x1000);
121
+ create_unimplemented_device("qspi-write-config", 0xe0600000, 0x1000);
122
+
123
mms->bootinfo.ram_size = machine->ram_size;
124
mms->bootinfo.board_id = -1;
125
mms->bootinfo.loader_start = mmc->loader_start;
143
--
126
--
144
2.20.1
127
2.34.1
145
128
146
129
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/21] hw/arm: Use object_initialize_child for correct reference counting
[PULL 35/35] docs: Add documentation for the mps3-an536 board
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Add documentation for the mps3-an536 board type.
2
2
3
As explained in commit aff39be0ed97:
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Message-id: 20240206132931.38376-14-peter.maydell@linaro.org
6
---
7
docs/system/arm/mps2.rst | 37 ++++++++++++++++++++++++++++++++++---
8
1 file changed, 34 insertions(+), 3 deletions(-)
4
9
5
Both functions, object_initialize() and object_property_add_child()
10
diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
6
increase the reference counter of the new object, so one of the
7
references has to be dropped afterwards to get the reference
8
counting right. Otherwise the child object will not be properly
9
cleaned up when the parent gets destroyed.
10
Thus let's use now object_initialize_child() instead to get the
11
reference counting here right.
12
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Reviewed-by: Thomas Huth <thuth@redhat.com>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20190823143249.8096-3-philmd@redhat.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
hw/arm/mcimx7d-sabre.c | 9 ++++-----
21
hw/arm/mps2-tz.c | 15 +++++++--------
22
hw/arm/musca.c | 9 +++++----
23
3 files changed, 16 insertions(+), 17 deletions(-)
24
25
diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
26
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/mcimx7d-sabre.c
12
--- a/docs/system/arm/mps2.rst
28
+++ b/hw/arm/mcimx7d-sabre.c
13
+++ b/docs/system/arm/mps2.rst
29
@@ -XXX,XX +XXX,XX @@ static void mcimx7d_sabre_init(MachineState *machine)
14
@@ -XXX,XX +XXX,XX @@
30
{
15
-Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an547``)
31
static struct arm_boot_info boot_info;
16
-=========================================================================================================================================================
32
MCIMX7Sabre *s = g_new0(MCIMX7Sabre, 1);
17
+Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an536``, ``mps3-an547``)
33
- Object *soc;
18
+=========================================================================================================================================================================
34
int i;
19
35
20
-These board models all use Arm M-profile CPUs.
36
if (machine->ram_size > FSL_IMX7_MMDC_SIZE) {
21
+These board models use Arm M-profile or R-profile CPUs.
37
@@ -XXX,XX +XXX,XX @@ static void mcimx7d_sabre_init(MachineState *machine)
22
38
.nb_cpus = machine->smp.cpus,
23
The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a
39
};
24
bigger FPGA but is otherwise the same as the 2; the 3 has a bigger
40
25
@@ -XXX,XX +XXX,XX @@ FPGA image.
41
- object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX7);
26
42
- soc = OBJECT(&s->soc);
27
QEMU models the following FPGA images:
43
- object_property_add_child(OBJECT(machine), "soc", soc, &error_fatal);
28
44
- object_property_set_bool(soc, true, "realized", &error_fatal);
29
+FPGA images using M-profile CPUs:
45
+ object_initialize_child(OBJECT(machine), "soc",
46
+ &s->soc, sizeof(s->soc),
47
+ TYPE_FSL_IMX7, &error_fatal, NULL);
48
+ object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
49
50
memory_region_allocate_system_memory(&s->ram, NULL, "mcimx7d-sabre.ram",
51
machine->ram_size);
52
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/arm/mps2-tz.c
55
+++ b/hw/arm/mps2-tz.c
56
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
57
/* The sec_resp_cfg output from the IoTKit must be split into multiple
58
* lines, one for each of the PPCs we create here, plus one per MSC.
59
*/
60
- object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter),
61
- TYPE_SPLIT_IRQ);
62
- object_property_add_child(OBJECT(machine), "sec-resp-splitter",
63
- OBJECT(&mms->sec_resp_splitter), &error_abort);
64
+ object_initialize_child(OBJECT(machine), "sec-resp-splitter",
65
+ &mms->sec_resp_splitter,
66
+ sizeof(mms->sec_resp_splitter),
67
+ TYPE_SPLIT_IRQ, &error_abort, NULL);
68
object_property_set_int(OBJECT(&mms->sec_resp_splitter),
69
ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc),
70
"num-lines", &error_fatal);
71
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
72
* Tx, Rx and "combined" IRQs are sent to the NVIC separately.
73
* Create the OR gate for this.
74
*/
75
- object_initialize(&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate),
76
- TYPE_OR_IRQ);
77
- object_property_add_child(OBJECT(mms), "uart-irq-orgate",
78
- OBJECT(&mms->uart_irq_orgate), &error_abort);
79
+ object_initialize_child(OBJECT(mms), "uart-irq-orgate",
80
+ &mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate),
81
+ TYPE_OR_IRQ, &error_abort, NULL);
82
object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines",
83
&error_fatal);
84
object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true,
85
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
86
index XXXXXXX..XXXXXXX 100644
87
--- a/hw/arm/musca.c
88
+++ b/hw/arm/musca.c
89
@@ -XXX,XX +XXX,XX @@ static void musca_init(MachineState *machine)
90
* The sec_resp_cfg output from the SSE-200 must be split into multiple
91
* lines, one for each of the PPCs we create here.
92
*/
93
- object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter),
94
- TYPE_SPLIT_IRQ);
95
- object_property_add_child(OBJECT(machine), "sec-resp-splitter",
96
- OBJECT(&mms->sec_resp_splitter), &error_fatal);
97
+ object_initialize_child(OBJECT(machine), "sec-resp-splitter",
98
+ &mms->sec_resp_splitter,
99
+ sizeof(mms->sec_resp_splitter),
100
+ TYPE_SPLIT_IRQ, &error_fatal, NULL);
101
+
30
+
102
object_property_set_int(OBJECT(&mms->sec_resp_splitter),
31
``mps2-an385``
103
ARRAY_SIZE(mms->ppc), "num-lines", &error_fatal);
32
Cortex-M3 as documented in Arm Application Note AN385
104
object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true,
33
``mps2-an386``
34
@@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images:
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``mps3-an547``
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Cortex-M55 on an MPS3, as documented in Arm Application Note AN547
37
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+FPGA images using R-profile CPUs:
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+
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+``mps3-an536``
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+ Dual Cortex-R52 on an MPS3, as documented in Arm Application Note AN536
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+
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Differences between QEMU and real hardware:
44
45
- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to
46
@@ -XXX,XX +XXX,XX @@ Differences between QEMU and real hardware:
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flash, but only as simple ROM, so attempting to rewrite the flash
48
from the guest will fail
49
- QEMU does not model the USB controller in MPS3 boards
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+- AN536 does not support runtime control of CPU reset and halt via
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+ the SCC CFG_REG0 register.
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+- AN536 does not support enabling or disabling the flash and ATCM
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+ interfaces via the SCC CFG_REG1 register.
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+- AN536 does not support setting of the initial vector table
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+ base address via the SCC CFG_REG6 and CFG_REG7 register config,
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+ and does not provide a mechanism for specifying these values at
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+ startup, so all guest images must be built to start from TCM
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+ (i.e. to expect the interrupt vector base at 0 from reset).
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+- AN536 defaults to only creating a single CPU; this is the equivalent
60
+ of the way the real FPGA image usually runs with the second Cortex-R52
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+ held in halt via the initial SCC CFG_REG0 register setting. You can
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+ create the second CPU with ``-smp 2``; both CPUs will then start
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+ execution immediately on startup.
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+
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+Note that for the AN536 the first UART is accessible only by
66
+CPU0, and the second UART is accessible only by CPU1. The
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+first UART accessible shared between both CPUs is the third
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+UART. Guest software might therefore be built to use either
69
+the first UART or the third UART; if you don't see any output
70
+from the UART you are looking at, try one of the others.
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+(Even if the AN536 machine is started with a single CPU and so
72
+no "CPU1-only UART", the UART numbering remains the same,
73
+with the third UART being the first of the shared ones.)
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75
Machine-specific options
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""""""""""""""""""""""""
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--
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--
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2.20.1
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2.34.1
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108
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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