[Qemu-devel] [PULL 00/29] target-arm queue
[PULL 00/52] target-arm queue
1
First arm pullreq of 4.2...
1
Big pullreq this week, though none of the new features are
2
particularly earthshaking. Most of the bulk is from code cleanup
3
patches from me or rth.
2
4
3
thanks
5
thanks
4
-- PMM
6
-- PMM
5
7
6
The following changes since commit 27608c7c66bd923eb5e5faab80e795408cbe2b51:
8
The following changes since commit b651b80822fa8cb66ca30087ac7fbc75507ae5d2:
7
9
8
Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20190814a' into staging (2019-08-16 12:00:18 +0100)
10
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.0-pull-request' into staging (2020-02-20 17:35:42 +0000)
9
11
10
are available in the Git repository at:
12
are available in the Git repository at:
11
13
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190816
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200221
13
15
14
for you to fetch changes up to 664b7e3b97d6376f3329986c465b3782458b0f8b:
16
for you to fetch changes up to 270a679b3f950d7c4c600f324aab8bff292d0971:
15
17
16
target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word (2019-08-16 14:02:53 +0100)
18
target/arm: Add missing checks for fpsp_v2 (2020-02-21 12:54:25 +0000)
17
19
18
----------------------------------------------------------------
20
----------------------------------------------------------------
19
target-arm queue:
21
target-arm queue:
20
* target/arm: generate a custom MIDR for -cpu max
22
* aspeed/scu: Implement chip ID register
21
* hw/misc/zynq_slcr: refactor to use standard register definition
23
* hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register
22
* Set ENET_BD_BDU in I.MX FEC controller
24
* mainstone: Make providing flash images non-mandatory
23
* target/arm: Fix routing of singlestep exceptions
25
* z2: Make providing flash images non-mandatory
24
* refactor a32/t32 decoder handling of PC
26
* Fix failures to flush SVE high bits after AdvSIMD INS/ZIP/UZP/TRN/TBL/TBX/EXT
25
* minor optimisations/cleanups of some a32/t32 codegen
27
* Minor performance improvement: spend less time recalculating hflags values
26
* target/arm/cpu64: Ensure kvm really supports aarch64=off
28
* Code cleanup to isar_feature function tests
27
* target/arm/cpu: Ensure we can use the pmu with kvm
29
* Implement ARMv8.1-PMU and ARMv8.4-PMU extensions
28
* target/arm: Minor cleanups preparatory to KVM SVE support
30
* Bugfix: correct handling of PMCR_EL0.LC bit
31
* Bugfix: correct definition of PMCRDP
32
* Correctly implement ACTLR2, HACTLR2
33
* allwinner: Wire up USB ports
34
* Vectorize emulation of USHL, SSHL, PMUL*
35
* xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd
36
* sh4: Fix PCI ISA IO memory subregion
37
* Code cleanup to use more isar_feature tests and fewer ARM_FEATURE_* tests
29
38
30
----------------------------------------------------------------
39
----------------------------------------------------------------
31
Aaron Hill (1):
40
Francisco Iglesias (1):
32
Set ENET_BD_BDU in I.MX FEC controller
41
xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd
33
42
34
Alex Bennée (1):
43
Guenter Roeck (6):
35
target/arm: generate a custom MIDR for -cpu max
44
mainstone: Make providing flash images non-mandatory
45
z2: Make providing flash images non-mandatory
46
hw: usb: hcd-ohci: Move OHCISysBusState and TYPE_SYSBUS_OHCI to include file
47
hcd-ehci: Introduce "companion-enable" sysbus property
48
arm: allwinner: Wire up USB ports
49
sh4: Fix PCI ISA IO memory subregion
36
50
37
Andrew Jones (6):
51
Joel Stanley (2):
38
target/arm/cpu64: Ensure kvm really supports aarch64=off
52
aspeed/scu: Create separate write callbacks
39
target/arm/cpu: Ensure we can use the pmu with kvm
53
aspeed/scu: Implement chip ID register
40
target/arm/helper: zcr: Add build bug next to value range assumption
41
target/arm/cpu: Use div-round-up to determine predicate register array size
42
target/arm/kvm64: Fix error returns
43
target/arm/kvm64: Move the get/put of fpsimd registers out
44
54
45
Damien Hedde (1):
55
Peter Maydell (21):
46
hw/misc/zynq_slcr: use standard register definition
56
target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers
57
target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan
58
target/arm: Add isar_feature_any_fp16 and document naming/usage conventions
59
target/arm: Define and use any_predinv isar_feature test
60
target/arm: Factor out PMU register definitions
61
target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1
62
target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field
63
target/arm: Define an aa32_pmu_8_1 isar feature test function
64
target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks
65
target/arm: Stop assuming DBGDIDR always exists
66
target/arm: Move DBGDIDR into ARMISARegisters
67
target/arm: Read debug-related ID registers from KVM
68
target/arm: Implement ARMv8.1-PMU extension
69
target/arm: Implement ARMv8.4-PMU extension
70
target/arm: Provide ARMv8.4-PMU in '-cpu max'
71
target/arm: Correct definition of PMCRDP
72
target/arm: Correct handling of PMCR_EL0.LC bit
73
target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks
74
target/arm: Use isar_feature function for testing AA32HPD feature
75
target/arm: Use FIELD_EX32 for testing 32-bit fields
76
target/arm: Correctly implement ACTLR2, HACTLR2
47
77
48
Peter Maydell (2):
78
Philippe Mathieu-Daudé (1):
49
target/arm: Factor out 'generate singlestep exception' function
79
hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register
50
target/arm: Fix routing of singlestep exceptions
51
80
52
Richard Henderson (18):
81
Richard Henderson (21):
53
target/arm: Pass in pc to thumb_insn_is_16bit
82
target/arm: Flush high bits of sve register after AdvSIMD EXT
54
target/arm: Introduce pc_curr
83
target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX
55
target/arm: Introduce read_pc
84
target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN
56
target/arm: Introduce add_reg_for_lit
85
target/arm: Flush high bits of sve register after AdvSIMD INS
57
target/arm: Remove redundant s->pc & ~1
86
target/arm: Use bit 55 explicitly for pauth
58
target/arm: Replace s->pc with s->base.pc_next
87
target/arm: Fix select for aa64_va_parameters_both
59
target/arm: Replace offset with pc in gen_exception_insn
88
target/arm: Remove ttbr1_valid check from get_phys_addr_lpae
60
target/arm: Replace offset with pc in gen_exception_internal_insn
89
target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid
61
target/arm: Remove offset argument to gen_exception_bkpt_insn
90
target/arm: Vectorize USHL and SSHL
62
target/arm: Use unallocated_encoding for aarch32
91
target/arm: Convert PMUL.8 to gvec
63
target/arm: Remove helper_double_saturate
92
target/arm: Convert PMULL.64 to gvec
64
target/arm: Use tcg_gen_extract_i32 for shifter_out_im
93
target/arm: Convert PMULL.8 to gvec
65
target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB
94
target/arm: Rename isar_feature_aa32_simd_r32
66
target/arm: Remove redundant shift tests
95
target/arm: Use isar_feature_aa32_simd_r32 more places
67
target/arm: Use ror32 instead of open-coding the operation
96
target/arm: Set MVFR0.FPSP for ARMv5 cpus
68
target/arm: Use tcg_gen_rotri_i32 for gen_swap_half
97
target/arm: Add isar_feature_aa32_simd_r16
69
target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR
98
target/arm: Rename isar_feature_aa32_fpdp_v2
70
target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word
99
target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}
100
target/arm: Perform fpdp_v2 check first
101
target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3
102
target/arm: Add missing checks for fpsp_v2
71
103
72
target/arm/cpu.h | 13 +-
104
hw/usb/hcd-ohci.h | 16 ++
73
target/arm/helper.h | 1 -
105
include/hw/arm/allwinner-a10.h | 6 +
74
target/arm/kvm_arm.h | 28 ++
106
target/arm/cpu.h | 173 ++++++++++++---
75
target/arm/translate-a64.h | 4 +-
107
target/arm/helper-sve.h | 2 +
76
target/arm/translate.h | 39 ++-
108
target/arm/helper.h | 21 +-
77
hw/misc/zynq_slcr.c | 450 ++++++++++++++++----------------
109
target/arm/internals.h | 47 +++-
78
hw/net/imx_fec.c | 4 +
110
target/arm/translate.h | 6 +
79
target/arm/cpu.c | 30 ++-
111
hw/arm/allwinner-a10.c | 43 ++++
80
target/arm/cpu64.c | 31 ++-
112
hw/arm/mainstone.c | 11 +-
81
target/arm/helper.c | 7 +
113
hw/arm/z2.c | 6 -
82
target/arm/kvm.c | 7 +
114
hw/intc/armv7m_nvic.c | 30 +--
83
target/arm/kvm64.c | 161 +++++++-----
115
hw/misc/aspeed_scu.c | 93 ++++++--
84
target/arm/op_helper.c | 15 --
116
hw/misc/iotkit-secctl.c | 2 +-
85
target/arm/translate-a64.c | 130 ++++------
117
hw/sh4/sh_pci.c | 11 +-
86
target/arm/translate-vfp.inc.c | 45 +---
118
hw/ssi/xilinx_spips.c | 2 +-
87
target/arm/translate.c | 572 +++++++++++++++++------------------------
119
hw/usb/hcd-ehci-sysbus.c | 2 +
88
16 files changed, 771 insertions(+), 766 deletions(-)
120
hw/usb/hcd-ohci.c | 15 --
121
linux-user/arm/signal.c | 4 +-
122
linux-user/elfload.c | 4 +-
123
target/arm/arch_dump.c | 11 +-
124
target/arm/cpu.c | 175 +++++++--------
125
target/arm/cpu64.c | 58 +++--
126
target/arm/debug_helper.c | 6 +-
127
target/arm/helper.c | 472 +++++++++++++++++++++++------------------
128
target/arm/kvm32.c | 25 +++
129
target/arm/kvm64.c | 46 ++++
130
target/arm/m_helper.c | 11 +-
131
target/arm/machine.c | 3 +-
132
target/arm/neon_helper.c | 117 ----------
133
target/arm/pauth_helper.c | 3 +-
134
target/arm/translate-a64.c | 92 ++++----
135
target/arm/translate-vfp.inc.c | 263 ++++++++++++++---------
136
target/arm/translate.c | 356 ++++++++++++++++++++++++++-----
137
target/arm/vec_helper.c | 211 ++++++++++++++++++
138
target/arm/vfp_helper.c | 2 +-
139
35 files changed, 1564 insertions(+), 781 deletions(-)
89
140
diff view generated by jsdifflib
[Qemu-devel] [PULL 22/29] target/arm/kvm64: Move the get/put of fpsimd registers out
[PULL 01/52] aspeed/scu: Create separate write callbacks
1
From: Andrew Jones <drjones@redhat.com>
1
From: Joel Stanley <joel@jms.id.au>
2
2
3
Move the getting/putting of the fpsimd registers out of
3
This splits the common write callback into separate ast2400 and ast2500
4
kvm_arch_get/put_registers() into their own helper functions
4
implementations. This makes it clearer when implementing differing
5
to prepare for alternatively getting/putting SVE registers.
5
behaviour.
6
6
7
No functional change.
7
Signed-off-by: Joel Stanley <joel@jms.id.au>
8
8
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
9
Signed-off-by: Andrew Jones <drjones@redhat.com>
9
Reviewed-by: Cédric Le Goater <clg@kaod.org>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20200121013302.43839-2-joel@jms.id.au
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
13
---
14
target/arm/kvm64.c | 148 +++++++++++++++++++++++++++------------------
14
hw/misc/aspeed_scu.c | 80 +++++++++++++++++++++++++++++++-------------
15
1 file changed, 88 insertions(+), 60 deletions(-)
15
1 file changed, 57 insertions(+), 23 deletions(-)
16
16
17
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
17
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
18
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/kvm64.c
19
--- a/hw/misc/aspeed_scu.c
20
+++ b/target/arm/kvm64.c
20
+++ b/hw/misc/aspeed_scu.c
21
@@ -XXX,XX +XXX,XX @@ int kvm_arm_cpreg_level(uint64_t regidx)
21
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
22
#define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \
22
return s->regs[reg];
23
KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
23
}
24
24
25
+static int kvm_arch_put_fpsimd(CPUState *cs)
25
-static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
26
- unsigned size)
27
+static void aspeed_ast2400_scu_write(void *opaque, hwaddr offset,
28
+ uint64_t data, unsigned size)
26
+{
29
+{
27
+ ARMCPU *cpu = ARM_CPU(cs);
30
+ AspeedSCUState *s = ASPEED_SCU(opaque);
28
+ CPUARMState *env = &cpu->env;
31
+ int reg = TO_REG(offset);
29
+ struct kvm_one_reg reg;
30
+ uint32_t fpr;
31
+ int i, ret;
32
+
32
+
33
+ for (i = 0; i < 32; i++) {
33
+ if (reg >= ASPEED_SCU_NR_REGS) {
34
+ uint64_t *q = aa64_vfp_qreg(env, i);
34
+ qemu_log_mask(LOG_GUEST_ERROR,
35
+#ifdef HOST_WORDS_BIGENDIAN
35
+ "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
36
+ uint64_t fp_val[2] = { q[1], q[0] };
36
+ __func__, offset);
37
+ reg.addr = (uintptr_t)fp_val;
37
+ return;
38
+#else
39
+ reg.addr = (uintptr_t)q;
40
+#endif
41
+ reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
42
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
43
+ if (ret) {
44
+ return ret;
45
+ }
46
+ }
38
+ }
47
+
39
+
48
+ reg.addr = (uintptr_t)(&fpr);
40
+ if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
49
+ fpr = vfp_get_fpsr(env);
41
+ !s->regs[PROT_KEY]) {
50
+ reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
42
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
51
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
52
+ if (ret) {
53
+ return ret;
54
+ }
43
+ }
55
+
44
+
56
+ reg.addr = (uintptr_t)(&fpr);
45
+ trace_aspeed_scu_write(offset, size, data);
57
+ fpr = vfp_get_fpcr(env);
46
+
58
+ reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
47
+ switch (reg) {
59
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
48
+ case PROT_KEY:
60
+ if (ret) {
49
+ s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
61
+ return ret;
50
+ return;
51
+ case SILICON_REV:
52
+ case FREQ_CNTR_EVAL:
53
+ case VGA_SCRATCH1 ... VGA_SCRATCH8:
54
+ case RNG_DATA:
55
+ case FREE_CNTR4:
56
+ case FREE_CNTR4_EXT:
57
+ qemu_log_mask(LOG_GUEST_ERROR,
58
+ "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
59
+ __func__, offset);
60
+ return;
62
+ }
61
+ }
63
+
62
+
64
+ return 0;
63
+ s->regs[reg] = data;
65
+}
64
+}
66
+
65
+
67
int kvm_arch_put_registers(CPUState *cs, int level)
66
+static void aspeed_ast2500_scu_write(void *opaque, hwaddr offset,
67
+ uint64_t data, unsigned size)
68
{
68
{
69
struct kvm_one_reg reg;
69
AspeedSCUState *s = ASPEED_SCU(opaque);
70
- uint32_t fpr;
70
int reg = TO_REG(offset);
71
uint64_t val;
71
@@ -XXX,XX +XXX,XX @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
72
- int i;
72
case PROT_KEY:
73
- int ret;
73
s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
74
+ int i, ret;
74
return;
75
unsigned int el;
75
- case CLK_SEL:
76
76
- s->regs[reg] = data;
77
ARMCPU *cpu = ARM_CPU(cs);
77
- break;
78
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
78
case HW_STRAP1:
79
}
79
- if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
80
}
80
- s->regs[HW_STRAP1] |= data;
81
81
- return;
82
- /* Advanced SIMD and FP registers. */
83
- for (i = 0; i < 32; i++) {
84
- uint64_t *q = aa64_vfp_qreg(env, i);
85
-#ifdef HOST_WORDS_BIGENDIAN
86
- uint64_t fp_val[2] = { q[1], q[0] };
87
- reg.addr = (uintptr_t)fp_val;
88
-#else
89
- reg.addr = (uintptr_t)q;
90
-#endif
91
- reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
92
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
93
- if (ret) {
94
- return ret;
95
- }
82
- }
96
- }
83
- /* Jump to assignment below */
97
-
84
- break;
98
- reg.addr = (uintptr_t)(&fpr);
85
+ s->regs[HW_STRAP1] |= data;
99
- fpr = vfp_get_fpsr(env);
86
+ return;
100
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
87
case SILICON_REV:
101
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
88
- if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
102
- if (ret) {
89
- s->regs[HW_STRAP1] &= ~data;
103
- return ret;
90
- } else {
104
- }
91
- qemu_log_mask(LOG_GUEST_ERROR,
105
-
92
- "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
106
- fpr = vfp_get_fpcr(env);
93
- __func__, offset);
107
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
94
- }
108
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
95
- /* Avoid assignment below, we've handled everything */
109
+ ret = kvm_arch_put_fpsimd(cs);
96
+ s->regs[HW_STRAP1] &= ~data;
110
if (ret) {
97
return;
111
return ret;
98
case FREQ_CNTR_EVAL:
112
}
99
case VGA_SCRATCH1 ... VGA_SCRATCH8:
113
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
100
@@ -XXX,XX +XXX,XX @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
114
return ret;
101
s->regs[reg] = data;
115
}
102
}
116
103
117
+static int kvm_arch_get_fpsimd(CPUState *cs)
104
-static const MemoryRegionOps aspeed_scu_ops = {
118
+{
105
+static const MemoryRegionOps aspeed_ast2400_scu_ops = {
119
+ ARMCPU *cpu = ARM_CPU(cs);
106
.read = aspeed_scu_read,
120
+ CPUARMState *env = &cpu->env;
107
- .write = aspeed_scu_write,
121
+ struct kvm_one_reg reg;
108
+ .write = aspeed_ast2400_scu_write,
122
+ uint32_t fpr;
109
+ .endianness = DEVICE_LITTLE_ENDIAN,
123
+ int i, ret;
110
+ .valid.min_access_size = 4,
111
+ .valid.max_access_size = 4,
112
+ .valid.unaligned = false,
113
+};
124
+
114
+
125
+ for (i = 0; i < 32; i++) {
115
+static const MemoryRegionOps aspeed_ast2500_scu_ops = {
126
+ uint64_t *q = aa64_vfp_qreg(env, i);
116
+ .read = aspeed_scu_read,
127
+ reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
117
+ .write = aspeed_ast2500_scu_write,
128
+ reg.addr = (uintptr_t)q;
118
.endianness = DEVICE_LITTLE_ENDIAN,
129
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
119
.valid.min_access_size = 4,
130
+ if (ret) {
120
.valid.max_access_size = 4,
131
+ return ret;
121
@@ -XXX,XX +XXX,XX @@ static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data)
132
+ } else {
122
asc->calc_hpll = aspeed_2400_scu_calc_hpll;
133
+#ifdef HOST_WORDS_BIGENDIAN
123
asc->apb_divider = 2;
134
+ uint64_t t;
124
asc->nr_regs = ASPEED_SCU_NR_REGS;
135
+ t = q[0], q[0] = q[1], q[1] = t;
125
- asc->ops = &aspeed_scu_ops;
136
+#endif
126
+ asc->ops = &aspeed_ast2400_scu_ops;
137
+ }
127
}
138
+ }
128
139
+
129
static const TypeInfo aspeed_2400_scu_info = {
140
+ reg.addr = (uintptr_t)(&fpr);
130
@@ -XXX,XX +XXX,XX @@ static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data)
141
+ reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
131
asc->calc_hpll = aspeed_2500_scu_calc_hpll;
142
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
132
asc->apb_divider = 4;
143
+ if (ret) {
133
asc->nr_regs = ASPEED_SCU_NR_REGS;
144
+ return ret;
134
- asc->ops = &aspeed_scu_ops;
145
+ }
135
+ asc->ops = &aspeed_ast2500_scu_ops;
146
+ vfp_set_fpsr(env, fpr);
136
}
147
+
137
148
+ reg.addr = (uintptr_t)(&fpr);
138
static const TypeInfo aspeed_2500_scu_info = {
149
+ reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
150
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
151
+ if (ret) {
152
+ return ret;
153
+ }
154
+ vfp_set_fpcr(env, fpr);
155
+
156
+ return 0;
157
+}
158
+
159
int kvm_arch_get_registers(CPUState *cs)
160
{
161
struct kvm_one_reg reg;
162
uint64_t val;
163
- uint32_t fpr;
164
unsigned int el;
165
- int i;
166
- int ret;
167
+ int i, ret;
168
169
ARMCPU *cpu = ARM_CPU(cs);
170
CPUARMState *env = &cpu->env;
171
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
172
env->spsr = env->banked_spsr[i];
173
}
174
175
- /* Advanced SIMD and FP registers */
176
- for (i = 0; i < 32; i++) {
177
- uint64_t *q = aa64_vfp_qreg(env, i);
178
- reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
179
- reg.addr = (uintptr_t)q;
180
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
181
- if (ret) {
182
- return ret;
183
- } else {
184
-#ifdef HOST_WORDS_BIGENDIAN
185
- uint64_t t;
186
- t = q[0], q[0] = q[1], q[1] = t;
187
-#endif
188
- }
189
- }
190
-
191
- reg.addr = (uintptr_t)(&fpr);
192
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
193
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
194
+ ret = kvm_arch_get_fpsimd(cs);
195
if (ret) {
196
return ret;
197
}
198
- vfp_set_fpsr(env, fpr);
199
-
200
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
201
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
202
- if (ret) {
203
- return ret;
204
- }
205
- vfp_set_fpcr(env, fpr);
206
207
ret = kvm_get_vcpu_events(cpu);
208
if (ret) {
209
--
139
--
210
2.20.1
140
2.20.1
211
141
212
142
diff view generated by jsdifflib
New patch
[PULL 02/52] aspeed/scu: Implement chip ID register
1
From: Joel Stanley <joel@jms.id.au>
1
2
3
This returns a fixed but non-zero value for the chip id.
4
5
Signed-off-by: Joel Stanley <joel@jms.id.au>
6
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20200121013302.43839-3-joel@jms.id.au
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/misc/aspeed_scu.c | 13 +++++++++++++
13
1 file changed, 13 insertions(+)
14
15
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/misc/aspeed_scu.c
18
+++ b/hw/misc/aspeed_scu.c
19
@@ -XXX,XX +XXX,XX @@
20
#define CPU2_BASE_SEG4 TO_REG(0x110)
21
#define CPU2_BASE_SEG5 TO_REG(0x114)
22
#define CPU2_CACHE_CTRL TO_REG(0x118)
23
+#define CHIP_ID0 TO_REG(0x150)
24
+#define CHIP_ID1 TO_REG(0x154)
25
#define UART_HPLL_CLK TO_REG(0x160)
26
#define PCIE_CTRL TO_REG(0x180)
27
#define BMC_MMIO_CTRL TO_REG(0x184)
28
@@ -XXX,XX +XXX,XX @@
29
#define AST2600_HW_STRAP2_PROT TO_REG(0x518)
30
#define AST2600_RNG_CTRL TO_REG(0x524)
31
#define AST2600_RNG_DATA TO_REG(0x540)
32
+#define AST2600_CHIP_ID0 TO_REG(0x5B0)
33
+#define AST2600_CHIP_ID1 TO_REG(0x5B4)
34
35
#define AST2600_CLK TO_REG(0x40)
36
37
@@ -XXX,XX +XXX,XX @@ static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = {
38
[CPU2_BASE_SEG1] = 0x80000000U,
39
[CPU2_BASE_SEG4] = 0x1E600000U,
40
[CPU2_BASE_SEG5] = 0xC0000000U,
41
+ [CHIP_ID0] = 0x1234ABCDU,
42
+ [CHIP_ID1] = 0x88884444U,
43
[UART_HPLL_CLK] = 0x00001903U,
44
[PCIE_CTRL] = 0x0000007BU,
45
[BMC_DEV_ID] = 0x00002402U
46
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2500_scu_write(void *opaque, hwaddr offset,
47
case RNG_DATA:
48
case FREE_CNTR4:
49
case FREE_CNTR4_EXT:
50
+ case CHIP_ID0:
51
+ case CHIP_ID1:
52
qemu_log_mask(LOG_GUEST_ERROR,
53
"%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
54
__func__, offset);
55
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset,
56
case AST2600_RNG_DATA:
57
case AST2600_SILICON_REV:
58
case AST2600_SILICON_REV2:
59
+ case AST2600_CHIP_ID0:
60
+ case AST2600_CHIP_ID1:
61
/* Add read only registers here */
62
qemu_log_mask(LOG_GUEST_ERROR,
63
"%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
64
@@ -XXX,XX +XXX,XX @@ static const uint32_t ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = {
65
[AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0,
66
[AST2600_SDRAM_HANDSHAKE] = 0x00000040, /* SoC completed DRAM init */
67
[AST2600_HPLL_PARAM] = 0x1000405F,
68
+ [AST2600_CHIP_ID0] = 0x1234ABCD,
69
+ [AST2600_CHIP_ID1] = 0x88884444,
70
+
71
};
72
73
static void aspeed_ast2600_scu_reset(DeviceState *dev)
74
--
75
2.20.1
76
77
diff view generated by jsdifflib
New patch
[PULL 03/52] hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Fix warning reported by Clang static code analyzer:
4
5
CC hw/misc/iotkit-secctl.o
6
hw/misc/iotkit-secctl.c:343:9: warning: Value stored to 'value' is never read
7
value &= 0x00f000f3;
8
^ ~~~~~~~~~~
9
10
Fixes: b3717c23e1c
11
Reported-by: Clang Static Analyzer
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20200217132922.24607-1-f4bug@amsat.org
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/misc/iotkit-secctl.c | 2 +-
18
1 file changed, 1 insertion(+), 1 deletion(-)
19
20
diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/misc/iotkit-secctl.c
23
+++ b/hw/misc/iotkit-secctl.c
24
@@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr,
25
qemu_set_irq(s->sec_resp_cfg, s->secrespcfg);
26
break;
27
case A_SECPPCINTCLR:
28
- value &= 0x00f000f3;
29
+ s->secppcintstat &= ~(value & 0x00f000f3);
30
foreach_ppc(s, iotkit_secctl_ppc_update_irq_clear);
31
break;
32
case A_SECPPCINTEN:
33
--
34
2.20.1
35
36
diff view generated by jsdifflib
New patch
[PULL 04/52] mainstone: Make providing flash images non-mandatory
1
From: Guenter Roeck <linux@roeck-us.net>
1
2
3
Up to now, the mainstone machine only boots if two flash images are
4
provided. This is not really necessary; the machine can boot from initrd
5
or from SD without it. At the same time, having to provide dummy flash
6
images is a nuisance and does not add any real value. Make it optional.
7
8
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 20200217210824.18513-1-linux@roeck-us.net
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/mainstone.c | 11 +----------
14
1 file changed, 1 insertion(+), 10 deletions(-)
15
16
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/mainstone.c
19
+++ b/hw/arm/mainstone.c
20
@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
21
/* There are two 32MiB flash devices on the board */
22
for (i = 0; i < 2; i ++) {
23
dinfo = drive_get(IF_PFLASH, 0, i);
24
- if (!dinfo) {
25
- if (qtest_enabled()) {
26
- break;
27
- }
28
- error_report("Two flash images must be given with the "
29
- "'pflash' parameter");
30
- exit(1);
31
- }
32
-
33
if (!pflash_cfi01_register(mainstone_flash_base[i],
34
i ? "mainstone.flash1" : "mainstone.flash0",
35
MAINSTONE_FLASH,
36
- blk_by_legacy_dinfo(dinfo),
37
+ dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
38
sector_len, 4, 0, 0, 0, 0, be)) {
39
error_report("Error registering flash memory");
40
exit(1);
41
--
42
2.20.1
43
44
diff view generated by jsdifflib
New patch
[PULL 05/52] z2: Make providing flash images non-mandatory
1
From: Guenter Roeck <linux@roeck-us.net>
1
2
3
Up to now, the z2 machine only boots if a flash image is provided.
4
This is not really necessary; the machine can boot from initrd or from
5
SD without it. At the same time, having to provide dummy flash images
6
is a nuisance and does not add any real value. Make it optional.
7
8
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 20200217210903.18602-1-linux@roeck-us.net
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/z2.c | 6 ------
14
1 file changed, 6 deletions(-)
15
16
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/z2.c
19
+++ b/hw/arm/z2.c
20
@@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine)
21
be = 0;
22
#endif
23
dinfo = drive_get(IF_PFLASH, 0, 0);
24
- if (!dinfo && !qtest_enabled()) {
25
- error_report("Flash image must be given with the "
26
- "'pflash' parameter");
27
- exit(1);
28
- }
29
-
30
if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
31
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
32
sector_len, 4, 0, 0, 0, 0, be)) {
33
--
34
2.20.1
35
36
diff view generated by jsdifflib
[Qemu-devel] [PULL 29/29] target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word
[PULL 06/52] target/arm: Flush high bits of sve register after AdvSIMD EXT
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Separate shift + extract low will result in one extra insn
3
Writes to AdvSIMD registers flush the bits above 128.
4
for hosts like RISC-V, MIPS, and Sparc.
5
4
5
Buglink: https://bugs.launchpad.net/bugs/1863247
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190808202616.13782-8-richard.henderson@linaro.org
7
Message-id: 20200214194643.23317-2-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/translate.c | 18 ++++++------------
11
target/arm/translate-a64.c | 1 +
12
1 file changed, 6 insertions(+), 12 deletions(-)
12
1 file changed, 1 insertion(+)
13
13
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
16
--- a/target/arm/translate-a64.c
17
+++ b/target/arm/translate.c
17
+++ b/target/arm/translate-a64.c
18
@@ -XXX,XX +XXX,XX @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
18
@@ -XXX,XX +XXX,XX @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
19
if (insn & ARM_CP_RW_BIT) { /* TMRRC */
19
tcg_temp_free_i64(tcg_resl);
20
iwmmxt_load_reg(cpu_V0, wrd);
20
write_vec_element(s, tcg_resh, rd, 1, MO_64);
21
tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0);
21
tcg_temp_free_i64(tcg_resh);
22
- tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
22
+ clear_vec_high(s, true, rd);
23
- tcg_gen_extrl_i64_i32(cpu_R[rdhi], cpu_V0);
24
+ tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0);
25
} else { /* TMCRR */
26
tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
27
iwmmxt_store_reg(cpu_V0, wrd);
28
@@ -XXX,XX +XXX,XX @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
29
if (insn & ARM_CP_RW_BIT) { /* MRA */
30
iwmmxt_load_reg(cpu_V0, acc);
31
tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0);
32
- tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
33
- tcg_gen_extrl_i64_i32(cpu_R[rdhi], cpu_V0);
34
+ tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0);
35
tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
36
} else { /* MAR */
37
tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
38
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
39
gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
40
break;
41
case 2:
42
- tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
43
- tcg_gen_extrl_i64_i32(tmp, cpu_V0);
44
+ tcg_gen_extrh_i64_i32(tmp, cpu_V0);
45
break;
46
default: abort();
47
}
48
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
49
break;
50
case 2:
51
tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
52
- tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
53
- tcg_gen_extrl_i64_i32(tmp, cpu_V0);
54
+ tcg_gen_extrh_i64_i32(tmp, cpu_V0);
55
break;
56
default: abort();
57
}
58
@@ -XXX,XX +XXX,XX @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
59
tmp = tcg_temp_new_i32();
60
tcg_gen_extrl_i64_i32(tmp, tmp64);
61
store_reg(s, rt, tmp);
62
- tcg_gen_shri_i64(tmp64, tmp64, 32);
63
tmp = tcg_temp_new_i32();
64
- tcg_gen_extrl_i64_i32(tmp, tmp64);
65
+ tcg_gen_extrh_i64_i32(tmp, tmp64);
66
tcg_temp_free_i64(tmp64);
67
store_reg(s, rt2, tmp);
68
} else {
69
@@ -XXX,XX +XXX,XX @@ static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
70
tcg_gen_extrl_i64_i32(tmp, val);
71
store_reg(s, rlow, tmp);
72
tmp = tcg_temp_new_i32();
73
- tcg_gen_shri_i64(val, val, 32);
74
- tcg_gen_extrl_i64_i32(tmp, val);
75
+ tcg_gen_extrh_i64_i32(tmp, val);
76
store_reg(s, rhigh, tmp);
77
}
23
}
78
24
25
/* TBL/TBX
79
--
26
--
80
2.20.1
27
2.20.1
81
28
82
29
diff view generated by jsdifflib
[Qemu-devel] [PULL 28/29] target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR
[PULL 07/52] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
All of the inputs to these instructions are 32-bits. Rather than
3
Writes to AdvSIMD registers flush the bits above 128.
4
extend each input to 64-bits and then extract the high 32-bits of
5
the output, use tcg_gen_muls2_i32 and other 32-bit generator functions.
6
4
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20190808202616.13782-7-richard.henderson@linaro.org
6
Message-id: 20200214194643.23317-3-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
9
---
12
target/arm/translate.c | 72 +++++++++++++++---------------------------
10
target/arm/translate-a64.c | 1 +
13
1 file changed, 26 insertions(+), 46 deletions(-)
11
1 file changed, 1 insertion(+)
14
12
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.c
15
--- a/target/arm/translate-a64.c
18
+++ b/target/arm/translate.c
16
+++ b/target/arm/translate-a64.c
19
@@ -XXX,XX +XXX,XX @@ static void gen_revsh(TCGv_i32 var)
17
@@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
20
tcg_gen_ext16s_i32(var, var);
18
tcg_temp_free_i64(tcg_resl);
19
write_vec_element(s, tcg_resh, rd, 1, MO_64);
20
tcg_temp_free_i64(tcg_resh);
21
+ clear_vec_high(s, true, rd);
21
}
22
}
22
23
23
-/* Return (b << 32) + a. Mark inputs as dead */
24
/* ZIP/UZP/TRN
24
-static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv_i32 b)
25
-{
26
- TCGv_i64 tmp64 = tcg_temp_new_i64();
27
-
28
- tcg_gen_extu_i32_i64(tmp64, b);
29
- tcg_temp_free_i32(b);
30
- tcg_gen_shli_i64(tmp64, tmp64, 32);
31
- tcg_gen_add_i64(a, tmp64, a);
32
-
33
- tcg_temp_free_i64(tmp64);
34
- return a;
35
-}
36
-
37
-/* Return (b << 32) - a. Mark inputs as dead. */
38
-static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv_i32 b)
39
-{
40
- TCGv_i64 tmp64 = tcg_temp_new_i64();
41
-
42
- tcg_gen_extu_i32_i64(tmp64, b);
43
- tcg_temp_free_i32(b);
44
- tcg_gen_shli_i64(tmp64, tmp64, 32);
45
- tcg_gen_sub_i64(a, tmp64, a);
46
-
47
- tcg_temp_free_i64(tmp64);
48
- return a;
49
-}
50
-
51
/* 32x32->64 multiply. Marks inputs as dead. */
52
static TCGv_i64 gen_mulu_i64_i32(TCGv_i32 a, TCGv_i32 b)
53
{
54
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
55
(SMMUL, SMMLA, SMMLS) */
56
tmp = load_reg(s, rm);
57
tmp2 = load_reg(s, rs);
58
- tmp64 = gen_muls_i64_i32(tmp, tmp2);
59
+ tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2);
60
61
if (rd != 15) {
62
- tmp = load_reg(s, rd);
63
+ tmp3 = load_reg(s, rd);
64
if (insn & (1 << 6)) {
65
- tmp64 = gen_subq_msw(tmp64, tmp);
66
+ tcg_gen_sub_i32(tmp, tmp, tmp3);
67
} else {
68
- tmp64 = gen_addq_msw(tmp64, tmp);
69
+ tcg_gen_add_i32(tmp, tmp, tmp3);
70
}
71
+ tcg_temp_free_i32(tmp3);
72
}
73
if (insn & (1 << 5)) {
74
- tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
75
+ /*
76
+ * Adding 0x80000000 to the 64-bit quantity
77
+ * means that we have carry in to the high
78
+ * word when the low word has the high bit set.
79
+ */
80
+ tcg_gen_shri_i32(tmp2, tmp2, 31);
81
+ tcg_gen_add_i32(tmp, tmp, tmp2);
82
}
83
- tcg_gen_shri_i64(tmp64, tmp64, 32);
84
- tmp = tcg_temp_new_i32();
85
- tcg_gen_extrl_i64_i32(tmp, tmp64);
86
- tcg_temp_free_i64(tmp64);
87
+ tcg_temp_free_i32(tmp2);
88
store_reg(s, rn, tmp);
89
break;
90
case 0:
91
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
92
}
93
break;
94
case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
95
- tmp64 = gen_muls_i64_i32(tmp, tmp2);
96
+ tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2);
97
if (rs != 15) {
98
- tmp = load_reg(s, rs);
99
+ tmp3 = load_reg(s, rs);
100
if (insn & (1 << 20)) {
101
- tmp64 = gen_addq_msw(tmp64, tmp);
102
+ tcg_gen_add_i32(tmp, tmp, tmp3);
103
} else {
104
- tmp64 = gen_subq_msw(tmp64, tmp);
105
+ tcg_gen_sub_i32(tmp, tmp, tmp3);
106
}
107
+ tcg_temp_free_i32(tmp3);
108
}
109
if (insn & (1 << 4)) {
110
- tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
111
+ /*
112
+ * Adding 0x80000000 to the 64-bit quantity
113
+ * means that we have carry in to the high
114
+ * word when the low word has the high bit set.
115
+ */
116
+ tcg_gen_shri_i32(tmp2, tmp2, 31);
117
+ tcg_gen_add_i32(tmp, tmp, tmp2);
118
}
119
- tcg_gen_shri_i64(tmp64, tmp64, 32);
120
- tmp = tcg_temp_new_i32();
121
- tcg_gen_extrl_i64_i32(tmp, tmp64);
122
- tcg_temp_free_i64(tmp64);
123
+ tcg_temp_free_i32(tmp2);
124
break;
125
case 7: /* Unsigned sum of absolute differences. */
126
gen_helper_usad8(tmp, tmp, tmp2);
127
--
25
--
128
2.20.1
26
2.20.1
129
27
130
28
diff view generated by jsdifflib
[Qemu-devel] [PULL 27/29] target/arm: Use tcg_gen_rotri_i32 for gen_swap_half
[PULL 08/52] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Rotate is the more compact and obvious way to swap 16-bit
3
Writes to AdvSIMD registers flush the bits above 128.
4
elements of a 32-bit word.
5
4
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190808202616.13782-6-richard.henderson@linaro.org
6
Message-id: 20200214194643.23317-4-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
9
---
11
target/arm/translate.c | 6 +-----
10
target/arm/translate-a64.c | 1 +
12
1 file changed, 1 insertion(+), 5 deletions(-)
11
1 file changed, 1 insertion(+)
13
12
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
15
--- a/target/arm/translate-a64.c
17
+++ b/target/arm/translate.c
16
+++ b/target/arm/translate-a64.c
18
@@ -XXX,XX +XXX,XX @@ static TCGv_i64 gen_muls_i64_i32(TCGv_i32 a, TCGv_i32 b)
17
@@ -XXX,XX +XXX,XX @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
19
/* Swap low and high halfwords. */
18
tcg_temp_free_i64(tcg_resl);
20
static void gen_swap_half(TCGv_i32 var)
19
write_vec_element(s, tcg_resh, rd, 1, MO_64);
21
{
20
tcg_temp_free_i64(tcg_resh);
22
- TCGv_i32 tmp = tcg_temp_new_i32();
21
+ clear_vec_high(s, true, rd);
23
- tcg_gen_shri_i32(tmp, var, 16);
24
- tcg_gen_shli_i32(var, var, 16);
25
- tcg_gen_or_i32(var, var, tmp);
26
- tcg_temp_free_i32(tmp);
27
+ tcg_gen_rotri_i32(var, var, 16);
28
}
22
}
29
23
30
/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
24
/*
31
--
25
--
32
2.20.1
26
2.20.1
33
27
34
28
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/29] target/arm: Remove offset argument to gen_exception_bkpt_insn
[PULL 09/52] target/arm: Flush high bits of sve register after AdvSIMD INS
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Unlike the other more generic gen_exception{,_internal}_insn
3
Writes to AdvSIMD registers flush the bits above 128.
4
interfaces, breakpoints always refer to the current instruction.
5
4
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200214194643.23317-5-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190807045335.1361-10-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
9
---
12
target/arm/translate-a64.c | 7 +++----
10
target/arm/translate-a64.c | 6 ++++++
13
target/arm/translate.c | 8 ++++----
11
1 file changed, 6 insertions(+)
14
2 files changed, 7 insertions(+), 8 deletions(-)
15
12
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-a64.c
15
--- a/target/arm/translate-a64.c
19
+++ b/target/arm/translate-a64.c
16
+++ b/target/arm/translate-a64.c
20
@@ -XXX,XX +XXX,XX @@ static void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
17
@@ -XXX,XX +XXX,XX @@ static void handle_simd_inse(DisasContext *s, int rd, int rn,
21
s->base.is_jmp = DISAS_NORETURN;
18
write_vec_element(s, tmp, rd, dst_index, size);
19
20
tcg_temp_free_i64(tmp);
21
+
22
+ /* INS is considered a 128-bit write for SVE. */
23
+ clear_vec_high(s, true, rd);
22
}
24
}
23
25
24
-static void gen_exception_bkpt_insn(DisasContext *s, int offset,
26
25
- uint32_t syndrome)
27
@@ -XXX,XX +XXX,XX @@ static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5)
26
+static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome)
28
27
{
29
idx = extract32(imm5, 1 + size, 4 - size);
28
TCGv_i32 tcg_syn;
30
write_vec_element(s, cpu_reg(s, rn), rd, idx, size);
29
31
+
30
- gen_a64_set_pc_im(s->base.pc_next - offset);
32
+ /* INS is considered a 128-bit write for SVE. */
31
+ gen_a64_set_pc_im(s->pc_curr);
33
+ clear_vec_high(s, true, rd);
32
tcg_syn = tcg_const_i32(syndrome);
33
gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
34
tcg_temp_free_i32(tcg_syn);
35
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
36
break;
37
}
38
/* BRK */
39
- gen_exception_bkpt_insn(s, 4, syn_aa64_bkpt(imm16));
40
+ gen_exception_bkpt_insn(s, syn_aa64_bkpt(imm16));
41
break;
42
case 2:
43
if (op2_ll != 0) {
44
diff --git a/target/arm/translate.c b/target/arm/translate.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/translate.c
47
+++ b/target/arm/translate.c
48
@@ -XXX,XX +XXX,XX @@ static void gen_exception_insn(DisasContext *s, uint32_t pc, int excp,
49
s->base.is_jmp = DISAS_NORETURN;
50
}
34
}
51
35
52
-static void gen_exception_bkpt_insn(DisasContext *s, int offset, uint32_t syn)
36
/*
53
+static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
54
{
55
TCGv_i32 tcg_syn;
56
57
gen_set_condexec(s);
58
- gen_set_pc_im(s, s->base.pc_next - offset);
59
+ gen_set_pc_im(s, s->pc_curr);
60
tcg_syn = tcg_const_i32(syn);
61
gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
62
tcg_temp_free_i32(tcg_syn);
63
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
64
case 1:
65
/* bkpt */
66
ARCH(5);
67
- gen_exception_bkpt_insn(s, 4, syn_aa32_bkpt(imm16, false));
68
+ gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm16, false));
69
break;
70
case 2:
71
/* Hypervisor call (v7) */
72
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
73
{
74
int imm8 = extract32(insn, 0, 8);
75
ARCH(5);
76
- gen_exception_bkpt_insn(s, 2, syn_aa32_bkpt(imm8, true));
77
+ gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true));
78
break;
79
}
80
81
--
37
--
82
2.20.1
38
2.20.1
83
39
84
40
diff view generated by jsdifflib
New patch
[PULL 10/52] target/arm: Use bit 55 explicitly for pauth
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The psuedocode in aarch64/functions/pac/auth/Auth and
4
aarch64/functions/pac/strip/Strip always uses bit 55 for
5
extfield and do not consider if the current regime has 2 ranges.
6
7
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20200216194343.21331-2-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/pauth_helper.c | 3 ++-
14
1 file changed, 2 insertions(+), 1 deletion(-)
15
16
diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/pauth_helper.c
19
+++ b/target/arm/pauth_helper.c
20
@@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
21
22
static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
23
{
24
- uint64_t extfield = -param.select;
25
+ /* Note that bit 55 is used whether or not the regime has 2 ranges. */
26
+ uint64_t extfield = sextract64(ptr, 55, 1);
27
int bot_pac_bit = 64 - param.tsz;
28
int top_pac_bit = 64 - 8 * param.tbi;
29
30
--
31
2.20.1
32
33
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/29] target/arm/helper: zcr: Add build bug next to value range assumption
[PULL 11/52] target/arm: Fix select for aa64_va_parameters_both
1
From: Andrew Jones <drjones@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The current implementation of ZCR_ELx matches the architecture, only
3
Select should always be 0 for a regime with one range.
4
implementing the lower four bits, with the rest RAZ/WI. This puts
5
a strict limit on ARM_MAX_VQ of 16. Make sure we don't let ARM_MAX_VQ
6
grow without a corresponding update here.
7
4
8
Suggested-by: Dave Martin <Dave.Martin@arm.com>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Andrew Jones <drjones@redhat.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200216194343.21331-3-richard.henderson@linaro.org
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
9
---
14
target/arm/helper.c | 1 +
10
target/arm/helper.c | 46 +++++++++++++++++++++++----------------------
15
1 file changed, 1 insertion(+)
11
1 file changed, 24 insertions(+), 22 deletions(-)
16
12
17
diff --git a/target/arm/helper.c b/target/arm/helper.c
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
18
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper.c
15
--- a/target/arm/helper.c
20
+++ b/target/arm/helper.c
16
+++ b/target/arm/helper.c
21
@@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
17
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
22
int new_len;
18
bool tbi, tbid, epd, hpd, using16k, using64k;
23
19
int select, tsz;
24
/* Bits other than [3:0] are RAZ/WI. */
20
25
+ QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16);
21
- /*
26
raw_write(env, ri, value & 0xf);
22
- * Bit 55 is always between the two regions, and is canonical for
27
23
- * determining if address tagging is enabled.
28
/*
24
- */
25
- select = extract64(va, 55, 1);
26
-
27
if (!regime_has_2_ranges(mmu_idx)) {
28
+ select = 0;
29
tsz = extract32(tcr, 0, 6);
30
using64k = extract32(tcr, 14, 1);
31
using16k = extract32(tcr, 15, 1);
32
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
33
tbid = extract32(tcr, 29, 1);
34
}
35
epd = false;
36
- } else if (!select) {
37
- tsz = extract32(tcr, 0, 6);
38
- epd = extract32(tcr, 7, 1);
39
- using64k = extract32(tcr, 14, 1);
40
- using16k = extract32(tcr, 15, 1);
41
- tbi = extract64(tcr, 37, 1);
42
- hpd = extract64(tcr, 41, 1);
43
- tbid = extract64(tcr, 51, 1);
44
} else {
45
- int tg = extract32(tcr, 30, 2);
46
- using16k = tg == 1;
47
- using64k = tg == 3;
48
- tsz = extract32(tcr, 16, 6);
49
- epd = extract32(tcr, 23, 1);
50
- tbi = extract64(tcr, 38, 1);
51
- hpd = extract64(tcr, 42, 1);
52
- tbid = extract64(tcr, 52, 1);
53
+ /*
54
+ * Bit 55 is always between the two regions, and is canonical for
55
+ * determining if address tagging is enabled.
56
+ */
57
+ select = extract64(va, 55, 1);
58
+ if (!select) {
59
+ tsz = extract32(tcr, 0, 6);
60
+ epd = extract32(tcr, 7, 1);
61
+ using64k = extract32(tcr, 14, 1);
62
+ using16k = extract32(tcr, 15, 1);
63
+ tbi = extract64(tcr, 37, 1);
64
+ hpd = extract64(tcr, 41, 1);
65
+ tbid = extract64(tcr, 51, 1);
66
+ } else {
67
+ int tg = extract32(tcr, 30, 2);
68
+ using16k = tg == 1;
69
+ using64k = tg == 3;
70
+ tsz = extract32(tcr, 16, 6);
71
+ epd = extract32(tcr, 23, 1);
72
+ tbi = extract64(tcr, 38, 1);
73
+ hpd = extract64(tcr, 42, 1);
74
+ tbid = extract64(tcr, 52, 1);
75
+ }
76
}
77
tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */
78
tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
29
--
79
--
30
2.20.1
80
2.20.1
31
81
32
82
diff view generated by jsdifflib
[Qemu-devel] [PULL 26/29] target/arm: Use ror32 instead of open-coding the operation
[PULL 12/52] target/arm: Remove ttbr1_valid check from get_phys_addr_lpae
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The helper function is more documentary, and also already
3
Now that aa64_va_parameters_both sets select based on the number
4
handles the case of rotate by zero.
4
of ranges in the regime, the ttbr1_valid check is redundant.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190808202616.13782-5-richard.henderson@linaro.org
7
Message-id: 20200216194343.21331-4-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/translate.c | 7 ++-----
11
target/arm/helper.c | 6 +-----
12
1 file changed, 2 insertions(+), 5 deletions(-)
12
1 file changed, 1 insertion(+), 5 deletions(-)
13
13
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
16
--- a/target/arm/helper.c
17
+++ b/target/arm/translate.c
17
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
18
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
19
/* CPSR = immediate */
19
TCR *tcr = regime_tcr(env, mmu_idx);
20
val = insn & 0xff;
20
int ap, ns, xn, pxn;
21
shift = ((insn >> 8) & 0xf) * 2;
21
uint32_t el = regime_el(env, mmu_idx);
22
- if (shift)
22
- bool ttbr1_valid;
23
- val = (val >> shift) | (val << (32 - shift));
23
uint64_t descaddrmask;
24
+ val = ror32(val, shift);
24
bool aarch64 = arm_el_is_aa64(env, el);
25
i = ((insn & (1 << 22)) != 0);
25
bool guarded = false;
26
if (gen_set_psr_im(s, msr_mask(s, (insn >> 16) & 0xf, i),
26
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
27
i, val)) {
27
param = aa64_va_parameters(env, address, mmu_idx,
28
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
28
access_type != MMU_INST_FETCH);
29
/* immediate operand */
29
level = 0;
30
val = insn & 0xff;
30
- ttbr1_valid = regime_has_2_ranges(mmu_idx);
31
shift = ((insn >> 8) & 0xf) * 2;
31
addrsize = 64 - 8 * param.tbi;
32
- if (shift) {
32
inputsize = 64 - param.tsz;
33
- val = (val >> shift) | (val << (32 - shift));
33
} else {
34
- }
34
param = aa32_va_parameters(env, address, mmu_idx);
35
+ val = ror32(val, shift);
35
level = 1;
36
tmp2 = tcg_temp_new_i32();
36
- /* There is no TTBR1 for EL2 */
37
tcg_gen_movi_i32(tmp2, val);
37
- ttbr1_valid = (el != 2);
38
if (logic_cc && shift) {
38
addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32);
39
inputsize = addrsize - param.tsz;
40
}
41
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
42
if (inputsize < addrsize) {
43
target_ulong top_bits = sextract64(address, inputsize,
44
addrsize - inputsize);
45
- if (-top_bits != param.select || (param.select && !ttbr1_valid)) {
46
+ if (-top_bits != param.select) {
47
/* The gap between the two regions is a Translation fault */
48
fault_type = ARMFault_Translation;
49
goto do_fault;
39
--
50
--
40
2.20.1
51
2.20.1
41
52
42
53
diff view generated by jsdifflib
New patch
[PULL 13/52] target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
For the purpose of rebuild_hflags_a64, we do not need to compute
4
all of the va parameters, only tbi. Moreover, we can compute them
5
in a form that is more useful to storing in hflags.
6
7
This eliminates the need for aa64_va_parameter_both, so fold that
8
in to aa64_va_parameter. The remaining calls to aa64_va_parameter
9
are in get_phys_addr_lpae and in pauth_helper.c.
10
11
This reduces the total cpu consumption of aa64_va_parameter in a
12
kernel boot plus a kvm guest kernel boot from 3% to 0.5%.
13
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 20200216194343.21331-5-richard.henderson@linaro.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
target/arm/internals.h | 3 --
20
target/arm/helper.c | 68 +++++++++++++++++++++++-------------------
21
2 files changed, 37 insertions(+), 34 deletions(-)
22
23
diff --git a/target/arm/internals.h b/target/arm/internals.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/internals.h
26
+++ b/target/arm/internals.h
27
@@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters {
28
unsigned tsz : 8;
29
unsigned select : 1;
30
bool tbi : 1;
31
- bool tbid : 1;
32
bool epd : 1;
33
bool hpd : 1;
34
bool using16k : 1;
35
bool using64k : 1;
36
} ARMVAParameters;
37
38
-ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
39
- ARMMMUIdx mmu_idx);
40
ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
41
ARMMMUIdx mmu_idx, bool data);
42
43
diff --git a/target/arm/helper.c b/target/arm/helper.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/helper.c
46
+++ b/target/arm/helper.c
47
@@ -XXX,XX +XXX,XX @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
48
}
49
#endif /* !CONFIG_USER_ONLY */
50
51
-ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
52
- ARMMMUIdx mmu_idx)
53
+static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx)
54
+{
55
+ if (regime_has_2_ranges(mmu_idx)) {
56
+ return extract64(tcr, 37, 2);
57
+ } else if (mmu_idx == ARMMMUIdx_Stage2) {
58
+ return 0; /* VTCR_EL2 */
59
+ } else {
60
+ return extract32(tcr, 20, 1);
61
+ }
62
+}
63
+
64
+static int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx)
65
+{
66
+ if (regime_has_2_ranges(mmu_idx)) {
67
+ return extract64(tcr, 51, 2);
68
+ } else if (mmu_idx == ARMMMUIdx_Stage2) {
69
+ return 0; /* VTCR_EL2 */
70
+ } else {
71
+ return extract32(tcr, 29, 1);
72
+ }
73
+}
74
+
75
+ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
76
+ ARMMMUIdx mmu_idx, bool data)
77
{
78
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
79
- bool tbi, tbid, epd, hpd, using16k, using64k;
80
- int select, tsz;
81
+ bool epd, hpd, using16k, using64k;
82
+ int select, tsz, tbi;
83
84
if (!regime_has_2_ranges(mmu_idx)) {
85
select = 0;
86
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
87
using16k = extract32(tcr, 15, 1);
88
if (mmu_idx == ARMMMUIdx_Stage2) {
89
/* VTCR_EL2 */
90
- tbi = tbid = hpd = false;
91
+ hpd = false;
92
} else {
93
- tbi = extract32(tcr, 20, 1);
94
hpd = extract32(tcr, 24, 1);
95
- tbid = extract32(tcr, 29, 1);
96
}
97
epd = false;
98
} else {
99
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
100
epd = extract32(tcr, 7, 1);
101
using64k = extract32(tcr, 14, 1);
102
using16k = extract32(tcr, 15, 1);
103
- tbi = extract64(tcr, 37, 1);
104
hpd = extract64(tcr, 41, 1);
105
- tbid = extract64(tcr, 51, 1);
106
} else {
107
int tg = extract32(tcr, 30, 2);
108
using16k = tg == 1;
109
using64k = tg == 3;
110
tsz = extract32(tcr, 16, 6);
111
epd = extract32(tcr, 23, 1);
112
- tbi = extract64(tcr, 38, 1);
113
hpd = extract64(tcr, 42, 1);
114
- tbid = extract64(tcr, 52, 1);
115
}
116
}
117
tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */
118
tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
119
120
+ /* Present TBI as a composite with TBID. */
121
+ tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
122
+ if (!data) {
123
+ tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
124
+ }
125
+ tbi = (tbi >> select) & 1;
126
+
127
return (ARMVAParameters) {
128
.tsz = tsz,
129
.select = select,
130
.tbi = tbi,
131
- .tbid = tbid,
132
.epd = epd,
133
.hpd = hpd,
134
.using16k = using16k,
135
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
136
};
137
}
138
139
-ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
140
- ARMMMUIdx mmu_idx, bool data)
141
-{
142
- ARMVAParameters ret = aa64_va_parameters_both(env, va, mmu_idx);
143
-
144
- /* Present TBI as a composite with TBID. */
145
- ret.tbi &= (data || !ret.tbid);
146
- return ret;
147
-}
148
-
149
#ifndef CONFIG_USER_ONLY
150
static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
151
ARMMMUIdx mmu_idx)
152
@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
153
{
154
uint32_t flags = rebuild_hflags_aprofile(env);
155
ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
156
- ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1);
157
+ uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
158
uint64_t sctlr;
159
int tbii, tbid;
160
161
flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
162
163
/* Get control bits for tagged addresses. */
164
- if (regime_has_2_ranges(mmu_idx)) {
165
- ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1);
166
- tbid = (p1.tbi << 1) | p0.tbi;
167
- tbii = tbid & ~((p1.tbid << 1) | p0.tbid);
168
- } else {
169
- tbid = p0.tbi;
170
- tbii = tbid & !p0.tbid;
171
- }
172
+ tbid = aa64_va_parameter_tbi(tcr, mmu_idx);
173
+ tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx);
174
175
flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii);
176
flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid);
177
--
178
2.20.1
179
180
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/29] target/arm: Fix routing of singlestep exceptions
[PULL 14/52] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers
1
When generating an architectural single-step exception we were
1
Enforce a convention that an isar_feature function that tests a
2
routing it to the "default exception level", which is to say
2
32-bit ID register always has _aa32_ in its name, and one that
3
the same exception level we execute at except that EL0 exceptions
3
tests a 64-bit ID register always has _aa64_ in its name.
4
go to EL1. This is incorrect because the debug exception level
4
We already follow this except for three cases: thumb_div,
5
can be configured by the guest for situations such as single
5
arm_div and jazelle, which all need _aa32_ adding.
6
stepping of EL0 and EL1 code by EL2.
7
6
8
We have to track the target debug exception level in the TB
7
(As noted in the comment, isar_feature_aa32_fp16_arith()
9
flags, because it is dependent on CPU state like HCR_EL2.TGE
8
is an exception in that it currently tests ID_AA64PFR0_EL1,
10
and MDCR_EL2.TDE. (That we were previously calling the
9
but will switch to MVFR1 once we've properly implemented
11
arm_debug_target_el() function to determine dc->ss_same_el
10
FP16 for AArch32.)
12
is itself a bug, though one that would only have manifested
13
as incorrect syndrome information.) Since we are out of TB
14
flag bits unless we want to expand into the cs_base field,
15
we share some bits with the M-profile only HANDLER and
16
STACKCHECK bits, since only A-profile has this singlestep.
17
11
18
Fixes: https://bugs.launchpad.net/qemu/+bug/1838913
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15
Message-id: 20200214175116.9164-2-peter.maydell@linaro.org
21
Tested-by: Alex Bennée <alex.bennee@linaro.org>
22
Message-id: 20190805130952.4415-3-peter.maydell@linaro.org
23
---
16
---
24
target/arm/cpu.h | 5 +++++
17
target/arm/cpu.h | 13 ++++++++++---
25
target/arm/translate.h | 15 +++++++++++----
18
target/arm/internals.h | 2 +-
26
target/arm/helper.c | 6 ++++++
19
linux-user/elfload.c | 4 ++--
27
target/arm/translate-a64.c | 2 +-
20
target/arm/cpu.c | 6 ++++--
28
target/arm/translate.c | 4 +++-
21
target/arm/helper.c | 2 +-
29
5 files changed, 26 insertions(+), 6 deletions(-)
22
target/arm/translate.c | 6 +++---
23
6 files changed, 21 insertions(+), 12 deletions(-)
30
24
31
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
25
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
32
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/cpu.h
27
--- a/target/arm/cpu.h
34
+++ b/target/arm/cpu.h
28
+++ b/target/arm/cpu.h
35
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1)
29
@@ -XXX,XX +XXX,XX @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
36
/* Target EL if we take a floating-point-disabled exception */
30
/* Shared between translate-sve.c and sve_helper.c. */
37
FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2)
31
extern const uint64_t pred_esz_masks[4];
38
FIELD(TBFLAG_ANY, BE_DATA, 23, 1)
32
39
+/*
33
+/*
40
+ * For A-profile only, target EL for debug exceptions.
34
+ * Naming convention for isar_feature functions:
41
+ * Note that this overlaps with the M-profile-only HANDLER and STACKCHECK bits.
35
+ * Functions which test 32-bit ID registers should have _aa32_ in
36
+ * their name. Functions which test 64-bit ID registers should have
37
+ * _aa64_ in their name.
42
+ */
38
+ */
43
+FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2)
39
+
44
40
/*
45
/* Bit usage when in AArch32 state: */
41
* 32-bit feature tests via id registers.
46
FIELD(TBFLAG_A32, THUMB, 0, 1)
42
*/
47
diff --git a/target/arm/translate.h b/target/arm/translate.h
43
-static inline bool isar_feature_thumb_div(const ARMISARegisters *id)
44
+static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
45
{
46
return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
47
}
48
49
-static inline bool isar_feature_arm_div(const ARMISARegisters *id)
50
+static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
51
{
52
return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
53
}
54
55
-static inline bool isar_feature_jazelle(const ARMISARegisters *id)
56
+static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
57
{
58
return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
59
}
60
diff --git a/target/arm/internals.h b/target/arm/internals.h
48
index XXXXXXX..XXXXXXX 100644
61
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/translate.h
62
--- a/target/arm/internals.h
50
+++ b/target/arm/translate.h
63
+++ b/target/arm/internals.h
51
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
64
@@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
52
uint32_t svc_imm;
65
if ((features >> ARM_FEATURE_THUMB2) & 1) {
53
int aarch64;
66
valid |= CPSR_IT;
54
int current_el;
67
}
55
+ /* Debug target exception level for single-step exceptions */
68
- if (isar_feature_jazelle(id)) {
56
+ int debug_target_el;
69
+ if (isar_feature_aa32_jazelle(id)) {
57
GHashTable *cp_regs;
70
valid |= CPSR_J;
58
uint64_t features; /* CPU features bits */
71
}
59
/* Because unallocated encodings generate different exception syndrome
72
if (isar_feature_aa32_pan(id)) {
60
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
73
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
61
* ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
74
index XXXXXXX..XXXXXXX 100644
62
*/
75
--- a/linux-user/elfload.c
63
bool is_ldex;
76
+++ b/linux-user/elfload.c
64
- /* True if a single-step exception will be taken to the current EL */
77
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
65
- bool ss_same_el;
78
GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3);
66
/* True if v8.3-PAuth is active. */
79
GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS);
67
bool pauth_active;
80
GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4);
68
/* True with v8.5-BTI and SCTLR_ELx.BT* set. */
81
- GET_FEATURE_ID(arm_div, ARM_HWCAP_ARM_IDIVA);
69
@@ -XXX,XX +XXX,XX @@ static inline void gen_exception(int excp, uint32_t syndrome,
82
- GET_FEATURE_ID(thumb_div, ARM_HWCAP_ARM_IDIVT);
70
/* Generate an architectural singlestep exception */
83
+ GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA);
71
static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
84
+ GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT);
72
{
85
/* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.c.
73
- gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, isv, ex),
86
* Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of
74
- default_exception_el(s));
87
* ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated
75
+ bool same_el = (s->debug_target_el == s->current_el);
88
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
76
+
89
index XXXXXXX..XXXXXXX 100644
77
+ /*
90
--- a/target/arm/cpu.c
78
+ * If singlestep is targeting a lower EL than the current one,
91
+++ b/target/arm/cpu.c
79
+ * then s->ss_active must be false and we can never get here.
92
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
80
+ */
93
* Presence of EL2 itself is ARM_FEATURE_EL2, and of the
81
+ assert(s->debug_target_el >= s->current_el);
94
* Security Extensions is ARM_FEATURE_EL3.
82
+
95
*/
83
+ gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target_el);
96
- assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu));
84
}
97
+ assert(!tcg_enabled() || no_aa32 ||
85
98
+ cpu_isar_feature(aa32_arm_div, cpu));
86
/*
99
set_feature(env, ARM_FEATURE_LPAE);
100
set_feature(env, ARM_FEATURE_V7);
101
}
102
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
103
if (arm_feature(env, ARM_FEATURE_V6)) {
104
set_feature(env, ARM_FEATURE_V5);
105
if (!arm_feature(env, ARM_FEATURE_M)) {
106
- assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle, cpu));
107
+ assert(!tcg_enabled() || no_aa32 ||
108
+ cpu_isar_feature(aa32_jazelle, cpu));
109
set_feature(env, ARM_FEATURE_AUXCR);
110
}
111
}
87
diff --git a/target/arm/helper.c b/target/arm/helper.c
112
diff --git a/target/arm/helper.c b/target/arm/helper.c
88
index XXXXXXX..XXXXXXX 100644
113
index XXXXXXX..XXXXXXX 100644
89
--- a/target/arm/helper.c
114
--- a/target/arm/helper.c
90
+++ b/target/arm/helper.c
115
+++ b/target/arm/helper.c
91
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
116
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
92
}
117
if (arm_feature(env, ARM_FEATURE_LPAE)) {
118
define_arm_cp_regs(cpu, lpae_cp_reginfo);
93
}
119
}
94
120
- if (cpu_isar_feature(jazelle, cpu)) {
95
+ if (!arm_feature(env, ARM_FEATURE_M)) {
121
+ if (cpu_isar_feature(aa32_jazelle, cpu)) {
96
+ int target_el = arm_debug_target_el(env);
122
define_arm_cp_regs(cpu, jazelle_regs);
97
+
123
}
98
+ flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, target_el);
124
/* Slightly awkwardly, the OMAP and StrongARM cores need all of
99
+ }
100
+
101
*pflags = flags;
102
*cs_base = 0;
103
}
104
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/target/arm/translate-a64.c
107
+++ b/target/arm/translate-a64.c
108
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
109
dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE);
110
dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS);
111
dc->is_ldex = false;
112
- dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el);
113
+ dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL);
114
115
/* Bound the number of insns to execute to those left on the page. */
116
bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
117
diff --git a/target/arm/translate.c b/target/arm/translate.c
125
diff --git a/target/arm/translate.c b/target/arm/translate.c
118
index XXXXXXX..XXXXXXX 100644
126
index XXXXXXX..XXXXXXX 100644
119
--- a/target/arm/translate.c
127
--- a/target/arm/translate.c
120
+++ b/target/arm/translate.c
128
+++ b/target/arm/translate.c
121
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
129
@@ -XXX,XX +XXX,XX @@
122
dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE);
130
#define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5)
123
dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS);
131
/* currently all emulated v5 cores are also v5TE, so don't bother */
124
dc->is_ldex = false;
132
#define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5)
125
- dc->ss_same_el = false; /* Can't be true since EL_d must be AArch64 */
133
-#define ENABLE_ARCH_5J dc_isar_feature(jazelle, s)
126
+ if (!arm_feature(env, ARM_FEATURE_M)) {
134
+#define ENABLE_ARCH_5J dc_isar_feature(aa32_jazelle, s)
127
+ dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL);
135
#define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6)
128
+ }
136
#define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K)
129
137
#define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2)
130
dc->page_start = dc->base.pc_first & TARGET_PAGE_MASK;
138
@@ -XXX,XX +XXX,XX @@ static bool op_div(DisasContext *s, arg_rrr *a, bool u)
139
TCGv_i32 t1, t2;
140
141
if (s->thumb
142
- ? !dc_isar_feature(thumb_div, s)
143
- : !dc_isar_feature(arm_div, s)) {
144
+ ? !dc_isar_feature(aa32_thumb_div, s)
145
+ : !dc_isar_feature(aa32_arm_div, s)) {
146
return false;
147
}
131
148
132
--
149
--
133
2.20.1
150
2.20.1
134
151
135
152
diff view generated by jsdifflib
New patch
[PULL 15/52] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan
1
In take_aarch32_exception(), we know we are dealing with a CPU that
2
has AArch32, so the right isar_feature test is aa32_pan, not aa64_pan.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200214175116.9164-3-peter.maydell@linaro.org
7
---
8
target/arm/helper.c | 2 +-
9
1 file changed, 1 insertion(+), 1 deletion(-)
10
11
diff --git a/target/arm/helper.c b/target/arm/helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/helper.c
14
+++ b/target/arm/helper.c
15
@@ -XXX,XX +XXX,XX @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
16
env->elr_el[2] = env->regs[15];
17
} else {
18
/* CPSR.PAN is normally preserved preserved unless... */
19
- if (cpu_isar_feature(aa64_pan, env_archcpu(env))) {
20
+ if (cpu_isar_feature(aa32_pan, env_archcpu(env))) {
21
switch (new_el) {
22
case 3:
23
if (!arm_is_secure_below_el3(env)) {
24
--
25
2.20.1
26
27
diff view generated by jsdifflib
New patch
[PULL 16/52] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions
1
Our current usage of the isar_feature feature tests almost always
2
uses an _aa32_ test when the code path is known to be AArch32
3
specific and an _aa64_ test when the code path is known to be
4
AArch64 specific. There is just one exception: in the vfp_set_fpscr
5
helper we check aa64_fp16 to determine whether the FZ16 bit in
6
the FP(S)CR exists, but this code is also used for AArch32.
7
There are other places in future where we're likely to want
8
a general "does this feature exist for either AArch32 or
9
AArch64" check (typically where architecturally the feature exists
10
for both CPU states if it exists at all, but the CPU might be
11
AArch32-only or AArch64-only, and so only have one set of ID
12
registers).
1
13
14
Introduce a new category of isar_feature_* functions:
15
isar_feature_any_foo() should be tested when what we want to
16
know is "does this feature exist for either AArch32 or AArch64",
17
and always returns the logical OR of isar_feature_aa32_foo()
18
and isar_feature_aa64_foo().
19
20
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
21
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Message-id: 20200214175116.9164-4-peter.maydell@linaro.org
24
---
25
target/arm/cpu.h | 19 ++++++++++++++++++-
26
target/arm/vfp_helper.c | 2 +-
27
2 files changed, 19 insertions(+), 2 deletions(-)
28
29
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/cpu.h
32
+++ b/target/arm/cpu.h
33
@@ -XXX,XX +XXX,XX @@ extern const uint64_t pred_esz_masks[4];
34
* Naming convention for isar_feature functions:
35
* Functions which test 32-bit ID registers should have _aa32_ in
36
* their name. Functions which test 64-bit ID registers should have
37
- * _aa64_ in their name.
38
+ * _aa64_ in their name. These must only be used in code where we
39
+ * know for certain that the CPU has AArch32 or AArch64 respectively
40
+ * or where the correct answer for a CPU which doesn't implement that
41
+ * CPU state is "false" (eg when generating A32 or A64 code, if adding
42
+ * system registers that are specific to that CPU state, for "should
43
+ * we let this system register bit be set" tests where the 32-bit
44
+ * flavour of the register doesn't have the bit, and so on).
45
+ * Functions which simply ask "does this feature exist at all" have
46
+ * _any_ in their name, and always return the logical OR of the _aa64_
47
+ * and the _aa32_ function.
48
*/
49
50
/*
51
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
52
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
53
}
54
55
+/*
56
+ * Feature tests for "does this exist in either 32-bit or 64-bit?"
57
+ */
58
+static inline bool isar_feature_any_fp16(const ARMISARegisters *id)
59
+{
60
+ return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id);
61
+}
62
+
63
/*
64
* Forward to the above feature tests given an ARMCPU pointer.
65
*/
66
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/arm/vfp_helper.c
69
+++ b/target/arm/vfp_helper.c
70
@@ -XXX,XX +XXX,XX @@ uint32_t vfp_get_fpscr(CPUARMState *env)
71
void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
72
{
73
/* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
74
- if (!cpu_isar_feature(aa64_fp16, env_archcpu(env))) {
75
+ if (!cpu_isar_feature(any_fp16, env_archcpu(env))) {
76
val &= ~FPCR_FZ16;
77
}
78
79
--
80
2.20.1
81
82
diff view generated by jsdifflib
New patch
[PULL 17/52] target/arm: Define and use any_predinv isar_feature test
1
Instead of open-coding "ARM_FEATURE_AARCH64 ? aa64_predinv: aa32_predinv",
2
define and use an any_predinv isar_feature test function.
1
3
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20200214175116.9164-5-peter.maydell@linaro.org
8
---
9
target/arm/cpu.h | 5 +++++
10
target/arm/helper.c | 9 +--------
11
2 files changed, 6 insertions(+), 8 deletions(-)
12
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.h
16
+++ b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_fp16(const ARMISARegisters *id)
18
return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id);
19
}
20
21
+static inline bool isar_feature_any_predinv(const ARMISARegisters *id)
22
+{
23
+ return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id);
24
+}
25
+
26
/*
27
* Forward to the above feature tests given an ARMCPU pointer.
28
*/
29
diff --git a/target/arm/helper.c b/target/arm/helper.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/helper.c
32
+++ b/target/arm/helper.c
33
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
34
#endif /*CONFIG_USER_ONLY*/
35
#endif
36
37
- /*
38
- * While all v8.0 cpus support aarch64, QEMU does have configurations
39
- * that do not set ID_AA64ISAR1, e.g. user-only qemu-arm -cpu max,
40
- * which will set ID_ISAR6.
41
- */
42
- if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
43
- ? cpu_isar_feature(aa64_predinv, cpu)
44
- : cpu_isar_feature(aa32_predinv, cpu)) {
45
+ if (cpu_isar_feature(any_predinv, cpu)) {
46
define_arm_cp_regs(cpu, predinv_reginfo);
47
}
48
49
--
50
2.20.1
51
52
diff view generated by jsdifflib
New patch
[PULL 18/52] target/arm: Factor out PMU register definitions
1
1
Pull the code that defines the various PMU registers out
2
into its own function, matching the pattern we have
3
already for the debug registers.
4
5
Apart from one style fix to a multi-line comment, this
6
is purely movement of code with no changes to it.
7
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20200214175116.9164-6-peter.maydell@linaro.org
12
---
13
target/arm/helper.c | 158 +++++++++++++++++++++++---------------------
14
1 file changed, 82 insertions(+), 76 deletions(-)
15
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
19
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
21
}
22
}
23
24
+static void define_pmu_regs(ARMCPU *cpu)
25
+{
26
+ /*
27
+ * v7 performance monitor control register: same implementor
28
+ * field as main ID register, and we implement four counters in
29
+ * addition to the cycle count register.
30
+ */
31
+ unsigned int i, pmcrn = 4;
32
+ ARMCPRegInfo pmcr = {
33
+ .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
34
+ .access = PL0_RW,
35
+ .type = ARM_CP_IO | ARM_CP_ALIAS,
36
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
37
+ .accessfn = pmreg_access, .writefn = pmcr_write,
38
+ .raw_writefn = raw_write,
39
+ };
40
+ ARMCPRegInfo pmcr64 = {
41
+ .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
42
+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
43
+ .access = PL0_RW, .accessfn = pmreg_access,
44
+ .type = ARM_CP_IO,
45
+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
46
+ .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT),
47
+ .writefn = pmcr_write, .raw_writefn = raw_write,
48
+ };
49
+ define_one_arm_cp_reg(cpu, &pmcr);
50
+ define_one_arm_cp_reg(cpu, &pmcr64);
51
+ for (i = 0; i < pmcrn; i++) {
52
+ char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i);
53
+ char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i);
54
+ char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i);
55
+ char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i);
56
+ ARMCPRegInfo pmev_regs[] = {
57
+ { .name = pmevcntr_name, .cp = 15, .crn = 14,
58
+ .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
59
+ .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
60
+ .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
61
+ .accessfn = pmreg_access },
62
+ { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
63
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
64
+ .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
65
+ .type = ARM_CP_IO,
66
+ .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
67
+ .raw_readfn = pmevcntr_rawread,
68
+ .raw_writefn = pmevcntr_rawwrite },
69
+ { .name = pmevtyper_name, .cp = 15, .crn = 14,
70
+ .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
71
+ .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
72
+ .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
73
+ .accessfn = pmreg_access },
74
+ { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,
75
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),
76
+ .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
77
+ .type = ARM_CP_IO,
78
+ .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
79
+ .raw_writefn = pmevtyper_rawwrite },
80
+ REGINFO_SENTINEL
81
+ };
82
+ define_arm_cp_regs(cpu, pmev_regs);
83
+ g_free(pmevcntr_name);
84
+ g_free(pmevcntr_el0_name);
85
+ g_free(pmevtyper_name);
86
+ g_free(pmevtyper_el0_name);
87
+ }
88
+ if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
89
+ FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) {
90
+ ARMCPRegInfo v81_pmu_regs[] = {
91
+ { .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
92
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
93
+ .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
94
+ .resetvalue = extract64(cpu->pmceid0, 32, 32) },
95
+ { .name = "PMCEID3", .state = ARM_CP_STATE_AA32,
96
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
97
+ .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
98
+ .resetvalue = extract64(cpu->pmceid1, 32, 32) },
99
+ REGINFO_SENTINEL
100
+ };
101
+ define_arm_cp_regs(cpu, v81_pmu_regs);
102
+ }
103
+}
104
+
105
/* We don't know until after realize whether there's a GICv3
106
* attached, and that is what registers the gicv3 sysregs.
107
* So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
108
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
109
define_arm_cp_regs(cpu, pmovsset_cp_reginfo);
110
}
111
if (arm_feature(env, ARM_FEATURE_V7)) {
112
- /* v7 performance monitor control register: same implementor
113
- * field as main ID register, and we implement four counters in
114
- * addition to the cycle count register.
115
- */
116
- unsigned int i, pmcrn = 4;
117
- ARMCPRegInfo pmcr = {
118
- .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
119
- .access = PL0_RW,
120
- .type = ARM_CP_IO | ARM_CP_ALIAS,
121
- .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
122
- .accessfn = pmreg_access, .writefn = pmcr_write,
123
- .raw_writefn = raw_write,
124
- };
125
- ARMCPRegInfo pmcr64 = {
126
- .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
127
- .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
128
- .access = PL0_RW, .accessfn = pmreg_access,
129
- .type = ARM_CP_IO,
130
- .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
131
- .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT),
132
- .writefn = pmcr_write, .raw_writefn = raw_write,
133
- };
134
- define_one_arm_cp_reg(cpu, &pmcr);
135
- define_one_arm_cp_reg(cpu, &pmcr64);
136
- for (i = 0; i < pmcrn; i++) {
137
- char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i);
138
- char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i);
139
- char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i);
140
- char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i);
141
- ARMCPRegInfo pmev_regs[] = {
142
- { .name = pmevcntr_name, .cp = 15, .crn = 14,
143
- .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
144
- .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
145
- .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
146
- .accessfn = pmreg_access },
147
- { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
148
- .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
149
- .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
150
- .type = ARM_CP_IO,
151
- .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
152
- .raw_readfn = pmevcntr_rawread,
153
- .raw_writefn = pmevcntr_rawwrite },
154
- { .name = pmevtyper_name, .cp = 15, .crn = 14,
155
- .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
156
- .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
157
- .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
158
- .accessfn = pmreg_access },
159
- { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,
160
- .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),
161
- .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
162
- .type = ARM_CP_IO,
163
- .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
164
- .raw_writefn = pmevtyper_rawwrite },
165
- REGINFO_SENTINEL
166
- };
167
- define_arm_cp_regs(cpu, pmev_regs);
168
- g_free(pmevcntr_name);
169
- g_free(pmevcntr_el0_name);
170
- g_free(pmevtyper_name);
171
- g_free(pmevtyper_el0_name);
172
- }
173
ARMCPRegInfo clidr = {
174
.name = "CLIDR", .state = ARM_CP_STATE_BOTH,
175
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
176
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
177
define_one_arm_cp_reg(cpu, &clidr);
178
define_arm_cp_regs(cpu, v7_cp_reginfo);
179
define_debug_regs(cpu);
180
+ define_pmu_regs(cpu);
181
} else {
182
define_arm_cp_regs(cpu, not_v7_cp_reginfo);
183
}
184
- if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
185
- FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) {
186
- ARMCPRegInfo v81_pmu_regs[] = {
187
- { .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
188
- .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
189
- .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
190
- .resetvalue = extract64(cpu->pmceid0, 32, 32) },
191
- { .name = "PMCEID3", .state = ARM_CP_STATE_AA32,
192
- .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
193
- .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
194
- .resetvalue = extract64(cpu->pmceid1, 32, 32) },
195
- REGINFO_SENTINEL
196
- };
197
- define_arm_cp_regs(cpu, v81_pmu_regs);
198
- }
199
if (arm_feature(env, ARM_FEATURE_V8)) {
200
/* AArch64 ID registers, which all have impdef reset values.
201
* Note that within the ID register ranges the unused slots
202
--
203
2.20.1
204
205
diff view generated by jsdifflib
New patch
[PULL 19/52] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1
1
Add FIELD() definitions for the ID_AA64DFR0_EL1 and use them
2
where we currently have hard-coded bit values.
1
3
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20200214175116.9164-7-peter.maydell@linaro.org
8
---
9
target/arm/cpu.h | 10 ++++++++++
10
target/arm/cpu.c | 2 +-
11
target/arm/helper.c | 6 +++---
12
3 files changed, 14 insertions(+), 4 deletions(-)
13
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.h
17
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR2, BBM, 52, 4)
19
FIELD(ID_AA64MMFR2, EVT, 56, 4)
20
FIELD(ID_AA64MMFR2, E0PD, 60, 4)
21
22
+FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
23
+FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
24
+FIELD(ID_AA64DFR0, PMUVER, 8, 4)
25
+FIELD(ID_AA64DFR0, BRPS, 12, 4)
26
+FIELD(ID_AA64DFR0, WRPS, 20, 4)
27
+FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
28
+FIELD(ID_AA64DFR0, PMSVER, 32, 4)
29
+FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
30
+FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
31
+
32
FIELD(ID_DFR0, COPDBG, 0, 4)
33
FIELD(ID_DFR0, COPSDBG, 4, 4)
34
FIELD(ID_DFR0, MMAPDBG, 8, 4)
35
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/cpu.c
38
+++ b/target/arm/cpu.c
39
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
40
cpu);
41
#endif
42
} else {
43
- cpu->id_aa64dfr0 &= ~0xf00;
44
+ cpu->id_aa64dfr0 = FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
45
cpu->id_dfr0 &= ~(0xf << 24);
46
cpu->pmceid0 = 0;
47
cpu->pmceid1 = 0;
48
diff --git a/target/arm/helper.c b/target/arm/helper.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/helper.c
51
+++ b/target/arm/helper.c
52
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
53
* check that if they both exist then they agree.
54
*/
55
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
56
- assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
57
- assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
58
- assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
59
+ assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, BRPS) == brps);
60
+ assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, WRPS) == wrps);
61
+ assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) == ctx_cmps);
62
}
63
64
define_one_arm_cp_reg(cpu, &dbgdidr);
65
--
66
2.20.1
67
68
diff view generated by jsdifflib
New patch
[PULL 20/52] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field
1
We already define FIELD macros for ID_DFR0, so use them in the
2
one place where we're doing direct bit value manipulation.
1
3
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20200214175116.9164-8-peter.maydell@linaro.org
8
---
9
target/arm/cpu.c | 2 +-
10
1 file changed, 1 insertion(+), 1 deletion(-)
11
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
17
#endif
18
} else {
19
cpu->id_aa64dfr0 = FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
20
- cpu->id_dfr0 &= ~(0xf << 24);
21
+ cpu->id_dfr0 = FIELD_DP32(cpu->id_dfr0, ID_DFR0, PERFMON, 0);
22
cpu->pmceid0 = 0;
23
cpu->pmceid1 = 0;
24
}
25
--
26
2.20.1
27
28
diff view generated by jsdifflib
New patch
[PULL 21/52] target/arm: Define an aa32_pmu_8_1 isar feature test function
1
1
Instead of open-coding a check on the ID_DFR0 PerfMon ID register
2
field, create a standardly-named isar_feature for "does AArch32 have
3
a v8.1 PMUv3" and use it.
4
5
This entails moving the id_dfr0 field into the ARMISARegisters struct.
6
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20200214175116.9164-9-peter.maydell@linaro.org
10
---
11
target/arm/cpu.h | 9 ++++++++-
12
hw/intc/armv7m_nvic.c | 2 +-
13
target/arm/cpu.c | 28 ++++++++++++++--------------
14
target/arm/cpu64.c | 6 +++---
15
target/arm/helper.c | 5 ++---
16
5 files changed, 28 insertions(+), 22 deletions(-)
17
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.h
21
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
23
uint32_t mvfr0;
24
uint32_t mvfr1;
25
uint32_t mvfr2;
26
+ uint32_t id_dfr0;
27
uint64_t id_aa64isar0;
28
uint64_t id_aa64isar1;
29
uint64_t id_aa64pfr0;
30
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
31
uint32_t reset_sctlr;
32
uint32_t id_pfr0;
33
uint32_t id_pfr1;
34
- uint32_t id_dfr0;
35
uint64_t pmceid0;
36
uint64_t pmceid1;
37
uint32_t id_afr0;
38
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
39
return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2;
40
}
41
42
+static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id)
43
+{
44
+ /* 0xf means "non-standard IMPDEF PMU" */
45
+ return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
46
+ FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
47
+}
48
+
49
/*
50
* 64-bit feature tests via id registers.
51
*/
52
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/intc/armv7m_nvic.c
55
+++ b/hw/intc/armv7m_nvic.c
56
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
57
case 0xd44: /* PFR1. */
58
return cpu->id_pfr1;
59
case 0xd48: /* DFR0. */
60
- return cpu->id_dfr0;
61
+ return cpu->isar.id_dfr0;
62
case 0xd4c: /* AFR0. */
63
return cpu->id_afr0;
64
case 0xd50: /* MMFR0. */
65
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/target/arm/cpu.c
68
+++ b/target/arm/cpu.c
69
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
70
#endif
71
} else {
72
cpu->id_aa64dfr0 = FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
73
- cpu->id_dfr0 = FIELD_DP32(cpu->id_dfr0, ID_DFR0, PERFMON, 0);
74
+ cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0);
75
cpu->pmceid0 = 0;
76
cpu->pmceid1 = 0;
77
}
78
@@ -XXX,XX +XXX,XX @@ static void arm1136_r2_initfn(Object *obj)
79
cpu->reset_sctlr = 0x00050078;
80
cpu->id_pfr0 = 0x111;
81
cpu->id_pfr1 = 0x1;
82
- cpu->id_dfr0 = 0x2;
83
+ cpu->isar.id_dfr0 = 0x2;
84
cpu->id_afr0 = 0x3;
85
cpu->id_mmfr0 = 0x01130003;
86
cpu->id_mmfr1 = 0x10030302;
87
@@ -XXX,XX +XXX,XX @@ static void arm1136_initfn(Object *obj)
88
cpu->reset_sctlr = 0x00050078;
89
cpu->id_pfr0 = 0x111;
90
cpu->id_pfr1 = 0x1;
91
- cpu->id_dfr0 = 0x2;
92
+ cpu->isar.id_dfr0 = 0x2;
93
cpu->id_afr0 = 0x3;
94
cpu->id_mmfr0 = 0x01130003;
95
cpu->id_mmfr1 = 0x10030302;
96
@@ -XXX,XX +XXX,XX @@ static void arm1176_initfn(Object *obj)
97
cpu->reset_sctlr = 0x00050078;
98
cpu->id_pfr0 = 0x111;
99
cpu->id_pfr1 = 0x11;
100
- cpu->id_dfr0 = 0x33;
101
+ cpu->isar.id_dfr0 = 0x33;
102
cpu->id_afr0 = 0;
103
cpu->id_mmfr0 = 0x01130003;
104
cpu->id_mmfr1 = 0x10030302;
105
@@ -XXX,XX +XXX,XX @@ static void arm11mpcore_initfn(Object *obj)
106
cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
107
cpu->id_pfr0 = 0x111;
108
cpu->id_pfr1 = 0x1;
109
- cpu->id_dfr0 = 0;
110
+ cpu->isar.id_dfr0 = 0;
111
cpu->id_afr0 = 0x2;
112
cpu->id_mmfr0 = 0x01100103;
113
cpu->id_mmfr1 = 0x10020302;
114
@@ -XXX,XX +XXX,XX @@ static void cortex_m3_initfn(Object *obj)
115
cpu->pmsav7_dregion = 8;
116
cpu->id_pfr0 = 0x00000030;
117
cpu->id_pfr1 = 0x00000200;
118
- cpu->id_dfr0 = 0x00100000;
119
+ cpu->isar.id_dfr0 = 0x00100000;
120
cpu->id_afr0 = 0x00000000;
121
cpu->id_mmfr0 = 0x00000030;
122
cpu->id_mmfr1 = 0x00000000;
123
@@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj)
124
cpu->isar.mvfr2 = 0x00000000;
125
cpu->id_pfr0 = 0x00000030;
126
cpu->id_pfr1 = 0x00000200;
127
- cpu->id_dfr0 = 0x00100000;
128
+ cpu->isar.id_dfr0 = 0x00100000;
129
cpu->id_afr0 = 0x00000000;
130
cpu->id_mmfr0 = 0x00000030;
131
cpu->id_mmfr1 = 0x00000000;
132
@@ -XXX,XX +XXX,XX @@ static void cortex_m7_initfn(Object *obj)
133
cpu->isar.mvfr2 = 0x00000040;
134
cpu->id_pfr0 = 0x00000030;
135
cpu->id_pfr1 = 0x00000200;
136
- cpu->id_dfr0 = 0x00100000;
137
+ cpu->isar.id_dfr0 = 0x00100000;
138
cpu->id_afr0 = 0x00000000;
139
cpu->id_mmfr0 = 0x00100030;
140
cpu->id_mmfr1 = 0x00000000;
141
@@ -XXX,XX +XXX,XX @@ static void cortex_m33_initfn(Object *obj)
142
cpu->isar.mvfr2 = 0x00000040;
143
cpu->id_pfr0 = 0x00000030;
144
cpu->id_pfr1 = 0x00000210;
145
- cpu->id_dfr0 = 0x00200000;
146
+ cpu->isar.id_dfr0 = 0x00200000;
147
cpu->id_afr0 = 0x00000000;
148
cpu->id_mmfr0 = 0x00101F40;
149
cpu->id_mmfr1 = 0x00000000;
150
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
151
cpu->midr = 0x411fc153; /* r1p3 */
152
cpu->id_pfr0 = 0x0131;
153
cpu->id_pfr1 = 0x001;
154
- cpu->id_dfr0 = 0x010400;
155
+ cpu->isar.id_dfr0 = 0x010400;
156
cpu->id_afr0 = 0x0;
157
cpu->id_mmfr0 = 0x0210030;
158
cpu->id_mmfr1 = 0x00000000;
159
@@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj)
160
cpu->reset_sctlr = 0x00c50078;
161
cpu->id_pfr0 = 0x1031;
162
cpu->id_pfr1 = 0x11;
163
- cpu->id_dfr0 = 0x400;
164
+ cpu->isar.id_dfr0 = 0x400;
165
cpu->id_afr0 = 0;
166
cpu->id_mmfr0 = 0x31100003;
167
cpu->id_mmfr1 = 0x20000000;
168
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
169
cpu->reset_sctlr = 0x00c50078;
170
cpu->id_pfr0 = 0x1031;
171
cpu->id_pfr1 = 0x11;
172
- cpu->id_dfr0 = 0x000;
173
+ cpu->isar.id_dfr0 = 0x000;
174
cpu->id_afr0 = 0;
175
cpu->id_mmfr0 = 0x00100103;
176
cpu->id_mmfr1 = 0x20000000;
177
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
178
cpu->reset_sctlr = 0x00c50078;
179
cpu->id_pfr0 = 0x00001131;
180
cpu->id_pfr1 = 0x00011011;
181
- cpu->id_dfr0 = 0x02010555;
182
+ cpu->isar.id_dfr0 = 0x02010555;
183
cpu->id_afr0 = 0x00000000;
184
cpu->id_mmfr0 = 0x10101105;
185
cpu->id_mmfr1 = 0x40000000;
186
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
187
cpu->reset_sctlr = 0x00c50078;
188
cpu->id_pfr0 = 0x00001131;
189
cpu->id_pfr1 = 0x00011011;
190
- cpu->id_dfr0 = 0x02010555;
191
+ cpu->isar.id_dfr0 = 0x02010555;
192
cpu->id_afr0 = 0x00000000;
193
cpu->id_mmfr0 = 0x10201105;
194
cpu->id_mmfr1 = 0x20000000;
195
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
196
index XXXXXXX..XXXXXXX 100644
197
--- a/target/arm/cpu64.c
198
+++ b/target/arm/cpu64.c
199
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
200
cpu->reset_sctlr = 0x00c50838;
201
cpu->id_pfr0 = 0x00000131;
202
cpu->id_pfr1 = 0x00011011;
203
- cpu->id_dfr0 = 0x03010066;
204
+ cpu->isar.id_dfr0 = 0x03010066;
205
cpu->id_afr0 = 0x00000000;
206
cpu->id_mmfr0 = 0x10101105;
207
cpu->id_mmfr1 = 0x40000000;
208
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
209
cpu->reset_sctlr = 0x00c50838;
210
cpu->id_pfr0 = 0x00000131;
211
cpu->id_pfr1 = 0x00011011;
212
- cpu->id_dfr0 = 0x03010066;
213
+ cpu->isar.id_dfr0 = 0x03010066;
214
cpu->id_afr0 = 0x00000000;
215
cpu->id_mmfr0 = 0x10101105;
216
cpu->id_mmfr1 = 0x40000000;
217
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
218
cpu->reset_sctlr = 0x00c50838;
219
cpu->id_pfr0 = 0x00000131;
220
cpu->id_pfr1 = 0x00011011;
221
- cpu->id_dfr0 = 0x03010066;
222
+ cpu->isar.id_dfr0 = 0x03010066;
223
cpu->id_afr0 = 0x00000000;
224
cpu->id_mmfr0 = 0x10201105;
225
cpu->id_mmfr1 = 0x40000000;
226
diff --git a/target/arm/helper.c b/target/arm/helper.c
227
index XXXXXXX..XXXXXXX 100644
228
--- a/target/arm/helper.c
229
+++ b/target/arm/helper.c
230
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
231
g_free(pmevtyper_name);
232
g_free(pmevtyper_el0_name);
233
}
234
- if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
235
- FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) {
236
+ if (cpu_isar_feature(aa32_pmu_8_1, cpu)) {
237
ARMCPRegInfo v81_pmu_regs[] = {
238
{ .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
239
.cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
240
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
241
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
242
.access = PL1_R, .type = ARM_CP_CONST,
243
.accessfn = access_aa32_tid3,
244
- .resetvalue = cpu->id_dfr0 },
245
+ .resetvalue = cpu->isar.id_dfr0 },
246
{ .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
247
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
248
.access = PL1_R, .type = ARM_CP_CONST,
249
--
250
2.20.1
251
252
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/29] target/arm/cpu: Ensure we can use the pmu with kvm
[PULL 22/52] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks
1
From: Andrew Jones <drjones@redhat.com>
1
Add the 64-bit version of the "is this a v8.1 PMUv3?"
2
ID register check function, and the _any_ version that
3
checks for either AArch32 or AArch64 support. We'll use
4
this in a later commit.
2
5
3
We first convert the pmu property from a static property to one with
6
We don't (yet) do any isar_feature checks on ID_AA64DFR1_EL1,
4
its own accessors. Then we use the set accessor to check if the PMU is
7
but we move id_aa64dfr1 into the ARMISARegisters struct with
5
supported when using KVM. Indeed a 32-bit KVM host does not support
8
id_aa64dfr0, for consistency.
6
the PMU, so this check will catch an attempt to use it at property-set
7
time.
8
9
9
Signed-off-by: Andrew Jones <drjones@redhat.com>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Message-id: 20200214175116.9164-10-peter.maydell@linaro.org
12
---
14
---
13
target/arm/kvm_arm.h | 14 ++++++++++++++
15
target/arm/cpu.h | 15 +++++++++++++--
14
target/arm/cpu.c | 30 +++++++++++++++++++++++++-----
16
target/arm/cpu.c | 3 ++-
15
target/arm/kvm.c | 7 +++++++
17
target/arm/cpu64.c | 6 +++---
16
3 files changed, 46 insertions(+), 5 deletions(-)
18
target/arm/helper.c | 12 +++++++-----
19
4 files changed, 25 insertions(+), 11 deletions(-)
17
20
18
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/kvm_arm.h
23
--- a/target/arm/cpu.h
21
+++ b/target/arm/kvm_arm.h
24
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu);
25
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
23
*/
26
uint64_t id_aa64mmfr0;
24
bool kvm_arm_aarch32_supported(CPUState *cs);
27
uint64_t id_aa64mmfr1;
25
28
uint64_t id_aa64mmfr2;
26
+/**
29
+ uint64_t id_aa64dfr0;
27
+ * bool kvm_arm_pmu_supported:
30
+ uint64_t id_aa64dfr1;
28
+ * @cs: CPUState
31
} isar;
29
+ *
32
uint32_t midr;
30
+ * Returns: true if the KVM VCPU can enable its PMU
33
uint32_t revidr;
31
+ * and false otherwise.
34
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
32
+ */
35
uint32_t id_mmfr2;
33
+bool kvm_arm_pmu_supported(CPUState *cs);
36
uint32_t id_mmfr3;
34
+
37
uint32_t id_mmfr4;
35
/**
38
- uint64_t id_aa64dfr0;
36
* kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the
39
- uint64_t id_aa64dfr1;
37
* IPA address space supported by KVM
40
uint64_t id_aa64afr0;
38
@@ -XXX,XX +XXX,XX @@ static inline bool kvm_arm_aarch32_supported(CPUState *cs)
41
uint64_t id_aa64afr1;
39
return false;
42
uint32_t dbgdidr;
43
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
44
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
40
}
45
}
41
46
42
+static inline bool kvm_arm_pmu_supported(CPUState *cs)
47
+static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id)
43
+{
48
+{
44
+ return false;
49
+ return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
50
+ FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
45
+}
51
+}
46
+
52
+
47
static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
53
/*
48
{
54
* Feature tests for "does this exist in either 32-bit or 64-bit?"
49
return -ENOENT;
55
*/
56
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_predinv(const ARMISARegisters *id)
57
return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id);
58
}
59
60
+static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id)
61
+{
62
+ return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id);
63
+}
64
+
65
/*
66
* Forward to the above feature tests given an ARMCPU pointer.
67
*/
50
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
68
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
51
index XXXXXXX..XXXXXXX 100644
69
index XXXXXXX..XXXXXXX 100644
52
--- a/target/arm/cpu.c
70
--- a/target/arm/cpu.c
53
+++ b/target/arm/cpu.c
71
+++ b/target/arm/cpu.c
54
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_has_el3_property =
72
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
55
static Property arm_cpu_cfgend_property =
73
cpu);
56
DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
74
#endif
57
75
} else {
58
-/* use property name "pmu" to match other archs and virt tools */
76
- cpu->id_aa64dfr0 = FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
59
-static Property arm_cpu_has_pmu_property =
77
+ cpu->isar.id_aa64dfr0 =
60
- DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
78
+ FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
61
-
79
cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0);
62
static Property arm_cpu_has_vfp_property =
80
cpu->pmceid0 = 0;
63
DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
81
cpu->pmceid1 = 0;
64
82
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
65
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_pmsav7_dregion_property =
83
index XXXXXXX..XXXXXXX 100644
66
pmsav7_dregion,
84
--- a/target/arm/cpu64.c
67
qdev_prop_uint32, uint32_t);
85
+++ b/target/arm/cpu64.c
68
86
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
69
+static bool arm_get_pmu(Object *obj, Error **errp)
87
cpu->isar.id_isar5 = 0x00011121;
70
+{
88
cpu->isar.id_isar6 = 0;
71
+ ARMCPU *cpu = ARM_CPU(obj);
89
cpu->isar.id_aa64pfr0 = 0x00002222;
72
+
90
- cpu->id_aa64dfr0 = 0x10305106;
73
+ return cpu->has_pmu;
91
+ cpu->isar.id_aa64dfr0 = 0x10305106;
74
+}
92
cpu->isar.id_aa64isar0 = 0x00011120;
75
+
93
cpu->isar.id_aa64mmfr0 = 0x00001124;
76
+static void arm_set_pmu(Object *obj, bool value, Error **errp)
94
cpu->dbgdidr = 0x3516d000;
77
+{
95
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
78
+ ARMCPU *cpu = ARM_CPU(obj);
96
cpu->isar.id_isar5 = 0x00011121;
79
+
97
cpu->isar.id_isar6 = 0;
80
+ if (value) {
98
cpu->isar.id_aa64pfr0 = 0x00002222;
81
+ if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu))) {
99
- cpu->id_aa64dfr0 = 0x10305106;
82
+ error_setg(errp, "'pmu' feature not supported by KVM on this host");
100
+ cpu->isar.id_aa64dfr0 = 0x10305106;
83
+ return;
101
cpu->isar.id_aa64isar0 = 0x00011120;
84
+ }
102
cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
85
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
103
cpu->dbgdidr = 0x3516d000;
86
+ } else {
104
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
87
+ unset_feature(&cpu->env, ARM_FEATURE_PMU);
105
cpu->isar.id_isar4 = 0x00011142;
88
+ }
106
cpu->isar.id_isar5 = 0x00011121;
89
+ cpu->has_pmu = value;
107
cpu->isar.id_aa64pfr0 = 0x00002222;
90
+}
108
- cpu->id_aa64dfr0 = 0x10305106;
91
+
109
+ cpu->isar.id_aa64dfr0 = 0x10305106;
92
static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name,
110
cpu->isar.id_aa64isar0 = 0x00011120;
93
void *opaque, Error **errp)
111
cpu->isar.id_aa64mmfr0 = 0x00001124;
94
{
112
cpu->dbgdidr = 0x3516d000;
95
@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
113
diff --git a/target/arm/helper.c b/target/arm/helper.c
114
index XXXXXXX..XXXXXXX 100644
115
--- a/target/arm/helper.c
116
+++ b/target/arm/helper.c
117
@@ -XXX,XX +XXX,XX @@
118
#include "hw/semihosting/semihost.h"
119
#include "sysemu/cpus.h"
120
#include "sysemu/kvm.h"
121
+#include "sysemu/tcg.h"
122
#include "qemu/range.h"
123
#include "qapi/qapi-commands-machine-target.h"
124
#include "qapi/error.h"
125
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
126
* check that if they both exist then they agree.
127
*/
128
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
129
- assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, BRPS) == brps);
130
- assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, WRPS) == wrps);
131
- assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) == ctx_cmps);
132
+ assert(FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) == brps);
133
+ assert(FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) == wrps);
134
+ assert(FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS)
135
+ == ctx_cmps);
96
}
136
}
97
137
98
if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
138
define_one_arm_cp_reg(cpu, &dbgdidr);
99
- qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
139
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
100
+ cpu->has_pmu = true;
140
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
101
+ object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu,
141
.access = PL1_R, .type = ARM_CP_CONST,
102
&error_abort);
142
.accessfn = access_aa64_tid3,
103
}
143
- .resetvalue = cpu->id_aa64dfr0 },
104
144
+ .resetvalue = cpu->isar.id_aa64dfr0 },
105
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
145
{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
106
index XXXXXXX..XXXXXXX 100644
146
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
107
--- a/target/arm/kvm.c
147
.access = PL1_R, .type = ARM_CP_CONST,
108
+++ b/target/arm/kvm.c
148
.accessfn = access_aa64_tid3,
109
@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
149
- .resetvalue = cpu->id_aa64dfr1 },
110
env->features = arm_host_cpu_features.features;
150
+ .resetvalue = cpu->isar.id_aa64dfr1 },
111
}
151
{ .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
112
152
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
113
+bool kvm_arm_pmu_supported(CPUState *cpu)
153
.access = PL1_R, .type = ARM_CP_CONST,
114
+{
115
+ KVMState *s = KVM_STATE(current_machine->accelerator);
116
+
117
+ return kvm_check_extension(s, KVM_CAP_ARM_PMU_V3);
118
+}
119
+
120
int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
121
{
122
KVMState *s = KVM_STATE(ms->accelerator);
123
--
154
--
124
2.20.1
155
2.20.1
125
156
126
157
diff view generated by jsdifflib
New patch
[PULL 23/52] target/arm: Stop assuming DBGDIDR always exists
1
The AArch32 DBGDIDR defines properties like the number of
2
breakpoints, watchpoints and context-matching comparators. On an
3
AArch64 CPU, the register may not even exist if AArch32 is not
4
supported at EL1.
1
5
6
Currently we hard-code use of DBGDIDR to identify the number of
7
breakpoints etc; this works for all our TCG CPUs, but will break if
8
we ever add an AArch64-only CPU. We also have an assert() that the
9
AArch32 and AArch64 registers match, which currently works only by
10
luck for KVM because we don't populate either of these ID registers
11
from the KVM vCPU and so they are both zero.
12
13
Clean this up so we have functions for finding the number
14
of breakpoints, watchpoints and context comparators which look
15
in the appropriate ID register.
16
17
This allows us to drop the "check that AArch64 and AArch32 agree
18
on the number of breakpoints etc" asserts:
19
* we no longer look at the AArch32 versions unless that's the
20
right place to be looking
21
* it's valid to have a CPU (eg AArch64-only) where they don't match
22
* we shouldn't have been asserting the validity of ID registers
23
in a codepath used with KVM anyway
24
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
27
Message-id: 20200214175116.9164-11-peter.maydell@linaro.org
28
---
29
target/arm/cpu.h | 7 +++++++
30
target/arm/internals.h | 42 +++++++++++++++++++++++++++++++++++++++
31
target/arm/debug_helper.c | 6 +++---
32
target/arm/helper.c | 21 +++++---------------
33
4 files changed, 57 insertions(+), 19 deletions(-)
34
35
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/cpu.h
38
+++ b/target/arm/cpu.h
39
@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
40
FIELD(ID_DFR0, PERFMON, 24, 4)
41
FIELD(ID_DFR0, TRACEFILT, 28, 4)
42
43
+FIELD(DBGDIDR, SE_IMP, 12, 1)
44
+FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
45
+FIELD(DBGDIDR, VERSION, 16, 4)
46
+FIELD(DBGDIDR, CTX_CMPS, 20, 4)
47
+FIELD(DBGDIDR, BRPS, 24, 4)
48
+FIELD(DBGDIDR, WRPS, 28, 4)
49
+
50
FIELD(MVFR0, SIMDREG, 0, 4)
51
FIELD(MVFR0, FPSP, 4, 4)
52
FIELD(MVFR0, FPDP, 8, 4)
53
diff --git a/target/arm/internals.h b/target/arm/internals.h
54
index XXXXXXX..XXXXXXX 100644
55
--- a/target/arm/internals.h
56
+++ b/target/arm/internals.h
57
@@ -XXX,XX +XXX,XX @@ static inline uint32_t arm_debug_exception_fsr(CPUARMState *env)
58
}
59
}
60
61
+/**
62
+ * arm_num_brps: Return number of implemented breakpoints.
63
+ * Note that the ID register BRPS field is "number of bps - 1",
64
+ * and we return the actual number of breakpoints.
65
+ */
66
+static inline int arm_num_brps(ARMCPU *cpu)
67
+{
68
+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
69
+ return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1;
70
+ } else {
71
+ return FIELD_EX32(cpu->dbgdidr, DBGDIDR, BRPS) + 1;
72
+ }
73
+}
74
+
75
+/**
76
+ * arm_num_wrps: Return number of implemented watchpoints.
77
+ * Note that the ID register WRPS field is "number of wps - 1",
78
+ * and we return the actual number of watchpoints.
79
+ */
80
+static inline int arm_num_wrps(ARMCPU *cpu)
81
+{
82
+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
83
+ return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1;
84
+ } else {
85
+ return FIELD_EX32(cpu->dbgdidr, DBGDIDR, WRPS) + 1;
86
+ }
87
+}
88
+
89
+/**
90
+ * arm_num_ctx_cmps: Return number of implemented context comparators.
91
+ * Note that the ID register CTX_CMPS field is "number of cmps - 1",
92
+ * and we return the actual number of comparators.
93
+ */
94
+static inline int arm_num_ctx_cmps(ARMCPU *cpu)
95
+{
96
+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
97
+ return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1;
98
+ } else {
99
+ return FIELD_EX32(cpu->dbgdidr, DBGDIDR, CTX_CMPS) + 1;
100
+ }
101
+}
102
+
103
/* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3.
104
* Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits.
105
*/
106
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/debug_helper.c
109
+++ b/target/arm/debug_helper.c
110
@@ -XXX,XX +XXX,XX @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
111
{
112
CPUARMState *env = &cpu->env;
113
uint64_t bcr = env->cp15.dbgbcr[lbn];
114
- int brps = extract32(cpu->dbgdidr, 24, 4);
115
- int ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
116
+ int brps = arm_num_brps(cpu);
117
+ int ctx_cmps = arm_num_ctx_cmps(cpu);
118
int bt;
119
uint32_t contextidr;
120
uint64_t hcr_el2;
121
@@ -XXX,XX +XXX,XX @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
122
* case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
123
* We choose the former.
124
*/
125
- if (lbn > brps || lbn < (brps - ctx_cmps)) {
126
+ if (lbn >= brps || lbn < (brps - ctx_cmps)) {
127
return false;
128
}
129
130
diff --git a/target/arm/helper.c b/target/arm/helper.c
131
index XXXXXXX..XXXXXXX 100644
132
--- a/target/arm/helper.c
133
+++ b/target/arm/helper.c
134
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
135
};
136
137
/* Note that all these register fields hold "number of Xs minus 1". */
138
- brps = extract32(cpu->dbgdidr, 24, 4);
139
- wrps = extract32(cpu->dbgdidr, 28, 4);
140
- ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
141
+ brps = arm_num_brps(cpu);
142
+ wrps = arm_num_wrps(cpu);
143
+ ctx_cmps = arm_num_ctx_cmps(cpu);
144
145
assert(ctx_cmps <= brps);
146
147
- /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
148
- * of the debug registers such as number of breakpoints;
149
- * check that if they both exist then they agree.
150
- */
151
- if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
152
- assert(FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) == brps);
153
- assert(FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) == wrps);
154
- assert(FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS)
155
- == ctx_cmps);
156
- }
157
-
158
define_one_arm_cp_reg(cpu, &dbgdidr);
159
define_arm_cp_regs(cpu, debug_cp_reginfo);
160
161
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
162
define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
163
}
164
165
- for (i = 0; i < brps + 1; i++) {
166
+ for (i = 0; i < brps; i++) {
167
ARMCPRegInfo dbgregs[] = {
168
{ .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
169
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
170
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
171
define_arm_cp_regs(cpu, dbgregs);
172
}
173
174
- for (i = 0; i < wrps + 1; i++) {
175
+ for (i = 0; i < wrps; i++) {
176
ARMCPRegInfo dbgregs[] = {
177
{ .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
178
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
179
--
180
2.20.1
181
182
diff view generated by jsdifflib
New patch
[PULL 24/52] target/arm: Move DBGDIDR into ARMISARegisters
1
We're going to want to read the DBGDIDR register from KVM in
2
a subsequent commit, which means it needs to be in the
3
ARMISARegisters sub-struct. Move it.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200214175116.9164-12-peter.maydell@linaro.org
8
---
9
target/arm/cpu.h | 2 +-
10
target/arm/internals.h | 6 +++---
11
target/arm/cpu.c | 8 ++++----
12
target/arm/cpu64.c | 6 +++---
13
target/arm/helper.c | 2 +-
14
5 files changed, 12 insertions(+), 12 deletions(-)
15
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
21
uint32_t mvfr1;
22
uint32_t mvfr2;
23
uint32_t id_dfr0;
24
+ uint32_t dbgdidr;
25
uint64_t id_aa64isar0;
26
uint64_t id_aa64isar1;
27
uint64_t id_aa64pfr0;
28
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
29
uint32_t id_mmfr4;
30
uint64_t id_aa64afr0;
31
uint64_t id_aa64afr1;
32
- uint32_t dbgdidr;
33
uint32_t clidr;
34
uint64_t mp_affinity; /* MP ID without feature bits */
35
/* The elements of this array are the CCSIDR values for each cache,
36
diff --git a/target/arm/internals.h b/target/arm/internals.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/internals.h
39
+++ b/target/arm/internals.h
40
@@ -XXX,XX +XXX,XX @@ static inline int arm_num_brps(ARMCPU *cpu)
41
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
42
return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1;
43
} else {
44
- return FIELD_EX32(cpu->dbgdidr, DBGDIDR, BRPS) + 1;
45
+ return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1;
46
}
47
}
48
49
@@ -XXX,XX +XXX,XX @@ static inline int arm_num_wrps(ARMCPU *cpu)
50
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
51
return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1;
52
} else {
53
- return FIELD_EX32(cpu->dbgdidr, DBGDIDR, WRPS) + 1;
54
+ return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1;
55
}
56
}
57
58
@@ -XXX,XX +XXX,XX @@ static inline int arm_num_ctx_cmps(ARMCPU *cpu)
59
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
60
return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1;
61
} else {
62
- return FIELD_EX32(cpu->dbgdidr, DBGDIDR, CTX_CMPS) + 1;
63
+ return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1;
64
}
65
}
66
67
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/target/arm/cpu.c
70
+++ b/target/arm/cpu.c
71
@@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj)
72
cpu->isar.id_isar2 = 0x21232031;
73
cpu->isar.id_isar3 = 0x11112131;
74
cpu->isar.id_isar4 = 0x00111142;
75
- cpu->dbgdidr = 0x15141000;
76
+ cpu->isar.dbgdidr = 0x15141000;
77
cpu->clidr = (1 << 27) | (2 << 24) | 3;
78
cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
79
cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
80
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
81
cpu->isar.id_isar2 = 0x21232041;
82
cpu->isar.id_isar3 = 0x11112131;
83
cpu->isar.id_isar4 = 0x00111142;
84
- cpu->dbgdidr = 0x35141000;
85
+ cpu->isar.dbgdidr = 0x35141000;
86
cpu->clidr = (1 << 27) | (1 << 24) | 3;
87
cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
88
cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
89
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
90
cpu->isar.id_isar2 = 0x21232041;
91
cpu->isar.id_isar3 = 0x11112131;
92
cpu->isar.id_isar4 = 0x10011142;
93
- cpu->dbgdidr = 0x3515f005;
94
+ cpu->isar.dbgdidr = 0x3515f005;
95
cpu->clidr = 0x0a200023;
96
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
97
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
98
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
99
cpu->isar.id_isar2 = 0x21232041;
100
cpu->isar.id_isar3 = 0x11112131;
101
cpu->isar.id_isar4 = 0x10011142;
102
- cpu->dbgdidr = 0x3515f021;
103
+ cpu->isar.dbgdidr = 0x3515f021;
104
cpu->clidr = 0x0a200023;
105
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
106
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
107
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/target/arm/cpu64.c
110
+++ b/target/arm/cpu64.c
111
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
112
cpu->isar.id_aa64dfr0 = 0x10305106;
113
cpu->isar.id_aa64isar0 = 0x00011120;
114
cpu->isar.id_aa64mmfr0 = 0x00001124;
115
- cpu->dbgdidr = 0x3516d000;
116
+ cpu->isar.dbgdidr = 0x3516d000;
117
cpu->clidr = 0x0a200023;
118
cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
119
cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
120
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
121
cpu->isar.id_aa64dfr0 = 0x10305106;
122
cpu->isar.id_aa64isar0 = 0x00011120;
123
cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
124
- cpu->dbgdidr = 0x3516d000;
125
+ cpu->isar.dbgdidr = 0x3516d000;
126
cpu->clidr = 0x0a200023;
127
cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
128
cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
129
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
130
cpu->isar.id_aa64dfr0 = 0x10305106;
131
cpu->isar.id_aa64isar0 = 0x00011120;
132
cpu->isar.id_aa64mmfr0 = 0x00001124;
133
- cpu->dbgdidr = 0x3516d000;
134
+ cpu->isar.dbgdidr = 0x3516d000;
135
cpu->clidr = 0x0a200023;
136
cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
137
cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
138
diff --git a/target/arm/helper.c b/target/arm/helper.c
139
index XXXXXXX..XXXXXXX 100644
140
--- a/target/arm/helper.c
141
+++ b/target/arm/helper.c
142
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
143
ARMCPRegInfo dbgdidr = {
144
.name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
145
.access = PL0_R, .accessfn = access_tda,
146
- .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
147
+ .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
148
};
149
150
/* Note that all these register fields hold "number of Xs minus 1". */
151
--
152
2.20.1
153
154
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/29] target/arm/kvm64: Fix error returns
[PULL 25/52] target/arm: Read debug-related ID registers from KVM
1
From: Andrew Jones <drjones@redhat.com>
1
Now we have isar_feature test functions that look at fields in the
2
ID_AA64DFR0_EL1 and ID_DFR0 ID registers, add the code that reads
3
these register values from KVM so that the checks behave correctly
4
when we're using KVM.
2
5
3
A couple return -EINVAL's forgot their '-'s.
6
No isar_feature function tests ID_AA64DFR1_EL1 or DBGDIDR yet, but we
7
add it to maintain the invariant that every field in the
8
ARMISARegisters struct is populated for a KVM CPU and can be relied
9
on. This requirement isn't actually written down yet, so add a note
10
to the relevant comment.
4
11
5
Signed-off-by: Andrew Jones <drjones@redhat.com>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Eric Auger <eric.auger@redhat.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Message-id: 20200214175116.9164-13-peter.maydell@linaro.org
9
---
15
---
10
target/arm/kvm64.c | 4 ++--
16
target/arm/cpu.h | 5 +++++
11
1 file changed, 2 insertions(+), 2 deletions(-)
17
target/arm/kvm32.c | 8 ++++++++
18
target/arm/kvm64.c | 36 ++++++++++++++++++++++++++++++++++++
19
3 files changed, 49 insertions(+)
12
20
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.h
24
+++ b/target/arm/cpu.h
25
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
26
* prefix means a constant register.
27
* Some of these registers are split out into a substructure that
28
* is shared with the translators to control the ISA.
29
+ *
30
+ * Note that if you add an ID register to the ARMISARegisters struct
31
+ * you need to also update the 32-bit and 64-bit versions of the
32
+ * kvm_arm_get_host_cpu_features() function to correctly populate the
33
+ * field by reading the value from the KVM vCPU.
34
*/
35
struct ARMISARegisters {
36
uint32_t id_isar0;
37
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/kvm32.c
40
+++ b/target/arm/kvm32.c
41
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
42
ahcf->isar.id_isar6 = 0;
43
}
44
45
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
46
+ ARM_CP15_REG32(0, 0, 1, 2));
47
+
48
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
49
KVM_REG_ARM | KVM_REG_SIZE_U32 |
50
KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0);
51
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
52
* Fortunately there is not yet anything in there that affects migration.
53
*/
54
55
+ /*
56
+ * There is no way to read DBGDIDR, because currently 32-bit KVM
57
+ * doesn't implement debug at all. Leave it at zero.
58
+ */
59
+
60
kvm_arm_destroy_scratch_host_vcpu(fdarray);
61
62
if (err < 0) {
13
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
63
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
14
index XXXXXXX..XXXXXXX 100644
64
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/kvm64.c
65
--- a/target/arm/kvm64.c
16
+++ b/target/arm/kvm64.c
66
+++ b/target/arm/kvm64.c
17
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
67
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
18
write_cpustate_to_list(cpu, true);
68
} else {
19
69
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1,
20
if (!write_list_to_kvmstate(cpu, level)) {
70
ARM64_SYS_REG(3, 0, 0, 4, 1));
21
- return EINVAL;
71
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0,
22
+ return -EINVAL;
72
+ ARM64_SYS_REG(3, 0, 0, 5, 0));
73
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1,
74
+ ARM64_SYS_REG(3, 0, 0, 5, 1));
75
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0,
76
ARM64_SYS_REG(3, 0, 0, 6, 0));
77
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
78
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
79
* than skipping the reads and leaving 0, as we must avoid
80
* considering the values in every case.
81
*/
82
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
83
+ ARM64_SYS_REG(3, 0, 0, 1, 2));
84
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
85
ARM64_SYS_REG(3, 0, 0, 2, 0));
86
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
87
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
88
ARM64_SYS_REG(3, 0, 0, 3, 1));
89
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2,
90
ARM64_SYS_REG(3, 0, 0, 3, 2));
91
+
92
+ /*
93
+ * DBGDIDR is a bit complicated because the kernel doesn't
94
+ * provide an accessor for it in 64-bit mode, which is what this
95
+ * scratch VM is in, and there's no architected "64-bit sysreg
96
+ * which reads the same as the 32-bit register" the way there is
97
+ * for other ID registers. Instead we synthesize a value from the
98
+ * AArch64 ID_AA64DFR0, the same way the kernel code in
99
+ * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does.
100
+ * We only do this if the CPU supports AArch32 at EL1.
101
+ */
102
+ if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2) {
103
+ int wrps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS);
104
+ int brps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS);
105
+ int ctx_cmps =
106
+ FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS);
107
+ int version = 6; /* ARMv8 debug architecture */
108
+ bool has_el3 =
109
+ !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3);
110
+ uint32_t dbgdidr = 0;
111
+
112
+ dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps);
113
+ dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps);
114
+ dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps);
115
+ dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version);
116
+ dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3);
117
+ dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3);
118
+ dbgdidr |= (1 << 15); /* RES1 bit */
119
+ ahcf->isar.dbgdidr = dbgdidr;
120
+ }
23
}
121
}
24
122
25
kvm_arm_sync_mpstate_to_kvm(cpu);
123
sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
26
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
27
}
28
29
if (!write_kvmstate_to_list(cpu)) {
30
- return EINVAL;
31
+ return -EINVAL;
32
}
33
/* Note that it's OK to have registers which aren't in CPUState,
34
* so we can ignore a failure return here.
35
--
124
--
36
2.20.1
125
2.20.1
37
126
38
127
diff view generated by jsdifflib
New patch
[PULL 26/52] target/arm: Implement ARMv8.1-PMU extension
1
The ARMv8.1-PMU extension requires:
2
* the evtCount field in PMETYPER<n>_EL0 is 16 bits, not 10
3
* MDCR_EL2.HPMD allows event counting to be disabled at EL2
4
* two new required events, STALL_FRONTEND and STALL_BACKEND
5
* ID register bits in ID_AA64DFR0_EL1 and ID_DFR0
1
6
7
We already implement the 16-bit evtCount field and the
8
HPMD bit, so all that is missing is the two new events:
9
STALL_FRONTEND
10
"counts every cycle counted by the CPU_CYCLES event on which no
11
operation was issued because there are no operations available
12
to issue to this PE from the frontend"
13
STALL_BACKEND
14
"counts every cycle counted by the CPU_CYCLES event on which no
15
operation was issued because the backend is unable to accept
16
any available operations from the frontend"
17
18
QEMU never stalls in this sense, so our implementation is trivial:
19
always return a zero count.
20
21
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Message-id: 20200214175116.9164-14-peter.maydell@linaro.org
24
---
25
target/arm/helper.c | 32 ++++++++++++++++++++++++++++++--
26
1 file changed, 30 insertions(+), 2 deletions(-)
27
28
diff --git a/target/arm/helper.c b/target/arm/helper.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/helper.c
31
+++ b/target/arm/helper.c
32
@@ -XXX,XX +XXX,XX @@ static int64_t instructions_ns_per(uint64_t icount)
33
}
34
#endif
35
36
+static bool pmu_8_1_events_supported(CPUARMState *env)
37
+{
38
+ /* For events which are supported in any v8.1 PMU */
39
+ return cpu_isar_feature(any_pmu_8_1, env_archcpu(env));
40
+}
41
+
42
+static uint64_t zero_event_get_count(CPUARMState *env)
43
+{
44
+ /* For events which on QEMU never fire, so their count is always zero */
45
+ return 0;
46
+}
47
+
48
+static int64_t zero_event_ns_per(uint64_t cycles)
49
+{
50
+ /* An event which never fires can never overflow */
51
+ return -1;
52
+}
53
+
54
static const pm_event pm_events[] = {
55
{ .number = 0x000, /* SW_INCR */
56
.supported = event_always_supported,
57
@@ -XXX,XX +XXX,XX @@ static const pm_event pm_events[] = {
58
.supported = event_always_supported,
59
.get_count = cycles_get_count,
60
.ns_per_count = cycles_ns_per,
61
- }
62
+ },
63
#endif
64
+ { .number = 0x023, /* STALL_FRONTEND */
65
+ .supported = pmu_8_1_events_supported,
66
+ .get_count = zero_event_get_count,
67
+ .ns_per_count = zero_event_ns_per,
68
+ },
69
+ { .number = 0x024, /* STALL_BACKEND */
70
+ .supported = pmu_8_1_events_supported,
71
+ .get_count = zero_event_get_count,
72
+ .ns_per_count = zero_event_ns_per,
73
+ },
74
};
75
76
/*
77
@@ -XXX,XX +XXX,XX @@ static const pm_event pm_events[] = {
78
* should first be updated to something sparse instead of the current
79
* supported_event_map[] array.
80
*/
81
-#define MAX_EVENT_ID 0x11
82
+#define MAX_EVENT_ID 0x24
83
#define UNSUPPORTED_EVENT UINT16_MAX
84
static uint16_t supported_event_map[MAX_EVENT_ID + 1];
85
86
--
87
2.20.1
88
89
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/29] target/arm/cpu: Use div-round-up to determine predicate register array size
[PULL 27/52] target/arm: Implement ARMv8.4-PMU extension
1
From: Andrew Jones <drjones@redhat.com>
1
The ARMv8.4-PMU extension adds:
2
* one new required event, STALL
3
* one new system register PMMIR_EL1
2
4
3
Unless we're guaranteed to always increase ARM_MAX_VQ by a multiple of
5
(There are also some more L1-cache related events, but since
4
four, then we should use DIV_ROUND_UP to ensure we get an appropriate
6
we don't implement any cache we don't provide these, in the
5
array size.
7
same way we don't provide the base-PMUv3 cache events.)
6
8
7
Signed-off-by: Andrew Jones <drjones@redhat.com>
9
The STALL event "counts every attributable cycle on which no
10
attributable instruction or operation was sent for execution on this
11
PE". QEMU doesn't stall in this sense, so this is another
12
always-reads-zero event.
13
14
The PMMIR_EL1 register is a read-only register providing
15
implementation-specific information about the PMU; currently it has
16
only one field, SLOTS, which defines behaviour of the STALL_SLOT PMU
17
event. Since QEMU doesn't implement the STALL_SLOT event, we can
18
validly make the register read zero.
19
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Message-id: 20200214175116.9164-15-peter.maydell@linaro.org
10
---
23
---
11
target/arm/cpu.h | 2 +-
24
target/arm/cpu.h | 18 ++++++++++++++++++
12
1 file changed, 1 insertion(+), 1 deletion(-)
25
target/arm/helper.c | 22 +++++++++++++++++++++-
26
2 files changed, 39 insertions(+), 1 deletion(-)
13
27
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
28
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.h
30
--- a/target/arm/cpu.h
17
+++ b/target/arm/cpu.h
31
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ typedef struct ARMVectorReg {
32
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id)
19
#ifdef TARGET_AARCH64
33
FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
20
/* In AArch32 mode, predicate registers do not exist at all. */
34
}
21
typedef struct ARMPredicateReg {
35
22
- uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16);
36
+static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id)
23
+ uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
37
+{
24
} ARMPredicateReg;
38
+ /* 0xf means "non-standard IMPDEF PMU" */
25
39
+ return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 &&
26
/* In AArch32 mode, PAC keys do not exist at all. */
40
+ FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
41
+}
42
+
43
/*
44
* 64-bit feature tests via id registers.
45
*/
46
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id)
47
FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
48
}
49
50
+static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id)
51
+{
52
+ return FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
53
+ FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
54
+}
55
+
56
/*
57
* Feature tests for "does this exist in either 32-bit or 64-bit?"
58
*/
59
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id)
60
return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id);
61
}
62
63
+static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id)
64
+{
65
+ return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id);
66
+}
67
+
68
/*
69
* Forward to the above feature tests given an ARMCPU pointer.
70
*/
71
diff --git a/target/arm/helper.c b/target/arm/helper.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/helper.c
74
+++ b/target/arm/helper.c
75
@@ -XXX,XX +XXX,XX @@ static bool pmu_8_1_events_supported(CPUARMState *env)
76
return cpu_isar_feature(any_pmu_8_1, env_archcpu(env));
77
}
78
79
+static bool pmu_8_4_events_supported(CPUARMState *env)
80
+{
81
+ /* For events which are supported in any v8.1 PMU */
82
+ return cpu_isar_feature(any_pmu_8_4, env_archcpu(env));
83
+}
84
+
85
static uint64_t zero_event_get_count(CPUARMState *env)
86
{
87
/* For events which on QEMU never fire, so their count is always zero */
88
@@ -XXX,XX +XXX,XX @@ static const pm_event pm_events[] = {
89
.get_count = zero_event_get_count,
90
.ns_per_count = zero_event_ns_per,
91
},
92
+ { .number = 0x03c, /* STALL */
93
+ .supported = pmu_8_4_events_supported,
94
+ .get_count = zero_event_get_count,
95
+ .ns_per_count = zero_event_ns_per,
96
+ },
97
};
98
99
/*
100
@@ -XXX,XX +XXX,XX @@ static const pm_event pm_events[] = {
101
* should first be updated to something sparse instead of the current
102
* supported_event_map[] array.
103
*/
104
-#define MAX_EVENT_ID 0x24
105
+#define MAX_EVENT_ID 0x3c
106
#define UNSUPPORTED_EVENT UINT16_MAX
107
static uint16_t supported_event_map[MAX_EVENT_ID + 1];
108
109
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
110
};
111
define_arm_cp_regs(cpu, v81_pmu_regs);
112
}
113
+ if (cpu_isar_feature(any_pmu_8_4, cpu)) {
114
+ static const ARMCPRegInfo v84_pmmir = {
115
+ .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH,
116
+ .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6,
117
+ .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
118
+ .resetvalue = 0
119
+ };
120
+ define_one_arm_cp_reg(cpu, &v84_pmmir);
121
+ }
122
}
123
124
/* We don't know until after realize whether there's a GICv3
27
--
125
--
28
2.20.1
126
2.20.1
29
127
30
128
diff view generated by jsdifflib
New patch
[PULL 28/52] target/arm: Provide ARMv8.4-PMU in '-cpu max'
1
Set the ID register bits to provide ARMv8.4-PMU (and implicitly
2
also ARMv8.1-PMU) in the 'max' CPU.
1
3
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Message-id: 20200214175116.9164-16-peter.maydell@linaro.org
7
---
8
target/arm/cpu64.c | 8 ++++++++
9
1 file changed, 8 insertions(+)
10
11
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/cpu64.c
14
+++ b/target/arm/cpu64.c
15
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
16
u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
17
cpu->id_mmfr3 = u;
18
19
+ u = cpu->isar.id_aa64dfr0;
20
+ u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
21
+ cpu->isar.id_aa64dfr0 = u;
22
+
23
+ u = cpu->isar.id_dfr0;
24
+ u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
25
+ cpu->isar.id_dfr0 = u;
26
+
27
/*
28
* FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,
29
* so do not set MVFR1.FPHP. Strictly speaking this is not legal,
30
--
31
2.20.1
32
33
diff view generated by jsdifflib
New patch
[PULL 29/52] target/arm: Correct definition of PMCRDP
1
The PMCR_EL0.DP bit is bit 5, which is 0x20, not 0x10. 0x10 is 'X'.
2
Correct our #define of PMCRDP and add the missing PMCRX.
1
3
4
We do have the correct behaviour for handling the DP bit being
5
set, so this fixes a guest-visible bug.
6
7
Fixes: 033614c47de
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20200214175116.9164-17-peter.maydell@linaro.org
12
---
13
target/arm/helper.c | 3 ++-
14
1 file changed, 2 insertions(+), 1 deletion(-)
15
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
19
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
21
#define PMCRN_MASK 0xf800
22
#define PMCRN_SHIFT 11
23
#define PMCRLC 0x40
24
-#define PMCRDP 0x10
25
+#define PMCRDP 0x20
26
+#define PMCRX 0x10
27
#define PMCRD 0x8
28
#define PMCRC 0x4
29
#define PMCRP 0x2
30
--
31
2.20.1
32
33
diff view generated by jsdifflib
New patch
[PULL 30/52] target/arm: Correct handling of PMCR_EL0.LC bit
1
The LC bit in the PMCR_EL0 register is supposed to be:
2
* read/write
3
* RES1 on an AArch64-only implementation
4
* an architecturally UNKNOWN value on reset
5
(and use of LC==0 by software is deprecated).
1
6
7
We were implementing it incorrectly as read-only always zero,
8
though we do have all the code needed to test it and behave
9
accordingly.
10
11
Instead make it a read-write bit which resets to 1 always, which
12
satisfies all the architectural requirements above.
13
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 20200214175116.9164-18-peter.maydell@linaro.org
18
---
19
target/arm/helper.c | 13 +++++++++----
20
1 file changed, 9 insertions(+), 4 deletions(-)
21
22
diff --git a/target/arm/helper.c b/target/arm/helper.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/helper.c
25
+++ b/target/arm/helper.c
26
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
27
#define PMCRC 0x4
28
#define PMCRP 0x2
29
#define PMCRE 0x1
30
+/*
31
+ * Mask of PMCR bits writeable by guest (not including WO bits like C, P,
32
+ * which can be written as 1 to trigger behaviour but which stay RAZ).
33
+ */
34
+#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
35
36
#define PMXEVTYPER_P 0x80000000
37
#define PMXEVTYPER_U 0x40000000
38
@@ -XXX,XX +XXX,XX @@ static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
39
}
40
}
41
42
- /* only the DP, X, D and E bits are writable */
43
- env->cp15.c9_pmcr &= ~0x39;
44
- env->cp15.c9_pmcr |= (value & 0x39);
45
+ env->cp15.c9_pmcr &= ~PMCR_WRITEABLE_MASK;
46
+ env->cp15.c9_pmcr |= (value & PMCR_WRITEABLE_MASK);
47
48
pmu_op_finish(env);
49
}
50
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
51
.access = PL0_RW, .accessfn = pmreg_access,
52
.type = ARM_CP_IO,
53
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
54
- .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT),
55
+ .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) |
56
+ PMCRLC,
57
.writefn = pmcr_write, .raw_writefn = raw_write,
58
};
59
define_one_arm_cp_reg(cpu, &pmcr);
60
--
61
2.20.1
62
63
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/29] target/arm/cpu64: Ensure kvm really supports aarch64=off
[PULL 31/52] target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks
1
From: Andrew Jones <drjones@redhat.com>
1
The isar_feature_aa32_pan and isar_feature_aa32_ats1e1 functions
2
are supposed to be testing fields in ID_MMFR3; but a cut-and-paste
3
error meant we were looking at MVFR0 instead.
2
4
3
If -cpu <cpu>,aarch64=off is used then KVM must also be used, and it
5
Fix the functions to look at the right register; this requires
4
and the host must support running the vcpu in 32-bit mode. Also, if
6
us to move at least id_mmfr3 to the ARMISARegisters struct; we
5
-cpu <cpu>,aarch64=on is used, then it doesn't matter if kvm is
7
choose to move all the ID_MMFRn registers for consistency.
6
enabled or not.
7
8
8
Signed-off-by: Andrew Jones <drjones@redhat.com>
9
Fixes: 3d6ad6bb466f
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20200214175116.9164-19-peter.maydell@linaro.org
11
---
13
---
12
target/arm/kvm_arm.h | 14 ++++++++++++++
14
target/arm/cpu.h | 14 +++---
13
target/arm/cpu64.c | 12 ++++++------
15
hw/intc/armv7m_nvic.c | 8 ++--
14
target/arm/kvm64.c | 9 +++++++++
16
target/arm/cpu.c | 104 +++++++++++++++++++++---------------------
15
3 files changed, 29 insertions(+), 6 deletions(-)
17
target/arm/cpu64.c | 28 ++++++------
18
target/arm/helper.c | 12 ++---
19
target/arm/kvm32.c | 17 +++++++
20
target/arm/kvm64.c | 10 ++++
21
7 files changed, 110 insertions(+), 83 deletions(-)
16
22
17
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
23
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/kvm_arm.h
25
--- a/target/arm/cpu.h
20
+++ b/target/arm/kvm_arm.h
26
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf);
27
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
22
*/
28
uint32_t id_isar4;
23
void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu);
29
uint32_t id_isar5;
24
30
uint32_t id_isar6;
25
+/**
31
+ uint32_t id_mmfr0;
26
+ * kvm_arm_aarch32_supported:
32
+ uint32_t id_mmfr1;
27
+ * @cs: CPUState
33
+ uint32_t id_mmfr2;
28
+ *
34
+ uint32_t id_mmfr3;
29
+ * Returns: true if the KVM VCPU can enable AArch32 mode
35
+ uint32_t id_mmfr4;
30
+ * and false otherwise.
36
uint32_t mvfr0;
31
+ */
37
uint32_t mvfr1;
32
+bool kvm_arm_aarch32_supported(CPUState *cs);
38
uint32_t mvfr2;
33
+
39
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
34
/**
40
uint64_t pmceid0;
35
* kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the
41
uint64_t pmceid1;
36
* IPA address space supported by KVM
42
uint32_t id_afr0;
37
@@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
43
- uint32_t id_mmfr0;
38
cpu->host_cpu_probe_failed = true;
44
- uint32_t id_mmfr1;
45
- uint32_t id_mmfr2;
46
- uint32_t id_mmfr3;
47
- uint32_t id_mmfr4;
48
uint64_t id_aa64afr0;
49
uint64_t id_aa64afr1;
50
uint32_t clidr;
51
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
52
53
static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
54
{
55
- return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) != 0;
56
+ return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
39
}
57
}
40
58
41
+static inline bool kvm_arm_aarch32_supported(CPUState *cs)
59
static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
42
+{
43
+ return false;
44
+}
45
+
46
static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
47
{
60
{
48
return -ENOENT;
61
- return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2;
62
+ return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
63
}
64
65
static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id)
66
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/hw/intc/armv7m_nvic.c
69
+++ b/hw/intc/armv7m_nvic.c
70
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
71
case 0xd4c: /* AFR0. */
72
return cpu->id_afr0;
73
case 0xd50: /* MMFR0. */
74
- return cpu->id_mmfr0;
75
+ return cpu->isar.id_mmfr0;
76
case 0xd54: /* MMFR1. */
77
- return cpu->id_mmfr1;
78
+ return cpu->isar.id_mmfr1;
79
case 0xd58: /* MMFR2. */
80
- return cpu->id_mmfr2;
81
+ return cpu->isar.id_mmfr2;
82
case 0xd5c: /* MMFR3. */
83
- return cpu->id_mmfr3;
84
+ return cpu->isar.id_mmfr3;
85
case 0xd60: /* ISAR0. */
86
return cpu->isar.id_isar0;
87
case 0xd64: /* ISAR1. */
88
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/target/arm/cpu.c
91
+++ b/target/arm/cpu.c
92
@@ -XXX,XX +XXX,XX @@ static void arm1136_r2_initfn(Object *obj)
93
cpu->id_pfr1 = 0x1;
94
cpu->isar.id_dfr0 = 0x2;
95
cpu->id_afr0 = 0x3;
96
- cpu->id_mmfr0 = 0x01130003;
97
- cpu->id_mmfr1 = 0x10030302;
98
- cpu->id_mmfr2 = 0x01222110;
99
+ cpu->isar.id_mmfr0 = 0x01130003;
100
+ cpu->isar.id_mmfr1 = 0x10030302;
101
+ cpu->isar.id_mmfr2 = 0x01222110;
102
cpu->isar.id_isar0 = 0x00140011;
103
cpu->isar.id_isar1 = 0x12002111;
104
cpu->isar.id_isar2 = 0x11231111;
105
@@ -XXX,XX +XXX,XX @@ static void arm1136_initfn(Object *obj)
106
cpu->id_pfr1 = 0x1;
107
cpu->isar.id_dfr0 = 0x2;
108
cpu->id_afr0 = 0x3;
109
- cpu->id_mmfr0 = 0x01130003;
110
- cpu->id_mmfr1 = 0x10030302;
111
- cpu->id_mmfr2 = 0x01222110;
112
+ cpu->isar.id_mmfr0 = 0x01130003;
113
+ cpu->isar.id_mmfr1 = 0x10030302;
114
+ cpu->isar.id_mmfr2 = 0x01222110;
115
cpu->isar.id_isar0 = 0x00140011;
116
cpu->isar.id_isar1 = 0x12002111;
117
cpu->isar.id_isar2 = 0x11231111;
118
@@ -XXX,XX +XXX,XX @@ static void arm1176_initfn(Object *obj)
119
cpu->id_pfr1 = 0x11;
120
cpu->isar.id_dfr0 = 0x33;
121
cpu->id_afr0 = 0;
122
- cpu->id_mmfr0 = 0x01130003;
123
- cpu->id_mmfr1 = 0x10030302;
124
- cpu->id_mmfr2 = 0x01222100;
125
+ cpu->isar.id_mmfr0 = 0x01130003;
126
+ cpu->isar.id_mmfr1 = 0x10030302;
127
+ cpu->isar.id_mmfr2 = 0x01222100;
128
cpu->isar.id_isar0 = 0x0140011;
129
cpu->isar.id_isar1 = 0x12002111;
130
cpu->isar.id_isar2 = 0x11231121;
131
@@ -XXX,XX +XXX,XX @@ static void arm11mpcore_initfn(Object *obj)
132
cpu->id_pfr1 = 0x1;
133
cpu->isar.id_dfr0 = 0;
134
cpu->id_afr0 = 0x2;
135
- cpu->id_mmfr0 = 0x01100103;
136
- cpu->id_mmfr1 = 0x10020302;
137
- cpu->id_mmfr2 = 0x01222000;
138
+ cpu->isar.id_mmfr0 = 0x01100103;
139
+ cpu->isar.id_mmfr1 = 0x10020302;
140
+ cpu->isar.id_mmfr2 = 0x01222000;
141
cpu->isar.id_isar0 = 0x00100011;
142
cpu->isar.id_isar1 = 0x12002111;
143
cpu->isar.id_isar2 = 0x11221011;
144
@@ -XXX,XX +XXX,XX @@ static void cortex_m3_initfn(Object *obj)
145
cpu->id_pfr1 = 0x00000200;
146
cpu->isar.id_dfr0 = 0x00100000;
147
cpu->id_afr0 = 0x00000000;
148
- cpu->id_mmfr0 = 0x00000030;
149
- cpu->id_mmfr1 = 0x00000000;
150
- cpu->id_mmfr2 = 0x00000000;
151
- cpu->id_mmfr3 = 0x00000000;
152
+ cpu->isar.id_mmfr0 = 0x00000030;
153
+ cpu->isar.id_mmfr1 = 0x00000000;
154
+ cpu->isar.id_mmfr2 = 0x00000000;
155
+ cpu->isar.id_mmfr3 = 0x00000000;
156
cpu->isar.id_isar0 = 0x01141110;
157
cpu->isar.id_isar1 = 0x02111000;
158
cpu->isar.id_isar2 = 0x21112231;
159
@@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj)
160
cpu->id_pfr1 = 0x00000200;
161
cpu->isar.id_dfr0 = 0x00100000;
162
cpu->id_afr0 = 0x00000000;
163
- cpu->id_mmfr0 = 0x00000030;
164
- cpu->id_mmfr1 = 0x00000000;
165
- cpu->id_mmfr2 = 0x00000000;
166
- cpu->id_mmfr3 = 0x00000000;
167
+ cpu->isar.id_mmfr0 = 0x00000030;
168
+ cpu->isar.id_mmfr1 = 0x00000000;
169
+ cpu->isar.id_mmfr2 = 0x00000000;
170
+ cpu->isar.id_mmfr3 = 0x00000000;
171
cpu->isar.id_isar0 = 0x01141110;
172
cpu->isar.id_isar1 = 0x02111000;
173
cpu->isar.id_isar2 = 0x21112231;
174
@@ -XXX,XX +XXX,XX @@ static void cortex_m7_initfn(Object *obj)
175
cpu->id_pfr1 = 0x00000200;
176
cpu->isar.id_dfr0 = 0x00100000;
177
cpu->id_afr0 = 0x00000000;
178
- cpu->id_mmfr0 = 0x00100030;
179
- cpu->id_mmfr1 = 0x00000000;
180
- cpu->id_mmfr2 = 0x01000000;
181
- cpu->id_mmfr3 = 0x00000000;
182
+ cpu->isar.id_mmfr0 = 0x00100030;
183
+ cpu->isar.id_mmfr1 = 0x00000000;
184
+ cpu->isar.id_mmfr2 = 0x01000000;
185
+ cpu->isar.id_mmfr3 = 0x00000000;
186
cpu->isar.id_isar0 = 0x01101110;
187
cpu->isar.id_isar1 = 0x02112000;
188
cpu->isar.id_isar2 = 0x20232231;
189
@@ -XXX,XX +XXX,XX @@ static void cortex_m33_initfn(Object *obj)
190
cpu->id_pfr1 = 0x00000210;
191
cpu->isar.id_dfr0 = 0x00200000;
192
cpu->id_afr0 = 0x00000000;
193
- cpu->id_mmfr0 = 0x00101F40;
194
- cpu->id_mmfr1 = 0x00000000;
195
- cpu->id_mmfr2 = 0x01000000;
196
- cpu->id_mmfr3 = 0x00000000;
197
+ cpu->isar.id_mmfr0 = 0x00101F40;
198
+ cpu->isar.id_mmfr1 = 0x00000000;
199
+ cpu->isar.id_mmfr2 = 0x01000000;
200
+ cpu->isar.id_mmfr3 = 0x00000000;
201
cpu->isar.id_isar0 = 0x01101110;
202
cpu->isar.id_isar1 = 0x02212000;
203
cpu->isar.id_isar2 = 0x20232232;
204
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
205
cpu->id_pfr1 = 0x001;
206
cpu->isar.id_dfr0 = 0x010400;
207
cpu->id_afr0 = 0x0;
208
- cpu->id_mmfr0 = 0x0210030;
209
- cpu->id_mmfr1 = 0x00000000;
210
- cpu->id_mmfr2 = 0x01200000;
211
- cpu->id_mmfr3 = 0x0211;
212
+ cpu->isar.id_mmfr0 = 0x0210030;
213
+ cpu->isar.id_mmfr1 = 0x00000000;
214
+ cpu->isar.id_mmfr2 = 0x01200000;
215
+ cpu->isar.id_mmfr3 = 0x0211;
216
cpu->isar.id_isar0 = 0x02101111;
217
cpu->isar.id_isar1 = 0x13112111;
218
cpu->isar.id_isar2 = 0x21232141;
219
@@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj)
220
cpu->id_pfr1 = 0x11;
221
cpu->isar.id_dfr0 = 0x400;
222
cpu->id_afr0 = 0;
223
- cpu->id_mmfr0 = 0x31100003;
224
- cpu->id_mmfr1 = 0x20000000;
225
- cpu->id_mmfr2 = 0x01202000;
226
- cpu->id_mmfr3 = 0x11;
227
+ cpu->isar.id_mmfr0 = 0x31100003;
228
+ cpu->isar.id_mmfr1 = 0x20000000;
229
+ cpu->isar.id_mmfr2 = 0x01202000;
230
+ cpu->isar.id_mmfr3 = 0x11;
231
cpu->isar.id_isar0 = 0x00101111;
232
cpu->isar.id_isar1 = 0x12112111;
233
cpu->isar.id_isar2 = 0x21232031;
234
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
235
cpu->id_pfr1 = 0x11;
236
cpu->isar.id_dfr0 = 0x000;
237
cpu->id_afr0 = 0;
238
- cpu->id_mmfr0 = 0x00100103;
239
- cpu->id_mmfr1 = 0x20000000;
240
- cpu->id_mmfr2 = 0x01230000;
241
- cpu->id_mmfr3 = 0x00002111;
242
+ cpu->isar.id_mmfr0 = 0x00100103;
243
+ cpu->isar.id_mmfr1 = 0x20000000;
244
+ cpu->isar.id_mmfr2 = 0x01230000;
245
+ cpu->isar.id_mmfr3 = 0x00002111;
246
cpu->isar.id_isar0 = 0x00101111;
247
cpu->isar.id_isar1 = 0x13112111;
248
cpu->isar.id_isar2 = 0x21232041;
249
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
250
cpu->id_pfr1 = 0x00011011;
251
cpu->isar.id_dfr0 = 0x02010555;
252
cpu->id_afr0 = 0x00000000;
253
- cpu->id_mmfr0 = 0x10101105;
254
- cpu->id_mmfr1 = 0x40000000;
255
- cpu->id_mmfr2 = 0x01240000;
256
- cpu->id_mmfr3 = 0x02102211;
257
+ cpu->isar.id_mmfr0 = 0x10101105;
258
+ cpu->isar.id_mmfr1 = 0x40000000;
259
+ cpu->isar.id_mmfr2 = 0x01240000;
260
+ cpu->isar.id_mmfr3 = 0x02102211;
261
/* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
262
* table 4-41 gives 0x02101110, which includes the arm div insns.
263
*/
264
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
265
cpu->id_pfr1 = 0x00011011;
266
cpu->isar.id_dfr0 = 0x02010555;
267
cpu->id_afr0 = 0x00000000;
268
- cpu->id_mmfr0 = 0x10201105;
269
- cpu->id_mmfr1 = 0x20000000;
270
- cpu->id_mmfr2 = 0x01240000;
271
- cpu->id_mmfr3 = 0x02102211;
272
+ cpu->isar.id_mmfr0 = 0x10201105;
273
+ cpu->isar.id_mmfr1 = 0x20000000;
274
+ cpu->isar.id_mmfr2 = 0x01240000;
275
+ cpu->isar.id_mmfr3 = 0x02102211;
276
cpu->isar.id_isar0 = 0x02101110;
277
cpu->isar.id_isar1 = 0x13112111;
278
cpu->isar.id_isar2 = 0x21232041;
279
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
280
t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
281
cpu->isar.mvfr2 = t;
282
283
- t = cpu->id_mmfr3;
284
+ t = cpu->isar.id_mmfr3;
285
t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
286
- cpu->id_mmfr3 = t;
287
+ cpu->isar.id_mmfr3 = t;
288
289
- t = cpu->id_mmfr4;
290
+ t = cpu->isar.id_mmfr4;
291
t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
292
- cpu->id_mmfr4 = t;
293
+ cpu->isar.id_mmfr4 = t;
294
}
295
#endif
296
}
49
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
297
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
50
index XXXXXXX..XXXXXXX 100644
298
index XXXXXXX..XXXXXXX 100644
51
--- a/target/arm/cpu64.c
299
--- a/target/arm/cpu64.c
52
+++ b/target/arm/cpu64.c
300
+++ b/target/arm/cpu64.c
53
@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
301
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
54
* restriction allows us to avoid fixing up functionality that assumes a
302
cpu->id_pfr1 = 0x00011011;
55
* uniform execution state like do_interrupt.
303
cpu->isar.id_dfr0 = 0x03010066;
304
cpu->id_afr0 = 0x00000000;
305
- cpu->id_mmfr0 = 0x10101105;
306
- cpu->id_mmfr1 = 0x40000000;
307
- cpu->id_mmfr2 = 0x01260000;
308
- cpu->id_mmfr3 = 0x02102211;
309
+ cpu->isar.id_mmfr0 = 0x10101105;
310
+ cpu->isar.id_mmfr1 = 0x40000000;
311
+ cpu->isar.id_mmfr2 = 0x01260000;
312
+ cpu->isar.id_mmfr3 = 0x02102211;
313
cpu->isar.id_isar0 = 0x02101110;
314
cpu->isar.id_isar1 = 0x13112111;
315
cpu->isar.id_isar2 = 0x21232042;
316
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
317
cpu->id_pfr1 = 0x00011011;
318
cpu->isar.id_dfr0 = 0x03010066;
319
cpu->id_afr0 = 0x00000000;
320
- cpu->id_mmfr0 = 0x10101105;
321
- cpu->id_mmfr1 = 0x40000000;
322
- cpu->id_mmfr2 = 0x01260000;
323
- cpu->id_mmfr3 = 0x02102211;
324
+ cpu->isar.id_mmfr0 = 0x10101105;
325
+ cpu->isar.id_mmfr1 = 0x40000000;
326
+ cpu->isar.id_mmfr2 = 0x01260000;
327
+ cpu->isar.id_mmfr3 = 0x02102211;
328
cpu->isar.id_isar0 = 0x02101110;
329
cpu->isar.id_isar1 = 0x13112111;
330
cpu->isar.id_isar2 = 0x21232042;
331
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
332
cpu->id_pfr1 = 0x00011011;
333
cpu->isar.id_dfr0 = 0x03010066;
334
cpu->id_afr0 = 0x00000000;
335
- cpu->id_mmfr0 = 0x10201105;
336
- cpu->id_mmfr1 = 0x40000000;
337
- cpu->id_mmfr2 = 0x01260000;
338
- cpu->id_mmfr3 = 0x02102211;
339
+ cpu->isar.id_mmfr0 = 0x10201105;
340
+ cpu->isar.id_mmfr1 = 0x40000000;
341
+ cpu->isar.id_mmfr2 = 0x01260000;
342
+ cpu->isar.id_mmfr3 = 0x02102211;
343
cpu->isar.id_isar0 = 0x02101110;
344
cpu->isar.id_isar1 = 0x13112111;
345
cpu->isar.id_isar2 = 0x21232042;
346
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
347
u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
348
cpu->isar.id_isar6 = u;
349
350
- u = cpu->id_mmfr3;
351
+ u = cpu->isar.id_mmfr3;
352
u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
353
- cpu->id_mmfr3 = u;
354
+ cpu->isar.id_mmfr3 = u;
355
356
u = cpu->isar.id_aa64dfr0;
357
u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
358
diff --git a/target/arm/helper.c b/target/arm/helper.c
359
index XXXXXXX..XXXXXXX 100644
360
--- a/target/arm/helper.c
361
+++ b/target/arm/helper.c
362
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
363
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
364
.access = PL1_R, .type = ARM_CP_CONST,
365
.accessfn = access_aa32_tid3,
366
- .resetvalue = cpu->id_mmfr0 },
367
+ .resetvalue = cpu->isar.id_mmfr0 },
368
{ .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
369
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
370
.access = PL1_R, .type = ARM_CP_CONST,
371
.accessfn = access_aa32_tid3,
372
- .resetvalue = cpu->id_mmfr1 },
373
+ .resetvalue = cpu->isar.id_mmfr1 },
374
{ .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
375
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
376
.access = PL1_R, .type = ARM_CP_CONST,
377
.accessfn = access_aa32_tid3,
378
- .resetvalue = cpu->id_mmfr2 },
379
+ .resetvalue = cpu->isar.id_mmfr2 },
380
{ .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
381
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
382
.access = PL1_R, .type = ARM_CP_CONST,
383
.accessfn = access_aa32_tid3,
384
- .resetvalue = cpu->id_mmfr3 },
385
+ .resetvalue = cpu->isar.id_mmfr3 },
386
{ .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
387
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
388
.access = PL1_R, .type = ARM_CP_CONST,
389
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
390
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
391
.access = PL1_R, .type = ARM_CP_CONST,
392
.accessfn = access_aa32_tid3,
393
- .resetvalue = cpu->id_mmfr4 },
394
+ .resetvalue = cpu->isar.id_mmfr4 },
395
{ .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
396
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
397
.access = PL1_R, .type = ARM_CP_CONST,
398
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
399
define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
400
define_arm_cp_regs(cpu, vmsa_cp_reginfo);
401
/* TTCBR2 is introduced with ARMv8.2-A32HPD. */
402
- if (FIELD_EX32(cpu->id_mmfr4, ID_MMFR4, HPDS) != 0) {
403
+ if (FIELD_EX32(cpu->isar.id_mmfr4, ID_MMFR4, HPDS) != 0) {
404
define_one_arm_cp_reg(cpu, &ttbcr2_reginfo);
405
}
406
}
407
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
408
index XXXXXXX..XXXXXXX 100644
409
--- a/target/arm/kvm32.c
410
+++ b/target/arm/kvm32.c
411
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
412
* Fortunately there is not yet anything in there that affects migration.
56
*/
413
*/
57
- if (!kvm_enabled()) {
414
58
- error_setg(errp, "'aarch64' feature cannot be disabled "
415
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
59
- "unless KVM is enabled");
416
+ ARM_CP15_REG32(0, 0, 1, 4));
60
- return;
417
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1,
61
- }
418
+ ARM_CP15_REG32(0, 0, 1, 5));
62
-
419
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2,
63
if (value == false) {
420
+ ARM_CP15_REG32(0, 0, 1, 6));
64
+ if (!kvm_enabled() || !kvm_arm_aarch32_supported(CPU(cpu))) {
421
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3,
65
+ error_setg(errp, "'aarch64' feature cannot be disabled "
422
+ ARM_CP15_REG32(0, 0, 1, 7));
66
+ "unless KVM is enabled and 32-bit EL1 "
423
+ if (read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4,
67
+ "is supported");
424
+ ARM_CP15_REG32(0, 0, 2, 6))) {
68
+ return;
425
+ /*
69
+ }
426
+ * Older kernels don't support reading ID_MMFR4 (a new in v8
70
unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
427
+ * register); assume it's zero.
71
} else {
428
+ */
72
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
429
+ ahcf->isar.id_mmfr4 = 0;
430
+ }
431
+
432
/*
433
* There is no way to read DBGDIDR, because currently 32-bit KVM
434
* doesn't implement debug at all. Leave it at zero.
73
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
435
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
74
index XXXXXXX..XXXXXXX 100644
436
index XXXXXXX..XXXXXXX 100644
75
--- a/target/arm/kvm64.c
437
--- a/target/arm/kvm64.c
76
+++ b/target/arm/kvm64.c
438
+++ b/target/arm/kvm64.c
77
@@ -XXX,XX +XXX,XX @@
78
#include "exec/gdbstub.h"
79
#include "sysemu/sysemu.h"
80
#include "sysemu/kvm.h"
81
+#include "sysemu/kvm_int.h"
82
#include "kvm_arm.h"
83
+#include "hw/boards.h"
84
#include "internals.h"
85
86
static bool have_guest_debug;
87
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
439
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
88
return true;
440
*/
89
}
441
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
90
442
ARM64_SYS_REG(3, 0, 0, 1, 2));
91
+bool kvm_arm_aarch32_supported(CPUState *cpu)
443
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
92
+{
444
+ ARM64_SYS_REG(3, 0, 0, 1, 4));
93
+ KVMState *s = KVM_STATE(current_machine->accelerator);
445
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1,
94
+
446
+ ARM64_SYS_REG(3, 0, 0, 1, 5));
95
+ return kvm_check_extension(s, KVM_CAP_ARM_EL1_32BIT);
447
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2,
96
+}
448
+ ARM64_SYS_REG(3, 0, 0, 1, 6));
97
+
449
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3,
98
#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
450
+ ARM64_SYS_REG(3, 0, 0, 1, 7));
99
451
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
100
int kvm_arch_init_vcpu(CPUState *cs)
452
ARM64_SYS_REG(3, 0, 0, 2, 0));
453
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
454
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
455
ARM64_SYS_REG(3, 0, 0, 2, 4));
456
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
457
ARM64_SYS_REG(3, 0, 0, 2, 5));
458
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4,
459
+ ARM64_SYS_REG(3, 0, 0, 2, 6));
460
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
461
ARM64_SYS_REG(3, 0, 0, 2, 7));
462
101
--
463
--
102
2.20.1
464
2.20.1
103
465
104
466
diff view generated by jsdifflib
New patch
[PULL 32/52] target/arm: Use isar_feature function for testing AA32HPD feature
1
Now we have moved ID_MMFR4 into the ARMISARegisters struct, we
2
can define and use an isar_feature for the presence of the
3
ARMv8.2-AA32HPD feature, rather than open-coding the test.
1
4
5
While we're here, correct a comment typo which missed an 'A'
6
from the feature name.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200214175116.9164-20-peter.maydell@linaro.org
11
---
12
target/arm/cpu.h | 5 +++++
13
target/arm/helper.c | 4 ++--
14
2 files changed, 7 insertions(+), 2 deletions(-)
15
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id)
21
FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
22
}
23
24
+static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
25
+{
26
+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
27
+}
28
+
29
/*
30
* 64-bit feature tests via id registers.
31
*/
32
diff --git a/target/arm/helper.c b/target/arm/helper.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/helper.c
35
+++ b/target/arm/helper.c
36
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
37
} else {
38
define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
39
define_arm_cp_regs(cpu, vmsa_cp_reginfo);
40
- /* TTCBR2 is introduced with ARMv8.2-A32HPD. */
41
- if (FIELD_EX32(cpu->isar.id_mmfr4, ID_MMFR4, HPDS) != 0) {
42
+ /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
43
+ if (cpu_isar_feature(aa32_hpd, cpu)) {
44
define_one_arm_cp_reg(cpu, &ttbcr2_reginfo);
45
}
46
}
47
--
48
2.20.1
49
50
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/29] target/arm: Factor out 'generate singlestep exception' function
[PULL 33/52] target/arm: Use FIELD_EX32 for testing 32-bit fields
1
Factor out code to 'generate a singlestep exception', which is
1
Cut-and-paste errors mean we're using FIELD_EX64() to extract fields from
2
currently repeated in four places.
2
some 32-bit ID register fields. Use FIELD_EX32() instead. (This makes
3
3
no difference in behaviour, it's just more consistent.)
4
To do this we need to also pull the identical copies of the
5
gen-exception() function out of translate-a64.c and translate.c
6
into translate.h.
7
8
(There is a bug in the code: we're taking the exception to the wrong
9
target EL. This will be simpler to fix if there's only one place to
10
do it.)
11
4
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20200214175116.9164-21-peter.maydell@linaro.org
15
Message-id: 20190805130952.4415-2-peter.maydell@linaro.org
16
---
8
---
17
target/arm/translate.h | 23 +++++++++++++++++++++++
9
target/arm/cpu.h | 18 +++++++++---------
18
target/arm/translate-a64.c | 19 ++-----------------
10
1 file changed, 9 insertions(+), 9 deletions(-)
19
target/arm/translate.c | 20 ++------------------
20
3 files changed, 27 insertions(+), 35 deletions(-)
21
11
22
diff --git a/target/arm/translate.h b/target/arm/translate.h
12
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
23
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/translate.h
14
--- a/target/arm/cpu.h
25
+++ b/target/arm/translate.h
15
+++ b/target/arm/cpu.h
26
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
27
#define TARGET_ARM_TRANSLATE_H
17
static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id)
28
18
{
29
#include "exec/translator.h"
19
/* Return true if D16-D31 are implemented */
30
+#include "internals.h"
20
- return FIELD_EX64(id->mvfr0, MVFR0, SIMDREG) >= 2;
31
21
+ return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
32
33
/* internal defines */
34
@@ -XXX,XX +XXX,XX @@ static inline void gen_ss_advance(DisasContext *s)
35
}
36
}
22
}
37
23
38
+static inline void gen_exception(int excp, uint32_t syndrome,
24
static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
39
+ uint32_t target_el)
25
{
40
+{
26
- return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0;
41
+ TCGv_i32 tcg_excp = tcg_const_i32(excp);
27
+ return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
42
+ TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
28
}
43
+ TCGv_i32 tcg_el = tcg_const_i32(target_el);
29
44
+
30
static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
45
+ gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
31
{
46
+ tcg_syn, tcg_el);
32
/* Return true if CPU supports double precision floating point */
47
+
33
- return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0;
48
+ tcg_temp_free_i32(tcg_el);
34
+ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
49
+ tcg_temp_free_i32(tcg_syn);
35
}
50
+ tcg_temp_free_i32(tcg_excp);
36
51
+}
52
+
53
+/* Generate an architectural singlestep exception */
54
+static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
55
+{
56
+ gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, isv, ex),
57
+ default_exception_el(s));
58
+}
59
+
60
/*
37
/*
61
* Given a VFP floating point constant encoded into an 8 bit immediate in an
38
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
62
* instruction, expand it to the actual constant value of the specified
39
*/
63
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
40
static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
64
index XXXXXXX..XXXXXXX 100644
41
{
65
--- a/target/arm/translate-a64.c
42
- return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0;
66
+++ b/target/arm/translate-a64.c
43
+ return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;
67
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
68
tcg_temp_free_i32(tcg_excp);
69
}
44
}
70
45
71
-static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el)
46
static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
72
-{
73
- TCGv_i32 tcg_excp = tcg_const_i32(excp);
74
- TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
75
- TCGv_i32 tcg_el = tcg_const_i32(target_el);
76
-
77
- gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
78
- tcg_syn, tcg_el);
79
- tcg_temp_free_i32(tcg_el);
80
- tcg_temp_free_i32(tcg_syn);
81
- tcg_temp_free_i32(tcg_excp);
82
-}
83
-
84
static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
85
{
47
{
86
gen_a64_set_pc_im(s->pc - offset);
48
- return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1;
87
@@ -XXX,XX +XXX,XX @@ static void gen_step_complete_exception(DisasContext *s)
49
+ return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
88
* of the exception, and our syndrome information is always correct.
89
*/
90
gen_ss_advance(s);
91
- gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex),
92
- default_exception_el(s));
93
+ gen_swstep_exception(s, 1, s->is_ldex);
94
s->base.is_jmp = DISAS_NORETURN;
95
}
50
}
96
51
97
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
52
static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
98
* bits should be zero.
53
{
99
*/
54
- return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1;
100
assert(dc->base.num_insns == 1);
55
+ return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
101
- gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),
102
- default_exception_el(dc));
103
+ gen_swstep_exception(dc, 0, 0);
104
dc->base.is_jmp = DISAS_NORETURN;
105
} else {
106
disas_a64_insn(env, dc);
107
diff --git a/target/arm/translate.c b/target/arm/translate.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/target/arm/translate.c
110
+++ b/target/arm/translate.c
111
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
112
tcg_temp_free_i32(tcg_excp);
113
}
56
}
114
57
115
-static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el)
58
static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
116
-{
117
- TCGv_i32 tcg_excp = tcg_const_i32(excp);
118
- TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
119
- TCGv_i32 tcg_el = tcg_const_i32(target_el);
120
-
121
- gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
122
- tcg_syn, tcg_el);
123
-
124
- tcg_temp_free_i32(tcg_el);
125
- tcg_temp_free_i32(tcg_syn);
126
- tcg_temp_free_i32(tcg_excp);
127
-}
128
-
129
static void gen_step_complete_exception(DisasContext *s)
130
{
59
{
131
/* We just completed step of an insn. Move from Active-not-pending
60
- return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2;
132
@@ -XXX,XX +XXX,XX @@ static void gen_step_complete_exception(DisasContext *s)
61
+ return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;
133
* of the exception, and our syndrome information is always correct.
134
*/
135
gen_ss_advance(s);
136
- gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex),
137
- default_exception_el(s));
138
+ gen_swstep_exception(s, 1, s->is_ldex);
139
s->base.is_jmp = DISAS_NORETURN;
140
}
62
}
141
63
142
@@ -XXX,XX +XXX,XX @@ static bool arm_pre_translate_insn(DisasContext *dc)
64
static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
143
* bits should be zero.
65
{
144
*/
66
- return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3;
145
assert(dc->base.num_insns == 1);
67
+ return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;
146
- gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),
68
}
147
- default_exception_el(dc));
69
148
+ gen_swstep_exception(dc, 0, 0);
70
static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
149
dc->base.is_jmp = DISAS_NORETURN;
71
{
150
return true;
72
- return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4;
151
}
73
+ return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
74
}
75
76
static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
152
--
77
--
153
2.20.1
78
2.20.1
154
79
155
80
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/29] target/arm: generate a custom MIDR for -cpu max
[PULL 34/52] target/arm: Correctly implement ACTLR2, HACTLR2
1
From: Alex Bennée <alex.bennee@linaro.org>
1
The ACTLR2 and HACTLR2 AArch32 system registers didn't exist in ARMv7
2
or the original ARMv8. They were later added as optional registers,
3
whose presence is signaled by the ID_MMFR4.AC2 field. From ARMv8.2
4
they are mandatory (ie ID_MMFR4.AC2 must be non-zero).
2
5
3
While most features are now detected by probing the ID_* registers
6
We implemented HACTLR2 in commit 0e0456ab8895a5e85, but we
4
kernels can (and do) use MIDR_EL1 for working out of they have to
7
incorrectly made it exist for all v8 CPUs, and we didn't implement
5
apply errata. This can trip up warnings in the kernel as it tries to
8
ACTLR2 at all.
6
work out if it should apply workarounds to features that don't
7
actually exist in the reported CPU type.
8
9
9
Avoid this problem by synthesising our own MIDR value.
10
Sort this out by implementing both registers only when they are
11
supposed to exist, and setting the ID_MMFR4 bit for -cpu max.
10
12
11
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
13
Note that this removes HACTLR2 from our Cortex-A53, -A47 and -A72
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
CPU models; this is correct, because those CPUs do not implement
15
this register.
16
17
Fixes: 0e0456ab8895a5e85
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20190726113950.7499-1-alex.bennee@linaro.org
20
Message-id: 20200214175116.9164-22-peter.maydell@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
21
---
17
target/arm/cpu.h | 6 ++++++
22
target/arm/cpu.h | 5 +++++
18
target/arm/cpu64.c | 19 +++++++++++++++++++
23
target/arm/cpu.c | 1 +
19
2 files changed, 25 insertions(+)
24
target/arm/cpu64.c | 4 ++++
25
target/arm/helper.c | 32 +++++++++++++++++++++++---------
26
4 files changed, 33 insertions(+), 9 deletions(-)
20
27
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
28
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
22
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.h
30
--- a/target/arm/cpu.h
24
+++ b/target/arm/cpu.h
31
+++ b/target/arm/cpu.h
25
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
32
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
33
return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
34
}
35
36
+static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
37
+{
38
+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
39
+}
40
+
26
/*
41
/*
27
* System register ID fields.
42
* 64-bit feature tests via id registers.
28
*/
43
*/
29
+FIELD(MIDR_EL1, REVISION, 0, 4)
44
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
30
+FIELD(MIDR_EL1, PARTNUM, 4, 12)
45
index XXXXXXX..XXXXXXX 100644
31
+FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
46
--- a/target/arm/cpu.c
32
+FIELD(MIDR_EL1, VARIANT, 20, 4)
47
+++ b/target/arm/cpu.c
33
+FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
48
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
34
+
49
35
FIELD(ID_ISAR0, SWAP, 0, 4)
50
t = cpu->isar.id_mmfr4;
36
FIELD(ID_ISAR0, BITCOUNT, 4, 4)
51
t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
37
FIELD(ID_ISAR0, BITFIELD, 8, 4)
52
+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
53
cpu->isar.id_mmfr4 = t;
54
}
55
#endif
38
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
56
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
39
index XXXXXXX..XXXXXXX 100644
57
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/cpu64.c
58
--- a/target/arm/cpu64.c
41
+++ b/target/arm/cpu64.c
59
+++ b/target/arm/cpu64.c
42
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
60
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
43
uint32_t u;
61
u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
44
aarch64_a57_initfn(obj);
62
cpu->isar.id_mmfr3 = u;
45
63
46
+ /*
64
+ u = cpu->isar.id_mmfr4;
47
+ * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
65
+ u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
48
+ * one and try to apply errata workarounds or use impdef features we
66
+ cpu->isar.id_mmfr4 = u;
49
+ * don't provide.
50
+ * An IMPLEMENTER field of 0 means "reserved for software use";
51
+ * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
52
+ * to see which features are present";
53
+ * the VARIANT, PARTNUM and REVISION fields are all implementation
54
+ * defined and we choose to define PARTNUM just in case guest
55
+ * code needs to distinguish this QEMU CPU from other software
56
+ * implementations, though this shouldn't be needed.
57
+ */
58
+ t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
59
+ t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
60
+ t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
61
+ t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
62
+ t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
63
+ cpu->midr = t;
64
+
67
+
65
t = cpu->isar.id_aa64isar0;
68
u = cpu->isar.id_aa64dfr0;
66
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
69
u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
67
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
70
cpu->isar.id_aa64dfr0 = u;
71
diff --git a/target/arm/helper.c b/target/arm/helper.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/helper.c
74
+++ b/target/arm/helper.c
75
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1cp_reginfo[] = {
76
};
77
#endif
78
79
+/*
80
+ * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
81
+ * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
82
+ * is non-zero, which is never for ARMv7, optionally in ARMv8
83
+ * and mandatorily for ARMv8.2 and up.
84
+ * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
85
+ * implementation is RAZ/WI we can ignore this detail, as we
86
+ * do for ACTLR.
87
+ */
88
+static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = {
89
+ { .name = "ACTLR2", .state = ARM_CP_STATE_AA32,
90
+ .cp = 15, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 3,
91
+ .access = PL1_RW, .type = ARM_CP_CONST,
92
+ .resetvalue = 0 },
93
+ { .name = "HACTLR2", .state = ARM_CP_STATE_AA32,
94
+ .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
95
+ .access = PL2_RW, .type = ARM_CP_CONST,
96
+ .resetvalue = 0 },
97
+ REGINFO_SENTINEL
98
+};
99
+
100
void register_cp_regs_for_features(ARMCPU *cpu)
101
{
102
/* Register all the coprocessor registers based on feature bits */
103
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
104
REGINFO_SENTINEL
105
};
106
define_arm_cp_regs(cpu, auxcr_reginfo);
107
- if (arm_feature(env, ARM_FEATURE_V8)) {
108
- /* HACTLR2 maps to ACTLR_EL2[63:32] and is not in ARMv7 */
109
- ARMCPRegInfo hactlr2_reginfo = {
110
- .name = "HACTLR2", .state = ARM_CP_STATE_AA32,
111
- .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
112
- .access = PL2_RW, .type = ARM_CP_CONST,
113
- .resetvalue = 0
114
- };
115
- define_one_arm_cp_reg(cpu, &hactlr2_reginfo);
116
+ if (cpu_isar_feature(aa32_ac2, cpu)) {
117
+ define_arm_cp_regs(cpu, actlr2_hactlr2_reginfo);
118
}
119
}
120
68
--
121
--
69
2.20.1
122
2.20.1
70
123
71
124
diff view generated by jsdifflib
New patch
[PULL 35/52] hw: usb: hcd-ohci: Move OHCISysBusState and TYPE_SYSBUS_OHCI to include file
1
From: Guenter Roeck <linux@roeck-us.net>
1
2
3
We need to be able to use OHCISysBusState outside hcd-ohci.c, so move it
4
to its include file.
5
6
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
9
Message-id: 20200217204812.9857-2-linux@roeck-us.net
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/usb/hcd-ohci.h | 16 ++++++++++++++++
13
hw/usb/hcd-ohci.c | 15 ---------------
14
2 files changed, 16 insertions(+), 15 deletions(-)
15
16
diff --git a/hw/usb/hcd-ohci.h b/hw/usb/hcd-ohci.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/usb/hcd-ohci.h
19
+++ b/hw/usb/hcd-ohci.h
20
@@ -XXX,XX +XXX,XX @@
21
#define HCD_OHCI_H
22
23
#include "sysemu/dma.h"
24
+#include "hw/usb.h"
25
26
/* Number of Downstream Ports on the root hub: */
27
#define OHCI_MAX_PORTS 15
28
@@ -XXX,XX +XXX,XX @@ typedef struct OHCIState {
29
void (*ohci_die)(struct OHCIState *ohci);
30
} OHCIState;
31
32
+#define TYPE_SYSBUS_OHCI "sysbus-ohci"
33
+#define SYSBUS_OHCI(obj) OBJECT_CHECK(OHCISysBusState, (obj), TYPE_SYSBUS_OHCI)
34
+
35
+typedef struct {
36
+ /*< private >*/
37
+ SysBusDevice parent_obj;
38
+ /*< public >*/
39
+
40
+ OHCIState ohci;
41
+ char *masterbus;
42
+ uint32_t num_ports;
43
+ uint32_t firstport;
44
+ dma_addr_t dma_offset;
45
+} OHCISysBusState;
46
+
47
extern const VMStateDescription vmstate_ohci_state;
48
49
void usb_ohci_init(OHCIState *ohci, DeviceState *dev, uint32_t num_ports,
50
diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/hw/usb/hcd-ohci.c
53
+++ b/hw/usb/hcd-ohci.c
54
@@ -XXX,XX +XXX,XX @@ void ohci_sysbus_die(struct OHCIState *ohci)
55
ohci_bus_stop(ohci);
56
}
57
58
-#define TYPE_SYSBUS_OHCI "sysbus-ohci"
59
-#define SYSBUS_OHCI(obj) OBJECT_CHECK(OHCISysBusState, (obj), TYPE_SYSBUS_OHCI)
60
-
61
-typedef struct {
62
- /*< private >*/
63
- SysBusDevice parent_obj;
64
- /*< public >*/
65
-
66
- OHCIState ohci;
67
- char *masterbus;
68
- uint32_t num_ports;
69
- uint32_t firstport;
70
- dma_addr_t dma_offset;
71
-} OHCISysBusState;
72
-
73
static void ohci_realize_pxa(DeviceState *dev, Error **errp)
74
{
75
OHCISysBusState *s = SYSBUS_OHCI(dev);
76
--
77
2.20.1
78
79
diff view generated by jsdifflib
New patch
[PULL 36/52] hcd-ehci: Introduce "companion-enable" sysbus property
1
From: Guenter Roeck <linux@roeck-us.net>
1
2
3
We'll use this property in a follow-up patch to insantiate an EHCI
4
bus with companion support.
5
6
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
9
Message-id: 20200217204812.9857-3-linux@roeck-us.net
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/usb/hcd-ehci-sysbus.c | 2 ++
13
1 file changed, 2 insertions(+)
14
15
diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/usb/hcd-ehci-sysbus.c
18
+++ b/hw/usb/hcd-ehci-sysbus.c
19
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ehci_sysbus = {
20
21
static Property ehci_sysbus_properties[] = {
22
DEFINE_PROP_UINT32("maxframes", EHCISysBusState, ehci.maxframes, 128),
23
+ DEFINE_PROP_BOOL("companion-enable", EHCISysBusState, ehci.companion_enable,
24
+ false),
25
DEFINE_PROP_END_OF_LIST(),
26
};
27
28
--
29
2.20.1
30
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/29] hw/misc/zynq_slcr: use standard register definition
[PULL 37/52] arm: allwinner: Wire up USB ports
1
From: Damien Hedde <damien.hedde@greensocs.com>
1
From: Guenter Roeck <linux@roeck-us.net>
2
2
3
Replace the zynq_slcr registers enum and macros using the
3
Instantiate EHCI and OHCI controllers on Allwinner A10. OHCI ports are
4
hw/registerfields.h macros.
4
modeled as companions of the respective EHCI ports.
5
5
6
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
6
With this patch applied, USB controllers are discovered and instantiated
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
when booting the cubieboard machine with a recent Linux kernel.
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
9
Message-id: 20190729145654.14644-30-damien.hedde@greensocs.com
9
ehci-platform 1c14000.usb: EHCI Host Controller
10
ehci-platform 1c14000.usb: new USB bus registered, assigned bus number 1
11
ehci-platform 1c14000.usb: irq 26, io mem 0x01c14000
12
ehci-platform 1c14000.usb: USB 2.0 started, EHCI 1.00
13
ehci-platform 1c1c000.usb: EHCI Host Controller
14
ehci-platform 1c1c000.usb: new USB bus registered, assigned bus number 2
15
ehci-platform 1c1c000.usb: irq 31, io mem 0x01c1c000
16
ehci-platform 1c1c000.usb: USB 2.0 started, EHCI 1.00
17
ohci-platform 1c14400.usb: Generic Platform OHCI controller
18
ohci-platform 1c14400.usb: new USB bus registered, assigned bus number 3
19
ohci-platform 1c14400.usb: irq 27, io mem 0x01c14400
20
ohci-platform 1c1c400.usb: Generic Platform OHCI controller
21
ohci-platform 1c1c400.usb: new USB bus registered, assigned bus number 4
22
ohci-platform 1c1c400.usb: irq 32, io mem 0x01c1c400
23
usb 2-1: new high-speed USB device number 2 using ehci-platform
24
usb-storage 2-1:1.0: USB Mass Storage device detected
25
scsi host1: usb-storage 2-1:1.0
26
usb 3-1: new full-speed USB device number 2 using ohci-platform
27
input: QEMU QEMU USB Mouse as /devices/platform/soc/1c14400.usb/usb3/3-1/3-1:1.0/0003:0627:0001.0001/input/input0
28
29
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
30
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
31
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
32
Message-id: 20200217204812.9857-4-linux@roeck-us.net
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
34
---
12
hw/misc/zynq_slcr.c | 450 ++++++++++++++++++++++----------------------
35
include/hw/arm/allwinner-a10.h | 6 +++++
13
1 file changed, 225 insertions(+), 225 deletions(-)
36
hw/arm/allwinner-a10.c | 43 ++++++++++++++++++++++++++++++++++
37
2 files changed, 49 insertions(+)
14
38
15
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
39
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
16
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/misc/zynq_slcr.c
41
--- a/include/hw/arm/allwinner-a10.h
18
+++ b/hw/misc/zynq_slcr.c
42
+++ b/include/hw/arm/allwinner-a10.h
19
@@ -XXX,XX +XXX,XX @@
43
@@ -XXX,XX +XXX,XX @@
44
#include "hw/intc/allwinner-a10-pic.h"
45
#include "hw/net/allwinner_emac.h"
46
#include "hw/ide/ahci.h"
47
+#include "hw/usb/hcd-ohci.h"
48
+#include "hw/usb/hcd-ehci.h"
49
50
#include "target/arm/cpu.h"
51
52
53
#define AW_A10_SDRAM_BASE 0x40000000
54
55
+#define AW_A10_NUM_USB 2
56
+
57
#define TYPE_AW_A10 "allwinner-a10"
58
#define AW_A10(obj) OBJECT_CHECK(AwA10State, (obj), TYPE_AW_A10)
59
60
@@ -XXX,XX +XXX,XX @@ typedef struct AwA10State {
61
AwEmacState emac;
62
AllwinnerAHCIState sata;
63
MemoryRegion sram_a;
64
+ EHCISysBusState ehci[AW_A10_NUM_USB];
65
+ OHCISysBusState ohci[AW_A10_NUM_USB];
66
} AwA10State;
67
68
#endif
69
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/hw/arm/allwinner-a10.c
72
+++ b/hw/arm/allwinner-a10.c
73
@@ -XXX,XX +XXX,XX @@
74
#include "hw/arm/allwinner-a10.h"
75
#include "hw/misc/unimp.h"
20
#include "sysemu/sysemu.h"
76
#include "sysemu/sysemu.h"
21
#include "qemu/log.h"
77
+#include "hw/boards.h"
22
#include "qemu/module.h"
78
+#include "hw/usb/hcd-ohci.h"
23
+#include "hw/registerfields.h"
79
24
80
#define AW_A10_PIC_REG_BASE 0x01c20400
25
#ifndef ZYNQ_SLCR_ERR_DEBUG
81
#define AW_A10_PIT_REG_BASE 0x01c20c00
26
#define ZYNQ_SLCR_ERR_DEBUG 0
82
#define AW_A10_UART0_REG_BASE 0x01c28000
27
@@ -XXX,XX +XXX,XX @@
83
#define AW_A10_EMAC_BASE 0x01c0b000
28
#define XILINX_LOCK_KEY 0x767b
84
+#define AW_A10_EHCI_BASE 0x01c14000
29
#define XILINX_UNLOCK_KEY 0xdf0d
85
+#define AW_A10_OHCI_BASE 0x01c14400
30
86
#define AW_A10_SATA_BASE 0x01c18000
31
-#define R_PSS_RST_CTRL_SOFT_RST 0x1
87
32
+REG32(SCL, 0x000)
88
static void aw_a10_init(Object *obj)
33
+REG32(LOCK, 0x004)
89
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
34
+REG32(UNLOCK, 0x008)
90
35
+REG32(LOCKSTA, 0x00c)
91
sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata),
36
92
TYPE_ALLWINNER_AHCI);
37
-enum {
93
+
38
- SCL = 0x000 / 4,
94
+ if (machine_usb(current_machine)) {
39
- LOCK,
95
+ int i;
40
- UNLOCK,
96
+
41
- LOCKSTA,
97
+ for (i = 0; i < AW_A10_NUM_USB; i++) {
42
+REG32(ARM_PLL_CTRL, 0x100)
98
+ sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]),
43
+REG32(DDR_PLL_CTRL, 0x104)
99
+ sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
44
+REG32(IO_PLL_CTRL, 0x108)
100
+ sysbus_init_child_obj(obj, "ohci[*]", OBJECT(&s->ohci[i]),
45
+REG32(PLL_STATUS, 0x10c)
101
+ sizeof(s->ohci[i]), TYPE_SYSBUS_OHCI);
46
+REG32(ARM_PLL_CFG, 0x110)
102
+ }
47
+REG32(DDR_PLL_CFG, 0x114)
103
+ }
48
+REG32(IO_PLL_CFG, 0x118)
49
50
- ARM_PLL_CTRL = 0x100 / 4,
51
- DDR_PLL_CTRL,
52
- IO_PLL_CTRL,
53
- PLL_STATUS,
54
- ARM_PLL_CFG,
55
- DDR_PLL_CFG,
56
- IO_PLL_CFG,
57
-
58
- ARM_CLK_CTRL = 0x120 / 4,
59
- DDR_CLK_CTRL,
60
- DCI_CLK_CTRL,
61
- APER_CLK_CTRL,
62
- USB0_CLK_CTRL,
63
- USB1_CLK_CTRL,
64
- GEM0_RCLK_CTRL,
65
- GEM1_RCLK_CTRL,
66
- GEM0_CLK_CTRL,
67
- GEM1_CLK_CTRL,
68
- SMC_CLK_CTRL,
69
- LQSPI_CLK_CTRL,
70
- SDIO_CLK_CTRL,
71
- UART_CLK_CTRL,
72
- SPI_CLK_CTRL,
73
- CAN_CLK_CTRL,
74
- CAN_MIOCLK_CTRL,
75
- DBG_CLK_CTRL,
76
- PCAP_CLK_CTRL,
77
- TOPSW_CLK_CTRL,
78
+REG32(ARM_CLK_CTRL, 0x120)
79
+REG32(DDR_CLK_CTRL, 0x124)
80
+REG32(DCI_CLK_CTRL, 0x128)
81
+REG32(APER_CLK_CTRL, 0x12c)
82
+REG32(USB0_CLK_CTRL, 0x130)
83
+REG32(USB1_CLK_CTRL, 0x134)
84
+REG32(GEM0_RCLK_CTRL, 0x138)
85
+REG32(GEM1_RCLK_CTRL, 0x13c)
86
+REG32(GEM0_CLK_CTRL, 0x140)
87
+REG32(GEM1_CLK_CTRL, 0x144)
88
+REG32(SMC_CLK_CTRL, 0x148)
89
+REG32(LQSPI_CLK_CTRL, 0x14c)
90
+REG32(SDIO_CLK_CTRL, 0x150)
91
+REG32(UART_CLK_CTRL, 0x154)
92
+REG32(SPI_CLK_CTRL, 0x158)
93
+REG32(CAN_CLK_CTRL, 0x15c)
94
+REG32(CAN_MIOCLK_CTRL, 0x160)
95
+REG32(DBG_CLK_CTRL, 0x164)
96
+REG32(PCAP_CLK_CTRL, 0x168)
97
+REG32(TOPSW_CLK_CTRL, 0x16c)
98
99
#define FPGA_CTRL_REGS(n, start) \
100
- FPGA ## n ## _CLK_CTRL = (start) / 4, \
101
- FPGA ## n ## _THR_CTRL, \
102
- FPGA ## n ## _THR_CNT, \
103
- FPGA ## n ## _THR_STA,
104
- FPGA_CTRL_REGS(0, 0x170)
105
- FPGA_CTRL_REGS(1, 0x180)
106
- FPGA_CTRL_REGS(2, 0x190)
107
- FPGA_CTRL_REGS(3, 0x1a0)
108
+ REG32(FPGA ## n ## _CLK_CTRL, (start)) \
109
+ REG32(FPGA ## n ## _THR_CTRL, (start) + 0x4)\
110
+ REG32(FPGA ## n ## _THR_CNT, (start) + 0x8)\
111
+ REG32(FPGA ## n ## _THR_STA, (start) + 0xc)
112
+FPGA_CTRL_REGS(0, 0x170)
113
+FPGA_CTRL_REGS(1, 0x180)
114
+FPGA_CTRL_REGS(2, 0x190)
115
+FPGA_CTRL_REGS(3, 0x1a0)
116
117
- BANDGAP_TRIP = 0x1b8 / 4,
118
- PLL_PREDIVISOR = 0x1c0 / 4,
119
- CLK_621_TRUE,
120
+REG32(BANDGAP_TRIP, 0x1b8)
121
+REG32(PLL_PREDIVISOR, 0x1c0)
122
+REG32(CLK_621_TRUE, 0x1c4)
123
124
- PSS_RST_CTRL = 0x200 / 4,
125
- DDR_RST_CTRL,
126
- TOPSW_RESET_CTRL,
127
- DMAC_RST_CTRL,
128
- USB_RST_CTRL,
129
- GEM_RST_CTRL,
130
- SDIO_RST_CTRL,
131
- SPI_RST_CTRL,
132
- CAN_RST_CTRL,
133
- I2C_RST_CTRL,
134
- UART_RST_CTRL,
135
- GPIO_RST_CTRL,
136
- LQSPI_RST_CTRL,
137
- SMC_RST_CTRL,
138
- OCM_RST_CTRL,
139
- FPGA_RST_CTRL = 0x240 / 4,
140
- A9_CPU_RST_CTRL,
141
+REG32(PSS_RST_CTRL, 0x200)
142
+ FIELD(PSS_RST_CTRL, SOFT_RST, 0, 1)
143
+REG32(DDR_RST_CTRL, 0x204)
144
+REG32(TOPSW_RESET_CTRL, 0x208)
145
+REG32(DMAC_RST_CTRL, 0x20c)
146
+REG32(USB_RST_CTRL, 0x210)
147
+REG32(GEM_RST_CTRL, 0x214)
148
+REG32(SDIO_RST_CTRL, 0x218)
149
+REG32(SPI_RST_CTRL, 0x21c)
150
+REG32(CAN_RST_CTRL, 0x220)
151
+REG32(I2C_RST_CTRL, 0x224)
152
+REG32(UART_RST_CTRL, 0x228)
153
+REG32(GPIO_RST_CTRL, 0x22c)
154
+REG32(LQSPI_RST_CTRL, 0x230)
155
+REG32(SMC_RST_CTRL, 0x234)
156
+REG32(OCM_RST_CTRL, 0x238)
157
+REG32(FPGA_RST_CTRL, 0x240)
158
+REG32(A9_CPU_RST_CTRL, 0x244)
159
160
- RS_AWDT_CTRL = 0x24c / 4,
161
- RST_REASON,
162
+REG32(RS_AWDT_CTRL, 0x24c)
163
+REG32(RST_REASON, 0x250)
164
165
- REBOOT_STATUS = 0x258 / 4,
166
- BOOT_MODE,
167
+REG32(REBOOT_STATUS, 0x258)
168
+REG32(BOOT_MODE, 0x25c)
169
170
- APU_CTRL = 0x300 / 4,
171
- WDT_CLK_SEL,
172
+REG32(APU_CTRL, 0x300)
173
+REG32(WDT_CLK_SEL, 0x304)
174
175
- TZ_DMA_NS = 0x440 / 4,
176
- TZ_DMA_IRQ_NS,
177
- TZ_DMA_PERIPH_NS,
178
+REG32(TZ_DMA_NS, 0x440)
179
+REG32(TZ_DMA_IRQ_NS, 0x444)
180
+REG32(TZ_DMA_PERIPH_NS, 0x448)
181
182
- PSS_IDCODE = 0x530 / 4,
183
+REG32(PSS_IDCODE, 0x530)
184
185
- DDR_URGENT = 0x600 / 4,
186
- DDR_CAL_START = 0x60c / 4,
187
- DDR_REF_START = 0x614 / 4,
188
- DDR_CMD_STA,
189
- DDR_URGENT_SEL,
190
- DDR_DFI_STATUS,
191
+REG32(DDR_URGENT, 0x600)
192
+REG32(DDR_CAL_START, 0x60c)
193
+REG32(DDR_REF_START, 0x614)
194
+REG32(DDR_CMD_STA, 0x618)
195
+REG32(DDR_URGENT_SEL, 0x61c)
196
+REG32(DDR_DFI_STATUS, 0x620)
197
198
- MIO = 0x700 / 4,
199
+REG32(MIO, 0x700)
200
#define MIO_LENGTH 54
201
202
- MIO_LOOPBACK = 0x804 / 4,
203
- MIO_MST_TRI0,
204
- MIO_MST_TRI1,
205
+REG32(MIO_LOOPBACK, 0x804)
206
+REG32(MIO_MST_TRI0, 0x808)
207
+REG32(MIO_MST_TRI1, 0x80c)
208
209
- SD0_WP_CD_SEL = 0x830 / 4,
210
- SD1_WP_CD_SEL,
211
+REG32(SD0_WP_CD_SEL, 0x830)
212
+REG32(SD1_WP_CD_SEL, 0x834)
213
214
- LVL_SHFTR_EN = 0x900 / 4,
215
- OCM_CFG = 0x910 / 4,
216
+REG32(LVL_SHFTR_EN, 0x900)
217
+REG32(OCM_CFG, 0x910)
218
219
- CPU_RAM = 0xa00 / 4,
220
+REG32(CPU_RAM, 0xa00)
221
222
- IOU = 0xa30 / 4,
223
+REG32(IOU, 0xa30)
224
225
- DMAC_RAM = 0xa50 / 4,
226
+REG32(DMAC_RAM, 0xa50)
227
228
- AFI0 = 0xa60 / 4,
229
- AFI1 = AFI0 + 3,
230
- AFI2 = AFI1 + 3,
231
- AFI3 = AFI2 + 3,
232
+REG32(AFI0, 0xa60)
233
+REG32(AFI1, 0xa6c)
234
+REG32(AFI2, 0xa78)
235
+REG32(AFI3, 0xa84)
236
#define AFI_LENGTH 3
237
238
- OCM = 0xa90 / 4,
239
+REG32(OCM, 0xa90)
240
241
- DEVCI_RAM = 0xaa0 / 4,
242
+REG32(DEVCI_RAM, 0xaa0)
243
244
- CSG_RAM = 0xab0 / 4,
245
+REG32(CSG_RAM, 0xab0)
246
247
- GPIOB_CTRL = 0xb00 / 4,
248
- GPIOB_CFG_CMOS18,
249
- GPIOB_CFG_CMOS25,
250
- GPIOB_CFG_CMOS33,
251
- GPIOB_CFG_HSTL = 0xb14 / 4,
252
- GPIOB_DRVR_BIAS_CTRL,
253
+REG32(GPIOB_CTRL, 0xb00)
254
+REG32(GPIOB_CFG_CMOS18, 0xb04)
255
+REG32(GPIOB_CFG_CMOS25, 0xb08)
256
+REG32(GPIOB_CFG_CMOS33, 0xb0c)
257
+REG32(GPIOB_CFG_HSTL, 0xb14)
258
+REG32(GPIOB_DRVR_BIAS_CTRL, 0xb18)
259
260
- DDRIOB = 0xb40 / 4,
261
+REG32(DDRIOB, 0xb40)
262
#define DDRIOB_LENGTH 14
263
-};
264
265
#define ZYNQ_SLCR_MMIO_SIZE 0x1000
266
#define ZYNQ_SLCR_NUM_REGS (ZYNQ_SLCR_MMIO_SIZE / 4)
267
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_reset(DeviceState *d)
268
269
DB_PRINT("RESET\n");
270
271
- s->regs[LOCKSTA] = 1;
272
+ s->regs[R_LOCKSTA] = 1;
273
/* 0x100 - 0x11C */
274
- s->regs[ARM_PLL_CTRL] = 0x0001A008;
275
- s->regs[DDR_PLL_CTRL] = 0x0001A008;
276
- s->regs[IO_PLL_CTRL] = 0x0001A008;
277
- s->regs[PLL_STATUS] = 0x0000003F;
278
- s->regs[ARM_PLL_CFG] = 0x00014000;
279
- s->regs[DDR_PLL_CFG] = 0x00014000;
280
- s->regs[IO_PLL_CFG] = 0x00014000;
281
+ s->regs[R_ARM_PLL_CTRL] = 0x0001A008;
282
+ s->regs[R_DDR_PLL_CTRL] = 0x0001A008;
283
+ s->regs[R_IO_PLL_CTRL] = 0x0001A008;
284
+ s->regs[R_PLL_STATUS] = 0x0000003F;
285
+ s->regs[R_ARM_PLL_CFG] = 0x00014000;
286
+ s->regs[R_DDR_PLL_CFG] = 0x00014000;
287
+ s->regs[R_IO_PLL_CFG] = 0x00014000;
288
289
/* 0x120 - 0x16C */
290
- s->regs[ARM_CLK_CTRL] = 0x1F000400;
291
- s->regs[DDR_CLK_CTRL] = 0x18400003;
292
- s->regs[DCI_CLK_CTRL] = 0x01E03201;
293
- s->regs[APER_CLK_CTRL] = 0x01FFCCCD;
294
- s->regs[USB0_CLK_CTRL] = s->regs[USB1_CLK_CTRL] = 0x00101941;
295
- s->regs[GEM0_RCLK_CTRL] = s->regs[GEM1_RCLK_CTRL] = 0x00000001;
296
- s->regs[GEM0_CLK_CTRL] = s->regs[GEM1_CLK_CTRL] = 0x00003C01;
297
- s->regs[SMC_CLK_CTRL] = 0x00003C01;
298
- s->regs[LQSPI_CLK_CTRL] = 0x00002821;
299
- s->regs[SDIO_CLK_CTRL] = 0x00001E03;
300
- s->regs[UART_CLK_CTRL] = 0x00003F03;
301
- s->regs[SPI_CLK_CTRL] = 0x00003F03;
302
- s->regs[CAN_CLK_CTRL] = 0x00501903;
303
- s->regs[DBG_CLK_CTRL] = 0x00000F03;
304
- s->regs[PCAP_CLK_CTRL] = 0x00000F01;
305
+ s->regs[R_ARM_CLK_CTRL] = 0x1F000400;
306
+ s->regs[R_DDR_CLK_CTRL] = 0x18400003;
307
+ s->regs[R_DCI_CLK_CTRL] = 0x01E03201;
308
+ s->regs[R_APER_CLK_CTRL] = 0x01FFCCCD;
309
+ s->regs[R_USB0_CLK_CTRL] = s->regs[R_USB1_CLK_CTRL] = 0x00101941;
310
+ s->regs[R_GEM0_RCLK_CTRL] = s->regs[R_GEM1_RCLK_CTRL] = 0x00000001;
311
+ s->regs[R_GEM0_CLK_CTRL] = s->regs[R_GEM1_CLK_CTRL] = 0x00003C01;
312
+ s->regs[R_SMC_CLK_CTRL] = 0x00003C01;
313
+ s->regs[R_LQSPI_CLK_CTRL] = 0x00002821;
314
+ s->regs[R_SDIO_CLK_CTRL] = 0x00001E03;
315
+ s->regs[R_UART_CLK_CTRL] = 0x00003F03;
316
+ s->regs[R_SPI_CLK_CTRL] = 0x00003F03;
317
+ s->regs[R_CAN_CLK_CTRL] = 0x00501903;
318
+ s->regs[R_DBG_CLK_CTRL] = 0x00000F03;
319
+ s->regs[R_PCAP_CLK_CTRL] = 0x00000F01;
320
321
/* 0x170 - 0x1AC */
322
- s->regs[FPGA0_CLK_CTRL] = s->regs[FPGA1_CLK_CTRL] = s->regs[FPGA2_CLK_CTRL]
323
- = s->regs[FPGA3_CLK_CTRL] = 0x00101800;
324
- s->regs[FPGA0_THR_STA] = s->regs[FPGA1_THR_STA] = s->regs[FPGA2_THR_STA]
325
- = s->regs[FPGA3_THR_STA] = 0x00010000;
326
+ s->regs[R_FPGA0_CLK_CTRL] = s->regs[R_FPGA1_CLK_CTRL]
327
+ = s->regs[R_FPGA2_CLK_CTRL]
328
+ = s->regs[R_FPGA3_CLK_CTRL] = 0x00101800;
329
+ s->regs[R_FPGA0_THR_STA] = s->regs[R_FPGA1_THR_STA]
330
+ = s->regs[R_FPGA2_THR_STA]
331
+ = s->regs[R_FPGA3_THR_STA] = 0x00010000;
332
333
/* 0x1B0 - 0x1D8 */
334
- s->regs[BANDGAP_TRIP] = 0x0000001F;
335
- s->regs[PLL_PREDIVISOR] = 0x00000001;
336
- s->regs[CLK_621_TRUE] = 0x00000001;
337
+ s->regs[R_BANDGAP_TRIP] = 0x0000001F;
338
+ s->regs[R_PLL_PREDIVISOR] = 0x00000001;
339
+ s->regs[R_CLK_621_TRUE] = 0x00000001;
340
341
/* 0x200 - 0x25C */
342
- s->regs[FPGA_RST_CTRL] = 0x01F33F0F;
343
- s->regs[RST_REASON] = 0x00000040;
344
+ s->regs[R_FPGA_RST_CTRL] = 0x01F33F0F;
345
+ s->regs[R_RST_REASON] = 0x00000040;
346
347
- s->regs[BOOT_MODE] = 0x00000001;
348
+ s->regs[R_BOOT_MODE] = 0x00000001;
349
350
/* 0x700 - 0x7D4 */
351
for (i = 0; i < 54; i++) {
352
- s->regs[MIO + i] = 0x00001601;
353
+ s->regs[R_MIO + i] = 0x00001601;
354
}
355
for (i = 2; i <= 8; i++) {
356
- s->regs[MIO + i] = 0x00000601;
357
+ s->regs[R_MIO + i] = 0x00000601;
358
}
359
360
- s->regs[MIO_MST_TRI0] = s->regs[MIO_MST_TRI1] = 0xFFFFFFFF;
361
+ s->regs[R_MIO_MST_TRI0] = s->regs[R_MIO_MST_TRI1] = 0xFFFFFFFF;
362
363
- s->regs[CPU_RAM + 0] = s->regs[CPU_RAM + 1] = s->regs[CPU_RAM + 3]
364
- = s->regs[CPU_RAM + 4] = s->regs[CPU_RAM + 7]
365
- = 0x00010101;
366
- s->regs[CPU_RAM + 2] = s->regs[CPU_RAM + 5] = 0x01010101;
367
- s->regs[CPU_RAM + 6] = 0x00000001;
368
+ s->regs[R_CPU_RAM + 0] = s->regs[R_CPU_RAM + 1] = s->regs[R_CPU_RAM + 3]
369
+ = s->regs[R_CPU_RAM + 4] = s->regs[R_CPU_RAM + 7]
370
+ = 0x00010101;
371
+ s->regs[R_CPU_RAM + 2] = s->regs[R_CPU_RAM + 5] = 0x01010101;
372
+ s->regs[R_CPU_RAM + 6] = 0x00000001;
373
374
- s->regs[IOU + 0] = s->regs[IOU + 1] = s->regs[IOU + 2] = s->regs[IOU + 3]
375
- = 0x09090909;
376
- s->regs[IOU + 4] = s->regs[IOU + 5] = 0x00090909;
377
- s->regs[IOU + 6] = 0x00000909;
378
+ s->regs[R_IOU + 0] = s->regs[R_IOU + 1] = s->regs[R_IOU + 2]
379
+ = s->regs[R_IOU + 3] = 0x09090909;
380
+ s->regs[R_IOU + 4] = s->regs[R_IOU + 5] = 0x00090909;
381
+ s->regs[R_IOU + 6] = 0x00000909;
382
383
- s->regs[DMAC_RAM] = 0x00000009;
384
+ s->regs[R_DMAC_RAM] = 0x00000009;
385
386
- s->regs[AFI0 + 0] = s->regs[AFI0 + 1] = 0x09090909;
387
- s->regs[AFI1 + 0] = s->regs[AFI1 + 1] = 0x09090909;
388
- s->regs[AFI2 + 0] = s->regs[AFI2 + 1] = 0x09090909;
389
- s->regs[AFI3 + 0] = s->regs[AFI3 + 1] = 0x09090909;
390
- s->regs[AFI0 + 2] = s->regs[AFI1 + 2] = s->regs[AFI2 + 2]
391
- = s->regs[AFI3 + 2] = 0x00000909;
392
+ s->regs[R_AFI0 + 0] = s->regs[R_AFI0 + 1] = 0x09090909;
393
+ s->regs[R_AFI1 + 0] = s->regs[R_AFI1 + 1] = 0x09090909;
394
+ s->regs[R_AFI2 + 0] = s->regs[R_AFI2 + 1] = 0x09090909;
395
+ s->regs[R_AFI3 + 0] = s->regs[R_AFI3 + 1] = 0x09090909;
396
+ s->regs[R_AFI0 + 2] = s->regs[R_AFI1 + 2] = s->regs[R_AFI2 + 2]
397
+ = s->regs[R_AFI3 + 2] = 0x00000909;
398
399
- s->regs[OCM + 0] = 0x01010101;
400
- s->regs[OCM + 1] = s->regs[OCM + 2] = 0x09090909;
401
+ s->regs[R_OCM + 0] = 0x01010101;
402
+ s->regs[R_OCM + 1] = s->regs[R_OCM + 2] = 0x09090909;
403
404
- s->regs[DEVCI_RAM] = 0x00000909;
405
- s->regs[CSG_RAM] = 0x00000001;
406
+ s->regs[R_DEVCI_RAM] = 0x00000909;
407
+ s->regs[R_CSG_RAM] = 0x00000001;
408
409
- s->regs[DDRIOB + 0] = s->regs[DDRIOB + 1] = s->regs[DDRIOB + 2]
410
- = s->regs[DDRIOB + 3] = 0x00000e00;
411
- s->regs[DDRIOB + 4] = s->regs[DDRIOB + 5] = s->regs[DDRIOB + 6]
412
- = 0x00000e00;
413
- s->regs[DDRIOB + 12] = 0x00000021;
414
+ s->regs[R_DDRIOB + 0] = s->regs[R_DDRIOB + 1] = s->regs[R_DDRIOB + 2]
415
+ = s->regs[R_DDRIOB + 3] = 0x00000e00;
416
+ s->regs[R_DDRIOB + 4] = s->regs[R_DDRIOB + 5] = s->regs[R_DDRIOB + 6]
417
+ = 0x00000e00;
418
+ s->regs[R_DDRIOB + 12] = 0x00000021;
419
}
104
}
420
105
421
106
static void aw_a10_realize(DeviceState *dev, Error **errp)
422
static bool zynq_slcr_check_offset(hwaddr offset, bool rnw)
107
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
423
{
108
serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2,
424
switch (offset) {
109
qdev_get_gpio_in(dev, 1),
425
- case LOCK:
110
115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
426
- case UNLOCK:
111
+
427
- case DDR_CAL_START:
112
+ if (machine_usb(current_machine)) {
428
- case DDR_REF_START:
113
+ int i;
429
+ case R_LOCK:
114
+
430
+ case R_UNLOCK:
115
+ for (i = 0; i < AW_A10_NUM_USB; i++) {
431
+ case R_DDR_CAL_START:
116
+ char bus[16];
432
+ case R_DDR_REF_START:
117
+
433
return !rnw; /* Write only */
118
+ sprintf(bus, "usb-bus.%d", i);
434
- case LOCKSTA:
119
+
435
- case FPGA0_THR_STA:
120
+ object_property_set_bool(OBJECT(&s->ehci[i]), true,
436
- case FPGA1_THR_STA:
121
+ "companion-enable", &error_fatal);
437
- case FPGA2_THR_STA:
122
+ object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized",
438
- case FPGA3_THR_STA:
123
+ &error_fatal);
439
- case BOOT_MODE:
124
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
440
- case PSS_IDCODE:
125
+ AW_A10_EHCI_BASE + i * 0x8000);
441
- case DDR_CMD_STA:
126
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
442
- case DDR_DFI_STATUS:
127
+ qdev_get_gpio_in(dev, 39 + i));
443
- case PLL_STATUS:
128
+
444
+ case R_LOCKSTA:
129
+ object_property_set_str(OBJECT(&s->ohci[i]), bus, "masterbus",
445
+ case R_FPGA0_THR_STA:
130
+ &error_fatal);
446
+ case R_FPGA1_THR_STA:
131
+ object_property_set_bool(OBJECT(&s->ohci[i]), true, "realized",
447
+ case R_FPGA2_THR_STA:
132
+ &error_fatal);
448
+ case R_FPGA3_THR_STA:
133
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
449
+ case R_BOOT_MODE:
134
+ AW_A10_OHCI_BASE + i * 0x8000);
450
+ case R_PSS_IDCODE:
135
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
451
+ case R_DDR_CMD_STA:
136
+ qdev_get_gpio_in(dev, 64 + i));
452
+ case R_DDR_DFI_STATUS:
137
+ }
453
+ case R_PLL_STATUS:
138
+ }
454
return rnw;/* read only */
139
}
455
- case SCL:
140
456
- case ARM_PLL_CTRL ... IO_PLL_CTRL:
141
static void aw_a10_class_init(ObjectClass *oc, void *data)
457
- case ARM_PLL_CFG ... IO_PLL_CFG:
458
- case ARM_CLK_CTRL ... TOPSW_CLK_CTRL:
459
- case FPGA0_CLK_CTRL ... FPGA0_THR_CNT:
460
- case FPGA1_CLK_CTRL ... FPGA1_THR_CNT:
461
- case FPGA2_CLK_CTRL ... FPGA2_THR_CNT:
462
- case FPGA3_CLK_CTRL ... FPGA3_THR_CNT:
463
- case BANDGAP_TRIP:
464
- case PLL_PREDIVISOR:
465
- case CLK_621_TRUE:
466
- case PSS_RST_CTRL ... A9_CPU_RST_CTRL:
467
- case RS_AWDT_CTRL:
468
- case RST_REASON:
469
- case REBOOT_STATUS:
470
- case APU_CTRL:
471
- case WDT_CLK_SEL:
472
- case TZ_DMA_NS ... TZ_DMA_PERIPH_NS:
473
- case DDR_URGENT:
474
- case DDR_URGENT_SEL:
475
- case MIO ... MIO + MIO_LENGTH - 1:
476
- case MIO_LOOPBACK ... MIO_MST_TRI1:
477
- case SD0_WP_CD_SEL:
478
- case SD1_WP_CD_SEL:
479
- case LVL_SHFTR_EN:
480
- case OCM_CFG:
481
- case CPU_RAM:
482
- case IOU:
483
- case DMAC_RAM:
484
- case AFI0 ... AFI3 + AFI_LENGTH - 1:
485
- case OCM:
486
- case DEVCI_RAM:
487
- case CSG_RAM:
488
- case GPIOB_CTRL ... GPIOB_CFG_CMOS33:
489
- case GPIOB_CFG_HSTL:
490
- case GPIOB_DRVR_BIAS_CTRL:
491
- case DDRIOB ... DDRIOB + DDRIOB_LENGTH - 1:
492
+ case R_SCL:
493
+ case R_ARM_PLL_CTRL ... R_IO_PLL_CTRL:
494
+ case R_ARM_PLL_CFG ... R_IO_PLL_CFG:
495
+ case R_ARM_CLK_CTRL ... R_TOPSW_CLK_CTRL:
496
+ case R_FPGA0_CLK_CTRL ... R_FPGA0_THR_CNT:
497
+ case R_FPGA1_CLK_CTRL ... R_FPGA1_THR_CNT:
498
+ case R_FPGA2_CLK_CTRL ... R_FPGA2_THR_CNT:
499
+ case R_FPGA3_CLK_CTRL ... R_FPGA3_THR_CNT:
500
+ case R_BANDGAP_TRIP:
501
+ case R_PLL_PREDIVISOR:
502
+ case R_CLK_621_TRUE:
503
+ case R_PSS_RST_CTRL ... R_A9_CPU_RST_CTRL:
504
+ case R_RS_AWDT_CTRL:
505
+ case R_RST_REASON:
506
+ case R_REBOOT_STATUS:
507
+ case R_APU_CTRL:
508
+ case R_WDT_CLK_SEL:
509
+ case R_TZ_DMA_NS ... R_TZ_DMA_PERIPH_NS:
510
+ case R_DDR_URGENT:
511
+ case R_DDR_URGENT_SEL:
512
+ case R_MIO ... R_MIO + MIO_LENGTH - 1:
513
+ case R_MIO_LOOPBACK ... R_MIO_MST_TRI1:
514
+ case R_SD0_WP_CD_SEL:
515
+ case R_SD1_WP_CD_SEL:
516
+ case R_LVL_SHFTR_EN:
517
+ case R_OCM_CFG:
518
+ case R_CPU_RAM:
519
+ case R_IOU:
520
+ case R_DMAC_RAM:
521
+ case R_AFI0 ... R_AFI3 + AFI_LENGTH - 1:
522
+ case R_OCM:
523
+ case R_DEVCI_RAM:
524
+ case R_CSG_RAM:
525
+ case R_GPIOB_CTRL ... R_GPIOB_CFG_CMOS33:
526
+ case R_GPIOB_CFG_HSTL:
527
+ case R_GPIOB_DRVR_BIAS_CTRL:
528
+ case R_DDRIOB ... R_DDRIOB + DDRIOB_LENGTH - 1:
529
return true;
530
default:
531
return false;
532
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
533
}
534
535
switch (offset) {
536
- case SCL:
537
- s->regs[SCL] = val & 0x1;
538
+ case R_SCL:
539
+ s->regs[R_SCL] = val & 0x1;
540
return;
541
- case LOCK:
542
+ case R_LOCK:
543
if ((val & 0xFFFF) == XILINX_LOCK_KEY) {
544
DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
545
(unsigned)val & 0xFFFF);
546
- s->regs[LOCKSTA] = 1;
547
+ s->regs[R_LOCKSTA] = 1;
548
} else {
549
DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
550
(int)offset, (unsigned)val & 0xFFFF);
551
}
552
return;
553
- case UNLOCK:
554
+ case R_UNLOCK:
555
if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) {
556
DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
557
(unsigned)val & 0xFFFF);
558
- s->regs[LOCKSTA] = 0;
559
+ s->regs[R_LOCKSTA] = 0;
560
} else {
561
DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
562
(int)offset, (unsigned)val & 0xFFFF);
563
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
564
return;
565
}
566
567
- if (s->regs[LOCKSTA]) {
568
+ if (s->regs[R_LOCKSTA]) {
569
qemu_log_mask(LOG_GUEST_ERROR,
570
"SCLR registers are locked. Unlock them first\n");
571
return;
572
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
573
s->regs[offset] = val;
574
575
switch (offset) {
576
- case PSS_RST_CTRL:
577
- if (val & R_PSS_RST_CTRL_SOFT_RST) {
578
+ case R_PSS_RST_CTRL:
579
+ if (FIELD_EX32(val, PSS_RST_CTRL, SOFT_RST)) {
580
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
581
}
582
break;
583
--
142
--
584
2.20.1
143
2.20.1
585
144
586
145
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/29] target/arm: Replace s->pc with s->base.pc_next
[PULL 38/52] target/arm: Vectorize USHL and SSHL
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We must update s->base.pc_next when we return from the translate_insn
3
These instructions shift left or right depending on the sign
4
hook to the main translator loop. By incrementing s->base.pc_next
4
of the input, and 7 bits are significant to the shift. This
5
immediately after reading the insn word, "pc_next" contains the address
5
requires several masks and selects in addition to the actual
6
of the next instruction throughout translation.
6
shifts to form the complete answer.
7
7
8
All remaining uses of s->pc are referencing the address of the next insn,
8
That said, the operation is still a small improvement even for
9
so this is now a simple global replacement. Remove the "s->pc" field.
9
two 64-bit elements -- 13 vector operations instead of 2 * 7
10
integer operations.
10
11
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Message-id: 20200216214232.4230-2-richard.henderson@linaro.org
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Message-id: 20190807045335.1361-7-richard.henderson@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
16
---
17
target/arm/translate.h | 1 -
17
target/arm/helper.h | 11 +-
18
target/arm/translate-a64.c | 51 +++++++++---------
18
target/arm/translate.h | 6 +
19
target/arm/translate.c | 103 ++++++++++++++++++-------------------
19
target/arm/neon_helper.c | 33 ----
20
3 files changed, 72 insertions(+), 83 deletions(-)
20
target/arm/translate-a64.c | 18 +--
21
target/arm/translate.c | 299 +++++++++++++++++++++++++++++++++++--
22
target/arm/vec_helper.c | 88 +++++++++++
23
6 files changed, 389 insertions(+), 66 deletions(-)
21
24
25
diff --git a/target/arm/helper.h b/target/arm/helper.h
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/helper.h
28
+++ b/target/arm/helper.h
29
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(neon_abd_s16, i32, i32, i32)
30
DEF_HELPER_2(neon_abd_u32, i32, i32, i32)
31
DEF_HELPER_2(neon_abd_s32, i32, i32, i32)
32
33
-DEF_HELPER_2(neon_shl_u8, i32, i32, i32)
34
-DEF_HELPER_2(neon_shl_s8, i32, i32, i32)
35
DEF_HELPER_2(neon_shl_u16, i32, i32, i32)
36
DEF_HELPER_2(neon_shl_s16, i32, i32, i32)
37
-DEF_HELPER_2(neon_shl_u32, i32, i32, i32)
38
-DEF_HELPER_2(neon_shl_s32, i32, i32, i32)
39
-DEF_HELPER_2(neon_shl_u64, i64, i64, i64)
40
-DEF_HELPER_2(neon_shl_s64, i64, i64, i64)
41
DEF_HELPER_2(neon_rshl_u8, i32, i32, i32)
42
DEF_HELPER_2(neon_rshl_s8, i32, i32, i32)
43
DEF_HELPER_2(neon_rshl_u16, i32, i32, i32)
44
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, ptr)
45
DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, ptr)
46
DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, ptr)
47
48
+DEF_HELPER_FLAGS_4(gvec_sshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
49
+DEF_HELPER_FLAGS_4(gvec_sshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
50
+DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
51
+DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
52
+
53
#ifdef TARGET_AARCH64
54
#include "helper-a64.h"
55
#include "helper-sve.h"
22
diff --git a/target/arm/translate.h b/target/arm/translate.h
56
diff --git a/target/arm/translate.h b/target/arm/translate.h
23
index XXXXXXX..XXXXXXX 100644
57
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/translate.h
58
--- a/target/arm/translate.h
25
+++ b/target/arm/translate.h
59
+++ b/target/arm/translate.h
26
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
60
@@ -XXX,XX +XXX,XX @@ uint64_t vfp_expand_imm(int size, uint8_t imm8);
27
DisasContextBase base;
61
extern const GVecGen3 mla_op[4];
28
const ARMISARegisters *isar;
62
extern const GVecGen3 mls_op[4];
29
63
extern const GVecGen3 cmtst_op[4];
30
- target_ulong pc;
64
+extern const GVecGen3 sshl_op[4];
31
/* The address of the current instruction being translated. */
65
+extern const GVecGen3 ushl_op[4];
32
target_ulong pc_curr;
66
extern const GVecGen2i ssra_op[4];
33
target_ulong page_start;
67
extern const GVecGen2i usra_op[4];
68
extern const GVecGen2i sri_op[4];
69
@@ -XXX,XX +XXX,XX @@ extern const GVecGen4 sqadd_op[4];
70
extern const GVecGen4 uqsub_op[4];
71
extern const GVecGen4 sqsub_op[4];
72
void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
73
+void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
74
+void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
75
+void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
76
+void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
77
78
/*
79
* Forward to the isar_feature_* tests given a DisasContext pointer.
80
diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/arm/neon_helper.c
83
+++ b/target/arm/neon_helper.c
84
@@ -XXX,XX +XXX,XX @@ NEON_VOP(abd_u32, neon_u32, 1)
85
} else { \
86
dest = src1 << tmp; \
87
}} while (0)
88
-NEON_VOP(shl_u8, neon_u8, 4)
89
NEON_VOP(shl_u16, neon_u16, 2)
90
-NEON_VOP(shl_u32, neon_u32, 1)
91
#undef NEON_FN
92
93
-uint64_t HELPER(neon_shl_u64)(uint64_t val, uint64_t shiftop)
94
-{
95
- int8_t shift = (int8_t)shiftop;
96
- if (shift >= 64 || shift <= -64) {
97
- val = 0;
98
- } else if (shift < 0) {
99
- val >>= -shift;
100
- } else {
101
- val <<= shift;
102
- }
103
- return val;
104
-}
105
-
106
#define NEON_FN(dest, src1, src2) do { \
107
int8_t tmp; \
108
tmp = (int8_t)src2; \
109
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_shl_u64)(uint64_t val, uint64_t shiftop)
110
} else { \
111
dest = src1 << tmp; \
112
}} while (0)
113
-NEON_VOP(shl_s8, neon_s8, 4)
114
NEON_VOP(shl_s16, neon_s16, 2)
115
-NEON_VOP(shl_s32, neon_s32, 1)
116
#undef NEON_FN
117
118
-uint64_t HELPER(neon_shl_s64)(uint64_t valop, uint64_t shiftop)
119
-{
120
- int8_t shift = (int8_t)shiftop;
121
- int64_t val = valop;
122
- if (shift >= 64) {
123
- val = 0;
124
- } else if (shift <= -64) {
125
- val >>= 63;
126
- } else if (shift < 0) {
127
- val >>= -shift;
128
- } else {
129
- val <<= shift;
130
- }
131
- return val;
132
-}
133
-
134
#define NEON_FN(dest, src1, src2) do { \
135
int8_t tmp; \
136
tmp = (int8_t)src2; \
34
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
137
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
35
index XXXXXXX..XXXXXXX 100644
138
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/translate-a64.c
139
--- a/target/arm/translate-a64.c
37
+++ b/target/arm/translate-a64.c
140
+++ b/target/arm/translate-a64.c
38
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
141
@@ -XXX,XX +XXX,XX @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
39
142
break;
40
static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
143
case 0x8: /* SSHL, USHL */
41
{
144
if (u) {
42
- gen_a64_set_pc_im(s->pc - offset);
145
- gen_helper_neon_shl_u64(tcg_rd, tcg_rn, tcg_rm);
43
+ gen_a64_set_pc_im(s->base.pc_next - offset);
146
+ gen_ushl_i64(tcg_rd, tcg_rn, tcg_rm);
44
gen_exception_internal(excp);
147
} else {
45
s->base.is_jmp = DISAS_NORETURN;
148
- gen_helper_neon_shl_s64(tcg_rd, tcg_rn, tcg_rm);
46
}
149
+ gen_sshl_i64(tcg_rd, tcg_rn, tcg_rm);
47
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
48
static void gen_exception_insn(DisasContext *s, int offset, int excp,
49
uint32_t syndrome, uint32_t target_el)
50
{
51
- gen_a64_set_pc_im(s->pc - offset);
52
+ gen_a64_set_pc_im(s->base.pc_next - offset);
53
gen_exception(excp, syndrome, target_el);
54
s->base.is_jmp = DISAS_NORETURN;
55
}
56
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, int offset,
57
{
58
TCGv_i32 tcg_syn;
59
60
- gen_a64_set_pc_im(s->pc - offset);
61
+ gen_a64_set_pc_im(s->base.pc_next - offset);
62
tcg_syn = tcg_const_i32(syndrome);
63
gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
64
tcg_temp_free_i32(tcg_syn);
65
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
66
67
if (insn & (1U << 31)) {
68
/* BL Branch with link */
69
- tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
70
+ tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
71
}
72
73
/* B Branch / BL Branch with link */
74
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
75
tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
76
tcg_cmp, 0, label_match);
77
78
- gen_goto_tb(s, 0, s->pc);
79
+ gen_goto_tb(s, 0, s->base.pc_next);
80
gen_set_label(label_match);
81
gen_goto_tb(s, 1, addr);
82
}
83
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
84
tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
85
tcg_cmp, 0, label_match);
86
tcg_temp_free_i64(tcg_cmp);
87
- gen_goto_tb(s, 0, s->pc);
88
+ gen_goto_tb(s, 0, s->base.pc_next);
89
gen_set_label(label_match);
90
gen_goto_tb(s, 1, addr);
91
}
92
@@ -XXX,XX +XXX,XX @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
93
/* genuinely conditional branches */
94
TCGLabel *label_match = gen_new_label();
95
arm_gen_test_cc(cond, label_match);
96
- gen_goto_tb(s, 0, s->pc);
97
+ gen_goto_tb(s, 0, s->base.pc_next);
98
gen_set_label(label_match);
99
gen_goto_tb(s, 1, addr);
100
} else {
101
@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,
102
* any pending interrupts immediately.
103
*/
104
reset_btype(s);
105
- gen_goto_tb(s, 0, s->pc);
106
+ gen_goto_tb(s, 0, s->base.pc_next);
107
return;
108
109
case 7: /* SB */
110
@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,
111
* MB and end the TB instead.
112
*/
113
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
114
- gen_goto_tb(s, 0, s->pc);
115
+ gen_goto_tb(s, 0, s->base.pc_next);
116
return;
117
118
default:
119
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
120
gen_a64_set_pc(s, dst);
121
/* BLR also needs to load return address */
122
if (opc == 1) {
123
- tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
124
+ tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
125
}
150
}
126
break;
151
break;
127
152
case 0x9: /* SQSHL, UQSHL */
128
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
153
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
129
gen_a64_set_pc(s, dst);
154
is_q ? 16 : 8, vec_full_reg_size(s),
130
/* BLRAA also needs to load return address */
155
(u ? uqsub_op : sqsub_op) + size);
131
if (opc == 9) {
156
return;
132
- tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
157
+ case 0x08: /* SSHL, USHL */
133
+ tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
158
+ gen_gvec_op3(s, is_q, rd, rn, rm,
134
}
159
+ u ? &ushl_op[size] : &sshl_op[size]);
135
break;
160
+ return;
136
161
case 0x0c: /* SMAX, UMAX */
137
@@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
162
if (u) {
138
{
163
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size);
139
uint32_t insn;
164
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
140
165
genfn = fns[size][u];
141
- s->pc_curr = s->pc;
166
break;
142
- insn = arm_ldl_code(env, s->pc, s->sctlr_b);
167
}
143
+ s->pc_curr = s->base.pc_next;
168
- case 0x8: /* SSHL, USHL */
144
+ insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b);
169
- {
145
s->insn = insn;
170
- static NeonGenTwoOpFn * const fns[3][2] = {
146
- s->pc += 4;
171
- { gen_helper_neon_shl_s8, gen_helper_neon_shl_u8 },
147
+ s->base.pc_next += 4;
172
- { gen_helper_neon_shl_s16, gen_helper_neon_shl_u16 },
148
173
- { gen_helper_neon_shl_s32, gen_helper_neon_shl_u32 },
149
s->fp_access_checked = false;
174
- };
150
175
- genfn = fns[size][u];
151
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
176
- break;
152
int bound, core_mmu_idx;
177
- }
153
178
case 0x9: /* SQSHL, UQSHL */
154
dc->isar = &arm_cpu->isar;
179
{
155
- dc->pc = dc->base.pc_first;
180
static NeonGenTwoOpEnvFn * const fns[3][2] = {
156
dc->condjmp = 0;
157
158
dc->aarch64 = 1;
159
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
160
{
161
DisasContext *dc = container_of(dcbase, DisasContext, base);
162
163
- tcg_gen_insn_start(dc->pc, 0, 0);
164
+ tcg_gen_insn_start(dc->base.pc_next, 0, 0);
165
dc->insn_start = tcg_last_op();
166
}
167
168
@@ -XXX,XX +XXX,XX @@ static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
169
DisasContext *dc = container_of(dcbase, DisasContext, base);
170
171
if (bp->flags & BP_CPU) {
172
- gen_a64_set_pc_im(dc->pc);
173
+ gen_a64_set_pc_im(dc->base.pc_next);
174
gen_helper_check_breakpoints(cpu_env);
175
/* End the TB early; it likely won't be executed */
176
dc->base.is_jmp = DISAS_TOO_MANY;
177
@@ -XXX,XX +XXX,XX @@ static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
178
to for it to be properly cleared -- thus we
179
increment the PC here so that the logic setting
180
tb->size below does the right thing. */
181
- dc->pc += 4;
182
+ dc->base.pc_next += 4;
183
dc->base.is_jmp = DISAS_NORETURN;
184
}
185
186
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
187
disas_a64_insn(env, dc);
188
}
189
190
- dc->base.pc_next = dc->pc;
191
translator_loop_temp_check(&dc->base);
192
}
193
194
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
195
*/
196
switch (dc->base.is_jmp) {
197
default:
198
- gen_a64_set_pc_im(dc->pc);
199
+ gen_a64_set_pc_im(dc->base.pc_next);
200
/* fall through */
201
case DISAS_EXIT:
202
case DISAS_JUMP:
203
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
204
switch (dc->base.is_jmp) {
205
case DISAS_NEXT:
206
case DISAS_TOO_MANY:
207
- gen_goto_tb(dc, 1, dc->pc);
208
+ gen_goto_tb(dc, 1, dc->base.pc_next);
209
break;
210
default:
211
case DISAS_UPDATE:
212
- gen_a64_set_pc_im(dc->pc);
213
+ gen_a64_set_pc_im(dc->base.pc_next);
214
/* fall through */
215
case DISAS_EXIT:
216
tcg_gen_exit_tb(NULL, 0);
217
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
218
case DISAS_SWI:
219
break;
220
case DISAS_WFE:
221
- gen_a64_set_pc_im(dc->pc);
222
+ gen_a64_set_pc_im(dc->base.pc_next);
223
gen_helper_wfe(cpu_env);
224
break;
225
case DISAS_YIELD:
226
- gen_a64_set_pc_im(dc->pc);
227
+ gen_a64_set_pc_im(dc->base.pc_next);
228
gen_helper_yield(cpu_env);
229
break;
230
case DISAS_WFI:
231
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
232
*/
233
TCGv_i32 tmp = tcg_const_i32(4);
234
235
- gen_a64_set_pc_im(dc->pc);
236
+ gen_a64_set_pc_im(dc->base.pc_next);
237
gen_helper_wfi(cpu_env, tmp);
238
tcg_temp_free_i32(tmp);
239
/* The helper doesn't necessarily throw an exception, but we
240
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
241
}
242
}
243
}
244
-
245
- /* Functions above can change dc->pc, so re-align db->pc_next */
246
- dc->base.pc_next = dc->pc;
247
}
248
249
static void aarch64_tr_disas_log(const DisasContextBase *dcbase,
250
diff --git a/target/arm/translate.c b/target/arm/translate.c
181
diff --git a/target/arm/translate.c b/target/arm/translate.c
251
index XXXXXXX..XXXXXXX 100644
182
index XXXXXXX..XXXXXXX 100644
252
--- a/target/arm/translate.c
183
--- a/target/arm/translate.c
253
+++ b/target/arm/translate.c
184
+++ b/target/arm/translate.c
254
@@ -XXX,XX +XXX,XX @@ static inline void gen_blxns(DisasContext *s, int rm)
185
@@ -XXX,XX +XXX,XX @@ static inline void gen_neon_shift_narrow(int size, TCGv_i32 var, TCGv_i32 shift,
255
* We do however need to set the PC, because the blxns helper reads it.
186
if (u) {
256
* The blxns helper may throw an exception.
187
switch (size) {
257
*/
188
case 1: gen_helper_neon_shl_u16(var, var, shift); break;
258
- gen_set_pc_im(s, s->pc);
189
- case 2: gen_helper_neon_shl_u32(var, var, shift); break;
259
+ gen_set_pc_im(s, s->base.pc_next);
190
+ case 2: gen_ushl_i32(var, var, shift); break;
260
gen_helper_v7m_blxns(cpu_env, var);
191
default: abort();
261
tcg_temp_free_i32(var);
192
}
262
s->base.is_jmp = DISAS_EXIT;
193
} else {
263
@@ -XXX,XX +XXX,XX @@ static inline void gen_hvc(DisasContext *s, int imm16)
194
switch (size) {
264
* for single stepping.)
195
case 1: gen_helper_neon_shl_s16(var, var, shift); break;
265
*/
196
- case 2: gen_helper_neon_shl_s32(var, var, shift); break;
266
s->svc_imm = imm16;
197
+ case 2: gen_sshl_i32(var, var, shift); break;
267
- gen_set_pc_im(s, s->pc);
198
default: abort();
268
+ gen_set_pc_im(s, s->base.pc_next);
199
}
269
s->base.is_jmp = DISAS_HVC;
200
}
201
@@ -XXX,XX +XXX,XX @@ const GVecGen3 cmtst_op[4] = {
202
.vece = MO_64 },
203
};
204
205
+void gen_ushl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
206
+{
207
+ TCGv_i32 lval = tcg_temp_new_i32();
208
+ TCGv_i32 rval = tcg_temp_new_i32();
209
+ TCGv_i32 lsh = tcg_temp_new_i32();
210
+ TCGv_i32 rsh = tcg_temp_new_i32();
211
+ TCGv_i32 zero = tcg_const_i32(0);
212
+ TCGv_i32 max = tcg_const_i32(32);
213
+
214
+ /*
215
+ * Rely on the TCG guarantee that out of range shifts produce
216
+ * unspecified results, not undefined behaviour (i.e. no trap).
217
+ * Discard out-of-range results after the fact.
218
+ */
219
+ tcg_gen_ext8s_i32(lsh, shift);
220
+ tcg_gen_neg_i32(rsh, lsh);
221
+ tcg_gen_shl_i32(lval, src, lsh);
222
+ tcg_gen_shr_i32(rval, src, rsh);
223
+ tcg_gen_movcond_i32(TCG_COND_LTU, dst, lsh, max, lval, zero);
224
+ tcg_gen_movcond_i32(TCG_COND_LTU, dst, rsh, max, rval, dst);
225
+
226
+ tcg_temp_free_i32(lval);
227
+ tcg_temp_free_i32(rval);
228
+ tcg_temp_free_i32(lsh);
229
+ tcg_temp_free_i32(rsh);
230
+ tcg_temp_free_i32(zero);
231
+ tcg_temp_free_i32(max);
232
+}
233
+
234
+void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
235
+{
236
+ TCGv_i64 lval = tcg_temp_new_i64();
237
+ TCGv_i64 rval = tcg_temp_new_i64();
238
+ TCGv_i64 lsh = tcg_temp_new_i64();
239
+ TCGv_i64 rsh = tcg_temp_new_i64();
240
+ TCGv_i64 zero = tcg_const_i64(0);
241
+ TCGv_i64 max = tcg_const_i64(64);
242
+
243
+ /*
244
+ * Rely on the TCG guarantee that out of range shifts produce
245
+ * unspecified results, not undefined behaviour (i.e. no trap).
246
+ * Discard out-of-range results after the fact.
247
+ */
248
+ tcg_gen_ext8s_i64(lsh, shift);
249
+ tcg_gen_neg_i64(rsh, lsh);
250
+ tcg_gen_shl_i64(lval, src, lsh);
251
+ tcg_gen_shr_i64(rval, src, rsh);
252
+ tcg_gen_movcond_i64(TCG_COND_LTU, dst, lsh, max, lval, zero);
253
+ tcg_gen_movcond_i64(TCG_COND_LTU, dst, rsh, max, rval, dst);
254
+
255
+ tcg_temp_free_i64(lval);
256
+ tcg_temp_free_i64(rval);
257
+ tcg_temp_free_i64(lsh);
258
+ tcg_temp_free_i64(rsh);
259
+ tcg_temp_free_i64(zero);
260
+ tcg_temp_free_i64(max);
261
+}
262
+
263
+static void gen_ushl_vec(unsigned vece, TCGv_vec dst,
264
+ TCGv_vec src, TCGv_vec shift)
265
+{
266
+ TCGv_vec lval = tcg_temp_new_vec_matching(dst);
267
+ TCGv_vec rval = tcg_temp_new_vec_matching(dst);
268
+ TCGv_vec lsh = tcg_temp_new_vec_matching(dst);
269
+ TCGv_vec rsh = tcg_temp_new_vec_matching(dst);
270
+ TCGv_vec msk, max;
271
+
272
+ tcg_gen_neg_vec(vece, rsh, shift);
273
+ if (vece == MO_8) {
274
+ tcg_gen_mov_vec(lsh, shift);
275
+ } else {
276
+ msk = tcg_temp_new_vec_matching(dst);
277
+ tcg_gen_dupi_vec(vece, msk, 0xff);
278
+ tcg_gen_and_vec(vece, lsh, shift, msk);
279
+ tcg_gen_and_vec(vece, rsh, rsh, msk);
280
+ tcg_temp_free_vec(msk);
281
+ }
282
+
283
+ /*
284
+ * Rely on the TCG guarantee that out of range shifts produce
285
+ * unspecified results, not undefined behaviour (i.e. no trap).
286
+ * Discard out-of-range results after the fact.
287
+ */
288
+ tcg_gen_shlv_vec(vece, lval, src, lsh);
289
+ tcg_gen_shrv_vec(vece, rval, src, rsh);
290
+
291
+ max = tcg_temp_new_vec_matching(dst);
292
+ tcg_gen_dupi_vec(vece, max, 8 << vece);
293
+
294
+ /*
295
+ * The choice of LT (signed) and GEU (unsigned) are biased toward
296
+ * the instructions of the x86_64 host. For MO_8, the whole byte
297
+ * is significant so we must use an unsigned compare; otherwise we
298
+ * have already masked to a byte and so a signed compare works.
299
+ * Other tcg hosts have a full set of comparisons and do not care.
300
+ */
301
+ if (vece == MO_8) {
302
+ tcg_gen_cmp_vec(TCG_COND_GEU, vece, lsh, lsh, max);
303
+ tcg_gen_cmp_vec(TCG_COND_GEU, vece, rsh, rsh, max);
304
+ tcg_gen_andc_vec(vece, lval, lval, lsh);
305
+ tcg_gen_andc_vec(vece, rval, rval, rsh);
306
+ } else {
307
+ tcg_gen_cmp_vec(TCG_COND_LT, vece, lsh, lsh, max);
308
+ tcg_gen_cmp_vec(TCG_COND_LT, vece, rsh, rsh, max);
309
+ tcg_gen_and_vec(vece, lval, lval, lsh);
310
+ tcg_gen_and_vec(vece, rval, rval, rsh);
311
+ }
312
+ tcg_gen_or_vec(vece, dst, lval, rval);
313
+
314
+ tcg_temp_free_vec(max);
315
+ tcg_temp_free_vec(lval);
316
+ tcg_temp_free_vec(rval);
317
+ tcg_temp_free_vec(lsh);
318
+ tcg_temp_free_vec(rsh);
319
+}
320
+
321
+static const TCGOpcode ushl_list[] = {
322
+ INDEX_op_neg_vec, INDEX_op_shlv_vec,
323
+ INDEX_op_shrv_vec, INDEX_op_cmp_vec, 0
324
+};
325
+
326
+const GVecGen3 ushl_op[4] = {
327
+ { .fniv = gen_ushl_vec,
328
+ .fno = gen_helper_gvec_ushl_b,
329
+ .opt_opc = ushl_list,
330
+ .vece = MO_8 },
331
+ { .fniv = gen_ushl_vec,
332
+ .fno = gen_helper_gvec_ushl_h,
333
+ .opt_opc = ushl_list,
334
+ .vece = MO_16 },
335
+ { .fni4 = gen_ushl_i32,
336
+ .fniv = gen_ushl_vec,
337
+ .opt_opc = ushl_list,
338
+ .vece = MO_32 },
339
+ { .fni8 = gen_ushl_i64,
340
+ .fniv = gen_ushl_vec,
341
+ .opt_opc = ushl_list,
342
+ .vece = MO_64 },
343
+};
344
+
345
+void gen_sshl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
346
+{
347
+ TCGv_i32 lval = tcg_temp_new_i32();
348
+ TCGv_i32 rval = tcg_temp_new_i32();
349
+ TCGv_i32 lsh = tcg_temp_new_i32();
350
+ TCGv_i32 rsh = tcg_temp_new_i32();
351
+ TCGv_i32 zero = tcg_const_i32(0);
352
+ TCGv_i32 max = tcg_const_i32(31);
353
+
354
+ /*
355
+ * Rely on the TCG guarantee that out of range shifts produce
356
+ * unspecified results, not undefined behaviour (i.e. no trap).
357
+ * Discard out-of-range results after the fact.
358
+ */
359
+ tcg_gen_ext8s_i32(lsh, shift);
360
+ tcg_gen_neg_i32(rsh, lsh);
361
+ tcg_gen_shl_i32(lval, src, lsh);
362
+ tcg_gen_umin_i32(rsh, rsh, max);
363
+ tcg_gen_sar_i32(rval, src, rsh);
364
+ tcg_gen_movcond_i32(TCG_COND_LEU, lval, lsh, max, lval, zero);
365
+ tcg_gen_movcond_i32(TCG_COND_LT, dst, lsh, zero, rval, lval);
366
+
367
+ tcg_temp_free_i32(lval);
368
+ tcg_temp_free_i32(rval);
369
+ tcg_temp_free_i32(lsh);
370
+ tcg_temp_free_i32(rsh);
371
+ tcg_temp_free_i32(zero);
372
+ tcg_temp_free_i32(max);
373
+}
374
+
375
+void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
376
+{
377
+ TCGv_i64 lval = tcg_temp_new_i64();
378
+ TCGv_i64 rval = tcg_temp_new_i64();
379
+ TCGv_i64 lsh = tcg_temp_new_i64();
380
+ TCGv_i64 rsh = tcg_temp_new_i64();
381
+ TCGv_i64 zero = tcg_const_i64(0);
382
+ TCGv_i64 max = tcg_const_i64(63);
383
+
384
+ /*
385
+ * Rely on the TCG guarantee that out of range shifts produce
386
+ * unspecified results, not undefined behaviour (i.e. no trap).
387
+ * Discard out-of-range results after the fact.
388
+ */
389
+ tcg_gen_ext8s_i64(lsh, shift);
390
+ tcg_gen_neg_i64(rsh, lsh);
391
+ tcg_gen_shl_i64(lval, src, lsh);
392
+ tcg_gen_umin_i64(rsh, rsh, max);
393
+ tcg_gen_sar_i64(rval, src, rsh);
394
+ tcg_gen_movcond_i64(TCG_COND_LEU, lval, lsh, max, lval, zero);
395
+ tcg_gen_movcond_i64(TCG_COND_LT, dst, lsh, zero, rval, lval);
396
+
397
+ tcg_temp_free_i64(lval);
398
+ tcg_temp_free_i64(rval);
399
+ tcg_temp_free_i64(lsh);
400
+ tcg_temp_free_i64(rsh);
401
+ tcg_temp_free_i64(zero);
402
+ tcg_temp_free_i64(max);
403
+}
404
+
405
+static void gen_sshl_vec(unsigned vece, TCGv_vec dst,
406
+ TCGv_vec src, TCGv_vec shift)
407
+{
408
+ TCGv_vec lval = tcg_temp_new_vec_matching(dst);
409
+ TCGv_vec rval = tcg_temp_new_vec_matching(dst);
410
+ TCGv_vec lsh = tcg_temp_new_vec_matching(dst);
411
+ TCGv_vec rsh = tcg_temp_new_vec_matching(dst);
412
+ TCGv_vec tmp = tcg_temp_new_vec_matching(dst);
413
+
414
+ /*
415
+ * Rely on the TCG guarantee that out of range shifts produce
416
+ * unspecified results, not undefined behaviour (i.e. no trap).
417
+ * Discard out-of-range results after the fact.
418
+ */
419
+ tcg_gen_neg_vec(vece, rsh, shift);
420
+ if (vece == MO_8) {
421
+ tcg_gen_mov_vec(lsh, shift);
422
+ } else {
423
+ tcg_gen_dupi_vec(vece, tmp, 0xff);
424
+ tcg_gen_and_vec(vece, lsh, shift, tmp);
425
+ tcg_gen_and_vec(vece, rsh, rsh, tmp);
426
+ }
427
+
428
+ /* Bound rsh so out of bound right shift gets -1. */
429
+ tcg_gen_dupi_vec(vece, tmp, (8 << vece) - 1);
430
+ tcg_gen_umin_vec(vece, rsh, rsh, tmp);
431
+ tcg_gen_cmp_vec(TCG_COND_GT, vece, tmp, lsh, tmp);
432
+
433
+ tcg_gen_shlv_vec(vece, lval, src, lsh);
434
+ tcg_gen_sarv_vec(vece, rval, src, rsh);
435
+
436
+ /* Select in-bound left shift. */
437
+ tcg_gen_andc_vec(vece, lval, lval, tmp);
438
+
439
+ /* Select between left and right shift. */
440
+ if (vece == MO_8) {
441
+ tcg_gen_dupi_vec(vece, tmp, 0);
442
+ tcg_gen_cmpsel_vec(TCG_COND_LT, vece, dst, lsh, tmp, rval, lval);
443
+ } else {
444
+ tcg_gen_dupi_vec(vece, tmp, 0x80);
445
+ tcg_gen_cmpsel_vec(TCG_COND_LT, vece, dst, lsh, tmp, lval, rval);
446
+ }
447
+
448
+ tcg_temp_free_vec(lval);
449
+ tcg_temp_free_vec(rval);
450
+ tcg_temp_free_vec(lsh);
451
+ tcg_temp_free_vec(rsh);
452
+ tcg_temp_free_vec(tmp);
453
+}
454
+
455
+static const TCGOpcode sshl_list[] = {
456
+ INDEX_op_neg_vec, INDEX_op_umin_vec, INDEX_op_shlv_vec,
457
+ INDEX_op_sarv_vec, INDEX_op_cmp_vec, INDEX_op_cmpsel_vec, 0
458
+};
459
+
460
+const GVecGen3 sshl_op[4] = {
461
+ { .fniv = gen_sshl_vec,
462
+ .fno = gen_helper_gvec_sshl_b,
463
+ .opt_opc = sshl_list,
464
+ .vece = MO_8 },
465
+ { .fniv = gen_sshl_vec,
466
+ .fno = gen_helper_gvec_sshl_h,
467
+ .opt_opc = sshl_list,
468
+ .vece = MO_16 },
469
+ { .fni4 = gen_sshl_i32,
470
+ .fniv = gen_sshl_vec,
471
+ .opt_opc = sshl_list,
472
+ .vece = MO_32 },
473
+ { .fni8 = gen_sshl_i64,
474
+ .fniv = gen_sshl_vec,
475
+ .opt_opc = sshl_list,
476
+ .vece = MO_64 },
477
+};
478
+
479
static void gen_uqadd_vec(unsigned vece, TCGv_vec t, TCGv_vec sat,
480
TCGv_vec a, TCGv_vec b)
481
{
482
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
483
vec_size, vec_size);
484
}
485
return 0;
486
+
487
+ case NEON_3R_VSHL:
488
+ /* Note the operation is vshl vd,vm,vn */
489
+ tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
490
+ u ? &ushl_op[size] : &sshl_op[size]);
491
+ return 0;
492
}
493
494
if (size == 3) {
495
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
496
neon_load_reg64(cpu_V0, rn + pass);
497
neon_load_reg64(cpu_V1, rm + pass);
498
switch (op) {
499
- case NEON_3R_VSHL:
500
- if (u) {
501
- gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
502
- } else {
503
- gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
504
- }
505
- break;
506
case NEON_3R_VQSHL:
507
if (u) {
508
gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
509
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
510
}
511
pairwise = 0;
512
switch (op) {
513
- case NEON_3R_VSHL:
514
case NEON_3R_VQSHL:
515
case NEON_3R_VRSHL:
516
case NEON_3R_VQRSHL:
517
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
518
case NEON_3R_VHSUB:
519
GEN_NEON_INTEGER_OP(hsub);
520
break;
521
- case NEON_3R_VSHL:
522
- GEN_NEON_INTEGER_OP(shl);
523
- break;
524
case NEON_3R_VQSHL:
525
GEN_NEON_INTEGER_OP_ENV(qshl);
526
break;
527
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
528
}
529
} else {
530
if (input_unsigned) {
531
- gen_helper_neon_shl_u64(cpu_V0, in, tmp64);
532
+ gen_ushl_i64(cpu_V0, in, tmp64);
533
} else {
534
- gen_helper_neon_shl_s64(cpu_V0, in, tmp64);
535
+ gen_sshl_i64(cpu_V0, in, tmp64);
536
}
537
}
538
tmp = tcg_temp_new_i32();
539
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
540
index XXXXXXX..XXXXXXX 100644
541
--- a/target/arm/vec_helper.c
542
+++ b/target/arm/vec_helper.c
543
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
544
do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc,
545
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
270
}
546
}
271
547
+
272
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
548
+void HELPER(gvec_sshl_b)(void *vd, void *vn, void *vm, uint32_t desc)
273
tmp = tcg_const_i32(syn_aa32_smc());
549
+{
274
gen_helper_pre_smc(cpu_env, tmp);
550
+ intptr_t i, opr_sz = simd_oprsz(desc);
275
tcg_temp_free_i32(tmp);
551
+ int8_t *d = vd, *n = vn, *m = vm;
276
- gen_set_pc_im(s, s->pc);
552
+
277
+ gen_set_pc_im(s, s->base.pc_next);
553
+ for (i = 0; i < opr_sz; ++i) {
278
s->base.is_jmp = DISAS_SMC;
554
+ int8_t mm = m[i];
279
}
555
+ int8_t nn = n[i];
280
556
+ int8_t res = 0;
281
static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
557
+ if (mm >= 0) {
282
{
558
+ if (mm < 8) {
283
gen_set_condexec(s);
559
+ res = nn << mm;
284
- gen_set_pc_im(s, s->pc - offset);
560
+ }
285
+ gen_set_pc_im(s, s->base.pc_next - offset);
561
+ } else {
286
gen_exception_internal(excp);
562
+ res = nn >> (mm > -8 ? -mm : 7);
287
s->base.is_jmp = DISAS_NORETURN;
563
+ }
288
}
564
+ d[i] = res;
289
@@ -XXX,XX +XXX,XX @@ static void gen_exception_insn(DisasContext *s, int offset, int excp,
565
+ }
290
int syn, uint32_t target_el)
566
+ clear_tail(d, opr_sz, simd_maxsz(desc));
291
{
567
+}
292
gen_set_condexec(s);
568
+
293
- gen_set_pc_im(s, s->pc - offset);
569
+void HELPER(gvec_sshl_h)(void *vd, void *vn, void *vm, uint32_t desc)
294
+ gen_set_pc_im(s, s->base.pc_next - offset);
570
+{
295
gen_exception(excp, syn, target_el);
571
+ intptr_t i, opr_sz = simd_oprsz(desc);
296
s->base.is_jmp = DISAS_NORETURN;
572
+ int16_t *d = vd, *n = vn, *m = vm;
297
}
573
+
298
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, int offset, uint32_t syn)
574
+ for (i = 0; i < opr_sz / 2; ++i) {
299
TCGv_i32 tcg_syn;
575
+ int8_t mm = m[i]; /* only 8 bits of shift are significant */
300
576
+ int16_t nn = n[i];
301
gen_set_condexec(s);
577
+ int16_t res = 0;
302
- gen_set_pc_im(s, s->pc - offset);
578
+ if (mm >= 0) {
303
+ gen_set_pc_im(s, s->base.pc_next - offset);
579
+ if (mm < 16) {
304
tcg_syn = tcg_const_i32(syn);
580
+ res = nn << mm;
305
gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
581
+ }
306
tcg_temp_free_i32(tcg_syn);
582
+ } else {
307
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, int offset, uint32_t syn)
583
+ res = nn >> (mm > -16 ? -mm : 15);
308
/* Force a TB lookup after an instruction that changes the CPU state. */
584
+ }
309
static inline void gen_lookup_tb(DisasContext *s)
585
+ d[i] = res;
310
{
586
+ }
311
- tcg_gen_movi_i32(cpu_R[15], s->pc);
587
+ clear_tail(d, opr_sz, simd_maxsz(desc));
312
+ tcg_gen_movi_i32(cpu_R[15], s->base.pc_next);
588
+}
313
s->base.is_jmp = DISAS_EXIT;
589
+
314
}
590
+void HELPER(gvec_ushl_b)(void *vd, void *vn, void *vm, uint32_t desc)
315
591
+{
316
@@ -XXX,XX +XXX,XX @@ static inline bool use_goto_tb(DisasContext *s, target_ulong dest)
592
+ intptr_t i, opr_sz = simd_oprsz(desc);
317
{
593
+ uint8_t *d = vd, *n = vn, *m = vm;
318
#ifndef CONFIG_USER_ONLY
594
+
319
return (s->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
595
+ for (i = 0; i < opr_sz; ++i) {
320
- ((s->pc - 1) & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
596
+ int8_t mm = m[i];
321
+ ((s->base.pc_next - 1) & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
597
+ uint8_t nn = n[i];
322
#else
598
+ uint8_t res = 0;
323
return true;
599
+ if (mm >= 0) {
324
#endif
600
+ if (mm < 8) {
325
@@ -XXX,XX +XXX,XX @@ static void gen_nop_hint(DisasContext *s, int val)
601
+ res = nn << mm;
326
*/
602
+ }
327
case 1: /* yield */
603
+ } else {
328
if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
604
+ if (mm > -8) {
329
- gen_set_pc_im(s, s->pc);
605
+ res = nn >> -mm;
330
+ gen_set_pc_im(s, s->base.pc_next);
606
+ }
331
s->base.is_jmp = DISAS_YIELD;
607
+ }
332
}
608
+ d[i] = res;
333
break;
609
+ }
334
case 3: /* wfi */
610
+ clear_tail(d, opr_sz, simd_maxsz(desc));
335
- gen_set_pc_im(s, s->pc);
611
+}
336
+ gen_set_pc_im(s, s->base.pc_next);
612
+
337
s->base.is_jmp = DISAS_WFI;
613
+void HELPER(gvec_ushl_h)(void *vd, void *vn, void *vm, uint32_t desc)
338
break;
614
+{
339
case 2: /* wfe */
615
+ intptr_t i, opr_sz = simd_oprsz(desc);
340
if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
616
+ uint16_t *d = vd, *n = vn, *m = vm;
341
- gen_set_pc_im(s, s->pc);
617
+
342
+ gen_set_pc_im(s, s->base.pc_next);
618
+ for (i = 0; i < opr_sz / 2; ++i) {
343
s->base.is_jmp = DISAS_WFE;
619
+ int8_t mm = m[i]; /* only 8 bits of shift are significant */
344
}
620
+ uint16_t nn = n[i];
345
break;
621
+ uint16_t res = 0;
346
@@ -XXX,XX +XXX,XX @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
622
+ if (mm >= 0) {
347
if (isread) {
623
+ if (mm < 16) {
348
return 1;
624
+ res = nn << mm;
349
}
625
+ }
350
- gen_set_pc_im(s, s->pc);
626
+ } else {
351
+ gen_set_pc_im(s, s->base.pc_next);
627
+ if (mm > -16) {
352
s->base.is_jmp = DISAS_WFI;
628
+ res = nn >> -mm;
353
return 0;
629
+ }
354
default:
630
+ }
355
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
631
+ d[i] = res;
356
* self-modifying code correctly and also to take
632
+ }
357
* any pending interrupts immediately.
633
+ clear_tail(d, opr_sz, simd_maxsz(desc));
358
*/
634
+}
359
- gen_goto_tb(s, 0, s->pc);
360
+ gen_goto_tb(s, 0, s->base.pc_next);
361
return;
362
case 7: /* sb */
363
if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
364
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
365
* for TCG; MB and end the TB instead.
366
*/
367
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
368
- gen_goto_tb(s, 0, s->pc);
369
+ gen_goto_tb(s, 0, s->base.pc_next);
370
return;
371
default:
372
goto illegal_op;
373
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
374
int32_t offset;
375
376
tmp = tcg_temp_new_i32();
377
- tcg_gen_movi_i32(tmp, s->pc);
378
+ tcg_gen_movi_i32(tmp, s->base.pc_next);
379
store_reg(s, 14, tmp);
380
/* Sign-extend the 24-bit offset */
381
offset = (((int32_t)insn) << 8) >> 8;
382
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
383
/* branch link/exchange thumb (blx) */
384
tmp = load_reg(s, rm);
385
tmp2 = tcg_temp_new_i32();
386
- tcg_gen_movi_i32(tmp2, s->pc);
387
+ tcg_gen_movi_i32(tmp2, s->base.pc_next);
388
store_reg(s, 14, tmp2);
389
gen_bx(s, tmp);
390
break;
391
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
392
/* branch (and link) */
393
if (insn & (1 << 24)) {
394
tmp = tcg_temp_new_i32();
395
- tcg_gen_movi_i32(tmp, s->pc);
396
+ tcg_gen_movi_i32(tmp, s->base.pc_next);
397
store_reg(s, 14, tmp);
398
}
399
offset = sextract32(insn << 2, 0, 26);
400
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
401
break;
402
case 0xf:
403
/* swi */
404
- gen_set_pc_im(s, s->pc);
405
+ gen_set_pc_im(s, s->base.pc_next);
406
s->svc_imm = extract32(insn, 0, 24);
407
s->base.is_jmp = DISAS_SWI;
408
break;
409
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
410
411
if (insn & (1 << 14)) {
412
/* Branch and link. */
413
- tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
414
+ tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1);
415
}
416
417
offset += read_pc(s);
418
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
419
* and also to take any pending interrupts
420
* immediately.
421
*/
422
- gen_goto_tb(s, 0, s->pc);
423
+ gen_goto_tb(s, 0, s->base.pc_next);
424
break;
425
case 7: /* sb */
426
if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
427
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
428
* for TCG; MB and end the TB instead.
429
*/
430
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
431
- gen_goto_tb(s, 0, s->pc);
432
+ gen_goto_tb(s, 0, s->base.pc_next);
433
break;
434
default:
435
goto illegal_op;
436
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
437
/* BLX/BX */
438
tmp = load_reg(s, rm);
439
if (link) {
440
- val = (uint32_t)s->pc | 1;
441
+ val = (uint32_t)s->base.pc_next | 1;
442
tmp2 = tcg_temp_new_i32();
443
tcg_gen_movi_i32(tmp2, val);
444
store_reg(s, 14, tmp2);
445
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
446
447
if (cond == 0xf) {
448
/* swi */
449
- gen_set_pc_im(s, s->pc);
450
+ gen_set_pc_im(s, s->base.pc_next);
451
s->svc_imm = extract32(insn, 0, 8);
452
s->base.is_jmp = DISAS_SWI;
453
break;
454
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
455
tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
456
457
tmp2 = tcg_temp_new_i32();
458
- tcg_gen_movi_i32(tmp2, s->pc | 1);
459
+ tcg_gen_movi_i32(tmp2, s->base.pc_next | 1);
460
store_reg(s, 14, tmp2);
461
gen_bx(s, tmp);
462
break;
463
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
464
tcg_gen_addi_i32(tmp, tmp, offset);
465
466
tmp2 = tcg_temp_new_i32();
467
- tcg_gen_movi_i32(tmp2, s->pc | 1);
468
+ tcg_gen_movi_i32(tmp2, s->base.pc_next | 1);
469
store_reg(s, 14, tmp2);
470
gen_bx(s, tmp);
471
} else {
472
@@ -XXX,XX +XXX,XX @@ undef:
473
474
static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
475
{
476
- /* Return true if the insn at dc->pc might cross a page boundary.
477
+ /* Return true if the insn at dc->base.pc_next might cross a page boundary.
478
* (False positives are OK, false negatives are not.)
479
* We know this is a Thumb insn, and our caller ensures we are
480
- * only called if dc->pc is less than 4 bytes from the page
481
+ * only called if dc->base.pc_next is less than 4 bytes from the page
482
* boundary, so we cross the page if the first 16 bits indicate
483
* that this is a 32 bit insn.
484
*/
485
- uint16_t insn = arm_lduw_code(env, s->pc, s->sctlr_b);
486
+ uint16_t insn = arm_lduw_code(env, s->base.pc_next, s->sctlr_b);
487
488
- return !thumb_insn_is_16bit(s, s->pc, insn);
489
+ return !thumb_insn_is_16bit(s, s->base.pc_next, insn);
490
}
491
492
static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
493
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
494
uint32_t condexec, core_mmu_idx;
495
496
dc->isar = &cpu->isar;
497
- dc->pc = dc->base.pc_first;
498
dc->condjmp = 0;
499
500
dc->aarch64 = 0;
501
@@ -XXX,XX +XXX,XX @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
502
{
503
DisasContext *dc = container_of(dcbase, DisasContext, base);
504
505
- tcg_gen_insn_start(dc->pc,
506
+ tcg_gen_insn_start(dc->base.pc_next,
507
(dc->condexec_cond << 4) | (dc->condexec_mask >> 1),
508
0);
509
dc->insn_start = tcg_last_op();
510
@@ -XXX,XX +XXX,XX @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
511
512
if (bp->flags & BP_CPU) {
513
gen_set_condexec(dc);
514
- gen_set_pc_im(dc, dc->pc);
515
+ gen_set_pc_im(dc, dc->base.pc_next);
516
gen_helper_check_breakpoints(cpu_env);
517
/* End the TB early; it's likely not going to be executed */
518
dc->base.is_jmp = DISAS_TOO_MANY;
519
@@ -XXX,XX +XXX,XX @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
520
tb->size below does the right thing. */
521
/* TODO: Advance PC by correct instruction length to
522
* avoid disassembler error messages */
523
- dc->pc += 2;
524
+ dc->base.pc_next += 2;
525
dc->base.is_jmp = DISAS_NORETURN;
526
}
527
528
@@ -XXX,XX +XXX,XX @@ static bool arm_pre_translate_insn(DisasContext *dc)
529
{
530
#ifdef CONFIG_USER_ONLY
531
/* Intercept jump to the magic kernel page. */
532
- if (dc->pc >= 0xffff0000) {
533
+ if (dc->base.pc_next >= 0xffff0000) {
534
/* We always get here via a jump, so know we are not in a
535
conditional execution block. */
536
gen_exception_internal(EXCP_KERNEL_TRAP);
537
@@ -XXX,XX +XXX,XX @@ static void arm_post_translate_insn(DisasContext *dc)
538
gen_set_label(dc->condlabel);
539
dc->condjmp = 0;
540
}
541
- dc->base.pc_next = dc->pc;
542
translator_loop_temp_check(&dc->base);
543
}
544
545
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
546
return;
547
}
548
549
- dc->pc_curr = dc->pc;
550
- insn = arm_ldl_code(env, dc->pc, dc->sctlr_b);
551
+ dc->pc_curr = dc->base.pc_next;
552
+ insn = arm_ldl_code(env, dc->base.pc_next, dc->sctlr_b);
553
dc->insn = insn;
554
- dc->pc += 4;
555
+ dc->base.pc_next += 4;
556
disas_arm_insn(dc, insn);
557
558
arm_post_translate_insn(dc);
559
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
560
return;
561
}
562
563
- dc->pc_curr = dc->pc;
564
- insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);
565
- is_16bit = thumb_insn_is_16bit(dc, dc->pc, insn);
566
- dc->pc += 2;
567
+ dc->pc_curr = dc->base.pc_next;
568
+ insn = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b);
569
+ is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn);
570
+ dc->base.pc_next += 2;
571
if (!is_16bit) {
572
- uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b);
573
+ uint32_t insn2 = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b);
574
575
insn = insn << 16 | insn2;
576
- dc->pc += 2;
577
+ dc->base.pc_next += 2;
578
}
579
dc->insn = insn;
580
581
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
582
* but isn't very efficient).
583
*/
584
if (dc->base.is_jmp == DISAS_NEXT
585
- && (dc->pc - dc->page_start >= TARGET_PAGE_SIZE
586
- || (dc->pc - dc->page_start >= TARGET_PAGE_SIZE - 3
587
+ && (dc->base.pc_next - dc->page_start >= TARGET_PAGE_SIZE
588
+ || (dc->base.pc_next - dc->page_start >= TARGET_PAGE_SIZE - 3
589
&& insn_crosses_page(env, dc)))) {
590
dc->base.is_jmp = DISAS_TOO_MANY;
591
}
592
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
593
case DISAS_NEXT:
594
case DISAS_TOO_MANY:
595
case DISAS_UPDATE:
596
- gen_set_pc_im(dc, dc->pc);
597
+ gen_set_pc_im(dc, dc->base.pc_next);
598
/* fall through */
599
default:
600
/* FIXME: Single stepping a WFI insn will not halt the CPU. */
601
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
602
switch(dc->base.is_jmp) {
603
case DISAS_NEXT:
604
case DISAS_TOO_MANY:
605
- gen_goto_tb(dc, 1, dc->pc);
606
+ gen_goto_tb(dc, 1, dc->base.pc_next);
607
break;
608
case DISAS_JUMP:
609
gen_goto_ptr();
610
break;
611
case DISAS_UPDATE:
612
- gen_set_pc_im(dc, dc->pc);
613
+ gen_set_pc_im(dc, dc->base.pc_next);
614
/* fall through */
615
default:
616
/* indicate that the hash table must be used to find the next TB */
617
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
618
gen_set_label(dc->condlabel);
619
gen_set_condexec(dc);
620
if (unlikely(is_singlestepping(dc))) {
621
- gen_set_pc_im(dc, dc->pc);
622
+ gen_set_pc_im(dc, dc->base.pc_next);
623
gen_singlestep_exception(dc);
624
} else {
625
- gen_goto_tb(dc, 1, dc->pc);
626
+ gen_goto_tb(dc, 1, dc->base.pc_next);
627
}
628
}
629
-
630
- /* Functions above can change dc->pc, so re-align db->pc_next */
631
- dc->base.pc_next = dc->pc;
632
}
633
634
static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
635
--
635
--
636
2.20.1
636
2.20.1
637
637
638
638
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/29] target/arm: Replace offset with pc in gen_exception_internal_insn
[PULL 39/52] target/arm: Convert PMUL.8 to gvec
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The offset is variable depending on the instruction set.
3
The gvec form will be needed for implementing SVE2.
4
Passing in the actual value is clearer in intent.
5
4
5
Extend the implementation to operate on uint64_t instead of uint32_t.
6
Use a counted inner loop instead of terminating when op1 goes to zero,
7
looking toward the required implementation for ARMv8.4-DIT.
8
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20200216214232.4230-3-richard.henderson@linaro.org
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190807045335.1361-9-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
14
---
12
target/arm/translate-a64.c | 8 ++++----
15
target/arm/helper.h | 3 ++-
13
target/arm/translate.c | 8 ++++----
16
target/arm/neon_helper.c | 22 ----------------------
14
2 files changed, 8 insertions(+), 8 deletions(-)
17
target/arm/translate-a64.c | 10 +++-------
18
target/arm/translate.c | 11 ++++-------
19
target/arm/vec_helper.c | 30 ++++++++++++++++++++++++++++++
20
5 files changed, 39 insertions(+), 37 deletions(-)
15
21
22
diff --git a/target/arm/helper.h b/target/arm/helper.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/helper.h
25
+++ b/target/arm/helper.h
26
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(neon_sub_u8, i32, i32, i32)
27
DEF_HELPER_2(neon_sub_u16, i32, i32, i32)
28
DEF_HELPER_2(neon_mul_u8, i32, i32, i32)
29
DEF_HELPER_2(neon_mul_u16, i32, i32, i32)
30
-DEF_HELPER_2(neon_mul_p8, i32, i32, i32)
31
DEF_HELPER_2(neon_mull_p8, i64, i32, i32)
32
33
DEF_HELPER_2(neon_tst_u8, i32, i32, i32)
34
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(gvec_sshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
35
DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
36
DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
37
38
+DEF_HELPER_FLAGS_4(gvec_pmul_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
39
+
40
#ifdef TARGET_AARCH64
41
#include "helper-a64.h"
42
#include "helper-sve.h"
43
diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/neon_helper.c
46
+++ b/target/arm/neon_helper.c
47
@@ -XXX,XX +XXX,XX @@ NEON_VOP(mul_u16, neon_u16, 2)
48
49
/* Polynomial multiplication is like integer multiplication except the
50
partial products are XORed, not added. */
51
-uint32_t HELPER(neon_mul_p8)(uint32_t op1, uint32_t op2)
52
-{
53
- uint32_t mask;
54
- uint32_t result;
55
- result = 0;
56
- while (op1) {
57
- mask = 0;
58
- if (op1 & 1)
59
- mask |= 0xff;
60
- if (op1 & (1 << 8))
61
- mask |= (0xff << 8);
62
- if (op1 & (1 << 16))
63
- mask |= (0xff << 16);
64
- if (op1 & (1 << 24))
65
- mask |= (0xff << 24);
66
- result ^= op2 & mask;
67
- op1 = (op1 >> 1) & 0x7f7f7f7f;
68
- op2 = (op2 << 1) & 0xfefefefe;
69
- }
70
- return result;
71
-}
72
-
73
uint64_t HELPER(neon_mull_p8)(uint32_t op1, uint32_t op2)
74
{
75
uint64_t result = 0;
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
76
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
index XXXXXXX..XXXXXXX 100644
77
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-a64.c
78
--- a/target/arm/translate-a64.c
19
+++ b/target/arm/translate-a64.c
79
+++ b/target/arm/translate-a64.c
20
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
80
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
21
tcg_temp_free_i32(tcg_excp);
81
case 0x13: /* MUL, PMUL */
22
}
82
if (!u) { /* MUL */
23
83
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_mul, size);
24
-static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
84
- return;
25
+static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
85
+ } else { /* PMUL */
26
{
86
+ gen_gvec_op3_ool(s, is_q, rd, rn, rm, 0, gen_helper_gvec_pmul_b);
27
- gen_a64_set_pc_im(s->base.pc_next - offset);
87
}
28
+ gen_a64_set_pc_im(pc);
88
- break;
29
gen_exception_internal(excp);
89
+ return;
30
s->base.is_jmp = DISAS_NORETURN;
90
case 0x12: /* MLA, MLS */
31
}
91
if (u) {
32
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
92
gen_gvec_op3(s, is_q, rd, rn, rm, &mls_op[size]);
93
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
94
genfn = fns[size][u];
33
break;
95
break;
34
}
96
}
35
#endif
97
- case 0x13: /* MUL, PMUL */
36
- gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
98
- assert(u); /* PMUL */
37
+ gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST);
99
- assert(size == 0);
38
} else {
100
- genfn = gen_helper_neon_mul_p8;
39
unsupported_encoding(s, insn);
101
- break;
40
}
102
case 0x16: /* SQDMULH, SQRDMULH */
41
@@ -XXX,XX +XXX,XX @@ static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
103
{
42
/* End the TB early; it likely won't be executed */
104
static NeonGenTwoOpEnvFn * const fns[2][2] = {
43
dc->base.is_jmp = DISAS_TOO_MANY;
44
} else {
45
- gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
46
+ gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG);
47
/* The address covered by the breakpoint must be
48
included in [tb->pc, tb->pc + tb->size) in order
49
to for it to be properly cleared -- thus we
50
diff --git a/target/arm/translate.c b/target/arm/translate.c
105
diff --git a/target/arm/translate.c b/target/arm/translate.c
51
index XXXXXXX..XXXXXXX 100644
106
index XXXXXXX..XXXXXXX 100644
52
--- a/target/arm/translate.c
107
--- a/target/arm/translate.c
53
+++ b/target/arm/translate.c
108
+++ b/target/arm/translate.c
54
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
109
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
55
s->base.is_jmp = DISAS_SMC;
110
111
case NEON_3R_VMUL: /* VMUL */
112
if (u) {
113
- /* Polynomial case allows only P8 and is handled below. */
114
+ /* Polynomial case allows only P8. */
115
if (size != 0) {
116
return 1;
117
}
118
+ tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size,
119
+ 0, gen_helper_gvec_pmul_b);
120
} else {
121
tcg_gen_gvec_mul(size, rd_ofs, rn_ofs, rm_ofs,
122
vec_size, vec_size);
123
- return 0;
124
}
125
- break;
126
+ return 0;
127
128
case NEON_3R_VML: /* VMLA, VMLS */
129
tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size,
130
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
131
tmp2 = neon_load_reg(rd, pass);
132
gen_neon_add(size, tmp, tmp2);
133
break;
134
- case NEON_3R_VMUL:
135
- /* VMUL.P8; other cases already eliminated. */
136
- gen_helper_neon_mul_p8(tmp, tmp, tmp2);
137
- break;
138
case NEON_3R_VPMAX:
139
GEN_NEON_INTEGER_OP(pmax);
140
break;
141
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
142
index XXXXXXX..XXXXXXX 100644
143
--- a/target/arm/vec_helper.c
144
+++ b/target/arm/vec_helper.c
145
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_ushl_h)(void *vd, void *vn, void *vm, uint32_t desc)
146
}
147
clear_tail(d, opr_sz, simd_maxsz(desc));
56
}
148
}
57
149
+
58
-static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
150
+/*
59
+static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
151
+ * 8x8->8 polynomial multiply.
60
{
152
+ *
61
gen_set_condexec(s);
153
+ * Polynomial multiplication is like integer multiplication except the
62
- gen_set_pc_im(s, s->base.pc_next - offset);
154
+ * partial products are XORed, not added.
63
+ gen_set_pc_im(s, pc);
155
+ *
64
gen_exception_internal(excp);
156
+ * TODO: expose this as a generic vector operation, as it is a common
65
s->base.is_jmp = DISAS_NORETURN;
157
+ * crypto building block.
66
}
158
+ */
67
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
159
+void HELPER(gvec_pmul_b)(void *vd, void *vn, void *vm, uint32_t desc)
68
s->current_el != 0 &&
160
+{
69
#endif
161
+ intptr_t i, j, opr_sz = simd_oprsz(desc);
70
(imm == (s->thumb ? 0x3c : 0xf000))) {
162
+ uint64_t *d = vd, *n = vn, *m = vm;
71
- gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
163
+
72
+ gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST);
164
+ for (i = 0; i < opr_sz / 8; ++i) {
73
return;
165
+ uint64_t nn = n[i];
74
}
166
+ uint64_t mm = m[i];
75
167
+ uint64_t rr = 0;
76
@@ -XXX,XX +XXX,XX @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
168
+
77
/* End the TB early; it's likely not going to be executed */
169
+ for (j = 0; j < 8; ++j) {
78
dc->base.is_jmp = DISAS_TOO_MANY;
170
+ uint64_t mask = (nn & 0x0101010101010101ull) * 0xff;
79
} else {
171
+ rr ^= mm & mask;
80
- gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
172
+ mm = (mm << 1) & 0xfefefefefefefefeull;
81
+ gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG);
173
+ nn >>= 1;
82
/* The address covered by the breakpoint must be
174
+ }
83
included in [tb->pc, tb->pc + tb->size) in order
175
+ d[i] = rr;
84
to for it to be properly cleared -- thus we
176
+ }
177
+ clear_tail(d, opr_sz, simd_maxsz(desc));
178
+}
85
--
179
--
86
2.20.1
180
2.20.1
87
181
88
182
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/29] target/arm: Remove helper_double_saturate
[PULL 40/52] target/arm: Convert PMULL.64 to gvec
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Replace x = double_saturate(y) with x = add_saturate(y, y).
3
The gvec form will be needed for implementing SVE2.
4
There is no need for a separate more specialized helper.
5
4
5
Tested-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20200216214232.4230-4-richard.henderson@linaro.org
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190807045335.1361-12-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/helper.h | 1 -
11
target/arm/helper.h | 4 +---
13
target/arm/op_helper.c | 15 ---------------
12
target/arm/neon_helper.c | 30 ------------------------------
14
target/arm/translate.c | 4 ++--
13
target/arm/translate-a64.c | 28 +++-------------------------
15
3 files changed, 2 insertions(+), 18 deletions(-)
14
target/arm/translate.c | 16 ++--------------
15
target/arm/vec_helper.c | 33 +++++++++++++++++++++++++++++++++
16
5 files changed, 39 insertions(+), 72 deletions(-)
16
17
17
diff --git a/target/arm/helper.h b/target/arm/helper.h
18
diff --git a/target/arm/helper.h b/target/arm/helper.h
18
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper.h
20
--- a/target/arm/helper.h
20
+++ b/target/arm/helper.h
21
+++ b/target/arm/helper.h
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(add_saturate, i32, env, i32, i32)
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
22
DEF_HELPER_3(sub_saturate, i32, env, i32, i32)
23
DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
23
DEF_HELPER_3(add_usaturate, i32, env, i32, i32)
24
DEF_HELPER_2(dc_zva, void, env, i64)
24
DEF_HELPER_3(sub_usaturate, i32, env, i32, i32)
25
25
-DEF_HELPER_2(double_saturate, i32, env, s32)
26
-DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64)
26
DEF_HELPER_FLAGS_2(sdiv, TCG_CALL_NO_RWG_SE, s32, s32, s32)
27
-DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64)
27
DEF_HELPER_FLAGS_2(udiv, TCG_CALL_NO_RWG_SE, i32, i32, i32)
28
-
28
DEF_HELPER_FLAGS_1(rbit, TCG_CALL_NO_RWG_SE, i32, i32)
29
DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG,
29
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
30
void, ptr, ptr, ptr, ptr, i32)
31
DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s16, TCG_CALL_NO_RWG,
32
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
33
DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
34
35
DEF_HELPER_FLAGS_4(gvec_pmul_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(gvec_pmull_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
37
38
#ifdef TARGET_AARCH64
39
#include "helper-a64.h"
40
diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c
30
index XXXXXXX..XXXXXXX 100644
41
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/op_helper.c
42
--- a/target/arm/neon_helper.c
32
+++ b/target/arm/op_helper.c
43
+++ b/target/arm/neon_helper.c
33
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
44
@@ -XXX,XX +XXX,XX @@ void HELPER(neon_zip16)(void *vd, void *vm)
34
return res;
45
rm[0] = m0;
46
rd[0] = d0;
35
}
47
}
36
48
-
37
-uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
49
-/* Helper function for 64 bit polynomial multiply case:
50
- * perform PolynomialMult(op1, op2) and return either the top or
51
- * bottom half of the 128 bit result.
52
- */
53
-uint64_t HELPER(neon_pmull_64_lo)(uint64_t op1, uint64_t op2)
38
-{
54
-{
39
- uint32_t res;
55
- int bitnum;
40
- if (val >= 0x40000000) {
56
- uint64_t res = 0;
41
- res = ~SIGNBIT;
57
-
42
- env->QF = 1;
58
- for (bitnum = 0; bitnum < 64; bitnum++) {
43
- } else if (val <= (int32_t)0xc0000000) {
59
- if (op1 & (1ULL << bitnum)) {
44
- res = SIGNBIT;
60
- res ^= op2 << bitnum;
45
- env->QF = 1;
61
- }
46
- } else {
47
- res = val << 1;
48
- }
62
- }
49
- return res;
63
- return res;
50
-}
64
-}
65
-uint64_t HELPER(neon_pmull_64_hi)(uint64_t op1, uint64_t op2)
66
-{
67
- int bitnum;
68
- uint64_t res = 0;
51
-
69
-
52
uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
70
- /* bit 0 of op1 can't influence the high 64 bits at all */
53
{
71
- for (bitnum = 1; bitnum < 64; bitnum++) {
54
uint32_t res = a + b;
72
- if (op1 & (1ULL << bitnum)) {
73
- res ^= op2 >> (64 - bitnum);
74
- }
75
- }
76
- return res;
77
-}
78
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/target/arm/translate-a64.c
81
+++ b/target/arm/translate-a64.c
82
@@ -XXX,XX +XXX,XX @@ static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size,
83
clear_vec_high(s, is_q, rd);
84
}
85
86
-static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm)
87
-{
88
- /* PMULL of 64 x 64 -> 128 is an odd special case because it
89
- * is the only three-reg-diff instruction which produces a
90
- * 128-bit wide result from a single operation. However since
91
- * it's possible to calculate the two halves more or less
92
- * separately we just use two helper calls.
93
- */
94
- TCGv_i64 tcg_op1 = tcg_temp_new_i64();
95
- TCGv_i64 tcg_op2 = tcg_temp_new_i64();
96
- TCGv_i64 tcg_res = tcg_temp_new_i64();
97
-
98
- read_vec_element(s, tcg_op1, rn, is_q, MO_64);
99
- read_vec_element(s, tcg_op2, rm, is_q, MO_64);
100
- gen_helper_neon_pmull_64_lo(tcg_res, tcg_op1, tcg_op2);
101
- write_vec_element(s, tcg_res, rd, 0, MO_64);
102
- gen_helper_neon_pmull_64_hi(tcg_res, tcg_op1, tcg_op2);
103
- write_vec_element(s, tcg_res, rd, 1, MO_64);
104
-
105
- tcg_temp_free_i64(tcg_op1);
106
- tcg_temp_free_i64(tcg_op2);
107
- tcg_temp_free_i64(tcg_res);
108
-}
109
-
110
/* AdvSIMD three different
111
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
112
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
113
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
114
if (!fp_access_check(s)) {
115
return;
116
}
117
- handle_pmull_64(s, is_q, rd, rn, rm);
118
+ /* The Q field specifies lo/hi half input for this insn. */
119
+ gen_gvec_op3_ool(s, true, rd, rn, rm, is_q,
120
+ gen_helper_gvec_pmull_q);
121
return;
122
}
123
goto is_widening;
55
diff --git a/target/arm/translate.c b/target/arm/translate.c
124
diff --git a/target/arm/translate.c b/target/arm/translate.c
56
index XXXXXXX..XXXXXXX 100644
125
index XXXXXXX..XXXXXXX 100644
57
--- a/target/arm/translate.c
126
--- a/target/arm/translate.c
58
+++ b/target/arm/translate.c
127
+++ b/target/arm/translate.c
59
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
128
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
60
tmp = load_reg(s, rm);
129
* outside the loop below as it only performs a single pass.
61
tmp2 = load_reg(s, rn);
130
*/
62
if (op1 & 2)
131
if (op == 14 && size == 2) {
63
- gen_helper_double_saturate(tmp2, cpu_env, tmp2);
132
- TCGv_i64 tcg_rn, tcg_rm, tcg_rd;
64
+ gen_helper_add_saturate(tmp2, cpu_env, tmp2, tmp2);
133
-
65
if (op1 & 1)
134
if (!dc_isar_feature(aa32_pmull, s)) {
66
gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2);
135
return 1;
67
else
136
}
68
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
137
- tcg_rn = tcg_temp_new_i64();
69
tmp = load_reg(s, rn);
138
- tcg_rm = tcg_temp_new_i64();
70
tmp2 = load_reg(s, rm);
139
- tcg_rd = tcg_temp_new_i64();
71
if (op & 1)
140
- neon_load_reg64(tcg_rn, rn);
72
- gen_helper_double_saturate(tmp, cpu_env, tmp);
141
- neon_load_reg64(tcg_rm, rm);
73
+ gen_helper_add_saturate(tmp, cpu_env, tmp, tmp);
142
- gen_helper_neon_pmull_64_lo(tcg_rd, tcg_rn, tcg_rm);
74
if (op & 2)
143
- neon_store_reg64(tcg_rd, rd);
75
gen_helper_sub_saturate(tmp, cpu_env, tmp2, tmp);
144
- gen_helper_neon_pmull_64_hi(tcg_rd, tcg_rn, tcg_rm);
76
else
145
- neon_store_reg64(tcg_rd, rd + 1);
146
- tcg_temp_free_i64(tcg_rn);
147
- tcg_temp_free_i64(tcg_rm);
148
- tcg_temp_free_i64(tcg_rd);
149
+ tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, 16, 16,
150
+ 0, gen_helper_gvec_pmull_q);
151
return 0;
152
}
153
154
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
155
index XXXXXXX..XXXXXXX 100644
156
--- a/target/arm/vec_helper.c
157
+++ b/target/arm/vec_helper.c
158
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_pmul_b)(void *vd, void *vn, void *vm, uint32_t desc)
159
}
160
clear_tail(d, opr_sz, simd_maxsz(desc));
161
}
162
+
163
+/*
164
+ * 64x64->128 polynomial multiply.
165
+ * Because of the lanes are not accessed in strict columns,
166
+ * this probably cannot be turned into a generic helper.
167
+ */
168
+void HELPER(gvec_pmull_q)(void *vd, void *vn, void *vm, uint32_t desc)
169
+{
170
+ intptr_t i, j, opr_sz = simd_oprsz(desc);
171
+ intptr_t hi = simd_data(desc);
172
+ uint64_t *d = vd, *n = vn, *m = vm;
173
+
174
+ for (i = 0; i < opr_sz / 8; i += 2) {
175
+ uint64_t nn = n[i + hi];
176
+ uint64_t mm = m[i + hi];
177
+ uint64_t rhi = 0;
178
+ uint64_t rlo = 0;
179
+
180
+ /* Bit 0 can only influence the low 64-bit result. */
181
+ if (nn & 1) {
182
+ rlo = mm;
183
+ }
184
+
185
+ for (j = 1; j < 64; ++j) {
186
+ uint64_t mask = -((nn >> j) & 1);
187
+ rlo ^= (mm << j) & mask;
188
+ rhi ^= (mm >> (64 - j)) & mask;
189
+ }
190
+ d[i] = rlo;
191
+ d[i + 1] = rhi;
192
+ }
193
+ clear_tail(d, opr_sz, simd_maxsz(desc));
194
+}
77
--
195
--
78
2.20.1
196
2.20.1
79
197
80
198
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/29] target/arm: Introduce pc_curr
[PULL 41/52] target/arm: Convert PMULL.8 to gvec
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add a new field to retain the address of the instruction currently
3
We still need two different helpers, since NEON and SVE2 get the
4
being translated. The 32-bit uses are all within subroutines used
4
inputs from different locations within the source vector. However,
5
by a32 and t32. This will become less obvious when t16 support is
5
we can convert both to the same internal form for computation.
6
merged with a32+t32, and having a clear definition will help.
6
7
7
The sve2 helper is not used yet, but adding it with this patch
8
Convert aarch64 as well for consistency. Note that there is one
8
helps illustrate why the neon changes are helpful.
9
instance of a pre-assert fprintf that used the wrong value for the
9
10
address of the current instruction.
10
Tested-by: Alex Bennée <alex.bennee@linaro.org>
11
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Message-id: 20200216214232.4230-5-richard.henderson@linaro.org
14
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Message-id: 20190807045335.1361-3-richard.henderson@linaro.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
15
---
18
target/arm/translate-a64.h | 2 +-
16
target/arm/helper-sve.h | 2 ++
19
target/arm/translate.h | 2 ++
17
target/arm/helper.h | 3 +-
20
target/arm/translate-a64.c | 21 +++++++++++----------
18
target/arm/neon_helper.c | 32 --------------------
21
target/arm/translate.c | 14 ++++++++------
19
target/arm/translate-a64.c | 27 +++++++++++------
22
4 files changed, 22 insertions(+), 17 deletions(-)
20
target/arm/translate.c | 26 ++++++++---------
23
21
target/arm/vec_helper.c | 60 ++++++++++++++++++++++++++++++++++++++
24
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
22
6 files changed, 95 insertions(+), 55 deletions(-)
25
index XXXXXXX..XXXXXXX 100644
23
26
--- a/target/arm/translate-a64.h
24
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
27
+++ b/target/arm/translate-a64.h
25
index XXXXXXX..XXXXXXX 100644
28
@@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s);
26
--- a/target/arm/helper-sve.h
29
qemu_log_mask(LOG_UNIMP, \
27
+++ b/target/arm/helper-sve.h
30
"%s:%d: unsupported instruction encoding 0x%08x " \
28
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_6(sve_stdd_le_zd, TCG_CALL_NO_WG,
31
"at pc=%016" PRIx64 "\n", \
29
void, env, ptr, ptr, ptr, tl, i32)
32
- __FILE__, __LINE__, insn, s->pc - 4); \
30
DEF_HELPER_FLAGS_6(sve_stdd_be_zd, TCG_CALL_NO_WG,
33
+ __FILE__, __LINE__, insn, s->pc_curr); \
31
void, env, ptr, ptr, ptr, tl, i32)
34
unallocated_encoding(s); \
32
+
35
} while (0)
33
+DEF_HELPER_FLAGS_4(sve2_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
36
34
diff --git a/target/arm/helper.h b/target/arm/helper.h
37
diff --git a/target/arm/translate.h b/target/arm/translate.h
35
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/helper.h
39
--- a/target/arm/translate.h
37
+++ b/target/arm/helper.h
40
+++ b/target/arm/translate.h
38
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(neon_sub_u8, i32, i32, i32)
41
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
39
DEF_HELPER_2(neon_sub_u16, i32, i32, i32)
42
const ARMISARegisters *isar;
40
DEF_HELPER_2(neon_mul_u8, i32, i32, i32)
43
41
DEF_HELPER_2(neon_mul_u16, i32, i32, i32)
44
target_ulong pc;
42
-DEF_HELPER_2(neon_mull_p8, i64, i32, i32)
45
+ /* The address of the current instruction being translated. */
43
46
+ target_ulong pc_curr;
44
DEF_HELPER_2(neon_tst_u8, i32, i32, i32)
47
target_ulong page_start;
45
DEF_HELPER_2(neon_tst_u16, i32, i32, i32)
48
uint32_t insn;
46
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
49
/* Nonzero if this instruction has been conditionally skipped. */
47
DEF_HELPER_FLAGS_4(gvec_pmul_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
48
DEF_HELPER_FLAGS_4(gvec_pmull_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
49
50
+DEF_HELPER_FLAGS_4(neon_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
51
+
52
#ifdef TARGET_AARCH64
53
#include "helper-a64.h"
54
#include "helper-sve.h"
55
diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/arm/neon_helper.c
58
+++ b/target/arm/neon_helper.c
59
@@ -XXX,XX +XXX,XX @@ NEON_VOP(mul_u8, neon_u8, 4)
60
NEON_VOP(mul_u16, neon_u16, 2)
61
#undef NEON_FN
62
63
-/* Polynomial multiplication is like integer multiplication except the
64
- partial products are XORed, not added. */
65
-uint64_t HELPER(neon_mull_p8)(uint32_t op1, uint32_t op2)
66
-{
67
- uint64_t result = 0;
68
- uint64_t mask;
69
- uint64_t op2ex = op2;
70
- op2ex = (op2ex & 0xff) |
71
- ((op2ex & 0xff00) << 8) |
72
- ((op2ex & 0xff0000) << 16) |
73
- ((op2ex & 0xff000000) << 24);
74
- while (op1) {
75
- mask = 0;
76
- if (op1 & 1) {
77
- mask |= 0xffff;
78
- }
79
- if (op1 & (1 << 8)) {
80
- mask |= (0xffffU << 16);
81
- }
82
- if (op1 & (1 << 16)) {
83
- mask |= (0xffffULL << 32);
84
- }
85
- if (op1 & (1 << 24)) {
86
- mask |= (0xffffULL << 48);
87
- }
88
- result ^= op2ex & mask;
89
- op1 = (op1 >> 1) & 0x7f7f7f7f;
90
- op2ex <<= 1;
91
- }
92
- return result;
93
-}
94
-
95
#define NEON_FN(dest, src1, src2) dest = (src1 & src2) ? -1 : 0
96
NEON_VOP(tst_u8, neon_u8, 4)
97
NEON_VOP(tst_u16, neon_u16, 2)
50
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
98
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
51
index XXXXXXX..XXXXXXX 100644
99
index XXXXXXX..XXXXXXX 100644
52
--- a/target/arm/translate-a64.c
100
--- a/target/arm/translate-a64.c
53
+++ b/target/arm/translate-a64.c
101
+++ b/target/arm/translate-a64.c
54
@@ -XXX,XX +XXX,XX @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
102
@@ -XXX,XX +XXX,XX @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
55
*/
103
gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env,
56
static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
104
tcg_passres, tcg_passres);
57
{
58
- uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
59
+ uint64_t addr = s->pc_curr + sextract32(insn, 0, 26) * 4;
60
61
if (insn & (1U << 31)) {
62
/* BL Branch with link */
63
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
64
sf = extract32(insn, 31, 1);
65
op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */
66
rt = extract32(insn, 0, 5);
67
- addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
68
+ addr = s->pc_curr + sextract32(insn, 5, 19) * 4;
69
70
tcg_cmp = read_cpu_reg(s, rt, sf);
71
label_match = gen_new_label();
72
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
73
74
bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
75
op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */
76
- addr = s->pc + sextract32(insn, 5, 14) * 4 - 4;
77
+ addr = s->pc_curr + sextract32(insn, 5, 14) * 4;
78
rt = extract32(insn, 0, 5);
79
80
tcg_cmp = tcg_temp_new_i64();
81
@@ -XXX,XX +XXX,XX @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
82
unallocated_encoding(s);
83
return;
84
}
85
- addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
86
+ addr = s->pc_curr + sextract32(insn, 5, 19) * 4;
87
cond = extract32(insn, 0, 4);
88
89
reset_btype(s);
90
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
91
TCGv_i32 tcg_syn, tcg_isread;
92
uint32_t syndrome;
93
94
- gen_a64_set_pc_im(s->pc - 4);
95
+ gen_a64_set_pc_im(s->pc_curr);
96
tmpptr = tcg_const_ptr(ri);
97
syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
98
tcg_syn = tcg_const_i32(syndrome);
99
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
100
/* The pre HVC helper handles cases when HVC gets trapped
101
* as an undefined insn by runtime configuration.
102
*/
103
- gen_a64_set_pc_im(s->pc - 4);
104
+ gen_a64_set_pc_im(s->pc_curr);
105
gen_helper_pre_hvc(cpu_env);
106
gen_ss_advance(s);
107
gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16), 2);
108
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
109
unallocated_encoding(s);
110
break;
105
break;
111
}
106
- case 14: /* PMULL */
112
- gen_a64_set_pc_im(s->pc - 4);
107
- assert(size == 0);
113
+ gen_a64_set_pc_im(s->pc_curr);
108
- gen_helper_neon_mull_p8(tcg_passres, tcg_op1, tcg_op2);
114
tmp = tcg_const_i32(syn_aa64_smc(imm16));
109
- break;
115
gen_helper_pre_smc(cpu_env, tmp);
116
tcg_temp_free_i32(tmp);
117
@@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
118
119
tcg_rt = cpu_reg(s, rt);
120
121
- clean_addr = tcg_const_i64((s->pc - 4) + imm);
122
+ clean_addr = tcg_const_i64(s->pc_curr + imm);
123
if (is_vector) {
124
do_fp_ld(s, rt, clean_addr, size);
125
} else {
126
@@ -XXX,XX +XXX,XX @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
127
offset = sextract64(insn, 5, 19);
128
offset = offset << 2 | extract32(insn, 29, 2);
129
rd = extract32(insn, 0, 5);
130
- base = s->pc - 4;
131
+ base = s->pc_curr;
132
133
if (page) {
134
/* ADRP (page based) */
135
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
136
break;
137
default:
110
default:
138
fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
139
- __func__, insn, fpopcode, s->pc);
140
+ __func__, insn, fpopcode, s->pc_curr);
141
g_assert_not_reached();
111
g_assert_not_reached();
142
}
112
}
143
113
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
144
@@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
114
handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm);
145
{
115
break;
146
uint32_t insn;
116
case 14: /* PMULL, PMULL2 */
147
117
- if (is_u || size == 1 || size == 2) {
148
+ s->pc_curr = s->pc;
118
+ if (is_u) {
149
insn = arm_ldl_code(env, s->pc, s->sctlr_b);
119
unallocated_encoding(s);
150
s->insn = insn;
120
return;
151
s->pc += 4;
121
}
122
- if (size == 3) {
123
+ switch (size) {
124
+ case 0: /* PMULL.P8 */
125
+ if (!fp_access_check(s)) {
126
+ return;
127
+ }
128
+ /* The Q field specifies lo/hi half input for this insn. */
129
+ gen_gvec_op3_ool(s, true, rd, rn, rm, is_q,
130
+ gen_helper_neon_pmull_h);
131
+ break;
132
+
133
+ case 3: /* PMULL.P64 */
134
if (!dc_isar_feature(aa64_pmull, s)) {
135
unallocated_encoding(s);
136
return;
137
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
138
/* The Q field specifies lo/hi half input for this insn. */
139
gen_gvec_op3_ool(s, true, rd, rn, rm, is_q,
140
gen_helper_gvec_pmull_q);
141
- return;
142
+ break;
143
+
144
+ default:
145
+ unallocated_encoding(s);
146
+ break;
147
}
148
- goto is_widening;
149
+ return;
150
case 9: /* SQDMLAL, SQDMLAL2 */
151
case 11: /* SQDMLSL, SQDMLSL2 */
152
case 13: /* SQDMULL, SQDMULL2 */
153
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
154
unallocated_encoding(s);
155
return;
156
}
157
- is_widening:
158
if (!fp_access_check(s)) {
159
return;
160
}
152
diff --git a/target/arm/translate.c b/target/arm/translate.c
161
diff --git a/target/arm/translate.c b/target/arm/translate.c
153
index XXXXXXX..XXXXXXX 100644
162
index XXXXXXX..XXXXXXX 100644
154
--- a/target/arm/translate.c
163
--- a/target/arm/translate.c
155
+++ b/target/arm/translate.c
164
+++ b/target/arm/translate.c
156
@@ -XXX,XX +XXX,XX @@ static inline void gen_hvc(DisasContext *s, int imm16)
165
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
157
* as an undefined insn by runtime configuration (ie before
166
return 1;
158
* the insn really executes).
167
}
159
*/
168
160
- gen_set_pc_im(s, s->pc - 4);
169
- /* Handle VMULL.P64 (Polynomial 64x64 to 128 bit multiply)
161
+ gen_set_pc_im(s, s->pc_curr);
170
- * outside the loop below as it only performs a single pass.
162
gen_helper_pre_hvc(cpu_env);
171
- */
163
/* Otherwise we will treat this as a real exception which
172
- if (op == 14 && size == 2) {
164
* happens after execution of the insn. (The distinction matters
173
- if (!dc_isar_feature(aa32_pmull, s)) {
165
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
174
- return 1;
166
*/
175
+ /* Handle polynomial VMULL in a single pass. */
167
TCGv_i32 tmp;
176
+ if (op == 14) {
168
177
+ if (size == 0) {
169
- gen_set_pc_im(s, s->pc - 4);
178
+ /* VMULL.P8 */
170
+ gen_set_pc_im(s, s->pc_curr);
179
+ tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, 16, 16,
171
tmp = tcg_const_i32(syn_aa32_smc());
180
+ 0, gen_helper_neon_pmull_h);
172
gen_helper_pre_smc(cpu_env, tmp);
181
+ } else {
173
tcg_temp_free_i32(tmp);
182
+ /* VMULL.P64 */
174
@@ -XXX,XX +XXX,XX @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
183
+ if (!dc_isar_feature(aa32_pmull, s)) {
175
184
+ return 1;
176
/* Sync state because msr_banked() can raise exceptions */
185
+ }
177
gen_set_condexec(s);
186
+ tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, 16, 16,
178
- gen_set_pc_im(s, s->pc - 4);
187
+ 0, gen_helper_gvec_pmull_q);
179
+ gen_set_pc_im(s, s->pc_curr);
188
}
180
tcg_reg = load_reg(s, rn);
189
- tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, 16, 16,
181
tcg_tgtmode = tcg_const_i32(tgtmode);
190
- 0, gen_helper_gvec_pmull_q);
182
tcg_regno = tcg_const_i32(regno);
191
return 0;
183
@@ -XXX,XX +XXX,XX @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
192
}
184
193
185
/* Sync state because mrs_banked() can raise exceptions */
194
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
186
gen_set_condexec(s);
195
/* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
187
- gen_set_pc_im(s, s->pc - 4);
196
gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
188
+ gen_set_pc_im(s, s->pc_curr);
197
break;
189
tcg_reg = tcg_temp_new_i32();
198
- case 14: /* Polynomial VMULL */
190
tcg_tgtmode = tcg_const_i32(tgtmode);
199
- gen_helper_neon_mull_p8(cpu_V0, tmp, tmp2);
191
tcg_regno = tcg_const_i32(regno);
200
- tcg_temp_free_i32(tmp2);
192
@@ -XXX,XX +XXX,XX @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
201
- tcg_temp_free_i32(tmp);
193
}
202
- break;
194
203
default: /* 15 is RESERVED: caught earlier */
195
gen_set_condexec(s);
204
abort();
196
- gen_set_pc_im(s, s->pc - 4);
205
}
197
+ gen_set_pc_im(s, s->pc_curr);
206
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
198
tmpptr = tcg_const_ptr(ri);
207
index XXXXXXX..XXXXXXX 100644
199
tcg_syn = tcg_const_i32(syndrome);
208
--- a/target/arm/vec_helper.c
200
tcg_isread = tcg_const_i32(isread);
209
+++ b/target/arm/vec_helper.c
201
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
210
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_pmull_q)(void *vd, void *vn, void *vm, uint32_t desc)
202
tmp = tcg_const_i32(mode);
203
/* get_r13_banked() will raise an exception if called from System mode */
204
gen_set_condexec(s);
205
- gen_set_pc_im(s, s->pc - 4);
206
+ gen_set_pc_im(s, s->pc_curr);
207
gen_helper_get_r13_banked(addr, cpu_env, tmp);
208
tcg_temp_free_i32(tmp);
209
switch (amode) {
210
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
211
return;
212
}
211
}
213
212
clear_tail(d, opr_sz, simd_maxsz(desc));
214
+ dc->pc_curr = dc->pc;
213
}
215
insn = arm_ldl_code(env, dc->pc, dc->sctlr_b);
214
+
216
dc->insn = insn;
215
+/*
217
dc->pc += 4;
216
+ * 8x8->16 polynomial multiply.
218
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
217
+ *
219
return;
218
+ * The byte inputs are expanded to (or extracted from) half-words.
220
}
219
+ * Note that neon and sve2 get the inputs from different positions.
221
220
+ * This allows 4 bytes to be processed in parallel with uint64_t.
222
+ dc->pc_curr = dc->pc;
221
+ */
223
insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);
222
+
224
is_16bit = thumb_insn_is_16bit(dc, dc->pc, insn);
223
+static uint64_t expand_byte_to_half(uint64_t x)
225
dc->pc += 2;
224
+{
225
+ return (x & 0x000000ff)
226
+ | ((x & 0x0000ff00) << 8)
227
+ | ((x & 0x00ff0000) << 16)
228
+ | ((x & 0xff000000) << 24);
229
+}
230
+
231
+static uint64_t pmull_h(uint64_t op1, uint64_t op2)
232
+{
233
+ uint64_t result = 0;
234
+ int i;
235
+
236
+ for (i = 0; i < 8; ++i) {
237
+ uint64_t mask = (op1 & 0x0001000100010001ull) * 0xffff;
238
+ result ^= op2 & mask;
239
+ op1 >>= 1;
240
+ op2 <<= 1;
241
+ }
242
+ return result;
243
+}
244
+
245
+void HELPER(neon_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc)
246
+{
247
+ int hi = simd_data(desc);
248
+ uint64_t *d = vd, *n = vn, *m = vm;
249
+ uint64_t nn = n[hi], mm = m[hi];
250
+
251
+ d[0] = pmull_h(expand_byte_to_half(nn), expand_byte_to_half(mm));
252
+ nn >>= 32;
253
+ mm >>= 32;
254
+ d[1] = pmull_h(expand_byte_to_half(nn), expand_byte_to_half(mm));
255
+
256
+ clear_tail(d, 16, simd_maxsz(desc));
257
+}
258
+
259
+#ifdef TARGET_AARCH64
260
+void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc)
261
+{
262
+ int shift = simd_data(desc) * 8;
263
+ intptr_t i, opr_sz = simd_oprsz(desc);
264
+ uint64_t *d = vd, *n = vn, *m = vm;
265
+
266
+ for (i = 0; i < opr_sz / 8; ++i) {
267
+ uint64_t nn = (n[i] >> shift) & 0x00ff00ff00ff00ffull;
268
+ uint64_t mm = (m[i] >> shift) & 0x00ff00ff00ff00ffull;
269
+
270
+ d[i] = pmull_h(nn, mm);
271
+ }
272
+}
273
+#endif
226
--
274
--
227
2.20.1
275
2.20.1
228
276
229
277
diff view generated by jsdifflib
New patch
[PULL 42/52] xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd
1
From: Francisco Iglesias <francisco.iglesias@xilinx.com>
1
2
3
Correct the number of dummy cycles required by the FAST_READ_4 command (to
4
be eight, one dummy byte).
5
6
Fixes: ef06ca3946 ("xilinx_spips: Add support for RX discard and RX drain")
7
Suggested-by: Cédric Le Goater <clg@kaod.org>
8
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
9
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
Message-id: 20200218113350.6090-1-frasse.iglesias@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/ssi/xilinx_spips.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/ssi/xilinx_spips.c
19
+++ b/hw/ssi/xilinx_spips.c
20
@@ -XXX,XX +XXX,XX @@ static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command)
21
case FAST_READ:
22
case DOR:
23
case QOR:
24
+ case FAST_READ_4:
25
case DOR_4:
26
case QOR_4:
27
return 1;
28
case DIOR:
29
- case FAST_READ_4:
30
case DIOR_4:
31
return 2;
32
case QIOR:
33
--
34
2.20.1
35
36
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/29] Set ENET_BD_BDU in I.MX FEC controller
[PULL 43/52] sh4: Fix PCI ISA IO memory subregion
1
From: Aaron Hill <aa1ronham@gmail.com>
1
From: Guenter Roeck <linux@roeck-us.net>
2
2
3
This commit properly sets the ENET_BD_BDU flag once the emulated FEC controller
3
Booting the r2d machine from flash fails because flash is not discovered.
4
has finished processing the last descriptor. This is done for both transmit
4
Looking at the flattened memory tree, we see the following.
5
and receive descriptors.
6
5
7
This allows the QNX 7.0.0 BSP for the Sabrelite board (which can be
6
FlatView #1
8
found at http://blackberry.qnx.com/en/developers/bsp) to properly
7
AS "memory", root: system
9
control the FEC. Without this patch, the BSP ethernet driver will never
8
AS "cpu-memory-0", root: system
10
re-use FEC descriptors, as the unset ENET_BD_BDU flag will cause
9
AS "sh_pci_host", root: bus master container
11
it to believe that the descriptors are still in use by the NIC.
10
Root memory region: system
11
0000000000000000-000000000000ffff (prio 0, i/o): io
12
0000000000010000-0000000000ffffff (prio 0, i/o): r2d.flash @0000000000010000
12
13
13
Note that Linux does not appear to use this field at all, and is
14
The overlapping memory region is sh_pci.isa, ie the ISA I/O region bridge.
14
unaffected by this patch.
15
This region is initially assigned to address 0xfe240000, but overwritten
16
with a write into the PCIIOBR register. This write is expected to adjust
17
the PCI memory window, but not to change the region's base adddress.
15
18
16
Without this patch, QNX will think that the NIC is still processing its
19
Peter Maydell provided the following detailed explanation.
17
transaction descriptors, and won't send any more data over the network.
18
20
19
For reference:
21
"Section 22.3.7 and in particular figure 22.3 (of "SSH7751R user's manual:
22
hardware") are clear about how this is supposed to work: there is a window
23
at 0xfe240000 in the system register space for PCI I/O space. When the CPU
24
makes an access into that area, the PCI controller calculates the PCI
25
address to use by combining bits 0..17 of the system address with the
26
bits 31..18 value that the guest has put into the PCIIOBR. That is, writing
27
to the PCIIOBR changes which section of the IO address space is visible in
28
the 0xfe240000 window. Instead what QEMU's implementation does is move the
29
window to whatever value the guest writes to the PCIIOBR register -- so if
30
the guest writes 0 we put the window at 0 in system address space."
20
31
21
On page 1192 of the I.MX 6DQ reference manual revision (Rev. 5, 06/2018),
32
Fix the problem by calling memory_region_set_alias_offset() instead of
22
which can be found at https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-6-processors/i.mx-6quad-processors-high-performance-3d-graphics-hd-video-arm-cortex-a9-core:i.MX6Q?&tab=Documentation_Tab&linkline=Application-Note
33
removing and re-adding the PCI ISA subregion on writes into PCIIOBR.
34
At the same time, in sh_pci_device_realize(), don't set iobr since
35
it is overwritten later anyway. Instead, pass the base address to
36
memory_region_add_subregion() directly.
23
37
24
the 'BDU' field is described as follows for the 'Enhanced transmit
38
Many thanks to Peter Maydell for the detailed problem analysis, and for
25
buffer descriptor':
39
providing suggestions on how to fix the problem.
26
40
27
'Last buffer descriptor update done. Indicates that the last BD data has been updated by
41
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
28
uDMA. This field is written by the user (=0) and uDMA (=1).'
42
Message-id: 20200218201050.15273-1-linux@roeck-us.net
29
30
The same description is used for the receive buffer descriptor.
31
32
Signed-off-by: Aaron Hill <aa1ronham@gmail.com>
33
Message-id: 20190805142417.10433-1-aaron.hill@alertinnovation.com
34
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
43
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
44
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
36
---
45
---
37
hw/net/imx_fec.c | 4 ++++
46
hw/sh4/sh_pci.c | 11 +++--------
38
1 file changed, 4 insertions(+)
47
1 file changed, 3 insertions(+), 8 deletions(-)
39
48
40
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
49
diff --git a/hw/sh4/sh_pci.c b/hw/sh4/sh_pci.c
41
index XXXXXXX..XXXXXXX 100644
50
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/net/imx_fec.c
51
--- a/hw/sh4/sh_pci.c
43
+++ b/hw/net/imx_fec.c
52
+++ b/hw/sh4/sh_pci.c
44
@@ -XXX,XX +XXX,XX @@ static void imx_enet_do_tx(IMXFECState *s, uint32_t index)
53
@@ -XXX,XX +XXX,XX @@ static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val,
45
if (bd.option & ENET_BD_TX_INT) {
54
pcic->mbr = val & 0xff000001;
46
s->regs[ENET_EIR] |= int_txf;
55
break;
47
}
56
case 0x1c8:
48
+ /* Indicate that we've updated the last buffer descriptor. */
57
- if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) {
49
+ bd.last_buffer = ENET_BD_BDU;
58
- memory_region_del_subregion(get_system_memory(), &pcic->isa);
50
}
59
- pcic->iobr = val & 0xfffc0001;
51
if (bd.option & ENET_BD_TX_INT) {
60
- memory_region_add_subregion(get_system_memory(),
52
s->regs[ENET_EIR] |= int_txb;
61
- pcic->iobr & 0xfffc0000, &pcic->isa);
53
@@ -XXX,XX +XXX,XX @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
62
- }
54
/* Last buffer in frame. */
63
+ pcic->iobr = val & 0xfffc0001;
55
bd.flags |= flags | ENET_BD_L;
64
+ memory_region_set_alias_offset(&pcic->isa, val & 0xfffc0000);
56
FEC_PRINTF("rx frame flags %04x\n", bd.flags);
65
break;
57
+ /* Indicate that we've updated the last buffer descriptor. */
66
case 0x220:
58
+ bd.last_buffer = ENET_BD_BDU;
67
pci_data_write(phb->bus, pcic->par, val, 4);
59
if (bd.option & ENET_BD_RX_INT) {
68
@@ -XXX,XX +XXX,XX @@ static void sh_pci_device_realize(DeviceState *dev, Error **errp)
60
s->regs[ENET_EIR] |= ENET_INT_RXF;
69
get_system_io(), 0, 0x40000);
61
}
70
sysbus_init_mmio(sbd, &s->memconfig_p4);
71
sysbus_init_mmio(sbd, &s->memconfig_a7);
72
- s->iobr = 0xfe240000;
73
- memory_region_add_subregion(get_system_memory(), s->iobr, &s->isa);
74
+ memory_region_add_subregion(get_system_memory(), 0xfe240000, &s->isa);
75
76
s->dev = pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "sh_pci_host");
77
}
62
--
78
--
63
2.20.1
79
2.20.1
64
80
65
81
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/29] target/arm: Replace offset with pc in gen_exception_insn
[PULL 44/52] target/arm: Rename isar_feature_aa32_simd_r32
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The offset is variable depending on the instruction set, whereas
3
The old name, isar_feature_aa32_fp_d32, does not reflect
4
we have stored values for the current pc and the next pc. Passing
4
the MVFR0 field name, SIMDReg.
5
in the actual value is clearer in intent.
6
5
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20200214181547.21408-3-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
[PMM: wrapped one long line]
10
Message-id: 20190807045335.1361-8-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
12
---
13
target/arm/translate-a64.c | 25 ++++++++++++++-----------
13
target/arm/cpu.h | 2 +-
14
target/arm/translate-vfp.inc.c | 6 +++---
14
target/arm/translate-vfp.inc.c | 53 +++++++++++++++++-----------------
15
target/arm/translate.c | 31 ++++++++++++++++---------------
15
2 files changed, 28 insertions(+), 27 deletions(-)
16
3 files changed, 33 insertions(+), 29 deletions(-)
16
17
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
19
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate-a64.c
19
--- a/target/arm/cpu.h
21
+++ b/target/arm/translate-a64.c
20
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
21
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
23
s->base.is_jmp = DISAS_NORETURN;
22
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
24
}
23
}
25
24
26
-static void gen_exception_insn(DisasContext *s, int offset, int excp,
25
-static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id)
27
+static void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
26
+static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
28
uint32_t syndrome, uint32_t target_el)
29
{
27
{
30
- gen_a64_set_pc_im(s->base.pc_next - offset);
28
/* Return true if D16-D31 are implemented */
31
+ gen_a64_set_pc_im(pc);
29
return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
32
gen_exception(excp, syndrome, target_el);
33
s->base.is_jmp = DISAS_NORETURN;
34
}
35
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
36
void unallocated_encoding(DisasContext *s)
37
{
38
/* Unallocated and reserved encodings are uncategorized */
39
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
40
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
41
default_exception_el(s));
42
}
43
44
@@ -XXX,XX +XXX,XX @@ static inline bool fp_access_check(DisasContext *s)
45
return true;
46
}
47
48
- gen_exception_insn(s, 4, EXCP_UDEF, syn_fp_access_trap(1, 0xe, false),
49
- s->fp_excp_el);
50
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
51
+ syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
52
return false;
53
}
54
55
@@ -XXX,XX +XXX,XX @@ static inline bool fp_access_check(DisasContext *s)
56
bool sve_access_check(DisasContext *s)
57
{
58
if (s->sve_excp_el) {
59
- gen_exception_insn(s, 4, EXCP_UDEF, syn_sve_access_trap(),
60
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_sve_access_trap(),
61
s->sve_excp_el);
62
return false;
63
}
64
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
65
switch (op2_ll) {
66
case 1: /* SVC */
67
gen_ss_advance(s);
68
- gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16),
69
- default_exception_el(s));
70
+ gen_exception_insn(s, s->base.pc_next, EXCP_SWI,
71
+ syn_aa64_svc(imm16), default_exception_el(s));
72
break;
73
case 2: /* HVC */
74
if (s->current_el == 0) {
75
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
76
gen_a64_set_pc_im(s->pc_curr);
77
gen_helper_pre_hvc(cpu_env);
78
gen_ss_advance(s);
79
- gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16), 2);
80
+ gen_exception_insn(s, s->base.pc_next, EXCP_HVC,
81
+ syn_aa64_hvc(imm16), 2);
82
break;
83
case 3: /* SMC */
84
if (s->current_el == 0) {
85
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
86
gen_helper_pre_smc(cpu_env, tmp);
87
tcg_temp_free_i32(tmp);
88
gen_ss_advance(s);
89
- gen_exception_insn(s, 0, EXCP_SMC, syn_aa64_smc(imm16), 3);
90
+ gen_exception_insn(s, s->base.pc_next, EXCP_SMC,
91
+ syn_aa64_smc(imm16), 3);
92
break;
93
default:
94
unallocated_encoding(s);
95
@@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
96
if (s->btype != 0
97
&& s->guarded_page
98
&& !btype_destination_ok(insn, s->bt, s->btype)) {
99
- gen_exception_insn(s, 4, EXCP_UDEF, syn_btitrap(s->btype),
100
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
101
+ syn_btitrap(s->btype),
102
default_exception_el(s));
103
return;
104
}
105
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
30
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
106
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
107
--- a/target/arm/translate-vfp.inc.c
32
--- a/target/arm/translate-vfp.inc.c
108
+++ b/target/arm/translate-vfp.inc.c
33
+++ b/target/arm/translate-vfp.inc.c
109
@@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
34
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
110
{
35
}
111
if (s->fp_excp_el) {
36
112
if (arm_dc_feature(s, ARM_FEATURE_M)) {
37
/* UNDEF accesses to D16-D31 if they don't exist */
113
- gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(),
38
- if (dp && !dc_isar_feature(aa32_fp_d32, s) &&
114
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(),
39
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
115
s->fp_excp_el);
40
((a->vm | a->vn | a->vd) & 0x10)) {
116
} else {
41
return false;
117
- gen_exception_insn(s, 4, EXCP_UDEF,
42
}
118
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
43
@@ -XXX,XX +XXX,XX @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
119
syn_fp_access_trap(1, 0xe, false),
44
}
120
s->fp_excp_el);
45
121
}
46
/* UNDEF accesses to D16-D31 if they don't exist */
122
@@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
47
- if (dp && !dc_isar_feature(aa32_fp_d32, s) &&
123
48
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
124
if (!s->vfp_enabled && !ignore_vfp_enabled) {
49
((a->vm | a->vn | a->vd) & 0x10)) {
125
assert(!arm_dc_feature(s, ARM_FEATURE_M));
50
return false;
126
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
51
}
127
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
52
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
128
default_exception_el(s));
53
}
129
return false;
54
130
}
55
/* UNDEF accesses to D16-D31 if they don't exist */
131
diff --git a/target/arm/translate.c b/target/arm/translate.c
56
- if (dp && !dc_isar_feature(aa32_fp_d32, s) &&
132
index XXXXXXX..XXXXXXX 100644
57
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
133
--- a/target/arm/translate.c
58
((a->vm | a->vd) & 0x10)) {
134
+++ b/target/arm/translate.c
59
return false;
135
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
60
}
136
s->base.is_jmp = DISAS_NORETURN;
61
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
137
}
62
}
138
63
139
-static void gen_exception_insn(DisasContext *s, int offset, int excp,
64
/* UNDEF accesses to D16-D31 if they don't exist */
140
+static void gen_exception_insn(DisasContext *s, uint32_t pc, int excp,
65
- if (dp && !dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
141
int syn, uint32_t target_el)
66
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
142
{
67
return false;
143
gen_set_condexec(s);
68
}
144
- gen_set_pc_im(s, s->base.pc_next - offset);
69
145
+ gen_set_pc_im(s, pc);
70
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
146
gen_exception(excp, syn, target_el);
71
uint32_t offset;
147
s->base.is_jmp = DISAS_NORETURN;
72
148
}
73
/* UNDEF accesses to D16-D31 if they don't exist */
149
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
74
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) {
150
return;
75
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
151
}
76
return false;
152
77
}
153
- gen_exception_insn(s, s->thumb ? 2 : 4, EXCP_UDEF, syn_uncategorized(),
78
154
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
79
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
155
default_exception_el(s));
80
uint32_t offset;
156
}
81
157
82
/* UNDEF accesses to D16-D31 if they don't exist */
158
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
83
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) {
159
84
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
160
undef:
85
return false;
161
/* If we get here then some access check did not pass */
86
}
162
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), exc_target);
87
163
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
88
@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
164
+ syn_uncategorized(), exc_target);
89
}
165
return false;
90
166
}
91
/* UNDEF accesses to D16-D31 if they don't exist */
167
92
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) {
168
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
93
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
169
* for attempts to execute invalid vfp/neon encodings with FP disabled.
94
return false;
95
}
96
97
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a)
170
*/
98
*/
171
if (s->fp_excp_el) {
99
172
- gen_exception_insn(s, 4, EXCP_UDEF,
100
/* UNDEF accesses to D16-D31 if they don't exist */
173
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
101
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
174
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
102
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
175
return 0;
103
return false;
176
}
104
}
177
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
105
178
* for attempts to execute invalid vfp/neon encodings with FP disabled.
106
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
179
*/
107
TCGv_i64 tmp;
180
if (s->fp_excp_el) {
108
181
- gen_exception_insn(s, 4, EXCP_UDEF,
109
/* UNDEF accesses to D16-D31 if they don't exist */
182
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
110
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
183
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
111
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
184
return 0;
112
return false;
185
}
113
}
186
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
114
187
}
115
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
188
116
}
189
if (s->fp_excp_el) {
117
190
- gen_exception_insn(s, 4, EXCP_UDEF,
118
/* UNDEF accesses to D16-D31 if they don't exist */
191
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
119
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd + n) > 16) {
192
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
120
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd + n) > 16) {
193
return 0;
121
return false;
194
}
122
}
195
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
123
196
off_rm = vfp_reg_offset(0, rm);
124
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
197
}
125
TCGv_ptr fpst;
198
if (s->fp_excp_el) {
126
199
- gen_exception_insn(s, 4, EXCP_UDEF,
127
/* UNDEF accesses to D16-D31 if they don't exist */
200
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
128
- if (!dc_isar_feature(aa32_fp_d32, s) && ((vd | vn | vm) & 0x10)) {
201
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
129
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
202
return 0;
130
return false;
203
}
131
}
204
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
132
205
* For the UNPREDICTABLE cases we choose to UNDEF.
133
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
206
*/
134
TCGv_i64 f0, fd;
207
if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) {
135
208
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), 3);
136
/* UNDEF accesses to D16-D31 if they don't exist */
209
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), 3);
137
- if (!dc_isar_feature(aa32_fp_d32, s) && ((vd | vm) & 0x10)) {
210
return;
138
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
211
}
139
return false;
212
140
}
213
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
141
214
}
142
@@ -XXX,XX +XXX,XX @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
215
143
}
216
if (undef) {
144
217
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
145
/* UNDEF accesses to D16-D31 if they don't exist. */
218
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
146
- if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vn | a->vm) & 0x10)) {
219
default_exception_el(s));
147
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
220
return;
148
+ ((a->vd | a->vn | a->vm) & 0x10)) {
221
}
149
return false;
222
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
150
}
223
* UsageFault exception.
151
224
*/
152
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
225
if (arm_dc_feature(s, ARM_FEATURE_M)) {
153
vd = a->vd;
226
- gen_exception_insn(s, 4, EXCP_INVSTATE, syn_uncategorized(),
154
227
+ gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
155
/* UNDEF accesses to D16-D31 if they don't exist. */
228
default_exception_el(s));
156
- if (!dc_isar_feature(aa32_fp_d32, s) && (vd & 0x10)) {
229
return;
157
+ if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
230
}
158
return false;
231
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
159
}
232
break;
160
233
default:
161
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
234
illegal_op:
162
}
235
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
163
236
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
164
/* UNDEF accesses to D16-D31 if they don't exist. */
237
default_exception_el(s));
165
- if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) {
238
break;
166
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
239
}
167
return false;
240
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
168
}
241
}
169
242
170
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
243
/* All other insns: NOCP */
171
}
244
- gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(),
172
245
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(),
173
/* UNDEF accesses to D16-D31 if they don't exist. */
246
default_exception_el(s));
174
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
247
break;
175
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
248
}
176
return false;
249
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
177
}
250
}
178
251
return;
179
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
252
illegal_op:
180
}
253
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
181
254
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
182
/* UNDEF accesses to D16-D31 if they don't exist. */
255
default_exception_el(s));
183
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
256
}
184
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
257
185
return false;
258
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
186
}
259
return;
187
260
illegal_op:
188
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
261
undef:
189
}
262
- gen_exception_insn(s, 2, EXCP_UDEF, syn_uncategorized(),
190
263
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
191
/* UNDEF accesses to D16-D31 if they don't exist. */
264
default_exception_el(s));
192
- if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) {
265
}
193
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
194
return false;
195
}
196
197
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
198
}
199
200
/* UNDEF accesses to D16-D31 if they don't exist. */
201
- if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) {
202
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
203
return false;
204
}
205
206
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
207
}
208
209
/* UNDEF accesses to D16-D31 if they don't exist. */
210
- if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) {
211
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
212
return false;
213
}
214
215
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
216
TCGv_i32 vm;
217
218
/* UNDEF accesses to D16-D31 if they don't exist. */
219
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
220
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
221
return false;
222
}
223
224
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
225
TCGv_i32 vd;
226
227
/* UNDEF accesses to D16-D31 if they don't exist. */
228
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
229
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
230
return false;
231
}
232
233
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
234
TCGv_ptr fpst;
235
236
/* UNDEF accesses to D16-D31 if they don't exist. */
237
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
238
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
239
return false;
240
}
241
242
@@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
243
}
244
245
/* UNDEF accesses to D16-D31 if they don't exist. */
246
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
247
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
248
return false;
249
}
250
251
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
252
}
253
254
/* UNDEF accesses to D16-D31 if they don't exist. */
255
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
256
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
257
return false;
258
}
259
260
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
261
TCGv_ptr fpst;
262
263
/* UNDEF accesses to D16-D31 if they don't exist. */
264
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
265
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
266
return false;
267
}
266
268
267
--
269
--
268
2.20.1
270
2.20.1
269
271
270
272
diff view generated by jsdifflib
[Qemu-devel] [PULL 25/29] target/arm: Remove redundant shift tests
[PULL 45/52] target/arm: Use isar_feature_aa32_simd_r32 more places
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The immediate shift generator functions already test for,
3
Many uses of ARM_FEATURE_VFP3 are testing for the number of simd
4
and eliminate, the case of a shift by zero.
4
registers implemented. Use the proper test vs MVFR0.SIMDReg.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190808202616.13782-4-richard.henderson@linaro.org
7
Message-id: 20200214181547.21408-4-richard.henderson@linaro.org
8
[PMM: fix typo in commit message]
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
target/arm/translate.c | 19 +++++++------------
12
target/arm/cpu.c | 9 ++++-----
12
1 file changed, 7 insertions(+), 12 deletions(-)
13
target/arm/helper.c | 13 ++++++-------
14
target/arm/translate.c | 2 +-
15
3 files changed, 11 insertions(+), 13 deletions(-)
13
16
17
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.c
20
+++ b/target/arm/cpu.c
21
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
22
23
if (flags & CPU_DUMP_FPU) {
24
int numvfpregs = 0;
25
- if (arm_feature(env, ARM_FEATURE_VFP)) {
26
- numvfpregs += 16;
27
- }
28
- if (arm_feature(env, ARM_FEATURE_VFP3)) {
29
- numvfpregs += 16;
30
+ if (cpu_isar_feature(aa32_simd_r32, cpu)) {
31
+ numvfpregs = 32;
32
+ } else if (arm_feature(env, ARM_FEATURE_VFP)) {
33
+ numvfpregs = 16;
34
}
35
for (i = 0; i < numvfpregs; i++) {
36
uint64_t v = *aa32_vfp_dreg(env, i);
37
diff --git a/target/arm/helper.c b/target/arm/helper.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/helper.c
40
+++ b/target/arm/helper.c
41
@@ -XXX,XX +XXX,XX @@ static void switch_mode(CPUARMState *env, int mode);
42
43
static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
44
{
45
- int nregs;
46
+ ARMCPU *cpu = env_archcpu(env);
47
+ int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
48
49
/* VFP data registers are always little-endian. */
50
- nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
51
if (reg < nregs) {
52
stq_le_p(buf, *aa32_vfp_dreg(env, reg));
53
return 8;
54
@@ -XXX,XX +XXX,XX @@ static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
55
56
static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
57
{
58
- int nregs;
59
+ ARMCPU *cpu = env_archcpu(env);
60
+ int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
61
62
- nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
63
if (reg < nregs) {
64
*aa32_vfp_dreg(env, reg) = ldq_le_p(buf);
65
return 8;
66
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
67
/* VFPv3 and upwards with NEON implement 32 double precision
68
* registers (D0-D31).
69
*/
70
- if (!arm_feature(env, ARM_FEATURE_NEON) ||
71
- !arm_feature(env, ARM_FEATURE_VFP3)) {
72
+ if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) {
73
/* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
74
value |= (1 << 30);
75
}
76
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
77
} else if (arm_feature(env, ARM_FEATURE_NEON)) {
78
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
79
51, "arm-neon.xml", 0);
80
- } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
81
+ } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
82
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
83
35, "arm-vfp3.xml", 0);
84
} else if (arm_feature(env, ARM_FEATURE_VFP)) {
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
85
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
index XXXXXXX..XXXXXXX 100644
86
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
87
--- a/target/arm/translate.c
17
+++ b/target/arm/translate.c
88
+++ b/target/arm/translate.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
89
@@ -XXX,XX +XXX,XX @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
19
shift = (insn >> 10) & 3;
90
#define VFP_SREG(insn, bigbit, smallbit) \
20
/* ??? In many cases it's not necessary to do a
91
((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
21
rotate, a shift is sufficient. */
92
#define VFP_DREG(reg, insn, bigbit, smallbit) do { \
22
- if (shift != 0)
93
- if (arm_dc_feature(s, ARM_FEATURE_VFP3)) { \
23
- tcg_gen_rotri_i32(tmp, tmp, shift * 8);
94
+ if (dc_isar_feature(aa32_simd_r32, s)) { \
24
+ tcg_gen_rotri_i32(tmp, tmp, shift * 8);
95
reg = (((insn) >> (bigbit)) & 0x0f) \
25
op1 = (insn >> 20) & 7;
96
| (((insn) >> ((smallbit) - 4)) & 0x10); \
26
switch (op1) {
97
} else { \
27
case 0: gen_sxtb16(tmp); break;
28
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
29
shift = (insn >> 4) & 3;
30
/* ??? In many cases it's not necessary to do a
31
rotate, a shift is sufficient. */
32
- if (shift != 0)
33
- tcg_gen_rotri_i32(tmp, tmp, shift * 8);
34
+ tcg_gen_rotri_i32(tmp, tmp, shift * 8);
35
op = (insn >> 20) & 7;
36
switch (op) {
37
case 0: gen_sxth(tmp); break;
38
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
39
case 7:
40
goto illegal_op;
41
default: /* Saturate. */
42
- if (shift) {
43
- if (op & 1)
44
- tcg_gen_sari_i32(tmp, tmp, shift);
45
- else
46
- tcg_gen_shli_i32(tmp, tmp, shift);
47
+ if (op & 1) {
48
+ tcg_gen_sari_i32(tmp, tmp, shift);
49
+ } else {
50
+ tcg_gen_shli_i32(tmp, tmp, shift);
51
}
52
tmp2 = tcg_const_i32(imm);
53
if (op & 4) {
54
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
55
goto illegal_op;
56
}
57
tmp = load_reg(s, rm);
58
- if (shift) {
59
- tcg_gen_shli_i32(tmp, tmp, shift);
60
- }
61
+ tcg_gen_shli_i32(tmp, tmp, shift);
62
tcg_gen_add_i32(addr, addr, tmp);
63
tcg_temp_free_i32(tmp);
64
break;
65
--
98
--
66
2.20.1
99
2.20.1
67
100
68
101
diff view generated by jsdifflib
[Qemu-devel] [PULL 24/29] target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB
[PULL 46/52] target/arm: Set MVFR0.FPSP for ARMv5 cpus
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Use deposit as the composit operation to merge the
3
We are going to convert FEATURE tests to ISAR tests,
4
bits from the two inputs.
4
so FPSP needs to be set for these cpus, like we have
5
already for FPDP.
5
6
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190808202616.13782-3-richard.henderson@linaro.org
8
Message-id: 20200214181547.21408-5-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
target/arm/translate.c | 26 ++++++++++----------------
12
target/arm/cpu.c | 10 ++++++----
12
1 file changed, 10 insertions(+), 16 deletions(-)
13
1 file changed, 6 insertions(+), 4 deletions(-)
13
14
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
17
--- a/target/arm/cpu.c
17
+++ b/target/arm/translate.c
18
+++ b/target/arm/cpu.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
19
@@ -XXX,XX +XXX,XX @@ static void arm926_initfn(Object *obj)
19
shift = (insn >> 7) & 0x1f;
20
*/
20
if (insn & (1 << 6)) {
21
cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
21
/* pkhtb */
22
/*
22
- if (shift == 0)
23
- * Similarly, we need to set MVFR0 fields to enable double precision
23
+ if (shift == 0) {
24
- * and short vector support even though ARMv5 doesn't have this register.
24
shift = 31;
25
+ * Similarly, we need to set MVFR0 fields to enable vfp and short vector
25
+ }
26
+ * support even though ARMv5 doesn't have this register.
26
tcg_gen_sari_i32(tmp2, tmp2, shift);
27
*/
27
- tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
28
cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
28
- tcg_gen_ext16u_i32(tmp2, tmp2);
29
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
29
+ tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16);
30
cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
30
} else {
31
}
31
/* pkhbt */
32
32
- if (shift)
33
@@ -XXX,XX +XXX,XX @@ static void arm1026_initfn(Object *obj)
33
- tcg_gen_shli_i32(tmp2, tmp2, shift);
34
*/
34
- tcg_gen_ext16u_i32(tmp, tmp);
35
cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
35
- tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
36
/*
36
+ tcg_gen_shli_i32(tmp2, tmp2, shift);
37
- * Similarly, we need to set MVFR0 fields to enable double precision
37
+ tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16);
38
- * and short vector support even though ARMv5 doesn't have this register.
38
}
39
+ * Similarly, we need to set MVFR0 fields to enable vfp and short vector
39
- tcg_gen_or_i32(tmp, tmp, tmp2);
40
+ * support even though ARMv5 doesn't have this register.
40
tcg_temp_free_i32(tmp2);
41
*/
41
store_reg(s, rd, tmp);
42
cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
42
} else if ((insn & 0x00200020) == 0x00200000) {
43
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
43
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
44
cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
44
shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3);
45
45
if (insn & (1 << 5)) {
46
{
46
/* pkhtb */
47
- if (shift == 0)
48
+ if (shift == 0) {
49
shift = 31;
50
+ }
51
tcg_gen_sari_i32(tmp2, tmp2, shift);
52
- tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
53
- tcg_gen_ext16u_i32(tmp2, tmp2);
54
+ tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16);
55
} else {
56
/* pkhbt */
57
- if (shift)
58
- tcg_gen_shli_i32(tmp2, tmp2, shift);
59
- tcg_gen_ext16u_i32(tmp, tmp);
60
- tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
61
+ tcg_gen_shli_i32(tmp2, tmp2, shift);
62
+ tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16);
63
}
64
- tcg_gen_or_i32(tmp, tmp, tmp2);
65
tcg_temp_free_i32(tmp2);
66
store_reg(s, rd, tmp);
67
} else {
68
--
47
--
69
2.20.1
48
2.20.1
70
49
71
50
diff view generated by jsdifflib
[Qemu-devel] [PULL 23/29] target/arm: Use tcg_gen_extract_i32 for shifter_out_im
[PULL 47/52] target/arm: Add isar_feature_aa32_simd_r16
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Extract is a compact combination of shift + and.
3
Use this in the places that were checking ARM_FEATURE_VFP, and
4
are obviously testing for the existance of the register set
5
as opposed to testing for some particular instruction extension.
4
6
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20190808202616.13782-2-richard.henderson@linaro.org
8
Message-id: 20200214181547.21408-6-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
11
---
10
target/arm/translate.c | 9 +--------
12
target/arm/cpu.h | 6 ++++++
11
1 file changed, 1 insertion(+), 8 deletions(-)
13
hw/intc/armv7m_nvic.c | 20 ++++++++++----------
12
14
linux-user/arm/signal.c | 4 ++--
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
target/arm/arch_dump.c | 11 ++++++-----
14
index XXXXXXX..XXXXXXX 100644
16
target/arm/cpu.c | 8 ++++----
15
--- a/target/arm/translate.c
17
target/arm/helper.c | 4 ++--
16
+++ b/target/arm/translate.c
18
target/arm/m_helper.c | 11 ++++++-----
17
@@ -XXX,XX +XXX,XX @@ static void gen_sar(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
19
target/arm/machine.c | 3 +--
18
20
8 files changed, 37 insertions(+), 30 deletions(-)
19
static void shifter_out_im(TCGv_i32 var, int shift)
21
22
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/cpu.h
25
+++ b/target/arm/cpu.h
26
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
27
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
28
}
29
30
+static inline bool isar_feature_aa32_simd_r16(const ARMISARegisters *id)
31
+{
32
+ /* Return true if D0-D15 are implemented */
33
+ return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
34
+}
35
+
36
static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
20
{
37
{
21
- if (shift == 0) {
38
/* Return true if D16-D31 are implemented */
22
- tcg_gen_andi_i32(cpu_CF, var, 1);
39
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
23
- } else {
40
index XXXXXXX..XXXXXXX 100644
24
- tcg_gen_shri_i32(cpu_CF, var, shift);
41
--- a/hw/intc/armv7m_nvic.c
25
- if (shift != 31) {
42
+++ b/hw/intc/armv7m_nvic.c
26
- tcg_gen_andi_i32(cpu_CF, cpu_CF, 1);
43
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
27
- }
44
case 0xd84: /* CSSELR */
28
- }
45
return cpu->env.v7m.csselr[attrs.secure];
29
+ tcg_gen_extract_i32(cpu_CF, var, shift, 1);
46
case 0xd88: /* CPACR */
47
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
48
+ if (!cpu_isar_feature(aa32_simd_r16, cpu)) {
49
return 0;
50
}
51
return cpu->env.v7m.cpacr[attrs.secure];
52
case 0xd8c: /* NSACR */
53
- if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
54
+ if (!attrs.secure || !cpu_isar_feature(aa32_simd_r16, cpu)) {
55
return 0;
56
}
57
return cpu->env.v7m.nsacr;
58
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
59
}
60
return cpu->env.v7m.sfar;
61
case 0xf34: /* FPCCR */
62
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
63
+ if (!cpu_isar_feature(aa32_simd_r16, cpu)) {
64
return 0;
65
}
66
if (attrs.secure) {
67
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
68
return value;
69
}
70
case 0xf38: /* FPCAR */
71
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
72
+ if (!cpu_isar_feature(aa32_simd_r16, cpu)) {
73
return 0;
74
}
75
return cpu->env.v7m.fpcar[attrs.secure];
76
case 0xf3c: /* FPDSCR */
77
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
78
+ if (!cpu_isar_feature(aa32_simd_r16, cpu)) {
79
return 0;
80
}
81
return cpu->env.v7m.fpdscr[attrs.secure];
82
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
83
}
84
break;
85
case 0xd88: /* CPACR */
86
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
87
+ if (cpu_isar_feature(aa32_simd_r16, cpu)) {
88
/* We implement only the Floating Point extension's CP10/CP11 */
89
cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20);
90
}
91
break;
92
case 0xd8c: /* NSACR */
93
- if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
94
+ if (attrs.secure && cpu_isar_feature(aa32_simd_r16, cpu)) {
95
/* We implement only the Floating Point extension's CP10/CP11 */
96
cpu->env.v7m.nsacr = value & (3 << 10);
97
}
98
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
99
break;
100
}
101
case 0xf34: /* FPCCR */
102
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
103
+ if (cpu_isar_feature(aa32_simd_r16, cpu)) {
104
/* Not all bits here are banked. */
105
uint32_t fpccr_s;
106
107
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
108
}
109
break;
110
case 0xf38: /* FPCAR */
111
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
112
+ if (cpu_isar_feature(aa32_simd_r16, cpu)) {
113
value &= ~7;
114
cpu->env.v7m.fpcar[attrs.secure] = value;
115
}
116
break;
117
case 0xf3c: /* FPDSCR */
118
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
119
+ if (cpu_isar_feature(aa32_simd_r16, cpu)) {
120
value &= 0x07c00000;
121
cpu->env.v7m.fpdscr[attrs.secure] = value;
122
}
123
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
124
index XXXXXXX..XXXXXXX 100644
125
--- a/linux-user/arm/signal.c
126
+++ b/linux-user/arm/signal.c
127
@@ -XXX,XX +XXX,XX @@ static void setup_sigframe_v2(struct target_ucontext_v2 *uc,
128
setup_sigcontext(&uc->tuc_mcontext, env, set->sig[0]);
129
/* Save coprocessor signal frame. */
130
regspace = uc->tuc_regspace;
131
- if (arm_feature(env, ARM_FEATURE_VFP)) {
132
+ if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env))) {
133
regspace = setup_sigframe_v2_vfp(regspace, env);
134
}
135
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
136
@@ -XXX,XX +XXX,XX @@ static int do_sigframe_return_v2(CPUARMState *env,
137
138
/* Restore coprocessor signal frame */
139
regspace = uc->tuc_regspace;
140
- if (arm_feature(env, ARM_FEATURE_VFP)) {
141
+ if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env))) {
142
regspace = restore_sigframe_v2_vfp(env, regspace);
143
if (!regspace) {
144
return 1;
145
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
146
index XXXXXXX..XXXXXXX 100644
147
--- a/target/arm/arch_dump.c
148
+++ b/target/arm/arch_dump.c
149
@@ -XXX,XX +XXX,XX @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
150
int cpuid, void *opaque)
151
{
152
struct arm_note note;
153
- CPUARMState *env = &ARM_CPU(cs)->env;
154
+ ARMCPU *cpu = ARM_CPU(cs);
155
+ CPUARMState *env = &cpu->env;
156
DumpState *s = opaque;
157
- int ret, i, fpvalid = !!arm_feature(env, ARM_FEATURE_VFP);
158
+ int ret, i;
159
+ bool fpvalid = cpu_isar_feature(aa32_simd_r16, cpu);
160
161
arm_note_init(&note, s, "CORE", 5, NT_PRSTATUS, sizeof(note.prstatus));
162
163
@@ -XXX,XX +XXX,XX @@ int cpu_get_dump_info(ArchDumpInfo *info,
164
ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
165
{
166
ARMCPU *cpu = ARM_CPU(first_cpu);
167
- CPUARMState *env = &cpu->env;
168
size_t note_size;
169
170
if (class == ELFCLASS64) {
171
@@ -XXX,XX +XXX,XX @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
172
note_size += AARCH64_PRFPREG_NOTE_SIZE;
173
#ifdef TARGET_AARCH64
174
if (cpu_isar_feature(aa64_sve, cpu)) {
175
- note_size += AARCH64_SVE_NOTE_SIZE(env);
176
+ note_size += AARCH64_SVE_NOTE_SIZE(&cpu->env);
177
}
178
#endif
179
} else {
180
note_size = ARM_PRSTATUS_NOTE_SIZE;
181
- if (arm_feature(env, ARM_FEATURE_VFP)) {
182
+ if (cpu_isar_feature(aa32_simd_r16, cpu)) {
183
note_size += ARM_VFP_NOTE_SIZE;
184
}
185
}
186
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
187
index XXXXXXX..XXXXXXX 100644
188
--- a/target/arm/cpu.c
189
+++ b/target/arm/cpu.c
190
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
191
env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
192
}
193
194
- if (arm_feature(env, ARM_FEATURE_VFP)) {
195
+ if (cpu_isar_feature(aa32_simd_r16, cpu)) {
196
env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
197
env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
198
R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
199
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
200
int numvfpregs = 0;
201
if (cpu_isar_feature(aa32_simd_r32, cpu)) {
202
numvfpregs = 32;
203
- } else if (arm_feature(env, ARM_FEATURE_VFP)) {
204
+ } else if (cpu_isar_feature(aa32_simd_r16, cpu)) {
205
numvfpregs = 16;
206
}
207
for (i = 0; i < numvfpregs; i++) {
208
@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
209
* KVM does not currently allow us to lie to the guest about its
210
* ID/feature registers, so the guest always sees what the host has.
211
*/
212
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
213
+ if (cpu_isar_feature(aa32_simd_r16, cpu)) {
214
cpu->has_vfp = true;
215
if (!kvm_enabled()) {
216
qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property);
217
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
218
* We rely on no XScale CPU having VFP so we can use the same bits in the
219
* TB flags field for VECSTRIDE and XSCALE_CPAR.
220
*/
221
- assert(!(arm_feature(env, ARM_FEATURE_VFP) &&
222
+ assert(!(cpu_isar_feature(aa32_simd_r16, cpu) &&
223
arm_feature(env, ARM_FEATURE_XSCALE)));
224
225
if (arm_feature(env, ARM_FEATURE_V7) &&
226
diff --git a/target/arm/helper.c b/target/arm/helper.c
227
index XXXXXXX..XXXXXXX 100644
228
--- a/target/arm/helper.c
229
+++ b/target/arm/helper.c
230
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
231
* ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
232
* TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
233
*/
234
- if (arm_feature(env, ARM_FEATURE_VFP)) {
235
+ if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env))) {
236
/* VFP coprocessor: cp10 & cp11 [23:20] */
237
mask |= (1 << 31) | (1 << 30) | (0xf << 20);
238
239
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
240
} else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
241
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
242
35, "arm-vfp3.xml", 0);
243
- } else if (arm_feature(env, ARM_FEATURE_VFP)) {
244
+ } else if (cpu_isar_feature(aa32_simd_r16, cpu)) {
245
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
246
19, "arm-vfp.xml", 0);
247
}
248
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
249
index XXXXXXX..XXXXXXX 100644
250
--- a/target/arm/m_helper.c
251
+++ b/target/arm/m_helper.c
252
@@ -XXX,XX +XXX,XX @@ static uint32_t v7m_integrity_sig(CPUARMState *env, uint32_t lr)
253
*/
254
uint32_t sig = 0xfefa125a;
255
256
- if (!arm_feature(env, ARM_FEATURE_VFP) || (lr & R_V7M_EXCRET_FTYPE_MASK)) {
257
+ if (!cpu_isar_feature(aa32_simd_r16, env_archcpu(env))
258
+ || (lr & R_V7M_EXCRET_FTYPE_MASK)) {
259
sig |= 1;
260
}
261
return sig;
262
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
263
264
if (dotailchain) {
265
/* Sanitize LR FType and PREFIX bits */
266
- if (!arm_feature(env, ARM_FEATURE_VFP)) {
267
+ if (!cpu_isar_feature(aa32_simd_r16, cpu)) {
268
lr |= R_V7M_EXCRET_FTYPE_MASK;
269
}
270
lr = deposit32(lr, 24, 8, 0xff);
271
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
272
273
ftype = excret & R_V7M_EXCRET_FTYPE_MASK;
274
275
- if (!arm_feature(env, ARM_FEATURE_VFP) && !ftype) {
276
+ if (!ftype && !cpu_isar_feature(aa32_simd_r16, cpu)) {
277
qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception "
278
"exit PC value 0x%" PRIx32 " is UNPREDICTABLE "
279
"if FPU not present\n",
280
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
281
* SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 == 0,
282
* RES0 if the FPU is not present, and is stored in the S bank
283
*/
284
- if (arm_feature(env, ARM_FEATURE_VFP) &&
285
+ if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env)) &&
286
extract32(env->v7m.nsacr, 10, 1)) {
287
env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK;
288
env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_FPCA_MASK;
289
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
290
env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK;
291
env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;
292
}
293
- if (arm_feature(env, ARM_FEATURE_VFP)) {
294
+ if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env))) {
295
/*
296
* SFPA is RAZ/WI from NS or if no FPU.
297
* FPCA is RO if NSACR.CP10 == 0, RES0 if the FPU is not present.
298
diff --git a/target/arm/machine.c b/target/arm/machine.c
299
index XXXXXXX..XXXXXXX 100644
300
--- a/target/arm/machine.c
301
+++ b/target/arm/machine.c
302
@@ -XXX,XX +XXX,XX @@
303
static bool vfp_needed(void *opaque)
304
{
305
ARMCPU *cpu = opaque;
306
- CPUARMState *env = &cpu->env;
307
308
- return arm_feature(env, ARM_FEATURE_VFP);
309
+ return cpu_isar_feature(aa32_simd_r16, cpu);
30
}
310
}
31
311
32
/* Shift by immediate. Includes special handling for shift == 0. */
312
static int get_fpscr(QEMUFile *f, void *opaque, size_t size,
33
--
313
--
34
2.20.1
314
2.20.1
35
315
36
316
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/29] target/arm: Remove redundant s->pc & ~1
[PULL 48/52] target/arm: Rename isar_feature_aa32_fpdp_v2
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The thumb bit has already been removed from s->pc, and is always even.
3
The old name, isar_feature_aa32_fpdp, does not reflect
4
that the test includes VFPv2. We will introduce further
5
feature tests for VFPv3.
4
6
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20200214181547.21408-7-richard.henderson@linaro.org
10
[PMM: fixed grammar in commit message]
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20190807045335.1361-6-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
13
---
11
target/arm/translate.c | 10 +++++-----
14
target/arm/cpu.h | 4 ++--
12
1 file changed, 5 insertions(+), 5 deletions(-)
15
target/arm/translate-vfp.inc.c | 40 +++++++++++++++++-----------------
13
16
2 files changed, 22 insertions(+), 22 deletions(-)
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
17
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
20
--- a/target/arm/cpu.h
17
+++ b/target/arm/translate.c
21
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, int offset, uint32_t syn)
22
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
19
/* Force a TB lookup after an instruction that changes the CPU state. */
23
return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
20
static inline void gen_lookup_tb(DisasContext *s)
24
}
25
26
-static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
27
+static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
21
{
28
{
22
- tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
29
- /* Return true if CPU supports double precision floating point */
23
+ tcg_gen_movi_i32(cpu_R[15], s->pc);
30
+ /* Return true if CPU supports double precision floating point, VFPv2 */
24
s->base.is_jmp = DISAS_EXIT;
31
return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
25
}
32
}
26
33
27
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
34
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
28
* self-modifying code correctly and also to take
35
index XXXXXXX..XXXXXXX 100644
29
* any pending interrupts immediately.
36
--- a/target/arm/translate-vfp.inc.c
30
*/
37
+++ b/target/arm/translate-vfp.inc.c
31
- gen_goto_tb(s, 0, s->pc & ~1);
38
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
32
+ gen_goto_tb(s, 0, s->pc);
39
return false;
33
return;
40
}
34
case 7: /* sb */
41
35
if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
42
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
36
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
43
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
37
* for TCG; MB and end the TB instead.
44
return false;
38
*/
45
}
39
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
46
40
- gen_goto_tb(s, 0, s->pc & ~1);
47
@@ -XXX,XX +XXX,XX @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
41
+ gen_goto_tb(s, 0, s->pc);
48
return false;
42
return;
49
}
43
default:
50
44
goto illegal_op;
51
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
45
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
52
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
46
* and also to take any pending interrupts
53
return false;
47
* immediately.
54
}
48
*/
55
49
- gen_goto_tb(s, 0, s->pc & ~1);
56
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
50
+ gen_goto_tb(s, 0, s->pc);
57
return false;
51
break;
58
}
52
case 7: /* sb */
59
53
if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
60
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
54
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
61
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
55
* for TCG; MB and end the TB instead.
62
return false;
56
*/
63
}
57
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
64
58
- gen_goto_tb(s, 0, s->pc & ~1);
65
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
59
+ gen_goto_tb(s, 0, s->pc);
66
return false;
60
break;
67
}
61
default:
68
62
goto illegal_op;
69
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
70
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
71
return false;
72
}
73
74
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
75
return false;
76
}
77
78
- if (!dc_isar_feature(aa32_fpdp, s)) {
79
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
80
return false;
81
}
82
83
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
84
return false;
85
}
86
87
- if (!dc_isar_feature(aa32_fpdp, s)) {
88
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
89
return false;
90
}
91
92
@@ -XXX,XX +XXX,XX @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
93
return false;
94
}
95
96
- if (!dc_isar_feature(aa32_fpdp, s)) {
97
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
98
return false;
99
}
100
101
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
102
return false;
103
}
104
105
- if (!dc_isar_feature(aa32_fpdp, s)) {
106
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
107
return false;
108
}
109
110
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
111
return false;
112
}
113
114
- if (!dc_isar_feature(aa32_fpdp, s)) {
115
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
116
return false;
117
}
118
119
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
120
return false;
121
}
122
123
- if (!dc_isar_feature(aa32_fpdp, s)) {
124
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
125
return false;
126
}
127
128
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
129
return false;
130
}
131
132
- if (!dc_isar_feature(aa32_fpdp, s)) {
133
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
134
return false;
135
}
136
137
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
138
return false;
139
}
140
141
- if (!dc_isar_feature(aa32_fpdp, s)) {
142
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
143
return false;
144
}
145
146
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
147
return false;
148
}
149
150
- if (!dc_isar_feature(aa32_fpdp, s)) {
151
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
152
return false;
153
}
154
155
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
156
return false;
157
}
158
159
- if (!dc_isar_feature(aa32_fpdp, s)) {
160
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
161
return false;
162
}
163
164
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
165
return false;
166
}
167
168
- if (!dc_isar_feature(aa32_fpdp, s)) {
169
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
170
return false;
171
}
172
173
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
174
return false;
175
}
176
177
- if (!dc_isar_feature(aa32_fpdp, s)) {
178
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
179
return false;
180
}
181
182
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
183
return false;
184
}
185
186
- if (!dc_isar_feature(aa32_fpdp, s)) {
187
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
188
return false;
189
}
190
191
@@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
192
return false;
193
}
194
195
- if (!dc_isar_feature(aa32_fpdp, s)) {
196
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
197
return false;
198
}
199
200
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
201
return false;
202
}
203
204
- if (!dc_isar_feature(aa32_fpdp, s)) {
205
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
206
return false;
207
}
208
209
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
210
return false;
211
}
212
213
- if (!dc_isar_feature(aa32_fpdp, s)) {
214
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
215
return false;
216
}
217
63
--
218
--
64
2.20.1
219
2.20.1
65
220
66
221
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/29] target/arm: Pass in pc to thumb_insn_is_16bit
[PULL 49/52] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This function is used in two different contexts, and it will be
3
We will shortly use these to test for VFPv2 and VFPv3
4
clearer if the function is given the address to which it applies.
4
in different situations.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200214181547.21408-8-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190807045335.1361-2-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/translate.c | 14 +++++++-------
11
target/arm/cpu.h | 18 ++++++++++++++++++
13
1 file changed, 7 insertions(+), 7 deletions(-)
12
1 file changed, 18 insertions(+)
14
13
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.c
16
--- a/target/arm/cpu.h
18
+++ b/target/arm/translate.c
17
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
18
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
20
}
19
return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
21
}
20
}
22
21
23
-static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
22
+static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
24
+static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn)
23
+{
24
+ /* Return true if CPU supports single precision floating point, VFPv2 */
25
+ return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
26
+}
27
+
28
+static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
29
+{
30
+ /* Return true if CPU supports single precision floating point, VFPv3 */
31
+ return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
32
+}
33
+
34
static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
25
{
35
{
26
- /* Return true if this is a 16 bit instruction. We must be precise
36
/* Return true if CPU supports double precision floating point, VFPv2 */
27
- * about this (matching the decode). We assume that s->pc still
37
return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
28
- * points to the first 16 bits of the insn.
29
+ /*
30
+ * Return true if this is a 16 bit instruction. We must be precise
31
+ * about this (matching the decode).
32
*/
33
if ((insn >> 11) < 0x1d) {
34
/* Definitely a 16-bit instruction */
35
@@ -XXX,XX +XXX,XX @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
36
return false;
37
}
38
39
- if ((insn >> 11) == 0x1e && s->pc - s->page_start < TARGET_PAGE_SIZE - 3) {
40
+ if ((insn >> 11) == 0x1e && pc - s->page_start < TARGET_PAGE_SIZE - 3) {
41
/* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix
42
* is not on the next page; we merge this into a 32-bit
43
* insn.
44
@@ -XXX,XX +XXX,XX @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
45
*/
46
uint16_t insn = arm_lduw_code(env, s->pc, s->sctlr_b);
47
48
- return !thumb_insn_is_16bit(s, insn);
49
+ return !thumb_insn_is_16bit(s, s->pc, insn);
50
}
38
}
51
39
52
static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
40
+static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
53
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
41
+{
54
}
42
+ /* Return true if CPU supports double precision floating point, VFPv3 */
55
43
+ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
56
insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);
44
+}
57
- is_16bit = thumb_insn_is_16bit(dc, insn);
45
+
58
+ is_16bit = thumb_insn_is_16bit(dc, dc->pc, insn);
46
/*
59
dc->pc += 2;
47
* We always set the FP and SIMD FP16 fields to indicate identical
60
if (!is_16bit) {
48
* levels of support (assuming SIMD is implemented at all), so
61
uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b);
62
--
49
--
63
2.20.1
50
2.20.1
64
51
65
52
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/29] target/arm: Introduce add_reg_for_lit
[PULL 50/52] target/arm: Perform fpdp_v2 check first
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Provide a common routine for the places that require ALIGN(PC, 4)
3
Shuffle the order of the checks so that we test the ISA
4
as the base address as opposed to plain PC. The two are always
4
before we test anything else, such as the register arguments.
5
the same for A32, but the difference is meaningful for thumb mode.
6
5
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200214181547.21408-9-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 20190807045335.1361-5-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
target/arm/translate-vfp.inc.c | 38 ++------
11
target/arm/translate-vfp.inc.c | 144 ++++++++++++++++-----------------
14
target/arm/translate.c | 166 +++++++++++++++------------------
12
1 file changed, 72 insertions(+), 72 deletions(-)
15
2 files changed, 82 insertions(+), 122 deletions(-)
16
13
17
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
14
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate-vfp.inc.c
16
--- a/target/arm/translate-vfp.inc.c
20
+++ b/target/arm/translate-vfp.inc.c
17
+++ b/target/arm/translate-vfp.inc.c
21
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
18
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
22
offset = -offset;
19
return false;
23
}
20
}
24
21
25
- if (s->thumb && a->rn == 15) {
22
- /* UNDEF accesses to D16-D31 if they don't exist */
26
- /* This is actually UNPREDICTABLE */
23
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
27
- addr = tcg_temp_new_i32();
24
- ((a->vm | a->vn | a->vd) & 0x10)) {
28
- tcg_gen_movi_i32(addr, s->pc & ~2);
25
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
29
- } else {
26
return false;
30
- addr = load_reg(s, a->rn);
27
}
31
- }
28
32
- tcg_gen_addi_i32(addr, addr, offset);
29
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
33
+ /* For thumb, use of PC is UNPREDICTABLE. */
30
+ /* UNDEF accesses to D16-D31 if they don't exist */
34
+ addr = add_reg_for_lit(s, a->rn, offset);
31
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
35
tmp = tcg_temp_new_i32();
32
+ ((a->vm | a->vn | a->vd) & 0x10)) {
36
if (a->l) {
33
return false;
37
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
34
}
38
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
35
39
offset = -offset;
36
@@ -XXX,XX +XXX,XX @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
40
}
37
return false;
41
38
}
42
- if (s->thumb && a->rn == 15) {
39
43
- /* This is actually UNPREDICTABLE */
40
- /* UNDEF accesses to D16-D31 if they don't exist */
44
- addr = tcg_temp_new_i32();
41
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
45
- tcg_gen_movi_i32(addr, s->pc & ~2);
42
- ((a->vm | a->vn | a->vd) & 0x10)) {
46
- } else {
43
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
47
- addr = load_reg(s, a->rn);
44
return false;
48
- }
45
}
49
- tcg_gen_addi_i32(addr, addr, offset);
46
50
+ /* For thumb, use of PC is UNPREDICTABLE. */
47
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
51
+ addr = add_reg_for_lit(s, a->rn, offset);
48
+ /* UNDEF accesses to D16-D31 if they don't exist */
52
tmp = tcg_temp_new_i64();
49
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
53
if (a->l) {
50
+ ((a->vm | a->vn | a->vd) & 0x10)) {
54
gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
51
return false;
55
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
52
}
56
return true;
53
57
}
54
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
58
55
return false;
59
- if (s->thumb && a->rn == 15) {
56
}
60
- /* This is actually UNPREDICTABLE */
57
61
- addr = tcg_temp_new_i32();
58
- /* UNDEF accesses to D16-D31 if they don't exist */
62
- tcg_gen_movi_i32(addr, s->pc & ~2);
59
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
63
- } else {
60
- ((a->vm | a->vd) & 0x10)) {
64
- addr = load_reg(s, a->rn);
61
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
65
- }
62
return false;
66
+ /* For thumb, use of PC is UNPREDICTABLE. */
63
}
67
+ addr = add_reg_for_lit(s, a->rn, 0);
64
68
if (a->p) {
65
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
69
/* pre-decrement */
66
+ /* UNDEF accesses to D16-D31 if they don't exist */
70
tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
67
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
71
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
68
+ ((a->vm | a->vd) & 0x10)) {
72
return true;
69
return false;
73
}
70
}
74
71
75
- if (s->thumb && a->rn == 15) {
72
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
76
- /* This is actually UNPREDICTABLE */
73
return false;
77
- addr = tcg_temp_new_i32();
74
}
78
- tcg_gen_movi_i32(addr, s->pc & ~2);
75
79
- } else {
76
- /* UNDEF accesses to D16-D31 if they don't exist */
80
- addr = load_reg(s, a->rn);
77
- if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
81
- }
78
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
82
+ /* For thumb, use of PC is UNPREDICTABLE. */
79
return false;
83
+ addr = add_reg_for_lit(s, a->rn, 0);
80
}
84
if (a->p) {
81
85
/* pre-decrement */
82
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
86
tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
83
+ /* UNDEF accesses to D16-D31 if they don't exist */
87
diff --git a/target/arm/translate.c b/target/arm/translate.c
84
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
88
index XXXXXXX..XXXXXXX 100644
85
return false;
89
--- a/target/arm/translate.c
86
}
90
+++ b/target/arm/translate.c
87
91
@@ -XXX,XX +XXX,XX @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg)
88
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
92
return tmp;
89
TCGv_i64 f0, f1, fd;
93
}
90
TCGv_ptr fpst;
94
91
95
+/*
92
- /* UNDEF accesses to D16-D31 if they don't exist */
96
+ * Create a new temp, REG + OFS, except PC is ALIGN(PC, 4).
93
- if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
97
+ * This is used for load/store for which use of PC implies (literal),
94
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
98
+ * or ADD that implies ADR.
95
return false;
99
+ */
96
}
100
+static TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs)
97
101
+{
98
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
102
+ TCGv_i32 tmp = tcg_temp_new_i32();
99
+ /* UNDEF accesses to D16-D31 if they don't exist */
103
+
100
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
104
+ if (reg == 15) {
101
return false;
105
+ tcg_gen_movi_i32(tmp, (read_pc(s) & ~3) + ofs);
102
}
106
+ } else {
103
107
+ tcg_gen_addi_i32(tmp, cpu_R[reg], ofs);
104
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
108
+ }
105
int veclen = s->vec_len;
109
+ return tmp;
106
TCGv_i64 f0, fd;
110
+}
107
111
+
108
- /* UNDEF accesses to D16-D31 if they don't exist */
112
/* Set a CPU register. The source must be a temporary and will be
109
- if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
113
marked as dead. */
110
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
114
static void store_reg(DisasContext *s, int reg, TCGv_i32 var)
111
return false;
115
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
112
}
116
*/
113
117
bool wback = extract32(insn, 21, 1);
114
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
118
115
+ /* UNDEF accesses to D16-D31 if they don't exist */
119
- if (rn == 15) {
116
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
120
- if (insn & (1 << 21)) {
117
return false;
121
- /* UNPREDICTABLE */
118
}
122
- goto illegal_op;
119
123
- }
120
@@ -XXX,XX +XXX,XX @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
124
- addr = tcg_temp_new_i32();
121
return false;
125
- tcg_gen_movi_i32(addr, s->pc & ~3);
122
}
126
- } else {
123
127
- addr = load_reg(s, rn);
124
- /* UNDEF accesses to D16-D31 if they don't exist. */
128
+ if (rn == 15 && (insn & (1 << 21))) {
125
- if (!dc_isar_feature(aa32_simd_r32, s) &&
129
+ /* UNPREDICTABLE */
126
- ((a->vd | a->vn | a->vm) & 0x10)) {
130
+ goto illegal_op;
127
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
131
}
128
return false;
132
+
129
}
133
+ addr = add_reg_for_lit(s, rn, 0);
130
134
offset = (insn & 0xff) * 4;
131
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
135
if ((insn & (1 << 23)) == 0) {
132
+ /* UNDEF accesses to D16-D31 if they don't exist. */
136
offset = -offset;
133
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
137
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
134
+ ((a->vd | a->vn | a->vm) & 0x10)) {
138
store_reg(s, rd, tmp);
135
return false;
139
} else {
136
}
140
/* Add/sub 12-bit immediate. */
137
141
- if (rn == 15) {
138
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
142
- offset = s->pc & ~(uint32_t)3;
139
143
- if (insn & (1 << 23))
140
vd = a->vd;
144
- offset -= imm;
141
145
- else
142
- /* UNDEF accesses to D16-D31 if they don't exist. */
146
- offset += imm;
143
- if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
147
- tmp = tcg_temp_new_i32();
144
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
148
- tcg_gen_movi_i32(tmp, offset);
145
return false;
149
- store_reg(s, rd, tmp);
146
}
150
+ if (insn & (1 << 23)) {
147
151
+ imm = -imm;
148
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
152
+ }
149
+ /* UNDEF accesses to D16-D31 if they don't exist. */
153
+ tmp = add_reg_for_lit(s, rn, imm);
150
+ if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
154
+ if (rn == 13 && rd == 13) {
151
return false;
155
+ /* ADD SP, SP, imm or SUB SP, SP, imm */
152
}
156
+ store_sp_checked(s, tmp);
153
157
} else {
154
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
158
- tmp = load_reg(s, rn);
155
{
159
- if (insn & (1 << 23))
156
TCGv_i64 vd, vm;
160
- tcg_gen_subi_i32(tmp, tmp, imm);
157
161
- else
158
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
162
- tcg_gen_addi_i32(tmp, tmp, imm);
159
+ return false;
163
- if (rn == 13 && rd == 13) {
160
+ }
164
- /* ADD SP, SP, imm or SUB SP, SP, imm */
161
+
165
- store_sp_checked(s, tmp);
162
/* Vm/M bits must be zero for the Z variant */
166
- } else {
163
if (a->z && a->vm != 0) {
167
- store_reg(s, rd, tmp);
164
return false;
168
- }
165
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
169
+ store_reg(s, rd, tmp);
166
return false;
170
}
167
}
171
}
168
172
}
169
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
173
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
170
- return false;
174
}
171
- }
175
}
172
-
176
memidx = get_mem_index(s);
173
if (!vfp_access_check(s)) {
177
- if (rn == 15) {
174
return true;
178
- addr = tcg_temp_new_i32();
175
}
179
- /* PC relative. */
176
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
180
- /* s->pc has already been incremented by 4. */
177
TCGv_i32 tmp;
181
- imm = s->pc & 0xfffffffc;
178
TCGv_i64 vd;
182
- if (insn & (1 << 23))
179
183
- imm += insn & 0xfff;
180
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
184
- else
181
+ return false;
185
- imm -= insn & 0xfff;
182
+ }
186
- tcg_gen_movi_i32(addr, imm);
183
+
187
+ imm = insn & 0xfff;
184
if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
188
+ if (insn & (1 << 23)) {
185
return false;
189
+ /* PC relative or Positive offset. */
186
}
190
+ addr = add_reg_for_lit(s, rn, imm);
187
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
191
+ } else if (rn == 15) {
188
return false;
192
+ /* PC relative with negative offset. */
189
}
193
+ addr = add_reg_for_lit(s, rn, -imm);
190
194
} else {
191
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
195
addr = load_reg(s, rn);
192
- return false;
196
- if (insn & (1 << 23)) {
193
- }
197
- /* Positive offset. */
194
-
198
- imm = insn & 0xfff;
195
if (!vfp_access_check(s)) {
199
- tcg_gen_addi_i32(addr, addr, imm);
196
return true;
200
- } else {
197
}
201
- imm = insn & 0xff;
198
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
202
- switch ((insn >> 8) & 0xf) {
199
TCGv_i32 tmp;
203
- case 0x0: /* Shifted Register. */
200
TCGv_i64 vm;
204
- shift = (insn >> 4) & 0xf;
201
205
- if (shift > 3) {
202
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
206
- tcg_temp_free_i32(addr);
203
+ return false;
207
- goto illegal_op;
204
+ }
208
- }
205
+
209
- tmp = load_reg(s, rm);
206
if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
210
- if (shift)
207
return false;
211
- tcg_gen_shli_i32(tmp, tmp, shift);
208
}
212
- tcg_gen_add_i32(addr, addr, tmp);
209
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
213
- tcg_temp_free_i32(tmp);
210
return false;
214
- break;
211
}
215
- case 0xc: /* Negative offset. */
212
216
- tcg_gen_addi_i32(addr, addr, -imm);
213
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
217
- break;
214
- return false;
218
- case 0xe: /* User privilege. */
215
- }
219
- tcg_gen_addi_i32(addr, addr, imm);
216
-
220
- memidx = get_a32_user_mem_index(s);
217
if (!vfp_access_check(s)) {
221
- break;
218
return true;
222
- case 0x9: /* Post-decrement. */
219
}
223
- imm = -imm;
220
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
224
- /* Fall through. */
221
TCGv_ptr fpst;
225
- case 0xb: /* Post-increment. */
222
TCGv_i64 tmp;
226
- postinc = 1;
223
227
- writeback = 1;
224
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
228
- break;
225
+ return false;
229
- case 0xd: /* Pre-decrement. */
226
+ }
230
- imm = -imm;
227
+
231
- /* Fall through. */
228
if (!dc_isar_feature(aa32_vrint, s)) {
232
- case 0xf: /* Pre-increment. */
229
return false;
233
- writeback = 1;
230
}
234
- break;
231
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
235
- default:
232
return false;
236
+ imm = insn & 0xff;
233
}
237
+ switch ((insn >> 8) & 0xf) {
234
238
+ case 0x0: /* Shifted Register. */
235
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
239
+ shift = (insn >> 4) & 0xf;
236
- return false;
240
+ if (shift > 3) {
237
- }
241
tcg_temp_free_i32(addr);
238
-
242
goto illegal_op;
239
if (!vfp_access_check(s)) {
243
}
240
return true;
244
+ tmp = load_reg(s, rm);
241
}
245
+ if (shift) {
242
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
246
+ tcg_gen_shli_i32(tmp, tmp, shift);
243
TCGv_i64 tmp;
247
+ }
244
TCGv_i32 tcg_rmode;
248
+ tcg_gen_add_i32(addr, addr, tmp);
245
249
+ tcg_temp_free_i32(tmp);
246
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
250
+ break;
247
+ return false;
251
+ case 0xc: /* Negative offset. */
248
+ }
252
+ tcg_gen_addi_i32(addr, addr, -imm);
249
+
253
+ break;
250
if (!dc_isar_feature(aa32_vrint, s)) {
254
+ case 0xe: /* User privilege. */
251
return false;
255
+ tcg_gen_addi_i32(addr, addr, imm);
252
}
256
+ memidx = get_a32_user_mem_index(s);
253
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
257
+ break;
254
return false;
258
+ case 0x9: /* Post-decrement. */
255
}
259
+ imm = -imm;
256
260
+ /* Fall through. */
257
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
261
+ case 0xb: /* Post-increment. */
258
- return false;
262
+ postinc = 1;
259
- }
263
+ writeback = 1;
260
-
264
+ break;
261
if (!vfp_access_check(s)) {
265
+ case 0xd: /* Pre-decrement. */
262
return true;
266
+ imm = -imm;
263
}
267
+ /* Fall through. */
264
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
268
+ case 0xf: /* Pre-increment. */
265
TCGv_ptr fpst;
269
+ writeback = 1;
266
TCGv_i64 tmp;
270
+ break;
267
271
+ default:
268
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
272
+ tcg_temp_free_i32(addr);
269
+ return false;
273
+ goto illegal_op;
270
+ }
274
}
271
+
275
}
272
if (!dc_isar_feature(aa32_vrint, s)) {
276
273
return false;
277
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
274
}
278
if (insn & (1 << 11)) {
275
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
279
rd = (insn >> 8) & 7;
276
return false;
280
/* load pc-relative. Bit 1 of PC is ignored. */
277
}
281
- val = read_pc(s) + ((insn & 0xff) * 4);
278
282
- val &= ~(uint32_t)2;
279
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
283
- addr = tcg_temp_new_i32();
280
- return false;
284
- tcg_gen_movi_i32(addr, val);
281
- }
285
+ addr = add_reg_for_lit(s, 15, (insn & 0xff) * 4);
282
-
286
tmp = tcg_temp_new_i32();
283
if (!vfp_access_check(s)) {
287
gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
284
return true;
288
rd | ISSIs16Bit);
285
}
289
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
286
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
290
* - Add PC/SP (immediate)
287
TCGv_i64 vd;
291
*/
288
TCGv_i32 vm;
292
rd = (insn >> 8) & 7;
289
293
- if (insn & (1 << 11)) {
290
- /* UNDEF accesses to D16-D31 if they don't exist. */
294
- /* SP */
291
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
295
- tmp = load_reg(s, 13);
292
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
296
- } else {
293
return false;
297
- /* PC. bit 1 is ignored. */
294
}
298
- tmp = tcg_temp_new_i32();
295
299
- tcg_gen_movi_i32(tmp, read_pc(s) & ~(uint32_t)2);
296
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
300
- }
297
+ /* UNDEF accesses to D16-D31 if they don't exist. */
301
val = (insn & 0xff) * 4;
298
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
302
- tcg_gen_addi_i32(tmp, tmp, val);
299
return false;
303
+ tmp = add_reg_for_lit(s, insn & (1 << 11) ? 13 : 15, val);
300
}
304
store_reg(s, rd, tmp);
301
305
break;
302
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
303
TCGv_i64 vm;
304
TCGv_i32 vd;
305
306
- /* UNDEF accesses to D16-D31 if they don't exist. */
307
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
308
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
309
return false;
310
}
311
312
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
313
+ /* UNDEF accesses to D16-D31 if they don't exist. */
314
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
315
return false;
316
}
317
318
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
319
TCGv_i64 vd;
320
TCGv_ptr fpst;
321
322
- /* UNDEF accesses to D16-D31 if they don't exist. */
323
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
324
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
325
return false;
326
}
327
328
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
329
+ /* UNDEF accesses to D16-D31 if they don't exist. */
330
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
331
return false;
332
}
333
334
@@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
335
TCGv_i32 vd;
336
TCGv_i64 vm;
337
338
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
339
+ return false;
340
+ }
341
+
342
if (!dc_isar_feature(aa32_jscvt, s)) {
343
return false;
344
}
345
@@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
346
return false;
347
}
348
349
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
350
- return false;
351
- }
352
-
353
if (!vfp_access_check(s)) {
354
return true;
355
}
356
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
357
TCGv_ptr fpst;
358
int frac_bits;
359
360
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
361
+ return false;
362
+ }
363
+
364
if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
365
return false;
366
}
367
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
368
return false;
369
}
370
371
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
372
- return false;
373
- }
374
-
375
if (!vfp_access_check(s)) {
376
return true;
377
}
378
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
379
TCGv_i64 vm;
380
TCGv_ptr fpst;
381
382
- /* UNDEF accesses to D16-D31 if they don't exist. */
383
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
384
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
385
return false;
386
}
387
388
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
389
+ /* UNDEF accesses to D16-D31 if they don't exist. */
390
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
391
return false;
392
}
306
393
307
--
394
--
308
2.20.1
395
2.20.1
309
396
310
397
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/29] target/arm: Use unallocated_encoding for aarch32
[PULL 51/52] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Promote this function from aarch64 to fully general use.
3
Sort this check to the start of a trans_* function.
4
Use it to unify the code sequences for generating illegal
4
Merge this with any existing test for fpdp_v2.
5
opcode exceptions.
6
5
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200214181547.21408-10-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 20190807045335.1361-11-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
target/arm/translate-a64.h | 2 --
11
target/arm/translate-vfp.inc.c | 24 ++++++++----------------
14
target/arm/translate.h | 2 ++
12
1 file changed, 8 insertions(+), 16 deletions(-)
15
target/arm/translate-a64.c | 7 -------
16
target/arm/translate-vfp.inc.c | 3 +--
17
target/arm/translate.c | 22 ++++++++++++----------
18
5 files changed, 15 insertions(+), 21 deletions(-)
19
13
20
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/translate-a64.h
23
+++ b/target/arm/translate-a64.h
24
@@ -XXX,XX +XXX,XX @@
25
#ifndef TARGET_ARM_TRANSLATE_A64_H
26
#define TARGET_ARM_TRANSLATE_A64_H
27
28
-void unallocated_encoding(DisasContext *s);
29
-
30
#define unsupported_encoding(s, insn) \
31
do { \
32
qemu_log_mask(LOG_UNIMP, \
33
diff --git a/target/arm/translate.h b/target/arm/translate.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/translate.h
36
+++ b/target/arm/translate.h
37
@@ -XXX,XX +XXX,XX @@ typedef struct DisasCompare {
38
bool value_global;
39
} DisasCompare;
40
41
+void unallocated_encoding(DisasContext *s);
42
+
43
/* Share the TCG temporaries common between 32 and 64 bit modes. */
44
extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
45
extern TCGv_i64 cpu_exclusive_addr;
46
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/translate-a64.c
49
+++ b/target/arm/translate-a64.c
50
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
51
}
52
}
53
54
-void unallocated_encoding(DisasContext *s)
55
-{
56
- /* Unallocated and reserved encodings are uncategorized */
57
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
58
- default_exception_el(s));
59
-}
60
-
61
static void init_tmp_a64_array(DisasContext *s)
62
{
63
#ifdef CONFIG_DEBUG_TCG
64
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
14
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
65
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
66
--- a/target/arm/translate-vfp.inc.c
16
--- a/target/arm/translate-vfp.inc.c
67
+++ b/target/arm/translate-vfp.inc.c
17
+++ b/target/arm/translate-vfp.inc.c
68
@@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
18
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
69
19
* VFPv2 allows access to FPSID from userspace; VFPv3 restricts
70
if (!s->vfp_enabled && !ignore_vfp_enabled) {
20
* all ID registers to privileged access only.
71
assert(!arm_dc_feature(s, ARM_FEATURE_M));
21
*/
72
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
22
- if (IS_USER(s) && arm_dc_feature(s, ARM_FEATURE_VFP3)) {
73
- default_exception_el(s));
23
+ if (IS_USER(s) && dc_isar_feature(aa32_fpsp_v3, s)) {
74
+ unallocated_encoding(s);
24
return false;
25
}
26
ignore_vfp_enabled = true;
27
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
28
case ARM_VFP_FPINST:
29
case ARM_VFP_FPINST2:
30
/* Not present in VFPv3 */
31
- if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_VFP3)) {
32
+ if (IS_USER(s) || dc_isar_feature(aa32_fpsp_v3, s)) {
33
return false;
34
}
35
break;
36
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
37
38
vd = a->vd;
39
40
- if (!dc_isar_feature(aa32_fpshvec, s) &&
41
- (veclen != 0 || s->vec_stride != 0)) {
42
+ if (!dc_isar_feature(aa32_fpsp_v3, s)) {
75
return false;
43
return false;
76
}
44
}
77
45
78
diff --git a/target/arm/translate.c b/target/arm/translate.c
46
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
79
index XXXXXXX..XXXXXXX 100644
47
+ if (!dc_isar_feature(aa32_fpshvec, s) &&
80
--- a/target/arm/translate.c
48
+ (veclen != 0 || s->vec_stride != 0)) {
81
+++ b/target/arm/translate.c
49
return false;
82
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
83
s->base.is_jmp = DISAS_NORETURN;
84
}
85
86
+void unallocated_encoding(DisasContext *s)
87
+{
88
+ /* Unallocated and reserved encodings are uncategorized */
89
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
90
+ default_exception_el(s));
91
+}
92
+
93
/* Force a TB lookup after an instruction that changes the CPU state. */
94
static inline void gen_lookup_tb(DisasContext *s)
95
{
96
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
97
return;
98
}
50
}
99
51
100
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
52
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
101
- default_exception_el(s));
53
102
+ unallocated_encoding(s);
54
vd = a->vd;
103
}
55
104
56
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
105
static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
57
+ if (!dc_isar_feature(aa32_fpdp_v3, s)) {
106
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
58
return false;
107
}
59
}
108
60
109
if (undef) {
61
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
110
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
62
return false;
111
- default_exception_el(s));
112
+ unallocated_encoding(s);
113
return;
114
}
63
}
115
64
116
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
65
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
117
break;
66
- return false;
118
default:
67
- }
119
illegal_op:
68
-
120
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
69
if (!vfp_access_check(s)) {
121
- default_exception_el(s));
70
return true;
122
+ unallocated_encoding(s);
123
break;
124
}
125
}
71
}
126
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
72
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
73
TCGv_ptr fpst;
74
int frac_bits;
75
76
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
77
+ if (!dc_isar_feature(aa32_fpsp_v3, s)) {
78
return false;
127
}
79
}
128
return;
80
129
illegal_op:
81
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
130
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
82
TCGv_ptr fpst;
131
- default_exception_el(s));
83
int frac_bits;
132
+ unallocated_encoding(s);
84
133
}
85
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
134
86
- return false;
135
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
87
- }
136
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
88
-
137
return;
89
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
138
illegal_op:
90
+ if (!dc_isar_feature(aa32_fpdp_v3, s)) {
139
undef:
91
return false;
140
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
92
}
141
- default_exception_el(s));
93
142
+ unallocated_encoding(s);
143
}
144
145
static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
146
--
94
--
147
2.20.1
95
2.20.1
148
96
149
97
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/29] target/arm: Introduce read_pc
[PULL 52/52] target/arm: Add missing checks for fpsp_v2
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We currently have 3 different ways of computing the architectural
3
We will eventually remove the early ARM_FEATURE_VFP test,
4
value of "PC" as seen in the ARM ARM.
4
so add a proper test for each trans_* that does not already
5
5
have another ISA test.
6
The value of s->pc has been incremented past the current insn,
7
but that is all. Thus for a32, PC = s->pc + 4; for t32, PC = s->pc;
8
for t16, PC = s->pc + 2. These differing computations make it
9
impossible at present to unify the various code paths.
10
11
With the newly introduced s->pc_curr, we can compute the correct
12
value for all cases, using the formula given in the ARM ARM.
13
14
This changes the behaviour for load_reg() and load_reg_var()
15
when called with reg==15 from a 32-bit Thumb instruction:
16
previously they would have returned the incorrect value
17
of pc_curr + 6, and now they will return the architecturally
18
correct value of PC, which is pc_curr + 4. This will not
19
affect well-behaved guest software, because all of the places
20
we call these functions from T32 code are instructions where
21
using r15 is UNPREDICTABLE. Using the architectural PC value
22
here is more consistent with the T16 and A32 behaviour.
23
6
24
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200214181547.21408-11-richard.henderson@linaro.org
25
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
26
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
27
Message-id: 20190807045335.1361-4-richard.henderson@linaro.org
28
[PMM: added commit message note about UNPREDICTABLE T32 cases]
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
---
11
---
31
target/arm/translate.c | 59 ++++++++++++++++--------------------------
12
target/arm/translate-vfp.inc.c | 78 ++++++++++++++++++++++++++++++----
32
1 file changed, 23 insertions(+), 36 deletions(-)
13
1 file changed, 69 insertions(+), 9 deletions(-)
33
14
34
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
35
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/translate.c
17
--- a/target/arm/translate-vfp.inc.c
37
+++ b/target/arm/translate.c
18
+++ b/target/arm/translate-vfp.inc.c
38
@@ -XXX,XX +XXX,XX @@ static inline void store_cpu_offset(TCGv_i32 var, int offset)
19
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
39
#define store_cpu_field(var, name) \
20
int pass;
40
store_cpu_offset(var, offsetof(CPUARMState, name))
21
uint32_t offset;
41
22
42
+/* The architectural value of PC. */
23
+ /* SIZE == 2 is a VFP instruction; otherwise NEON. */
43
+static uint32_t read_pc(DisasContext *s)
24
+ if (a->size == 2
44
+{
25
+ ? !dc_isar_feature(aa32_fpsp_v2, s)
45
+ return s->pc_curr + (s->thumb ? 4 : 8);
26
+ : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
46
+}
27
+ return false;
47
+
28
+ }
48
/* Set a variable to the value of a CPU register. */
29
+
49
static void load_reg_var(DisasContext *s, TCGv_i32 var, int reg)
30
/* UNDEF accesses to D16-D31 if they don't exist */
31
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
32
return false;
33
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
34
pass = extract32(offset, 2, 1);
35
offset = extract32(offset, 0, 2) * 8;
36
37
- if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) {
38
- return false;
39
- }
40
-
41
if (!vfp_access_check(s)) {
42
return true;
43
}
44
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
45
int pass;
46
uint32_t offset;
47
48
+ /* SIZE == 2 is a VFP instruction; otherwise NEON. */
49
+ if (a->size == 2
50
+ ? !dc_isar_feature(aa32_fpsp_v2, s)
51
+ : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
52
+ return false;
53
+ }
54
+
55
/* UNDEF accesses to D16-D31 if they don't exist */
56
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
57
return false;
58
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
59
pass = extract32(offset, 2, 1);
60
offset = extract32(offset, 0, 2) * 8;
61
62
- if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) {
63
- return false;
64
- }
65
-
66
if (!vfp_access_check(s)) {
67
return true;
68
}
69
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
70
TCGv_i32 tmp;
71
bool ignore_vfp_enabled = false;
72
73
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
74
+ return false;
75
+ }
76
+
77
if (arm_dc_feature(s, ARM_FEATURE_M)) {
78
/*
79
* The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
80
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
50
{
81
{
51
if (reg == 15) {
82
TCGv_i32 tmp;
52
- uint32_t addr;
83
53
- /* normally, since we updated PC, we need only to add one insn */
84
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
54
- if (s->thumb)
85
+ return false;
55
- addr = (long)s->pc + 2;
86
+ }
56
- else
87
+
57
- addr = (long)s->pc + 4;
88
if (!vfp_access_check(s)) {
58
- tcg_gen_movi_i32(var, addr);
89
return true;
59
+ tcg_gen_movi_i32(var, read_pc(s));
90
}
60
} else {
91
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a)
61
tcg_gen_mov_i32(var, cpu_R[reg]);
92
{
62
}
93
TCGv_i32 tmp;
63
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
94
64
/* branch link and change to thumb (blx <offset>) */
95
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
65
int32_t offset;
96
+ return false;
66
97
+ }
67
- val = (uint32_t)s->pc;
98
+
68
tmp = tcg_temp_new_i32();
99
/*
69
- tcg_gen_movi_i32(tmp, val);
100
* VMOV between two general-purpose registers and two single precision
70
+ tcg_gen_movi_i32(tmp, s->pc);
101
* floating point registers
71
store_reg(s, 14, tmp);
102
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a)
72
/* Sign-extend the 24-bit offset */
103
73
offset = (((int32_t)insn) << 8) >> 8;
104
/*
74
+ val = read_pc(s);
105
* VMOV between two general-purpose registers and one double precision
75
/* offset * 4 + bit24 * 2 + (thumb bit) */
106
- * floating point register
76
val += (offset << 2) | ((insn >> 23) & 2) | 1;
107
+ * floating point register. Note that this does not require support
77
- /* pipeline offset */
108
+ * for double precision arithmetic.
78
- val += 4;
109
*/
79
/* protected by ARCH(5); above, near the start of uncond block */
110
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
80
gen_bx_im(s, val);
111
+ return false;
81
return;
112
+ }
82
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
113
83
} else {
114
/* UNDEF accesses to D16-D31 if they don't exist */
84
/* store */
115
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
85
if (i == 15) {
116
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
86
- /* special case: r15 = PC + 8 */
117
uint32_t offset;
87
- val = (long)s->pc + 4;
118
TCGv_i32 addr, tmp;
88
tmp = tcg_temp_new_i32();
119
89
- tcg_gen_movi_i32(tmp, val);
120
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
90
+ tcg_gen_movi_i32(tmp, read_pc(s));
121
+ return false;
91
} else if (user) {
122
+ }
92
tmp = tcg_temp_new_i32();
123
+
93
tmp2 = tcg_const_i32(i);
124
if (!vfp_access_check(s)) {
94
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
125
return true;
95
int32_t offset;
126
}
96
127
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
97
/* branch (and link) */
128
TCGv_i32 addr;
98
- val = (int32_t)s->pc;
129
TCGv_i64 tmp;
99
if (insn & (1 << 24)) {
130
100
tmp = tcg_temp_new_i32();
131
+ /* Note that this does not require support for double arithmetic. */
101
- tcg_gen_movi_i32(tmp, val);
132
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
102
+ tcg_gen_movi_i32(tmp, s->pc);
133
+ return false;
103
store_reg(s, 14, tmp);
134
+ }
104
}
135
+
105
offset = sextract32(insn << 2, 0, 26);
136
/* UNDEF accesses to D16-D31 if they don't exist */
106
- val += offset + 4;
137
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
107
- gen_jmp(s, val);
138
return false;
108
+ gen_jmp(s, read_pc(s) + offset);
139
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
109
}
140
TCGv_i32 addr, tmp;
110
break;
141
int i, n;
111
case 0xc:
142
112
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
143
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
113
tcg_temp_free_i32(addr);
144
+ return false;
114
} else if ((insn & (7 << 5)) == 0) {
145
+ }
115
/* Table Branch. */
146
+
116
- if (rn == 15) {
147
n = a->imm;
117
- addr = tcg_temp_new_i32();
148
118
- tcg_gen_movi_i32(addr, s->pc);
149
if (n == 0 || (a->vd + n) > 32) {
119
- } else {
150
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
120
- addr = load_reg(s, rn);
151
TCGv_i64 tmp;
121
- }
152
int i, n;
122
+ addr = load_reg(s, rn);
153
123
tmp = load_reg(s, rm);
154
+ /* Note that this does not require support for double arithmetic. */
124
tcg_gen_add_i32(addr, addr, tmp);
155
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
125
if (insn & (1 << 4)) {
156
+ return false;
126
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
157
+ }
127
}
158
+
128
tcg_temp_free_i32(addr);
159
n = a->imm >> 1;
129
tcg_gen_shli_i32(tmp, tmp, 1);
160
130
- tcg_gen_addi_i32(tmp, tmp, s->pc);
161
if (n == 0 || (a->vd + n) > 32 || n > 16) {
131
+ tcg_gen_addi_i32(tmp, tmp, read_pc(s));
162
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
132
store_reg(s, 15, tmp);
163
TCGv_i32 f0, f1, fd;
133
} else {
164
TCGv_ptr fpst;
134
bool is_lasr = false;
165
135
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
166
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
136
tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
167
+ return false;
137
}
168
+ }
138
169
+
139
- offset += s->pc;
170
if (!dc_isar_feature(aa32_fpshvec, s) &&
140
+ offset += read_pc(s);
171
(veclen != 0 || s->vec_stride != 0)) {
141
if (insn & (1 << 12)) {
172
return false;
142
/* b/bl */
173
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
143
gen_jmp(s, offset);
174
int veclen = s->vec_len;
144
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
175
TCGv_i32 f0, fd;
145
offset |= (insn & (1 << 11)) << 8;
176
146
177
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
147
/* jump to the offset */
178
+ return false;
148
- gen_jmp(s, s->pc + offset);
179
+ }
149
+ gen_jmp(s, read_pc(s) + offset);
180
+
150
}
181
if (!dc_isar_feature(aa32_fpshvec, s) &&
151
} else {
182
(veclen != 0 || s->vec_stride != 0)) {
152
/*
183
return false;
153
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
184
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a)
154
if (insn & (1 << 11)) {
185
{
155
rd = (insn >> 8) & 7;
186
TCGv_i32 vd, vm;
156
/* load pc-relative. Bit 1 of PC is ignored. */
187
157
- val = s->pc + 2 + ((insn & 0xff) * 4);
188
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
158
+ val = read_pc(s) + ((insn & 0xff) * 4);
189
+ return false;
159
val &= ~(uint32_t)2;
190
+ }
160
addr = tcg_temp_new_i32();
191
+
161
tcg_gen_movi_i32(addr, val);
192
/* Vm/M bits must be zero for the Z variant */
162
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
193
if (a->z && a->vm != 0) {
163
} else {
194
return false;
164
/* PC. bit 1 is ignored. */
195
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
165
tmp = tcg_temp_new_i32();
196
TCGv_i32 vm;
166
- tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
197
TCGv_ptr fpst;
167
+ tcg_gen_movi_i32(tmp, read_pc(s) & ~(uint32_t)2);
198
168
}
199
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
169
val = (insn & 0xff) * 4;
200
+ return false;
170
tcg_gen_addi_i32(tmp, tmp, val);
201
+ }
171
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
202
+
172
tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
203
if (!vfp_access_check(s)) {
173
tcg_temp_free_i32(tmp);
204
return true;
174
offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
205
}
175
- val = (uint32_t)s->pc + 2;
206
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
176
- val += offset;
207
TCGv_i32 vm;
177
- gen_jmp(s, val);
208
TCGv_ptr fpst;
178
+ gen_jmp(s, read_pc(s) + offset);
209
179
break;
210
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
180
211
+ return false;
181
case 15: /* IT, nop-hint. */
212
+ }
182
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
213
+
183
arm_skip_unless(s, cond);
214
if (!vfp_access_check(s)) {
184
215
return true;
185
/* jump to the offset */
186
- val = (uint32_t)s->pc + 2;
187
+ val = read_pc(s);
188
offset = ((int32_t)insn << 24) >> 24;
189
val += offset << 1;
190
gen_jmp(s, val);
191
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
192
break;
193
}
194
/* unconditional branch */
195
- val = (uint32_t)s->pc;
196
+ val = read_pc(s);
197
offset = ((int32_t)insn << 21) >> 21;
198
- val += (offset << 1) + 2;
199
+ val += offset << 1;
200
gen_jmp(s, val);
201
break;
202
203
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
204
/* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */
205
uint32_t uoffset = ((int32_t)insn << 21) >> 9;
206
207
- tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + uoffset);
208
+ tcg_gen_movi_i32(cpu_R[14], read_pc(s) + uoffset);
209
}
210
break;
211
}
216
}
212
--
217
--
213
2.20.1
218
2.20.1
214
219
215
220
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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