[Qemu-devel] [PULL 0/5] target-arm queue
[PULL 00/19] target-arm queue
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Handful of bug fixes to sneak in before rc3.
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Hi; this is one last arm pullreq before the end of the year.
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Mostly minor cleanups, and also implementation of the
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FEAT_XS architectural feature.
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thanks
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thanks
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-- PMM
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-- PMM
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The following changes since commit c985266ea5b50e46e07b3568c1346e10064205c9:
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The following changes since commit 8032c78e556cd0baec111740a6c636863f9bd7c8:
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Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190726' into staging (2019-07-26 13:52:06 +0100)
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Merge tag 'firmware-20241216-pull-request' of https://gitlab.com/kraxel/qemu into staging (2024-12-16 14:20:33 -0500)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190726
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241217
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for you to fetch changes up to 67505c114e6acc26f3a1a2b74833c61b6a34ff95:
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for you to fetch changes up to e91254250acb8570bd7b8a8f89d30e6d18291d02:
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hw/arm/boot: Further improve initrd positioning code (2019-07-26 16:17:56 +0100)
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tests/functional: update sbsa-ref firmware used in test (2024-12-17 15:21:06 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* Fix broken migration on pl330 device
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* remove a line of redundant code
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* Fix broken migration on stellaris-input device
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* convert various TCG helper fns to use 'fpst' alias
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* Add type checks to vmstate varry macros to avoid this class of bugs
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* Use float_status in helper_fcvtx_f64_to_f32
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* hw/arm/boot: Fix some remaining cases where we would put the
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* Use float_status in helper_vfp_fcvt{ds,sd}
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initrd on top of the kernel image
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* Implement FEAT_XS
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* hw/intc/arm_gicv3_its: Zero initialize local DTEntry etc structs
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* tests/functional: update sbsa-ref firmware used in test
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----------------------------------------------------------------
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----------------------------------------------------------------
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Damien Hedde (1):
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Denis Rastyogin (1):
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pl330: fix vmstate description
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target/arm: remove redundant code
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34
Manos Pitsidianakis (3):
35
target/arm: Add decodetree entry for DSB nXS variant
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target/arm: Enable FEAT_XS for the max cpu
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tests/tcg/aarch64: add system test for FEAT_XS
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Marcin Juszkiewicz (1):
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tests/functional: update sbsa-ref firmware used in test
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Peter Maydell (4):
42
Peter Maydell (4):
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stellaris_input: Fix vmstate description of buttons field
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target/arm: Implement fine-grained-trap handling for FEAT_XS
32
vmstate.h: Type check VMSTATE_STRUCT_VARRAY macros
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target/arm: Add ARM_CP_ADD_TLBI_NXS type flag for NXS insns
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hw/arm/boot: Rename elf_{low, high}_addr to image_{low, high}_addr
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target/arm: Add ARM_CP_ADD_TLBI_NXS type flag to TLBI insns
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hw/arm/boot: Further improve initrd positioning code
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hw/intc/arm_gicv3_its: Zero initialize local DTEntry etc structs
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include/migration/vmstate.h | 30 ++++++++++++++++++++++++------
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Richard Henderson (10):
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hw/arm/boot.c | 37 +++++++++++++++++++++++++++----------
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target/arm: Convert vfp_helper.c to fpst alias
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hw/dma/pl330.c | 17 +++++++++--------
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target/arm: Convert helper-a64.c to fpst alias
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hw/input/stellaris_input.c | 10 ++++++----
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target/arm: Convert vec_helper.c to fpst alias
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4 files changed, 66 insertions(+), 28 deletions(-)
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target/arm: Convert neon_helper.c to fpst alias
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target/arm: Convert sve_helper.c to fpst alias
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target/arm: Convert sme_helper.c to fpst alias
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target/arm: Convert vec_helper.c to use env alias
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target/arm: Convert neon_helper.c to use env alias
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target/arm: Use float_status in helper_fcvtx_f64_to_f32
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target/arm: Use float_status in helper_vfp_fcvt{ds,sd}
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docs/system/arm/emulation.rst | 1 +
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target/arm/cpregs.h | 80 ++--
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target/arm/cpu-features.h | 5 +
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target/arm/helper.h | 638 +++++++++++++++----------------
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target/arm/tcg/helper-a64.h | 116 +++---
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target/arm/tcg/helper-sme.h | 4 +-
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target/arm/tcg/helper-sve.h | 426 ++++++++++-----------
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target/arm/tcg/a64.decode | 3 +
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hw/intc/arm_gicv3_its.c | 44 +--
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target/arm/helper.c | 30 +-
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target/arm/tcg/cpu64.c | 1 +
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target/arm/tcg/helper-a64.c | 101 ++---
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target/arm/tcg/neon_helper.c | 27 +-
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target/arm/tcg/op_helper.c | 11 +-
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target/arm/tcg/sme_helper.c | 8 +-
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target/arm/tcg/sve_helper.c | 96 ++---
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target/arm/tcg/tlb-insns.c | 202 ++++++----
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target/arm/tcg/translate-a64.c | 26 +-
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target/arm/tcg/translate-vfp.c | 4 +-
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target/arm/tcg/vec_helper.c | 81 ++--
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target/arm/vfp_helper.c | 130 +++----
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tests/tcg/aarch64/system/feat-xs.c | 27 ++
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tests/functional/test_aarch64_sbsaref.py | 20 +-
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23 files changed, 1083 insertions(+), 998 deletions(-)
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create mode 100644 tests/tcg/aarch64/system/feat-xs.c
diff view generated by jsdifflib
New patch
[PULL 01/19] target/arm: remove redundant code
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From: Denis Rastyogin <gerben@altlinux.org>
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This call is redundant as it only retrieves a value that is not used further.
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Found by Linux Verification Center (linuxtesting.org) with SVACE.
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Signed-off-by: Denis Rastyogin <gerben@altlinux.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20241212120618.518369-1-gerben@altlinux.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/vfp_helper.c | 2 --
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1 file changed, 2 deletions(-)
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diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/vfp_helper.c
18
+++ b/target/arm/vfp_helper.c
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@@ -XXX,XX +XXX,XX @@ float64 HELPER(rintd)(float64 x, void *fp_status)
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ret = float64_round_to_int(x, fp_status);
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- new_flags = get_float_exception_flags(fp_status);
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-
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/* Suppress any inexact exceptions the conversion produced */
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if (!(old_flags & float_flag_inexact)) {
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new_flags = get_float_exception_flags(fp_status);
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--
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2.34.1
diff view generated by jsdifflib
New patch
[PULL 02/19] target/arm: Convert vfp_helper.c to fpst alias
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From: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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Message-id: 20241206031224.78525-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/helper.h | 268 ++++++++++++++++++++--------------------
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target/arm/vfp_helper.c | 120 ++++++++----------
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2 files changed, 186 insertions(+), 202 deletions(-)
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diff --git a/target/arm/helper.h b/target/arm/helper.h
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/helper.h
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+++ b/target/arm/helper.h
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@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, tl, i32, i32, i32)
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DEF_HELPER_1(vfp_get_fpscr, i32, env)
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DEF_HELPER_2(vfp_set_fpscr, void, env, i32)
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-DEF_HELPER_3(vfp_addh, f16, f16, f16, ptr)
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-DEF_HELPER_3(vfp_adds, f32, f32, f32, ptr)
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-DEF_HELPER_3(vfp_addd, f64, f64, f64, ptr)
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-DEF_HELPER_3(vfp_subh, f16, f16, f16, ptr)
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-DEF_HELPER_3(vfp_subs, f32, f32, f32, ptr)
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-DEF_HELPER_3(vfp_subd, f64, f64, f64, ptr)
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-DEF_HELPER_3(vfp_mulh, f16, f16, f16, ptr)
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-DEF_HELPER_3(vfp_muls, f32, f32, f32, ptr)
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-DEF_HELPER_3(vfp_muld, f64, f64, f64, ptr)
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-DEF_HELPER_3(vfp_divh, f16, f16, f16, ptr)
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-DEF_HELPER_3(vfp_divs, f32, f32, f32, ptr)
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-DEF_HELPER_3(vfp_divd, f64, f64, f64, ptr)
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-DEF_HELPER_3(vfp_maxh, f16, f16, f16, ptr)
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-DEF_HELPER_3(vfp_maxs, f32, f32, f32, ptr)
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-DEF_HELPER_3(vfp_maxd, f64, f64, f64, ptr)
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-DEF_HELPER_3(vfp_minh, f16, f16, f16, ptr)
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-DEF_HELPER_3(vfp_mins, f32, f32, f32, ptr)
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-DEF_HELPER_3(vfp_mind, f64, f64, f64, ptr)
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-DEF_HELPER_3(vfp_maxnumh, f16, f16, f16, ptr)
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-DEF_HELPER_3(vfp_maxnums, f32, f32, f32, ptr)
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-DEF_HELPER_3(vfp_maxnumd, f64, f64, f64, ptr)
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-DEF_HELPER_3(vfp_minnumh, f16, f16, f16, ptr)
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-DEF_HELPER_3(vfp_minnums, f32, f32, f32, ptr)
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-DEF_HELPER_3(vfp_minnumd, f64, f64, f64, ptr)
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-DEF_HELPER_2(vfp_sqrth, f16, f16, ptr)
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-DEF_HELPER_2(vfp_sqrts, f32, f32, ptr)
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-DEF_HELPER_2(vfp_sqrtd, f64, f64, ptr)
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+DEF_HELPER_3(vfp_addh, f16, f16, f16, fpst)
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+DEF_HELPER_3(vfp_adds, f32, f32, f32, fpst)
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+DEF_HELPER_3(vfp_addd, f64, f64, f64, fpst)
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+DEF_HELPER_3(vfp_subh, f16, f16, f16, fpst)
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+DEF_HELPER_3(vfp_subs, f32, f32, f32, fpst)
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+DEF_HELPER_3(vfp_subd, f64, f64, f64, fpst)
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+DEF_HELPER_3(vfp_mulh, f16, f16, f16, fpst)
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+DEF_HELPER_3(vfp_muls, f32, f32, f32, fpst)
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+DEF_HELPER_3(vfp_muld, f64, f64, f64, fpst)
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+DEF_HELPER_3(vfp_divh, f16, f16, f16, fpst)
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+DEF_HELPER_3(vfp_divs, f32, f32, f32, fpst)
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+DEF_HELPER_3(vfp_divd, f64, f64, f64, fpst)
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+DEF_HELPER_3(vfp_maxh, f16, f16, f16, fpst)
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+DEF_HELPER_3(vfp_maxs, f32, f32, f32, fpst)
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+DEF_HELPER_3(vfp_maxd, f64, f64, f64, fpst)
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+DEF_HELPER_3(vfp_minh, f16, f16, f16, fpst)
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+DEF_HELPER_3(vfp_mins, f32, f32, f32, fpst)
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+DEF_HELPER_3(vfp_mind, f64, f64, f64, fpst)
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+DEF_HELPER_3(vfp_maxnumh, f16, f16, f16, fpst)
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+DEF_HELPER_3(vfp_maxnums, f32, f32, f32, fpst)
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+DEF_HELPER_3(vfp_maxnumd, f64, f64, f64, fpst)
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+DEF_HELPER_3(vfp_minnumh, f16, f16, f16, fpst)
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+DEF_HELPER_3(vfp_minnums, f32, f32, f32, fpst)
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+DEF_HELPER_3(vfp_minnumd, f64, f64, f64, fpst)
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+DEF_HELPER_2(vfp_sqrth, f16, f16, fpst)
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+DEF_HELPER_2(vfp_sqrts, f32, f32, fpst)
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+DEF_HELPER_2(vfp_sqrtd, f64, f64, fpst)
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DEF_HELPER_3(vfp_cmph, void, f16, f16, env)
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DEF_HELPER_3(vfp_cmps, void, f32, f32, env)
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DEF_HELPER_3(vfp_cmpd, void, f64, f64, env)
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@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_cmped, void, f64, f64, env)
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DEF_HELPER_2(vfp_fcvtds, f64, f32, env)
80
DEF_HELPER_2(vfp_fcvtsd, f32, f64, env)
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-DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, ptr)
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-DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, ptr)
83
+DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, fpst)
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+DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, fpst)
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-DEF_HELPER_2(vfp_uitoh, f16, i32, ptr)
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-DEF_HELPER_2(vfp_uitos, f32, i32, ptr)
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-DEF_HELPER_2(vfp_uitod, f64, i32, ptr)
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-DEF_HELPER_2(vfp_sitoh, f16, i32, ptr)
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-DEF_HELPER_2(vfp_sitos, f32, i32, ptr)
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-DEF_HELPER_2(vfp_sitod, f64, i32, ptr)
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+DEF_HELPER_2(vfp_uitoh, f16, i32, fpst)
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+DEF_HELPER_2(vfp_uitos, f32, i32, fpst)
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+DEF_HELPER_2(vfp_uitod, f64, i32, fpst)
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+DEF_HELPER_2(vfp_sitoh, f16, i32, fpst)
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+DEF_HELPER_2(vfp_sitos, f32, i32, fpst)
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+DEF_HELPER_2(vfp_sitod, f64, i32, fpst)
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-DEF_HELPER_2(vfp_touih, i32, f16, ptr)
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-DEF_HELPER_2(vfp_touis, i32, f32, ptr)
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-DEF_HELPER_2(vfp_touid, i32, f64, ptr)
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-DEF_HELPER_2(vfp_touizh, i32, f16, ptr)
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-DEF_HELPER_2(vfp_touizs, i32, f32, ptr)
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-DEF_HELPER_2(vfp_touizd, i32, f64, ptr)
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-DEF_HELPER_2(vfp_tosih, s32, f16, ptr)
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-DEF_HELPER_2(vfp_tosis, s32, f32, ptr)
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-DEF_HELPER_2(vfp_tosid, s32, f64, ptr)
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-DEF_HELPER_2(vfp_tosizh, s32, f16, ptr)
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-DEF_HELPER_2(vfp_tosizs, s32, f32, ptr)
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-DEF_HELPER_2(vfp_tosizd, s32, f64, ptr)
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+DEF_HELPER_2(vfp_touih, i32, f16, fpst)
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+DEF_HELPER_2(vfp_touis, i32, f32, fpst)
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+DEF_HELPER_2(vfp_touid, i32, f64, fpst)
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+DEF_HELPER_2(vfp_touizh, i32, f16, fpst)
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+DEF_HELPER_2(vfp_touizs, i32, f32, fpst)
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+DEF_HELPER_2(vfp_touizd, i32, f64, fpst)
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+DEF_HELPER_2(vfp_tosih, s32, f16, fpst)
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+DEF_HELPER_2(vfp_tosis, s32, f32, fpst)
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+DEF_HELPER_2(vfp_tosid, s32, f64, fpst)
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+DEF_HELPER_2(vfp_tosizh, s32, f16, fpst)
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+DEF_HELPER_2(vfp_tosizs, s32, f32, fpst)
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+DEF_HELPER_2(vfp_tosizd, s32, f64, fpst)
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-DEF_HELPER_3(vfp_toshh_round_to_zero, i32, f16, i32, ptr)
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-DEF_HELPER_3(vfp_toslh_round_to_zero, i32, f16, i32, ptr)
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-DEF_HELPER_3(vfp_touhh_round_to_zero, i32, f16, i32, ptr)
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-DEF_HELPER_3(vfp_toulh_round_to_zero, i32, f16, i32, ptr)
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-DEF_HELPER_3(vfp_toshs_round_to_zero, i32, f32, i32, ptr)
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-DEF_HELPER_3(vfp_tosls_round_to_zero, i32, f32, i32, ptr)
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-DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, ptr)
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-DEF_HELPER_3(vfp_touls_round_to_zero, i32, f32, i32, ptr)
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-DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr)
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-DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr)
134
-DEF_HELPER_3(vfp_tosqd_round_to_zero, i64, f64, i32, ptr)
135
-DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
136
-DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
137
-DEF_HELPER_3(vfp_touqd_round_to_zero, i64, f64, i32, ptr)
138
-DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr)
139
-DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr)
140
-DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
141
-DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
142
-DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr)
143
-DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr)
144
-DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
145
-DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
146
-DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
147
-DEF_HELPER_3(vfp_touhs, i32, f32, i32, ptr)
148
-DEF_HELPER_3(vfp_touls, i32, f32, i32, ptr)
149
-DEF_HELPER_3(vfp_touqs, i64, f32, i32, ptr)
150
-DEF_HELPER_3(vfp_toshd, i64, f64, i32, ptr)
151
-DEF_HELPER_3(vfp_tosld, i64, f64, i32, ptr)
152
-DEF_HELPER_3(vfp_tosqd, i64, f64, i32, ptr)
153
-DEF_HELPER_3(vfp_touhd, i64, f64, i32, ptr)
154
-DEF_HELPER_3(vfp_tould, i64, f64, i32, ptr)
155
-DEF_HELPER_3(vfp_touqd, i64, f64, i32, ptr)
156
-DEF_HELPER_3(vfp_shtos, f32, i32, i32, ptr)
157
-DEF_HELPER_3(vfp_sltos, f32, i32, i32, ptr)
158
-DEF_HELPER_3(vfp_sqtos, f32, i64, i32, ptr)
159
-DEF_HELPER_3(vfp_uhtos, f32, i32, i32, ptr)
160
-DEF_HELPER_3(vfp_ultos, f32, i32, i32, ptr)
161
-DEF_HELPER_3(vfp_uqtos, f32, i64, i32, ptr)
162
-DEF_HELPER_3(vfp_shtod, f64, i64, i32, ptr)
163
-DEF_HELPER_3(vfp_sltod, f64, i64, i32, ptr)
164
-DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr)
165
-DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr)
166
-DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
167
-DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
168
-DEF_HELPER_3(vfp_shtoh, f16, i32, i32, ptr)
169
-DEF_HELPER_3(vfp_uhtoh, f16, i32, i32, ptr)
170
-DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
171
-DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
172
-DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)
173
-DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)
174
+DEF_HELPER_3(vfp_toshh_round_to_zero, i32, f16, i32, fpst)
175
+DEF_HELPER_3(vfp_toslh_round_to_zero, i32, f16, i32, fpst)
176
+DEF_HELPER_3(vfp_touhh_round_to_zero, i32, f16, i32, fpst)
177
+DEF_HELPER_3(vfp_toulh_round_to_zero, i32, f16, i32, fpst)
178
+DEF_HELPER_3(vfp_toshs_round_to_zero, i32, f32, i32, fpst)
179
+DEF_HELPER_3(vfp_tosls_round_to_zero, i32, f32, i32, fpst)
180
+DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, fpst)
181
+DEF_HELPER_3(vfp_touls_round_to_zero, i32, f32, i32, fpst)
182
+DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, fpst)
183
+DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, fpst)
184
+DEF_HELPER_3(vfp_tosqd_round_to_zero, i64, f64, i32, fpst)
185
+DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, fpst)
186
+DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, fpst)
187
+DEF_HELPER_3(vfp_touqd_round_to_zero, i64, f64, i32, fpst)
188
+DEF_HELPER_3(vfp_touhh, i32, f16, i32, fpst)
189
+DEF_HELPER_3(vfp_toshh, i32, f16, i32, fpst)
190
+DEF_HELPER_3(vfp_toulh, i32, f16, i32, fpst)
191
+DEF_HELPER_3(vfp_toslh, i32, f16, i32, fpst)
192
+DEF_HELPER_3(vfp_touqh, i64, f16, i32, fpst)
193
+DEF_HELPER_3(vfp_tosqh, i64, f16, i32, fpst)
194
+DEF_HELPER_3(vfp_toshs, i32, f32, i32, fpst)
195
+DEF_HELPER_3(vfp_tosls, i32, f32, i32, fpst)
196
+DEF_HELPER_3(vfp_tosqs, i64, f32, i32, fpst)
197
+DEF_HELPER_3(vfp_touhs, i32, f32, i32, fpst)
198
+DEF_HELPER_3(vfp_touls, i32, f32, i32, fpst)
199
+DEF_HELPER_3(vfp_touqs, i64, f32, i32, fpst)
200
+DEF_HELPER_3(vfp_toshd, i64, f64, i32, fpst)
201
+DEF_HELPER_3(vfp_tosld, i64, f64, i32, fpst)
202
+DEF_HELPER_3(vfp_tosqd, i64, f64, i32, fpst)
203
+DEF_HELPER_3(vfp_touhd, i64, f64, i32, fpst)
204
+DEF_HELPER_3(vfp_tould, i64, f64, i32, fpst)
205
+DEF_HELPER_3(vfp_touqd, i64, f64, i32, fpst)
206
+DEF_HELPER_3(vfp_shtos, f32, i32, i32, fpst)
207
+DEF_HELPER_3(vfp_sltos, f32, i32, i32, fpst)
208
+DEF_HELPER_3(vfp_sqtos, f32, i64, i32, fpst)
209
+DEF_HELPER_3(vfp_uhtos, f32, i32, i32, fpst)
210
+DEF_HELPER_3(vfp_ultos, f32, i32, i32, fpst)
211
+DEF_HELPER_3(vfp_uqtos, f32, i64, i32, fpst)
212
+DEF_HELPER_3(vfp_shtod, f64, i64, i32, fpst)
213
+DEF_HELPER_3(vfp_sltod, f64, i64, i32, fpst)
214
+DEF_HELPER_3(vfp_sqtod, f64, i64, i32, fpst)
215
+DEF_HELPER_3(vfp_uhtod, f64, i64, i32, fpst)
216
+DEF_HELPER_3(vfp_ultod, f64, i64, i32, fpst)
217
+DEF_HELPER_3(vfp_uqtod, f64, i64, i32, fpst)
218
+DEF_HELPER_3(vfp_shtoh, f16, i32, i32, fpst)
219
+DEF_HELPER_3(vfp_uhtoh, f16, i32, i32, fpst)
220
+DEF_HELPER_3(vfp_sltoh, f16, i32, i32, fpst)
221
+DEF_HELPER_3(vfp_ultoh, f16, i32, i32, fpst)
222
+DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, fpst)
223
+DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, fpst)
224
225
-DEF_HELPER_3(vfp_shtos_round_to_nearest, f32, i32, i32, ptr)
226
-DEF_HELPER_3(vfp_sltos_round_to_nearest, f32, i32, i32, ptr)
227
-DEF_HELPER_3(vfp_uhtos_round_to_nearest, f32, i32, i32, ptr)
228
-DEF_HELPER_3(vfp_ultos_round_to_nearest, f32, i32, i32, ptr)
229
-DEF_HELPER_3(vfp_shtod_round_to_nearest, f64, i64, i32, ptr)
230
-DEF_HELPER_3(vfp_sltod_round_to_nearest, f64, i64, i32, ptr)
231
-DEF_HELPER_3(vfp_uhtod_round_to_nearest, f64, i64, i32, ptr)
232
-DEF_HELPER_3(vfp_ultod_round_to_nearest, f64, i64, i32, ptr)
233
-DEF_HELPER_3(vfp_shtoh_round_to_nearest, f16, i32, i32, ptr)
234
-DEF_HELPER_3(vfp_uhtoh_round_to_nearest, f16, i32, i32, ptr)
235
-DEF_HELPER_3(vfp_sltoh_round_to_nearest, f16, i32, i32, ptr)
236
-DEF_HELPER_3(vfp_ultoh_round_to_nearest, f16, i32, i32, ptr)
237
+DEF_HELPER_3(vfp_shtos_round_to_nearest, f32, i32, i32, fpst)
238
+DEF_HELPER_3(vfp_sltos_round_to_nearest, f32, i32, i32, fpst)
239
+DEF_HELPER_3(vfp_uhtos_round_to_nearest, f32, i32, i32, fpst)
240
+DEF_HELPER_3(vfp_ultos_round_to_nearest, f32, i32, i32, fpst)
241
+DEF_HELPER_3(vfp_shtod_round_to_nearest, f64, i64, i32, fpst)
242
+DEF_HELPER_3(vfp_sltod_round_to_nearest, f64, i64, i32, fpst)
243
+DEF_HELPER_3(vfp_uhtod_round_to_nearest, f64, i64, i32, fpst)
244
+DEF_HELPER_3(vfp_ultod_round_to_nearest, f64, i64, i32, fpst)
245
+DEF_HELPER_3(vfp_shtoh_round_to_nearest, f16, i32, i32, fpst)
246
+DEF_HELPER_3(vfp_uhtoh_round_to_nearest, f16, i32, i32, fpst)
247
+DEF_HELPER_3(vfp_sltoh_round_to_nearest, f16, i32, i32, fpst)
248
+DEF_HELPER_3(vfp_ultoh_round_to_nearest, f16, i32, i32, fpst)
249
250
-DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
251
+DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, fpst)
252
253
-DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, ptr, i32)
254
-DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, ptr, i32)
255
-DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, ptr, i32)
256
-DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, ptr, i32)
257
+DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, fpst, i32)
258
+DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, fpst, i32)
259
+DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, fpst, i32)
260
+DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, fpst, i32)
261
262
-DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, ptr)
263
-DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr)
264
-DEF_HELPER_4(vfp_muladdh, f16, f16, f16, f16, ptr)
265
+DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, fpst)
266
+DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, fpst)
267
+DEF_HELPER_4(vfp_muladdh, f16, f16, f16, f16, fpst)
268
269
-DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
270
-DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
271
-DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
272
-DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
273
-DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
274
-DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
275
+DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, fpst)
276
+DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
277
+DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, fpst)
278
+DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, fpst)
279
+DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
280
+DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, fpst)
281
DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32)
282
DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32)
283
DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64)
284
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(shr_cc, i32, env, i32, i32)
285
DEF_HELPER_3(sar_cc, i32, env, i32, i32)
286
DEF_HELPER_3(ror_cc, i32, env, i32, i32)
287
288
-DEF_HELPER_FLAGS_2(rinth_exact, TCG_CALL_NO_RWG, f16, f16, ptr)
289
-DEF_HELPER_FLAGS_2(rints_exact, TCG_CALL_NO_RWG, f32, f32, ptr)
290
-DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, ptr)
291
-DEF_HELPER_FLAGS_2(rinth, TCG_CALL_NO_RWG, f16, f16, ptr)
292
-DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, ptr)
293
-DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr)
294
+DEF_HELPER_FLAGS_2(rinth_exact, TCG_CALL_NO_RWG, f16, f16, fpst)
295
+DEF_HELPER_FLAGS_2(rints_exact, TCG_CALL_NO_RWG, f32, f32, fpst)
296
+DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, fpst)
297
+DEF_HELPER_FLAGS_2(rinth, TCG_CALL_NO_RWG, f16, f16, fpst)
298
+DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, fpst)
299
+DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, fpst)
300
301
DEF_HELPER_FLAGS_2(vjcvt, TCG_CALL_NO_RWG, i32, f64, env)
302
-DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, ptr)
303
+DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, fpst)
304
305
DEF_HELPER_FLAGS_3(check_hcr_el2_trap, TCG_CALL_NO_WG, void, env, i32, i32)
306
307
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG,
308
DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG,
309
void, ptr, ptr, ptr, ptr, i32)
310
311
-DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, ptr)
312
-DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, ptr)
313
-DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, ptr)
314
-DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, ptr)
315
+DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, fpst)
316
+DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, fpst)
317
+DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, fpst)
318
+DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, fpst)
319
320
DEF_HELPER_FLAGS_3(gvec_ceq0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
321
DEF_HELPER_FLAGS_3(gvec_ceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
322
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
323
index XXXXXXX..XXXXXXX 100644
324
--- a/target/arm/vfp_helper.c
325
+++ b/target/arm/vfp_helper.c
326
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val)
327
#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
328
329
#define VFP_BINOP(name) \
330
-dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, void *fpstp) \
331
+dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, float_status *fpst) \
332
{ \
333
- float_status *fpst = fpstp; \
334
return float16_ ## name(a, b, fpst); \
335
} \
336
-float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
337
+float32 VFP_HELPER(name, s)(float32 a, float32 b, float_status *fpst) \
338
{ \
339
- float_status *fpst = fpstp; \
340
return float32_ ## name(a, b, fpst); \
341
} \
342
-float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
343
+float64 VFP_HELPER(name, d)(float64 a, float64 b, float_status *fpst) \
344
{ \
345
- float_status *fpst = fpstp; \
346
return float64_ ## name(a, b, fpst); \
347
}
348
VFP_BINOP(add)
349
@@ -XXX,XX +XXX,XX @@ VFP_BINOP(minnum)
350
VFP_BINOP(maxnum)
351
#undef VFP_BINOP
352
353
-dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, void *fpstp)
354
+dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, float_status *fpst)
355
{
356
- return float16_sqrt(a, fpstp);
357
+ return float16_sqrt(a, fpst);
358
}
359
360
-float32 VFP_HELPER(sqrt, s)(float32 a, void *fpstp)
361
+float32 VFP_HELPER(sqrt, s)(float32 a, float_status *fpst)
362
{
363
- return float32_sqrt(a, fpstp);
364
+ return float32_sqrt(a, fpst);
365
}
366
367
-float64 VFP_HELPER(sqrt, d)(float64 a, void *fpstp)
368
+float64 VFP_HELPER(sqrt, d)(float64 a, float_status *fpst)
369
{
370
- return float64_sqrt(a, fpstp);
371
+ return float64_sqrt(a, fpst);
372
}
373
374
static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp)
375
@@ -XXX,XX +XXX,XX @@ DO_VFP_cmp(d, float64, float64, fp_status)
376
/* Integer to float and float to integer conversions */
377
378
#define CONV_ITOF(name, ftype, fsz, sign) \
379
-ftype HELPER(name)(uint32_t x, void *fpstp) \
380
+ftype HELPER(name)(uint32_t x, float_status *fpst) \
381
{ \
382
- float_status *fpst = fpstp; \
383
return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
384
}
385
386
#define CONV_FTOI(name, ftype, fsz, sign, round) \
387
-sign##int32_t HELPER(name)(ftype x, void *fpstp) \
388
+sign##int32_t HELPER(name)(ftype x, float_status *fpst) \
389
{ \
390
- float_status *fpst = fpstp; \
391
if (float##fsz##_is_any_nan(x)) { \
392
float_raise(float_flag_invalid, fpst); \
393
return 0; \
394
@@ -XXX,XX +XXX,XX @@ float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
395
return float64_to_float32(x, &env->vfp.fp_status);
396
}
397
398
-uint32_t HELPER(bfcvt)(float32 x, void *status)
399
+uint32_t HELPER(bfcvt)(float32 x, float_status *status)
400
{
401
return float32_to_bfloat16(x, status);
402
}
403
404
-uint32_t HELPER(bfcvt_pair)(uint64_t pair, void *status)
405
+uint32_t HELPER(bfcvt_pair)(uint64_t pair, float_status *status)
406
{
407
bfloat16 lo = float32_to_bfloat16(extract64(pair, 0, 32), status);
408
bfloat16 hi = float32_to_bfloat16(extract64(pair, 32, 32), status);
409
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(bfcvt_pair)(uint64_t pair, void *status)
410
*/
411
#define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
412
ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
413
- void *fpstp) \
414
-{ return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
415
+ float_status *fpst) \
416
+{ return itype##_to_##float##fsz##_scalbn(x, -shift, fpst); }
417
418
#define VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \
419
ftype HELPER(vfp_##name##to##p##_round_to_nearest)(uint##isz##_t x, \
420
uint32_t shift, \
421
- void *fpstp) \
422
+ float_status *fpst) \
423
{ \
424
ftype ret; \
425
- float_status *fpst = fpstp; \
426
FloatRoundMode oldmode = fpst->float_rounding_mode; \
427
fpst->float_rounding_mode = float_round_nearest_even; \
428
- ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); \
429
+ ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpst); \
430
fpst->float_rounding_mode = oldmode; \
431
return ret; \
432
}
433
434
#define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \
435
uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \
436
- void *fpst) \
437
+ float_status *fpst) \
438
{ \
439
if (unlikely(float##fsz##_is_any_nan(x))) { \
440
float_raise(float_flag_invalid, fpst); \
441
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FLOAT_FIX_ROUND(uq, d, 64, float64, 64, uint64,
442
/* Set the current fp rounding mode and return the old one.
443
* The argument is a softfloat float_round_ value.
444
*/
445
-uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
446
+uint32_t HELPER(set_rmode)(uint32_t rmode, float_status *fp_status)
447
{
448
- float_status *fp_status = fpstp;
449
-
450
uint32_t prev_rmode = get_float_rounding_mode(fp_status);
451
set_float_rounding_mode(rmode, fp_status);
452
453
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
454
}
455
456
/* Half precision conversions. */
457
-float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
458
+float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, float_status *fpst,
459
+ uint32_t ahp_mode)
460
{
461
/* Squash FZ16 to 0 for the duration of conversion. In this case,
462
* it would affect flushing input denormals.
463
*/
464
- float_status *fpst = fpstp;
465
bool save = get_flush_inputs_to_zero(fpst);
466
set_flush_inputs_to_zero(false, fpst);
467
float32 r = float16_to_float32(a, !ahp_mode, fpst);
468
@@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
469
return r;
470
}
471
472
-uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
473
+uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, float_status *fpst,
474
+ uint32_t ahp_mode)
475
{
476
/* Squash FZ16 to 0 for the duration of conversion. In this case,
477
* it would affect flushing output denormals.
478
*/
479
- float_status *fpst = fpstp;
480
bool save = get_flush_to_zero(fpst);
481
set_flush_to_zero(false, fpst);
482
float16 r = float32_to_float16(a, !ahp_mode, fpst);
483
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
484
return r;
485
}
486
487
-float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
488
+float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, float_status *fpst,
489
+ uint32_t ahp_mode)
490
{
491
/* Squash FZ16 to 0 for the duration of conversion. In this case,
492
* it would affect flushing input denormals.
493
*/
494
- float_status *fpst = fpstp;
495
bool save = get_flush_inputs_to_zero(fpst);
496
set_flush_inputs_to_zero(false, fpst);
497
float64 r = float16_to_float64(a, !ahp_mode, fpst);
498
@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
499
return r;
500
}
501
502
-uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
503
+uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, float_status *fpst,
504
+ uint32_t ahp_mode)
505
{
506
/* Squash FZ16 to 0 for the duration of conversion. In this case,
507
* it would affect flushing output denormals.
508
*/
509
- float_status *fpst = fpstp;
510
bool save = get_flush_to_zero(fpst);
511
set_flush_to_zero(false, fpst);
512
float16 r = float64_to_float16(a, !ahp_mode, fpst);
513
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
514
}
515
}
516
517
-uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
518
+uint32_t HELPER(recpe_f16)(uint32_t input, float_status *fpst)
519
{
520
- float_status *fpst = fpstp;
521
float16 f16 = float16_squash_input_denormal(input, fpst);
522
uint32_t f16_val = float16_val(f16);
523
uint32_t f16_sign = float16_is_neg(f16);
524
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
525
return make_float16(f16_val);
526
}
527
528
-float32 HELPER(recpe_f32)(float32 input, void *fpstp)
529
+float32 HELPER(recpe_f32)(float32 input, float_status *fpst)
530
{
531
- float_status *fpst = fpstp;
532
float32 f32 = float32_squash_input_denormal(input, fpst);
533
uint32_t f32_val = float32_val(f32);
534
bool f32_sign = float32_is_neg(f32);
535
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
536
return make_float32(f32_val);
537
}
538
539
-float64 HELPER(recpe_f64)(float64 input, void *fpstp)
540
+float64 HELPER(recpe_f64)(float64 input, float_status *fpst)
541
{
542
- float_status *fpst = fpstp;
543
float64 f64 = float64_squash_input_denormal(input, fpst);
544
uint64_t f64_val = float64_val(f64);
545
bool f64_sign = float64_is_neg(f64);
546
@@ -XXX,XX +XXX,XX @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
547
return extract64(estimate, 0, 8) << 44;
548
}
549
550
-uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
551
+uint32_t HELPER(rsqrte_f16)(uint32_t input, float_status *s)
552
{
553
- float_status *s = fpstp;
554
float16 f16 = float16_squash_input_denormal(input, s);
555
uint16_t val = float16_val(f16);
556
bool f16_sign = float16_is_neg(f16);
557
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
558
if (float16_is_signaling_nan(f16, s)) {
559
float_raise(float_flag_invalid, s);
560
if (!s->default_nan_mode) {
561
- nan = float16_silence_nan(f16, fpstp);
562
+ nan = float16_silence_nan(f16, s);
563
}
564
}
565
if (s->default_nan_mode) {
566
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
567
return make_float16(val);
568
}
569
570
-float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
571
+float32 HELPER(rsqrte_f32)(float32 input, float_status *s)
572
{
573
- float_status *s = fpstp;
574
float32 f32 = float32_squash_input_denormal(input, s);
575
uint32_t val = float32_val(f32);
576
uint32_t f32_sign = float32_is_neg(f32);
577
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
578
if (float32_is_signaling_nan(f32, s)) {
579
float_raise(float_flag_invalid, s);
580
if (!s->default_nan_mode) {
581
- nan = float32_silence_nan(f32, fpstp);
582
+ nan = float32_silence_nan(f32, s);
583
}
584
}
585
if (s->default_nan_mode) {
586
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
587
return make_float32(val);
588
}
589
590
-float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
591
+float64 HELPER(rsqrte_f64)(float64 input, float_status *s)
592
{
593
- float_status *s = fpstp;
594
float64 f64 = float64_squash_input_denormal(input, s);
595
uint64_t val = float64_val(f64);
596
bool f64_sign = float64_is_neg(f64);
597
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
598
if (float64_is_signaling_nan(f64, s)) {
599
float_raise(float_flag_invalid, s);
600
if (!s->default_nan_mode) {
601
- nan = float64_silence_nan(f64, fpstp);
602
+ nan = float64_silence_nan(f64, s);
603
}
604
}
605
if (s->default_nan_mode) {
606
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_u32)(uint32_t a)
607
608
/* VFPv4 fused multiply-accumulate */
609
dh_ctype_f16 VFP_HELPER(muladd, h)(dh_ctype_f16 a, dh_ctype_f16 b,
610
- dh_ctype_f16 c, void *fpstp)
611
+ dh_ctype_f16 c, float_status *fpst)
612
{
613
- float_status *fpst = fpstp;
614
return float16_muladd(a, b, c, 0, fpst);
615
}
616
617
-float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
618
+float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c,
619
+ float_status *fpst)
620
{
621
- float_status *fpst = fpstp;
622
return float32_muladd(a, b, c, 0, fpst);
623
}
624
625
-float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
626
+float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c,
627
+ float_status *fpst)
628
{
629
- float_status *fpst = fpstp;
630
return float64_muladd(a, b, c, 0, fpst);
631
}
632
633
/* ARMv8 round to integral */
634
-dh_ctype_f16 HELPER(rinth_exact)(dh_ctype_f16 x, void *fp_status)
635
+dh_ctype_f16 HELPER(rinth_exact)(dh_ctype_f16 x, float_status *fp_status)
636
{
637
return float16_round_to_int(x, fp_status);
638
}
639
640
-float32 HELPER(rints_exact)(float32 x, void *fp_status)
641
+float32 HELPER(rints_exact)(float32 x, float_status *fp_status)
642
{
643
return float32_round_to_int(x, fp_status);
644
}
645
646
-float64 HELPER(rintd_exact)(float64 x, void *fp_status)
647
+float64 HELPER(rintd_exact)(float64 x, float_status *fp_status)
648
{
649
return float64_round_to_int(x, fp_status);
650
}
651
652
-dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, void *fp_status)
653
+dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, float_status *fp_status)
654
{
655
int old_flags = get_float_exception_flags(fp_status), new_flags;
656
float16 ret;
657
@@ -XXX,XX +XXX,XX @@ dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, void *fp_status)
658
return ret;
659
}
660
661
-float32 HELPER(rints)(float32 x, void *fp_status)
662
+float32 HELPER(rints)(float32 x, float_status *fp_status)
663
{
664
int old_flags = get_float_exception_flags(fp_status), new_flags;
665
float32 ret;
666
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rints)(float32 x, void *fp_status)
667
return ret;
668
}
669
670
-float64 HELPER(rintd)(float64 x, void *fp_status)
671
+float64 HELPER(rintd)(float64 x, float_status *fp_status)
672
{
673
int old_flags = get_float_exception_flags(fp_status), new_flags;
674
float64 ret;
675
@@ -XXX,XX +XXX,XX @@ const FloatRoundMode arm_rmode_to_sf_map[] = {
676
* Implement float64 to int32_t conversion without saturation;
677
* the result is supplied modulo 2^32.
678
*/
679
-uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus)
680
+uint64_t HELPER(fjcvtzs)(float64 value, float_status *status)
681
{
682
- float_status *status = vstatus;
683
uint32_t frac, e_old, e_new;
684
bool inexact;
685
686
@@ -XXX,XX +XXX,XX @@ static float32 frint_s(float32 f, float_status *fpst, int intsize)
687
return (0x100u + 126u + intsize) << 23;
688
}
689
690
-float32 HELPER(frint32_s)(float32 f, void *fpst)
691
+float32 HELPER(frint32_s)(float32 f, float_status *fpst)
692
{
693
return frint_s(f, fpst, 32);
694
}
695
696
-float32 HELPER(frint64_s)(float32 f, void *fpst)
697
+float32 HELPER(frint64_s)(float32 f, float_status *fpst)
698
{
699
return frint_s(f, fpst, 64);
700
}
701
@@ -XXX,XX +XXX,XX @@ static float64 frint_d(float64 f, float_status *fpst, int intsize)
702
return (uint64_t)(0x800 + 1022 + intsize) << 52;
703
}
704
705
-float64 HELPER(frint32_d)(float64 f, void *fpst)
706
+float64 HELPER(frint32_d)(float64 f, float_status *fpst)
707
{
708
return frint_d(f, fpst, 32);
709
}
710
711
-float64 HELPER(frint64_d)(float64 f, void *fpst)
712
+float64 HELPER(frint64_d)(float64 f, float_status *fpst)
713
{
714
return frint_d(f, fpst, 64);
715
}
716
--
717
2.34.1
718
719
diff view generated by jsdifflib
New patch
[PULL 03/19] target/arm: Convert helper-a64.c to fpst alias
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Message-id: 20241206031224.78525-4-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/tcg/helper-a64.h | 94 +++++++++++++++++------------------
9
target/arm/tcg/helper-a64.c | 98 +++++++++++++------------------------
10
2 files changed, 80 insertions(+), 112 deletions(-)
11
12
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/tcg/helper-a64.h
15
+++ b/target/arm/tcg/helper-a64.h
16
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(msr_i_spsel, void, env, i32)
17
DEF_HELPER_2(msr_i_daifset, void, env, i32)
18
DEF_HELPER_2(msr_i_daifclear, void, env, i32)
19
DEF_HELPER_1(msr_set_allint_el1, void, env)
20
-DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
21
-DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
22
-DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
23
-DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
24
-DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
25
-DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, ptr)
26
+DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, fpst)
27
+DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, fpst)
28
+DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, fpst)
29
+DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, fpst)
30
+DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, fpst)
31
+DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, fpst)
32
DEF_HELPER_FLAGS_4(simd_tblx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
33
-DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
34
-DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
35
-DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
36
-DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
37
-DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
38
-DEF_HELPER_FLAGS_3(recpsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
39
-DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
40
-DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
41
-DEF_HELPER_FLAGS_3(rsqrtsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
42
-DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
43
-DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
44
-DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
45
-DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
46
-DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
47
+DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, fpst)
48
+DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, fpst)
49
+DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, fpst)
50
+DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, fpst)
51
+DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, fpst)
52
+DEF_HELPER_FLAGS_3(recpsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
53
+DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, fpst)
54
+DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, fpst)
55
+DEF_HELPER_FLAGS_3(rsqrtsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
56
+DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, fpst)
57
+DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, fpst)
58
+DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, fpst)
59
+DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
60
+DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, fpst)
61
DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env)
62
DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
63
DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
64
-DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
65
-DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
66
-DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
67
-DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
68
-DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr)
69
-DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr)
70
-DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr)
71
-DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr)
72
-DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr)
73
-DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
74
-DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
75
-DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
76
-DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
77
-DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
78
-DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr)
79
-DEF_HELPER_3(advsimd_add2h, i32, i32, i32, ptr)
80
-DEF_HELPER_3(advsimd_sub2h, i32, i32, i32, ptr)
81
-DEF_HELPER_3(advsimd_mul2h, i32, i32, i32, ptr)
82
-DEF_HELPER_3(advsimd_div2h, i32, i32, i32, ptr)
83
-DEF_HELPER_3(advsimd_max2h, i32, i32, i32, ptr)
84
-DEF_HELPER_3(advsimd_min2h, i32, i32, i32, ptr)
85
-DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr)
86
-DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr)
87
-DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
88
-DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
89
-DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
90
-DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
91
+DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
92
+DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
93
+DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
94
+DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
95
+DEF_HELPER_3(advsimd_addh, f16, f16, f16, fpst)
96
+DEF_HELPER_3(advsimd_subh, f16, f16, f16, fpst)
97
+DEF_HELPER_3(advsimd_mulh, f16, f16, f16, fpst)
98
+DEF_HELPER_3(advsimd_divh, f16, f16, f16, fpst)
99
+DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, fpst)
100
+DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, fpst)
101
+DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, fpst)
102
+DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, fpst)
103
+DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, fpst)
104
+DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, fpst)
105
+DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, fpst)
106
+DEF_HELPER_3(advsimd_add2h, i32, i32, i32, fpst)
107
+DEF_HELPER_3(advsimd_sub2h, i32, i32, i32, fpst)
108
+DEF_HELPER_3(advsimd_mul2h, i32, i32, i32, fpst)
109
+DEF_HELPER_3(advsimd_div2h, i32, i32, i32, fpst)
110
+DEF_HELPER_3(advsimd_max2h, i32, i32, i32, fpst)
111
+DEF_HELPER_3(advsimd_min2h, i32, i32, i32, fpst)
112
+DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, fpst)
113
+DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, fpst)
114
+DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, fpst)
115
+DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, fpst)
116
+DEF_HELPER_2(advsimd_rinth_exact, f16, f16, fpst)
117
+DEF_HELPER_2(advsimd_rinth, f16, f16, fpst)
118
119
DEF_HELPER_2(exception_return, void, env, i64)
120
DEF_HELPER_FLAGS_2(dc_zva, TCG_CALL_NO_WG, void, env, i64)
121
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
122
index XXXXXXX..XXXXXXX 100644
123
--- a/target/arm/tcg/helper-a64.c
124
+++ b/target/arm/tcg/helper-a64.c
125
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
126
return flags;
127
}
128
129
-uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status)
130
+uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, float_status *fp_status)
131
{
132
return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
133
}
134
135
-uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status)
136
+uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, float_status *fp_status)
137
{
138
return float_rel_to_flags(float16_compare(x, y, fp_status));
139
}
140
141
-uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
142
+uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, float_status *fp_status)
143
{
144
return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
145
}
146
147
-uint64_t HELPER(vfp_cmpes_a64)(float32 x, float32 y, void *fp_status)
148
+uint64_t HELPER(vfp_cmpes_a64)(float32 x, float32 y, float_status *fp_status)
149
{
150
return float_rel_to_flags(float32_compare(x, y, fp_status));
151
}
152
153
-uint64_t HELPER(vfp_cmpd_a64)(float64 x, float64 y, void *fp_status)
154
+uint64_t HELPER(vfp_cmpd_a64)(float64 x, float64 y, float_status *fp_status)
155
{
156
return float_rel_to_flags(float64_compare_quiet(x, y, fp_status));
157
}
158
159
-uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, void *fp_status)
160
+uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, float_status *fp_status)
161
{
162
return float_rel_to_flags(float64_compare(x, y, fp_status));
163
}
164
165
-float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp)
166
+float32 HELPER(vfp_mulxs)(float32 a, float32 b, float_status *fpst)
167
{
168
- float_status *fpst = fpstp;
169
-
170
a = float32_squash_input_denormal(a, fpst);
171
b = float32_squash_input_denormal(b, fpst);
172
173
@@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp)
174
return float32_mul(a, b, fpst);
175
}
176
177
-float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
178
+float64 HELPER(vfp_mulxd)(float64 a, float64 b, float_status *fpst)
179
{
180
- float_status *fpst = fpstp;
181
-
182
a = float64_squash_input_denormal(a, fpst);
183
b = float64_squash_input_denormal(b, fpst);
184
185
@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
186
}
187
188
/* 64bit/double versions of the neon float compare functions */
189
-uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp)
190
+uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, float_status *fpst)
191
{
192
- float_status *fpst = fpstp;
193
return -float64_eq_quiet(a, b, fpst);
194
}
195
196
-uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, void *fpstp)
197
+uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, float_status *fpst)
198
{
199
- float_status *fpst = fpstp;
200
return -float64_le(b, a, fpst);
201
}
202
203
-uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
204
+uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, float_status *fpst)
205
{
206
- float_status *fpst = fpstp;
207
return -float64_lt(b, a, fpst);
208
}
209
210
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
211
* multiply-add-and-halve.
212
*/
213
214
-uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
215
+uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, float_status *fpst)
216
{
217
- float_status *fpst = fpstp;
218
-
219
a = float16_squash_input_denormal(a, fpst);
220
b = float16_squash_input_denormal(b, fpst);
221
222
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
223
return float16_muladd(a, b, float16_two, 0, fpst);
224
}
225
226
-float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
227
+float32 HELPER(recpsf_f32)(float32 a, float32 b, float_status *fpst)
228
{
229
- float_status *fpst = fpstp;
230
-
231
a = float32_squash_input_denormal(a, fpst);
232
b = float32_squash_input_denormal(b, fpst);
233
234
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
235
return float32_muladd(a, b, float32_two, 0, fpst);
236
}
237
238
-float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
239
+float64 HELPER(recpsf_f64)(float64 a, float64 b, float_status *fpst)
240
{
241
- float_status *fpst = fpstp;
242
-
243
a = float64_squash_input_denormal(a, fpst);
244
b = float64_squash_input_denormal(b, fpst);
245
246
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
247
return float64_muladd(a, b, float64_two, 0, fpst);
248
}
249
250
-uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
251
+uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, float_status *fpst)
252
{
253
- float_status *fpst = fpstp;
254
-
255
a = float16_squash_input_denormal(a, fpst);
256
b = float16_squash_input_denormal(b, fpst);
257
258
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
259
return float16_muladd(a, b, float16_three, float_muladd_halve_result, fpst);
260
}
261
262
-float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
263
+float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, float_status *fpst)
264
{
265
- float_status *fpst = fpstp;
266
-
267
a = float32_squash_input_denormal(a, fpst);
268
b = float32_squash_input_denormal(b, fpst);
269
270
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
271
return float32_muladd(a, b, float32_three, float_muladd_halve_result, fpst);
272
}
273
274
-float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
275
+float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, float_status *fpst)
276
{
277
- float_status *fpst = fpstp;
278
-
279
a = float64_squash_input_denormal(a, fpst);
280
b = float64_squash_input_denormal(b, fpst);
281
282
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
283
}
284
285
/* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
286
-uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
287
+uint32_t HELPER(frecpx_f16)(uint32_t a, float_status *fpst)
288
{
289
- float_status *fpst = fpstp;
290
uint16_t val16, sbit;
291
int16_t exp;
292
293
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
294
}
295
}
296
297
-float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
298
+float32 HELPER(frecpx_f32)(float32 a, float_status *fpst)
299
{
300
- float_status *fpst = fpstp;
301
uint32_t val32, sbit;
302
int32_t exp;
303
304
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
305
}
306
}
307
308
-float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
309
+float64 HELPER(frecpx_f64)(float64 a, float_status *fpst)
310
{
311
- float_status *fpst = fpstp;
312
uint64_t val64, sbit;
313
int64_t exp;
314
315
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes)
316
#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
317
318
#define ADVSIMD_HALFOP(name) \
319
-uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \
320
+uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, float_status *fpst) \
321
{ \
322
- float_status *fpst = fpstp; \
323
return float16_ ## name(a, b, fpst); \
324
}
325
326
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(minnum)
327
ADVSIMD_HALFOP(maxnum)
328
329
#define ADVSIMD_TWOHALFOP(name) \
330
-uint32_t ADVSIMD_HELPER(name, 2h)(uint32_t two_a, uint32_t two_b, void *fpstp) \
331
+uint32_t ADVSIMD_HELPER(name, 2h)(uint32_t two_a, uint32_t two_b, \
332
+ float_status *fpst) \
333
{ \
334
float16 a1, a2, b1, b2; \
335
uint32_t r1, r2; \
336
- float_status *fpst = fpstp; \
337
a1 = extract32(two_a, 0, 16); \
338
a2 = extract32(two_a, 16, 16); \
339
b1 = extract32(two_b, 0, 16); \
340
@@ -XXX,XX +XXX,XX @@ ADVSIMD_TWOHALFOP(minnum)
341
ADVSIMD_TWOHALFOP(maxnum)
342
343
/* Data processing - scalar floating-point and advanced SIMD */
344
-static float16 float16_mulx(float16 a, float16 b, void *fpstp)
345
+static float16 float16_mulx(float16 a, float16 b, float_status *fpst)
346
{
347
- float_status *fpst = fpstp;
348
-
349
a = float16_squash_input_denormal(a, fpst);
350
b = float16_squash_input_denormal(b, fpst);
351
352
@@ -XXX,XX +XXX,XX @@ ADVSIMD_TWOHALFOP(mulx)
353
354
/* fused multiply-accumulate */
355
uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c,
356
- void *fpstp)
357
+ float_status *fpst)
358
{
359
- float_status *fpst = fpstp;
360
return float16_muladd(a, b, c, 0, fpst);
361
}
362
363
uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
364
- uint32_t two_c, void *fpstp)
365
+ uint32_t two_c, float_status *fpst)
366
{
367
- float_status *fpst = fpstp;
368
float16 a1, a2, b1, b2, c1, c2;
369
uint32_t r1, r2;
370
a1 = extract32(two_a, 0, 16);
371
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
372
373
#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
374
375
-uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp)
376
+uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, float_status *fpst)
377
{
378
- float_status *fpst = fpstp;
379
int compare = float16_compare_quiet(a, b, fpst);
380
return ADVSIMD_CMPRES(compare == float_relation_equal);
381
}
382
383
-uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp)
384
+uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, float_status *fpst)
385
{
386
- float_status *fpst = fpstp;
387
int compare = float16_compare(a, b, fpst);
388
return ADVSIMD_CMPRES(compare == float_relation_greater ||
389
compare == float_relation_equal);
390
}
391
392
-uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp)
393
+uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, float_status *fpst)
394
{
395
- float_status *fpst = fpstp;
396
int compare = float16_compare(a, b, fpst);
397
return ADVSIMD_CMPRES(compare == float_relation_greater);
398
}
399
400
-uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
401
+uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, float_status *fpst)
402
{
403
- float_status *fpst = fpstp;
404
float16 f0 = float16_abs(a);
405
float16 f1 = float16_abs(b);
406
int compare = float16_compare(f0, f1, fpst);
407
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
408
compare == float_relation_equal);
409
}
410
411
-uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
412
+uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, float_status *fpst)
413
{
414
- float_status *fpst = fpstp;
415
float16 f0 = float16_abs(a);
416
float16 f1 = float16_abs(b);
417
int compare = float16_compare(f0, f1, fpst);
418
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
419
}
420
421
/* round to integral */
422
-uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status)
423
+uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, float_status *fp_status)
424
{
425
return float16_round_to_int(x, fp_status);
426
}
427
428
-uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status)
429
+uint32_t HELPER(advsimd_rinth)(uint32_t x, float_status *fp_status)
430
{
431
int old_flags = get_float_exception_flags(fp_status), new_flags;
432
float16 ret;
433
--
434
2.34.1
435
436
diff view generated by jsdifflib
New patch
[PULL 04/19] target/arm: Convert vec_helper.c to fpst alias
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Message-id: 20241206031224.78525-5-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/helper.h | 284 ++++++++++++++++++------------------
9
target/arm/tcg/helper-a64.h | 18 +--
10
target/arm/tcg/helper-sve.h | 12 +-
11
target/arm/tcg/vec_helper.c | 60 ++++----
12
4 files changed, 183 insertions(+), 191 deletions(-)
13
14
diff --git a/target/arm/helper.h b/target/arm/helper.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.h
17
+++ b/target/arm/helper.h
18
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_usdot_idx_b, TCG_CALL_NO_RWG,
19
void, ptr, ptr, ptr, ptr, i32)
20
21
DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG,
22
- void, ptr, ptr, ptr, ptr, i32)
23
+ void, ptr, ptr, ptr, fpst, i32)
24
DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG,
25
- void, ptr, ptr, ptr, ptr, i32)
26
+ void, ptr, ptr, ptr, fpst, i32)
27
DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG,
28
- void, ptr, ptr, ptr, ptr, i32)
29
+ void, ptr, ptr, ptr, fpst, i32)
30
31
DEF_HELPER_FLAGS_6(gvec_fcmlah, TCG_CALL_NO_RWG,
32
- void, ptr, ptr, ptr, ptr, ptr, i32)
33
+ void, ptr, ptr, ptr, ptr, fpst, i32)
34
DEF_HELPER_FLAGS_6(gvec_fcmlah_idx, TCG_CALL_NO_RWG,
35
- void, ptr, ptr, ptr, ptr, ptr, i32)
36
+ void, ptr, ptr, ptr, ptr, fpst, i32)
37
DEF_HELPER_FLAGS_6(gvec_fcmlas, TCG_CALL_NO_RWG,
38
- void, ptr, ptr, ptr, ptr, ptr, i32)
39
+ void, ptr, ptr, ptr, ptr, fpst, i32)
40
DEF_HELPER_FLAGS_6(gvec_fcmlas_idx, TCG_CALL_NO_RWG,
41
- void, ptr, ptr, ptr, ptr, ptr, i32)
42
+ void, ptr, ptr, ptr, ptr, fpst, i32)
43
DEF_HELPER_FLAGS_6(gvec_fcmlad, TCG_CALL_NO_RWG,
44
- void, ptr, ptr, ptr, ptr, ptr, i32)
45
+ void, ptr, ptr, ptr, ptr, fpst, i32)
46
47
-DEF_HELPER_FLAGS_4(gvec_sstoh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
48
-DEF_HELPER_FLAGS_4(gvec_sitos, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
49
-DEF_HELPER_FLAGS_4(gvec_ustoh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
50
-DEF_HELPER_FLAGS_4(gvec_uitos, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
51
-DEF_HELPER_FLAGS_4(gvec_tosszh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
52
-DEF_HELPER_FLAGS_4(gvec_tosizs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
53
-DEF_HELPER_FLAGS_4(gvec_touszh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
54
-DEF_HELPER_FLAGS_4(gvec_touizs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
55
+DEF_HELPER_FLAGS_4(gvec_sstoh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
56
+DEF_HELPER_FLAGS_4(gvec_sitos, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
57
+DEF_HELPER_FLAGS_4(gvec_ustoh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
58
+DEF_HELPER_FLAGS_4(gvec_uitos, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
59
+DEF_HELPER_FLAGS_4(gvec_tosszh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
60
+DEF_HELPER_FLAGS_4(gvec_tosizs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
61
+DEF_HELPER_FLAGS_4(gvec_touszh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
62
+DEF_HELPER_FLAGS_4(gvec_touizs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
63
64
-DEF_HELPER_FLAGS_4(gvec_vcvt_sf, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
65
-DEF_HELPER_FLAGS_4(gvec_vcvt_uf, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
66
-DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
67
-DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
68
+DEF_HELPER_FLAGS_4(gvec_vcvt_sf, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
69
+DEF_HELPER_FLAGS_4(gvec_vcvt_uf, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
70
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
71
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fu, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
72
73
-DEF_HELPER_FLAGS_4(gvec_vcvt_sh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
74
-DEF_HELPER_FLAGS_4(gvec_vcvt_uh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
75
-DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
76
-DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
77
+DEF_HELPER_FLAGS_4(gvec_vcvt_sh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
78
+DEF_HELPER_FLAGS_4(gvec_vcvt_uh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
79
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
80
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hu, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
81
82
-DEF_HELPER_FLAGS_4(gvec_vcvt_sd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
83
-DEF_HELPER_FLAGS_4(gvec_vcvt_ud, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
84
-DEF_HELPER_FLAGS_4(gvec_vcvt_rz_ds, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
85
-DEF_HELPER_FLAGS_4(gvec_vcvt_rz_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
86
+DEF_HELPER_FLAGS_4(gvec_vcvt_sd, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
87
+DEF_HELPER_FLAGS_4(gvec_vcvt_ud, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
88
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_ds, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
89
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_du, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
90
91
-DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
92
-DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ud, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
93
-DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ss, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
94
-DEF_HELPER_FLAGS_4(gvec_vcvt_rm_us, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
95
-DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
96
-DEF_HELPER_FLAGS_4(gvec_vcvt_rm_uh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
97
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sd, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
98
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ud, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
99
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ss, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
100
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_us, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
101
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
102
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_uh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
103
104
-DEF_HELPER_FLAGS_4(gvec_vrint_rm_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
105
-DEF_HELPER_FLAGS_4(gvec_vrint_rm_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
106
+DEF_HELPER_FLAGS_4(gvec_vrint_rm_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
107
+DEF_HELPER_FLAGS_4(gvec_vrint_rm_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
108
109
-DEF_HELPER_FLAGS_4(gvec_vrintx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
110
-DEF_HELPER_FLAGS_4(gvec_vrintx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
111
+DEF_HELPER_FLAGS_4(gvec_vrintx_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
112
+DEF_HELPER_FLAGS_4(gvec_vrintx_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
113
114
-DEF_HELPER_FLAGS_4(gvec_frecpe_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
115
-DEF_HELPER_FLAGS_4(gvec_frecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
116
-DEF_HELPER_FLAGS_4(gvec_frecpe_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
117
+DEF_HELPER_FLAGS_4(gvec_frecpe_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
118
+DEF_HELPER_FLAGS_4(gvec_frecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
119
+DEF_HELPER_FLAGS_4(gvec_frecpe_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
120
121
-DEF_HELPER_FLAGS_4(gvec_frsqrte_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
122
-DEF_HELPER_FLAGS_4(gvec_frsqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
123
-DEF_HELPER_FLAGS_4(gvec_frsqrte_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
124
+DEF_HELPER_FLAGS_4(gvec_frsqrte_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
125
+DEF_HELPER_FLAGS_4(gvec_frsqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
126
+DEF_HELPER_FLAGS_4(gvec_frsqrte_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
127
128
-DEF_HELPER_FLAGS_4(gvec_fcgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
129
-DEF_HELPER_FLAGS_4(gvec_fcgt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
130
-DEF_HELPER_FLAGS_4(gvec_fcgt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
131
+DEF_HELPER_FLAGS_4(gvec_fcgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
132
+DEF_HELPER_FLAGS_4(gvec_fcgt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
133
+DEF_HELPER_FLAGS_4(gvec_fcgt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
134
135
-DEF_HELPER_FLAGS_4(gvec_fcge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
136
-DEF_HELPER_FLAGS_4(gvec_fcge0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
137
-DEF_HELPER_FLAGS_4(gvec_fcge0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
138
+DEF_HELPER_FLAGS_4(gvec_fcge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
139
+DEF_HELPER_FLAGS_4(gvec_fcge0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
140
+DEF_HELPER_FLAGS_4(gvec_fcge0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
141
142
-DEF_HELPER_FLAGS_4(gvec_fceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
143
-DEF_HELPER_FLAGS_4(gvec_fceq0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
144
-DEF_HELPER_FLAGS_4(gvec_fceq0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
145
+DEF_HELPER_FLAGS_4(gvec_fceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
146
+DEF_HELPER_FLAGS_4(gvec_fceq0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
147
+DEF_HELPER_FLAGS_4(gvec_fceq0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
148
149
-DEF_HELPER_FLAGS_4(gvec_fcle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
150
-DEF_HELPER_FLAGS_4(gvec_fcle0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
151
-DEF_HELPER_FLAGS_4(gvec_fcle0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
152
+DEF_HELPER_FLAGS_4(gvec_fcle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
153
+DEF_HELPER_FLAGS_4(gvec_fcle0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
154
+DEF_HELPER_FLAGS_4(gvec_fcle0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
155
156
-DEF_HELPER_FLAGS_4(gvec_fclt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
157
-DEF_HELPER_FLAGS_4(gvec_fclt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
158
-DEF_HELPER_FLAGS_4(gvec_fclt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
159
+DEF_HELPER_FLAGS_4(gvec_fclt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
160
+DEF_HELPER_FLAGS_4(gvec_fclt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
161
+DEF_HELPER_FLAGS_4(gvec_fclt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
162
163
-DEF_HELPER_FLAGS_5(gvec_fadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
164
-DEF_HELPER_FLAGS_5(gvec_fadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
165
-DEF_HELPER_FLAGS_5(gvec_fadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
166
+DEF_HELPER_FLAGS_5(gvec_fadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
167
+DEF_HELPER_FLAGS_5(gvec_fadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
168
+DEF_HELPER_FLAGS_5(gvec_fadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
169
170
-DEF_HELPER_FLAGS_5(gvec_fsub_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
171
-DEF_HELPER_FLAGS_5(gvec_fsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
172
-DEF_HELPER_FLAGS_5(gvec_fsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
173
+DEF_HELPER_FLAGS_5(gvec_fsub_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
174
+DEF_HELPER_FLAGS_5(gvec_fsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
175
+DEF_HELPER_FLAGS_5(gvec_fsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
176
177
-DEF_HELPER_FLAGS_5(gvec_fmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
178
-DEF_HELPER_FLAGS_5(gvec_fmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
179
-DEF_HELPER_FLAGS_5(gvec_fmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
180
+DEF_HELPER_FLAGS_5(gvec_fmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
181
+DEF_HELPER_FLAGS_5(gvec_fmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
182
+DEF_HELPER_FLAGS_5(gvec_fmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
183
184
-DEF_HELPER_FLAGS_5(gvec_fabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
185
-DEF_HELPER_FLAGS_5(gvec_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
186
-DEF_HELPER_FLAGS_5(gvec_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
187
+DEF_HELPER_FLAGS_5(gvec_fabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
188
+DEF_HELPER_FLAGS_5(gvec_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
189
+DEF_HELPER_FLAGS_5(gvec_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
190
191
-DEF_HELPER_FLAGS_5(gvec_fceq_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
192
-DEF_HELPER_FLAGS_5(gvec_fceq_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
193
-DEF_HELPER_FLAGS_5(gvec_fceq_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
194
+DEF_HELPER_FLAGS_5(gvec_fceq_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
195
+DEF_HELPER_FLAGS_5(gvec_fceq_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
196
+DEF_HELPER_FLAGS_5(gvec_fceq_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
197
198
-DEF_HELPER_FLAGS_5(gvec_fcge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
199
-DEF_HELPER_FLAGS_5(gvec_fcge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
200
-DEF_HELPER_FLAGS_5(gvec_fcge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
201
+DEF_HELPER_FLAGS_5(gvec_fcge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
202
+DEF_HELPER_FLAGS_5(gvec_fcge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
203
+DEF_HELPER_FLAGS_5(gvec_fcge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
204
205
-DEF_HELPER_FLAGS_5(gvec_fcgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
206
-DEF_HELPER_FLAGS_5(gvec_fcgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
207
-DEF_HELPER_FLAGS_5(gvec_fcgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
208
+DEF_HELPER_FLAGS_5(gvec_fcgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
209
+DEF_HELPER_FLAGS_5(gvec_fcgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
210
+DEF_HELPER_FLAGS_5(gvec_fcgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
211
212
-DEF_HELPER_FLAGS_5(gvec_facge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
213
-DEF_HELPER_FLAGS_5(gvec_facge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
214
-DEF_HELPER_FLAGS_5(gvec_facge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
215
+DEF_HELPER_FLAGS_5(gvec_facge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
216
+DEF_HELPER_FLAGS_5(gvec_facge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
217
+DEF_HELPER_FLAGS_5(gvec_facge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
218
219
-DEF_HELPER_FLAGS_5(gvec_facgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
220
-DEF_HELPER_FLAGS_5(gvec_facgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
221
-DEF_HELPER_FLAGS_5(gvec_facgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
222
+DEF_HELPER_FLAGS_5(gvec_facgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
223
+DEF_HELPER_FLAGS_5(gvec_facgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
224
+DEF_HELPER_FLAGS_5(gvec_facgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
225
226
-DEF_HELPER_FLAGS_5(gvec_fmax_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
227
-DEF_HELPER_FLAGS_5(gvec_fmax_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
228
-DEF_HELPER_FLAGS_5(gvec_fmax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
229
+DEF_HELPER_FLAGS_5(gvec_fmax_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
230
+DEF_HELPER_FLAGS_5(gvec_fmax_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
231
+DEF_HELPER_FLAGS_5(gvec_fmax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
232
233
-DEF_HELPER_FLAGS_5(gvec_fmin_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
234
-DEF_HELPER_FLAGS_5(gvec_fmin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
235
-DEF_HELPER_FLAGS_5(gvec_fmin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
236
+DEF_HELPER_FLAGS_5(gvec_fmin_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
237
+DEF_HELPER_FLAGS_5(gvec_fmin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
238
+DEF_HELPER_FLAGS_5(gvec_fmin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
239
240
-DEF_HELPER_FLAGS_5(gvec_fmaxnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
241
-DEF_HELPER_FLAGS_5(gvec_fmaxnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
242
-DEF_HELPER_FLAGS_5(gvec_fmaxnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
243
+DEF_HELPER_FLAGS_5(gvec_fmaxnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
244
+DEF_HELPER_FLAGS_5(gvec_fmaxnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
245
+DEF_HELPER_FLAGS_5(gvec_fmaxnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
246
247
-DEF_HELPER_FLAGS_5(gvec_fminnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
248
-DEF_HELPER_FLAGS_5(gvec_fminnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
249
-DEF_HELPER_FLAGS_5(gvec_fminnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
250
+DEF_HELPER_FLAGS_5(gvec_fminnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
251
+DEF_HELPER_FLAGS_5(gvec_fminnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
252
+DEF_HELPER_FLAGS_5(gvec_fminnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
253
254
-DEF_HELPER_FLAGS_5(gvec_recps_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
255
-DEF_HELPER_FLAGS_5(gvec_recps_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
256
+DEF_HELPER_FLAGS_5(gvec_recps_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
257
+DEF_HELPER_FLAGS_5(gvec_recps_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
258
259
-DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
260
-DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
261
+DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
262
+DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
263
264
-DEF_HELPER_FLAGS_5(gvec_fmla_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
265
-DEF_HELPER_FLAGS_5(gvec_fmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
266
+DEF_HELPER_FLAGS_5(gvec_fmla_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
267
+DEF_HELPER_FLAGS_5(gvec_fmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
268
269
-DEF_HELPER_FLAGS_5(gvec_fmls_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
270
-DEF_HELPER_FLAGS_5(gvec_fmls_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
271
+DEF_HELPER_FLAGS_5(gvec_fmls_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
272
+DEF_HELPER_FLAGS_5(gvec_fmls_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
273
274
-DEF_HELPER_FLAGS_5(gvec_vfma_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
275
-DEF_HELPER_FLAGS_5(gvec_vfma_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
276
-DEF_HELPER_FLAGS_5(gvec_vfma_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
277
+DEF_HELPER_FLAGS_5(gvec_vfma_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
278
+DEF_HELPER_FLAGS_5(gvec_vfma_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
279
+DEF_HELPER_FLAGS_5(gvec_vfma_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
280
281
-DEF_HELPER_FLAGS_5(gvec_vfms_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
282
-DEF_HELPER_FLAGS_5(gvec_vfms_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
283
-DEF_HELPER_FLAGS_5(gvec_vfms_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
284
+DEF_HELPER_FLAGS_5(gvec_vfms_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
285
+DEF_HELPER_FLAGS_5(gvec_vfms_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
286
+DEF_HELPER_FLAGS_5(gvec_vfms_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
287
288
DEF_HELPER_FLAGS_5(gvec_ftsmul_h, TCG_CALL_NO_RWG,
289
- void, ptr, ptr, ptr, ptr, i32)
290
+ void, ptr, ptr, ptr, fpst, i32)
291
DEF_HELPER_FLAGS_5(gvec_ftsmul_s, TCG_CALL_NO_RWG,
292
- void, ptr, ptr, ptr, ptr, i32)
293
+ void, ptr, ptr, ptr, fpst, i32)
294
DEF_HELPER_FLAGS_5(gvec_ftsmul_d, TCG_CALL_NO_RWG,
295
- void, ptr, ptr, ptr, ptr, i32)
296
+ void, ptr, ptr, ptr, fpst, i32)
297
298
DEF_HELPER_FLAGS_5(gvec_fmul_idx_h, TCG_CALL_NO_RWG,
299
- void, ptr, ptr, ptr, ptr, i32)
300
+ void, ptr, ptr, ptr, fpst, i32)
301
DEF_HELPER_FLAGS_5(gvec_fmul_idx_s, TCG_CALL_NO_RWG,
302
- void, ptr, ptr, ptr, ptr, i32)
303
+ void, ptr, ptr, ptr, fpst, i32)
304
DEF_HELPER_FLAGS_5(gvec_fmul_idx_d, TCG_CALL_NO_RWG,
305
- void, ptr, ptr, ptr, ptr, i32)
306
+ void, ptr, ptr, ptr, fpst, i32)
307
308
DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_h, TCG_CALL_NO_RWG,
309
- void, ptr, ptr, ptr, ptr, i32)
310
+ void, ptr, ptr, ptr, fpst, i32)
311
DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_s, TCG_CALL_NO_RWG,
312
- void, ptr, ptr, ptr, ptr, i32)
313
+ void, ptr, ptr, ptr, fpst, i32)
314
315
DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_h, TCG_CALL_NO_RWG,
316
- void, ptr, ptr, ptr, ptr, i32)
317
+ void, ptr, ptr, ptr, fpst, i32)
318
DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_s, TCG_CALL_NO_RWG,
319
- void, ptr, ptr, ptr, ptr, i32)
320
+ void, ptr, ptr, ptr, fpst, i32)
321
322
DEF_HELPER_FLAGS_6(gvec_fmla_idx_h, TCG_CALL_NO_RWG,
323
- void, ptr, ptr, ptr, ptr, ptr, i32)
324
+ void, ptr, ptr, ptr, ptr, fpst, i32)
325
DEF_HELPER_FLAGS_6(gvec_fmla_idx_s, TCG_CALL_NO_RWG,
326
- void, ptr, ptr, ptr, ptr, ptr, i32)
327
+ void, ptr, ptr, ptr, ptr, fpst, i32)
328
DEF_HELPER_FLAGS_6(gvec_fmla_idx_d, TCG_CALL_NO_RWG,
329
- void, ptr, ptr, ptr, ptr, ptr, i32)
330
+ void, ptr, ptr, ptr, ptr, fpst, i32)
331
332
DEF_HELPER_FLAGS_5(gvec_uqadd_b, TCG_CALL_NO_RWG,
333
void, ptr, ptr, ptr, ptr, i32)
334
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_6(gvec_bfmmla, TCG_CALL_NO_RWG,
335
void, ptr, ptr, ptr, ptr, env, i32)
336
337
DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG,
338
- void, ptr, ptr, ptr, ptr, ptr, i32)
339
+ void, ptr, ptr, ptr, ptr, fpst, i32)
340
DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG,
341
- void, ptr, ptr, ptr, ptr, ptr, i32)
342
+ void, ptr, ptr, ptr, ptr, fpst, i32)
343
344
DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG,
345
void, ptr, ptr, ptr, ptr, i32)
346
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG,
347
DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG,
348
void, ptr, ptr, ptr, ptr, i32)
349
350
-DEF_HELPER_FLAGS_5(gvec_faddp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
351
-DEF_HELPER_FLAGS_5(gvec_faddp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
352
-DEF_HELPER_FLAGS_5(gvec_faddp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
353
+DEF_HELPER_FLAGS_5(gvec_faddp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
354
+DEF_HELPER_FLAGS_5(gvec_faddp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
355
+DEF_HELPER_FLAGS_5(gvec_faddp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
356
357
-DEF_HELPER_FLAGS_5(gvec_fmaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
358
-DEF_HELPER_FLAGS_5(gvec_fmaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
359
-DEF_HELPER_FLAGS_5(gvec_fmaxp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
360
+DEF_HELPER_FLAGS_5(gvec_fmaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
361
+DEF_HELPER_FLAGS_5(gvec_fmaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
362
+DEF_HELPER_FLAGS_5(gvec_fmaxp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
363
364
-DEF_HELPER_FLAGS_5(gvec_fminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
365
-DEF_HELPER_FLAGS_5(gvec_fminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
366
-DEF_HELPER_FLAGS_5(gvec_fminp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
367
+DEF_HELPER_FLAGS_5(gvec_fminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
368
+DEF_HELPER_FLAGS_5(gvec_fminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
369
+DEF_HELPER_FLAGS_5(gvec_fminp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
370
371
-DEF_HELPER_FLAGS_5(gvec_fmaxnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
372
-DEF_HELPER_FLAGS_5(gvec_fmaxnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
373
-DEF_HELPER_FLAGS_5(gvec_fmaxnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
374
+DEF_HELPER_FLAGS_5(gvec_fmaxnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
375
+DEF_HELPER_FLAGS_5(gvec_fmaxnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
376
+DEF_HELPER_FLAGS_5(gvec_fmaxnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
377
378
-DEF_HELPER_FLAGS_5(gvec_fminnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
379
-DEF_HELPER_FLAGS_5(gvec_fminnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
380
-DEF_HELPER_FLAGS_5(gvec_fminnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
381
+DEF_HELPER_FLAGS_5(gvec_fminnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
382
+DEF_HELPER_FLAGS_5(gvec_fminnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
383
+DEF_HELPER_FLAGS_5(gvec_fminnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
384
385
DEF_HELPER_FLAGS_4(gvec_addp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
386
DEF_HELPER_FLAGS_4(gvec_addp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
387
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
388
index XXXXXXX..XXXXXXX 100644
389
--- a/target/arm/tcg/helper-a64.h
390
+++ b/target/arm/tcg/helper-a64.h
391
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(cpyfe, void, env, i32, i32, i32)
392
DEF_HELPER_FLAGS_1(guarded_page_check, TCG_CALL_NO_WG, void, env)
393
DEF_HELPER_FLAGS_2(guarded_page_br, TCG_CALL_NO_RWG, void, env, tl)
394
395
-DEF_HELPER_FLAGS_5(gvec_fdiv_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
396
-DEF_HELPER_FLAGS_5(gvec_fdiv_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
397
-DEF_HELPER_FLAGS_5(gvec_fdiv_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
398
+DEF_HELPER_FLAGS_5(gvec_fdiv_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
399
+DEF_HELPER_FLAGS_5(gvec_fdiv_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
400
+DEF_HELPER_FLAGS_5(gvec_fdiv_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
401
402
-DEF_HELPER_FLAGS_5(gvec_fmulx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
403
-DEF_HELPER_FLAGS_5(gvec_fmulx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
404
-DEF_HELPER_FLAGS_5(gvec_fmulx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
405
+DEF_HELPER_FLAGS_5(gvec_fmulx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
406
+DEF_HELPER_FLAGS_5(gvec_fmulx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
407
+DEF_HELPER_FLAGS_5(gvec_fmulx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
408
409
-DEF_HELPER_FLAGS_5(gvec_fmulx_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
410
-DEF_HELPER_FLAGS_5(gvec_fmulx_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
411
-DEF_HELPER_FLAGS_5(gvec_fmulx_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
412
+DEF_HELPER_FLAGS_5(gvec_fmulx_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
413
+DEF_HELPER_FLAGS_5(gvec_fmulx_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
414
+DEF_HELPER_FLAGS_5(gvec_fmulx_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
415
diff --git a/target/arm/tcg/helper-sve.h b/target/arm/tcg/helper-sve.h
416
index XXXXXXX..XXXXXXX 100644
417
--- a/target/arm/tcg/helper-sve.h
418
+++ b/target/arm/tcg/helper-sve.h
419
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_umini_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
420
DEF_HELPER_FLAGS_4(sve_umini_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
421
422
DEF_HELPER_FLAGS_5(gvec_recps_h, TCG_CALL_NO_RWG,
423
- void, ptr, ptr, ptr, ptr, i32)
424
+ void, ptr, ptr, ptr, fpst, i32)
425
DEF_HELPER_FLAGS_5(gvec_recps_s, TCG_CALL_NO_RWG,
426
- void, ptr, ptr, ptr, ptr, i32)
427
+ void, ptr, ptr, ptr, fpst, i32)
428
DEF_HELPER_FLAGS_5(gvec_recps_d, TCG_CALL_NO_RWG,
429
- void, ptr, ptr, ptr, ptr, i32)
430
+ void, ptr, ptr, ptr, fpst, i32)
431
432
DEF_HELPER_FLAGS_5(gvec_rsqrts_h, TCG_CALL_NO_RWG,
433
- void, ptr, ptr, ptr, ptr, i32)
434
+ void, ptr, ptr, ptr, fpst, i32)
435
DEF_HELPER_FLAGS_5(gvec_rsqrts_s, TCG_CALL_NO_RWG,
436
- void, ptr, ptr, ptr, ptr, i32)
437
+ void, ptr, ptr, ptr, fpst, i32)
438
DEF_HELPER_FLAGS_5(gvec_rsqrts_d, TCG_CALL_NO_RWG,
439
- void, ptr, ptr, ptr, ptr, i32)
440
+ void, ptr, ptr, ptr, fpst, i32)
441
442
DEF_HELPER_FLAGS_4(sve_faddv_h, TCG_CALL_NO_RWG,
443
i64, ptr, ptr, ptr, i32)
444
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
445
index XXXXXXX..XXXXXXX 100644
446
--- a/target/arm/tcg/vec_helper.c
447
+++ b/target/arm/tcg/vec_helper.c
448
@@ -XXX,XX +XXX,XX @@ DO_DOT_IDX(gvec_sdot_idx_h, int64_t, int16_t, int16_t, H8)
449
DO_DOT_IDX(gvec_udot_idx_h, uint64_t, uint16_t, uint16_t, H8)
450
451
void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm,
452
- void *vfpst, uint32_t desc)
453
+ float_status *fpst, uint32_t desc)
454
{
455
uintptr_t opr_sz = simd_oprsz(desc);
456
float16 *d = vd;
457
float16 *n = vn;
458
float16 *m = vm;
459
- float_status *fpst = vfpst;
460
uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
461
uint32_t neg_imag = neg_real ^ 1;
462
uintptr_t i;
463
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm,
464
}
465
466
void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm,
467
- void *vfpst, uint32_t desc)
468
+ float_status *fpst, uint32_t desc)
469
{
470
uintptr_t opr_sz = simd_oprsz(desc);
471
float32 *d = vd;
472
float32 *n = vn;
473
float32 *m = vm;
474
- float_status *fpst = vfpst;
475
uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
476
uint32_t neg_imag = neg_real ^ 1;
477
uintptr_t i;
478
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm,
479
}
480
481
void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm,
482
- void *vfpst, uint32_t desc)
483
+ float_status *fpst, uint32_t desc)
484
{
485
uintptr_t opr_sz = simd_oprsz(desc);
486
float64 *d = vd;
487
float64 *n = vn;
488
float64 *m = vm;
489
- float_status *fpst = vfpst;
490
uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1);
491
uint64_t neg_imag = neg_real ^ 1;
492
uintptr_t i;
493
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm,
494
}
495
496
void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, void *va,
497
- void *vfpst, uint32_t desc)
498
+ float_status *fpst, uint32_t desc)
499
{
500
uintptr_t opr_sz = simd_oprsz(desc);
501
float16 *d = vd, *n = vn, *m = vm, *a = va;
502
- float_status *fpst = vfpst;
503
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
504
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
505
uint32_t neg_real = flip ^ neg_imag;
506
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, void *va,
507
}
508
509
void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, void *va,
510
- void *vfpst, uint32_t desc)
511
+ float_status *fpst, uint32_t desc)
512
{
513
uintptr_t opr_sz = simd_oprsz(desc);
514
float16 *d = vd, *n = vn, *m = vm, *a = va;
515
- float_status *fpst = vfpst;
516
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
517
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
518
intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2);
519
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, void *va,
520
}
521
522
void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, void *va,
523
- void *vfpst, uint32_t desc)
524
+ float_status *fpst, uint32_t desc)
525
{
526
uintptr_t opr_sz = simd_oprsz(desc);
527
float32 *d = vd, *n = vn, *m = vm, *a = va;
528
- float_status *fpst = vfpst;
529
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
530
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
531
uint32_t neg_real = flip ^ neg_imag;
532
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, void *va,
533
}
534
535
void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, void *va,
536
- void *vfpst, uint32_t desc)
537
+ float_status *fpst, uint32_t desc)
538
{
539
uintptr_t opr_sz = simd_oprsz(desc);
540
float32 *d = vd, *n = vn, *m = vm, *a = va;
541
- float_status *fpst = vfpst;
542
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
543
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
544
intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2);
545
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, void *va,
546
}
547
548
void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, void *va,
549
- void *vfpst, uint32_t desc)
550
+ float_status *fpst, uint32_t desc)
551
{
552
uintptr_t opr_sz = simd_oprsz(desc);
553
float64 *d = vd, *n = vn, *m = vm, *a = va;
554
- float_status *fpst = vfpst;
555
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
556
uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
557
uint64_t neg_real = flip ^ neg_imag;
558
@@ -XXX,XX +XXX,XX @@ static uint64_t float64_acgt(float64 op1, float64 op2, float_status *stat)
559
return -float64_lt(float64_abs(op2), float64_abs(op1), stat);
560
}
561
562
-static int16_t vfp_tosszh(float16 x, void *fpstp)
563
+static int16_t vfp_tosszh(float16 x, float_status *fpst)
564
{
565
- float_status *fpst = fpstp;
566
if (float16_is_any_nan(x)) {
567
float_raise(float_flag_invalid, fpst);
568
return 0;
569
@@ -XXX,XX +XXX,XX @@ static int16_t vfp_tosszh(float16 x, void *fpstp)
570
return float16_to_int16_round_to_zero(x, fpst);
571
}
572
573
-static uint16_t vfp_touszh(float16 x, void *fpstp)
574
+static uint16_t vfp_touszh(float16 x, float_status *fpst)
575
{
576
- float_status *fpst = fpstp;
577
if (float16_is_any_nan(x)) {
578
float_raise(float_flag_invalid, fpst);
579
return 0;
580
@@ -XXX,XX +XXX,XX @@ static uint16_t vfp_touszh(float16 x, void *fpstp)
581
}
582
583
#define DO_2OP(NAME, FUNC, TYPE) \
584
-void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \
585
+void HELPER(NAME)(void *vd, void *vn, float_status *stat, uint32_t desc) \
586
{ \
587
intptr_t i, oprsz = simd_oprsz(desc); \
588
TYPE *d = vd, *n = vn; \
589
@@ -XXX,XX +XXX,XX @@ static float32 float32_rsqrts_nf(float32 op1, float32 op2, float_status *stat)
590
}
591
592
#define DO_3OP(NAME, FUNC, TYPE) \
593
-void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
594
+void HELPER(NAME)(void *vd, void *vn, void *vm, \
595
+ float_status *stat, uint32_t desc) \
596
{ \
597
intptr_t i, oprsz = simd_oprsz(desc); \
598
TYPE *d = vd, *n = vn, *m = vm; \
599
@@ -XXX,XX +XXX,XX @@ static float64 float64_mulsub_f(float64 dest, float64 op1, float64 op2,
600
return float64_muladd(float64_chs(op1), op2, dest, 0, stat);
601
}
602
603
-#define DO_MULADD(NAME, FUNC, TYPE) \
604
-void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
605
+#define DO_MULADD(NAME, FUNC, TYPE) \
606
+void HELPER(NAME)(void *vd, void *vn, void *vm, \
607
+ float_status *stat, uint32_t desc) \
608
{ \
609
intptr_t i, oprsz = simd_oprsz(desc); \
610
TYPE *d = vd, *n = vn, *m = vm; \
611
@@ -XXX,XX +XXX,XX @@ DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -, H8)
612
#undef DO_MLA_IDX
613
614
#define DO_FMUL_IDX(NAME, ADD, MUL, TYPE, H) \
615
-void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
616
+void HELPER(NAME)(void *vd, void *vn, void *vm, \
617
+ float_status *stat, uint32_t desc) \
618
{ \
619
intptr_t i, j, oprsz = simd_oprsz(desc); \
620
intptr_t segment = MIN(16, oprsz) / sizeof(TYPE); \
621
@@ -XXX,XX +XXX,XX @@ DO_FMUL_IDX(gvec_fmls_nf_idx_s, float32_sub, float32_mul, float32, H4)
622
623
#define DO_FMLA_IDX(NAME, TYPE, H) \
624
void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, \
625
- void *stat, uint32_t desc) \
626
+ float_status *stat, uint32_t desc) \
627
{ \
628
intptr_t i, j, oprsz = simd_oprsz(desc); \
629
intptr_t segment = MIN(16, oprsz) / sizeof(TYPE); \
630
@@ -XXX,XX +XXX,XX @@ DO_ABA(gvec_uaba_d, uint64_t)
631
#undef DO_ABA
632
633
#define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \
634
-void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
635
+void HELPER(NAME)(void *vd, void *vn, void *vm, \
636
+ float_status *stat, uint32_t desc) \
637
{ \
638
ARMVectorReg scratch; \
639
intptr_t oprsz = simd_oprsz(desc); \
640
@@ -XXX,XX +XXX,XX @@ DO_3OP_PAIR(gvec_uminp_s, MIN, uint32_t, H4)
641
#undef DO_3OP_PAIR
642
643
#define DO_VCVT_FIXED(NAME, FUNC, TYPE) \
644
- void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \
645
+ void HELPER(NAME)(void *vd, void *vn, float_status *stat, uint32_t desc) \
646
{ \
647
intptr_t i, oprsz = simd_oprsz(desc); \
648
int shift = simd_data(desc); \
649
@@ -XXX,XX +XXX,XX @@ DO_VCVT_FIXED(gvec_vcvt_rz_hu, helper_vfp_touhh_round_to_zero, uint16_t)
650
#undef DO_VCVT_FIXED
651
652
#define DO_VCVT_RMODE(NAME, FUNC, TYPE) \
653
- void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \
654
+ void HELPER(NAME)(void *vd, void *vn, float_status *fpst, uint32_t desc) \
655
{ \
656
- float_status *fpst = stat; \
657
intptr_t i, oprsz = simd_oprsz(desc); \
658
uint32_t rmode = simd_data(desc); \
659
uint32_t prev_rmode = get_float_rounding_mode(fpst); \
660
@@ -XXX,XX +XXX,XX @@ DO_VCVT_RMODE(gvec_vcvt_rm_uh, helper_vfp_touhh, uint16_t)
661
#undef DO_VCVT_RMODE
662
663
#define DO_VRINT_RMODE(NAME, FUNC, TYPE) \
664
- void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \
665
+ void HELPER(NAME)(void *vd, void *vn, float_status *fpst, uint32_t desc) \
666
{ \
667
- float_status *fpst = stat; \
668
intptr_t i, oprsz = simd_oprsz(desc); \
669
uint32_t rmode = simd_data(desc); \
670
uint32_t prev_rmode = get_float_rounding_mode(fpst); \
671
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_bfmmla)(void *vd, void *vn, void *vm, void *va,
672
}
673
674
void HELPER(gvec_bfmlal)(void *vd, void *vn, void *vm, void *va,
675
- void *stat, uint32_t desc)
676
+ float_status *stat, uint32_t desc)
677
{
678
intptr_t i, opr_sz = simd_oprsz(desc);
679
intptr_t sel = simd_data(desc);
680
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_bfmlal)(void *vd, void *vn, void *vm, void *va,
681
}
682
683
void HELPER(gvec_bfmlal_idx)(void *vd, void *vn, void *vm,
684
- void *va, void *stat, uint32_t desc)
685
+ void *va, float_status *stat, uint32_t desc)
686
{
687
intptr_t i, j, opr_sz = simd_oprsz(desc);
688
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT, 1);
689
--
690
2.34.1
691
692
diff view generated by jsdifflib
New patch
[PULL 05/19] target/arm: Convert neon_helper.c to fpst alias
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Message-id: 20241206031224.78525-6-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/helper.h | 14 +++++++-------
9
target/arm/tcg/neon_helper.c | 21 +++++++--------------
10
2 files changed, 14 insertions(+), 21 deletions(-)
11
12
diff --git a/target/arm/helper.h b/target/arm/helper.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/helper.h
15
+++ b/target/arm/helper.h
16
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(neon_qneg_s16, TCG_CALL_NO_RWG, i32, env, i32)
17
DEF_HELPER_FLAGS_2(neon_qneg_s32, TCG_CALL_NO_RWG, i32, env, i32)
18
DEF_HELPER_FLAGS_2(neon_qneg_s64, TCG_CALL_NO_RWG, i64, env, i64)
19
20
-DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, ptr)
21
-DEF_HELPER_3(neon_cge_f32, i32, i32, i32, ptr)
22
-DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, ptr)
23
-DEF_HELPER_3(neon_acge_f32, i32, i32, i32, ptr)
24
-DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, ptr)
25
-DEF_HELPER_3(neon_acge_f64, i64, i64, i64, ptr)
26
-DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, ptr)
27
+DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, fpst)
28
+DEF_HELPER_3(neon_cge_f32, i32, i32, i32, fpst)
29
+DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, fpst)
30
+DEF_HELPER_3(neon_acge_f32, i32, i32, i32, fpst)
31
+DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, fpst)
32
+DEF_HELPER_3(neon_acge_f64, i64, i64, i64, fpst)
33
+DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, fpst)
34
35
/* iwmmxt_helper.c */
36
DEF_HELPER_2(iwmmxt_maddsq, i64, i64, i64)
37
diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/tcg/neon_helper.c
40
+++ b/target/arm/tcg/neon_helper.c
41
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_qneg_s64)(CPUARMState *env, uint64_t x)
42
* Note that EQ doesn't signal InvalidOp for QNaNs but GE and GT do.
43
* Softfloat routines return 0/1, which we convert to the 0/-1 Neon requires.
44
*/
45
-uint32_t HELPER(neon_ceq_f32)(uint32_t a, uint32_t b, void *fpstp)
46
+uint32_t HELPER(neon_ceq_f32)(uint32_t a, uint32_t b, float_status *fpst)
47
{
48
- float_status *fpst = fpstp;
49
return -float32_eq_quiet(make_float32(a), make_float32(b), fpst);
50
}
51
52
-uint32_t HELPER(neon_cge_f32)(uint32_t a, uint32_t b, void *fpstp)
53
+uint32_t HELPER(neon_cge_f32)(uint32_t a, uint32_t b, float_status *fpst)
54
{
55
- float_status *fpst = fpstp;
56
return -float32_le(make_float32(b), make_float32(a), fpst);
57
}
58
59
-uint32_t HELPER(neon_cgt_f32)(uint32_t a, uint32_t b, void *fpstp)
60
+uint32_t HELPER(neon_cgt_f32)(uint32_t a, uint32_t b, float_status *fpst)
61
{
62
- float_status *fpst = fpstp;
63
return -float32_lt(make_float32(b), make_float32(a), fpst);
64
}
65
66
-uint32_t HELPER(neon_acge_f32)(uint32_t a, uint32_t b, void *fpstp)
67
+uint32_t HELPER(neon_acge_f32)(uint32_t a, uint32_t b, float_status *fpst)
68
{
69
- float_status *fpst = fpstp;
70
float32 f0 = float32_abs(make_float32(a));
71
float32 f1 = float32_abs(make_float32(b));
72
return -float32_le(f1, f0, fpst);
73
}
74
75
-uint32_t HELPER(neon_acgt_f32)(uint32_t a, uint32_t b, void *fpstp)
76
+uint32_t HELPER(neon_acgt_f32)(uint32_t a, uint32_t b, float_status *fpst)
77
{
78
- float_status *fpst = fpstp;
79
float32 f0 = float32_abs(make_float32(a));
80
float32 f1 = float32_abs(make_float32(b));
81
return -float32_lt(f1, f0, fpst);
82
}
83
84
-uint64_t HELPER(neon_acge_f64)(uint64_t a, uint64_t b, void *fpstp)
85
+uint64_t HELPER(neon_acge_f64)(uint64_t a, uint64_t b, float_status *fpst)
86
{
87
- float_status *fpst = fpstp;
88
float64 f0 = float64_abs(make_float64(a));
89
float64 f1 = float64_abs(make_float64(b));
90
return -float64_le(f1, f0, fpst);
91
}
92
93
-uint64_t HELPER(neon_acgt_f64)(uint64_t a, uint64_t b, void *fpstp)
94
+uint64_t HELPER(neon_acgt_f64)(uint64_t a, uint64_t b, float_status *fpst)
95
{
96
- float_status *fpst = fpstp;
97
float64 f0 = float64_abs(make_float64(a));
98
float64 f1 = float64_abs(make_float64(b));
99
return -float64_lt(f1, f0, fpst);
100
--
101
2.34.1
102
103
diff view generated by jsdifflib
New patch
[PULL 06/19] target/arm: Convert sve_helper.c to fpst alias
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Message-id: 20241206031224.78525-7-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/tcg/helper-sve.h | 414 ++++++++++++++++++------------------
9
target/arm/tcg/sve_helper.c | 96 +++++----
10
2 files changed, 258 insertions(+), 252 deletions(-)
11
12
diff --git a/target/arm/tcg/helper-sve.h b/target/arm/tcg/helper-sve.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/tcg/helper-sve.h
15
+++ b/target/arm/tcg/helper-sve.h
16
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_rsqrts_d, TCG_CALL_NO_RWG,
17
void, ptr, ptr, ptr, fpst, i32)
18
19
DEF_HELPER_FLAGS_4(sve_faddv_h, TCG_CALL_NO_RWG,
20
- i64, ptr, ptr, ptr, i32)
21
+ i64, ptr, ptr, fpst, i32)
22
DEF_HELPER_FLAGS_4(sve_faddv_s, TCG_CALL_NO_RWG,
23
- i64, ptr, ptr, ptr, i32)
24
+ i64, ptr, ptr, fpst, i32)
25
DEF_HELPER_FLAGS_4(sve_faddv_d, TCG_CALL_NO_RWG,
26
- i64, ptr, ptr, ptr, i32)
27
+ i64, ptr, ptr, fpst, i32)
28
29
DEF_HELPER_FLAGS_4(sve_fmaxnmv_h, TCG_CALL_NO_RWG,
30
- i64, ptr, ptr, ptr, i32)
31
+ i64, ptr, ptr, fpst, i32)
32
DEF_HELPER_FLAGS_4(sve_fmaxnmv_s, TCG_CALL_NO_RWG,
33
- i64, ptr, ptr, ptr, i32)
34
+ i64, ptr, ptr, fpst, i32)
35
DEF_HELPER_FLAGS_4(sve_fmaxnmv_d, TCG_CALL_NO_RWG,
36
- i64, ptr, ptr, ptr, i32)
37
+ i64, ptr, ptr, fpst, i32)
38
39
DEF_HELPER_FLAGS_4(sve_fminnmv_h, TCG_CALL_NO_RWG,
40
- i64, ptr, ptr, ptr, i32)
41
+ i64, ptr, ptr, fpst, i32)
42
DEF_HELPER_FLAGS_4(sve_fminnmv_s, TCG_CALL_NO_RWG,
43
- i64, ptr, ptr, ptr, i32)
44
+ i64, ptr, ptr, fpst, i32)
45
DEF_HELPER_FLAGS_4(sve_fminnmv_d, TCG_CALL_NO_RWG,
46
- i64, ptr, ptr, ptr, i32)
47
+ i64, ptr, ptr, fpst, i32)
48
49
DEF_HELPER_FLAGS_4(sve_fmaxv_h, TCG_CALL_NO_RWG,
50
- i64, ptr, ptr, ptr, i32)
51
+ i64, ptr, ptr, fpst, i32)
52
DEF_HELPER_FLAGS_4(sve_fmaxv_s, TCG_CALL_NO_RWG,
53
- i64, ptr, ptr, ptr, i32)
54
+ i64, ptr, ptr, fpst, i32)
55
DEF_HELPER_FLAGS_4(sve_fmaxv_d, TCG_CALL_NO_RWG,
56
- i64, ptr, ptr, ptr, i32)
57
+ i64, ptr, ptr, fpst, i32)
58
59
DEF_HELPER_FLAGS_4(sve_fminv_h, TCG_CALL_NO_RWG,
60
- i64, ptr, ptr, ptr, i32)
61
+ i64, ptr, ptr, fpst, i32)
62
DEF_HELPER_FLAGS_4(sve_fminv_s, TCG_CALL_NO_RWG,
63
- i64, ptr, ptr, ptr, i32)
64
+ i64, ptr, ptr, fpst, i32)
65
DEF_HELPER_FLAGS_4(sve_fminv_d, TCG_CALL_NO_RWG,
66
- i64, ptr, ptr, ptr, i32)
67
+ i64, ptr, ptr, fpst, i32)
68
69
DEF_HELPER_FLAGS_5(sve_fadda_h, TCG_CALL_NO_RWG,
70
- i64, i64, ptr, ptr, ptr, i32)
71
+ i64, i64, ptr, ptr, fpst, i32)
72
DEF_HELPER_FLAGS_5(sve_fadda_s, TCG_CALL_NO_RWG,
73
- i64, i64, ptr, ptr, ptr, i32)
74
+ i64, i64, ptr, ptr, fpst, i32)
75
DEF_HELPER_FLAGS_5(sve_fadda_d, TCG_CALL_NO_RWG,
76
- i64, i64, ptr, ptr, ptr, i32)
77
+ i64, i64, ptr, ptr, fpst, i32)
78
79
DEF_HELPER_FLAGS_5(sve_fcmge0_h, TCG_CALL_NO_RWG,
80
- void, ptr, ptr, ptr, ptr, i32)
81
+ void, ptr, ptr, ptr, fpst, i32)
82
DEF_HELPER_FLAGS_5(sve_fcmge0_s, TCG_CALL_NO_RWG,
83
- void, ptr, ptr, ptr, ptr, i32)
84
+ void, ptr, ptr, ptr, fpst, i32)
85
DEF_HELPER_FLAGS_5(sve_fcmge0_d, TCG_CALL_NO_RWG,
86
- void, ptr, ptr, ptr, ptr, i32)
87
+ void, ptr, ptr, ptr, fpst, i32)
88
89
DEF_HELPER_FLAGS_5(sve_fcmgt0_h, TCG_CALL_NO_RWG,
90
- void, ptr, ptr, ptr, ptr, i32)
91
+ void, ptr, ptr, ptr, fpst, i32)
92
DEF_HELPER_FLAGS_5(sve_fcmgt0_s, TCG_CALL_NO_RWG,
93
- void, ptr, ptr, ptr, ptr, i32)
94
+ void, ptr, ptr, ptr, fpst, i32)
95
DEF_HELPER_FLAGS_5(sve_fcmgt0_d, TCG_CALL_NO_RWG,
96
- void, ptr, ptr, ptr, ptr, i32)
97
+ void, ptr, ptr, ptr, fpst, i32)
98
99
DEF_HELPER_FLAGS_5(sve_fcmlt0_h, TCG_CALL_NO_RWG,
100
- void, ptr, ptr, ptr, ptr, i32)
101
+ void, ptr, ptr, ptr, fpst, i32)
102
DEF_HELPER_FLAGS_5(sve_fcmlt0_s, TCG_CALL_NO_RWG,
103
- void, ptr, ptr, ptr, ptr, i32)
104
+ void, ptr, ptr, ptr, fpst, i32)
105
DEF_HELPER_FLAGS_5(sve_fcmlt0_d, TCG_CALL_NO_RWG,
106
- void, ptr, ptr, ptr, ptr, i32)
107
+ void, ptr, ptr, ptr, fpst, i32)
108
109
DEF_HELPER_FLAGS_5(sve_fcmle0_h, TCG_CALL_NO_RWG,
110
- void, ptr, ptr, ptr, ptr, i32)
111
+ void, ptr, ptr, ptr, fpst, i32)
112
DEF_HELPER_FLAGS_5(sve_fcmle0_s, TCG_CALL_NO_RWG,
113
- void, ptr, ptr, ptr, ptr, i32)
114
+ void, ptr, ptr, ptr, fpst, i32)
115
DEF_HELPER_FLAGS_5(sve_fcmle0_d, TCG_CALL_NO_RWG,
116
- void, ptr, ptr, ptr, ptr, i32)
117
+ void, ptr, ptr, ptr, fpst, i32)
118
119
DEF_HELPER_FLAGS_5(sve_fcmeq0_h, TCG_CALL_NO_RWG,
120
- void, ptr, ptr, ptr, ptr, i32)
121
+ void, ptr, ptr, ptr, fpst, i32)
122
DEF_HELPER_FLAGS_5(sve_fcmeq0_s, TCG_CALL_NO_RWG,
123
- void, ptr, ptr, ptr, ptr, i32)
124
+ void, ptr, ptr, ptr, fpst, i32)
125
DEF_HELPER_FLAGS_5(sve_fcmeq0_d, TCG_CALL_NO_RWG,
126
- void, ptr, ptr, ptr, ptr, i32)
127
+ void, ptr, ptr, ptr, fpst, i32)
128
129
DEF_HELPER_FLAGS_5(sve_fcmne0_h, TCG_CALL_NO_RWG,
130
- void, ptr, ptr, ptr, ptr, i32)
131
+ void, ptr, ptr, ptr, fpst, i32)
132
DEF_HELPER_FLAGS_5(sve_fcmne0_s, TCG_CALL_NO_RWG,
133
- void, ptr, ptr, ptr, ptr, i32)
134
+ void, ptr, ptr, ptr, fpst, i32)
135
DEF_HELPER_FLAGS_5(sve_fcmne0_d, TCG_CALL_NO_RWG,
136
- void, ptr, ptr, ptr, ptr, i32)
137
+ void, ptr, ptr, ptr, fpst, i32)
138
139
DEF_HELPER_FLAGS_6(sve_fadd_h, TCG_CALL_NO_RWG,
140
- void, ptr, ptr, ptr, ptr, ptr, i32)
141
+ void, ptr, ptr, ptr, ptr, fpst, i32)
142
DEF_HELPER_FLAGS_6(sve_fadd_s, TCG_CALL_NO_RWG,
143
- void, ptr, ptr, ptr, ptr, ptr, i32)
144
+ void, ptr, ptr, ptr, ptr, fpst, i32)
145
DEF_HELPER_FLAGS_6(sve_fadd_d, TCG_CALL_NO_RWG,
146
- void, ptr, ptr, ptr, ptr, ptr, i32)
147
+ void, ptr, ptr, ptr, ptr, fpst, i32)
148
149
DEF_HELPER_FLAGS_6(sve_fsub_h, TCG_CALL_NO_RWG,
150
- void, ptr, ptr, ptr, ptr, ptr, i32)
151
+ void, ptr, ptr, ptr, ptr, fpst, i32)
152
DEF_HELPER_FLAGS_6(sve_fsub_s, TCG_CALL_NO_RWG,
153
- void, ptr, ptr, ptr, ptr, ptr, i32)
154
+ void, ptr, ptr, ptr, ptr, fpst, i32)
155
DEF_HELPER_FLAGS_6(sve_fsub_d, TCG_CALL_NO_RWG,
156
- void, ptr, ptr, ptr, ptr, ptr, i32)
157
+ void, ptr, ptr, ptr, ptr, fpst, i32)
158
159
DEF_HELPER_FLAGS_6(sve_fmul_h, TCG_CALL_NO_RWG,
160
- void, ptr, ptr, ptr, ptr, ptr, i32)
161
+ void, ptr, ptr, ptr, ptr, fpst, i32)
162
DEF_HELPER_FLAGS_6(sve_fmul_s, TCG_CALL_NO_RWG,
163
- void, ptr, ptr, ptr, ptr, ptr, i32)
164
+ void, ptr, ptr, ptr, ptr, fpst, i32)
165
DEF_HELPER_FLAGS_6(sve_fmul_d, TCG_CALL_NO_RWG,
166
- void, ptr, ptr, ptr, ptr, ptr, i32)
167
+ void, ptr, ptr, ptr, ptr, fpst, i32)
168
169
DEF_HELPER_FLAGS_6(sve_fdiv_h, TCG_CALL_NO_RWG,
170
- void, ptr, ptr, ptr, ptr, ptr, i32)
171
+ void, ptr, ptr, ptr, ptr, fpst, i32)
172
DEF_HELPER_FLAGS_6(sve_fdiv_s, TCG_CALL_NO_RWG,
173
- void, ptr, ptr, ptr, ptr, ptr, i32)
174
+ void, ptr, ptr, ptr, ptr, fpst, i32)
175
DEF_HELPER_FLAGS_6(sve_fdiv_d, TCG_CALL_NO_RWG,
176
- void, ptr, ptr, ptr, ptr, ptr, i32)
177
+ void, ptr, ptr, ptr, ptr, fpst, i32)
178
179
DEF_HELPER_FLAGS_6(sve_fmin_h, TCG_CALL_NO_RWG,
180
- void, ptr, ptr, ptr, ptr, ptr, i32)
181
+ void, ptr, ptr, ptr, ptr, fpst, i32)
182
DEF_HELPER_FLAGS_6(sve_fmin_s, TCG_CALL_NO_RWG,
183
- void, ptr, ptr, ptr, ptr, ptr, i32)
184
+ void, ptr, ptr, ptr, ptr, fpst, i32)
185
DEF_HELPER_FLAGS_6(sve_fmin_d, TCG_CALL_NO_RWG,
186
- void, ptr, ptr, ptr, ptr, ptr, i32)
187
+ void, ptr, ptr, ptr, ptr, fpst, i32)
188
189
DEF_HELPER_FLAGS_6(sve_fmax_h, TCG_CALL_NO_RWG,
190
- void, ptr, ptr, ptr, ptr, ptr, i32)
191
+ void, ptr, ptr, ptr, ptr, fpst, i32)
192
DEF_HELPER_FLAGS_6(sve_fmax_s, TCG_CALL_NO_RWG,
193
- void, ptr, ptr, ptr, ptr, ptr, i32)
194
+ void, ptr, ptr, ptr, ptr, fpst, i32)
195
DEF_HELPER_FLAGS_6(sve_fmax_d, TCG_CALL_NO_RWG,
196
- void, ptr, ptr, ptr, ptr, ptr, i32)
197
+ void, ptr, ptr, ptr, ptr, fpst, i32)
198
199
DEF_HELPER_FLAGS_6(sve_fminnum_h, TCG_CALL_NO_RWG,
200
- void, ptr, ptr, ptr, ptr, ptr, i32)
201
+ void, ptr, ptr, ptr, ptr, fpst, i32)
202
DEF_HELPER_FLAGS_6(sve_fminnum_s, TCG_CALL_NO_RWG,
203
- void, ptr, ptr, ptr, ptr, ptr, i32)
204
+ void, ptr, ptr, ptr, ptr, fpst, i32)
205
DEF_HELPER_FLAGS_6(sve_fminnum_d, TCG_CALL_NO_RWG,
206
- void, ptr, ptr, ptr, ptr, ptr, i32)
207
+ void, ptr, ptr, ptr, ptr, fpst, i32)
208
209
DEF_HELPER_FLAGS_6(sve_fmaxnum_h, TCG_CALL_NO_RWG,
210
- void, ptr, ptr, ptr, ptr, ptr, i32)
211
+ void, ptr, ptr, ptr, ptr, fpst, i32)
212
DEF_HELPER_FLAGS_6(sve_fmaxnum_s, TCG_CALL_NO_RWG,
213
- void, ptr, ptr, ptr, ptr, ptr, i32)
214
+ void, ptr, ptr, ptr, ptr, fpst, i32)
215
DEF_HELPER_FLAGS_6(sve_fmaxnum_d, TCG_CALL_NO_RWG,
216
- void, ptr, ptr, ptr, ptr, ptr, i32)
217
+ void, ptr, ptr, ptr, ptr, fpst, i32)
218
219
DEF_HELPER_FLAGS_6(sve_fabd_h, TCG_CALL_NO_RWG,
220
- void, ptr, ptr, ptr, ptr, ptr, i32)
221
+ void, ptr, ptr, ptr, ptr, fpst, i32)
222
DEF_HELPER_FLAGS_6(sve_fabd_s, TCG_CALL_NO_RWG,
223
- void, ptr, ptr, ptr, ptr, ptr, i32)
224
+ void, ptr, ptr, ptr, ptr, fpst, i32)
225
DEF_HELPER_FLAGS_6(sve_fabd_d, TCG_CALL_NO_RWG,
226
- void, ptr, ptr, ptr, ptr, ptr, i32)
227
+ void, ptr, ptr, ptr, ptr, fpst, i32)
228
229
DEF_HELPER_FLAGS_6(sve_fscalbn_h, TCG_CALL_NO_RWG,
230
- void, ptr, ptr, ptr, ptr, ptr, i32)
231
+ void, ptr, ptr, ptr, ptr, fpst, i32)
232
DEF_HELPER_FLAGS_6(sve_fscalbn_s, TCG_CALL_NO_RWG,
233
- void, ptr, ptr, ptr, ptr, ptr, i32)
234
+ void, ptr, ptr, ptr, ptr, fpst, i32)
235
DEF_HELPER_FLAGS_6(sve_fscalbn_d, TCG_CALL_NO_RWG,
236
- void, ptr, ptr, ptr, ptr, ptr, i32)
237
+ void, ptr, ptr, ptr, ptr, fpst, i32)
238
239
DEF_HELPER_FLAGS_6(sve_fmulx_h, TCG_CALL_NO_RWG,
240
- void, ptr, ptr, ptr, ptr, ptr, i32)
241
+ void, ptr, ptr, ptr, ptr, fpst, i32)
242
DEF_HELPER_FLAGS_6(sve_fmulx_s, TCG_CALL_NO_RWG,
243
- void, ptr, ptr, ptr, ptr, ptr, i32)
244
+ void, ptr, ptr, ptr, ptr, fpst, i32)
245
DEF_HELPER_FLAGS_6(sve_fmulx_d, TCG_CALL_NO_RWG,
246
- void, ptr, ptr, ptr, ptr, ptr, i32)
247
+ void, ptr, ptr, ptr, ptr, fpst, i32)
248
249
DEF_HELPER_FLAGS_6(sve_fadds_h, TCG_CALL_NO_RWG,
250
- void, ptr, ptr, ptr, i64, ptr, i32)
251
+ void, ptr, ptr, ptr, i64, fpst, i32)
252
DEF_HELPER_FLAGS_6(sve_fadds_s, TCG_CALL_NO_RWG,
253
- void, ptr, ptr, ptr, i64, ptr, i32)
254
+ void, ptr, ptr, ptr, i64, fpst, i32)
255
DEF_HELPER_FLAGS_6(sve_fadds_d, TCG_CALL_NO_RWG,
256
- void, ptr, ptr, ptr, i64, ptr, i32)
257
+ void, ptr, ptr, ptr, i64, fpst, i32)
258
259
DEF_HELPER_FLAGS_6(sve_fsubs_h, TCG_CALL_NO_RWG,
260
- void, ptr, ptr, ptr, i64, ptr, i32)
261
+ void, ptr, ptr, ptr, i64, fpst, i32)
262
DEF_HELPER_FLAGS_6(sve_fsubs_s, TCG_CALL_NO_RWG,
263
- void, ptr, ptr, ptr, i64, ptr, i32)
264
+ void, ptr, ptr, ptr, i64, fpst, i32)
265
DEF_HELPER_FLAGS_6(sve_fsubs_d, TCG_CALL_NO_RWG,
266
- void, ptr, ptr, ptr, i64, ptr, i32)
267
+ void, ptr, ptr, ptr, i64, fpst, i32)
268
269
DEF_HELPER_FLAGS_6(sve_fmuls_h, TCG_CALL_NO_RWG,
270
- void, ptr, ptr, ptr, i64, ptr, i32)
271
+ void, ptr, ptr, ptr, i64, fpst, i32)
272
DEF_HELPER_FLAGS_6(sve_fmuls_s, TCG_CALL_NO_RWG,
273
- void, ptr, ptr, ptr, i64, ptr, i32)
274
+ void, ptr, ptr, ptr, i64, fpst, i32)
275
DEF_HELPER_FLAGS_6(sve_fmuls_d, TCG_CALL_NO_RWG,
276
- void, ptr, ptr, ptr, i64, ptr, i32)
277
+ void, ptr, ptr, ptr, i64, fpst, i32)
278
279
DEF_HELPER_FLAGS_6(sve_fsubrs_h, TCG_CALL_NO_RWG,
280
- void, ptr, ptr, ptr, i64, ptr, i32)
281
+ void, ptr, ptr, ptr, i64, fpst, i32)
282
DEF_HELPER_FLAGS_6(sve_fsubrs_s, TCG_CALL_NO_RWG,
283
- void, ptr, ptr, ptr, i64, ptr, i32)
284
+ void, ptr, ptr, ptr, i64, fpst, i32)
285
DEF_HELPER_FLAGS_6(sve_fsubrs_d, TCG_CALL_NO_RWG,
286
- void, ptr, ptr, ptr, i64, ptr, i32)
287
+ void, ptr, ptr, ptr, i64, fpst, i32)
288
289
DEF_HELPER_FLAGS_6(sve_fmaxnms_h, TCG_CALL_NO_RWG,
290
- void, ptr, ptr, ptr, i64, ptr, i32)
291
+ void, ptr, ptr, ptr, i64, fpst, i32)
292
DEF_HELPER_FLAGS_6(sve_fmaxnms_s, TCG_CALL_NO_RWG,
293
- void, ptr, ptr, ptr, i64, ptr, i32)
294
+ void, ptr, ptr, ptr, i64, fpst, i32)
295
DEF_HELPER_FLAGS_6(sve_fmaxnms_d, TCG_CALL_NO_RWG,
296
- void, ptr, ptr, ptr, i64, ptr, i32)
297
+ void, ptr, ptr, ptr, i64, fpst, i32)
298
299
DEF_HELPER_FLAGS_6(sve_fminnms_h, TCG_CALL_NO_RWG,
300
- void, ptr, ptr, ptr, i64, ptr, i32)
301
+ void, ptr, ptr, ptr, i64, fpst, i32)
302
DEF_HELPER_FLAGS_6(sve_fminnms_s, TCG_CALL_NO_RWG,
303
- void, ptr, ptr, ptr, i64, ptr, i32)
304
+ void, ptr, ptr, ptr, i64, fpst, i32)
305
DEF_HELPER_FLAGS_6(sve_fminnms_d, TCG_CALL_NO_RWG,
306
- void, ptr, ptr, ptr, i64, ptr, i32)
307
+ void, ptr, ptr, ptr, i64, fpst, i32)
308
309
DEF_HELPER_FLAGS_6(sve_fmaxs_h, TCG_CALL_NO_RWG,
310
- void, ptr, ptr, ptr, i64, ptr, i32)
311
+ void, ptr, ptr, ptr, i64, fpst, i32)
312
DEF_HELPER_FLAGS_6(sve_fmaxs_s, TCG_CALL_NO_RWG,
313
- void, ptr, ptr, ptr, i64, ptr, i32)
314
+ void, ptr, ptr, ptr, i64, fpst, i32)
315
DEF_HELPER_FLAGS_6(sve_fmaxs_d, TCG_CALL_NO_RWG,
316
- void, ptr, ptr, ptr, i64, ptr, i32)
317
+ void, ptr, ptr, ptr, i64, fpst, i32)
318
319
DEF_HELPER_FLAGS_6(sve_fmins_h, TCG_CALL_NO_RWG,
320
- void, ptr, ptr, ptr, i64, ptr, i32)
321
+ void, ptr, ptr, ptr, i64, fpst, i32)
322
DEF_HELPER_FLAGS_6(sve_fmins_s, TCG_CALL_NO_RWG,
323
- void, ptr, ptr, ptr, i64, ptr, i32)
324
+ void, ptr, ptr, ptr, i64, fpst, i32)
325
DEF_HELPER_FLAGS_6(sve_fmins_d, TCG_CALL_NO_RWG,
326
- void, ptr, ptr, ptr, i64, ptr, i32)
327
+ void, ptr, ptr, ptr, i64, fpst, i32)
328
329
DEF_HELPER_FLAGS_5(sve_fcvt_sh, TCG_CALL_NO_RWG,
330
- void, ptr, ptr, ptr, ptr, i32)
331
+ void, ptr, ptr, ptr, fpst, i32)
332
DEF_HELPER_FLAGS_5(sve_fcvt_dh, TCG_CALL_NO_RWG,
333
- void, ptr, ptr, ptr, ptr, i32)
334
+ void, ptr, ptr, ptr, fpst, i32)
335
DEF_HELPER_FLAGS_5(sve_fcvt_hs, TCG_CALL_NO_RWG,
336
- void, ptr, ptr, ptr, ptr, i32)
337
+ void, ptr, ptr, ptr, fpst, i32)
338
DEF_HELPER_FLAGS_5(sve_fcvt_ds, TCG_CALL_NO_RWG,
339
- void, ptr, ptr, ptr, ptr, i32)
340
+ void, ptr, ptr, ptr, fpst, i32)
341
DEF_HELPER_FLAGS_5(sve_fcvt_hd, TCG_CALL_NO_RWG,
342
- void, ptr, ptr, ptr, ptr, i32)
343
+ void, ptr, ptr, ptr, fpst, i32)
344
DEF_HELPER_FLAGS_5(sve_fcvt_sd, TCG_CALL_NO_RWG,
345
- void, ptr, ptr, ptr, ptr, i32)
346
+ void, ptr, ptr, ptr, fpst, i32)
347
DEF_HELPER_FLAGS_5(sve_bfcvt, TCG_CALL_NO_RWG,
348
- void, ptr, ptr, ptr, ptr, i32)
349
+ void, ptr, ptr, ptr, fpst, i32)
350
351
DEF_HELPER_FLAGS_5(sve_fcvtzs_hh, TCG_CALL_NO_RWG,
352
- void, ptr, ptr, ptr, ptr, i32)
353
+ void, ptr, ptr, ptr, fpst, i32)
354
DEF_HELPER_FLAGS_5(sve_fcvtzs_hs, TCG_CALL_NO_RWG,
355
- void, ptr, ptr, ptr, ptr, i32)
356
+ void, ptr, ptr, ptr, fpst, i32)
357
DEF_HELPER_FLAGS_5(sve_fcvtzs_ss, TCG_CALL_NO_RWG,
358
- void, ptr, ptr, ptr, ptr, i32)
359
+ void, ptr, ptr, ptr, fpst, i32)
360
DEF_HELPER_FLAGS_5(sve_fcvtzs_ds, TCG_CALL_NO_RWG,
361
- void, ptr, ptr, ptr, ptr, i32)
362
+ void, ptr, ptr, ptr, fpst, i32)
363
DEF_HELPER_FLAGS_5(sve_fcvtzs_hd, TCG_CALL_NO_RWG,
364
- void, ptr, ptr, ptr, ptr, i32)
365
+ void, ptr, ptr, ptr, fpst, i32)
366
DEF_HELPER_FLAGS_5(sve_fcvtzs_sd, TCG_CALL_NO_RWG,
367
- void, ptr, ptr, ptr, ptr, i32)
368
+ void, ptr, ptr, ptr, fpst, i32)
369
DEF_HELPER_FLAGS_5(sve_fcvtzs_dd, TCG_CALL_NO_RWG,
370
- void, ptr, ptr, ptr, ptr, i32)
371
+ void, ptr, ptr, ptr, fpst, i32)
372
373
DEF_HELPER_FLAGS_5(sve_fcvtzu_hh, TCG_CALL_NO_RWG,
374
- void, ptr, ptr, ptr, ptr, i32)
375
+ void, ptr, ptr, ptr, fpst, i32)
376
DEF_HELPER_FLAGS_5(sve_fcvtzu_hs, TCG_CALL_NO_RWG,
377
- void, ptr, ptr, ptr, ptr, i32)
378
+ void, ptr, ptr, ptr, fpst, i32)
379
DEF_HELPER_FLAGS_5(sve_fcvtzu_ss, TCG_CALL_NO_RWG,
380
- void, ptr, ptr, ptr, ptr, i32)
381
+ void, ptr, ptr, ptr, fpst, i32)
382
DEF_HELPER_FLAGS_5(sve_fcvtzu_ds, TCG_CALL_NO_RWG,
383
- void, ptr, ptr, ptr, ptr, i32)
384
+ void, ptr, ptr, ptr, fpst, i32)
385
DEF_HELPER_FLAGS_5(sve_fcvtzu_hd, TCG_CALL_NO_RWG,
386
- void, ptr, ptr, ptr, ptr, i32)
387
+ void, ptr, ptr, ptr, fpst, i32)
388
DEF_HELPER_FLAGS_5(sve_fcvtzu_sd, TCG_CALL_NO_RWG,
389
- void, ptr, ptr, ptr, ptr, i32)
390
+ void, ptr, ptr, ptr, fpst, i32)
391
DEF_HELPER_FLAGS_5(sve_fcvtzu_dd, TCG_CALL_NO_RWG,
392
- void, ptr, ptr, ptr, ptr, i32)
393
+ void, ptr, ptr, ptr, fpst, i32)
394
395
DEF_HELPER_FLAGS_5(sve_frint_h, TCG_CALL_NO_RWG,
396
- void, ptr, ptr, ptr, ptr, i32)
397
+ void, ptr, ptr, ptr, fpst, i32)
398
DEF_HELPER_FLAGS_5(sve_frint_s, TCG_CALL_NO_RWG,
399
- void, ptr, ptr, ptr, ptr, i32)
400
+ void, ptr, ptr, ptr, fpst, i32)
401
DEF_HELPER_FLAGS_5(sve_frint_d, TCG_CALL_NO_RWG,
402
- void, ptr, ptr, ptr, ptr, i32)
403
+ void, ptr, ptr, ptr, fpst, i32)
404
405
DEF_HELPER_FLAGS_5(sve_frintx_h, TCG_CALL_NO_RWG,
406
- void, ptr, ptr, ptr, ptr, i32)
407
+ void, ptr, ptr, ptr, fpst, i32)
408
DEF_HELPER_FLAGS_5(sve_frintx_s, TCG_CALL_NO_RWG,
409
- void, ptr, ptr, ptr, ptr, i32)
410
+ void, ptr, ptr, ptr, fpst, i32)
411
DEF_HELPER_FLAGS_5(sve_frintx_d, TCG_CALL_NO_RWG,
412
- void, ptr, ptr, ptr, ptr, i32)
413
+ void, ptr, ptr, ptr, fpst, i32)
414
415
DEF_HELPER_FLAGS_5(sve_frecpx_h, TCG_CALL_NO_RWG,
416
- void, ptr, ptr, ptr, ptr, i32)
417
+ void, ptr, ptr, ptr, fpst, i32)
418
DEF_HELPER_FLAGS_5(sve_frecpx_s, TCG_CALL_NO_RWG,
419
- void, ptr, ptr, ptr, ptr, i32)
420
+ void, ptr, ptr, ptr, fpst, i32)
421
DEF_HELPER_FLAGS_5(sve_frecpx_d, TCG_CALL_NO_RWG,
422
- void, ptr, ptr, ptr, ptr, i32)
423
+ void, ptr, ptr, ptr, fpst, i32)
424
425
DEF_HELPER_FLAGS_5(sve_fsqrt_h, TCG_CALL_NO_RWG,
426
- void, ptr, ptr, ptr, ptr, i32)
427
+ void, ptr, ptr, ptr, fpst, i32)
428
DEF_HELPER_FLAGS_5(sve_fsqrt_s, TCG_CALL_NO_RWG,
429
- void, ptr, ptr, ptr, ptr, i32)
430
+ void, ptr, ptr, ptr, fpst, i32)
431
DEF_HELPER_FLAGS_5(sve_fsqrt_d, TCG_CALL_NO_RWG,
432
- void, ptr, ptr, ptr, ptr, i32)
433
+ void, ptr, ptr, ptr, fpst, i32)
434
435
DEF_HELPER_FLAGS_5(sve_scvt_hh, TCG_CALL_NO_RWG,
436
- void, ptr, ptr, ptr, ptr, i32)
437
+ void, ptr, ptr, ptr, fpst, i32)
438
DEF_HELPER_FLAGS_5(sve_scvt_sh, TCG_CALL_NO_RWG,
439
- void, ptr, ptr, ptr, ptr, i32)
440
+ void, ptr, ptr, ptr, fpst, i32)
441
DEF_HELPER_FLAGS_5(sve_scvt_dh, TCG_CALL_NO_RWG,
442
- void, ptr, ptr, ptr, ptr, i32)
443
+ void, ptr, ptr, ptr, fpst, i32)
444
DEF_HELPER_FLAGS_5(sve_scvt_ss, TCG_CALL_NO_RWG,
445
- void, ptr, ptr, ptr, ptr, i32)
446
+ void, ptr, ptr, ptr, fpst, i32)
447
DEF_HELPER_FLAGS_5(sve_scvt_sd, TCG_CALL_NO_RWG,
448
- void, ptr, ptr, ptr, ptr, i32)
449
+ void, ptr, ptr, ptr, fpst, i32)
450
DEF_HELPER_FLAGS_5(sve_scvt_ds, TCG_CALL_NO_RWG,
451
- void, ptr, ptr, ptr, ptr, i32)
452
+ void, ptr, ptr, ptr, fpst, i32)
453
DEF_HELPER_FLAGS_5(sve_scvt_dd, TCG_CALL_NO_RWG,
454
- void, ptr, ptr, ptr, ptr, i32)
455
+ void, ptr, ptr, ptr, fpst, i32)
456
457
DEF_HELPER_FLAGS_5(sve_ucvt_hh, TCG_CALL_NO_RWG,
458
- void, ptr, ptr, ptr, ptr, i32)
459
+ void, ptr, ptr, ptr, fpst, i32)
460
DEF_HELPER_FLAGS_5(sve_ucvt_sh, TCG_CALL_NO_RWG,
461
- void, ptr, ptr, ptr, ptr, i32)
462
+ void, ptr, ptr, ptr, fpst, i32)
463
DEF_HELPER_FLAGS_5(sve_ucvt_dh, TCG_CALL_NO_RWG,
464
- void, ptr, ptr, ptr, ptr, i32)
465
+ void, ptr, ptr, ptr, fpst, i32)
466
DEF_HELPER_FLAGS_5(sve_ucvt_ss, TCG_CALL_NO_RWG,
467
- void, ptr, ptr, ptr, ptr, i32)
468
+ void, ptr, ptr, ptr, fpst, i32)
469
DEF_HELPER_FLAGS_5(sve_ucvt_sd, TCG_CALL_NO_RWG,
470
- void, ptr, ptr, ptr, ptr, i32)
471
+ void, ptr, ptr, ptr, fpst, i32)
472
DEF_HELPER_FLAGS_5(sve_ucvt_ds, TCG_CALL_NO_RWG,
473
- void, ptr, ptr, ptr, ptr, i32)
474
+ void, ptr, ptr, ptr, fpst, i32)
475
DEF_HELPER_FLAGS_5(sve_ucvt_dd, TCG_CALL_NO_RWG,
476
- void, ptr, ptr, ptr, ptr, i32)
477
+ void, ptr, ptr, ptr, fpst, i32)
478
479
DEF_HELPER_FLAGS_6(sve_fcmge_h, TCG_CALL_NO_RWG,
480
- void, ptr, ptr, ptr, ptr, ptr, i32)
481
+ void, ptr, ptr, ptr, ptr, fpst, i32)
482
DEF_HELPER_FLAGS_6(sve_fcmge_s, TCG_CALL_NO_RWG,
483
- void, ptr, ptr, ptr, ptr, ptr, i32)
484
+ void, ptr, ptr, ptr, ptr, fpst, i32)
485
DEF_HELPER_FLAGS_6(sve_fcmge_d, TCG_CALL_NO_RWG,
486
- void, ptr, ptr, ptr, ptr, ptr, i32)
487
+ void, ptr, ptr, ptr, ptr, fpst, i32)
488
489
DEF_HELPER_FLAGS_6(sve_fcmgt_h, TCG_CALL_NO_RWG,
490
- void, ptr, ptr, ptr, ptr, ptr, i32)
491
+ void, ptr, ptr, ptr, ptr, fpst, i32)
492
DEF_HELPER_FLAGS_6(sve_fcmgt_s, TCG_CALL_NO_RWG,
493
- void, ptr, ptr, ptr, ptr, ptr, i32)
494
+ void, ptr, ptr, ptr, ptr, fpst, i32)
495
DEF_HELPER_FLAGS_6(sve_fcmgt_d, TCG_CALL_NO_RWG,
496
- void, ptr, ptr, ptr, ptr, ptr, i32)
497
+ void, ptr, ptr, ptr, ptr, fpst, i32)
498
499
DEF_HELPER_FLAGS_6(sve_fcmeq_h, TCG_CALL_NO_RWG,
500
- void, ptr, ptr, ptr, ptr, ptr, i32)
501
+ void, ptr, ptr, ptr, ptr, fpst, i32)
502
DEF_HELPER_FLAGS_6(sve_fcmeq_s, TCG_CALL_NO_RWG,
503
- void, ptr, ptr, ptr, ptr, ptr, i32)
504
+ void, ptr, ptr, ptr, ptr, fpst, i32)
505
DEF_HELPER_FLAGS_6(sve_fcmeq_d, TCG_CALL_NO_RWG,
506
- void, ptr, ptr, ptr, ptr, ptr, i32)
507
+ void, ptr, ptr, ptr, ptr, fpst, i32)
508
509
DEF_HELPER_FLAGS_6(sve_fcmne_h, TCG_CALL_NO_RWG,
510
- void, ptr, ptr, ptr, ptr, ptr, i32)
511
+ void, ptr, ptr, ptr, ptr, fpst, i32)
512
DEF_HELPER_FLAGS_6(sve_fcmne_s, TCG_CALL_NO_RWG,
513
- void, ptr, ptr, ptr, ptr, ptr, i32)
514
+ void, ptr, ptr, ptr, ptr, fpst, i32)
515
DEF_HELPER_FLAGS_6(sve_fcmne_d, TCG_CALL_NO_RWG,
516
- void, ptr, ptr, ptr, ptr, ptr, i32)
517
+ void, ptr, ptr, ptr, ptr, fpst, i32)
518
519
DEF_HELPER_FLAGS_6(sve_fcmuo_h, TCG_CALL_NO_RWG,
520
- void, ptr, ptr, ptr, ptr, ptr, i32)
521
+ void, ptr, ptr, ptr, ptr, fpst, i32)
522
DEF_HELPER_FLAGS_6(sve_fcmuo_s, TCG_CALL_NO_RWG,
523
- void, ptr, ptr, ptr, ptr, ptr, i32)
524
+ void, ptr, ptr, ptr, ptr, fpst, i32)
525
DEF_HELPER_FLAGS_6(sve_fcmuo_d, TCG_CALL_NO_RWG,
526
- void, ptr, ptr, ptr, ptr, ptr, i32)
527
+ void, ptr, ptr, ptr, ptr, fpst, i32)
528
529
DEF_HELPER_FLAGS_6(sve_facge_h, TCG_CALL_NO_RWG,
530
- void, ptr, ptr, ptr, ptr, ptr, i32)
531
+ void, ptr, ptr, ptr, ptr, fpst, i32)
532
DEF_HELPER_FLAGS_6(sve_facge_s, TCG_CALL_NO_RWG,
533
- void, ptr, ptr, ptr, ptr, ptr, i32)
534
+ void, ptr, ptr, ptr, ptr, fpst, i32)
535
DEF_HELPER_FLAGS_6(sve_facge_d, TCG_CALL_NO_RWG,
536
- void, ptr, ptr, ptr, ptr, ptr, i32)
537
+ void, ptr, ptr, ptr, ptr, fpst, i32)
538
539
DEF_HELPER_FLAGS_6(sve_facgt_h, TCG_CALL_NO_RWG,
540
- void, ptr, ptr, ptr, ptr, ptr, i32)
541
+ void, ptr, ptr, ptr, ptr, fpst, i32)
542
DEF_HELPER_FLAGS_6(sve_facgt_s, TCG_CALL_NO_RWG,
543
- void, ptr, ptr, ptr, ptr, ptr, i32)
544
+ void, ptr, ptr, ptr, ptr, fpst, i32)
545
DEF_HELPER_FLAGS_6(sve_facgt_d, TCG_CALL_NO_RWG,
546
- void, ptr, ptr, ptr, ptr, ptr, i32)
547
+ void, ptr, ptr, ptr, ptr, fpst, i32)
548
549
DEF_HELPER_FLAGS_6(sve_fcadd_h, TCG_CALL_NO_RWG,
550
- void, ptr, ptr, ptr, ptr, ptr, i32)
551
+ void, ptr, ptr, ptr, ptr, fpst, i32)
552
DEF_HELPER_FLAGS_6(sve_fcadd_s, TCG_CALL_NO_RWG,
553
- void, ptr, ptr, ptr, ptr, ptr, i32)
554
+ void, ptr, ptr, ptr, ptr, fpst, i32)
555
DEF_HELPER_FLAGS_6(sve_fcadd_d, TCG_CALL_NO_RWG,
556
- void, ptr, ptr, ptr, ptr, ptr, i32)
557
+ void, ptr, ptr, ptr, ptr, fpst, i32)
558
559
DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG,
560
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
561
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
562
DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG,
563
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
564
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
565
DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG,
566
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
567
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
568
569
DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG,
570
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
571
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
572
DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG,
573
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
574
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
575
DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG,
576
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
577
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
578
579
DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG,
580
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
581
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
582
DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG,
583
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
584
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
585
DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG,
586
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
587
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
588
589
DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG,
590
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
591
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
592
DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG,
593
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
594
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
595
DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG,
596
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
597
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
598
599
DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG,
600
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
601
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
602
DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG,
603
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
604
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
605
DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG,
606
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
607
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
608
609
-DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
610
-DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
611
-DEF_HELPER_FLAGS_5(sve_ftmad_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
612
+DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
613
+DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
614
+DEF_HELPER_FLAGS_5(sve_ftmad_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
615
616
DEF_HELPER_FLAGS_4(sve2_saddl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
617
DEF_HELPER_FLAGS_4(sve2_saddl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
618
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve2_xar_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
619
DEF_HELPER_FLAGS_4(sve2_xar_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
620
621
DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_h, TCG_CALL_NO_RWG,
622
- void, ptr, ptr, ptr, ptr, ptr, i32)
623
+ void, ptr, ptr, ptr, ptr, fpst, i32)
624
DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_s, TCG_CALL_NO_RWG,
625
- void, ptr, ptr, ptr, ptr, ptr, i32)
626
+ void, ptr, ptr, ptr, ptr, fpst, i32)
627
DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_d, TCG_CALL_NO_RWG,
628
- void, ptr, ptr, ptr, ptr, ptr, i32)
629
+ void, ptr, ptr, ptr, ptr, fpst, i32)
630
631
DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_h, TCG_CALL_NO_RWG,
632
- void, ptr, ptr, ptr, ptr, ptr, i32)
633
+ void, ptr, ptr, ptr, ptr, fpst, i32)
634
DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_s, TCG_CALL_NO_RWG,
635
- void, ptr, ptr, ptr, ptr, ptr, i32)
636
+ void, ptr, ptr, ptr, ptr, fpst, i32)
637
DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_d, TCG_CALL_NO_RWG,
638
- void, ptr, ptr, ptr, ptr, ptr, i32)
639
+ void, ptr, ptr, ptr, ptr, fpst, i32)
640
641
DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_h, TCG_CALL_NO_RWG,
642
- void, ptr, ptr, ptr, ptr, ptr, i32)
643
+ void, ptr, ptr, ptr, ptr, fpst, i32)
644
DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_s, TCG_CALL_NO_RWG,
645
- void, ptr, ptr, ptr, ptr, ptr, i32)
646
+ void, ptr, ptr, ptr, ptr, fpst, i32)
647
DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_d, TCG_CALL_NO_RWG,
648
- void, ptr, ptr, ptr, ptr, ptr, i32)
649
+ void, ptr, ptr, ptr, ptr, fpst, i32)
650
651
DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_h, TCG_CALL_NO_RWG,
652
- void, ptr, ptr, ptr, ptr, ptr, i32)
653
+ void, ptr, ptr, ptr, ptr, fpst, i32)
654
DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_s, TCG_CALL_NO_RWG,
655
- void, ptr, ptr, ptr, ptr, ptr, i32)
656
+ void, ptr, ptr, ptr, ptr, fpst, i32)
657
DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_d, TCG_CALL_NO_RWG,
658
- void, ptr, ptr, ptr, ptr, ptr, i32)
659
+ void, ptr, ptr, ptr, ptr, fpst, i32)
660
661
DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_h, TCG_CALL_NO_RWG,
662
- void, ptr, ptr, ptr, ptr, ptr, i32)
663
+ void, ptr, ptr, ptr, ptr, fpst, i32)
664
DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_s, TCG_CALL_NO_RWG,
665
- void, ptr, ptr, ptr, ptr, ptr, i32)
666
+ void, ptr, ptr, ptr, ptr, fpst, i32)
667
DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_d, TCG_CALL_NO_RWG,
668
- void, ptr, ptr, ptr, ptr, ptr, i32)
669
+ void, ptr, ptr, ptr, ptr, fpst, i32)
670
671
DEF_HELPER_FLAGS_5(sve2_eor3, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
672
DEF_HELPER_FLAGS_5(sve2_bcax, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
673
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_zzzz_s, TCG_CALL_NO_RWG,
674
DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_zzzz_d, TCG_CALL_NO_RWG,
675
void, ptr, ptr, ptr, ptr, i32)
676
677
-DEF_HELPER_FLAGS_6(fmmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32)
678
-DEF_HELPER_FLAGS_6(fmmla_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32)
679
+DEF_HELPER_FLAGS_6(fmmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, fpst, i32)
680
+DEF_HELPER_FLAGS_6(fmmla_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, fpst, i32)
681
682
DEF_HELPER_FLAGS_5(sve2_sqrdmlah_idx_h, TCG_CALL_NO_RWG,
683
void, ptr, ptr, ptr, ptr, i32)
684
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sve2_cdot_idx_d, TCG_CALL_NO_RWG,
685
void, ptr, ptr, ptr, ptr, i32)
686
687
DEF_HELPER_FLAGS_5(sve2_fcvtnt_sh, TCG_CALL_NO_RWG,
688
- void, ptr, ptr, ptr, ptr, i32)
689
+ void, ptr, ptr, ptr, fpst, i32)
690
DEF_HELPER_FLAGS_5(sve2_fcvtnt_ds, TCG_CALL_NO_RWG,
691
- void, ptr, ptr, ptr, ptr, i32)
692
+ void, ptr, ptr, ptr, fpst, i32)
693
DEF_HELPER_FLAGS_5(sve_bfcvtnt, TCG_CALL_NO_RWG,
694
- void, ptr, ptr, ptr, ptr, i32)
695
+ void, ptr, ptr, ptr, fpst, i32)
696
697
DEF_HELPER_FLAGS_5(sve2_fcvtlt_hs, TCG_CALL_NO_RWG,
698
- void, ptr, ptr, ptr, ptr, i32)
699
+ void, ptr, ptr, ptr, fpst, i32)
700
DEF_HELPER_FLAGS_5(sve2_fcvtlt_sd, TCG_CALL_NO_RWG,
701
- void, ptr, ptr, ptr, ptr, i32)
702
+ void, ptr, ptr, ptr, fpst, i32)
703
704
-DEF_HELPER_FLAGS_5(flogb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
705
-DEF_HELPER_FLAGS_5(flogb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
706
-DEF_HELPER_FLAGS_5(flogb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
707
+DEF_HELPER_FLAGS_5(flogb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
708
+DEF_HELPER_FLAGS_5(flogb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
709
+DEF_HELPER_FLAGS_5(flogb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
710
711
DEF_HELPER_FLAGS_4(sve2_sqshl_zpzi_b, TCG_CALL_NO_RWG,
712
void, ptr, ptr, ptr, i32)
713
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
714
index XXXXXXX..XXXXXXX 100644
715
--- a/target/arm/tcg/sve_helper.c
716
+++ b/target/arm/tcg/sve_helper.c
717
@@ -XXX,XX +XXX,XX @@ DO_ZPZZ_PAIR_D(sve2_sminp_zpzz_d, int64_t, DO_MIN)
718
719
#define DO_ZPZZ_PAIR_FP(NAME, TYPE, H, OP) \
720
void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, \
721
- void *status, uint32_t desc) \
722
+ float_status *status, uint32_t desc) \
723
{ \
724
intptr_t i, opr_sz = simd_oprsz(desc); \
725
for (i = 0; i < opr_sz; ) { \
726
@@ -XXX,XX +XXX,XX @@ static TYPE NAME##_reduce(TYPE *data, float_status *status, uintptr_t n) \
727
return TYPE##_##FUNC(lo, hi, status); \
728
} \
729
} \
730
-uint64_t HELPER(NAME)(void *vn, void *vg, void *vs, uint32_t desc) \
731
+uint64_t HELPER(NAME)(void *vn, void *vg, float_status *s, uint32_t desc) \
732
{ \
733
uintptr_t i, oprsz = simd_oprsz(desc), maxsz = simd_data(desc); \
734
TYPE data[sizeof(ARMVectorReg) / sizeof(TYPE)]; \
735
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(NAME)(void *vn, void *vg, void *vs, uint32_t desc) \
736
for (; i < maxsz; i += sizeof(TYPE)) { \
737
*(TYPE *)((void *)data + i) = IDENT; \
738
} \
739
- return NAME##_reduce(data, vs, maxsz / sizeof(TYPE)); \
740
+ return NAME##_reduce(data, s, maxsz / sizeof(TYPE)); \
741
}
742
743
DO_REDUCE(sve_faddv_h, float16, H1_2, add, float16_zero)
744
@@ -XXX,XX +XXX,XX @@ DO_REDUCE(sve_fmaxv_d, float64, H1_8, max, float64_chs(float64_infinity))
745
#undef DO_REDUCE
746
747
uint64_t HELPER(sve_fadda_h)(uint64_t nn, void *vm, void *vg,
748
- void *status, uint32_t desc)
749
+ float_status *status, uint32_t desc)
750
{
751
intptr_t i = 0, opr_sz = simd_oprsz(desc);
752
float16 result = nn;
753
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(sve_fadda_h)(uint64_t nn, void *vm, void *vg,
754
}
755
756
uint64_t HELPER(sve_fadda_s)(uint64_t nn, void *vm, void *vg,
757
- void *status, uint32_t desc)
758
+ float_status *status, uint32_t desc)
759
{
760
intptr_t i = 0, opr_sz = simd_oprsz(desc);
761
float32 result = nn;
762
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(sve_fadda_s)(uint64_t nn, void *vm, void *vg,
763
}
764
765
uint64_t HELPER(sve_fadda_d)(uint64_t nn, void *vm, void *vg,
766
- void *status, uint32_t desc)
767
+ float_status *status, uint32_t desc)
768
{
769
intptr_t i = 0, opr_sz = simd_oprsz(desc) / 8;
770
uint64_t *m = vm;
771
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(sve_fadda_d)(uint64_t nn, void *vm, void *vg,
772
*/
773
#define DO_ZPZZ_FP(NAME, TYPE, H, OP) \
774
void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, \
775
- void *status, uint32_t desc) \
776
+ float_status *status, uint32_t desc) \
777
{ \
778
intptr_t i = simd_oprsz(desc); \
779
uint64_t *g = vg; \
780
@@ -XXX,XX +XXX,XX @@ DO_ZPZZ_FP(sve_fmulx_d, uint64_t, H1_8, helper_vfp_mulxd)
781
*/
782
#define DO_ZPZS_FP(NAME, TYPE, H, OP) \
783
void HELPER(NAME)(void *vd, void *vn, void *vg, uint64_t scalar, \
784
- void *status, uint32_t desc) \
785
+ float_status *status, uint32_t desc) \
786
{ \
787
intptr_t i = simd_oprsz(desc); \
788
uint64_t *g = vg; \
789
@@ -XXX,XX +XXX,XX @@ DO_ZPZS_FP(sve_fmins_d, float64, H1_8, float64_min)
790
* With the extra float_status parameter.
791
*/
792
#define DO_ZPZ_FP(NAME, TYPE, H, OP) \
793
-void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \
794
+void HELPER(NAME)(void *vd, void *vn, void *vg, \
795
+ float_status *status, uint32_t desc) \
796
{ \
797
intptr_t i = simd_oprsz(desc); \
798
uint64_t *g = vg; \
799
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_h(void *vd, void *vn, void *vm, void *va, void *vg,
800
}
801
802
void HELPER(sve_fmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
803
- void *vg, void *status, uint32_t desc)
804
+ void *vg, float_status *status, uint32_t desc)
805
{
806
do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0);
807
}
808
809
void HELPER(sve_fmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
810
- void *vg, void *status, uint32_t desc)
811
+ void *vg, float_status *status, uint32_t desc)
812
{
813
do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0);
814
}
815
816
void HELPER(sve_fnmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
817
- void *vg, void *status, uint32_t desc)
818
+ void *vg, float_status *status, uint32_t desc)
819
{
820
do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0x8000);
821
}
822
823
void HELPER(sve_fnmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
824
- void *vg, void *status, uint32_t desc)
825
+ void *vg, float_status *status, uint32_t desc)
826
{
827
do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0x8000);
828
}
829
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_s(void *vd, void *vn, void *vm, void *va, void *vg,
830
}
831
832
void HELPER(sve_fmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
833
- void *vg, void *status, uint32_t desc)
834
+ void *vg, float_status *status, uint32_t desc)
835
{
836
do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0);
837
}
838
839
void HELPER(sve_fmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
840
- void *vg, void *status, uint32_t desc)
841
+ void *vg, float_status *status, uint32_t desc)
842
{
843
do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0);
844
}
845
846
void HELPER(sve_fnmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
847
- void *vg, void *status, uint32_t desc)
848
+ void *vg, float_status *status, uint32_t desc)
849
{
850
do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0x80000000);
851
}
852
853
void HELPER(sve_fnmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
854
- void *vg, void *status, uint32_t desc)
855
+ void *vg, float_status *status, uint32_t desc)
856
{
857
do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0x80000000);
858
}
859
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_d(void *vd, void *vn, void *vm, void *va, void *vg,
860
}
861
862
void HELPER(sve_fmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
863
- void *vg, void *status, uint32_t desc)
864
+ void *vg, float_status *status, uint32_t desc)
865
{
866
do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, 0);
867
}
868
869
void HELPER(sve_fmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
870
- void *vg, void *status, uint32_t desc)
871
+ void *vg, float_status *status, uint32_t desc)
872
{
873
do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, 0);
874
}
875
876
void HELPER(sve_fnmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
877
- void *vg, void *status, uint32_t desc)
878
+ void *vg, float_status *status, uint32_t desc)
879
{
880
do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, INT64_MIN);
881
}
882
883
void HELPER(sve_fnmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
884
- void *vg, void *status, uint32_t desc)
885
+ void *vg, float_status *status, uint32_t desc)
886
{
887
do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, INT64_MIN);
888
}
889
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fnmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
890
*/
891
#define DO_FPCMP_PPZZ(NAME, TYPE, H, OP) \
892
void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, \
893
- void *status, uint32_t desc) \
894
+ float_status *status, uint32_t desc) \
895
{ \
896
intptr_t i = simd_oprsz(desc), j = (i - 1) >> 6; \
897
uint64_t *d = vd, *g = vg; \
898
@@ -XXX,XX +XXX,XX @@ DO_FPCMP_PPZZ_ALL(sve_facgt, DO_FACGT)
899
*/
900
#define DO_FPCMP_PPZ0(NAME, TYPE, H, OP) \
901
void HELPER(NAME)(void *vd, void *vn, void *vg, \
902
- void *status, uint32_t desc) \
903
+ float_status *status, uint32_t desc) \
904
{ \
905
intptr_t i = simd_oprsz(desc), j = (i - 1) >> 6; \
906
uint64_t *d = vd, *g = vg; \
907
@@ -XXX,XX +XXX,XX @@ DO_FPCMP_PPZ0_ALL(sve_fcmne0, DO_FCMNE)
908
909
/* FP Trig Multiply-Add. */
910
911
-void HELPER(sve_ftmad_h)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
912
+void HELPER(sve_ftmad_h)(void *vd, void *vn, void *vm,
913
+ float_status *s, uint32_t desc)
914
{
915
static const float16 coeff[16] = {
916
0x3c00, 0xb155, 0x2030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
917
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_ftmad_h)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
918
mm = float16_abs(mm);
919
xx += 8;
920
}
921
- d[i] = float16_muladd(n[i], mm, coeff[xx], 0, vs);
922
+ d[i] = float16_muladd(n[i], mm, coeff[xx], 0, s);
923
}
924
}
925
926
-void HELPER(sve_ftmad_s)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
927
+void HELPER(sve_ftmad_s)(void *vd, void *vn, void *vm,
928
+ float_status *s, uint32_t desc)
929
{
930
static const float32 coeff[16] = {
931
0x3f800000, 0xbe2aaaab, 0x3c088886, 0xb95008b9,
932
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_ftmad_s)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
933
mm = float32_abs(mm);
934
xx += 8;
935
}
936
- d[i] = float32_muladd(n[i], mm, coeff[xx], 0, vs);
937
+ d[i] = float32_muladd(n[i], mm, coeff[xx], 0, s);
938
}
939
}
940
941
-void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
942
+void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm,
943
+ float_status *s, uint32_t desc)
944
{
945
static const float64 coeff[16] = {
946
0x3ff0000000000000ull, 0xbfc5555555555543ull,
947
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
948
mm = float64_abs(mm);
949
xx += 8;
950
}
951
- d[i] = float64_muladd(n[i], mm, coeff[xx], 0, vs);
952
+ d[i] = float64_muladd(n[i], mm, coeff[xx], 0, s);
953
}
954
}
955
956
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
957
*/
958
959
void HELPER(sve_fcadd_h)(void *vd, void *vn, void *vm, void *vg,
960
- void *vs, uint32_t desc)
961
+ float_status *s, uint32_t desc)
962
{
963
intptr_t j, i = simd_oprsz(desc);
964
uint64_t *g = vg;
965
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcadd_h)(void *vd, void *vn, void *vm, void *vg,
966
e3 = *(float16 *)(vm + H1_2(i)) ^ neg_imag;
967
968
if (likely((pg >> (i & 63)) & 1)) {
969
- *(float16 *)(vd + H1_2(i)) = float16_add(e0, e1, vs);
970
+ *(float16 *)(vd + H1_2(i)) = float16_add(e0, e1, s);
971
}
972
if (likely((pg >> (j & 63)) & 1)) {
973
- *(float16 *)(vd + H1_2(j)) = float16_add(e2, e3, vs);
974
+ *(float16 *)(vd + H1_2(j)) = float16_add(e2, e3, s);
975
}
976
} while (i & 63);
977
} while (i != 0);
978
}
979
980
void HELPER(sve_fcadd_s)(void *vd, void *vn, void *vm, void *vg,
981
- void *vs, uint32_t desc)
982
+ float_status *s, uint32_t desc)
983
{
984
intptr_t j, i = simd_oprsz(desc);
985
uint64_t *g = vg;
986
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcadd_s)(void *vd, void *vn, void *vm, void *vg,
987
e3 = *(float32 *)(vm + H1_2(i)) ^ neg_imag;
988
989
if (likely((pg >> (i & 63)) & 1)) {
990
- *(float32 *)(vd + H1_2(i)) = float32_add(e0, e1, vs);
991
+ *(float32 *)(vd + H1_2(i)) = float32_add(e0, e1, s);
992
}
993
if (likely((pg >> (j & 63)) & 1)) {
994
- *(float32 *)(vd + H1_2(j)) = float32_add(e2, e3, vs);
995
+ *(float32 *)(vd + H1_2(j)) = float32_add(e2, e3, s);
996
}
997
} while (i & 63);
998
} while (i != 0);
999
}
1000
1001
void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg,
1002
- void *vs, uint32_t desc)
1003
+ float_status *s, uint32_t desc)
1004
{
1005
intptr_t j, i = simd_oprsz(desc);
1006
uint64_t *g = vg;
1007
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg,
1008
e3 = *(float64 *)(vm + H1_2(i)) ^ neg_imag;
1009
1010
if (likely((pg >> (i & 63)) & 1)) {
1011
- *(float64 *)(vd + H1_2(i)) = float64_add(e0, e1, vs);
1012
+ *(float64 *)(vd + H1_2(i)) = float64_add(e0, e1, s);
1013
}
1014
if (likely((pg >> (j & 63)) & 1)) {
1015
- *(float64 *)(vd + H1_2(j)) = float64_add(e2, e3, vs);
1016
+ *(float64 *)(vd + H1_2(j)) = float64_add(e2, e3, s);
1017
}
1018
} while (i & 63);
1019
} while (i != 0);
1020
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg,
1021
*/
1022
1023
void HELPER(sve_fcmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
1024
- void *vg, void *status, uint32_t desc)
1025
+ void *vg, float_status *status, uint32_t desc)
1026
{
1027
intptr_t j, i = simd_oprsz(desc);
1028
unsigned rot = simd_data(desc);
1029
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
1030
}
1031
1032
void HELPER(sve_fcmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
1033
- void *vg, void *status, uint32_t desc)
1034
+ void *vg, float_status *status, uint32_t desc)
1035
{
1036
intptr_t j, i = simd_oprsz(desc);
1037
unsigned rot = simd_data(desc);
1038
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
1039
}
1040
1041
void HELPER(sve_fcmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
1042
- void *vg, void *status, uint32_t desc)
1043
+ void *vg, float_status *status, uint32_t desc)
1044
{
1045
intptr_t j, i = simd_oprsz(desc);
1046
unsigned rot = simd_data(desc);
1047
@@ -XXX,XX +XXX,XX @@ void HELPER(sve2_xar_s)(void *vd, void *vn, void *vm, uint32_t desc)
1048
}
1049
1050
void HELPER(fmmla_s)(void *vd, void *vn, void *vm, void *va,
1051
- void *status, uint32_t desc)
1052
+ float_status *status, uint32_t desc)
1053
{
1054
intptr_t s, opr_sz = simd_oprsz(desc) / (sizeof(float32) * 4);
1055
1056
@@ -XXX,XX +XXX,XX @@ void HELPER(fmmla_s)(void *vd, void *vn, void *vm, void *va,
1057
}
1058
1059
void HELPER(fmmla_d)(void *vd, void *vn, void *vm, void *va,
1060
- void *status, uint32_t desc)
1061
+ float_status *status, uint32_t desc)
1062
{
1063
intptr_t s, opr_sz = simd_oprsz(desc) / (sizeof(float64) * 4);
1064
1065
@@ -XXX,XX +XXX,XX @@ void HELPER(fmmla_d)(void *vd, void *vn, void *vm, void *va,
1066
}
1067
1068
#define DO_FCVTNT(NAME, TYPEW, TYPEN, HW, HN, OP) \
1069
-void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \
1070
+void HELPER(NAME)(void *vd, void *vn, void *vg, \
1071
+ float_status *status, uint32_t desc) \
1072
{ \
1073
intptr_t i = simd_oprsz(desc); \
1074
uint64_t *g = vg; \
1075
@@ -XXX,XX +XXX,XX @@ DO_FCVTNT(sve2_fcvtnt_sh, uint32_t, uint16_t, H1_4, H1_2, sve_f32_to_f16)
1076
DO_FCVTNT(sve2_fcvtnt_ds, uint64_t, uint32_t, H1_8, H1_4, float64_to_float32)
1077
1078
#define DO_FCVTLT(NAME, TYPEW, TYPEN, HW, HN, OP) \
1079
-void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \
1080
+void HELPER(NAME)(void *vd, void *vn, void *vg, \
1081
+ float_status *status, uint32_t desc) \
1082
{ \
1083
intptr_t i = simd_oprsz(desc); \
1084
uint64_t *g = vg; \
1085
--
1086
2.34.1
1087
1088
diff view generated by jsdifflib
New patch
[PULL 07/19] target/arm: Convert sme_helper.c to fpst alias
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20241206031224.78525-8-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/tcg/helper-sme.h | 4 ++--
9
target/arm/tcg/sme_helper.c | 8 ++++----
10
2 files changed, 6 insertions(+), 6 deletions(-)
11
12
diff --git a/target/arm/tcg/helper-sme.h b/target/arm/tcg/helper-sme.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/tcg/helper-sme.h
15
+++ b/target/arm/tcg/helper-sme.h
16
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
17
DEF_HELPER_FLAGS_7(sme_fmopa_h, TCG_CALL_NO_RWG,
18
void, ptr, ptr, ptr, ptr, ptr, env, i32)
19
DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG,
20
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
21
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
22
DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG,
23
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
24
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
25
DEF_HELPER_FLAGS_7(sme_bfmopa, TCG_CALL_NO_RWG,
26
void, ptr, ptr, ptr, ptr, ptr, env, i32)
27
DEF_HELPER_FLAGS_6(sme_smopa_s, TCG_CALL_NO_RWG,
28
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/tcg/sme_helper.c
31
+++ b/target/arm/tcg/sme_helper.c
32
@@ -XXX,XX +XXX,XX @@ void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn,
33
}
34
35
void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn,
36
- void *vpm, void *vst, uint32_t desc)
37
+ void *vpm, float_status *fpst_in, uint32_t desc)
38
{
39
intptr_t row, col, oprsz = simd_maxsz(desc);
40
uint32_t neg = simd_data(desc) << 31;
41
@@ -XXX,XX +XXX,XX @@ void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn,
42
* update the cumulative fp exception status. It also produces
43
* default nans.
44
*/
45
- fpst = *(float_status *)vst;
46
+ fpst = *fpst_in;
47
set_default_nan_mode(true, &fpst);
48
49
for (row = 0; row < oprsz; ) {
50
@@ -XXX,XX +XXX,XX @@ void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn,
51
}
52
53
void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn,
54
- void *vpm, void *vst, uint32_t desc)
55
+ void *vpm, float_status *fpst_in, uint32_t desc)
56
{
57
intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
58
uint64_t neg = (uint64_t)simd_data(desc) << 63;
59
uint64_t *za = vza, *zn = vzn, *zm = vzm;
60
uint8_t *pn = vpn, *pm = vpm;
61
- float_status fpst = *(float_status *)vst;
62
+ float_status fpst = *fpst_in;
63
64
set_default_nan_mode(true, &fpst);
65
66
--
67
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 3/5] vmstate.h: Type check VMSTATE_STRUCT_VARRAY macros
[PULL 08/19] target/arm: Convert vec_helper.c to use env alias
1
The VMSTATE_STRUCT_VARRAY_UINT32 macro is intended to handle
1
From: Richard Henderson <richard.henderson@linaro.org>
2
migrating a field which is an array of structs, but where instead of
3
migrating the entire array we only migrate a variable number of
4
elements of it.
5
2
6
The VMSTATE_STRUCT_VARRAY_POINTER_UINT32 macro is intended to handle
3
Allow the helpers to receive CPUARMState* directly
7
migrating a field which is of pointer type, and points to a
4
instead of via void*.
8
dynamically allocated array of structs of variable size.
9
5
10
We weren't actually checking that the field passed to
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
VMSTATE_STRUCT_VARRAY_UINT32 really is an array, with the result that
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
accidentally using it where the _POINTER_ macro was intended would
8
Message-id: 20241206031224.78525-9-richard.henderson@linaro.org
13
compile but silently corrupt memory on migration.
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/helper.h | 12 ++++++------
12
target/arm/tcg/helper-a64.h | 2 +-
13
target/arm/tcg/vec_helper.c | 21 +++++++--------------
14
3 files changed, 14 insertions(+), 21 deletions(-)
14
15
15
Add type-checking that enforces that the field passed in is
16
diff --git a/target/arm/helper.h b/target/arm/helper.h
16
really of the right array type. This applies to all the VMSTATE
17
macros which use flags including VMS_VARRAY_* but not VMS_POINTER.
18
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
21
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
22
Tested-by: Damien Hedde <damien.hedde@greensocs.com>
23
Message-id: 20190725163710.11703-3-peter.maydell@linaro.org
24
---
25
include/migration/vmstate.h | 30 ++++++++++++++++++++++++------
26
1 file changed, 24 insertions(+), 6 deletions(-)
27
28
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
29
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
30
--- a/include/migration/vmstate.h
18
--- a/target/arm/helper.h
31
+++ b/include/migration/vmstate.h
19
+++ b/target/arm/helper.h
32
@@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_bitmap;
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_suqadd_d, TCG_CALL_NO_RWG,
33
extern const VMStateInfo vmstate_info_qtailq;
21
void, ptr, ptr, ptr, ptr, i32)
34
22
35
#define type_check_2darray(t1,t2,n,m) ((t1(*)[n][m])0 - (t2*)0)
23
DEF_HELPER_FLAGS_5(gvec_fmlal_a32, TCG_CALL_NO_RWG,
36
+/*
24
- void, ptr, ptr, ptr, ptr, i32)
37
+ * Check that type t2 is an array of type t1 of size n,
25
+ void, ptr, ptr, ptr, env, i32)
38
+ * e.g. if t1 is 'foo' and n is 32 then t2 must be 'foo[32]'
26
DEF_HELPER_FLAGS_5(gvec_fmlal_a64, TCG_CALL_NO_RWG,
39
+ */
27
- void, ptr, ptr, ptr, ptr, i32)
40
#define type_check_array(t1,t2,n) ((t1(*)[n])0 - (t2*)0)
28
+ void, ptr, ptr, ptr, env, i32)
41
#define type_check_pointer(t1,t2) ((t1**)0 - (t2*)0)
29
DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG,
42
+/*
30
- void, ptr, ptr, ptr, ptr, i32)
43
+ * type of element 0 of the specified (array) field of the type.
31
+ void, ptr, ptr, ptr, env, i32)
44
+ * Note that if the field is a pointer then this will return the
32
DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG,
45
+ * pointed-to type rather than complaining.
33
- void, ptr, ptr, ptr, ptr, i32)
46
+ */
34
+ void, ptr, ptr, ptr, env, i32)
47
+#define typeof_elt_of_field(type, field) typeof(((type *)0)->field[0])
35
48
+/* Check that field f in struct type t2 is an array of t1, of any size */
36
DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, fpst)
49
+#define type_check_varray(t1, t2, f) \
37
DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, fpst)
50
+ (type_check(t1, typeof_elt_of_field(t2, f)) \
38
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_d, TCG_CALL_NO_RWG,
51
+ + QEMU_BUILD_BUG_ON_ZERO(!QEMU_IS_ARRAY(((t2 *)0)->f)))
39
void, ptr, ptr, ptr, i32)
52
40
53
#define vmstate_offset_value(_state, _field, _type) \
41
DEF_HELPER_FLAGS_6(sve2_fmlal_zzzw_s, TCG_CALL_NO_RWG,
54
(offsetof(_state, _field) + \
42
- void, ptr, ptr, ptr, ptr, ptr, i32)
55
@@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq;
43
+ void, ptr, ptr, ptr, ptr, env, i32)
56
vmstate_offset_array(_state, _field, uint8_t, \
44
DEF_HELPER_FLAGS_6(sve2_fmlal_zzxw_s, TCG_CALL_NO_RWG,
57
sizeof(typeof_field(_state, _field)))
45
- void, ptr, ptr, ptr, ptr, ptr, i32)
58
46
+ void, ptr, ptr, ptr, ptr, env, i32)
59
+#define vmstate_offset_varray(_state, _field, _type) \
47
60
+ (offsetof(_state, _field) + \
48
DEF_HELPER_FLAGS_4(gvec_xar_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
61
+ type_check_varray(_type, _state, _field))
49
62
+
50
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
63
/* In the macros below, if there is a _version, that means the macro's
51
index XXXXXXX..XXXXXXX 100644
64
* field will be processed only if the version being received is >=
52
--- a/target/arm/tcg/helper-a64.h
65
* the _version specified. In general, if you add a new field, you
53
+++ b/target/arm/tcg/helper-a64.h
66
@@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq;
54
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, fpst)
67
.info = &(_info), \
55
DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, fpst)
68
.size = sizeof(_type), \
56
DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, fpst)
69
.flags = VMS_VARRAY_UINT32|VMS_MULTIPLY_ELEMENTS, \
57
DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, fpst)
70
- .offset = offsetof(_state, _field), \
58
-DEF_HELPER_FLAGS_4(simd_tblx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
71
+ .offset = vmstate_offset_varray(_state, _field, _type), \
59
+DEF_HELPER_FLAGS_4(simd_tblx, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
60
DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, fpst)
61
DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, fpst)
62
DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, fpst)
63
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/tcg/vec_helper.c
66
+++ b/target/arm/tcg/vec_helper.c
67
@@ -XXX,XX +XXX,XX @@ static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst,
72
}
68
}
73
69
74
#define VMSTATE_ARRAY_TEST(_field, _state, _num, _test, _info, _type) {\
70
void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm,
75
@@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq;
71
- void *venv, uint32_t desc)
76
.info = &(_info), \
72
+ CPUARMState *env, uint32_t desc)
77
.size = sizeof(_type), \
73
{
78
.flags = VMS_VARRAY_INT32, \
74
- CPUARMState *env = venv;
79
- .offset = offsetof(_state, _field), \
75
do_fmlal(vd, vn, vm, &env->vfp.standard_fp_status, desc,
80
+ .offset = vmstate_offset_varray(_state, _field, _type), \
76
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
81
}
77
}
82
78
83
#define VMSTATE_VARRAY_INT32(_field, _state, _field_num, _version, _info, _type) {\
79
void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
84
@@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq;
80
- void *venv, uint32_t desc)
85
.info = &(_info), \
81
+ CPUARMState *env, uint32_t desc)
86
.size = sizeof(_type), \
82
{
87
.flags = VMS_VARRAY_UINT16, \
83
- CPUARMState *env = venv;
88
- .offset = offsetof(_state, _field), \
84
do_fmlal(vd, vn, vm, &env->vfp.fp_status, desc,
89
+ .offset = vmstate_offset_varray(_state, _field, _type), \
85
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
90
}
86
}
91
87
92
#define VMSTATE_VSTRUCT_TEST(_field, _state, _test, _version, _vmsd, _type, _struct_version) { \
88
void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, void *vm, void *va,
93
@@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq;
89
- void *venv, uint32_t desc)
94
.vmsd = &(_vmsd), \
90
+ CPUARMState *env, uint32_t desc)
95
.size = sizeof(_type), \
91
{
96
.flags = VMS_STRUCT|VMS_VARRAY_UINT8, \
92
intptr_t i, oprsz = simd_oprsz(desc);
97
- .offset = offsetof(_state, _field), \
93
uint16_t negn = extract32(desc, SIMD_DATA_SHIFT, 1) << 15;
98
+ .offset = vmstate_offset_varray(_state, _field, _type), \
94
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16);
95
- CPUARMState *env = venv;
96
float_status *status = &env->vfp.fp_status;
97
bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16);
98
99
@@ -XXX,XX +XXX,XX @@ static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fpst,
99
}
100
}
100
101
101
/* a variable length array (i.e. _type *_field) but we know the
102
void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm,
102
@@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq;
103
- void *venv, uint32_t desc)
103
.vmsd = &(_vmsd), \
104
+ CPUARMState *env, uint32_t desc)
104
.size = sizeof(_type), \
105
{
105
.flags = VMS_STRUCT|VMS_VARRAY_INT32, \
106
- CPUARMState *env = venv;
106
- .offset = offsetof(_state, _field), \
107
do_fmlal_idx(vd, vn, vm, &env->vfp.standard_fp_status, desc,
107
+ .offset = vmstate_offset_varray(_state, _field, _type), \
108
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
108
}
109
}
109
110
110
#define VMSTATE_STRUCT_VARRAY_UINT32(_field, _state, _field_num, _version, _vmsd, _type) { \
111
void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
111
@@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq;
112
- void *venv, uint32_t desc)
112
.vmsd = &(_vmsd), \
113
+ CPUARMState *env, uint32_t desc)
113
.size = sizeof(_type), \
114
{
114
.flags = VMS_STRUCT|VMS_VARRAY_UINT32, \
115
- CPUARMState *env = venv;
115
- .offset = offsetof(_state, _field), \
116
do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc,
116
+ .offset = vmstate_offset_varray(_state, _field, _type), \
117
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
117
}
118
}
118
119
119
#define VMSTATE_STRUCT_VARRAY_ALLOC(_field, _state, _field_num, _version, _vmsd, _type) {\
120
void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, void *vm, void *va,
121
- void *venv, uint32_t desc)
122
+ CPUARMState *env, uint32_t desc)
123
{
124
intptr_t i, j, oprsz = simd_oprsz(desc);
125
uint16_t negn = extract32(desc, SIMD_DATA_SHIFT, 1) << 15;
126
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16);
127
intptr_t idx = extract32(desc, SIMD_DATA_SHIFT + 2, 3) * sizeof(float16);
128
- CPUARMState *env = venv;
129
float_status *status = &env->vfp.fp_status;
130
bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16);
131
132
@@ -XXX,XX +XXX,XX @@ DO_VRINT_RMODE(gvec_vrint_rm_s, helper_rints, uint32_t)
133
#undef DO_VRINT_RMODE
134
135
#ifdef TARGET_AARCH64
136
-void HELPER(simd_tblx)(void *vd, void *vm, void *venv, uint32_t desc)
137
+void HELPER(simd_tblx)(void *vd, void *vm, CPUARMState *env, uint32_t desc)
138
{
139
const uint8_t *indices = vm;
140
- CPUARMState *env = venv;
141
size_t oprsz = simd_oprsz(desc);
142
uint32_t rn = extract32(desc, SIMD_DATA_SHIFT, 5);
143
bool is_tbx = extract32(desc, SIMD_DATA_SHIFT + 5, 1);
120
--
144
--
121
2.20.1
145
2.34.1
122
146
123
147
diff view generated by jsdifflib
[Qemu-devel] [PULL 4/5] hw/arm/boot: Rename elf_{low, high}_addr to image_{low, high}_addr
[PULL 09/19] target/arm: Convert neon_helper.c to use env alias
1
Rename the elf_low_addr and elf_high_addr variables to image_low_addr
1
From: Richard Henderson <richard.henderson@linaro.org>
2
and image_high_addr -- in the next commit we will extend them to
3
be set for other kinds of image file and not just ELF files.
4
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Message-id: 20241206031224.78525-10-richard.henderson@linaro.org
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Tested-by: Mark Rutland <mark.rutland@arm.com>
9
Message-id: 20190722151804.25467-2-peter.maydell@linaro.org
10
---
7
---
11
hw/arm/boot.c | 20 +++++++++++---------
8
target/arm/helper.h | 56 ++++++++++++++++++------------------
12
1 file changed, 11 insertions(+), 9 deletions(-)
9
target/arm/tcg/neon_helper.c | 6 ++--
10
2 files changed, 30 insertions(+), 32 deletions(-)
13
11
14
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
12
diff --git a/target/arm/helper.h b/target/arm/helper.h
15
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/boot.c
14
--- a/target/arm/helper.h
17
+++ b/hw/arm/boot.c
15
+++ b/target/arm/helper.h
18
@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
16
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(neon_qrshl_u32, i32, env, i32, i32)
19
int kernel_size;
17
DEF_HELPER_3(neon_qrshl_s32, i32, env, i32, i32)
20
int initrd_size;
18
DEF_HELPER_3(neon_qrshl_u64, i64, env, i64, i64)
21
int is_linux = 0;
19
DEF_HELPER_3(neon_qrshl_s64, i64, env, i64, i64)
22
- uint64_t elf_entry, elf_low_addr, elf_high_addr;
20
-DEF_HELPER_FLAGS_5(neon_sqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
23
+ uint64_t elf_entry;
21
-DEF_HELPER_FLAGS_5(neon_sqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
24
+ /* Addresses of first byte used and first byte not used by the image */
22
-DEF_HELPER_FLAGS_5(neon_sqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
25
+ uint64_t image_low_addr, image_high_addr;
23
-DEF_HELPER_FLAGS_5(neon_sqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
26
int elf_machine;
24
-DEF_HELPER_FLAGS_5(neon_uqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
27
hwaddr entry;
25
-DEF_HELPER_FLAGS_5(neon_uqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
28
static const ARMInsnFixup *primary_loader;
26
-DEF_HELPER_FLAGS_5(neon_uqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
29
@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
27
-DEF_HELPER_FLAGS_5(neon_uqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
30
info->nb_cpus = 1;
28
-DEF_HELPER_FLAGS_5(neon_sqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
31
29
-DEF_HELPER_FLAGS_5(neon_sqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
32
/* Assume that raw images are linux kernels, and ELF images are not. */
30
-DEF_HELPER_FLAGS_5(neon_sqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
33
- kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr,
31
-DEF_HELPER_FLAGS_5(neon_sqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
34
- &elf_high_addr, elf_machine, as);
32
-DEF_HELPER_FLAGS_5(neon_uqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
35
+ kernel_size = arm_load_elf(info, &elf_entry, &image_low_addr,
33
-DEF_HELPER_FLAGS_5(neon_uqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
36
+ &image_high_addr, elf_machine, as);
34
-DEF_HELPER_FLAGS_5(neon_uqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
37
if (kernel_size > 0 && have_dtb(info)) {
35
-DEF_HELPER_FLAGS_5(neon_uqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
38
/*
36
-DEF_HELPER_FLAGS_4(neon_sqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
39
* If there is still some room left at the base of RAM, try and put
37
-DEF_HELPER_FLAGS_4(neon_sqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
40
* the DTB there like we do for images loaded with -bios or -pflash.
38
-DEF_HELPER_FLAGS_4(neon_sqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
41
*/
39
-DEF_HELPER_FLAGS_4(neon_sqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
42
- if (elf_low_addr > info->loader_start
40
-DEF_HELPER_FLAGS_4(neon_uqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
43
- || elf_high_addr < info->loader_start) {
41
-DEF_HELPER_FLAGS_4(neon_uqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
44
+ if (image_low_addr > info->loader_start
42
-DEF_HELPER_FLAGS_4(neon_uqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
45
+ || image_high_addr < info->loader_start) {
43
-DEF_HELPER_FLAGS_4(neon_uqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
46
/*
44
-DEF_HELPER_FLAGS_4(neon_sqshlui_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
47
- * Set elf_low_addr as address limit for arm_load_dtb if it may be
45
-DEF_HELPER_FLAGS_4(neon_sqshlui_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
48
+ * Set image_low_addr as address limit for arm_load_dtb if it may be
46
-DEF_HELPER_FLAGS_4(neon_sqshlui_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
49
* pointing into RAM, otherwise pass '0' (no limit)
47
-DEF_HELPER_FLAGS_4(neon_sqshlui_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
50
*/
48
+DEF_HELPER_FLAGS_5(neon_sqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
51
- if (elf_low_addr < info->loader_start) {
49
+DEF_HELPER_FLAGS_5(neon_sqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
52
- elf_low_addr = 0;
50
+DEF_HELPER_FLAGS_5(neon_sqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
53
+ if (image_low_addr < info->loader_start) {
51
+DEF_HELPER_FLAGS_5(neon_sqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
54
+ image_low_addr = 0;
52
+DEF_HELPER_FLAGS_5(neon_uqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
55
}
53
+DEF_HELPER_FLAGS_5(neon_uqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
56
info->dtb_start = info->loader_start;
54
+DEF_HELPER_FLAGS_5(neon_uqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
57
- info->dtb_limit = elf_low_addr;
55
+DEF_HELPER_FLAGS_5(neon_uqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
58
+ info->dtb_limit = image_low_addr;
56
+DEF_HELPER_FLAGS_5(neon_sqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
59
}
57
+DEF_HELPER_FLAGS_5(neon_sqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
60
}
58
+DEF_HELPER_FLAGS_5(neon_sqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
61
entry = elf_entry;
59
+DEF_HELPER_FLAGS_5(neon_sqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
60
+DEF_HELPER_FLAGS_5(neon_uqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
61
+DEF_HELPER_FLAGS_5(neon_uqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
62
+DEF_HELPER_FLAGS_5(neon_uqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
63
+DEF_HELPER_FLAGS_5(neon_uqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
64
+DEF_HELPER_FLAGS_4(neon_sqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
65
+DEF_HELPER_FLAGS_4(neon_sqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
66
+DEF_HELPER_FLAGS_4(neon_sqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
67
+DEF_HELPER_FLAGS_4(neon_sqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
68
+DEF_HELPER_FLAGS_4(neon_uqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
69
+DEF_HELPER_FLAGS_4(neon_uqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
70
+DEF_HELPER_FLAGS_4(neon_uqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
71
+DEF_HELPER_FLAGS_4(neon_uqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
72
+DEF_HELPER_FLAGS_4(neon_sqshlui_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
73
+DEF_HELPER_FLAGS_4(neon_sqshlui_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
74
+DEF_HELPER_FLAGS_4(neon_sqshlui_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
75
+DEF_HELPER_FLAGS_4(neon_sqshlui_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
76
77
DEF_HELPER_FLAGS_4(gvec_srshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
78
DEF_HELPER_FLAGS_4(gvec_srshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
79
diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/target/arm/tcg/neon_helper.c
82
+++ b/target/arm/tcg/neon_helper.c
83
@@ -XXX,XX +XXX,XX @@ void HELPER(name)(void *vd, void *vn, void *vm, uint32_t desc) \
84
}
85
86
#define NEON_GVEC_VOP2_ENV(name, vtype) \
87
-void HELPER(name)(void *vd, void *vn, void *vm, void *venv, uint32_t desc) \
88
+void HELPER(name)(void *vd, void *vn, void *vm, CPUARMState *env, uint32_t desc) \
89
{ \
90
intptr_t i, opr_sz = simd_oprsz(desc); \
91
vtype *d = vd, *n = vn, *m = vm; \
92
- CPUARMState *env = venv; \
93
for (i = 0; i < opr_sz / sizeof(vtype); i++) { \
94
NEON_FN(d[i], n[i], m[i]); \
95
} \
96
@@ -XXX,XX +XXX,XX @@ void HELPER(name)(void *vd, void *vn, void *vm, void *venv, uint32_t desc) \
97
}
98
99
#define NEON_GVEC_VOP2i_ENV(name, vtype) \
100
-void HELPER(name)(void *vd, void *vn, void *venv, uint32_t desc) \
101
+void HELPER(name)(void *vd, void *vn, CPUARMState *env, uint32_t desc) \
102
{ \
103
intptr_t i, opr_sz = simd_oprsz(desc); \
104
int imm = simd_data(desc); \
105
vtype *d = vd, *n = vn; \
106
- CPUARMState *env = venv; \
107
for (i = 0; i < opr_sz / sizeof(vtype); i++) { \
108
NEON_FN(d[i], n[i], imm); \
109
} \
62
--
110
--
63
2.20.1
111
2.34.1
64
112
65
113
diff view generated by jsdifflib
[Qemu-devel] [PULL 5/5] hw/arm/boot: Further improve initrd positioning code
[PULL 10/19] target/arm: Use float_status in helper_fcvtx_f64_to_f32
1
In commit e6b2b20d9735d4ef we made the boot loader code try to avoid
1
From: Richard Henderson <richard.henderson@linaro.org>
2
putting the initrd on top of the kernel. However the expression used
3
to calculate the start of the initrd:
4
2
5
info->initrd_start = info->loader_start +
3
Pass float_status not env to match other functions.
6
MAX(MIN(info->ram_size / 2, 128 * 1024 * 1024), kernel_size);
7
4
8
incorrectly uses 'kernel_size' as the offset within RAM of the
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
highest address to avoid. This is incorrect because the kernel
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
doesn't start at address 0, but slightly higher than that. This
7
Message-id: 20241206031952.78776-2-richard.henderson@linaro.org
11
means that we can still incorrectly end up overlaying the initrd on
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
the kernel in some cases, for example:
9
---
10
target/arm/tcg/helper-a64.h | 2 +-
11
target/arm/tcg/helper-a64.c | 3 +--
12
target/arm/tcg/translate-a64.c | 2 +-
13
3 files changed, 3 insertions(+), 4 deletions(-)
13
14
14
* The kernel's image_size is 0x0a7a8000
15
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
15
* The kernel was loaded at 0x40080000
16
* The end of the kernel is 0x4A828000
17
* The DTB was loaded at 0x4a800000
18
19
To get this right we need to track the actual highest address used
20
by the kernel and use that rather than kernel_size. We already
21
set image_low_addr and image_high_addr for ELF images; set them
22
also for the various other image types we support, and then use
23
image_high_addr as the lowest allowed address for the initrd.
24
(We don't use image_low_addr, but we set it for consistency
25
with the existing code path for ELF files.)
26
27
Fixes: e6b2b20d9735d4ef
28
Reported-by: Mark Rutland <mark.rutland@arm.com>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
31
Tested-by: Mark Rutland <mark.rutland@arm.com>
32
Message-id: 20190722151804.25467-3-peter.maydell@linaro.org
33
---
34
hw/arm/boot.c | 19 +++++++++++++++++--
35
1 file changed, 17 insertions(+), 2 deletions(-)
36
37
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
38
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/arm/boot.c
17
--- a/target/arm/tcg/helper-a64.h
40
+++ b/hw/arm/boot.c
18
+++ b/target/arm/tcg/helper-a64.h
41
@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, fpst)
42
int is_linux = 0;
20
DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, fpst)
43
uint64_t elf_entry;
21
DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
44
/* Addresses of first byte used and first byte not used by the image */
22
DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, fpst)
45
- uint64_t image_low_addr, image_high_addr;
23
-DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env)
46
+ uint64_t image_low_addr = 0, image_high_addr = 0;
24
+DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, fpst)
47
int elf_machine;
25
DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
48
hwaddr entry;
26
DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
49
static const ARMInsnFixup *primary_loader;
27
DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
50
@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
28
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
51
uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR;
29
index XXXXXXX..XXXXXXX 100644
52
kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr,
30
--- a/target/arm/tcg/helper-a64.c
53
&is_linux, NULL, NULL, as);
31
+++ b/target/arm/tcg/helper-a64.c
54
+ if (kernel_size >= 0) {
32
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, float_status *fpst)
55
+ image_low_addr = loadaddr;
56
+ image_high_addr = image_low_addr + kernel_size;
57
+ }
58
}
33
}
59
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) {
34
}
60
kernel_size = load_aarch64_image(info->kernel_filename,
35
61
info->loader_start, &entry, as);
36
-float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env)
62
is_linux = 1;
37
+float32 HELPER(fcvtx_f64_to_f32)(float64 a, float_status *fpst)
63
+ if (kernel_size >= 0) {
38
{
64
+ image_low_addr = entry;
39
float32 r;
65
+ image_high_addr = image_low_addr + kernel_size;
40
- float_status *fpst = &env->vfp.fp_status;
66
+ }
41
int old = get_float_rounding_mode(fpst);
67
} else if (kernel_size < 0) {
42
68
/* 32-bit ARM */
43
set_float_rounding_mode(float_round_to_odd, fpst);
69
entry = info->loader_start + KERNEL_LOAD_ADDR;
44
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
70
kernel_size = load_image_targphys_as(info->kernel_filename, entry,
45
index XXXXXXX..XXXXXXX 100644
71
ram_end - KERNEL_LOAD_ADDR, as);
46
--- a/target/arm/tcg/translate-a64.c
72
is_linux = 1;
47
+++ b/target/arm/tcg/translate-a64.c
73
+ if (kernel_size >= 0) {
48
@@ -XXX,XX +XXX,XX @@ static void gen_fcvtxn_sd(TCGv_i64 d, TCGv_i64 n)
74
+ image_low_addr = entry;
49
* with von Neumann rounding (round to odd)
75
+ image_high_addr = image_low_addr + kernel_size;
76
+ }
77
}
78
if (kernel_size < 0) {
79
error_report("could not load kernel '%s'", info->kernel_filename);
80
@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
81
* we might still make a bad choice here.
82
*/
50
*/
83
info->initrd_start = info->loader_start +
51
TCGv_i32 tmp = tcg_temp_new_i32();
84
- MAX(MIN(info->ram_size / 2, 128 * 1024 * 1024), kernel_size);
52
- gen_helper_fcvtx_f64_to_f32(tmp, n, tcg_env);
85
+ MIN(info->ram_size / 2, 128 * 1024 * 1024);
53
+ gen_helper_fcvtx_f64_to_f32(tmp, n, fpstatus_ptr(FPST_FPCR));
86
+ if (image_high_addr) {
54
tcg_gen_extu_i32_i64(d, tmp);
87
+ info->initrd_start = MAX(info->initrd_start, image_high_addr);
55
}
88
+ }
56
89
info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start);
90
91
if (is_linux) {
92
--
57
--
93
2.20.1
58
2.34.1
94
59
95
60
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/5] pl330: fix vmstate description
[PULL 11/19] target/arm: Use float_status in helper_vfp_fcvt{ds,sd}
1
From: Damien Hedde <damien.hedde@greensocs.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Fix the pl330 main and queue vmstate description.
3
Pass float_status not env to match other functions.
4
There were missing POINTER flags causing crashes during
5
incoming migration because:
6
+ PL330State chan field is a pointer to an array
7
+ PL330Queue queue field is a pointer to an array
8
4
9
Also bump corresponding vmsd version numbers.
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
7
Message-id: 20241206031952.78776-3-richard.henderson@linaro.org
12
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
13
Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
14
Message-id: 20190724143553.21557-1-damien.hedde@greensocs.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
9
---
17
hw/dma/pl330.c | 17 +++++++++--------
10
target/arm/helper.h | 4 ++--
18
1 file changed, 9 insertions(+), 8 deletions(-)
11
target/arm/tcg/translate-a64.c | 15 ++++++++++-----
12
target/arm/tcg/translate-vfp.c | 4 ++--
13
target/arm/vfp_helper.c | 8 ++++----
14
4 files changed, 18 insertions(+), 13 deletions(-)
19
15
20
diff --git a/hw/dma/pl330.c b/hw/dma/pl330.c
16
diff --git a/target/arm/helper.h b/target/arm/helper.h
21
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/dma/pl330.c
18
--- a/target/arm/helper.h
23
+++ b/hw/dma/pl330.c
19
+++ b/target/arm/helper.h
24
@@ -XXX,XX +XXX,XX @@ typedef struct PL330Queue {
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_cmpeh, void, f16, f16, env)
25
21
DEF_HELPER_3(vfp_cmpes, void, f32, f32, env)
26
static const VMStateDescription vmstate_pl330_queue = {
22
DEF_HELPER_3(vfp_cmped, void, f64, f64, env)
27
.name = "pl330_queue",
23
28
- .version_id = 1,
24
-DEF_HELPER_2(vfp_fcvtds, f64, f32, env)
29
- .minimum_version_id = 1,
25
-DEF_HELPER_2(vfp_fcvtsd, f32, f64, env)
30
+ .version_id = 2,
26
+DEF_HELPER_2(vfp_fcvtds, f64, f32, fpst)
31
+ .minimum_version_id = 2,
27
+DEF_HELPER_2(vfp_fcvtsd, f32, f64, fpst)
32
.fields = (VMStateField[]) {
28
DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, fpst)
33
- VMSTATE_STRUCT_VARRAY_UINT32(queue, PL330Queue, queue_size, 1,
29
DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, fpst)
34
- vmstate_pl330_queue_entry, PL330QueueEntry),
30
35
+ VMSTATE_STRUCT_VARRAY_POINTER_UINT32(queue, PL330Queue, queue_size,
31
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
36
+ vmstate_pl330_queue_entry,
32
index XXXXXXX..XXXXXXX 100644
37
+ PL330QueueEntry),
33
--- a/target/arm/tcg/translate-a64.c
38
VMSTATE_END_OF_LIST()
34
+++ b/target/arm/tcg/translate-a64.c
35
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVT_s_ds(DisasContext *s, arg_rr *a)
36
if (fp_access_check(s)) {
37
TCGv_i32 tcg_rn = read_fp_sreg(s, a->rn);
38
TCGv_i64 tcg_rd = tcg_temp_new_i64();
39
+ TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
40
41
- gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, tcg_env);
42
+ gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, fpst);
43
write_fp_dreg(s, a->rd, tcg_rd);
39
}
44
}
40
};
45
return true;
41
@@ -XXX,XX +XXX,XX @@ struct PL330State {
46
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVT_s_sd(DisasContext *s, arg_rr *a)
42
47
if (fp_access_check(s)) {
43
static const VMStateDescription vmstate_pl330 = {
48
TCGv_i64 tcg_rn = read_fp_dreg(s, a->rn);
44
.name = "pl330",
49
TCGv_i32 tcg_rd = tcg_temp_new_i32();
45
- .version_id = 1,
50
+ TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
46
- .minimum_version_id = 1,
51
47
+ .version_id = 2,
52
- gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, tcg_env);
48
+ .minimum_version_id = 2,
53
+ gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, fpst);
49
.fields = (VMStateField[]) {
54
write_fp_sreg(s, a->rd, tcg_rd);
50
VMSTATE_STRUCT(manager, PL330State, 0, vmstate_pl330_chan, PL330Chan),
55
}
51
- VMSTATE_STRUCT_VARRAY_UINT32(chan, PL330State, num_chnls, 0,
56
return true;
52
- vmstate_pl330_chan, PL330Chan),
57
@@ -XXX,XX +XXX,XX @@ static void gen_fcvtn_hs(TCGv_i64 d, TCGv_i64 n)
53
+ VMSTATE_STRUCT_VARRAY_POINTER_UINT32(chan, PL330State, num_chnls,
58
static void gen_fcvtn_sd(TCGv_i64 d, TCGv_i64 n)
54
+ vmstate_pl330_chan, PL330Chan),
59
{
55
VMSTATE_VBUFFER_UINT32(lo_seqn, PL330State, 1, NULL, num_chnls),
60
TCGv_i32 tmp = tcg_temp_new_i32();
56
VMSTATE_VBUFFER_UINT32(hi_seqn, PL330State, 1, NULL, num_chnls),
61
- gen_helper_vfp_fcvtsd(tmp, n, tcg_env);
57
VMSTATE_STRUCT(fifo, PL330State, 0, vmstate_pl330_fifo, PL330Fifo),
62
+ TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
63
+
64
+ gen_helper_vfp_fcvtsd(tmp, n, fpst);
65
tcg_gen_extu_i32_i64(d, tmp);
66
}
67
68
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
69
* The only instruction like this is FCVTL.
70
*/
71
int pass;
72
+ TCGv_ptr fpst;
73
74
if (!fp_access_check(s)) {
75
return true;
76
}
77
78
+ fpst = fpstatus_ptr(FPST_FPCR);
79
if (a->esz == MO_64) {
80
/* 32 -> 64 bit fp conversion */
81
TCGv_i64 tcg_res[2];
82
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
83
for (pass = 0; pass < 2; pass++) {
84
tcg_res[pass] = tcg_temp_new_i64();
85
read_vec_element_i32(s, tcg_op, a->rn, srcelt + pass, MO_32);
86
- gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, tcg_env);
87
+ gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, fpst);
88
}
89
for (pass = 0; pass < 2; pass++) {
90
write_vec_element(s, tcg_res[pass], a->rd, pass, MO_64);
91
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
92
/* 16 -> 32 bit fp conversion */
93
int srcelt = a->q ? 4 : 0;
94
TCGv_i32 tcg_res[4];
95
- TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
96
TCGv_i32 ahp = get_ahp_flag();
97
98
for (pass = 0; pass < 4; pass++) {
99
diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/target/arm/tcg/translate-vfp.c
102
+++ b/target/arm/tcg/translate-vfp.c
103
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
104
vm = tcg_temp_new_i32();
105
vd = tcg_temp_new_i64();
106
vfp_load_reg32(vm, a->vm);
107
- gen_helper_vfp_fcvtds(vd, vm, tcg_env);
108
+ gen_helper_vfp_fcvtds(vd, vm, fpstatus_ptr(FPST_FPCR));
109
vfp_store_reg64(vd, a->vd);
110
return true;
111
}
112
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
113
vd = tcg_temp_new_i32();
114
vm = tcg_temp_new_i64();
115
vfp_load_reg64(vm, a->vm);
116
- gen_helper_vfp_fcvtsd(vd, vm, tcg_env);
117
+ gen_helper_vfp_fcvtsd(vd, vm, fpstatus_ptr(FPST_FPCR));
118
vfp_store_reg32(vd, a->vd);
119
return true;
120
}
121
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
122
index XXXXXXX..XXXXXXX 100644
123
--- a/target/arm/vfp_helper.c
124
+++ b/target/arm/vfp_helper.c
125
@@ -XXX,XX +XXX,XX @@ FLOAT_CONVS(ui, d, float64, 64, u)
126
#undef FLOAT_CONVS
127
128
/* floating point conversion */
129
-float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
130
+float64 VFP_HELPER(fcvtd, s)(float32 x, float_status *status)
131
{
132
- return float32_to_float64(x, &env->vfp.fp_status);
133
+ return float32_to_float64(x, status);
134
}
135
136
-float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
137
+float32 VFP_HELPER(fcvts, d)(float64 x, float_status *status)
138
{
139
- return float64_to_float32(x, &env->vfp.fp_status);
140
+ return float64_to_float32(x, status);
141
}
142
143
uint32_t HELPER(bfcvt)(float32 x, float_status *status)
58
--
144
--
59
2.20.1
145
2.34.1
60
146
61
147
diff view generated by jsdifflib
New patch
[PULL 12/19] target/arm: Implement fine-grained-trap handling for FEAT_XS
1
FEAT_XS introduces a set of new TLBI maintenance instructions with an
2
"nXS" qualifier. These behave like the stardard ones except that
3
they do not wait for memory accesses with the XS attribute to
4
complete. They have an interaction with the fine-grained-trap
5
handling: the FGT bits that a hypervisor can use to trap TLBI
6
maintenance instructions normally trap also the nXS variants, but the
7
hypervisor can elect to not trap the nXS variants by setting
8
HCRX_EL2.FGTnXS to 1.
1
9
10
Add support to our FGT mechanism for these TLBI bits. For each
11
TLBI-trapping FGT bit we define, for example:
12
* FGT_TLBIVAE1 -- the same value we do at present for the
13
normal variant of the insn
14
* FGT_TLBIVAE1NXS -- for the nXS qualified insn; the value of
15
this enum has an NXS bit ORed into it
16
17
In access_check_cp_reg() we can then ignore the trap bit for an
18
access where ri->fgt has the NXS bit set and HCRX_EL2.FGTnXS is 1.
19
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
22
Message-id: 20241211144440.2700268-2-peter.maydell@linaro.org
23
---
24
target/arm/cpregs.h | 72 ++++++++++++++++++++++----------------
25
target/arm/cpu-features.h | 5 +++
26
target/arm/helper.c | 5 ++-
27
target/arm/tcg/op_helper.c | 11 +++++-
28
4 files changed, 61 insertions(+), 32 deletions(-)
29
30
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/cpregs.h
33
+++ b/target/arm/cpregs.h
34
@@ -XXX,XX +XXX,XX @@ FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1)
35
FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1)
36
FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1)
37
38
+FIELD(FGT, NXS, 13, 1) /* Honour HCR_EL2.FGTnXS to suppress FGT */
39
/* Which fine-grained trap bit register to check, if any */
40
FIELD(FGT, TYPE, 10, 3)
41
FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */
42
@@ -XXX,XX +XXX,XX @@ FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */
43
#define DO_REV_BIT(REG, BITNAME) \
44
FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT
45
46
+/*
47
+ * The FGT bits for TLBI maintenance instructions accessible at EL1 always
48
+ * affect the "normal" TLBI insns; they affect the corresponding TLBI insns
49
+ * with the nXS qualifier only if HCRX_EL2.FGTnXS is 0. We define e.g.
50
+ * FGT_TLBIVAE1 to use for the normal insn, and FGT_TLBIVAE1NXS to use
51
+ * for the nXS qualified insn.
52
+ */
53
+#define DO_TLBINXS_BIT(REG, BITNAME) \
54
+ FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT, \
55
+ FGT_##BITNAME##NXS = FGT_##BITNAME | R_FGT_NXS_MASK
56
+
57
typedef enum FGTBit {
58
/*
59
* These bits tell us which register arrays to use:
60
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
61
DO_BIT(HFGITR, ATS1E0W),
62
DO_BIT(HFGITR, ATS1E1RP),
63
DO_BIT(HFGITR, ATS1E1WP),
64
- DO_BIT(HFGITR, TLBIVMALLE1OS),
65
- DO_BIT(HFGITR, TLBIVAE1OS),
66
- DO_BIT(HFGITR, TLBIASIDE1OS),
67
- DO_BIT(HFGITR, TLBIVAAE1OS),
68
- DO_BIT(HFGITR, TLBIVALE1OS),
69
- DO_BIT(HFGITR, TLBIVAALE1OS),
70
- DO_BIT(HFGITR, TLBIRVAE1OS),
71
- DO_BIT(HFGITR, TLBIRVAAE1OS),
72
- DO_BIT(HFGITR, TLBIRVALE1OS),
73
- DO_BIT(HFGITR, TLBIRVAALE1OS),
74
- DO_BIT(HFGITR, TLBIVMALLE1IS),
75
- DO_BIT(HFGITR, TLBIVAE1IS),
76
- DO_BIT(HFGITR, TLBIASIDE1IS),
77
- DO_BIT(HFGITR, TLBIVAAE1IS),
78
- DO_BIT(HFGITR, TLBIVALE1IS),
79
- DO_BIT(HFGITR, TLBIVAALE1IS),
80
- DO_BIT(HFGITR, TLBIRVAE1IS),
81
- DO_BIT(HFGITR, TLBIRVAAE1IS),
82
- DO_BIT(HFGITR, TLBIRVALE1IS),
83
- DO_BIT(HFGITR, TLBIRVAALE1IS),
84
- DO_BIT(HFGITR, TLBIRVAE1),
85
- DO_BIT(HFGITR, TLBIRVAAE1),
86
- DO_BIT(HFGITR, TLBIRVALE1),
87
- DO_BIT(HFGITR, TLBIRVAALE1),
88
- DO_BIT(HFGITR, TLBIVMALLE1),
89
- DO_BIT(HFGITR, TLBIVAE1),
90
- DO_BIT(HFGITR, TLBIASIDE1),
91
- DO_BIT(HFGITR, TLBIVAAE1),
92
- DO_BIT(HFGITR, TLBIVALE1),
93
- DO_BIT(HFGITR, TLBIVAALE1),
94
+ DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1OS),
95
+ DO_TLBINXS_BIT(HFGITR, TLBIVAE1OS),
96
+ DO_TLBINXS_BIT(HFGITR, TLBIASIDE1OS),
97
+ DO_TLBINXS_BIT(HFGITR, TLBIVAAE1OS),
98
+ DO_TLBINXS_BIT(HFGITR, TLBIVALE1OS),
99
+ DO_TLBINXS_BIT(HFGITR, TLBIVAALE1OS),
100
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAE1OS),
101
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1OS),
102
+ DO_TLBINXS_BIT(HFGITR, TLBIRVALE1OS),
103
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1OS),
104
+ DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1IS),
105
+ DO_TLBINXS_BIT(HFGITR, TLBIVAE1IS),
106
+ DO_TLBINXS_BIT(HFGITR, TLBIASIDE1IS),
107
+ DO_TLBINXS_BIT(HFGITR, TLBIVAAE1IS),
108
+ DO_TLBINXS_BIT(HFGITR, TLBIVALE1IS),
109
+ DO_TLBINXS_BIT(HFGITR, TLBIVAALE1IS),
110
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAE1IS),
111
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1IS),
112
+ DO_TLBINXS_BIT(HFGITR, TLBIRVALE1IS),
113
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1IS),
114
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAE1),
115
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1),
116
+ DO_TLBINXS_BIT(HFGITR, TLBIRVALE1),
117
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1),
118
+ DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1),
119
+ DO_TLBINXS_BIT(HFGITR, TLBIVAE1),
120
+ DO_TLBINXS_BIT(HFGITR, TLBIASIDE1),
121
+ DO_TLBINXS_BIT(HFGITR, TLBIVAAE1),
122
+ DO_TLBINXS_BIT(HFGITR, TLBIVALE1),
123
+ DO_TLBINXS_BIT(HFGITR, TLBIVAALE1),
124
DO_BIT(HFGITR, CFPRCTX),
125
DO_BIT(HFGITR, DVPRCTX),
126
DO_BIT(HFGITR, CPPRCTX),
127
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
128
index XXXXXXX..XXXXXXX 100644
129
--- a/target/arm/cpu-features.h
130
+++ b/target/arm/cpu-features.h
131
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
132
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
133
}
134
135
+static inline bool isar_feature_aa64_xs(const ARMISARegisters *id)
136
+{
137
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, XS) != 0;
138
+}
139
+
140
/*
141
* These are the values from APA/API/APA3.
142
* In general these must be compared '>=', per the normal Arm ARM
143
diff --git a/target/arm/helper.c b/target/arm/helper.c
144
index XXXXXXX..XXXXXXX 100644
145
--- a/target/arm/helper.c
146
+++ b/target/arm/helper.c
147
@@ -XXX,XX +XXX,XX @@ static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri,
148
valid_mask |= HCRX_TALLINT | HCRX_VINMI | HCRX_VFNMI;
149
}
150
/* FEAT_CMOW adds CMOW */
151
-
152
if (cpu_isar_feature(aa64_cmow, cpu)) {
153
valid_mask |= HCRX_CMOW;
154
}
155
+ /* FEAT_XS adds FGTnXS, FnXS */
156
+ if (cpu_isar_feature(aa64_xs, cpu)) {
157
+ valid_mask |= HCRX_FGTNXS | HCRX_FNXS;
158
+ }
159
160
/* Clear RES0 bits. */
161
env->cp15.hcrx_el2 = value & valid_mask;
162
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
163
index XXXXXXX..XXXXXXX 100644
164
--- a/target/arm/tcg/op_helper.c
165
+++ b/target/arm/tcg/op_helper.c
166
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
167
unsigned int idx = FIELD_EX32(ri->fgt, FGT, IDX);
168
unsigned int bitpos = FIELD_EX32(ri->fgt, FGT, BITPOS);
169
bool rev = FIELD_EX32(ri->fgt, FGT, REV);
170
+ bool nxs = FIELD_EX32(ri->fgt, FGT, NXS);
171
bool trapbit;
172
173
if (ri->fgt & FGT_EXEC) {
174
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
175
trapword = env->cp15.fgt_write[idx];
176
}
177
178
- trapbit = extract64(trapword, bitpos, 1);
179
+ if (nxs && (arm_hcrx_el2_eff(env) & HCRX_FGTNXS)) {
180
+ /*
181
+ * If HCRX_EL2.FGTnXS is 1 then the fine-grained trap for
182
+ * TLBI maintenance insns does *not* apply to the nXS variant.
183
+ */
184
+ trapbit = 0;
185
+ } else {
186
+ trapbit = extract64(trapword, bitpos, 1);
187
+ }
188
if (trapbit != rev) {
189
res = CP_ACCESS_TRAP_EL2;
190
goto fail;
191
--
192
2.34.1
diff view generated by jsdifflib
New patch
[PULL 13/19] target/arm: Add ARM_CP_ADD_TLBI_NXS type flag for NXS insns
1
All of the TLBI insns with an NXS variant put that variant at the
2
same encoding but with a CRn field that is one greater than for the
3
original TLBI insn. To avoid having to define every TLBI insn
4
effectively twice, once in the normal way and once in a set of cpreg
5
arrays that are only registered when FEAT_XS is present, we define a
6
new ARM_CP_ADD_TLB_NXS type flag for cpregs. When this flag is set
7
in a cpreg struct and FEAT_XS is present,
8
define_one_arm_cp_reg_with_opaque() will automatically add a second
9
cpreg to the hash table for the TLBI NXS insn with:
10
* the crn+1 encoding
11
* an FGT field that indicates that it should honour HCR_EL2.FGTnXS
12
* a name with the "NXS" suffix
1
13
14
(If there are future TLBI NXS insns that don't use this same
15
encoding convention, it is also possible to define them manually.)
16
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20241211144440.2700268-3-peter.maydell@linaro.org
20
---
21
target/arm/cpregs.h | 8 ++++++++
22
target/arm/helper.c | 25 +++++++++++++++++++++++++
23
2 files changed, 33 insertions(+)
24
25
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/cpregs.h
28
+++ b/target/arm/cpregs.h
29
@@ -XXX,XX +XXX,XX @@ enum {
30
* equivalent EL1 register when FEAT_NV2 is enabled.
31
*/
32
ARM_CP_NV2_REDIRECT = 1 << 20,
33
+ /*
34
+ * Flag: this is a TLBI insn which (when FEAT_XS is present) also has
35
+ * an NXS variant at the same encoding except that crn is 1 greater,
36
+ * so when registering this cpreg automatically also register one
37
+ * for the TLBI NXS variant. (For QEMU the NXS variant behaves
38
+ * identically to the normal one, other than FGT trapping handling.)
39
+ */
40
+ ARM_CP_ADD_TLBI_NXS = 1 << 21,
41
};
42
43
/*
44
diff --git a/target/arm/helper.c b/target/arm/helper.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/helper.c
47
+++ b/target/arm/helper.c
48
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
49
if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
50
continue;
51
}
52
+ if ((r->type & ARM_CP_ADD_TLBI_NXS) &&
53
+ cpu_isar_feature(aa64_xs, cpu)) {
54
+ /*
55
+ * This is a TLBI insn which has an NXS variant. The
56
+ * NXS variant is at the same encoding except that
57
+ * crn is +1, and has the same behaviour except for
58
+ * fine-grained trapping. Add the NXS insn here and
59
+ * then fall through to add the normal register.
60
+ * add_cpreg_to_hashtable() copies the cpreg struct
61
+ * and name that it is passed, so it's OK to use
62
+ * a local struct here.
63
+ */
64
+ ARMCPRegInfo nxs_ri = *r;
65
+ g_autofree char *name = g_strdup_printf("%sNXS", r->name);
66
+
67
+ assert(state == ARM_CP_STATE_AA64);
68
+ assert(nxs_ri.crn < 0xf);
69
+ nxs_ri.crn++;
70
+ if (nxs_ri.fgt) {
71
+ nxs_ri.fgt |= R_FGT_NXS_MASK;
72
+ }
73
+ add_cpreg_to_hashtable(cpu, &nxs_ri, opaque, state,
74
+ ARM_CP_SECSTATE_NS,
75
+ crm, opc1, opc2, name);
76
+ }
77
if (state == ARM_CP_STATE_AA32) {
78
/*
79
* Under AArch32 CP registers can be common
80
--
81
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/19] target/arm: Add ARM_CP_ADD_TLBI_NXS type flag to TLBI insns
1
Add the ARM_CP_ADD_TLBI_NXS to the TLBI insns with an NXS variant.
2
This is every AArch64 TLBI encoding except for the four FEAT_RME TLBI
3
insns.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241211144440.2700268-4-peter.maydell@linaro.org
8
---
9
target/arm/tcg/tlb-insns.c | 202 +++++++++++++++++++++++--------------
10
1 file changed, 124 insertions(+), 78 deletions(-)
11
12
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/tcg/tlb-insns.c
15
+++ b/target/arm/tcg/tlb-insns.c
16
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbi_v8_cp_reginfo[] = {
17
/* AArch64 TLBI operations */
18
{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
19
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
20
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
21
+ .access = PL1_W, .accessfn = access_ttlbis,
22
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
23
.fgt = FGT_TLBIVMALLE1IS,
24
.writefn = tlbi_aa64_vmalle1is_write },
25
{ .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
26
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
27
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
28
+ .access = PL1_W, .accessfn = access_ttlbis,
29
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
30
.fgt = FGT_TLBIVAE1IS,
31
.writefn = tlbi_aa64_vae1is_write },
32
{ .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
33
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
34
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
35
+ .access = PL1_W, .accessfn = access_ttlbis,
36
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
37
.fgt = FGT_TLBIASIDE1IS,
38
.writefn = tlbi_aa64_vmalle1is_write },
39
{ .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
40
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
41
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
42
+ .access = PL1_W, .accessfn = access_ttlbis,
43
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
44
.fgt = FGT_TLBIVAAE1IS,
45
.writefn = tlbi_aa64_vae1is_write },
46
{ .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
47
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
48
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
49
+ .access = PL1_W, .accessfn = access_ttlbis,
50
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
51
.fgt = FGT_TLBIVALE1IS,
52
.writefn = tlbi_aa64_vae1is_write },
53
{ .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
54
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
55
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
56
+ .access = PL1_W, .accessfn = access_ttlbis,
57
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
58
.fgt = FGT_TLBIVAALE1IS,
59
.writefn = tlbi_aa64_vae1is_write },
60
{ .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
61
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
62
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
63
+ .access = PL1_W, .accessfn = access_ttlb,
64
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
65
.fgt = FGT_TLBIVMALLE1,
66
.writefn = tlbi_aa64_vmalle1_write },
67
{ .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
68
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
69
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
70
+ .access = PL1_W, .accessfn = access_ttlb,
71
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
72
.fgt = FGT_TLBIVAE1,
73
.writefn = tlbi_aa64_vae1_write },
74
{ .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
75
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
76
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
77
+ .access = PL1_W, .accessfn = access_ttlb,
78
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
79
.fgt = FGT_TLBIASIDE1,
80
.writefn = tlbi_aa64_vmalle1_write },
81
{ .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
82
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
83
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
84
+ .access = PL1_W, .accessfn = access_ttlb,
85
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
86
.fgt = FGT_TLBIVAAE1,
87
.writefn = tlbi_aa64_vae1_write },
88
{ .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
89
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
90
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
91
+ .access = PL1_W, .accessfn = access_ttlb,
92
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
93
.fgt = FGT_TLBIVALE1,
94
.writefn = tlbi_aa64_vae1_write },
95
{ .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
96
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
97
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
98
+ .access = PL1_W, .accessfn = access_ttlb,
99
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
100
.fgt = FGT_TLBIVAALE1,
101
.writefn = tlbi_aa64_vae1_write },
102
{ .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
103
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
104
- .access = PL2_W, .type = ARM_CP_NO_RAW,
105
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
106
.writefn = tlbi_aa64_ipas2e1is_write },
107
{ .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
108
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
109
- .access = PL2_W, .type = ARM_CP_NO_RAW,
110
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
111
.writefn = tlbi_aa64_ipas2e1is_write },
112
{ .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
113
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
114
- .access = PL2_W, .type = ARM_CP_NO_RAW,
115
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
116
.writefn = tlbi_aa64_alle1is_write },
117
{ .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
118
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
119
- .access = PL2_W, .type = ARM_CP_NO_RAW,
120
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
121
.writefn = tlbi_aa64_alle1is_write },
122
{ .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
123
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
124
- .access = PL2_W, .type = ARM_CP_NO_RAW,
125
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
126
.writefn = tlbi_aa64_ipas2e1_write },
127
{ .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
128
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
129
- .access = PL2_W, .type = ARM_CP_NO_RAW,
130
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
131
.writefn = tlbi_aa64_ipas2e1_write },
132
{ .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
133
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
134
- .access = PL2_W, .type = ARM_CP_NO_RAW,
135
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
136
.writefn = tlbi_aa64_alle1_write },
137
{ .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
138
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
139
- .access = PL2_W, .type = ARM_CP_NO_RAW,
140
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
141
.writefn = tlbi_aa64_alle1is_write },
142
};
143
144
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbi_el2_cp_reginfo[] = {
145
.writefn = tlbimva_hyp_is_write },
146
{ .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
147
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
148
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
149
+ .access = PL2_W,
150
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
151
.writefn = tlbi_aa64_alle2_write },
152
{ .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
153
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
154
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
155
+ .access = PL2_W,
156
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
157
.writefn = tlbi_aa64_vae2_write },
158
{ .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
159
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
160
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
161
+ .access = PL2_W,
162
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
163
.writefn = tlbi_aa64_vae2_write },
164
{ .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
165
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
166
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
167
+ .access = PL2_W,
168
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
169
.writefn = tlbi_aa64_alle2is_write },
170
{ .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
171
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
172
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
173
+ .access = PL2_W,
174
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
175
.writefn = tlbi_aa64_vae2is_write },
176
{ .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
177
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
178
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
179
+ .access = PL2_W,
180
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
181
.writefn = tlbi_aa64_vae2is_write },
182
};
183
184
static const ARMCPRegInfo tlbi_el3_cp_reginfo[] = {
185
{ .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
186
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
187
- .access = PL3_W, .type = ARM_CP_NO_RAW,
188
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
189
.writefn = tlbi_aa64_alle3is_write },
190
{ .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
191
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
192
- .access = PL3_W, .type = ARM_CP_NO_RAW,
193
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
194
.writefn = tlbi_aa64_vae3is_write },
195
{ .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
196
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
197
- .access = PL3_W, .type = ARM_CP_NO_RAW,
198
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
199
.writefn = tlbi_aa64_vae3is_write },
200
{ .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
201
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
202
- .access = PL3_W, .type = ARM_CP_NO_RAW,
203
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
204
.writefn = tlbi_aa64_alle3_write },
205
{ .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
206
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
207
- .access = PL3_W, .type = ARM_CP_NO_RAW,
208
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
209
.writefn = tlbi_aa64_vae3_write },
210
{ .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
211
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
212
- .access = PL3_W, .type = ARM_CP_NO_RAW,
213
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
214
.writefn = tlbi_aa64_vae3_write },
215
};
216
217
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_ripas2e1is_write(CPUARMState *env,
218
static const ARMCPRegInfo tlbirange_reginfo[] = {
219
{ .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
220
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
221
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
222
+ .access = PL1_W, .accessfn = access_ttlbis,
223
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
224
.fgt = FGT_TLBIRVAE1IS,
225
.writefn = tlbi_aa64_rvae1is_write },
226
{ .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
227
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
228
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
229
+ .access = PL1_W, .accessfn = access_ttlbis,
230
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
231
.fgt = FGT_TLBIRVAAE1IS,
232
.writefn = tlbi_aa64_rvae1is_write },
233
{ .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
234
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
235
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
236
+ .access = PL1_W, .accessfn = access_ttlbis,
237
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
238
.fgt = FGT_TLBIRVALE1IS,
239
.writefn = tlbi_aa64_rvae1is_write },
240
{ .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
241
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
242
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
243
+ .access = PL1_W, .accessfn = access_ttlbis,
244
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
245
.fgt = FGT_TLBIRVAALE1IS,
246
.writefn = tlbi_aa64_rvae1is_write },
247
{ .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
248
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
249
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
250
+ .access = PL1_W, .accessfn = access_ttlbos,
251
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
252
.fgt = FGT_TLBIRVAE1OS,
253
.writefn = tlbi_aa64_rvae1is_write },
254
{ .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64,
255
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
256
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
257
+ .access = PL1_W, .accessfn = access_ttlbos,
258
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
259
.fgt = FGT_TLBIRVAAE1OS,
260
.writefn = tlbi_aa64_rvae1is_write },
261
{ .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64,
262
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5,
263
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
264
+ .access = PL1_W, .accessfn = access_ttlbos,
265
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
266
.fgt = FGT_TLBIRVALE1OS,
267
.writefn = tlbi_aa64_rvae1is_write },
268
{ .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64,
269
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7,
270
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
271
+ .access = PL1_W, .accessfn = access_ttlbos,
272
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
273
.fgt = FGT_TLBIRVAALE1OS,
274
.writefn = tlbi_aa64_rvae1is_write },
275
{ .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64,
276
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
277
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
278
+ .access = PL1_W, .accessfn = access_ttlb,
279
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
280
.fgt = FGT_TLBIRVAE1,
281
.writefn = tlbi_aa64_rvae1_write },
282
{ .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64,
283
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3,
284
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
285
+ .access = PL1_W, .accessfn = access_ttlb,
286
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
287
.fgt = FGT_TLBIRVAAE1,
288
.writefn = tlbi_aa64_rvae1_write },
289
{ .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64,
290
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5,
291
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
292
+ .access = PL1_W, .accessfn = access_ttlb,
293
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
294
.fgt = FGT_TLBIRVALE1,
295
.writefn = tlbi_aa64_rvae1_write },
296
{ .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64,
297
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7,
298
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
299
+ .access = PL1_W, .accessfn = access_ttlb,
300
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
301
.fgt = FGT_TLBIRVAALE1,
302
.writefn = tlbi_aa64_rvae1_write },
303
{ .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64,
304
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2,
305
- .access = PL2_W, .type = ARM_CP_NO_RAW,
306
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
307
.writefn = tlbi_aa64_ripas2e1is_write },
308
{ .name = "TLBI_RIPAS2LE1IS", .state = ARM_CP_STATE_AA64,
309
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 6,
310
- .access = PL2_W, .type = ARM_CP_NO_RAW,
311
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
312
.writefn = tlbi_aa64_ripas2e1is_write },
313
{ .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
314
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
315
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
316
+ .access = PL2_W,
317
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
318
.writefn = tlbi_aa64_rvae2is_write },
319
{ .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64,
320
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5,
321
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
322
+ .access = PL2_W,
323
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
324
.writefn = tlbi_aa64_rvae2is_write },
325
{ .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
326
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
327
- .access = PL2_W, .type = ARM_CP_NO_RAW,
328
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
329
.writefn = tlbi_aa64_ripas2e1_write },
330
{ .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64,
331
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 6,
332
- .access = PL2_W, .type = ARM_CP_NO_RAW,
333
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
334
.writefn = tlbi_aa64_ripas2e1_write },
335
{ .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
336
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
337
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
338
+ .access = PL2_W,
339
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
340
.writefn = tlbi_aa64_rvae2is_write },
341
{ .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64,
342
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5,
343
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
344
+ .access = PL2_W,
345
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
346
.writefn = tlbi_aa64_rvae2is_write },
347
{ .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64,
348
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1,
349
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
350
+ .access = PL2_W,
351
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
352
.writefn = tlbi_aa64_rvae2_write },
353
{ .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64,
354
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5,
355
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
356
+ .access = PL2_W,
357
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
358
.writefn = tlbi_aa64_rvae2_write },
359
{ .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
360
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
361
- .access = PL3_W, .type = ARM_CP_NO_RAW,
362
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
363
.writefn = tlbi_aa64_rvae3is_write },
364
{ .name = "TLBI_RVALE3IS", .state = ARM_CP_STATE_AA64,
365
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 5,
366
- .access = PL3_W, .type = ARM_CP_NO_RAW,
367
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
368
.writefn = tlbi_aa64_rvae3is_write },
369
{ .name = "TLBI_RVAE3OS", .state = ARM_CP_STATE_AA64,
370
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 1,
371
- .access = PL3_W, .type = ARM_CP_NO_RAW,
372
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
373
.writefn = tlbi_aa64_rvae3is_write },
374
{ .name = "TLBI_RVALE3OS", .state = ARM_CP_STATE_AA64,
375
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 5,
376
- .access = PL3_W, .type = ARM_CP_NO_RAW,
377
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
378
.writefn = tlbi_aa64_rvae3is_write },
379
{ .name = "TLBI_RVAE3", .state = ARM_CP_STATE_AA64,
380
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 1,
381
- .access = PL3_W, .type = ARM_CP_NO_RAW,
382
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
383
.writefn = tlbi_aa64_rvae3_write },
384
{ .name = "TLBI_RVALE3", .state = ARM_CP_STATE_AA64,
385
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5,
386
- .access = PL3_W, .type = ARM_CP_NO_RAW,
387
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
388
.writefn = tlbi_aa64_rvae3_write },
389
};
390
391
static const ARMCPRegInfo tlbios_reginfo[] = {
392
{ .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
393
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
394
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
395
+ .access = PL1_W, .accessfn = access_ttlbos,
396
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
397
.fgt = FGT_TLBIVMALLE1OS,
398
.writefn = tlbi_aa64_vmalle1is_write },
399
{ .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64,
400
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1,
401
.fgt = FGT_TLBIVAE1OS,
402
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
403
+ .access = PL1_W, .accessfn = access_ttlbos,
404
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
405
.writefn = tlbi_aa64_vae1is_write },
406
{ .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
407
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
408
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
409
+ .access = PL1_W, .accessfn = access_ttlbos,
410
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
411
.fgt = FGT_TLBIASIDE1OS,
412
.writefn = tlbi_aa64_vmalle1is_write },
413
{ .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64,
414
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
415
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
416
+ .access = PL1_W, .accessfn = access_ttlbos,
417
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
418
.fgt = FGT_TLBIVAAE1OS,
419
.writefn = tlbi_aa64_vae1is_write },
420
{ .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64,
421
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5,
422
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
423
+ .access = PL1_W, .accessfn = access_ttlbos,
424
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
425
.fgt = FGT_TLBIVALE1OS,
426
.writefn = tlbi_aa64_vae1is_write },
427
{ .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64,
428
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7,
429
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
430
+ .access = PL1_W, .accessfn = access_ttlbos,
431
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
432
.fgt = FGT_TLBIVAALE1OS,
433
.writefn = tlbi_aa64_vae1is_write },
434
{ .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
435
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
436
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
437
+ .access = PL2_W,
438
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
439
.writefn = tlbi_aa64_alle2is_write },
440
{ .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64,
441
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1,
442
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
443
+ .access = PL2_W,
444
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
445
.writefn = tlbi_aa64_vae2is_write },
446
{ .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64,
447
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4,
448
- .access = PL2_W, .type = ARM_CP_NO_RAW,
449
+ .access = PL2_W,
450
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
451
.writefn = tlbi_aa64_alle1is_write },
452
{ .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64,
453
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5,
454
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
455
+ .access = PL2_W,
456
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
457
.writefn = tlbi_aa64_vae2is_write },
458
{ .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64,
459
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6,
460
- .access = PL2_W, .type = ARM_CP_NO_RAW,
461
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
462
.writefn = tlbi_aa64_alle1is_write },
463
{ .name = "TLBI_IPAS2E1OS", .state = ARM_CP_STATE_AA64,
464
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 0,
465
- .access = PL2_W, .type = ARM_CP_NOP },
466
+ .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
467
{ .name = "TLBI_RIPAS2E1OS", .state = ARM_CP_STATE_AA64,
468
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 3,
469
- .access = PL2_W, .type = ARM_CP_NOP },
470
+ .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
471
{ .name = "TLBI_IPAS2LE1OS", .state = ARM_CP_STATE_AA64,
472
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 4,
473
- .access = PL2_W, .type = ARM_CP_NOP },
474
+ .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
475
{ .name = "TLBI_RIPAS2LE1OS", .state = ARM_CP_STATE_AA64,
476
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 7,
477
- .access = PL2_W, .type = ARM_CP_NOP },
478
+ .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
479
{ .name = "TLBI_ALLE3OS", .state = ARM_CP_STATE_AA64,
480
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 0,
481
- .access = PL3_W, .type = ARM_CP_NO_RAW,
482
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
483
.writefn = tlbi_aa64_alle3is_write },
484
{ .name = "TLBI_VAE3OS", .state = ARM_CP_STATE_AA64,
485
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 1,
486
- .access = PL3_W, .type = ARM_CP_NO_RAW,
487
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
488
.writefn = tlbi_aa64_vae3is_write },
489
{ .name = "TLBI_VALE3OS", .state = ARM_CP_STATE_AA64,
490
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5,
491
- .access = PL3_W, .type = ARM_CP_NO_RAW,
492
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
493
.writefn = tlbi_aa64_vae3is_write },
494
};
495
496
--
497
2.34.1
diff view generated by jsdifflib
New patch
[PULL 15/19] target/arm: Add decodetree entry for DSB nXS variant
1
From: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
1
2
3
The DSB nXS variant is always both a reads and writes request type.
4
Ignore the domain field like we do in plain DSB and perform a full
5
system barrier operation.
6
7
The DSB nXS variant is part of FEAT_XS made mandatory from Armv8.7.
8
9
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241211144440.2700268-5-peter.maydell@linaro.org
13
[PMM: added missing "UNDEF unless feature present" check]
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
target/arm/tcg/a64.decode | 3 +++
17
target/arm/tcg/translate-a64.c | 9 +++++++++
18
2 files changed, 12 insertions(+)
19
20
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/tcg/a64.decode
23
+++ b/target/arm/tcg/a64.decode
24
@@ -XXX,XX +XXX,XX @@ WFIT 1101 0101 0000 0011 0001 0000 001 rd:5
25
26
CLREX 1101 0101 0000 0011 0011 ---- 010 11111
27
DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111
28
+# For the DSB nXS variant, types always equals MBReqTypes_All and we ignore the
29
+# domain bits.
30
+DSB_nXS 1101 0101 0000 0011 0011 -- 10 001 11111
31
ISB 1101 0101 0000 0011 0011 ---- 110 11111
32
SB 1101 0101 0000 0011 0011 0000 111 11111
33
34
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/tcg/translate-a64.c
37
+++ b/target/arm/tcg/translate-a64.c
38
@@ -XXX,XX +XXX,XX @@ static bool trans_DSB_DMB(DisasContext *s, arg_DSB_DMB *a)
39
return true;
40
}
41
42
+static bool trans_DSB_nXS(DisasContext *s, arg_DSB_nXS *a)
43
+{
44
+ if (!dc_isar_feature(aa64_xs, s)) {
45
+ return false;
46
+ }
47
+ tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
48
+ return true;
49
+}
50
+
51
static bool trans_ISB(DisasContext *s, arg_ISB *a)
52
{
53
/*
54
--
55
2.34.1
diff view generated by jsdifflib
New patch
[PULL 16/19] target/arm: Enable FEAT_XS for the max cpu
1
From: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
1
2
3
Add FEAT_XS feature report value in max cpu's ID_AA64ISAR1 sys register.
4
5
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241211144440.2700268-6-peter.maydell@linaro.org
9
[PMM: Add entry for FEAT_XS to documentation]
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
---
12
docs/system/arm/emulation.rst | 1 +
13
target/arm/tcg/cpu64.c | 1 +
14
2 files changed, 2 insertions(+)
15
16
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
17
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/emulation.rst
19
+++ b/docs/system/arm/emulation.rst
20
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
21
- FEAT_VMID16 (16-bit VMID)
22
- FEAT_WFxT (WFE and WFI instructions with timeout)
23
- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
24
+- FEAT_XS (XS attribute)
25
26
For information on the specifics of these extensions, please refer
27
to the `Arm Architecture Reference Manual for A-profile architecture
28
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/tcg/cpu64.c
31
+++ b/target/arm/tcg/cpu64.c
32
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
33
t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* FEAT_BF16, FEAT_EBF16 */
34
t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
35
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
36
+ t = FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* FEAT_XS */
37
cpu->isar.id_aa64isar1 = t;
38
39
t = cpu->isar.id_aa64isar2;
40
--
41
2.34.1
diff view generated by jsdifflib
New patch
[PULL 17/19] tests/tcg/aarch64: add system test for FEAT_XS
1
From: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
1
2
3
Add system test to make sure FEAT_XS is enabled for max cpu emulation
4
and that QEMU doesn't crash when encountering an NXS instruction
5
variant.
6
7
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20241211144440.2700268-7-peter.maydell@linaro.org
10
[PMM: In ISAR field test, mask with 0xf, not 0xff; use < rather
11
than an equality test to follow the standard ID register field
12
check guidelines]
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
tests/tcg/aarch64/system/feat-xs.c | 27 +++++++++++++++++++++++++++
16
1 file changed, 27 insertions(+)
17
create mode 100644 tests/tcg/aarch64/system/feat-xs.c
18
19
diff --git a/tests/tcg/aarch64/system/feat-xs.c b/tests/tcg/aarch64/system/feat-xs.c
20
new file mode 100644
21
index XXXXXXX..XXXXXXX
22
--- /dev/null
23
+++ b/tests/tcg/aarch64/system/feat-xs.c
24
@@ -XXX,XX +XXX,XX @@
25
+/*
26
+ * FEAT_XS Test
27
+ *
28
+ * Copyright (c) 2024 Linaro Ltd
29
+ *
30
+ * SPDX-License-Identifier: GPL-2.0-or-later
31
+ */
32
+
33
+#include <minilib.h>
34
+#include <stdint.h>
35
+
36
+int main(void)
37
+{
38
+ uint64_t isar1;
39
+
40
+ asm volatile ("mrs %0, id_aa64isar1_el1" : "=r"(isar1));
41
+ if (((isar1 >> 56) & 0xf) < 1) {
42
+ ml_printf("FEAT_XS not supported by CPU");
43
+ return 1;
44
+ }
45
+ /* VMALLE1NXS */
46
+ asm volatile (".inst 0xd508971f");
47
+ /* VMALLE1OSNXS */
48
+ asm volatile (".inst 0xd508911f");
49
+
50
+ return 0;
51
+}
52
--
53
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 2/5] stellaris_input: Fix vmstate description of buttons field
[PULL 18/19] hw/intc/arm_gicv3_its: Zero initialize local DTEntry etc structs
1
gamepad_state::buttons is a pointer to an array of structs,
1
In the GICv3 ITS model, we have a common coding pattern which has a
2
not an array of structs, so should be declared in the vmstate
2
local C struct like "DTEntry dte", which is a C representation of an
3
with VMSTATE_STRUCT_VARRAY_POINTER_INT32; otherwise we
3
in-guest-memory data structure, and we call a function such as
4
corrupt memory on incoming migration.
4
get_dte() to read guest memory and fill in the C struct. These
5
functions to read in the struct sometimes have cases where they will
6
leave early and not fill in the whole struct (for instance get_dte()
7
will set "dte->valid = false" and nothing else for the case where it
8
is passed an entry_addr implying that there is no L2 table entry for
9
the DTE). This then causes potential use of uninitialized memory
10
later, for instance when we call a trace event which prints all the
11
fields of the struct. Sufficiently advanced compilers may produce
12
-Wmaybe-uninitialized warnings about this, especially if LTO is
13
enabled.
5
14
6
We bump the vmstate version field as the easiest way to
15
Rather than trying to carefully separate out these trace events into
7
deal with the migration break, since migration wouldn't have
16
"only the 'valid' field is initialized" and "all fields can be
8
worked reliably before anyway.
17
printed", zero-init all the structs when we define them. None of
18
these structs are large (the biggest is 24 bytes) and having
19
consistent behaviour is less likely to be buggy.
9
20
21
Cc: qemu-stable@nongnu.org
22
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2718
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
25
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
26
Message-id: 20241213182337.3343068-1-peter.maydell@linaro.org
14
Message-id: 20190725163710.11703-2-peter.maydell@linaro.org
15
---
27
---
16
hw/input/stellaris_input.c | 10 ++++++----
28
hw/intc/arm_gicv3_its.c | 44 ++++++++++++++++++++---------------------
17
1 file changed, 6 insertions(+), 4 deletions(-)
29
1 file changed, 22 insertions(+), 22 deletions(-)
18
30
19
diff --git a/hw/input/stellaris_input.c b/hw/input/stellaris_input.c
31
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
20
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/input/stellaris_input.c
33
--- a/hw/intc/arm_gicv3_its.c
22
+++ b/hw/input/stellaris_input.c
34
+++ b/hw/intc/arm_gicv3_its.c
23
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_stellaris_button = {
35
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult lookup_vte(GICv3ITSState *s, const char *who,
24
36
static ItsCmdResult process_its_cmd_phys(GICv3ITSState *s, const ITEntry *ite,
25
static const VMStateDescription vmstate_stellaris_gamepad = {
37
int irqlevel)
26
.name = "stellaris_gamepad",
38
{
27
- .version_id = 1,
39
- CTEntry cte;
28
- .minimum_version_id = 1,
40
+ CTEntry cte = {};
29
+ .version_id = 2,
41
ItsCmdResult cmdres;
30
+ .minimum_version_id = 2,
42
31
.fields = (VMStateField[]) {
43
cmdres = lookup_cte(s, __func__, ite->icid, &cte);
32
VMSTATE_INT32(extension, gamepad_state),
44
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_its_cmd_phys(GICv3ITSState *s, const ITEntry *ite,
33
- VMSTATE_STRUCT_VARRAY_INT32(buttons, gamepad_state, num_buttons, 0,
45
static ItsCmdResult process_its_cmd_virt(GICv3ITSState *s, const ITEntry *ite,
34
- vmstate_stellaris_button, gamepad_button),
46
int irqlevel)
35
+ VMSTATE_STRUCT_VARRAY_POINTER_INT32(buttons, gamepad_state,
47
{
36
+ num_buttons,
48
- VTEntry vte;
37
+ vmstate_stellaris_button,
49
+ VTEntry vte = {};
38
+ gamepad_button),
50
ItsCmdResult cmdres;
39
VMSTATE_END_OF_LIST()
51
40
}
52
cmdres = lookup_vte(s, __func__, ite->vpeid, &vte);
41
};
53
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_its_cmd_virt(GICv3ITSState *s, const ITEntry *ite,
54
static ItsCmdResult do_process_its_cmd(GICv3ITSState *s, uint32_t devid,
55
uint32_t eventid, ItsCmdType cmd)
56
{
57
- DTEntry dte;
58
- ITEntry ite;
59
+ DTEntry dte = {};
60
+ ITEntry ite = {};
61
ItsCmdResult cmdres;
62
int irqlevel;
63
64
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_mapti(GICv3ITSState *s, const uint64_t *cmdpkt,
65
uint32_t pIntid = 0;
66
uint64_t num_eventids;
67
uint16_t icid = 0;
68
- DTEntry dte;
69
- ITEntry ite;
70
+ DTEntry dte = {};
71
+ ITEntry ite = {};
72
73
devid = (cmdpkt[0] & DEVID_MASK) >> DEVID_SHIFT;
74
eventid = cmdpkt[1] & EVENTID_MASK;
75
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_vmapti(GICv3ITSState *s, const uint64_t *cmdpkt,
76
{
77
uint32_t devid, eventid, vintid, doorbell, vpeid;
78
uint32_t num_eventids;
79
- DTEntry dte;
80
- ITEntry ite;
81
+ DTEntry dte = {};
82
+ ITEntry ite = {};
83
84
if (!its_feature_virtual(s)) {
85
return CMD_CONTINUE;
86
@@ -XXX,XX +XXX,XX @@ static bool update_cte(GICv3ITSState *s, uint16_t icid, const CTEntry *cte)
87
static ItsCmdResult process_mapc(GICv3ITSState *s, const uint64_t *cmdpkt)
88
{
89
uint16_t icid;
90
- CTEntry cte;
91
+ CTEntry cte = {};
92
93
icid = cmdpkt[2] & ICID_MASK;
94
cte.valid = cmdpkt[2] & CMD_FIELD_VALID_MASK;
95
@@ -XXX,XX +XXX,XX @@ static bool update_dte(GICv3ITSState *s, uint32_t devid, const DTEntry *dte)
96
static ItsCmdResult process_mapd(GICv3ITSState *s, const uint64_t *cmdpkt)
97
{
98
uint32_t devid;
99
- DTEntry dte;
100
+ DTEntry dte = {};
101
102
devid = (cmdpkt[0] & DEVID_MASK) >> DEVID_SHIFT;
103
dte.size = cmdpkt[1] & SIZE_MASK;
104
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_movi(GICv3ITSState *s, const uint64_t *cmdpkt)
105
{
106
uint32_t devid, eventid;
107
uint16_t new_icid;
108
- DTEntry dte;
109
- CTEntry old_cte, new_cte;
110
- ITEntry old_ite;
111
+ DTEntry dte = {};
112
+ CTEntry old_cte = {}, new_cte = {};
113
+ ITEntry old_ite = {};
114
ItsCmdResult cmdres;
115
116
devid = FIELD_EX64(cmdpkt[0], MOVI_0, DEVICEID);
117
@@ -XXX,XX +XXX,XX @@ static bool update_vte(GICv3ITSState *s, uint32_t vpeid, const VTEntry *vte)
118
119
static ItsCmdResult process_vmapp(GICv3ITSState *s, const uint64_t *cmdpkt)
120
{
121
- VTEntry vte;
122
+ VTEntry vte = {};
123
uint32_t vpeid;
124
125
if (!its_feature_virtual(s)) {
126
@@ -XXX,XX +XXX,XX @@ static void vmovp_callback(gpointer data, gpointer opaque)
127
*/
128
GICv3ITSState *s = data;
129
VmovpCallbackData *cbdata = opaque;
130
- VTEntry vte;
131
+ VTEntry vte = {};
132
ItsCmdResult cmdres;
133
134
cmdres = lookup_vte(s, __func__, cbdata->vpeid, &vte);
135
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_vmovi(GICv3ITSState *s, const uint64_t *cmdpkt)
136
{
137
uint32_t devid, eventid, vpeid, doorbell;
138
bool doorbell_valid;
139
- DTEntry dte;
140
- ITEntry ite;
141
- VTEntry old_vte, new_vte;
142
+ DTEntry dte = {};
143
+ ITEntry ite = {};
144
+ VTEntry old_vte = {}, new_vte = {};
145
ItsCmdResult cmdres;
146
147
if (!its_feature_virtual(s)) {
148
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_vinvall(GICv3ITSState *s, const uint64_t *cmdpkt)
149
static ItsCmdResult process_inv(GICv3ITSState *s, const uint64_t *cmdpkt)
150
{
151
uint32_t devid, eventid;
152
- ITEntry ite;
153
- DTEntry dte;
154
- CTEntry cte;
155
- VTEntry vte;
156
+ ITEntry ite = {};
157
+ DTEntry dte = {};
158
+ CTEntry cte = {};
159
+ VTEntry vte = {};
160
ItsCmdResult cmdres;
161
162
devid = FIELD_EX64(cmdpkt[0], INV_0, DEVICEID);
42
--
163
--
43
2.20.1
164
2.34.1
44
165
45
166
diff view generated by jsdifflib
New patch
[PULL 19/19] tests/functional: update sbsa-ref firmware used in test
1
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
1
2
3
Update the URLs for the binaries we use for the firmware in the
4
sbsa-ref functional tests.
5
6
The firmware is built using Debian 'bookworm' cross toolchain (gcc
7
12.2.0).
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9
Used versions:
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11
- Trusted Firmware v2.12.0
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- Tianocore EDK2 stable202411
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- Tianocore EDK2 Platforms code commit 4b3530d
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This allows us to move away from "some git commit on trunk"
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to a stable release for both TF-A and EDK2.
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Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
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Message-id: 20241125125448.185504-1-marcin.juszkiewicz@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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tests/functional/test_aarch64_sbsaref.py | 20 ++++++++++----------
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1 file changed, 10 insertions(+), 10 deletions(-)
25
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diff --git a/tests/functional/test_aarch64_sbsaref.py b/tests/functional/test_aarch64_sbsaref.py
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index XXXXXXX..XXXXXXX 100755
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--- a/tests/functional/test_aarch64_sbsaref.py
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+++ b/tests/functional/test_aarch64_sbsaref.py
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@@ -XXX,XX +XXX,XX @@ def fetch_firmware(test):
31
32
Used components:
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34
- - Trusted Firmware v2.11.0
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- - Tianocore EDK2 4d4f569924
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- - Tianocore EDK2-platforms 3f08401
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+ - Trusted Firmware v2.12.0
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+ - Tianocore EDK2 edk2-stable202411
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+ - Tianocore EDK2-platforms 4b3530d
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41
"""
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43
@@ -XXX,XX +XXX,XX @@ class Aarch64SbsarefMachine(QemuSystemTest):
44
45
ASSET_FLASH0 = Asset(
46
('https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/'
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- '20240619-148232/edk2/SBSA_FLASH0.fd.xz'),
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- '0c954842a590988f526984de22e21ae0ab9cb351a0c99a8a58e928f0c7359cf7')
49
+ '20241122-189881/edk2/SBSA_FLASH0.fd.xz'),
50
+ '76eb89d42eebe324e4395329f47447cda9ac920aabcf99aca85424609c3384a5')
51
52
ASSET_FLASH1 = Asset(
53
('https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/'
54
- '20240619-148232/edk2/SBSA_FLASH1.fd.xz'),
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- 'c6ec39374c4d79bb9e9cdeeb6db44732d90bb4a334cec92002b3f4b9cac4b5ee')
56
+ '20241122-189881/edk2/SBSA_FLASH1.fd.xz'),
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+ 'f850f243bd8dbd49c51e061e0f79f1697546938f454aeb59ab7d93e5f0d412fc')
58
59
def test_sbsaref_edk2_firmware(self):
60
61
@@ -XXX,XX +XXX,XX @@ def test_sbsaref_edk2_firmware(self):
62
63
# AP Trusted ROM
64
wait_for_console_pattern(self, "Booting Trusted Firmware")
65
- wait_for_console_pattern(self, "BL1: v2.11.0(release):")
66
+ wait_for_console_pattern(self, "BL1: v2.12.0(release):")
67
wait_for_console_pattern(self, "BL1: Booting BL2")
68
69
# Trusted Boot Firmware
70
- wait_for_console_pattern(self, "BL2: v2.11.0(release)")
71
+ wait_for_console_pattern(self, "BL2: v2.12.0(release)")
72
wait_for_console_pattern(self, "Booting BL31")
73
74
# EL3 Runtime Software
75
- wait_for_console_pattern(self, "BL31: v2.11.0(release)")
76
+ wait_for_console_pattern(self, "BL31: v2.12.0(release)")
77
78
# Non-trusted Firmware
79
wait_for_console_pattern(self, "UEFI firmware (version 1.0")
80
--
81
2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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