1 | Handful of bug fixes to sneak in before rc3. | 1 | Hi; this mostly contains the first slice of A64 decodetree |
---|---|---|---|
2 | patches, plus some other minor pieces. It also has the | ||
3 | enablement of MTE for KVM guests. | ||
2 | 4 | ||
3 | thanks | 5 | thanks |
4 | -- PMM | 6 | -- PMM |
5 | 7 | ||
6 | The following changes since commit c985266ea5b50e46e07b3568c1346e10064205c9: | 8 | The following changes since commit d27e7c359330ba7020bdbed7ed2316cb4cf6ffc1: |
7 | 9 | ||
8 | Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190726' into staging (2019-07-26 13:52:06 +0100) | 10 | qapi/parser: Drop two bad type hints for now (2023-05-17 10:18:33 -0700) |
9 | 11 | ||
10 | are available in the Git repository at: | 12 | are available in the Git repository at: |
11 | 13 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190726 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230518 |
13 | 15 | ||
14 | for you to fetch changes up to 67505c114e6acc26f3a1a2b74833c61b6a34ff95: | 16 | for you to fetch changes up to 91608e2a44f36e79cb83f863b8a7bb57d2c98061: |
15 | 17 | ||
16 | hw/arm/boot: Further improve initrd positioning code (2019-07-26 16:17:56 +0100) | 18 | docs: Convert u2f.txt to rST (2023-05-18 11:40:32 +0100) |
17 | 19 | ||
18 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
19 | target-arm queue: | 21 | target-arm queue: |
20 | * Fix broken migration on pl330 device | 22 | * Fix vd == vm overlap in sve_ldff1_z |
21 | * Fix broken migration on stellaris-input device | 23 | * Add support for MTE with KVM guests |
22 | * Add type checks to vmstate varry macros to avoid this class of bugs | 24 | * Add RAZ/WI handling for DBGDTR[TX|RX] |
23 | * hw/arm/boot: Fix some remaining cases where we would put the | 25 | * Start of conversion of A64 decoder to decodetree |
24 | initrd on top of the kernel image | 26 | * Saturate L2CTLR_EL1 core count field rather than overflowing |
27 | * vexpress: Avoid trivial memory leak of 'flashalias' | ||
28 | * sbsa-ref: switch default cpu core to Neoverse-N1 | ||
29 | * sbsa-ref: use Bochs graphics card instead of VGA | ||
30 | * MAINTAINERS: Add Marcin Juszkiewicz to sbsa-ref reviewer list | ||
31 | * docs: Convert u2f.txt to rST | ||
25 | 32 | ||
26 | ---------------------------------------------------------------- | 33 | ---------------------------------------------------------------- |
27 | Damien Hedde (1): | 34 | Alex Bennée (1): |
28 | pl330: fix vmstate description | 35 | target/arm: add RAZ/WI handling for DBGDTR[TX|RX] |
29 | 36 | ||
30 | Peter Maydell (4): | 37 | Cornelia Huck (1): |
31 | stellaris_input: Fix vmstate description of buttons field | 38 | arm/kvm: add support for MTE |
32 | vmstate.h: Type check VMSTATE_STRUCT_VARRAY macros | ||
33 | hw/arm/boot: Rename elf_{low, high}_addr to image_{low, high}_addr | ||
34 | hw/arm/boot: Further improve initrd positioning code | ||
35 | 39 | ||
36 | include/migration/vmstate.h | 30 ++++++++++++++++++++++++------ | 40 | Marcin Juszkiewicz (3): |
37 | hw/arm/boot.c | 37 +++++++++++++++++++++++++++---------- | 41 | sbsa-ref: switch default cpu core to Neoverse-N1 |
38 | hw/dma/pl330.c | 17 +++++++++-------- | 42 | Maintainers: add myself as reviewer for sbsa-ref |
39 | hw/input/stellaris_input.c | 10 ++++++---- | 43 | sbsa-ref: use Bochs graphics card instead of VGA |
40 | 4 files changed, 66 insertions(+), 28 deletions(-) | ||
41 | 44 | ||
45 | Peter Maydell (14): | ||
46 | target/arm: Create decodetree skeleton for A64 | ||
47 | target/arm: Pull calls to disas_sve() and disas_sme() out of legacy decoder | ||
48 | target/arm: Convert Extract instructions to decodetree | ||
49 | target/arm: Convert unconditional branch immediate to decodetree | ||
50 | target/arm: Convert CBZ, CBNZ to decodetree | ||
51 | target/arm: Convert TBZ, TBNZ to decodetree | ||
52 | target/arm: Convert conditional branch insns to decodetree | ||
53 | target/arm: Convert BR, BLR, RET to decodetree | ||
54 | target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to decodetree | ||
55 | target/arm: Convert BRAA, BRAB, BLRAA, BLRAB to decodetree | ||
56 | target/arm: Convert ERET, ERETAA, ERETAB to decodetree | ||
57 | target/arm: Saturate L2CTLR_EL1 core count field rather than overflowing | ||
58 | hw/arm/vexpress: Avoid trivial memory leak of 'flashalias' | ||
59 | docs: Convert u2f.txt to rST | ||
60 | |||
61 | Richard Henderson (10): | ||
62 | target/arm: Fix vd == vm overlap in sve_ldff1_z | ||
63 | target/arm: Split out disas_a64_legacy | ||
64 | target/arm: Convert PC-rel addressing to decodetree | ||
65 | target/arm: Split gen_add_CC and gen_sub_CC | ||
66 | target/arm: Convert Add/subtract (immediate) to decodetree | ||
67 | target/arm: Convert Add/subtract (immediate with tags) to decodetree | ||
68 | target/arm: Replace bitmask64 with MAKE_64BIT_MASK | ||
69 | target/arm: Convert Logical (immediate) to decodetree | ||
70 | target/arm: Convert Move wide (immediate) to decodetree | ||
71 | target/arm: Convert Bitfield to decodetree | ||
72 | |||
73 | MAINTAINERS | 1 + | ||
74 | docs/system/device-emulation.rst | 1 + | ||
75 | docs/system/devices/usb-u2f.rst | 93 +++ | ||
76 | docs/system/devices/usb.rst | 2 +- | ||
77 | docs/u2f.txt | 110 ---- | ||
78 | target/arm/cpu.h | 4 + | ||
79 | target/arm/kvm_arm.h | 19 + | ||
80 | target/arm/tcg/translate.h | 5 + | ||
81 | target/arm/tcg/a64.decode | 152 +++++ | ||
82 | hw/arm/sbsa-ref.c | 4 +- | ||
83 | hw/arm/vexpress.c | 40 +- | ||
84 | hw/arm/virt.c | 73 ++- | ||
85 | target/arm/cortex-regs.c | 11 +- | ||
86 | target/arm/cpu.c | 9 +- | ||
87 | target/arm/debug_helper.c | 11 +- | ||
88 | target/arm/kvm.c | 35 + | ||
89 | target/arm/kvm64.c | 5 + | ||
90 | target/arm/tcg/sve_helper.c | 6 + | ||
91 | target/arm/tcg/translate-a64.c | 1321 ++++++++++++++++---------------------- | ||
92 | target/arm/tcg/meson.build | 1 + | ||
93 | 20 files changed, 979 insertions(+), 924 deletions(-) | ||
94 | create mode 100644 docs/system/devices/usb-u2f.rst | ||
95 | delete mode 100644 docs/u2f.txt | ||
96 | create mode 100644 target/arm/tcg/a64.decode | ||
97 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> | ||
1 | 2 | ||
3 | The world outside moves to newer and newer cpu cores. Let move SBSA | ||
4 | Reference Platform to something newer as well. | ||
5 | |||
6 | Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> | ||
7 | Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> | ||
8 | Message-id: 20230506183417.1360427-1-marcin.juszkiewicz@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | hw/arm/sbsa-ref.c | 2 +- | ||
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/arm/sbsa-ref.c | ||
17 | +++ b/hw/arm/sbsa-ref.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void sbsa_ref_class_init(ObjectClass *oc, void *data) | ||
19 | |||
20 | mc->init = sbsa_ref_init; | ||
21 | mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; | ||
22 | - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57"); | ||
23 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n1"); | ||
24 | mc->max_cpus = 512; | ||
25 | mc->pci_allow_0_address = true; | ||
26 | mc->minimum_page_bits = 12; | ||
27 | -- | ||
28 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | If vd == vm, copy vm to scratch, so that we can pre-zero | ||
4 | the output and still access the gather indicies. | ||
5 | |||
6 | Cc: qemu-stable@nongnu.org | ||
7 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1612 | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20230504104232.1877774-1-richard.henderson@linaro.org | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | target/arm/tcg/sve_helper.c | 6 ++++++ | ||
14 | 1 file changed, 6 insertions(+) | ||
15 | |||
16 | diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/tcg/sve_helper.c | ||
19 | +++ b/target/arm/tcg/sve_helper.c | ||
20 | @@ -XXX,XX +XXX,XX @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, | ||
21 | intptr_t reg_off; | ||
22 | SVEHostPage info; | ||
23 | target_ulong addr, in_page; | ||
24 | + ARMVectorReg scratch; | ||
25 | |||
26 | /* Skip to the first true predicate. */ | ||
27 | reg_off = find_next_active(vg, 0, reg_max, esz); | ||
28 | @@ -XXX,XX +XXX,XX @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, | ||
29 | return; | ||
30 | } | ||
31 | |||
32 | + /* Protect against overlap between vd and vm. */ | ||
33 | + if (unlikely(vd == vm)) { | ||
34 | + vm = memcpy(&scratch, vm, reg_max); | ||
35 | + } | ||
36 | + | ||
37 | /* | ||
38 | * Probe the first element, allowing faults. | ||
39 | */ | ||
40 | -- | ||
41 | 2.34.1 | diff view generated by jsdifflib |
1 | In commit e6b2b20d9735d4ef we made the boot loader code try to avoid | 1 | From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
---|---|---|---|
2 | putting the initrd on top of the kernel. However the expression used | ||
3 | to calculate the start of the initrd: | ||
4 | 2 | ||
5 | info->initrd_start = info->loader_start + | 3 | At Linaro I work on sbsa-ref, know direction it goes. |
6 | MAX(MIN(info->ram_size / 2, 128 * 1024 * 1024), kernel_size); | ||
7 | 4 | ||
8 | incorrectly uses 'kernel_size' as the offset within RAM of the | 5 | May not get code details each time. |
9 | highest address to avoid. This is incorrect because the kernel | ||
10 | doesn't start at address 0, but slightly higher than that. This | ||
11 | means that we can still incorrectly end up overlaying the initrd on | ||
12 | the kernel in some cases, for example: | ||
13 | 6 | ||
14 | * The kernel's image_size is 0x0a7a8000 | 7 | Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
15 | * The kernel was loaded at 0x40080000 | 8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
16 | * The end of the kernel is 0x4A828000 | 9 | Message-id: 20230515143753.365591-1-marcin.juszkiewicz@linaro.org |
17 | * The DTB was loaded at 0x4a800000 | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | ||
12 | MAINTAINERS | 1 + | ||
13 | 1 file changed, 1 insertion(+) | ||
18 | 14 | ||
19 | To get this right we need to track the actual highest address used | 15 | diff --git a/MAINTAINERS b/MAINTAINERS |
20 | by the kernel and use that rather than kernel_size. We already | ||
21 | set image_low_addr and image_high_addr for ELF images; set them | ||
22 | also for the various other image types we support, and then use | ||
23 | image_high_addr as the lowest allowed address for the initrd. | ||
24 | (We don't use image_low_addr, but we set it for consistency | ||
25 | with the existing code path for ELF files.) | ||
26 | |||
27 | Fixes: e6b2b20d9735d4ef | ||
28 | Reported-by: Mark Rutland <mark.rutland@arm.com> | ||
29 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
30 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
31 | Tested-by: Mark Rutland <mark.rutland@arm.com> | ||
32 | Message-id: 20190722151804.25467-3-peter.maydell@linaro.org | ||
33 | --- | ||
34 | hw/arm/boot.c | 19 +++++++++++++++++-- | ||
35 | 1 file changed, 17 insertions(+), 2 deletions(-) | ||
36 | |||
37 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
39 | --- a/hw/arm/boot.c | 17 | --- a/MAINTAINERS |
40 | +++ b/hw/arm/boot.c | 18 | +++ b/MAINTAINERS |
41 | @@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, | 19 | @@ -XXX,XX +XXX,XX @@ SBSA-REF |
42 | int is_linux = 0; | 20 | M: Radoslaw Biernacki <rad@semihalf.com> |
43 | uint64_t elf_entry; | 21 | M: Peter Maydell <peter.maydell@linaro.org> |
44 | /* Addresses of first byte used and first byte not used by the image */ | 22 | R: Leif Lindholm <quic_llindhol@quicinc.com> |
45 | - uint64_t image_low_addr, image_high_addr; | 23 | +R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
46 | + uint64_t image_low_addr = 0, image_high_addr = 0; | 24 | L: qemu-arm@nongnu.org |
47 | int elf_machine; | 25 | S: Maintained |
48 | hwaddr entry; | 26 | F: hw/arm/sbsa-ref.c |
49 | static const ARMInsnFixup *primary_loader; | ||
50 | @@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, | ||
51 | uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR; | ||
52 | kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr, | ||
53 | &is_linux, NULL, NULL, as); | ||
54 | + if (kernel_size >= 0) { | ||
55 | + image_low_addr = loadaddr; | ||
56 | + image_high_addr = image_low_addr + kernel_size; | ||
57 | + } | ||
58 | } | ||
59 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { | ||
60 | kernel_size = load_aarch64_image(info->kernel_filename, | ||
61 | info->loader_start, &entry, as); | ||
62 | is_linux = 1; | ||
63 | + if (kernel_size >= 0) { | ||
64 | + image_low_addr = entry; | ||
65 | + image_high_addr = image_low_addr + kernel_size; | ||
66 | + } | ||
67 | } else if (kernel_size < 0) { | ||
68 | /* 32-bit ARM */ | ||
69 | entry = info->loader_start + KERNEL_LOAD_ADDR; | ||
70 | kernel_size = load_image_targphys_as(info->kernel_filename, entry, | ||
71 | ram_end - KERNEL_LOAD_ADDR, as); | ||
72 | is_linux = 1; | ||
73 | + if (kernel_size >= 0) { | ||
74 | + image_low_addr = entry; | ||
75 | + image_high_addr = image_low_addr + kernel_size; | ||
76 | + } | ||
77 | } | ||
78 | if (kernel_size < 0) { | ||
79 | error_report("could not load kernel '%s'", info->kernel_filename); | ||
80 | @@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, | ||
81 | * we might still make a bad choice here. | ||
82 | */ | ||
83 | info->initrd_start = info->loader_start + | ||
84 | - MAX(MIN(info->ram_size / 2, 128 * 1024 * 1024), kernel_size); | ||
85 | + MIN(info->ram_size / 2, 128 * 1024 * 1024); | ||
86 | + if (image_high_addr) { | ||
87 | + info->initrd_start = MAX(info->initrd_start, image_high_addr); | ||
88 | + } | ||
89 | info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start); | ||
90 | |||
91 | if (is_linux) { | ||
92 | -- | 27 | -- |
93 | 2.20.1 | 28 | 2.34.1 |
94 | 29 | ||
95 | 30 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Cornelia Huck <cohuck@redhat.com> | |
2 | |||
3 | Extend the 'mte' property for the virt machine to cover KVM as | ||
4 | well. For KVM, we don't allocate tag memory, but instead enable the | ||
5 | capability. | ||
6 | |||
7 | If MTE has been enabled, we need to disable migration, as we do not | ||
8 | yet have a way to migrate the tags as well. Therefore, MTE will stay | ||
9 | off with KVM unless requested explicitly. | ||
10 | |||
11 | Signed-off-by: Cornelia Huck <cohuck@redhat.com> | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Message-id: 20230428095533.21747-2-cohuck@redhat.com | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | --- | ||
17 | target/arm/cpu.h | 4 +++ | ||
18 | target/arm/kvm_arm.h | 19 ++++++++++++ | ||
19 | hw/arm/virt.c | 73 +++++++++++++++++++++++++------------------- | ||
20 | target/arm/cpu.c | 9 +++--- | ||
21 | target/arm/kvm.c | 35 +++++++++++++++++++++ | ||
22 | target/arm/kvm64.c | 5 +++ | ||
23 | 6 files changed, 109 insertions(+), 36 deletions(-) | ||
24 | |||
25 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/target/arm/cpu.h | ||
28 | +++ b/target/arm/cpu.h | ||
29 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { | ||
30 | */ | ||
31 | uint32_t psci_conduit; | ||
32 | |||
33 | + /* CPU has Memory Tag Extension */ | ||
34 | + bool has_mte; | ||
35 | + | ||
36 | /* For v8M, initial value of the Secure VTOR */ | ||
37 | uint32_t init_svtor; | ||
38 | /* For v8M, initial value of the Non-secure VTOR */ | ||
39 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { | ||
40 | bool prop_pauth; | ||
41 | bool prop_pauth_impdef; | ||
42 | bool prop_lpa2; | ||
43 | + OnOffAuto prop_mte; | ||
44 | |||
45 | /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ | ||
46 | uint32_t dcz_blocksize; | ||
47 | diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/target/arm/kvm_arm.h | ||
50 | +++ b/target/arm/kvm_arm.h | ||
51 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_pmu_supported(void); | ||
52 | */ | ||
53 | bool kvm_arm_sve_supported(void); | ||
54 | |||
55 | +/** | ||
56 | + * kvm_arm_mte_supported: | ||
57 | + * | ||
58 | + * Returns: true if KVM can enable MTE, and false otherwise. | ||
59 | + */ | ||
60 | +bool kvm_arm_mte_supported(void); | ||
61 | + | ||
62 | /** | ||
63 | * kvm_arm_get_max_vm_ipa_size: | ||
64 | * @ms: Machine state handle | ||
65 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa); | ||
66 | |||
67 | int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); | ||
68 | |||
69 | +void kvm_arm_enable_mte(Object *cpuobj, Error **errp); | ||
70 | + | ||
71 | #else | ||
72 | |||
73 | /* | ||
74 | @@ -XXX,XX +XXX,XX @@ static inline bool kvm_arm_steal_time_supported(void) | ||
75 | return false; | ||
76 | } | ||
77 | |||
78 | +static inline bool kvm_arm_mte_supported(void) | ||
79 | +{ | ||
80 | + return false; | ||
81 | +} | ||
82 | + | ||
83 | /* | ||
84 | * These functions should never actually be called without KVM support. | ||
85 | */ | ||
86 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t kvm_arm_sve_get_vls(CPUState *cs) | ||
87 | g_assert_not_reached(); | ||
88 | } | ||
89 | |||
90 | +static inline void kvm_arm_enable_mte(Object *cpuobj, Error **errp) | ||
91 | +{ | ||
92 | + g_assert_not_reached(); | ||
93 | +} | ||
94 | + | ||
95 | #endif | ||
96 | |||
97 | static inline const char *gic_class_name(void) | ||
98 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
99 | index XXXXXXX..XXXXXXX 100644 | ||
100 | --- a/hw/arm/virt.c | ||
101 | +++ b/hw/arm/virt.c | ||
102 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
103 | exit(1); | ||
104 | } | ||
105 | |||
106 | - if (vms->mte && (kvm_enabled() || hvf_enabled())) { | ||
107 | + if (vms->mte && hvf_enabled()) { | ||
108 | error_report("mach-virt: %s does not support providing " | ||
109 | "MTE to the guest CPU", | ||
110 | current_accel_name()); | ||
111 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
112 | } | ||
113 | |||
114 | if (vms->mte) { | ||
115 | - /* Create the memory region only once, but link to all cpus. */ | ||
116 | - if (!tag_sysmem) { | ||
117 | - /* | ||
118 | - * The property exists only if MemTag is supported. | ||
119 | - * If it is, we must allocate the ram to back that up. | ||
120 | - */ | ||
121 | - if (!object_property_find(cpuobj, "tag-memory")) { | ||
122 | - error_report("MTE requested, but not supported " | ||
123 | - "by the guest CPU"); | ||
124 | + if (tcg_enabled()) { | ||
125 | + /* Create the memory region only once, but link to all cpus. */ | ||
126 | + if (!tag_sysmem) { | ||
127 | + /* | ||
128 | + * The property exists only if MemTag is supported. | ||
129 | + * If it is, we must allocate the ram to back that up. | ||
130 | + */ | ||
131 | + if (!object_property_find(cpuobj, "tag-memory")) { | ||
132 | + error_report("MTE requested, but not supported " | ||
133 | + "by the guest CPU"); | ||
134 | + exit(1); | ||
135 | + } | ||
136 | + | ||
137 | + tag_sysmem = g_new(MemoryRegion, 1); | ||
138 | + memory_region_init(tag_sysmem, OBJECT(machine), | ||
139 | + "tag-memory", UINT64_MAX / 32); | ||
140 | + | ||
141 | + if (vms->secure) { | ||
142 | + secure_tag_sysmem = g_new(MemoryRegion, 1); | ||
143 | + memory_region_init(secure_tag_sysmem, OBJECT(machine), | ||
144 | + "secure-tag-memory", | ||
145 | + UINT64_MAX / 32); | ||
146 | + | ||
147 | + /* As with ram, secure-tag takes precedence over tag. */ | ||
148 | + memory_region_add_subregion_overlap(secure_tag_sysmem, | ||
149 | + 0, tag_sysmem, -1); | ||
150 | + } | ||
151 | + } | ||
152 | + | ||
153 | + object_property_set_link(cpuobj, "tag-memory", | ||
154 | + OBJECT(tag_sysmem), &error_abort); | ||
155 | + if (vms->secure) { | ||
156 | + object_property_set_link(cpuobj, "secure-tag-memory", | ||
157 | + OBJECT(secure_tag_sysmem), | ||
158 | + &error_abort); | ||
159 | + } | ||
160 | + } else if (kvm_enabled()) { | ||
161 | + if (!kvm_arm_mte_supported()) { | ||
162 | + error_report("MTE requested, but not supported by KVM"); | ||
163 | exit(1); | ||
164 | } | ||
165 | - | ||
166 | - tag_sysmem = g_new(MemoryRegion, 1); | ||
167 | - memory_region_init(tag_sysmem, OBJECT(machine), | ||
168 | - "tag-memory", UINT64_MAX / 32); | ||
169 | - | ||
170 | - if (vms->secure) { | ||
171 | - secure_tag_sysmem = g_new(MemoryRegion, 1); | ||
172 | - memory_region_init(secure_tag_sysmem, OBJECT(machine), | ||
173 | - "secure-tag-memory", UINT64_MAX / 32); | ||
174 | - | ||
175 | - /* As with ram, secure-tag takes precedence over tag. */ | ||
176 | - memory_region_add_subregion_overlap(secure_tag_sysmem, 0, | ||
177 | - tag_sysmem, -1); | ||
178 | - } | ||
179 | - } | ||
180 | - | ||
181 | - object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), | ||
182 | - &error_abort); | ||
183 | - if (vms->secure) { | ||
184 | - object_property_set_link(cpuobj, "secure-tag-memory", | ||
185 | - OBJECT(secure_tag_sysmem), | ||
186 | - &error_abort); | ||
187 | + kvm_arm_enable_mte(cpuobj, &error_abort); | ||
188 | } | ||
189 | } | ||
190 | |||
191 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
192 | index XXXXXXX..XXXXXXX 100644 | ||
193 | --- a/target/arm/cpu.c | ||
194 | +++ b/target/arm/cpu.c | ||
195 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj) | ||
196 | qdev_prop_allow_set_link_before_realize, | ||
197 | OBJ_PROP_LINK_STRONG); | ||
198 | } | ||
199 | + cpu->has_mte = true; | ||
200 | } | ||
201 | #endif | ||
202 | } | ||
203 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
204 | } | ||
205 | if (cpu->tag_memory) { | ||
206 | error_setg(errp, | ||
207 | - "Cannot enable %s when guest CPUs has MTE enabled", | ||
208 | + "Cannot enable %s when guest CPUs has tag memory enabled", | ||
209 | current_accel_name()); | ||
210 | return; | ||
211 | } | ||
212 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
213 | } | ||
214 | |||
215 | #ifndef CONFIG_USER_ONLY | ||
216 | - if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { | ||
217 | + if (!cpu->has_mte && cpu_isar_feature(aa64_mte, cpu)) { | ||
218 | /* | ||
219 | - * Disable the MTE feature bits if we do not have tag-memory | ||
220 | - * provided by the machine. | ||
221 | + * Disable the MTE feature bits if we do not have the feature | ||
222 | + * setup by the machine. | ||
223 | */ | ||
224 | cpu->isar.id_aa64pfr1 = | ||
225 | FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); | ||
226 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c | ||
227 | index XXXXXXX..XXXXXXX 100644 | ||
228 | --- a/target/arm/kvm.c | ||
229 | +++ b/target/arm/kvm.c | ||
230 | @@ -XXX,XX +XXX,XX @@ | ||
231 | #include "hw/boards.h" | ||
232 | #include "hw/irq.h" | ||
233 | #include "qemu/log.h" | ||
234 | +#include "migration/blocker.h" | ||
235 | |||
236 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { | ||
237 | KVM_CAP_LAST_INFO | ||
238 | @@ -XXX,XX +XXX,XX @@ bool kvm_arch_cpu_check_are_resettable(void) | ||
239 | void kvm_arch_accel_class_init(ObjectClass *oc) | ||
240 | { | ||
241 | } | ||
242 | + | ||
243 | +void kvm_arm_enable_mte(Object *cpuobj, Error **errp) | ||
244 | +{ | ||
245 | + static bool tried_to_enable; | ||
246 | + static bool succeeded_to_enable; | ||
247 | + Error *mte_migration_blocker = NULL; | ||
248 | + int ret; | ||
249 | + | ||
250 | + if (!tried_to_enable) { | ||
251 | + /* | ||
252 | + * MTE on KVM is enabled on a per-VM basis (and retrying doesn't make | ||
253 | + * sense), and we only want a single migration blocker as well. | ||
254 | + */ | ||
255 | + tried_to_enable = true; | ||
256 | + | ||
257 | + ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_ARM_MTE, 0); | ||
258 | + if (ret) { | ||
259 | + error_setg_errno(errp, -ret, "Failed to enable KVM_CAP_ARM_MTE"); | ||
260 | + return; | ||
261 | + } | ||
262 | + | ||
263 | + /* TODO: add proper migration support with MTE enabled */ | ||
264 | + error_setg(&mte_migration_blocker, | ||
265 | + "Live migration disabled due to MTE enabled"); | ||
266 | + if (migrate_add_blocker(mte_migration_blocker, errp)) { | ||
267 | + error_free(mte_migration_blocker); | ||
268 | + return; | ||
269 | + } | ||
270 | + succeeded_to_enable = true; | ||
271 | + } | ||
272 | + if (succeeded_to_enable) { | ||
273 | + object_property_set_bool(cpuobj, "has_mte", true, NULL); | ||
274 | + } | ||
275 | +} | ||
276 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
277 | index XXXXXXX..XXXXXXX 100644 | ||
278 | --- a/target/arm/kvm64.c | ||
279 | +++ b/target/arm/kvm64.c | ||
280 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_steal_time_supported(void) | ||
281 | return kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME); | ||
282 | } | ||
283 | |||
284 | +bool kvm_arm_mte_supported(void) | ||
285 | +{ | ||
286 | + return kvm_check_extension(kvm_state, KVM_CAP_ARM_MTE); | ||
287 | +} | ||
288 | + | ||
289 | QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1); | ||
290 | |||
291 | uint32_t kvm_arm_sve_get_vls(CPUState *cs) | ||
292 | -- | ||
293 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Damien Hedde <damien.hedde@greensocs.com> | 1 | From: Alex Bennée <alex.bennee@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Fix the pl330 main and queue vmstate description. | 3 | The commit b3aa2f2128 (target/arm: provide stubs for more external |
4 | There were missing POINTER flags causing crashes during | 4 | debug registers) was added to handle HyperV's unconditional usage of |
5 | incoming migration because: | 5 | Debug Communications Channel. It turns out that Linux will similarly |
6 | + PL330State chan field is a pointer to an array | 6 | break if you enable CONFIG_HVC_DCC "ARM JTAG DCC console". |
7 | + PL330Queue queue field is a pointer to an array | ||
8 | 7 | ||
9 | Also bump corresponding vmsd version numbers. | 8 | Extend the registers we RAZ/WI set to avoid this. |
10 | 9 | ||
11 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | 10 | Cc: Anders Roxell <anders.roxell@linaro.org> |
12 | Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> | 11 | Cc: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> |
13 | Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com> | 12 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
14 | Message-id: 20190724143553.21557-1-damien.hedde@greensocs.com | 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
14 | Message-id: 20230516104420.407912-1-alex.bennee@linaro.org | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | --- | 16 | --- |
17 | hw/dma/pl330.c | 17 +++++++++-------- | 17 | target/arm/debug_helper.c | 11 +++++++++-- |
18 | 1 file changed, 9 insertions(+), 8 deletions(-) | 18 | 1 file changed, 9 insertions(+), 2 deletions(-) |
19 | 19 | ||
20 | diff --git a/hw/dma/pl330.c b/hw/dma/pl330.c | 20 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c |
21 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/hw/dma/pl330.c | 22 | --- a/target/arm/debug_helper.c |
23 | +++ b/hw/dma/pl330.c | 23 | +++ b/target/arm/debug_helper.c |
24 | @@ -XXX,XX +XXX,XX @@ typedef struct PL330Queue { | 24 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { |
25 | 25 | .access = PL0_R, .accessfn = access_tdcc, | |
26 | static const VMStateDescription vmstate_pl330_queue = { | 26 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
27 | .name = "pl330_queue", | 27 | /* |
28 | - .version_id = 1, | 28 | - * OSDTRRX_EL1/OSDTRTX_EL1 are used for save and restore of DBGDTRRX_EL0. |
29 | - .minimum_version_id = 1, | 29 | - * It is a component of the Debug Communications Channel, which is not implemented. |
30 | + .version_id = 2, | 30 | + * These registers belong to the Debug Communications Channel, |
31 | + .minimum_version_id = 2, | 31 | + * which is not implemented. However we implement RAZ/WI behaviour |
32 | .fields = (VMStateField[]) { | 32 | + * with trapping to prevent spurious SIGILLs if the guest OS does |
33 | - VMSTATE_STRUCT_VARRAY_UINT32(queue, PL330Queue, queue_size, 1, | 33 | + * access them as the support cannot be probed for. |
34 | - vmstate_pl330_queue_entry, PL330QueueEntry), | 34 | */ |
35 | + VMSTATE_STRUCT_VARRAY_POINTER_UINT32(queue, PL330Queue, queue_size, | 35 | { .name = "OSDTRRX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, |
36 | + vmstate_pl330_queue_entry, | 36 | .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2, |
37 | + PL330QueueEntry), | 37 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { |
38 | VMSTATE_END_OF_LIST() | 38 | .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, |
39 | } | 39 | .access = PL1_RW, .accessfn = access_tdcc, |
40 | }; | 40 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
41 | @@ -XXX,XX +XXX,XX @@ struct PL330State { | 41 | + /* DBGDTRTX_EL0/DBGDTRRX_EL0 depend on direction */ |
42 | 42 | + { .name = "DBGDTR_EL0", .state = ARM_CP_STATE_BOTH, .cp = 14, | |
43 | static const VMStateDescription vmstate_pl330 = { | 43 | + .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 5, .opc2 = 0, |
44 | .name = "pl330", | 44 | + .access = PL0_RW, .accessfn = access_tdcc, |
45 | - .version_id = 1, | 45 | + .type = ARM_CP_CONST, .resetvalue = 0 }, |
46 | - .minimum_version_id = 1, | 46 | /* |
47 | + .version_id = 2, | 47 | * OSECCR_EL1 provides a mechanism for an operating system |
48 | + .minimum_version_id = 2, | 48 | * to access the contents of EDECCR. EDECCR is not implemented though, |
49 | .fields = (VMStateField[]) { | ||
50 | VMSTATE_STRUCT(manager, PL330State, 0, vmstate_pl330_chan, PL330Chan), | ||
51 | - VMSTATE_STRUCT_VARRAY_UINT32(chan, PL330State, num_chnls, 0, | ||
52 | - vmstate_pl330_chan, PL330Chan), | ||
53 | + VMSTATE_STRUCT_VARRAY_POINTER_UINT32(chan, PL330State, num_chnls, | ||
54 | + vmstate_pl330_chan, PL330Chan), | ||
55 | VMSTATE_VBUFFER_UINT32(lo_seqn, PL330State, 1, NULL, num_chnls), | ||
56 | VMSTATE_VBUFFER_UINT32(hi_seqn, PL330State, 1, NULL, num_chnls), | ||
57 | VMSTATE_STRUCT(fifo, PL330State, 0, vmstate_pl330_fifo, PL330Fifo), | ||
58 | -- | 49 | -- |
59 | 2.20.1 | 50 | 2.34.1 |
60 | 51 | ||
61 | 52 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> | ||
1 | 2 | ||
3 | Bochs card is normal PCI Express card so it fits better in system with | ||
4 | PCI Express bus. VGA is simple legacy PCI card. | ||
5 | |||
6 | Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> | ||
7 | Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> | ||
8 | Message-id: 20230505120936.1097060-1-marcin.juszkiewicz@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | hw/arm/sbsa-ref.c | 2 +- | ||
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/arm/sbsa-ref.c | ||
17 | +++ b/hw/arm/sbsa-ref.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void create_pcie(SBSAMachineState *sms) | ||
19 | } | ||
20 | } | ||
21 | |||
22 | - pci_create_simple(pci->bus, -1, "VGA"); | ||
23 | + pci_create_simple(pci->bus, -1, "bochs-display"); | ||
24 | |||
25 | create_smmu(sms, pci->bus); | ||
26 | } | ||
27 | -- | ||
28 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Split out all of the decode stuff from aarch64_tr_translate_insn. | ||
4 | Call it disas_a64_legacy to indicate it will be replaced. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Message-id: 20230512144106.3608981-2-peter.maydell@linaro.org | ||
10 | [PMM: Rebased] | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | target/arm/tcg/translate-a64.c | 82 ++++++++++++++++++---------------- | ||
15 | 1 file changed, 44 insertions(+), 38 deletions(-) | ||
16 | |||
17 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/tcg/translate-a64.c | ||
20 | +++ b/target/arm/tcg/translate-a64.c | ||
21 | @@ -XXX,XX +XXX,XX @@ static bool btype_destination_ok(uint32_t insn, bool bt, int btype) | ||
22 | return false; | ||
23 | } | ||
24 | |||
25 | +/* C3.1 A64 instruction index by encoding */ | ||
26 | +static void disas_a64_legacy(DisasContext *s, uint32_t insn) | ||
27 | +{ | ||
28 | + switch (extract32(insn, 25, 4)) { | ||
29 | + case 0x0: | ||
30 | + if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) { | ||
31 | + unallocated_encoding(s); | ||
32 | + } | ||
33 | + break; | ||
34 | + case 0x1: case 0x3: /* UNALLOCATED */ | ||
35 | + unallocated_encoding(s); | ||
36 | + break; | ||
37 | + case 0x2: | ||
38 | + if (!disas_sve(s, insn)) { | ||
39 | + unallocated_encoding(s); | ||
40 | + } | ||
41 | + break; | ||
42 | + case 0x8: case 0x9: /* Data processing - immediate */ | ||
43 | + disas_data_proc_imm(s, insn); | ||
44 | + break; | ||
45 | + case 0xa: case 0xb: /* Branch, exception generation and system insns */ | ||
46 | + disas_b_exc_sys(s, insn); | ||
47 | + break; | ||
48 | + case 0x4: | ||
49 | + case 0x6: | ||
50 | + case 0xc: | ||
51 | + case 0xe: /* Loads and stores */ | ||
52 | + disas_ldst(s, insn); | ||
53 | + break; | ||
54 | + case 0x5: | ||
55 | + case 0xd: /* Data processing - register */ | ||
56 | + disas_data_proc_reg(s, insn); | ||
57 | + break; | ||
58 | + case 0x7: | ||
59 | + case 0xf: /* Data processing - SIMD and floating point */ | ||
60 | + disas_data_proc_simd_fp(s, insn); | ||
61 | + break; | ||
62 | + default: | ||
63 | + assert(FALSE); /* all 15 cases should be handled above */ | ||
64 | + break; | ||
65 | + } | ||
66 | +} | ||
67 | + | ||
68 | static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, | ||
69 | CPUState *cpu) | ||
70 | { | ||
71 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
72 | disas_sme_fa64(s, insn); | ||
73 | } | ||
74 | |||
75 | - switch (extract32(insn, 25, 4)) { | ||
76 | - case 0x0: | ||
77 | - if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) { | ||
78 | - unallocated_encoding(s); | ||
79 | - } | ||
80 | - break; | ||
81 | - case 0x1: case 0x3: /* UNALLOCATED */ | ||
82 | - unallocated_encoding(s); | ||
83 | - break; | ||
84 | - case 0x2: | ||
85 | - if (!disas_sve(s, insn)) { | ||
86 | - unallocated_encoding(s); | ||
87 | - } | ||
88 | - break; | ||
89 | - case 0x8: case 0x9: /* Data processing - immediate */ | ||
90 | - disas_data_proc_imm(s, insn); | ||
91 | - break; | ||
92 | - case 0xa: case 0xb: /* Branch, exception generation and system insns */ | ||
93 | - disas_b_exc_sys(s, insn); | ||
94 | - break; | ||
95 | - case 0x4: | ||
96 | - case 0x6: | ||
97 | - case 0xc: | ||
98 | - case 0xe: /* Loads and stores */ | ||
99 | - disas_ldst(s, insn); | ||
100 | - break; | ||
101 | - case 0x5: | ||
102 | - case 0xd: /* Data processing - register */ | ||
103 | - disas_data_proc_reg(s, insn); | ||
104 | - break; | ||
105 | - case 0x7: | ||
106 | - case 0xf: /* Data processing - SIMD and floating point */ | ||
107 | - disas_data_proc_simd_fp(s, insn); | ||
108 | - break; | ||
109 | - default: | ||
110 | - assert(FALSE); /* all 15 cases should be handled above */ | ||
111 | - break; | ||
112 | - } | ||
113 | + disas_a64_legacy(s, insn); | ||
114 | |||
115 | /* | ||
116 | * After execution of most insns, btype is reset to 0. | ||
117 | -- | ||
118 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The A64 translator uses a hand-written decoder for everything except | ||
2 | SVE or SME. It's fairly well structured, but it's becoming obvious | ||
3 | that it's still more painful to add instructions to than the A32 | ||
4 | translator, because putting a new instruction into the right place in | ||
5 | a hand-written decoder is much harder than adding new instruction | ||
6 | patterns to a decodetree file. | ||
1 | 7 | ||
8 | As the first step in conversion to decodetree, create the skeleton of | ||
9 | the decodetree decoder; where it does not handle instructions we will | ||
10 | fall back to the legacy decoder (which will be for everything at the | ||
11 | moment, since there are no patterns in a64.decode). | ||
12 | |||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20230512144106.3608981-3-peter.maydell@linaro.org | ||
16 | --- | ||
17 | target/arm/tcg/a64.decode | 20 ++++++++++++++++++++ | ||
18 | target/arm/tcg/translate-a64.c | 18 +++++++++++------- | ||
19 | target/arm/tcg/meson.build | 1 + | ||
20 | 3 files changed, 32 insertions(+), 7 deletions(-) | ||
21 | create mode 100644 target/arm/tcg/a64.decode | ||
22 | |||
23 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode | ||
24 | new file mode 100644 | ||
25 | index XXXXXXX..XXXXXXX | ||
26 | --- /dev/null | ||
27 | +++ b/target/arm/tcg/a64.decode | ||
28 | @@ -XXX,XX +XXX,XX @@ | ||
29 | +# AArch64 A64 allowed instruction decoding | ||
30 | +# | ||
31 | +# Copyright (c) 2023 Linaro, Ltd | ||
32 | +# | ||
33 | +# This library is free software; you can redistribute it and/or | ||
34 | +# modify it under the terms of the GNU Lesser General Public | ||
35 | +# License as published by the Free Software Foundation; either | ||
36 | +# version 2.1 of the License, or (at your option) any later version. | ||
37 | +# | ||
38 | +# This library is distributed in the hope that it will be useful, | ||
39 | +# but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
40 | +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
41 | +# Lesser General Public License for more details. | ||
42 | +# | ||
43 | +# You should have received a copy of the GNU Lesser General Public | ||
44 | +# License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
45 | + | ||
46 | +# | ||
47 | +# This file is processed by scripts/decodetree.py | ||
48 | +# | ||
49 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/target/arm/tcg/translate-a64.c | ||
52 | +++ b/target/arm/tcg/translate-a64.c | ||
53 | @@ -XXX,XX +XXX,XX @@ enum a64_shift_type { | ||
54 | A64_SHIFT_TYPE_ROR = 3 | ||
55 | }; | ||
56 | |||
57 | +/* | ||
58 | + * Include the generated decoders. | ||
59 | + */ | ||
60 | + | ||
61 | +#include "decode-sme-fa64.c.inc" | ||
62 | +#include "decode-a64.c.inc" | ||
63 | + | ||
64 | /* Table based decoder typedefs - used when the relevant bits for decode | ||
65 | * are too awkwardly scattered across the instruction (eg SIMD). | ||
66 | */ | ||
67 | @@ -XXX,XX +XXX,XX @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) | ||
68 | } | ||
69 | } | ||
70 | |||
71 | -/* | ||
72 | - * Include the generated SME FA64 decoder. | ||
73 | - */ | ||
74 | - | ||
75 | -#include "decode-sme-fa64.c.inc" | ||
76 | - | ||
77 | static bool trans_OK(DisasContext *s, arg_OK *a) | ||
78 | { | ||
79 | return true; | ||
80 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
81 | disas_sme_fa64(s, insn); | ||
82 | } | ||
83 | |||
84 | - disas_a64_legacy(s, insn); | ||
85 | + | ||
86 | + if (!disas_a64(s, insn)) { | ||
87 | + disas_a64_legacy(s, insn); | ||
88 | + } | ||
89 | |||
90 | /* | ||
91 | * After execution of most insns, btype is reset to 0. | ||
92 | diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build | ||
93 | index XXXXXXX..XXXXXXX 100644 | ||
94 | --- a/target/arm/tcg/meson.build | ||
95 | +++ b/target/arm/tcg/meson.build | ||
96 | @@ -XXX,XX +XXX,XX @@ gen = [ | ||
97 | decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'), | ||
98 | decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'), | ||
99 | decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']), | ||
100 | + decodetree.process('a64.decode', extra_args: ['--static-decode=disas_a64']), | ||
101 | ] | ||
102 | |||
103 | arm_ss.add(gen) | ||
104 | -- | ||
105 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The SVE and SME decode is already done by decodetree. Pull the calls | ||
2 | to these decoders out of the legacy decoder. This doesn't change | ||
3 | behaviour because all the patterns in sve.decode and sme.decode | ||
4 | already require the bits that the legacy decoder is decoding to have | ||
5 | the correct values. | ||
1 | 6 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20230512144106.3608981-4-peter.maydell@linaro.org | ||
10 | --- | ||
11 | target/arm/tcg/translate-a64.c | 20 ++++---------------- | ||
12 | 1 file changed, 4 insertions(+), 16 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/tcg/translate-a64.c | ||
17 | +++ b/target/arm/tcg/translate-a64.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static bool btype_destination_ok(uint32_t insn, bool bt, int btype) | ||
19 | static void disas_a64_legacy(DisasContext *s, uint32_t insn) | ||
20 | { | ||
21 | switch (extract32(insn, 25, 4)) { | ||
22 | - case 0x0: | ||
23 | - if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) { | ||
24 | - unallocated_encoding(s); | ||
25 | - } | ||
26 | - break; | ||
27 | - case 0x1: case 0x3: /* UNALLOCATED */ | ||
28 | - unallocated_encoding(s); | ||
29 | - break; | ||
30 | - case 0x2: | ||
31 | - if (!disas_sve(s, insn)) { | ||
32 | - unallocated_encoding(s); | ||
33 | - } | ||
34 | - break; | ||
35 | case 0x8: case 0x9: /* Data processing - immediate */ | ||
36 | disas_data_proc_imm(s, insn); | ||
37 | break; | ||
38 | @@ -XXX,XX +XXX,XX @@ static void disas_a64_legacy(DisasContext *s, uint32_t insn) | ||
39 | disas_data_proc_simd_fp(s, insn); | ||
40 | break; | ||
41 | default: | ||
42 | - assert(FALSE); /* all 15 cases should be handled above */ | ||
43 | + unallocated_encoding(s); | ||
44 | break; | ||
45 | } | ||
46 | } | ||
47 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
48 | disas_sme_fa64(s, insn); | ||
49 | } | ||
50 | |||
51 | - | ||
52 | - if (!disas_a64(s, insn)) { | ||
53 | + if (!disas_a64(s, insn) && | ||
54 | + !disas_sme(s, insn) && | ||
55 | + !disas_sve(s, insn)) { | ||
56 | disas_a64_legacy(s, insn); | ||
57 | } | ||
58 | |||
59 | -- | ||
60 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Convert the ADR and ADRP instructions. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20230512144106.3608981-5-peter.maydell@linaro.org | ||
9 | [PMM: Rebased] | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | target/arm/tcg/a64.decode | 13 ++++++++++++ | ||
14 | target/arm/tcg/translate-a64.c | 38 +++++++++++++--------------------- | ||
15 | 2 files changed, 27 insertions(+), 24 deletions(-) | ||
16 | |||
17 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/tcg/a64.decode | ||
20 | +++ b/target/arm/tcg/a64.decode | ||
21 | @@ -XXX,XX +XXX,XX @@ | ||
22 | # | ||
23 | # This file is processed by scripts/decodetree.py | ||
24 | # | ||
25 | + | ||
26 | +&ri rd imm | ||
27 | + | ||
28 | + | ||
29 | +### Data Processing - Immediate | ||
30 | + | ||
31 | +# PC-rel addressing | ||
32 | + | ||
33 | +%imm_pcrel 5:s19 29:2 | ||
34 | +@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel | ||
35 | + | ||
36 | +ADR 0 .. 10000 ................... ..... @pcrel | ||
37 | +ADRP 1 .. 10000 ................... ..... @pcrel | ||
38 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/target/arm/tcg/translate-a64.c | ||
41 | +++ b/target/arm/tcg/translate-a64.c | ||
42 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst(DisasContext *s, uint32_t insn) | ||
43 | } | ||
44 | } | ||
45 | |||
46 | -/* PC-rel. addressing | ||
47 | - * 31 30 29 28 24 23 5 4 0 | ||
48 | - * +----+-------+-----------+-------------------+------+ | ||
49 | - * | op | immlo | 1 0 0 0 0 | immhi | Rd | | ||
50 | - * +----+-------+-----------+-------------------+------+ | ||
51 | +/* | ||
52 | + * PC-rel. addressing | ||
53 | */ | ||
54 | -static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) | ||
55 | + | ||
56 | +static bool trans_ADR(DisasContext *s, arg_ri *a) | ||
57 | { | ||
58 | - unsigned int page, rd; | ||
59 | - int64_t offset; | ||
60 | + gen_pc_plus_diff(s, cpu_reg(s, a->rd), a->imm); | ||
61 | + return true; | ||
62 | +} | ||
63 | |||
64 | - page = extract32(insn, 31, 1); | ||
65 | - /* SignExtend(immhi:immlo) -> offset */ | ||
66 | - offset = sextract64(insn, 5, 19); | ||
67 | - offset = offset << 2 | extract32(insn, 29, 2); | ||
68 | - rd = extract32(insn, 0, 5); | ||
69 | +static bool trans_ADRP(DisasContext *s, arg_ri *a) | ||
70 | +{ | ||
71 | + int64_t offset = (int64_t)a->imm << 12; | ||
72 | |||
73 | - if (page) { | ||
74 | - /* ADRP (page based) */ | ||
75 | - offset <<= 12; | ||
76 | - /* The page offset is ok for CF_PCREL. */ | ||
77 | - offset -= s->pc_curr & 0xfff; | ||
78 | - } | ||
79 | - | ||
80 | - gen_pc_plus_diff(s, cpu_reg(s, rd), offset); | ||
81 | + /* The page offset is ok for CF_PCREL. */ | ||
82 | + offset -= s->pc_curr & 0xfff; | ||
83 | + gen_pc_plus_diff(s, cpu_reg(s, a->rd), offset); | ||
84 | + return true; | ||
85 | } | ||
86 | |||
87 | /* | ||
88 | @@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn) | ||
89 | static void disas_data_proc_imm(DisasContext *s, uint32_t insn) | ||
90 | { | ||
91 | switch (extract32(insn, 23, 6)) { | ||
92 | - case 0x20: case 0x21: /* PC-rel. addressing */ | ||
93 | - disas_pc_rel_adr(s, insn); | ||
94 | - break; | ||
95 | case 0x22: /* Add/subtract (immediate) */ | ||
96 | disas_add_sub_imm(s, insn); | ||
97 | break; | ||
98 | -- | ||
99 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Split out specific 32-bit and 64-bit functions. | ||
4 | These carry the same signature as tcg_gen_add_i64, | ||
5 | and so will be easier to pass as callbacks. | ||
6 | |||
7 | Retain gen_add_CC and gen_sub_CC during conversion. | ||
8 | |||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Message-id: 20230512144106.3608981-6-peter.maydell@linaro.org | ||
13 | [PMM: rebased] | ||
14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | --- | ||
17 | target/arm/tcg/translate-a64.c | 149 +++++++++++++++++++-------------- | ||
18 | 1 file changed, 84 insertions(+), 65 deletions(-) | ||
19 | |||
20 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/target/arm/tcg/translate-a64.c | ||
23 | +++ b/target/arm/tcg/translate-a64.c | ||
24 | @@ -XXX,XX +XXX,XX @@ static inline void gen_logic_CC(int sf, TCGv_i64 result) | ||
25 | } | ||
26 | |||
27 | /* dest = T0 + T1; compute C, N, V and Z flags */ | ||
28 | +static void gen_add64_CC(TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | ||
29 | +{ | ||
30 | + TCGv_i64 result, flag, tmp; | ||
31 | + result = tcg_temp_new_i64(); | ||
32 | + flag = tcg_temp_new_i64(); | ||
33 | + tmp = tcg_temp_new_i64(); | ||
34 | + | ||
35 | + tcg_gen_movi_i64(tmp, 0); | ||
36 | + tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp); | ||
37 | + | ||
38 | + tcg_gen_extrl_i64_i32(cpu_CF, flag); | ||
39 | + | ||
40 | + gen_set_NZ64(result); | ||
41 | + | ||
42 | + tcg_gen_xor_i64(flag, result, t0); | ||
43 | + tcg_gen_xor_i64(tmp, t0, t1); | ||
44 | + tcg_gen_andc_i64(flag, flag, tmp); | ||
45 | + tcg_gen_extrh_i64_i32(cpu_VF, flag); | ||
46 | + | ||
47 | + tcg_gen_mov_i64(dest, result); | ||
48 | +} | ||
49 | + | ||
50 | +static void gen_add32_CC(TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | ||
51 | +{ | ||
52 | + TCGv_i32 t0_32 = tcg_temp_new_i32(); | ||
53 | + TCGv_i32 t1_32 = tcg_temp_new_i32(); | ||
54 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
55 | + | ||
56 | + tcg_gen_movi_i32(tmp, 0); | ||
57 | + tcg_gen_extrl_i64_i32(t0_32, t0); | ||
58 | + tcg_gen_extrl_i64_i32(t1_32, t1); | ||
59 | + tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp); | ||
60 | + tcg_gen_mov_i32(cpu_ZF, cpu_NF); | ||
61 | + tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | ||
62 | + tcg_gen_xor_i32(tmp, t0_32, t1_32); | ||
63 | + tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); | ||
64 | + tcg_gen_extu_i32_i64(dest, cpu_NF); | ||
65 | +} | ||
66 | + | ||
67 | static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | ||
68 | { | ||
69 | if (sf) { | ||
70 | - TCGv_i64 result, flag, tmp; | ||
71 | - result = tcg_temp_new_i64(); | ||
72 | - flag = tcg_temp_new_i64(); | ||
73 | - tmp = tcg_temp_new_i64(); | ||
74 | - | ||
75 | - tcg_gen_movi_i64(tmp, 0); | ||
76 | - tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp); | ||
77 | - | ||
78 | - tcg_gen_extrl_i64_i32(cpu_CF, flag); | ||
79 | - | ||
80 | - gen_set_NZ64(result); | ||
81 | - | ||
82 | - tcg_gen_xor_i64(flag, result, t0); | ||
83 | - tcg_gen_xor_i64(tmp, t0, t1); | ||
84 | - tcg_gen_andc_i64(flag, flag, tmp); | ||
85 | - tcg_gen_extrh_i64_i32(cpu_VF, flag); | ||
86 | - | ||
87 | - tcg_gen_mov_i64(dest, result); | ||
88 | + gen_add64_CC(dest, t0, t1); | ||
89 | } else { | ||
90 | - /* 32 bit arithmetic */ | ||
91 | - TCGv_i32 t0_32 = tcg_temp_new_i32(); | ||
92 | - TCGv_i32 t1_32 = tcg_temp_new_i32(); | ||
93 | - TCGv_i32 tmp = tcg_temp_new_i32(); | ||
94 | - | ||
95 | - tcg_gen_movi_i32(tmp, 0); | ||
96 | - tcg_gen_extrl_i64_i32(t0_32, t0); | ||
97 | - tcg_gen_extrl_i64_i32(t1_32, t1); | ||
98 | - tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp); | ||
99 | - tcg_gen_mov_i32(cpu_ZF, cpu_NF); | ||
100 | - tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | ||
101 | - tcg_gen_xor_i32(tmp, t0_32, t1_32); | ||
102 | - tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); | ||
103 | - tcg_gen_extu_i32_i64(dest, cpu_NF); | ||
104 | + gen_add32_CC(dest, t0, t1); | ||
105 | } | ||
106 | } | ||
107 | |||
108 | /* dest = T0 - T1; compute C, N, V and Z flags */ | ||
109 | +static void gen_sub64_CC(TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | ||
110 | +{ | ||
111 | + /* 64 bit arithmetic */ | ||
112 | + TCGv_i64 result, flag, tmp; | ||
113 | + | ||
114 | + result = tcg_temp_new_i64(); | ||
115 | + flag = tcg_temp_new_i64(); | ||
116 | + tcg_gen_sub_i64(result, t0, t1); | ||
117 | + | ||
118 | + gen_set_NZ64(result); | ||
119 | + | ||
120 | + tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1); | ||
121 | + tcg_gen_extrl_i64_i32(cpu_CF, flag); | ||
122 | + | ||
123 | + tcg_gen_xor_i64(flag, result, t0); | ||
124 | + tmp = tcg_temp_new_i64(); | ||
125 | + tcg_gen_xor_i64(tmp, t0, t1); | ||
126 | + tcg_gen_and_i64(flag, flag, tmp); | ||
127 | + tcg_gen_extrh_i64_i32(cpu_VF, flag); | ||
128 | + tcg_gen_mov_i64(dest, result); | ||
129 | +} | ||
130 | + | ||
131 | +static void gen_sub32_CC(TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | ||
132 | +{ | ||
133 | + /* 32 bit arithmetic */ | ||
134 | + TCGv_i32 t0_32 = tcg_temp_new_i32(); | ||
135 | + TCGv_i32 t1_32 = tcg_temp_new_i32(); | ||
136 | + TCGv_i32 tmp; | ||
137 | + | ||
138 | + tcg_gen_extrl_i64_i32(t0_32, t0); | ||
139 | + tcg_gen_extrl_i64_i32(t1_32, t1); | ||
140 | + tcg_gen_sub_i32(cpu_NF, t0_32, t1_32); | ||
141 | + tcg_gen_mov_i32(cpu_ZF, cpu_NF); | ||
142 | + tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32); | ||
143 | + tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | ||
144 | + tmp = tcg_temp_new_i32(); | ||
145 | + tcg_gen_xor_i32(tmp, t0_32, t1_32); | ||
146 | + tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); | ||
147 | + tcg_gen_extu_i32_i64(dest, cpu_NF); | ||
148 | +} | ||
149 | + | ||
150 | static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | ||
151 | { | ||
152 | if (sf) { | ||
153 | - /* 64 bit arithmetic */ | ||
154 | - TCGv_i64 result, flag, tmp; | ||
155 | - | ||
156 | - result = tcg_temp_new_i64(); | ||
157 | - flag = tcg_temp_new_i64(); | ||
158 | - tcg_gen_sub_i64(result, t0, t1); | ||
159 | - | ||
160 | - gen_set_NZ64(result); | ||
161 | - | ||
162 | - tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1); | ||
163 | - tcg_gen_extrl_i64_i32(cpu_CF, flag); | ||
164 | - | ||
165 | - tcg_gen_xor_i64(flag, result, t0); | ||
166 | - tmp = tcg_temp_new_i64(); | ||
167 | - tcg_gen_xor_i64(tmp, t0, t1); | ||
168 | - tcg_gen_and_i64(flag, flag, tmp); | ||
169 | - tcg_gen_extrh_i64_i32(cpu_VF, flag); | ||
170 | - tcg_gen_mov_i64(dest, result); | ||
171 | + gen_sub64_CC(dest, t0, t1); | ||
172 | } else { | ||
173 | - /* 32 bit arithmetic */ | ||
174 | - TCGv_i32 t0_32 = tcg_temp_new_i32(); | ||
175 | - TCGv_i32 t1_32 = tcg_temp_new_i32(); | ||
176 | - TCGv_i32 tmp; | ||
177 | - | ||
178 | - tcg_gen_extrl_i64_i32(t0_32, t0); | ||
179 | - tcg_gen_extrl_i64_i32(t1_32, t1); | ||
180 | - tcg_gen_sub_i32(cpu_NF, t0_32, t1_32); | ||
181 | - tcg_gen_mov_i32(cpu_ZF, cpu_NF); | ||
182 | - tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32); | ||
183 | - tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | ||
184 | - tmp = tcg_temp_new_i32(); | ||
185 | - tcg_gen_xor_i32(tmp, t0_32, t1_32); | ||
186 | - tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); | ||
187 | - tcg_gen_extu_i32_i64(dest, cpu_NF); | ||
188 | + gen_sub32_CC(dest, t0, t1); | ||
189 | } | ||
190 | } | ||
191 | |||
192 | -- | ||
193 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Convert the ADD and SUB (immediate) instructions. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20230512144106.3608981-7-peter.maydell@linaro.org | ||
9 | [PMM: Rebased; adjusted to use translate.h's TRANS macro] | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | target/arm/tcg/translate.h | 5 +++ | ||
14 | target/arm/tcg/a64.decode | 17 ++++++++ | ||
15 | target/arm/tcg/translate-a64.c | 73 ++++++++++------------------------ | ||
16 | 3 files changed, 42 insertions(+), 53 deletions(-) | ||
17 | |||
18 | diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/arm/tcg/translate.h | ||
21 | +++ b/target/arm/tcg/translate.h | ||
22 | @@ -XXX,XX +XXX,XX @@ static inline int rsub_8(DisasContext *s, int x) | ||
23 | return 8 - x; | ||
24 | } | ||
25 | |||
26 | +static inline int shl_12(DisasContext *s, int x) | ||
27 | +{ | ||
28 | + return x << 12; | ||
29 | +} | ||
30 | + | ||
31 | static inline int neon_3same_fp_size(DisasContext *s, int x) | ||
32 | { | ||
33 | /* Convert 0==fp32, 1==fp16 into a MO_* value */ | ||
34 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/target/arm/tcg/a64.decode | ||
37 | +++ b/target/arm/tcg/a64.decode | ||
38 | @@ -XXX,XX +XXX,XX @@ | ||
39 | # | ||
40 | |||
41 | &ri rd imm | ||
42 | +&rri_sf rd rn imm sf | ||
43 | |||
44 | |||
45 | ### Data Processing - Immediate | ||
46 | @@ -XXX,XX +XXX,XX @@ | ||
47 | |||
48 | ADR 0 .. 10000 ................... ..... @pcrel | ||
49 | ADRP 1 .. 10000 ................... ..... @pcrel | ||
50 | + | ||
51 | +# Add/subtract (immediate) | ||
52 | + | ||
53 | +%imm12_sh12 10:12 !function=shl_12 | ||
54 | +@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5 | ||
55 | +@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12 | ||
56 | + | ||
57 | +ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm | ||
58 | +ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12 | ||
59 | +ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm | ||
60 | +ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12 | ||
61 | + | ||
62 | +SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm | ||
63 | +SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12 | ||
64 | +SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm | ||
65 | +SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 | ||
66 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/target/arm/tcg/translate-a64.c | ||
69 | +++ b/target/arm/tcg/translate-a64.c | ||
70 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst(DisasContext *s, uint32_t insn) | ||
71 | } | ||
72 | } | ||
73 | |||
74 | +typedef void ArithTwoOp(TCGv_i64, TCGv_i64, TCGv_i64); | ||
75 | + | ||
76 | +static bool gen_rri(DisasContext *s, arg_rri_sf *a, | ||
77 | + bool rd_sp, bool rn_sp, ArithTwoOp *fn) | ||
78 | +{ | ||
79 | + TCGv_i64 tcg_rn = rn_sp ? cpu_reg_sp(s, a->rn) : cpu_reg(s, a->rn); | ||
80 | + TCGv_i64 tcg_rd = rd_sp ? cpu_reg_sp(s, a->rd) : cpu_reg(s, a->rd); | ||
81 | + TCGv_i64 tcg_imm = tcg_constant_i64(a->imm); | ||
82 | + | ||
83 | + fn(tcg_rd, tcg_rn, tcg_imm); | ||
84 | + if (!a->sf) { | ||
85 | + tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | ||
86 | + } | ||
87 | + return true; | ||
88 | +} | ||
89 | + | ||
90 | /* | ||
91 | * PC-rel. addressing | ||
92 | */ | ||
93 | @@ -XXX,XX +XXX,XX @@ static bool trans_ADRP(DisasContext *s, arg_ri *a) | ||
94 | |||
95 | /* | ||
96 | * Add/subtract (immediate) | ||
97 | - * | ||
98 | - * 31 30 29 28 23 22 21 10 9 5 4 0 | ||
99 | - * +--+--+--+-------------+--+-------------+-----+-----+ | ||
100 | - * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd | | ||
101 | - * +--+--+--+-------------+--+-------------+-----+-----+ | ||
102 | - * | ||
103 | - * sf: 0 -> 32bit, 1 -> 64bit | ||
104 | - * op: 0 -> add , 1 -> sub | ||
105 | - * S: 1 -> set flags | ||
106 | - * sh: 1 -> LSL imm by 12 | ||
107 | */ | ||
108 | -static void disas_add_sub_imm(DisasContext *s, uint32_t insn) | ||
109 | -{ | ||
110 | - int rd = extract32(insn, 0, 5); | ||
111 | - int rn = extract32(insn, 5, 5); | ||
112 | - uint64_t imm = extract32(insn, 10, 12); | ||
113 | - bool shift = extract32(insn, 22, 1); | ||
114 | - bool setflags = extract32(insn, 29, 1); | ||
115 | - bool sub_op = extract32(insn, 30, 1); | ||
116 | - bool is_64bit = extract32(insn, 31, 1); | ||
117 | - | ||
118 | - TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | ||
119 | - TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); | ||
120 | - TCGv_i64 tcg_result; | ||
121 | - | ||
122 | - if (shift) { | ||
123 | - imm <<= 12; | ||
124 | - } | ||
125 | - | ||
126 | - tcg_result = tcg_temp_new_i64(); | ||
127 | - if (!setflags) { | ||
128 | - if (sub_op) { | ||
129 | - tcg_gen_subi_i64(tcg_result, tcg_rn, imm); | ||
130 | - } else { | ||
131 | - tcg_gen_addi_i64(tcg_result, tcg_rn, imm); | ||
132 | - } | ||
133 | - } else { | ||
134 | - TCGv_i64 tcg_imm = tcg_constant_i64(imm); | ||
135 | - if (sub_op) { | ||
136 | - gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | ||
137 | - } else { | ||
138 | - gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | ||
139 | - } | ||
140 | - } | ||
141 | - | ||
142 | - if (is_64bit) { | ||
143 | - tcg_gen_mov_i64(tcg_rd, tcg_result); | ||
144 | - } else { | ||
145 | - tcg_gen_ext32u_i64(tcg_rd, tcg_result); | ||
146 | - } | ||
147 | -} | ||
148 | +TRANS(ADD_i, gen_rri, a, 1, 1, tcg_gen_add_i64) | ||
149 | +TRANS(SUB_i, gen_rri, a, 1, 1, tcg_gen_sub_i64) | ||
150 | +TRANS(ADDS_i, gen_rri, a, 0, 1, a->sf ? gen_add64_CC : gen_add32_CC) | ||
151 | +TRANS(SUBS_i, gen_rri, a, 0, 1, a->sf ? gen_sub64_CC : gen_sub32_CC) | ||
152 | |||
153 | /* | ||
154 | * Add/subtract (immediate, with tags) | ||
155 | @@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn) | ||
156 | static void disas_data_proc_imm(DisasContext *s, uint32_t insn) | ||
157 | { | ||
158 | switch (extract32(insn, 23, 6)) { | ||
159 | - case 0x22: /* Add/subtract (immediate) */ | ||
160 | - disas_add_sub_imm(s, insn); | ||
161 | - break; | ||
162 | case 0x23: /* Add/subtract (immediate, with tags) */ | ||
163 | disas_add_sub_imm_with_tags(s, insn); | ||
164 | break; | ||
165 | -- | ||
166 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Convert the ADDG and SUBG (immediate) instructions. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20230512144106.3608981-8-peter.maydell@linaro.org | ||
9 | [PMM: Rebased; use TRANS_FEAT()] | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | target/arm/tcg/a64.decode | 8 +++++++ | ||
14 | target/arm/tcg/translate-a64.c | 38 ++++++++++------------------------ | ||
15 | 2 files changed, 19 insertions(+), 27 deletions(-) | ||
16 | |||
17 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/tcg/a64.decode | ||
20 | +++ b/target/arm/tcg/a64.decode | ||
21 | @@ -XXX,XX +XXX,XX @@ SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm | ||
22 | SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12 | ||
23 | SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm | ||
24 | SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 | ||
25 | + | ||
26 | +# Add/subtract (immediate with tags) | ||
27 | + | ||
28 | +&rri_tag rd rn uimm6 uimm4 | ||
29 | +@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag | ||
30 | + | ||
31 | +ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag | ||
32 | +SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag | ||
33 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/arm/tcg/translate-a64.c | ||
36 | +++ b/target/arm/tcg/translate-a64.c | ||
37 | @@ -XXX,XX +XXX,XX @@ TRANS(SUBS_i, gen_rri, a, 0, 1, a->sf ? gen_sub64_CC : gen_sub32_CC) | ||
38 | |||
39 | /* | ||
40 | * Add/subtract (immediate, with tags) | ||
41 | - * | ||
42 | - * 31 30 29 28 23 22 21 16 14 10 9 5 4 0 | ||
43 | - * +--+--+--+-------------+--+---------+--+-------+-----+-----+ | ||
44 | - * |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd | | ||
45 | - * +--+--+--+-------------+--+---------+--+-------+-----+-----+ | ||
46 | - * | ||
47 | - * op: 0 -> add, 1 -> sub | ||
48 | */ | ||
49 | -static void disas_add_sub_imm_with_tags(DisasContext *s, uint32_t insn) | ||
50 | + | ||
51 | +static bool gen_add_sub_imm_with_tags(DisasContext *s, arg_rri_tag *a, | ||
52 | + bool sub_op) | ||
53 | { | ||
54 | - int rd = extract32(insn, 0, 5); | ||
55 | - int rn = extract32(insn, 5, 5); | ||
56 | - int uimm4 = extract32(insn, 10, 4); | ||
57 | - int uimm6 = extract32(insn, 16, 6); | ||
58 | - bool sub_op = extract32(insn, 30, 1); | ||
59 | TCGv_i64 tcg_rn, tcg_rd; | ||
60 | int imm; | ||
61 | |||
62 | - /* Test all of sf=1, S=0, o2=0, o3=0. */ | ||
63 | - if ((insn & 0xa040c000u) != 0x80000000u || | ||
64 | - !dc_isar_feature(aa64_mte_insn_reg, s)) { | ||
65 | - unallocated_encoding(s); | ||
66 | - return; | ||
67 | - } | ||
68 | - | ||
69 | - imm = uimm6 << LOG2_TAG_GRANULE; | ||
70 | + imm = a->uimm6 << LOG2_TAG_GRANULE; | ||
71 | if (sub_op) { | ||
72 | imm = -imm; | ||
73 | } | ||
74 | |||
75 | - tcg_rn = cpu_reg_sp(s, rn); | ||
76 | - tcg_rd = cpu_reg_sp(s, rd); | ||
77 | + tcg_rn = cpu_reg_sp(s, a->rn); | ||
78 | + tcg_rd = cpu_reg_sp(s, a->rd); | ||
79 | |||
80 | if (s->ata) { | ||
81 | gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn, | ||
82 | tcg_constant_i32(imm), | ||
83 | - tcg_constant_i32(uimm4)); | ||
84 | + tcg_constant_i32(a->uimm4)); | ||
85 | } else { | ||
86 | tcg_gen_addi_i64(tcg_rd, tcg_rn, imm); | ||
87 | gen_address_with_allocation_tag0(tcg_rd, tcg_rd); | ||
88 | } | ||
89 | + return true; | ||
90 | } | ||
91 | |||
92 | +TRANS_FEAT(ADDG_i, aa64_mte_insn_reg, gen_add_sub_imm_with_tags, a, false) | ||
93 | +TRANS_FEAT(SUBG_i, aa64_mte_insn_reg, gen_add_sub_imm_with_tags, a, true) | ||
94 | + | ||
95 | /* The input should be a value in the bottom e bits (with higher | ||
96 | * bits zero); returns that value replicated into every element | ||
97 | * of size e in a 64 bit integer. | ||
98 | @@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn) | ||
99 | static void disas_data_proc_imm(DisasContext *s, uint32_t insn) | ||
100 | { | ||
101 | switch (extract32(insn, 23, 6)) { | ||
102 | - case 0x23: /* Add/subtract (immediate, with tags) */ | ||
103 | - disas_add_sub_imm_with_tags(s, insn); | ||
104 | - break; | ||
105 | case 0x24: /* Logical (immediate) */ | ||
106 | disas_logic_imm(s, insn); | ||
107 | break; | ||
108 | -- | ||
109 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Use the bitops.h macro rather than rolling our own here. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20230512144106.3608981-9-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/tcg/translate-a64.c | 11 ++--------- | ||
11 | 1 file changed, 2 insertions(+), 9 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/tcg/translate-a64.c | ||
16 | +++ b/target/arm/tcg/translate-a64.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static uint64_t bitfield_replicate(uint64_t mask, unsigned int e) | ||
18 | return mask; | ||
19 | } | ||
20 | |||
21 | -/* Return a value with the bottom len bits set (where 0 < len <= 64) */ | ||
22 | -static inline uint64_t bitmask64(unsigned int length) | ||
23 | -{ | ||
24 | - assert(length > 0 && length <= 64); | ||
25 | - return ~0ULL >> (64 - length); | ||
26 | -} | ||
27 | - | ||
28 | /* Simplified variant of pseudocode DecodeBitMasks() for the case where we | ||
29 | * only require the wmask. Returns false if the imms/immr/immn are a reserved | ||
30 | * value (ie should cause a guest UNDEF exception), and true if they are | ||
31 | @@ -XXX,XX +XXX,XX @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, | ||
32 | /* Create the value of one element: s+1 set bits rotated | ||
33 | * by r within the element (which is e bits wide)... | ||
34 | */ | ||
35 | - mask = bitmask64(s + 1); | ||
36 | + mask = MAKE_64BIT_MASK(0, s + 1); | ||
37 | if (r) { | ||
38 | mask = (mask >> r) | (mask << (e - r)); | ||
39 | - mask &= bitmask64(e); | ||
40 | + mask &= MAKE_64BIT_MASK(0, e); | ||
41 | } | ||
42 | /* ...then replicate the element over the whole 64 bit value */ | ||
43 | mask = bitfield_replicate(mask, e); | ||
44 | -- | ||
45 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Convert the ADD, ORR, EOR, ANDS (immediate) instructions. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20230512144106.3608981-10-peter.maydell@linaro.org | ||
9 | [PMM: rebased] | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/tcg/a64.decode | 15 ++++++ | ||
13 | target/arm/tcg/translate-a64.c | 94 +++++++++++----------------------- | ||
14 | 2 files changed, 44 insertions(+), 65 deletions(-) | ||
15 | |||
16 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/tcg/a64.decode | ||
19 | +++ b/target/arm/tcg/a64.decode | ||
20 | @@ -XXX,XX +XXX,XX @@ SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 | ||
21 | |||
22 | ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag | ||
23 | SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag | ||
24 | + | ||
25 | +# Logical (immediate) | ||
26 | + | ||
27 | +&rri_log rd rn sf dbm | ||
28 | +@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1 | ||
29 | +@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0 | ||
30 | + | ||
31 | +AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64 | ||
32 | +AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32 | ||
33 | +ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64 | ||
34 | +ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32 | ||
35 | +EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64 | ||
36 | +EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 | ||
37 | +ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 | ||
38 | +ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 | ||
39 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
40 | index XXXXXXX..XXXXXXX 100644 | ||
41 | --- a/target/arm/tcg/translate-a64.c | ||
42 | +++ b/target/arm/tcg/translate-a64.c | ||
43 | @@ -XXX,XX +XXX,XX @@ static uint64_t bitfield_replicate(uint64_t mask, unsigned int e) | ||
44 | return mask; | ||
45 | } | ||
46 | |||
47 | -/* Simplified variant of pseudocode DecodeBitMasks() for the case where we | ||
48 | +/* | ||
49 | + * Logical (immediate) | ||
50 | + */ | ||
51 | + | ||
52 | +/* | ||
53 | + * Simplified variant of pseudocode DecodeBitMasks() for the case where we | ||
54 | * only require the wmask. Returns false if the imms/immr/immn are a reserved | ||
55 | * value (ie should cause a guest UNDEF exception), and true if they are | ||
56 | * valid, in which case the decoded bit pattern is written to result. | ||
57 | @@ -XXX,XX +XXX,XX @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, | ||
58 | return true; | ||
59 | } | ||
60 | |||
61 | -/* Logical (immediate) | ||
62 | - * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 | ||
63 | - * +----+-----+-------------+---+------+------+------+------+ | ||
64 | - * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd | | ||
65 | - * +----+-----+-------------+---+------+------+------+------+ | ||
66 | - */ | ||
67 | -static void disas_logic_imm(DisasContext *s, uint32_t insn) | ||
68 | +static bool gen_rri_log(DisasContext *s, arg_rri_log *a, bool set_cc, | ||
69 | + void (*fn)(TCGv_i64, TCGv_i64, int64_t)) | ||
70 | { | ||
71 | - unsigned int sf, opc, is_n, immr, imms, rn, rd; | ||
72 | TCGv_i64 tcg_rd, tcg_rn; | ||
73 | - uint64_t wmask; | ||
74 | - bool is_and = false; | ||
75 | + uint64_t imm; | ||
76 | |||
77 | - sf = extract32(insn, 31, 1); | ||
78 | - opc = extract32(insn, 29, 2); | ||
79 | - is_n = extract32(insn, 22, 1); | ||
80 | - immr = extract32(insn, 16, 6); | ||
81 | - imms = extract32(insn, 10, 6); | ||
82 | - rn = extract32(insn, 5, 5); | ||
83 | - rd = extract32(insn, 0, 5); | ||
84 | - | ||
85 | - if (!sf && is_n) { | ||
86 | - unallocated_encoding(s); | ||
87 | - return; | ||
88 | + /* Some immediate field values are reserved. */ | ||
89 | + if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1), | ||
90 | + extract32(a->dbm, 0, 6), | ||
91 | + extract32(a->dbm, 6, 6))) { | ||
92 | + return false; | ||
93 | + } | ||
94 | + if (!a->sf) { | ||
95 | + imm &= 0xffffffffull; | ||
96 | } | ||
97 | |||
98 | - if (opc == 0x3) { /* ANDS */ | ||
99 | - tcg_rd = cpu_reg(s, rd); | ||
100 | - } else { | ||
101 | - tcg_rd = cpu_reg_sp(s, rd); | ||
102 | - } | ||
103 | - tcg_rn = cpu_reg(s, rn); | ||
104 | + tcg_rd = set_cc ? cpu_reg(s, a->rd) : cpu_reg_sp(s, a->rd); | ||
105 | + tcg_rn = cpu_reg(s, a->rn); | ||
106 | |||
107 | - if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) { | ||
108 | - /* some immediate field values are reserved */ | ||
109 | - unallocated_encoding(s); | ||
110 | - return; | ||
111 | + fn(tcg_rd, tcg_rn, imm); | ||
112 | + if (set_cc) { | ||
113 | + gen_logic_CC(a->sf, tcg_rd); | ||
114 | } | ||
115 | - | ||
116 | - if (!sf) { | ||
117 | - wmask &= 0xffffffff; | ||
118 | - } | ||
119 | - | ||
120 | - switch (opc) { | ||
121 | - case 0x3: /* ANDS */ | ||
122 | - case 0x0: /* AND */ | ||
123 | - tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask); | ||
124 | - is_and = true; | ||
125 | - break; | ||
126 | - case 0x1: /* ORR */ | ||
127 | - tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask); | ||
128 | - break; | ||
129 | - case 0x2: /* EOR */ | ||
130 | - tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask); | ||
131 | - break; | ||
132 | - default: | ||
133 | - assert(FALSE); /* must handle all above */ | ||
134 | - break; | ||
135 | - } | ||
136 | - | ||
137 | - if (!sf && !is_and) { | ||
138 | - /* zero extend final result; we know we can skip this for AND | ||
139 | - * since the immediate had the high 32 bits clear. | ||
140 | - */ | ||
141 | + if (!a->sf) { | ||
142 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | ||
143 | } | ||
144 | - | ||
145 | - if (opc == 3) { /* ANDS */ | ||
146 | - gen_logic_CC(sf, tcg_rd); | ||
147 | - } | ||
148 | + return true; | ||
149 | } | ||
150 | |||
151 | +TRANS(AND_i, gen_rri_log, a, false, tcg_gen_andi_i64) | ||
152 | +TRANS(ORR_i, gen_rri_log, a, false, tcg_gen_ori_i64) | ||
153 | +TRANS(EOR_i, gen_rri_log, a, false, tcg_gen_xori_i64) | ||
154 | +TRANS(ANDS_i, gen_rri_log, a, true, tcg_gen_andi_i64) | ||
155 | + | ||
156 | /* | ||
157 | * Move wide (immediate) | ||
158 | * | ||
159 | @@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn) | ||
160 | static void disas_data_proc_imm(DisasContext *s, uint32_t insn) | ||
161 | { | ||
162 | switch (extract32(insn, 23, 6)) { | ||
163 | - case 0x24: /* Logical (immediate) */ | ||
164 | - disas_logic_imm(s, insn); | ||
165 | - break; | ||
166 | case 0x25: /* Move wide (immediate) */ | ||
167 | disas_movw_imm(s, insn); | ||
168 | break; | ||
169 | -- | ||
170 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Convert the MON, MOVZ, MOVK instructions. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20230512144106.3608981-11-peter.maydell@linaro.org | ||
9 | [PMM: Rebased] | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | target/arm/tcg/a64.decode | 13 ++++++ | ||
14 | target/arm/tcg/translate-a64.c | 73 ++++++++++++++-------------------- | ||
15 | 2 files changed, 42 insertions(+), 44 deletions(-) | ||
16 | |||
17 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/tcg/a64.decode | ||
20 | +++ b/target/arm/tcg/a64.decode | ||
21 | @@ -XXX,XX +XXX,XX @@ EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64 | ||
22 | EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 | ||
23 | ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 | ||
24 | ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 | ||
25 | + | ||
26 | +# Move wide (immediate) | ||
27 | + | ||
28 | +&movw rd sf imm hw | ||
29 | +@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1 | ||
30 | +@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0 | ||
31 | + | ||
32 | +MOVN . 00 100101 .. ................ ..... @movw_64 | ||
33 | +MOVN . 00 100101 .. ................ ..... @movw_32 | ||
34 | +MOVZ . 10 100101 .. ................ ..... @movw_64 | ||
35 | +MOVZ . 10 100101 .. ................ ..... @movw_32 | ||
36 | +MOVK . 11 100101 .. ................ ..... @movw_64 | ||
37 | +MOVK . 11 100101 .. ................ ..... @movw_32 | ||
38 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/target/arm/tcg/translate-a64.c | ||
41 | +++ b/target/arm/tcg/translate-a64.c | ||
42 | @@ -XXX,XX +XXX,XX @@ TRANS(ANDS_i, gen_rri_log, a, true, tcg_gen_andi_i64) | ||
43 | |||
44 | /* | ||
45 | * Move wide (immediate) | ||
46 | - * | ||
47 | - * 31 30 29 28 23 22 21 20 5 4 0 | ||
48 | - * +--+-----+-------------+-----+----------------+------+ | ||
49 | - * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd | | ||
50 | - * +--+-----+-------------+-----+----------------+------+ | ||
51 | - * | ||
52 | - * sf: 0 -> 32 bit, 1 -> 64 bit | ||
53 | - * opc: 00 -> N, 10 -> Z, 11 -> K | ||
54 | - * hw: shift/16 (0,16, and sf only 32, 48) | ||
55 | */ | ||
56 | -static void disas_movw_imm(DisasContext *s, uint32_t insn) | ||
57 | + | ||
58 | +static bool trans_MOVZ(DisasContext *s, arg_movw *a) | ||
59 | { | ||
60 | - int rd = extract32(insn, 0, 5); | ||
61 | - uint64_t imm = extract32(insn, 5, 16); | ||
62 | - int sf = extract32(insn, 31, 1); | ||
63 | - int opc = extract32(insn, 29, 2); | ||
64 | - int pos = extract32(insn, 21, 2) << 4; | ||
65 | - TCGv_i64 tcg_rd = cpu_reg(s, rd); | ||
66 | + int pos = a->hw << 4; | ||
67 | + tcg_gen_movi_i64(cpu_reg(s, a->rd), (uint64_t)a->imm << pos); | ||
68 | + return true; | ||
69 | +} | ||
70 | |||
71 | - if (!sf && (pos >= 32)) { | ||
72 | - unallocated_encoding(s); | ||
73 | - return; | ||
74 | - } | ||
75 | +static bool trans_MOVN(DisasContext *s, arg_movw *a) | ||
76 | +{ | ||
77 | + int pos = a->hw << 4; | ||
78 | + uint64_t imm = a->imm; | ||
79 | |||
80 | - switch (opc) { | ||
81 | - case 0: /* MOVN */ | ||
82 | - case 2: /* MOVZ */ | ||
83 | - imm <<= pos; | ||
84 | - if (opc == 0) { | ||
85 | - imm = ~imm; | ||
86 | - } | ||
87 | - if (!sf) { | ||
88 | - imm &= 0xffffffffu; | ||
89 | - } | ||
90 | - tcg_gen_movi_i64(tcg_rd, imm); | ||
91 | - break; | ||
92 | - case 3: /* MOVK */ | ||
93 | - tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_constant_i64(imm), pos, 16); | ||
94 | - if (!sf) { | ||
95 | - tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | ||
96 | - } | ||
97 | - break; | ||
98 | - default: | ||
99 | - unallocated_encoding(s); | ||
100 | - break; | ||
101 | + imm = ~(imm << pos); | ||
102 | + if (!a->sf) { | ||
103 | + imm = (uint32_t)imm; | ||
104 | } | ||
105 | + tcg_gen_movi_i64(cpu_reg(s, a->rd), imm); | ||
106 | + return true; | ||
107 | +} | ||
108 | + | ||
109 | +static bool trans_MOVK(DisasContext *s, arg_movw *a) | ||
110 | +{ | ||
111 | + int pos = a->hw << 4; | ||
112 | + TCGv_i64 tcg_rd, tcg_im; | ||
113 | + | ||
114 | + tcg_rd = cpu_reg(s, a->rd); | ||
115 | + tcg_im = tcg_constant_i64(a->imm); | ||
116 | + tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_im, pos, 16); | ||
117 | + if (!a->sf) { | ||
118 | + tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | ||
119 | + } | ||
120 | + return true; | ||
121 | } | ||
122 | |||
123 | /* Bitfield | ||
124 | @@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn) | ||
125 | static void disas_data_proc_imm(DisasContext *s, uint32_t insn) | ||
126 | { | ||
127 | switch (extract32(insn, 23, 6)) { | ||
128 | - case 0x25: /* Move wide (immediate) */ | ||
129 | - disas_movw_imm(s, insn); | ||
130 | - break; | ||
131 | case 0x26: /* Bitfield */ | ||
132 | disas_bitfield(s, insn); | ||
133 | break; | ||
134 | -- | ||
135 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Convert the BFM, SBFM, UBFM instructions. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20230512144106.3608981-12-peter.maydell@linaro.org | ||
9 | [PMM: Rebased] | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/tcg/a64.decode | 13 +++ | ||
13 | target/arm/tcg/translate-a64.c | 144 ++++++++++++++++++--------------- | ||
14 | 2 files changed, 94 insertions(+), 63 deletions(-) | ||
15 | |||
16 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/tcg/a64.decode | ||
19 | +++ b/target/arm/tcg/a64.decode | ||
20 | @@ -XXX,XX +XXX,XX @@ MOVZ . 10 100101 .. ................ ..... @movw_64 | ||
21 | MOVZ . 10 100101 .. ................ ..... @movw_32 | ||
22 | MOVK . 11 100101 .. ................ ..... @movw_64 | ||
23 | MOVK . 11 100101 .. ................ ..... @movw_32 | ||
24 | + | ||
25 | +# Bitfield | ||
26 | + | ||
27 | +&bitfield rd rn sf immr imms | ||
28 | +@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1 | ||
29 | +@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0 | ||
30 | + | ||
31 | +SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64 | ||
32 | +SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32 | ||
33 | +BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 | ||
34 | +BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 | ||
35 | +UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 | ||
36 | +UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 | ||
37 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/tcg/translate-a64.c | ||
40 | +++ b/target/arm/tcg/translate-a64.c | ||
41 | @@ -XXX,XX +XXX,XX @@ static bool trans_MOVK(DisasContext *s, arg_movw *a) | ||
42 | return true; | ||
43 | } | ||
44 | |||
45 | -/* Bitfield | ||
46 | - * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 | ||
47 | - * +----+-----+-------------+---+------+------+------+------+ | ||
48 | - * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd | | ||
49 | - * +----+-----+-------------+---+------+------+------+------+ | ||
50 | +/* | ||
51 | + * Bitfield | ||
52 | */ | ||
53 | -static void disas_bitfield(DisasContext *s, uint32_t insn) | ||
54 | + | ||
55 | +static bool trans_SBFM(DisasContext *s, arg_SBFM *a) | ||
56 | { | ||
57 | - unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len; | ||
58 | - TCGv_i64 tcg_rd, tcg_tmp; | ||
59 | + TCGv_i64 tcg_rd = cpu_reg(s, a->rd); | ||
60 | + TCGv_i64 tcg_tmp = read_cpu_reg(s, a->rn, 1); | ||
61 | + unsigned int bitsize = a->sf ? 64 : 32; | ||
62 | + unsigned int ri = a->immr; | ||
63 | + unsigned int si = a->imms; | ||
64 | + unsigned int pos, len; | ||
65 | |||
66 | - sf = extract32(insn, 31, 1); | ||
67 | - opc = extract32(insn, 29, 2); | ||
68 | - n = extract32(insn, 22, 1); | ||
69 | - ri = extract32(insn, 16, 6); | ||
70 | - si = extract32(insn, 10, 6); | ||
71 | - rn = extract32(insn, 5, 5); | ||
72 | - rd = extract32(insn, 0, 5); | ||
73 | - bitsize = sf ? 64 : 32; | ||
74 | - | ||
75 | - if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) { | ||
76 | - unallocated_encoding(s); | ||
77 | - return; | ||
78 | - } | ||
79 | - | ||
80 | - tcg_rd = cpu_reg(s, rd); | ||
81 | - | ||
82 | - /* Suppress the zero-extend for !sf. Since RI and SI are constrained | ||
83 | - to be smaller than bitsize, we'll never reference data outside the | ||
84 | - low 32-bits anyway. */ | ||
85 | - tcg_tmp = read_cpu_reg(s, rn, 1); | ||
86 | - | ||
87 | - /* Recognize simple(r) extractions. */ | ||
88 | if (si >= ri) { | ||
89 | /* Wd<s-r:0> = Wn<s:r> */ | ||
90 | len = (si - ri) + 1; | ||
91 | - if (opc == 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */ | ||
92 | - tcg_gen_sextract_i64(tcg_rd, tcg_tmp, ri, len); | ||
93 | - goto done; | ||
94 | - } else if (opc == 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */ | ||
95 | - tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len); | ||
96 | - return; | ||
97 | + tcg_gen_sextract_i64(tcg_rd, tcg_tmp, ri, len); | ||
98 | + if (!a->sf) { | ||
99 | + tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | ||
100 | } | ||
101 | - /* opc == 1, BFXIL fall through to deposit */ | ||
102 | + } else { | ||
103 | + /* Wd<32+s-r,32-r> = Wn<s:0> */ | ||
104 | + len = si + 1; | ||
105 | + pos = (bitsize - ri) & (bitsize - 1); | ||
106 | + | ||
107 | + if (len < ri) { | ||
108 | + /* | ||
109 | + * Sign extend the destination field from len to fill the | ||
110 | + * balance of the word. Let the deposit below insert all | ||
111 | + * of those sign bits. | ||
112 | + */ | ||
113 | + tcg_gen_sextract_i64(tcg_tmp, tcg_tmp, 0, len); | ||
114 | + len = ri; | ||
115 | + } | ||
116 | + | ||
117 | + /* | ||
118 | + * We start with zero, and we haven't modified any bits outside | ||
119 | + * bitsize, therefore no final zero-extension is unneeded for !sf. | ||
120 | + */ | ||
121 | + tcg_gen_deposit_z_i64(tcg_rd, tcg_tmp, pos, len); | ||
122 | + } | ||
123 | + return true; | ||
124 | +} | ||
125 | + | ||
126 | +static bool trans_UBFM(DisasContext *s, arg_UBFM *a) | ||
127 | +{ | ||
128 | + TCGv_i64 tcg_rd = cpu_reg(s, a->rd); | ||
129 | + TCGv_i64 tcg_tmp = read_cpu_reg(s, a->rn, 1); | ||
130 | + unsigned int bitsize = a->sf ? 64 : 32; | ||
131 | + unsigned int ri = a->immr; | ||
132 | + unsigned int si = a->imms; | ||
133 | + unsigned int pos, len; | ||
134 | + | ||
135 | + tcg_rd = cpu_reg(s, a->rd); | ||
136 | + tcg_tmp = read_cpu_reg(s, a->rn, 1); | ||
137 | + | ||
138 | + if (si >= ri) { | ||
139 | + /* Wd<s-r:0> = Wn<s:r> */ | ||
140 | + len = (si - ri) + 1; | ||
141 | + tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len); | ||
142 | + } else { | ||
143 | + /* Wd<32+s-r,32-r> = Wn<s:0> */ | ||
144 | + len = si + 1; | ||
145 | + pos = (bitsize - ri) & (bitsize - 1); | ||
146 | + tcg_gen_deposit_z_i64(tcg_rd, tcg_tmp, pos, len); | ||
147 | + } | ||
148 | + return true; | ||
149 | +} | ||
150 | + | ||
151 | +static bool trans_BFM(DisasContext *s, arg_BFM *a) | ||
152 | +{ | ||
153 | + TCGv_i64 tcg_rd = cpu_reg(s, a->rd); | ||
154 | + TCGv_i64 tcg_tmp = read_cpu_reg(s, a->rn, 1); | ||
155 | + unsigned int bitsize = a->sf ? 64 : 32; | ||
156 | + unsigned int ri = a->immr; | ||
157 | + unsigned int si = a->imms; | ||
158 | + unsigned int pos, len; | ||
159 | + | ||
160 | + tcg_rd = cpu_reg(s, a->rd); | ||
161 | + tcg_tmp = read_cpu_reg(s, a->rn, 1); | ||
162 | + | ||
163 | + if (si >= ri) { | ||
164 | + /* Wd<s-r:0> = Wn<s:r> */ | ||
165 | tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri); | ||
166 | + len = (si - ri) + 1; | ||
167 | pos = 0; | ||
168 | } else { | ||
169 | - /* Handle the ri > si case with a deposit | ||
170 | - * Wd<32+s-r,32-r> = Wn<s:0> | ||
171 | - */ | ||
172 | + /* Wd<32+s-r,32-r> = Wn<s:0> */ | ||
173 | len = si + 1; | ||
174 | pos = (bitsize - ri) & (bitsize - 1); | ||
175 | } | ||
176 | |||
177 | - if (opc == 0 && len < ri) { | ||
178 | - /* SBFM: sign extend the destination field from len to fill | ||
179 | - the balance of the word. Let the deposit below insert all | ||
180 | - of those sign bits. */ | ||
181 | - tcg_gen_sextract_i64(tcg_tmp, tcg_tmp, 0, len); | ||
182 | - len = ri; | ||
183 | - } | ||
184 | - | ||
185 | - if (opc == 1) { /* BFM, BFXIL */ | ||
186 | - tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); | ||
187 | - } else { | ||
188 | - /* SBFM or UBFM: We start with zero, and we haven't modified | ||
189 | - any bits outside bitsize, therefore the zero-extension | ||
190 | - below is unneeded. */ | ||
191 | - tcg_gen_deposit_z_i64(tcg_rd, tcg_tmp, pos, len); | ||
192 | - return; | ||
193 | - } | ||
194 | - | ||
195 | - done: | ||
196 | - if (!sf) { /* zero extend final result */ | ||
197 | + tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); | ||
198 | + if (!a->sf) { | ||
199 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | ||
200 | } | ||
201 | + return true; | ||
202 | } | ||
203 | |||
204 | /* Extract | ||
205 | @@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn) | ||
206 | static void disas_data_proc_imm(DisasContext *s, uint32_t insn) | ||
207 | { | ||
208 | switch (extract32(insn, 23, 6)) { | ||
209 | - case 0x26: /* Bitfield */ | ||
210 | - disas_bitfield(s, insn); | ||
211 | - break; | ||
212 | case 0x27: /* Extract */ | ||
213 | disas_extract(s, insn); | ||
214 | break; | ||
215 | -- | ||
216 | 2.34.1 | diff view generated by jsdifflib |
1 | Rename the elf_low_addr and elf_high_addr variables to image_low_addr | 1 | Convert the EXTR instruction to decodetree (this is the |
---|---|---|---|
2 | and image_high_addr -- in the next commit we will extend them to | 2 | only one in the 'Extract" class). This is the last of |
3 | be set for other kinds of image file and not just ELF files. | 3 | the dp-immediate insns in the legacy decoder, so we |
4 | can now remove disas_data_proc_imm(). | ||
4 | 5 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 8 | Message-id: 20230512144106.3608981-13-peter.maydell@linaro.org |
8 | Tested-by: Mark Rutland <mark.rutland@arm.com> | ||
9 | Message-id: 20190722151804.25467-2-peter.maydell@linaro.org | ||
10 | --- | 9 | --- |
11 | hw/arm/boot.c | 20 +++++++++++--------- | 10 | target/arm/tcg/a64.decode | 7 +++ |
12 | 1 file changed, 11 insertions(+), 9 deletions(-) | 11 | target/arm/tcg/translate-a64.c | 94 +++++++++++----------------------- |
12 | 2 files changed, 36 insertions(+), 65 deletions(-) | ||
13 | 13 | ||
14 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | 14 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/arm/boot.c | 16 | --- a/target/arm/tcg/a64.decode |
17 | +++ b/hw/arm/boot.c | 17 | +++ b/target/arm/tcg/a64.decode |
18 | @@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, | 18 | @@ -XXX,XX +XXX,XX @@ BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 |
19 | int kernel_size; | 19 | BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 |
20 | int initrd_size; | 20 | UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 |
21 | int is_linux = 0; | 21 | UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 |
22 | - uint64_t elf_entry, elf_low_addr, elf_high_addr; | 22 | + |
23 | + uint64_t elf_entry; | 23 | +# Extract |
24 | + /* Addresses of first byte used and first byte not used by the image */ | 24 | + |
25 | + uint64_t image_low_addr, image_high_addr; | 25 | +&extract rd rn rm imm sf |
26 | int elf_machine; | 26 | + |
27 | hwaddr entry; | 27 | +EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1 |
28 | static const ARMInsnFixup *primary_loader; | 28 | +EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 |
29 | @@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, | 29 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c |
30 | info->nb_cpus = 1; | 30 | index XXXXXXX..XXXXXXX 100644 |
31 | 31 | --- a/target/arm/tcg/translate-a64.c | |
32 | /* Assume that raw images are linux kernels, and ELF images are not. */ | 32 | +++ b/target/arm/tcg/translate-a64.c |
33 | - kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, | 33 | @@ -XXX,XX +XXX,XX @@ static bool trans_BFM(DisasContext *s, arg_BFM *a) |
34 | - &elf_high_addr, elf_machine, as); | 34 | return true; |
35 | + kernel_size = arm_load_elf(info, &elf_entry, &image_low_addr, | 35 | } |
36 | + &image_high_addr, elf_machine, as); | 36 | |
37 | if (kernel_size > 0 && have_dtb(info)) { | 37 | -/* Extract |
38 | /* | 38 | - * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0 |
39 | * If there is still some room left at the base of RAM, try and put | 39 | - * +----+------+-------------+---+----+------+--------+------+------+ |
40 | * the DTB there like we do for images loaded with -bios or -pflash. | 40 | - * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd | |
41 | */ | 41 | - * +----+------+-------------+---+----+------+--------+------+------+ |
42 | - if (elf_low_addr > info->loader_start | 42 | - */ |
43 | - || elf_high_addr < info->loader_start) { | 43 | -static void disas_extract(DisasContext *s, uint32_t insn) |
44 | + if (image_low_addr > info->loader_start | 44 | +static bool trans_EXTR(DisasContext *s, arg_extract *a) |
45 | + || image_high_addr < info->loader_start) { | 45 | { |
46 | /* | 46 | - unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0; |
47 | - * Set elf_low_addr as address limit for arm_load_dtb if it may be | 47 | + TCGv_i64 tcg_rd, tcg_rm, tcg_rn; |
48 | + * Set image_low_addr as address limit for arm_load_dtb if it may be | 48 | |
49 | * pointing into RAM, otherwise pass '0' (no limit) | 49 | - sf = extract32(insn, 31, 1); |
50 | */ | 50 | - n = extract32(insn, 22, 1); |
51 | - if (elf_low_addr < info->loader_start) { | 51 | - rm = extract32(insn, 16, 5); |
52 | - elf_low_addr = 0; | 52 | - imm = extract32(insn, 10, 6); |
53 | + if (image_low_addr < info->loader_start) { | 53 | - rn = extract32(insn, 5, 5); |
54 | + image_low_addr = 0; | 54 | - rd = extract32(insn, 0, 5); |
55 | - op21 = extract32(insn, 29, 2); | ||
56 | - op0 = extract32(insn, 21, 1); | ||
57 | - bitsize = sf ? 64 : 32; | ||
58 | + tcg_rd = cpu_reg(s, a->rd); | ||
59 | |||
60 | - if (sf != n || op21 || op0 || imm >= bitsize) { | ||
61 | - unallocated_encoding(s); | ||
62 | - } else { | ||
63 | - TCGv_i64 tcg_rd, tcg_rm, tcg_rn; | ||
64 | - | ||
65 | - tcg_rd = cpu_reg(s, rd); | ||
66 | - | ||
67 | - if (unlikely(imm == 0)) { | ||
68 | - /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts, | ||
69 | - * so an extract from bit 0 is a special case. | ||
70 | - */ | ||
71 | - if (sf) { | ||
72 | - tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm)); | ||
73 | - } else { | ||
74 | - tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm)); | ||
75 | - } | ||
76 | + if (unlikely(a->imm == 0)) { | ||
77 | + /* | ||
78 | + * tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts, | ||
79 | + * so an extract from bit 0 is a special case. | ||
80 | + */ | ||
81 | + if (a->sf) { | ||
82 | + tcg_gen_mov_i64(tcg_rd, cpu_reg(s, a->rm)); | ||
83 | } else { | ||
84 | - tcg_rm = cpu_reg(s, rm); | ||
85 | - tcg_rn = cpu_reg(s, rn); | ||
86 | + tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, a->rm)); | ||
87 | + } | ||
88 | + } else { | ||
89 | + tcg_rm = cpu_reg(s, a->rm); | ||
90 | + tcg_rn = cpu_reg(s, a->rn); | ||
91 | |||
92 | - if (sf) { | ||
93 | - /* Specialization to ROR happens in EXTRACT2. */ | ||
94 | - tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm); | ||
95 | + if (a->sf) { | ||
96 | + /* Specialization to ROR happens in EXTRACT2. */ | ||
97 | + tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, a->imm); | ||
98 | + } else { | ||
99 | + TCGv_i32 t0 = tcg_temp_new_i32(); | ||
100 | + | ||
101 | + tcg_gen_extrl_i64_i32(t0, tcg_rm); | ||
102 | + if (a->rm == a->rn) { | ||
103 | + tcg_gen_rotri_i32(t0, t0, a->imm); | ||
104 | } else { | ||
105 | - TCGv_i32 t0 = tcg_temp_new_i32(); | ||
106 | - | ||
107 | - tcg_gen_extrl_i64_i32(t0, tcg_rm); | ||
108 | - if (rm == rn) { | ||
109 | - tcg_gen_rotri_i32(t0, t0, imm); | ||
110 | - } else { | ||
111 | - TCGv_i32 t1 = tcg_temp_new_i32(); | ||
112 | - tcg_gen_extrl_i64_i32(t1, tcg_rn); | ||
113 | - tcg_gen_extract2_i32(t0, t0, t1, imm); | ||
114 | - } | ||
115 | - tcg_gen_extu_i32_i64(tcg_rd, t0); | ||
116 | + TCGv_i32 t1 = tcg_temp_new_i32(); | ||
117 | + tcg_gen_extrl_i64_i32(t1, tcg_rn); | ||
118 | + tcg_gen_extract2_i32(t0, t0, t1, a->imm); | ||
55 | } | 119 | } |
56 | info->dtb_start = info->loader_start; | 120 | + tcg_gen_extu_i32_i64(tcg_rd, t0); |
57 | - info->dtb_limit = elf_low_addr; | ||
58 | + info->dtb_limit = image_low_addr; | ||
59 | } | 121 | } |
60 | } | 122 | } |
61 | entry = elf_entry; | 123 | -} |
124 | - | ||
125 | -/* Data processing - immediate */ | ||
126 | -static void disas_data_proc_imm(DisasContext *s, uint32_t insn) | ||
127 | -{ | ||
128 | - switch (extract32(insn, 23, 6)) { | ||
129 | - case 0x27: /* Extract */ | ||
130 | - disas_extract(s, insn); | ||
131 | - break; | ||
132 | - default: | ||
133 | - unallocated_encoding(s); | ||
134 | - break; | ||
135 | - } | ||
136 | + return true; | ||
137 | } | ||
138 | |||
139 | /* Shift a TCGv src by TCGv shift_amount, put result in dst. | ||
140 | @@ -XXX,XX +XXX,XX @@ static bool btype_destination_ok(uint32_t insn, bool bt, int btype) | ||
141 | static void disas_a64_legacy(DisasContext *s, uint32_t insn) | ||
142 | { | ||
143 | switch (extract32(insn, 25, 4)) { | ||
144 | - case 0x8: case 0x9: /* Data processing - immediate */ | ||
145 | - disas_data_proc_imm(s, insn); | ||
146 | - break; | ||
147 | case 0xa: case 0xb: /* Branch, exception generation and system insns */ | ||
148 | disas_b_exc_sys(s, insn); | ||
149 | break; | ||
62 | -- | 150 | -- |
63 | 2.20.1 | 151 | 2.34.1 |
64 | |||
65 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Convert the unconditional branch immediate insns B and BL to | ||
2 | decodetree. | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20230512144106.3608981-14-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/tcg/a64.decode | 9 +++++++++ | ||
9 | target/arm/tcg/translate-a64.c | 31 +++++++++++-------------------- | ||
10 | 2 files changed, 20 insertions(+), 20 deletions(-) | ||
11 | |||
12 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/tcg/a64.decode | ||
15 | +++ b/target/arm/tcg/a64.decode | ||
16 | @@ -XXX,XX +XXX,XX @@ | ||
17 | |||
18 | &ri rd imm | ||
19 | &rri_sf rd rn imm sf | ||
20 | +&i imm | ||
21 | |||
22 | |||
23 | ### Data Processing - Immediate | ||
24 | @@ -XXX,XX +XXX,XX @@ UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 | ||
25 | |||
26 | EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1 | ||
27 | EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 | ||
28 | + | ||
29 | +# Branches | ||
30 | + | ||
31 | +%imm26 0:s26 !function=times_4 | ||
32 | +@branch . ..... .......................... &i imm=%imm26 | ||
33 | + | ||
34 | +B 0 00101 .......................... @branch | ||
35 | +BL 1 00101 .......................... @branch | ||
36 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/tcg/translate-a64.c | ||
39 | +++ b/target/arm/tcg/translate-a64.c | ||
40 | @@ -XXX,XX +XXX,XX @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table, | ||
41 | * match up with those in the manual. | ||
42 | */ | ||
43 | |||
44 | -/* Unconditional branch (immediate) | ||
45 | - * 31 30 26 25 0 | ||
46 | - * +----+-----------+-------------------------------------+ | ||
47 | - * | op | 0 0 1 0 1 | imm26 | | ||
48 | - * +----+-----------+-------------------------------------+ | ||
49 | - */ | ||
50 | -static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) | ||
51 | +static bool trans_B(DisasContext *s, arg_i *a) | ||
52 | { | ||
53 | - int64_t diff = sextract32(insn, 0, 26) * 4; | ||
54 | - | ||
55 | - if (insn & (1U << 31)) { | ||
56 | - /* BL Branch with link */ | ||
57 | - gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s)); | ||
58 | - } | ||
59 | - | ||
60 | - /* B Branch / BL Branch with link */ | ||
61 | reset_btype(s); | ||
62 | - gen_goto_tb(s, 0, diff); | ||
63 | + gen_goto_tb(s, 0, a->imm); | ||
64 | + return true; | ||
65 | +} | ||
66 | + | ||
67 | +static bool trans_BL(DisasContext *s, arg_i *a) | ||
68 | +{ | ||
69 | + gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s)); | ||
70 | + reset_btype(s); | ||
71 | + gen_goto_tb(s, 0, a->imm); | ||
72 | + return true; | ||
73 | } | ||
74 | |||
75 | /* Compare and branch (immediate) | ||
76 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) | ||
77 | static void disas_b_exc_sys(DisasContext *s, uint32_t insn) | ||
78 | { | ||
79 | switch (extract32(insn, 25, 7)) { | ||
80 | - case 0x0a: case 0x0b: | ||
81 | - case 0x4a: case 0x4b: /* Unconditional branch (immediate) */ | ||
82 | - disas_uncond_b_imm(s, insn); | ||
83 | - break; | ||
84 | case 0x1a: case 0x5a: /* Compare & branch (immediate) */ | ||
85 | disas_comp_b_imm(s, insn); | ||
86 | break; | ||
87 | -- | ||
88 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Convert the compare-and-branch-immediate insns CBZ and CBNZ | ||
2 | to decodetree. | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20230512144106.3608981-15-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/tcg/a64.decode | 5 +++++ | ||
9 | target/arm/tcg/translate-a64.c | 26 ++++++-------------------- | ||
10 | 2 files changed, 11 insertions(+), 20 deletions(-) | ||
11 | |||
12 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/tcg/a64.decode | ||
15 | +++ b/target/arm/tcg/a64.decode | ||
16 | @@ -XXX,XX +XXX,XX @@ EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 | ||
17 | |||
18 | B 0 00101 .......................... @branch | ||
19 | BL 1 00101 .......................... @branch | ||
20 | + | ||
21 | +%imm19 5:s19 !function=times_4 | ||
22 | +&cbz rt imm sf nz | ||
23 | + | ||
24 | +CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 | ||
25 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/target/arm/tcg/translate-a64.c | ||
28 | +++ b/target/arm/tcg/translate-a64.c | ||
29 | @@ -XXX,XX +XXX,XX @@ static bool trans_BL(DisasContext *s, arg_i *a) | ||
30 | return true; | ||
31 | } | ||
32 | |||
33 | -/* Compare and branch (immediate) | ||
34 | - * 31 30 25 24 23 5 4 0 | ||
35 | - * +----+-------------+----+---------------------+--------+ | ||
36 | - * | sf | 0 1 1 0 1 0 | op | imm19 | Rt | | ||
37 | - * +----+-------------+----+---------------------+--------+ | ||
38 | - */ | ||
39 | -static void disas_comp_b_imm(DisasContext *s, uint32_t insn) | ||
40 | + | ||
41 | +static bool trans_CBZ(DisasContext *s, arg_cbz *a) | ||
42 | { | ||
43 | - unsigned int sf, op, rt; | ||
44 | - int64_t diff; | ||
45 | DisasLabel match; | ||
46 | TCGv_i64 tcg_cmp; | ||
47 | |||
48 | - sf = extract32(insn, 31, 1); | ||
49 | - op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ | ||
50 | - rt = extract32(insn, 0, 5); | ||
51 | - diff = sextract32(insn, 5, 19) * 4; | ||
52 | - | ||
53 | - tcg_cmp = read_cpu_reg(s, rt, sf); | ||
54 | + tcg_cmp = read_cpu_reg(s, a->rt, a->sf); | ||
55 | reset_btype(s); | ||
56 | |||
57 | match = gen_disas_label(s); | ||
58 | - tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, | ||
59 | + tcg_gen_brcondi_i64(a->nz ? TCG_COND_NE : TCG_COND_EQ, | ||
60 | tcg_cmp, 0, match.label); | ||
61 | gen_goto_tb(s, 0, 4); | ||
62 | set_disas_label(s, match); | ||
63 | - gen_goto_tb(s, 1, diff); | ||
64 | + gen_goto_tb(s, 1, a->imm); | ||
65 | + return true; | ||
66 | } | ||
67 | |||
68 | /* Test and branch (immediate) | ||
69 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) | ||
70 | static void disas_b_exc_sys(DisasContext *s, uint32_t insn) | ||
71 | { | ||
72 | switch (extract32(insn, 25, 7)) { | ||
73 | - case 0x1a: case 0x5a: /* Compare & branch (immediate) */ | ||
74 | - disas_comp_b_imm(s, insn); | ||
75 | - break; | ||
76 | case 0x1b: case 0x5b: /* Test & branch (immediate) */ | ||
77 | disas_test_b_imm(s, insn); | ||
78 | break; | ||
79 | -- | ||
80 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Convert the test-and-branch-immediate insns TBZ and TBNZ | ||
2 | to decodetree. | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20230512144106.3608981-16-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/tcg/a64.decode | 6 ++++++ | ||
9 | target/arm/tcg/translate-a64.c | 25 +++++-------------------- | ||
10 | 2 files changed, 11 insertions(+), 20 deletions(-) | ||
11 | |||
12 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/tcg/a64.decode | ||
15 | +++ b/target/arm/tcg/a64.decode | ||
16 | @@ -XXX,XX +XXX,XX @@ BL 1 00101 .......................... @branch | ||
17 | &cbz rt imm sf nz | ||
18 | |||
19 | CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 | ||
20 | + | ||
21 | +%imm14 5:s14 !function=times_4 | ||
22 | +%imm31_19 31:1 19:5 | ||
23 | +&tbz rt imm nz bitpos | ||
24 | + | ||
25 | +TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 | ||
26 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/target/arm/tcg/translate-a64.c | ||
29 | +++ b/target/arm/tcg/translate-a64.c | ||
30 | @@ -XXX,XX +XXX,XX @@ static bool trans_CBZ(DisasContext *s, arg_cbz *a) | ||
31 | return true; | ||
32 | } | ||
33 | |||
34 | -/* Test and branch (immediate) | ||
35 | - * 31 30 25 24 23 19 18 5 4 0 | ||
36 | - * +----+-------------+----+-------+-------------+------+ | ||
37 | - * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt | | ||
38 | - * +----+-------------+----+-------+-------------+------+ | ||
39 | - */ | ||
40 | -static void disas_test_b_imm(DisasContext *s, uint32_t insn) | ||
41 | +static bool trans_TBZ(DisasContext *s, arg_tbz *a) | ||
42 | { | ||
43 | - unsigned int bit_pos, op, rt; | ||
44 | - int64_t diff; | ||
45 | DisasLabel match; | ||
46 | TCGv_i64 tcg_cmp; | ||
47 | |||
48 | - bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); | ||
49 | - op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ | ||
50 | - diff = sextract32(insn, 5, 14) * 4; | ||
51 | - rt = extract32(insn, 0, 5); | ||
52 | - | ||
53 | tcg_cmp = tcg_temp_new_i64(); | ||
54 | - tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); | ||
55 | + tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, a->rt), 1ULL << a->bitpos); | ||
56 | |||
57 | reset_btype(s); | ||
58 | |||
59 | match = gen_disas_label(s); | ||
60 | - tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, | ||
61 | + tcg_gen_brcondi_i64(a->nz ? TCG_COND_NE : TCG_COND_EQ, | ||
62 | tcg_cmp, 0, match.label); | ||
63 | gen_goto_tb(s, 0, 4); | ||
64 | set_disas_label(s, match); | ||
65 | - gen_goto_tb(s, 1, diff); | ||
66 | + gen_goto_tb(s, 1, a->imm); | ||
67 | + return true; | ||
68 | } | ||
69 | |||
70 | /* Conditional branch (immediate) | ||
71 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) | ||
72 | static void disas_b_exc_sys(DisasContext *s, uint32_t insn) | ||
73 | { | ||
74 | switch (extract32(insn, 25, 7)) { | ||
75 | - case 0x1b: case 0x5b: /* Test & branch (immediate) */ | ||
76 | - disas_test_b_imm(s, insn); | ||
77 | - break; | ||
78 | case 0x2a: /* Conditional branch (immediate) */ | ||
79 | disas_cond_b_imm(s, insn); | ||
80 | break; | ||
81 | -- | ||
82 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Convert the immediate conditional branch insn B.cond to | ||
2 | decodetree. | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20230512144106.3608981-17-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/tcg/a64.decode | 2 ++ | ||
9 | target/arm/tcg/translate-a64.c | 30 ++++++------------------------ | ||
10 | 2 files changed, 8 insertions(+), 24 deletions(-) | ||
11 | |||
12 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/tcg/a64.decode | ||
15 | +++ b/target/arm/tcg/a64.decode | ||
16 | @@ -XXX,XX +XXX,XX @@ CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 | ||
17 | &tbz rt imm nz bitpos | ||
18 | |||
19 | TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 | ||
20 | + | ||
21 | +B_cond 0101010 0 ................... 0 cond:4 imm=%imm19 | ||
22 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/target/arm/tcg/translate-a64.c | ||
25 | +++ b/target/arm/tcg/translate-a64.c | ||
26 | @@ -XXX,XX +XXX,XX @@ static bool trans_TBZ(DisasContext *s, arg_tbz *a) | ||
27 | return true; | ||
28 | } | ||
29 | |||
30 | -/* Conditional branch (immediate) | ||
31 | - * 31 25 24 23 5 4 3 0 | ||
32 | - * +---------------+----+---------------------+----+------+ | ||
33 | - * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond | | ||
34 | - * +---------------+----+---------------------+----+------+ | ||
35 | - */ | ||
36 | -static void disas_cond_b_imm(DisasContext *s, uint32_t insn) | ||
37 | +static bool trans_B_cond(DisasContext *s, arg_B_cond *a) | ||
38 | { | ||
39 | - unsigned int cond; | ||
40 | - int64_t diff; | ||
41 | - | ||
42 | - if ((insn & (1 << 4)) || (insn & (1 << 24))) { | ||
43 | - unallocated_encoding(s); | ||
44 | - return; | ||
45 | - } | ||
46 | - diff = sextract32(insn, 5, 19) * 4; | ||
47 | - cond = extract32(insn, 0, 4); | ||
48 | - | ||
49 | reset_btype(s); | ||
50 | - if (cond < 0x0e) { | ||
51 | + if (a->cond < 0x0e) { | ||
52 | /* genuinely conditional branches */ | ||
53 | DisasLabel match = gen_disas_label(s); | ||
54 | - arm_gen_test_cc(cond, match.label); | ||
55 | + arm_gen_test_cc(a->cond, match.label); | ||
56 | gen_goto_tb(s, 0, 4); | ||
57 | set_disas_label(s, match); | ||
58 | - gen_goto_tb(s, 1, diff); | ||
59 | + gen_goto_tb(s, 1, a->imm); | ||
60 | } else { | ||
61 | /* 0xe and 0xf are both "always" conditions */ | ||
62 | - gen_goto_tb(s, 0, diff); | ||
63 | + gen_goto_tb(s, 0, a->imm); | ||
64 | } | ||
65 | + return true; | ||
66 | } | ||
67 | |||
68 | /* HINT instruction group, including various allocated HINTs */ | ||
69 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) | ||
70 | static void disas_b_exc_sys(DisasContext *s, uint32_t insn) | ||
71 | { | ||
72 | switch (extract32(insn, 25, 7)) { | ||
73 | - case 0x2a: /* Conditional branch (immediate) */ | ||
74 | - disas_cond_b_imm(s, insn); | ||
75 | - break; | ||
76 | case 0x6a: /* Exception generation / System */ | ||
77 | if (insn & (1 << 24)) { | ||
78 | if (extract32(insn, 22, 2) == 0) { | ||
79 | -- | ||
80 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Convert the simple (non-pointer-auth) BR, BLR and RET insns | ||
2 | to decodetree. | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20230512144106.3608981-18-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/tcg/a64.decode | 5 ++++ | ||
9 | target/arm/tcg/translate-a64.c | 55 ++++++++++++++++++++++++++++++---- | ||
10 | 2 files changed, 54 insertions(+), 6 deletions(-) | ||
11 | |||
12 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/tcg/a64.decode | ||
15 | +++ b/target/arm/tcg/a64.decode | ||
16 | @@ -XXX,XX +XXX,XX @@ | ||
17 | # This file is processed by scripts/decodetree.py | ||
18 | # | ||
19 | |||
20 | +&r rn | ||
21 | &ri rd imm | ||
22 | &rri_sf rd rn imm sf | ||
23 | &i imm | ||
24 | @@ -XXX,XX +XXX,XX @@ CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 | ||
25 | TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 | ||
26 | |||
27 | B_cond 0101010 0 ................... 0 cond:4 imm=%imm19 | ||
28 | + | ||
29 | +BR 1101011 0000 11111 000000 rn:5 00000 &r | ||
30 | +BLR 1101011 0001 11111 000000 rn:5 00000 &r | ||
31 | +RET 1101011 0010 11111 000000 rn:5 00000 &r | ||
32 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/arm/tcg/translate-a64.c | ||
35 | +++ b/target/arm/tcg/translate-a64.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static bool trans_B_cond(DisasContext *s, arg_B_cond *a) | ||
37 | return true; | ||
38 | } | ||
39 | |||
40 | +static void set_btype_for_br(DisasContext *s, int rn) | ||
41 | +{ | ||
42 | + if (dc_isar_feature(aa64_bti, s)) { | ||
43 | + /* BR to {x16,x17} or !guard -> 1, else 3. */ | ||
44 | + set_btype(s, rn == 16 || rn == 17 || !s->guarded_page ? 1 : 3); | ||
45 | + } | ||
46 | +} | ||
47 | + | ||
48 | +static void set_btype_for_blr(DisasContext *s) | ||
49 | +{ | ||
50 | + if (dc_isar_feature(aa64_bti, s)) { | ||
51 | + /* BLR sets BTYPE to 2, regardless of source guarded page. */ | ||
52 | + set_btype(s, 2); | ||
53 | + } | ||
54 | +} | ||
55 | + | ||
56 | +static bool trans_BR(DisasContext *s, arg_r *a) | ||
57 | +{ | ||
58 | + gen_a64_set_pc(s, cpu_reg(s, a->rn)); | ||
59 | + set_btype_for_br(s, a->rn); | ||
60 | + s->base.is_jmp = DISAS_JUMP; | ||
61 | + return true; | ||
62 | +} | ||
63 | + | ||
64 | +static bool trans_BLR(DisasContext *s, arg_r *a) | ||
65 | +{ | ||
66 | + TCGv_i64 dst = cpu_reg(s, a->rn); | ||
67 | + TCGv_i64 lr = cpu_reg(s, 30); | ||
68 | + if (dst == lr) { | ||
69 | + TCGv_i64 tmp = tcg_temp_new_i64(); | ||
70 | + tcg_gen_mov_i64(tmp, dst); | ||
71 | + dst = tmp; | ||
72 | + } | ||
73 | + gen_pc_plus_diff(s, lr, curr_insn_len(s)); | ||
74 | + gen_a64_set_pc(s, dst); | ||
75 | + set_btype_for_blr(s); | ||
76 | + s->base.is_jmp = DISAS_JUMP; | ||
77 | + return true; | ||
78 | +} | ||
79 | + | ||
80 | +static bool trans_RET(DisasContext *s, arg_r *a) | ||
81 | +{ | ||
82 | + gen_a64_set_pc(s, cpu_reg(s, a->rn)); | ||
83 | + s->base.is_jmp = DISAS_JUMP; | ||
84 | + return true; | ||
85 | +} | ||
86 | + | ||
87 | /* HINT instruction group, including various allocated HINTs */ | ||
88 | static void handle_hint(DisasContext *s, uint32_t insn, | ||
89 | unsigned int op1, unsigned int op2, unsigned int crm) | ||
90 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) | ||
91 | btype_mod = opc; | ||
92 | switch (op3) { | ||
93 | case 0: | ||
94 | - /* BR, BLR, RET */ | ||
95 | - if (op4 != 0) { | ||
96 | - goto do_unallocated; | ||
97 | - } | ||
98 | - dst = cpu_reg(s, rn); | ||
99 | - break; | ||
100 | + /* BR, BLR, RET : handled in decodetree */ | ||
101 | + goto do_unallocated; | ||
102 | |||
103 | case 2: | ||
104 | case 3: | ||
105 | -- | ||
106 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Convert the single-register pointer-authentication variants of BR, | ||
2 | BLR, RET to decodetree. (BRAA/BLRAA are in a different branch of | ||
3 | the legacy decoder and will be dealt with in the next commit.) | ||
1 | 4 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20230512144106.3608981-19-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/tcg/a64.decode | 7 ++ | ||
10 | target/arm/tcg/translate-a64.c | 132 +++++++++++++++++++-------------- | ||
11 | 2 files changed, 84 insertions(+), 55 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/tcg/a64.decode | ||
16 | +++ b/target/arm/tcg/a64.decode | ||
17 | @@ -XXX,XX +XXX,XX @@ B_cond 0101010 0 ................... 0 cond:4 imm=%imm19 | ||
18 | BR 1101011 0000 11111 000000 rn:5 00000 &r | ||
19 | BLR 1101011 0001 11111 000000 rn:5 00000 &r | ||
20 | RET 1101011 0010 11111 000000 rn:5 00000 &r | ||
21 | + | ||
22 | +&braz rn m | ||
23 | +BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ | ||
24 | +BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ | ||
25 | + | ||
26 | +&reta m | ||
27 | +RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB | ||
28 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/target/arm/tcg/translate-a64.c | ||
31 | +++ b/target/arm/tcg/translate-a64.c | ||
32 | @@ -XXX,XX +XXX,XX @@ static bool trans_RET(DisasContext *s, arg_r *a) | ||
33 | return true; | ||
34 | } | ||
35 | |||
36 | +static TCGv_i64 auth_branch_target(DisasContext *s, TCGv_i64 dst, | ||
37 | + TCGv_i64 modifier, bool use_key_a) | ||
38 | +{ | ||
39 | + TCGv_i64 truedst; | ||
40 | + /* | ||
41 | + * Return the branch target for a BRAA/RETA/etc, which is either | ||
42 | + * just the destination dst, or that value with the pauth check | ||
43 | + * done and the code removed from the high bits. | ||
44 | + */ | ||
45 | + if (!s->pauth_active) { | ||
46 | + return dst; | ||
47 | + } | ||
48 | + | ||
49 | + truedst = tcg_temp_new_i64(); | ||
50 | + if (use_key_a) { | ||
51 | + gen_helper_autia(truedst, cpu_env, dst, modifier); | ||
52 | + } else { | ||
53 | + gen_helper_autib(truedst, cpu_env, dst, modifier); | ||
54 | + } | ||
55 | + return truedst; | ||
56 | +} | ||
57 | + | ||
58 | +static bool trans_BRAZ(DisasContext *s, arg_braz *a) | ||
59 | +{ | ||
60 | + TCGv_i64 dst; | ||
61 | + | ||
62 | + if (!dc_isar_feature(aa64_pauth, s)) { | ||
63 | + return false; | ||
64 | + } | ||
65 | + | ||
66 | + dst = auth_branch_target(s, cpu_reg(s, a->rn), tcg_constant_i64(0), !a->m); | ||
67 | + gen_a64_set_pc(s, dst); | ||
68 | + set_btype_for_br(s, a->rn); | ||
69 | + s->base.is_jmp = DISAS_JUMP; | ||
70 | + return true; | ||
71 | +} | ||
72 | + | ||
73 | +static bool trans_BLRAZ(DisasContext *s, arg_braz *a) | ||
74 | +{ | ||
75 | + TCGv_i64 dst, lr; | ||
76 | + | ||
77 | + if (!dc_isar_feature(aa64_pauth, s)) { | ||
78 | + return false; | ||
79 | + } | ||
80 | + | ||
81 | + dst = auth_branch_target(s, cpu_reg(s, a->rn), tcg_constant_i64(0), !a->m); | ||
82 | + lr = cpu_reg(s, 30); | ||
83 | + if (dst == lr) { | ||
84 | + TCGv_i64 tmp = tcg_temp_new_i64(); | ||
85 | + tcg_gen_mov_i64(tmp, dst); | ||
86 | + dst = tmp; | ||
87 | + } | ||
88 | + gen_pc_plus_diff(s, lr, curr_insn_len(s)); | ||
89 | + gen_a64_set_pc(s, dst); | ||
90 | + set_btype_for_blr(s); | ||
91 | + s->base.is_jmp = DISAS_JUMP; | ||
92 | + return true; | ||
93 | +} | ||
94 | + | ||
95 | +static bool trans_RETA(DisasContext *s, arg_reta *a) | ||
96 | +{ | ||
97 | + TCGv_i64 dst; | ||
98 | + | ||
99 | + dst = auth_branch_target(s, cpu_reg(s, 30), cpu_X[31], !a->m); | ||
100 | + gen_a64_set_pc(s, dst); | ||
101 | + s->base.is_jmp = DISAS_JUMP; | ||
102 | + return true; | ||
103 | +} | ||
104 | + | ||
105 | /* HINT instruction group, including various allocated HINTs */ | ||
106 | static void handle_hint(DisasContext *s, uint32_t insn, | ||
107 | unsigned int op1, unsigned int op2, unsigned int crm) | ||
108 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) | ||
109 | } | ||
110 | |||
111 | switch (opc) { | ||
112 | - case 0: /* BR */ | ||
113 | - case 1: /* BLR */ | ||
114 | - case 2: /* RET */ | ||
115 | - btype_mod = opc; | ||
116 | - switch (op3) { | ||
117 | - case 0: | ||
118 | - /* BR, BLR, RET : handled in decodetree */ | ||
119 | - goto do_unallocated; | ||
120 | - | ||
121 | - case 2: | ||
122 | - case 3: | ||
123 | - if (!dc_isar_feature(aa64_pauth, s)) { | ||
124 | - goto do_unallocated; | ||
125 | - } | ||
126 | - if (opc == 2) { | ||
127 | - /* RETAA, RETAB */ | ||
128 | - if (rn != 0x1f || op4 != 0x1f) { | ||
129 | - goto do_unallocated; | ||
130 | - } | ||
131 | - rn = 30; | ||
132 | - modifier = cpu_X[31]; | ||
133 | - } else { | ||
134 | - /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */ | ||
135 | - if (op4 != 0x1f) { | ||
136 | - goto do_unallocated; | ||
137 | - } | ||
138 | - modifier = tcg_constant_i64(0); | ||
139 | - } | ||
140 | - if (s->pauth_active) { | ||
141 | - dst = tcg_temp_new_i64(); | ||
142 | - if (op3 == 2) { | ||
143 | - gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); | ||
144 | - } else { | ||
145 | - gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); | ||
146 | - } | ||
147 | - } else { | ||
148 | - dst = cpu_reg(s, rn); | ||
149 | - } | ||
150 | - break; | ||
151 | - | ||
152 | - default: | ||
153 | - goto do_unallocated; | ||
154 | - } | ||
155 | - /* BLR also needs to load return address */ | ||
156 | - if (opc == 1) { | ||
157 | - TCGv_i64 lr = cpu_reg(s, 30); | ||
158 | - if (dst == lr) { | ||
159 | - TCGv_i64 tmp = tcg_temp_new_i64(); | ||
160 | - tcg_gen_mov_i64(tmp, dst); | ||
161 | - dst = tmp; | ||
162 | - } | ||
163 | - gen_pc_plus_diff(s, lr, curr_insn_len(s)); | ||
164 | - } | ||
165 | - gen_a64_set_pc(s, dst); | ||
166 | - break; | ||
167 | + case 0: | ||
168 | + case 1: | ||
169 | + case 2: | ||
170 | + /* | ||
171 | + * BR, BLR, RET, RETAA, RETAB, BRAAZ, BRABZ, BLRAAZ, BLRABZ: | ||
172 | + * handled in decodetree | ||
173 | + */ | ||
174 | + goto do_unallocated; | ||
175 | |||
176 | case 8: /* BRAA */ | ||
177 | case 9: /* BLRAA */ | ||
178 | -- | ||
179 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Convert the last four BR-with-pointer-auth insns to decodetree. | ||
2 | The remaining cases in the outer switch in disas_uncond_b_reg() | ||
3 | all return early rather than leaving the case statement, so we | ||
4 | can delete the now-unused code at the end of that function. | ||
1 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20230512144106.3608981-20-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/tcg/a64.decode | 4 ++ | ||
11 | target/arm/tcg/translate-a64.c | 97 ++++++++++++++-------------------- | ||
12 | 2 files changed, 43 insertions(+), 58 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/tcg/a64.decode | ||
17 | +++ b/target/arm/tcg/a64.decode | ||
18 | @@ -XXX,XX +XXX,XX @@ BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ | ||
19 | |||
20 | &reta m | ||
21 | RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB | ||
22 | + | ||
23 | +&bra rn rm m | ||
24 | +BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB | ||
25 | +BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB | ||
26 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/target/arm/tcg/translate-a64.c | ||
29 | +++ b/target/arm/tcg/translate-a64.c | ||
30 | @@ -XXX,XX +XXX,XX @@ static bool trans_RETA(DisasContext *s, arg_reta *a) | ||
31 | return true; | ||
32 | } | ||
33 | |||
34 | +static bool trans_BRA(DisasContext *s, arg_bra *a) | ||
35 | +{ | ||
36 | + TCGv_i64 dst; | ||
37 | + | ||
38 | + if (!dc_isar_feature(aa64_pauth, s)) { | ||
39 | + return false; | ||
40 | + } | ||
41 | + dst = auth_branch_target(s, cpu_reg(s,a->rn), cpu_reg_sp(s, a->rm), !a->m); | ||
42 | + gen_a64_set_pc(s, dst); | ||
43 | + set_btype_for_br(s, a->rn); | ||
44 | + s->base.is_jmp = DISAS_JUMP; | ||
45 | + return true; | ||
46 | +} | ||
47 | + | ||
48 | +static bool trans_BLRA(DisasContext *s, arg_bra *a) | ||
49 | +{ | ||
50 | + TCGv_i64 dst, lr; | ||
51 | + | ||
52 | + if (!dc_isar_feature(aa64_pauth, s)) { | ||
53 | + return false; | ||
54 | + } | ||
55 | + dst = auth_branch_target(s, cpu_reg(s, a->rn), cpu_reg_sp(s, a->rm), !a->m); | ||
56 | + lr = cpu_reg(s, 30); | ||
57 | + if (dst == lr) { | ||
58 | + TCGv_i64 tmp = tcg_temp_new_i64(); | ||
59 | + tcg_gen_mov_i64(tmp, dst); | ||
60 | + dst = tmp; | ||
61 | + } | ||
62 | + gen_pc_plus_diff(s, lr, curr_insn_len(s)); | ||
63 | + gen_a64_set_pc(s, dst); | ||
64 | + set_btype_for_blr(s); | ||
65 | + s->base.is_jmp = DISAS_JUMP; | ||
66 | + return true; | ||
67 | +} | ||
68 | + | ||
69 | /* HINT instruction group, including various allocated HINTs */ | ||
70 | static void handle_hint(DisasContext *s, uint32_t insn, | ||
71 | unsigned int op1, unsigned int op2, unsigned int crm) | ||
72 | @@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn) | ||
73 | static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) | ||
74 | { | ||
75 | unsigned int opc, op2, op3, rn, op4; | ||
76 | - unsigned btype_mod = 2; /* 0: BR, 1: BLR, 2: other */ | ||
77 | TCGv_i64 dst; | ||
78 | TCGv_i64 modifier; | ||
79 | |||
80 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) | ||
81 | case 0: | ||
82 | case 1: | ||
83 | case 2: | ||
84 | + case 8: | ||
85 | + case 9: | ||
86 | /* | ||
87 | - * BR, BLR, RET, RETAA, RETAB, BRAAZ, BRABZ, BLRAAZ, BLRABZ: | ||
88 | - * handled in decodetree | ||
89 | + * BR, BLR, RET, RETAA, RETAB, BRAAZ, BRABZ, BLRAAZ, BLRABZ, | ||
90 | + * BRAA, BLRAA: handled in decodetree | ||
91 | */ | ||
92 | goto do_unallocated; | ||
93 | |||
94 | - case 8: /* BRAA */ | ||
95 | - case 9: /* BLRAA */ | ||
96 | - if (!dc_isar_feature(aa64_pauth, s)) { | ||
97 | - goto do_unallocated; | ||
98 | - } | ||
99 | - if ((op3 & ~1) != 2) { | ||
100 | - goto do_unallocated; | ||
101 | - } | ||
102 | - btype_mod = opc & 1; | ||
103 | - if (s->pauth_active) { | ||
104 | - dst = tcg_temp_new_i64(); | ||
105 | - modifier = cpu_reg_sp(s, op4); | ||
106 | - if (op3 == 2) { | ||
107 | - gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); | ||
108 | - } else { | ||
109 | - gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); | ||
110 | - } | ||
111 | - } else { | ||
112 | - dst = cpu_reg(s, rn); | ||
113 | - } | ||
114 | - /* BLRAA also needs to load return address */ | ||
115 | - if (opc == 9) { | ||
116 | - TCGv_i64 lr = cpu_reg(s, 30); | ||
117 | - if (dst == lr) { | ||
118 | - TCGv_i64 tmp = tcg_temp_new_i64(); | ||
119 | - tcg_gen_mov_i64(tmp, dst); | ||
120 | - dst = tmp; | ||
121 | - } | ||
122 | - gen_pc_plus_diff(s, lr, curr_insn_len(s)); | ||
123 | - } | ||
124 | - gen_a64_set_pc(s, dst); | ||
125 | - break; | ||
126 | - | ||
127 | case 4: /* ERET */ | ||
128 | if (s->current_el == 0) { | ||
129 | goto do_unallocated; | ||
130 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) | ||
131 | unallocated_encoding(s); | ||
132 | return; | ||
133 | } | ||
134 | - | ||
135 | - switch (btype_mod) { | ||
136 | - case 0: /* BR */ | ||
137 | - if (dc_isar_feature(aa64_bti, s)) { | ||
138 | - /* BR to {x16,x17} or !guard -> 1, else 3. */ | ||
139 | - set_btype(s, rn == 16 || rn == 17 || !s->guarded_page ? 1 : 3); | ||
140 | - } | ||
141 | - break; | ||
142 | - | ||
143 | - case 1: /* BLR */ | ||
144 | - if (dc_isar_feature(aa64_bti, s)) { | ||
145 | - /* BLR sets BTYPE to 2, regardless of source guarded page. */ | ||
146 | - set_btype(s, 2); | ||
147 | - } | ||
148 | - break; | ||
149 | - | ||
150 | - default: /* RET or none of the above. */ | ||
151 | - /* BTYPE will be set to 0 by normal end-of-insn processing. */ | ||
152 | - break; | ||
153 | - } | ||
154 | - | ||
155 | - s->base.is_jmp = DISAS_JUMP; | ||
156 | } | ||
157 | |||
158 | /* Branches, exception generating and system instructions */ | ||
159 | -- | ||
160 | 2.34.1 | diff view generated by jsdifflib |
1 | The VMSTATE_STRUCT_VARRAY_UINT32 macro is intended to handle | 1 | Convert the exception-return insns ERET, ERETA and ERETB to |
---|---|---|---|
2 | migrating a field which is an array of structs, but where instead of | 2 | decodetree. These were the last insns left in the legacy |
3 | migrating the entire array we only migrate a variable number of | 3 | decoder function disas_uncond_reg_b(), which allows us to |
4 | elements of it. | 4 | remove it. |
5 | 5 | ||
6 | The VMSTATE_STRUCT_VARRAY_POINTER_UINT32 macro is intended to handle | 6 | The old decoder explicitly decoded the DRPS instruction, |
7 | migrating a field which is of pointer type, and points to a | 7 | only in order to call unallocated_encoding() on it, exactly |
8 | dynamically allocated array of structs of variable size. | 8 | as would have happened if it hadn't decoded it. This is |
9 | 9 | because this insn always UNDEFs unless the CPU is in | |
10 | We weren't actually checking that the field passed to | 10 | halting-debug state, which we don't emulate. So we list |
11 | VMSTATE_STRUCT_VARRAY_UINT32 really is an array, with the result that | 11 | the pattern in a comment in a64.decode, but don't actively |
12 | accidentally using it where the _POINTER_ macro was intended would | 12 | decode it. |
13 | compile but silently corrupt memory on migration. | ||
14 | |||
15 | Add type-checking that enforces that the field passed in is | ||
16 | really of the right array type. This applies to all the VMSTATE | ||
17 | macros which use flags including VMS_VARRAY_* but not VMS_POINTER. | ||
18 | 13 | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
20 | Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> | 15 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
21 | Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> | 16 | Message-id: 20230512144106.3608981-21-peter.maydell@linaro.org |
22 | Tested-by: Damien Hedde <damien.hedde@greensocs.com> | ||
23 | Message-id: 20190725163710.11703-3-peter.maydell@linaro.org | ||
24 | --- | 17 | --- |
25 | include/migration/vmstate.h | 30 ++++++++++++++++++++++++------ | 18 | target/arm/tcg/a64.decode | 8 ++ |
26 | 1 file changed, 24 insertions(+), 6 deletions(-) | 19 | target/arm/tcg/translate-a64.c | 163 +++++++++++---------------------- |
20 | 2 files changed, 63 insertions(+), 108 deletions(-) | ||
27 | 21 | ||
28 | diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h | 22 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
29 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/include/migration/vmstate.h | 24 | --- a/target/arm/tcg/a64.decode |
31 | +++ b/include/migration/vmstate.h | 25 | +++ b/target/arm/tcg/a64.decode |
32 | @@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_bitmap; | 26 | @@ -XXX,XX +XXX,XX @@ RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB |
33 | extern const VMStateInfo vmstate_info_qtailq; | 27 | &bra rn rm m |
34 | 28 | BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB | |
35 | #define type_check_2darray(t1,t2,n,m) ((t1(*)[n][m])0 - (t2*)0) | 29 | BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB |
36 | +/* | 30 | + |
37 | + * Check that type t2 is an array of type t1 of size n, | 31 | +ERET 1101011 0100 11111 000000 11111 00000 |
38 | + * e.g. if t1 is 'foo' and n is 32 then t2 must be 'foo[32]' | 32 | +ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB |
39 | + */ | 33 | + |
40 | #define type_check_array(t1,t2,n) ((t1(*)[n])0 - (t2*)0) | 34 | +# We don't need to decode DRPS because it always UNDEFs except when |
41 | #define type_check_pointer(t1,t2) ((t1**)0 - (t2*)0) | 35 | +# the processor is in halting debug state (which we don't implement). |
42 | +/* | 36 | +# The pattern is listed here as documentation. |
43 | + * type of element 0 of the specified (array) field of the type. | 37 | +# DRPS 1101011 0101 11111 000000 11111 00000 |
44 | + * Note that if the field is a pointer then this will return the | 38 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c |
45 | + * pointed-to type rather than complaining. | 39 | index XXXXXXX..XXXXXXX 100644 |
46 | + */ | 40 | --- a/target/arm/tcg/translate-a64.c |
47 | +#define typeof_elt_of_field(type, field) typeof(((type *)0)->field[0]) | 41 | +++ b/target/arm/tcg/translate-a64.c |
48 | +/* Check that field f in struct type t2 is an array of t1, of any size */ | 42 | @@ -XXX,XX +XXX,XX @@ static bool trans_BLRA(DisasContext *s, arg_bra *a) |
49 | +#define type_check_varray(t1, t2, f) \ | 43 | return true; |
50 | + (type_check(t1, typeof_elt_of_field(t2, f)) \ | ||
51 | + + QEMU_BUILD_BUG_ON_ZERO(!QEMU_IS_ARRAY(((t2 *)0)->f))) | ||
52 | |||
53 | #define vmstate_offset_value(_state, _field, _type) \ | ||
54 | (offsetof(_state, _field) + \ | ||
55 | @@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq; | ||
56 | vmstate_offset_array(_state, _field, uint8_t, \ | ||
57 | sizeof(typeof_field(_state, _field))) | ||
58 | |||
59 | +#define vmstate_offset_varray(_state, _field, _type) \ | ||
60 | + (offsetof(_state, _field) + \ | ||
61 | + type_check_varray(_type, _state, _field)) | ||
62 | + | ||
63 | /* In the macros below, if there is a _version, that means the macro's | ||
64 | * field will be processed only if the version being received is >= | ||
65 | * the _version specified. In general, if you add a new field, you | ||
66 | @@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq; | ||
67 | .info = &(_info), \ | ||
68 | .size = sizeof(_type), \ | ||
69 | .flags = VMS_VARRAY_UINT32|VMS_MULTIPLY_ELEMENTS, \ | ||
70 | - .offset = offsetof(_state, _field), \ | ||
71 | + .offset = vmstate_offset_varray(_state, _field, _type), \ | ||
72 | } | 44 | } |
73 | 45 | ||
74 | #define VMSTATE_ARRAY_TEST(_field, _state, _num, _test, _info, _type) {\ | 46 | +static bool trans_ERET(DisasContext *s, arg_ERET *a) |
75 | @@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq; | 47 | +{ |
76 | .info = &(_info), \ | 48 | + TCGv_i64 dst; |
77 | .size = sizeof(_type), \ | 49 | + |
78 | .flags = VMS_VARRAY_INT32, \ | 50 | + if (s->current_el == 0) { |
79 | - .offset = offsetof(_state, _field), \ | 51 | + return false; |
80 | + .offset = vmstate_offset_varray(_state, _field, _type), \ | 52 | + } |
53 | + if (s->fgt_eret) { | ||
54 | + gen_exception_insn_el(s, 0, EXCP_UDEF, 0, 2); | ||
55 | + return true; | ||
56 | + } | ||
57 | + dst = tcg_temp_new_i64(); | ||
58 | + tcg_gen_ld_i64(dst, cpu_env, | ||
59 | + offsetof(CPUARMState, elr_el[s->current_el])); | ||
60 | + | ||
61 | + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { | ||
62 | + gen_io_start(); | ||
63 | + } | ||
64 | + | ||
65 | + gen_helper_exception_return(cpu_env, dst); | ||
66 | + /* Must exit loop to check un-masked IRQs */ | ||
67 | + s->base.is_jmp = DISAS_EXIT; | ||
68 | + return true; | ||
69 | +} | ||
70 | + | ||
71 | +static bool trans_ERETA(DisasContext *s, arg_reta *a) | ||
72 | +{ | ||
73 | + TCGv_i64 dst; | ||
74 | + | ||
75 | + if (!dc_isar_feature(aa64_pauth, s)) { | ||
76 | + return false; | ||
77 | + } | ||
78 | + if (s->current_el == 0) { | ||
79 | + return false; | ||
80 | + } | ||
81 | + /* The FGT trap takes precedence over an auth trap. */ | ||
82 | + if (s->fgt_eret) { | ||
83 | + gen_exception_insn_el(s, 0, EXCP_UDEF, a->m ? 3 : 2, 2); | ||
84 | + return true; | ||
85 | + } | ||
86 | + dst = tcg_temp_new_i64(); | ||
87 | + tcg_gen_ld_i64(dst, cpu_env, | ||
88 | + offsetof(CPUARMState, elr_el[s->current_el])); | ||
89 | + | ||
90 | + dst = auth_branch_target(s, dst, cpu_X[31], !a->m); | ||
91 | + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { | ||
92 | + gen_io_start(); | ||
93 | + } | ||
94 | + | ||
95 | + gen_helper_exception_return(cpu_env, dst); | ||
96 | + /* Must exit loop to check un-masked IRQs */ | ||
97 | + s->base.is_jmp = DISAS_EXIT; | ||
98 | + return true; | ||
99 | +} | ||
100 | + | ||
101 | /* HINT instruction group, including various allocated HINTs */ | ||
102 | static void handle_hint(DisasContext *s, uint32_t insn, | ||
103 | unsigned int op1, unsigned int op2, unsigned int crm) | ||
104 | @@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn) | ||
105 | } | ||
81 | } | 106 | } |
82 | 107 | ||
83 | #define VMSTATE_VARRAY_INT32(_field, _state, _field_num, _version, _info, _type) {\ | 108 | -/* Unconditional branch (register) |
84 | @@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq; | 109 | - * 31 25 24 21 20 16 15 10 9 5 4 0 |
85 | .info = &(_info), \ | 110 | - * +---------------+-------+-------+-------+------+-------+ |
86 | .size = sizeof(_type), \ | 111 | - * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 | |
87 | .flags = VMS_VARRAY_UINT16, \ | 112 | - * +---------------+-------+-------+-------+------+-------+ |
88 | - .offset = offsetof(_state, _field), \ | 113 | - */ |
89 | + .offset = vmstate_offset_varray(_state, _field, _type), \ | 114 | -static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) |
90 | } | 115 | -{ |
91 | 116 | - unsigned int opc, op2, op3, rn, op4; | |
92 | #define VMSTATE_VSTRUCT_TEST(_field, _state, _test, _version, _vmsd, _type, _struct_version) { \ | 117 | - TCGv_i64 dst; |
93 | @@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq; | 118 | - TCGv_i64 modifier; |
94 | .vmsd = &(_vmsd), \ | 119 | - |
95 | .size = sizeof(_type), \ | 120 | - opc = extract32(insn, 21, 4); |
96 | .flags = VMS_STRUCT|VMS_VARRAY_UINT8, \ | 121 | - op2 = extract32(insn, 16, 5); |
97 | - .offset = offsetof(_state, _field), \ | 122 | - op3 = extract32(insn, 10, 6); |
98 | + .offset = vmstate_offset_varray(_state, _field, _type), \ | 123 | - rn = extract32(insn, 5, 5); |
99 | } | 124 | - op4 = extract32(insn, 0, 5); |
100 | 125 | - | |
101 | /* a variable length array (i.e. _type *_field) but we know the | 126 | - if (op2 != 0x1f) { |
102 | @@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq; | 127 | - goto do_unallocated; |
103 | .vmsd = &(_vmsd), \ | 128 | - } |
104 | .size = sizeof(_type), \ | 129 | - |
105 | .flags = VMS_STRUCT|VMS_VARRAY_INT32, \ | 130 | - switch (opc) { |
106 | - .offset = offsetof(_state, _field), \ | 131 | - case 0: |
107 | + .offset = vmstate_offset_varray(_state, _field, _type), \ | 132 | - case 1: |
108 | } | 133 | - case 2: |
109 | 134 | - case 8: | |
110 | #define VMSTATE_STRUCT_VARRAY_UINT32(_field, _state, _field_num, _version, _vmsd, _type) { \ | 135 | - case 9: |
111 | @@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq; | 136 | - /* |
112 | .vmsd = &(_vmsd), \ | 137 | - * BR, BLR, RET, RETAA, RETAB, BRAAZ, BRABZ, BLRAAZ, BLRABZ, |
113 | .size = sizeof(_type), \ | 138 | - * BRAA, BLRAA: handled in decodetree |
114 | .flags = VMS_STRUCT|VMS_VARRAY_UINT32, \ | 139 | - */ |
115 | - .offset = offsetof(_state, _field), \ | 140 | - goto do_unallocated; |
116 | + .offset = vmstate_offset_varray(_state, _field, _type), \ | 141 | - |
117 | } | 142 | - case 4: /* ERET */ |
118 | 143 | - if (s->current_el == 0) { | |
119 | #define VMSTATE_STRUCT_VARRAY_ALLOC(_field, _state, _field_num, _version, _vmsd, _type) {\ | 144 | - goto do_unallocated; |
145 | - } | ||
146 | - switch (op3) { | ||
147 | - case 0: /* ERET */ | ||
148 | - if (op4 != 0) { | ||
149 | - goto do_unallocated; | ||
150 | - } | ||
151 | - if (s->fgt_eret) { | ||
152 | - gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2); | ||
153 | - return; | ||
154 | - } | ||
155 | - dst = tcg_temp_new_i64(); | ||
156 | - tcg_gen_ld_i64(dst, cpu_env, | ||
157 | - offsetof(CPUARMState, elr_el[s->current_el])); | ||
158 | - break; | ||
159 | - | ||
160 | - case 2: /* ERETAA */ | ||
161 | - case 3: /* ERETAB */ | ||
162 | - if (!dc_isar_feature(aa64_pauth, s)) { | ||
163 | - goto do_unallocated; | ||
164 | - } | ||
165 | - if (rn != 0x1f || op4 != 0x1f) { | ||
166 | - goto do_unallocated; | ||
167 | - } | ||
168 | - /* The FGT trap takes precedence over an auth trap. */ | ||
169 | - if (s->fgt_eret) { | ||
170 | - gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2); | ||
171 | - return; | ||
172 | - } | ||
173 | - dst = tcg_temp_new_i64(); | ||
174 | - tcg_gen_ld_i64(dst, cpu_env, | ||
175 | - offsetof(CPUARMState, elr_el[s->current_el])); | ||
176 | - if (s->pauth_active) { | ||
177 | - modifier = cpu_X[31]; | ||
178 | - if (op3 == 2) { | ||
179 | - gen_helper_autia(dst, cpu_env, dst, modifier); | ||
180 | - } else { | ||
181 | - gen_helper_autib(dst, cpu_env, dst, modifier); | ||
182 | - } | ||
183 | - } | ||
184 | - break; | ||
185 | - | ||
186 | - default: | ||
187 | - goto do_unallocated; | ||
188 | - } | ||
189 | - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { | ||
190 | - gen_io_start(); | ||
191 | - } | ||
192 | - | ||
193 | - gen_helper_exception_return(cpu_env, dst); | ||
194 | - /* Must exit loop to check un-masked IRQs */ | ||
195 | - s->base.is_jmp = DISAS_EXIT; | ||
196 | - return; | ||
197 | - | ||
198 | - case 5: /* DRPS */ | ||
199 | - if (op3 != 0 || op4 != 0 || rn != 0x1f) { | ||
200 | - goto do_unallocated; | ||
201 | - } else { | ||
202 | - unallocated_encoding(s); | ||
203 | - } | ||
204 | - return; | ||
205 | - | ||
206 | - default: | ||
207 | - do_unallocated: | ||
208 | - unallocated_encoding(s); | ||
209 | - return; | ||
210 | - } | ||
211 | -} | ||
212 | - | ||
213 | /* Branches, exception generating and system instructions */ | ||
214 | static void disas_b_exc_sys(DisasContext *s, uint32_t insn) | ||
215 | { | ||
216 | @@ -XXX,XX +XXX,XX @@ static void disas_b_exc_sys(DisasContext *s, uint32_t insn) | ||
217 | disas_exc(s, insn); | ||
218 | } | ||
219 | break; | ||
220 | - case 0x6b: /* Unconditional branch (register) */ | ||
221 | - disas_uncond_b_reg(s, insn); | ||
222 | - break; | ||
223 | default: | ||
224 | unallocated_encoding(s); | ||
225 | break; | ||
120 | -- | 226 | -- |
121 | 2.20.1 | 227 | 2.34.1 |
122 | |||
123 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The IMPDEF sysreg L2CTLR_EL1 found on the Cortex-A35, A53, A57, A72 | ||
2 | and which we (arguably dubiously) also provide in '-cpu max' has a | ||
3 | 2 bit field for the number of processors in the cluster. On real | ||
4 | hardware this must be sufficient because it can only be configured | ||
5 | with up to 4 CPUs in the cluster. However on QEMU if the board code | ||
6 | does not explicitly configure the code into clusters with the right | ||
7 | CPU count we default to "give the value assuming that all CPUs in | ||
8 | the system are in a single cluster", which might be too big to fit | ||
9 | in the field. | ||
1 | 10 | ||
11 | Instead of just overflowing this 2-bit field, saturate to 3 (meaning | ||
12 | "4 CPUs", so at least we don't overwrite other fields in the register. | ||
13 | It's unlikely that any guest code really cares about the value in | ||
14 | this field; at least, if it does it probably also wants the system | ||
15 | to be more closely matching real hardware, i.e. not to have more | ||
16 | than 4 CPUs. | ||
17 | |||
18 | This issue has been present since the L2CTLR was first added in | ||
19 | commit 377a44ec8f2fac5b back in 2014. It was only noticed because | ||
20 | Coverity complains (CID 1509227) that the shift might overflow 32 bits | ||
21 | and inadvertently sign extend into the top half of the 64 bit value. | ||
22 | |||
23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
24 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
25 | Message-id: 20230512170223.3801643-2-peter.maydell@linaro.org | ||
26 | --- | ||
27 | target/arm/cortex-regs.c | 11 +++++++++-- | ||
28 | 1 file changed, 9 insertions(+), 2 deletions(-) | ||
29 | |||
30 | diff --git a/target/arm/cortex-regs.c b/target/arm/cortex-regs.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/arm/cortex-regs.c | ||
33 | +++ b/target/arm/cortex-regs.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
35 | { | ||
36 | ARMCPU *cpu = env_archcpu(env); | ||
37 | |||
38 | - /* Number of cores is in [25:24]; otherwise we RAZ */ | ||
39 | - return (cpu->core_count - 1) << 24; | ||
40 | + /* | ||
41 | + * Number of cores is in [25:24]; otherwise we RAZ. | ||
42 | + * If the board didn't configure the CPUs into clusters, | ||
43 | + * we default to "all CPUs in one cluster", which might be | ||
44 | + * more than the 4 that the hardware permits and which is | ||
45 | + * all you can report in this two-bit field. Saturate to | ||
46 | + * 0b11 (== 4 CPUs) rather than overflowing the field. | ||
47 | + */ | ||
48 | + return MIN(cpu->core_count - 1, 3) << 24; | ||
49 | } | ||
50 | |||
51 | static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { | ||
52 | -- | ||
53 | 2.34.1 | diff view generated by jsdifflib |
1 | gamepad_state::buttons is a pointer to an array of structs, | 1 | In the vexpress board code, we allocate a new MemoryRegion at the top |
---|---|---|---|
2 | not an array of structs, so should be declared in the vmstate | 2 | of vexpress_common_init() but only set it up and use it inside the |
3 | with VMSTATE_STRUCT_VARRAY_POINTER_INT32; otherwise we | 3 | "if (map[VE_NORFLASHALIAS] != -1)" conditional, so we leak it if not. |
4 | corrupt memory on incoming migration. | 4 | This isn't a very interesting leak as it's a tiny amount of memory |
5 | once at startup, but it's easy to fix. | ||
5 | 6 | ||
6 | We bump the vmstate version field as the easiest way to | 7 | We could silence Coverity simply by moving the g_new() into the |
7 | deal with the migration break, since migration wouldn't have | 8 | if() block, but this use of g_new(MemoryRegion, 1) is a legacy from |
8 | worked reliably before anyway. | 9 | when this board model was originally written; we wouldn't do that |
10 | if we wrote it today. The MemoryRegions are conceptually a part of | ||
11 | the board and must not go away until the whole board is done with | ||
12 | (at the end of the simulation), so they belong in its state struct. | ||
13 | |||
14 | This machine already has a VexpressMachineState struct that extends | ||
15 | MachineState, so statically put the MemoryRegions in there instead of | ||
16 | dynamically allocating them separately at runtime. | ||
17 | |||
18 | Spotted by Coverity (CID 1509083). | ||
9 | 19 | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> | 21 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
12 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 22 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
13 | Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> | 23 | Message-id: 20230512170223.3801643-3-peter.maydell@linaro.org |
14 | Message-id: 20190725163710.11703-2-peter.maydell@linaro.org | ||
15 | --- | 24 | --- |
16 | hw/input/stellaris_input.c | 10 ++++++---- | 25 | hw/arm/vexpress.c | 40 ++++++++++++++++++++-------------------- |
17 | 1 file changed, 6 insertions(+), 4 deletions(-) | 26 | 1 file changed, 20 insertions(+), 20 deletions(-) |
18 | 27 | ||
19 | diff --git a/hw/input/stellaris_input.c b/hw/input/stellaris_input.c | 28 | diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c |
20 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/input/stellaris_input.c | 30 | --- a/hw/arm/vexpress.c |
22 | +++ b/hw/input/stellaris_input.c | 31 | +++ b/hw/arm/vexpress.c |
23 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_stellaris_button = { | 32 | @@ -XXX,XX +XXX,XX @@ struct VexpressMachineClass { |
24 | 33 | ||
25 | static const VMStateDescription vmstate_stellaris_gamepad = { | 34 | struct VexpressMachineState { |
26 | .name = "stellaris_gamepad", | 35 | MachineState parent; |
27 | - .version_id = 1, | 36 | + MemoryRegion vram; |
28 | - .minimum_version_id = 1, | 37 | + MemoryRegion sram; |
29 | + .version_id = 2, | 38 | + MemoryRegion flashalias; |
30 | + .minimum_version_id = 2, | 39 | + MemoryRegion lowram; |
31 | .fields = (VMStateField[]) { | 40 | + MemoryRegion a15sram; |
32 | VMSTATE_INT32(extension, gamepad_state), | 41 | bool secure; |
33 | - VMSTATE_STRUCT_VARRAY_INT32(buttons, gamepad_state, num_buttons, 0, | 42 | bool virt; |
34 | - vmstate_stellaris_button, gamepad_button), | 43 | }; |
35 | + VMSTATE_STRUCT_VARRAY_POINTER_INT32(buttons, gamepad_state, | 44 | @@ -XXX,XX +XXX,XX @@ struct VexpressMachineState { |
36 | + num_buttons, | 45 | #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15") |
37 | + vmstate_stellaris_button, | 46 | OBJECT_DECLARE_TYPE(VexpressMachineState, VexpressMachineClass, VEXPRESS_MACHINE) |
38 | + gamepad_button), | 47 | |
39 | VMSTATE_END_OF_LIST() | 48 | -typedef void DBoardInitFn(const VexpressMachineState *machine, |
49 | +typedef void DBoardInitFn(VexpressMachineState *machine, | ||
50 | ram_addr_t ram_size, | ||
51 | const char *cpu_type, | ||
52 | qemu_irq *pic); | ||
53 | @@ -XXX,XX +XXX,XX @@ static void init_cpus(MachineState *ms, const char *cpu_type, | ||
40 | } | 54 | } |
55 | } | ||
56 | |||
57 | -static void a9_daughterboard_init(const VexpressMachineState *vms, | ||
58 | +static void a9_daughterboard_init(VexpressMachineState *vms, | ||
59 | ram_addr_t ram_size, | ||
60 | const char *cpu_type, | ||
61 | qemu_irq *pic) | ||
62 | { | ||
63 | MachineState *machine = MACHINE(vms); | ||
64 | MemoryRegion *sysmem = get_system_memory(); | ||
65 | - MemoryRegion *lowram = g_new(MemoryRegion, 1); | ||
66 | ram_addr_t low_ram_size; | ||
67 | |||
68 | if (ram_size > 0x40000000) { | ||
69 | @@ -XXX,XX +XXX,XX @@ static void a9_daughterboard_init(const VexpressMachineState *vms, | ||
70 | * address space should in theory be remappable to various | ||
71 | * things including ROM or RAM; we always map the RAM there. | ||
72 | */ | ||
73 | - memory_region_init_alias(lowram, NULL, "vexpress.lowmem", machine->ram, | ||
74 | - 0, low_ram_size); | ||
75 | - memory_region_add_subregion(sysmem, 0x0, lowram); | ||
76 | + memory_region_init_alias(&vms->lowram, NULL, "vexpress.lowmem", | ||
77 | + machine->ram, 0, low_ram_size); | ||
78 | + memory_region_add_subregion(sysmem, 0x0, &vms->lowram); | ||
79 | memory_region_add_subregion(sysmem, 0x60000000, machine->ram); | ||
80 | |||
81 | /* 0x1e000000 A9MPCore (SCU) private memory region */ | ||
82 | @@ -XXX,XX +XXX,XX @@ static VEDBoardInfo a9_daughterboard = { | ||
83 | .init = a9_daughterboard_init, | ||
41 | }; | 84 | }; |
85 | |||
86 | -static void a15_daughterboard_init(const VexpressMachineState *vms, | ||
87 | +static void a15_daughterboard_init(VexpressMachineState *vms, | ||
88 | ram_addr_t ram_size, | ||
89 | const char *cpu_type, | ||
90 | qemu_irq *pic) | ||
91 | { | ||
92 | MachineState *machine = MACHINE(vms); | ||
93 | MemoryRegion *sysmem = get_system_memory(); | ||
94 | - MemoryRegion *sram = g_new(MemoryRegion, 1); | ||
95 | |||
96 | { | ||
97 | /* We have to use a separate 64 bit variable here to avoid the gcc | ||
98 | @@ -XXX,XX +XXX,XX @@ static void a15_daughterboard_init(const VexpressMachineState *vms, | ||
99 | /* 0x2b060000: SP805 watchdog: not modelled */ | ||
100 | /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ | ||
101 | /* 0x2e000000: system SRAM */ | ||
102 | - memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000, | ||
103 | + memory_region_init_ram(&vms->a15sram, NULL, "vexpress.a15sram", 0x10000, | ||
104 | &error_fatal); | ||
105 | - memory_region_add_subregion(sysmem, 0x2e000000, sram); | ||
106 | + memory_region_add_subregion(sysmem, 0x2e000000, &vms->a15sram); | ||
107 | |||
108 | /* 0x7ffb0000: DMA330 DMA controller: not modelled */ | ||
109 | /* 0x7ffd0000: PL354 static memory controller: not modelled */ | ||
110 | @@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine) | ||
111 | I2CBus *i2c; | ||
112 | ram_addr_t vram_size, sram_size; | ||
113 | MemoryRegion *sysmem = get_system_memory(); | ||
114 | - MemoryRegion *vram = g_new(MemoryRegion, 1); | ||
115 | - MemoryRegion *sram = g_new(MemoryRegion, 1); | ||
116 | - MemoryRegion *flashalias = g_new(MemoryRegion, 1); | ||
117 | - MemoryRegion *flash0mem; | ||
118 | const hwaddr *map = daughterboard->motherboard_map; | ||
119 | int i; | ||
120 | |||
121 | @@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine) | ||
122 | |||
123 | if (map[VE_NORFLASHALIAS] != -1) { | ||
124 | /* Map flash 0 as an alias into low memory */ | ||
125 | + MemoryRegion *flash0mem; | ||
126 | flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); | ||
127 | - memory_region_init_alias(flashalias, NULL, "vexpress.flashalias", | ||
128 | + memory_region_init_alias(&vms->flashalias, NULL, "vexpress.flashalias", | ||
129 | flash0mem, 0, VEXPRESS_FLASH_SIZE); | ||
130 | - memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias); | ||
131 | + memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], &vms->flashalias); | ||
132 | } | ||
133 | |||
134 | dinfo = drive_get(IF_PFLASH, 0, 1); | ||
135 | ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", dinfo); | ||
136 | |||
137 | sram_size = 0x2000000; | ||
138 | - memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size, | ||
139 | + memory_region_init_ram(&vms->sram, NULL, "vexpress.sram", sram_size, | ||
140 | &error_fatal); | ||
141 | - memory_region_add_subregion(sysmem, map[VE_SRAM], sram); | ||
142 | + memory_region_add_subregion(sysmem, map[VE_SRAM], &vms->sram); | ||
143 | |||
144 | vram_size = 0x800000; | ||
145 | - memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size, | ||
146 | + memory_region_init_ram(&vms->vram, NULL, "vexpress.vram", vram_size, | ||
147 | &error_fatal); | ||
148 | - memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); | ||
149 | + memory_region_add_subregion(sysmem, map[VE_VIDEORAM], &vms->vram); | ||
150 | |||
151 | /* 0x4e000000 LAN9118 Ethernet */ | ||
152 | if (nd_table[0].used) { | ||
42 | -- | 153 | -- |
43 | 2.20.1 | 154 | 2.34.1 |
44 | 155 | ||
45 | 156 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | Convert the u2f.txt file to rST, and place it in the right place | |
2 | in our manual layout. The old text didn't fit very well into our | ||
3 | manual style, so the new version ends up looking like a rewrite, | ||
4 | although some of the original text is preserved: | ||
5 | |||
6 | * the 'building' section of the old file is removed, since we | ||
7 | generally assume that users have already built QEMU | ||
8 | * some rather verbose text has been cut back | ||
9 | * document the passthrough device first, on the assumption | ||
10 | that's most likely to be of interest to users | ||
11 | * cut back on the duplication of text between sections | ||
12 | * format example command lines etc with rST | ||
13 | |||
14 | As it's a short document it seemed simplest to do this all | ||
15 | in one go rather than try to do a minimal syntactic conversion | ||
16 | and then clean up the wording and layout. | ||
17 | |||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
20 | Message-id: 20230421163734.1152076-1-peter.maydell@linaro.org | ||
21 | --- | ||
22 | docs/system/device-emulation.rst | 1 + | ||
23 | docs/system/devices/usb-u2f.rst | 93 ++++++++++++++++++++++++++ | ||
24 | docs/system/devices/usb.rst | 2 +- | ||
25 | docs/u2f.txt | 110 ------------------------------- | ||
26 | 4 files changed, 95 insertions(+), 111 deletions(-) | ||
27 | create mode 100644 docs/system/devices/usb-u2f.rst | ||
28 | delete mode 100644 docs/u2f.txt | ||
29 | |||
30 | diff --git a/docs/system/device-emulation.rst b/docs/system/device-emulation.rst | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/docs/system/device-emulation.rst | ||
33 | +++ b/docs/system/device-emulation.rst | ||
34 | @@ -XXX,XX +XXX,XX @@ Emulated Devices | ||
35 | devices/virtio-pmem.rst | ||
36 | devices/vhost-user-rng.rst | ||
37 | devices/canokey.rst | ||
38 | + devices/usb-u2f.rst | ||
39 | devices/igb.rst | ||
40 | diff --git a/docs/system/devices/usb-u2f.rst b/docs/system/devices/usb-u2f.rst | ||
41 | new file mode 100644 | ||
42 | index XXXXXXX..XXXXXXX | ||
43 | --- /dev/null | ||
44 | +++ b/docs/system/devices/usb-u2f.rst | ||
45 | @@ -XXX,XX +XXX,XX @@ | ||
46 | +Universal Second Factor (U2F) USB Key Device | ||
47 | +============================================ | ||
48 | + | ||
49 | +U2F is an open authentication standard that enables relying parties | ||
50 | +exposed to the internet to offer a strong second factor option for end | ||
51 | +user authentication. | ||
52 | + | ||
53 | +The second factor is provided by a device implementing the U2F | ||
54 | +protocol. In case of a USB U2F security key, it is a USB HID device | ||
55 | +that implements the U2F protocol. | ||
56 | + | ||
57 | +QEMU supports both pass-through of a host U2F key device to a VM, | ||
58 | +and software emulation of a U2F key. | ||
59 | + | ||
60 | +``u2f-passthru`` | ||
61 | +---------------- | ||
62 | + | ||
63 | +The ``u2f-passthru`` device allows you to connect a real hardware | ||
64 | +U2F key on your host to a guest VM. All requests made from the guest | ||
65 | +are passed through to the physical security key connected to the | ||
66 | +host machine and vice versa. | ||
67 | + | ||
68 | +In addition, the dedicated pass-through allows you to share a single | ||
69 | +U2F security key with several guest VMs, which is not possible with a | ||
70 | +simple host device assignment pass-through. | ||
71 | + | ||
72 | +You can specify the host U2F key to use with the ``hidraw`` | ||
73 | +option, which takes the host path to a Linux ``/dev/hidrawN`` device: | ||
74 | + | ||
75 | +.. parsed-literal:: | ||
76 | + |qemu_system| -usb -device u2f-passthru,hidraw=/dev/hidraw0 | ||
77 | + | ||
78 | +If you don't specify the device, the ``u2f-passthru`` device will | ||
79 | +autoscan to take the first U2F device it finds on the host (this | ||
80 | +requires a working libudev): | ||
81 | + | ||
82 | +.. parsed-literal:: | ||
83 | + |qemu_system| -usb -device u2f-passthru | ||
84 | + | ||
85 | +``u2f-emulated`` | ||
86 | +---------------- | ||
87 | + | ||
88 | +``u2f-emulated`` is a completely software emulated U2F device. | ||
89 | +It uses `libu2f-emu <https://github.com/MattGorko/libu2f-emu>`__ | ||
90 | +for the U2F key emulation. libu2f-emu | ||
91 | +provides a complete implementation of the U2F protocol device part for | ||
92 | +all specified transports given by the FIDO Alliance. | ||
93 | + | ||
94 | +To work, an emulated U2F device must have four elements: | ||
95 | + | ||
96 | + * ec x509 certificate | ||
97 | + * ec private key | ||
98 | + * counter (four bytes value) | ||
99 | + * 48 bytes of entropy (random bits) | ||
100 | + | ||
101 | +To use this type of device, these have to be configured, and these | ||
102 | +four elements must be passed one way or another. | ||
103 | + | ||
104 | +Assuming that you have a working libu2f-emu installed on the host, | ||
105 | +there are three possible ways to configure the ``u2f-emulated`` device: | ||
106 | + | ||
107 | + * ephemeral | ||
108 | + * setup directory | ||
109 | + * manual | ||
110 | + | ||
111 | +Ephemeral is the simplest way to configure; it lets the device generate | ||
112 | +all the elements it needs for a single use of the lifetime of the device. | ||
113 | +It is the default if you do not pass any other options to the device. | ||
114 | + | ||
115 | +.. parsed-literal:: | ||
116 | + |qemu_system| -usb -device u2f-emulated | ||
117 | + | ||
118 | +You can pass the device the path of a setup directory on the host | ||
119 | +using the ``dir`` option; the directory must contain these four files: | ||
120 | + | ||
121 | + * ``certificate.pem``: ec x509 certificate | ||
122 | + * ``private-key.pem``: ec private key | ||
123 | + * ``counter``: counter value | ||
124 | + * ``entropy``: 48 bytes of entropy | ||
125 | + | ||
126 | +.. parsed-literal:: | ||
127 | + |qemu_system| -usb -device u2f-emulated,dir=$dir | ||
128 | + | ||
129 | +You can also manually pass the device the paths to each of these files, | ||
130 | +if you don't want them all to be in the same directory, using the options | ||
131 | + | ||
132 | + * ``cert`` | ||
133 | + * ``priv`` | ||
134 | + * ``counter`` | ||
135 | + * ``entropy`` | ||
136 | + | ||
137 | +.. parsed-literal:: | ||
138 | + |qemu_system| -usb -device u2f-emulated,cert=$DIR1/$FILE1,priv=$DIR2/$FILE2,counter=$DIR3/$FILE3,entropy=$DIR4/$FILE4 | ||
139 | diff --git a/docs/system/devices/usb.rst b/docs/system/devices/usb.rst | ||
140 | index XXXXXXX..XXXXXXX 100644 | ||
141 | --- a/docs/system/devices/usb.rst | ||
142 | +++ b/docs/system/devices/usb.rst | ||
143 | @@ -XXX,XX +XXX,XX @@ option or the ``device_add`` monitor command. Available devices are: | ||
144 | USB audio device | ||
145 | |||
146 | ``u2f-{emulated,passthru}`` | ||
147 | - Universal Second Factor device | ||
148 | + :doc:`usb-u2f` | ||
149 | |||
150 | ``canokey`` | ||
151 | An Open-source Secure Key implementing FIDO2, OpenPGP, PIV and more. | ||
152 | diff --git a/docs/u2f.txt b/docs/u2f.txt | ||
153 | deleted file mode 100644 | ||
154 | index XXXXXXX..XXXXXXX | ||
155 | --- a/docs/u2f.txt | ||
156 | +++ /dev/null | ||
157 | @@ -XXX,XX +XXX,XX @@ | ||
158 | -QEMU U2F Key Device Documentation. | ||
159 | - | ||
160 | -Contents | ||
161 | -1. USB U2F key device | ||
162 | -2. Building | ||
163 | -3. Using u2f-emulated | ||
164 | -4. Using u2f-passthru | ||
165 | -5. Libu2f-emu | ||
166 | - | ||
167 | -1. USB U2F key device | ||
168 | - | ||
169 | -U2F is an open authentication standard that enables relying parties | ||
170 | -exposed to the internet to offer a strong second factor option for end | ||
171 | -user authentication. | ||
172 | - | ||
173 | -The standard brings many advantages to both parties, client and server, | ||
174 | -allowing to reduce over-reliance on passwords, it increases authentication | ||
175 | -security and simplifies passwords. | ||
176 | - | ||
177 | -The second factor is materialized by a device implementing the U2F | ||
178 | -protocol. In case of a USB U2F security key, it is a USB HID device | ||
179 | -that implements the U2F protocol. | ||
180 | - | ||
181 | -In QEMU, the USB U2F key device offers a dedicated support of U2F, allowing | ||
182 | -guest USB FIDO/U2F security keys operating in two possible modes: | ||
183 | -pass-through and emulated. | ||
184 | - | ||
185 | -The pass-through mode consists of passing all requests made from the guest | ||
186 | -to the physical security key connected to the host machine and vice versa. | ||
187 | -In addition, the dedicated pass-through allows to have a U2F security key | ||
188 | -shared on several guests which is not possible with a simple host device | ||
189 | -assignment pass-through. | ||
190 | - | ||
191 | -The emulated mode consists of completely emulating the behavior of an | ||
192 | -U2F device through software part. Libu2f-emu is used for that. | ||
193 | - | ||
194 | - | ||
195 | -2. Building | ||
196 | - | ||
197 | -To ensure the build of the u2f-emulated device variant which depends | ||
198 | -on libu2f-emu: configuring and building: | ||
199 | - | ||
200 | - ./configure --enable-u2f && make | ||
201 | - | ||
202 | -The pass-through mode is built by default on Linux. To take advantage | ||
203 | -of the autoscan option it provides, make sure you have a working libudev | ||
204 | -installed on the host. | ||
205 | - | ||
206 | - | ||
207 | -3. Using u2f-emulated | ||
208 | - | ||
209 | -To work, an emulated U2F device must have four elements: | ||
210 | - * ec x509 certificate | ||
211 | - * ec private key | ||
212 | - * counter (four bytes value) | ||
213 | - * 48 bytes of entropy (random bits) | ||
214 | - | ||
215 | -To use this type of device, this one has to be configured, and these | ||
216 | -four elements must be passed one way or another. | ||
217 | - | ||
218 | -Assuming that you have a working libu2f-emu installed on the host. | ||
219 | -There are three possible ways of configurations: | ||
220 | - * ephemeral | ||
221 | - * setup directory | ||
222 | - * manual | ||
223 | - | ||
224 | -Ephemeral is the simplest way to configure, it lets the device generate | ||
225 | -all the elements it needs for a single use of the lifetime of the device. | ||
226 | - | ||
227 | - qemu -usb -device u2f-emulated | ||
228 | - | ||
229 | -Setup directory allows to configure the device from a directory containing | ||
230 | -four files: | ||
231 | - * certificate.pem: ec x509 certificate | ||
232 | - * private-key.pem: ec private key | ||
233 | - * counter: counter value | ||
234 | - * entropy: 48 bytes of entropy | ||
235 | - | ||
236 | - qemu -usb -device u2f-emulated,dir=$dir | ||
237 | - | ||
238 | -Manual allows to configure the device more finely by specifying each | ||
239 | -of the elements necessary for the device: | ||
240 | - * cert | ||
241 | - * priv | ||
242 | - * counter | ||
243 | - * entropy | ||
244 | - | ||
245 | - qemu -usb -device u2f-emulated,cert=$DIR1/$FILE1,priv=$DIR2/$FILE2,counter=$DIR3/$FILE3,entropy=$DIR4/$FILE4 | ||
246 | - | ||
247 | - | ||
248 | -4. Using u2f-passthru | ||
249 | - | ||
250 | -On the host specify the u2f-passthru device with a suitable hidraw: | ||
251 | - | ||
252 | - qemu -usb -device u2f-passthru,hidraw=/dev/hidraw0 | ||
253 | - | ||
254 | -Alternately, the u2f-passthru device can autoscan to take the first | ||
255 | -U2F device it finds on the host (this requires a working libudev): | ||
256 | - | ||
257 | - qemu -usb -device u2f-passthru | ||
258 | - | ||
259 | - | ||
260 | -5. Libu2f-emu | ||
261 | - | ||
262 | -The u2f-emulated device uses libu2f-emu for the U2F key emulation. Libu2f-emu | ||
263 | -implements completely the U2F protocol device part for all specified | ||
264 | -transport given by the FIDO Alliance. | ||
265 | - | ||
266 | -For more information about libu2f-emu see this page: | ||
267 | -https://github.com/MattGorko/libu2f-emu. | ||
268 | -- | ||
269 | 2.34.1 | diff view generated by jsdifflib |