| 1 | target-arm queue for rc2. This has 3 Arm related bug fixes, | 1 | This one's almost all docs fixes. |
|---|---|---|---|
| 2 | and a couple of non-arm patches which don't have an obviously | ||
| 3 | better route into the tree. | ||
| 4 | 2 | ||
| 5 | thanks | 3 | thanks |
| 6 | -- PMM | 4 | -- PMM |
| 7 | 5 | ||
| 8 | The following changes since commit b9e02bb3f98174209dbd5c96858e65a31723221b: | 6 | The following changes since commit ba54a7e6b86884e43bed2d2f5a79c719059652a8: |
| 9 | 7 | ||
| 10 | Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2019-07-19' into staging (2019-07-22 10:11:28 +0100) | 8 | Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2024-11-26 14:06:40 +0000) |
| 11 | 9 | ||
| 12 | are available in the Git repository at: | 10 | are available in the Git repository at: |
| 13 | 11 | ||
| 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190722 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241126 |
| 15 | 13 | ||
| 16 | for you to fetch changes up to ddb45afbfbc639365d6c934e4e29f6de5e5e2a0e: | 14 | for you to fetch changes up to d8790ead55a2ef1e65332ebec63ae3c5db598942: |
| 17 | 15 | ||
| 18 | contrib/elf2dmp: Build download.o with CURL_CFLAGS (2019-07-22 14:07:39 +0100) | 16 | docs/system/arm/aspeed: add missing model supermicrox11spi-bmc (2024-11-26 16:22:38 +0000) |
| 19 | 17 | ||
| 20 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
| 21 | target-arm queue: | 19 | target-arm queue: |
| 22 | * target/arm: Add missing break statement for Hypervisor Trap Exception | 20 | * target/arm/tcg/cpu32.c: swap ATCM and BTCM register names |
| 23 | (fixes handling of SMC insn taken to AArch32 Hyp mode via HCR.TSC) | 21 | * docs/system/arm: Fix broken links and missing feature names |
| 24 | * hw/arm/fsl-imx6ul.c: Remove dead SMP-related code | ||
| 25 | * target/arm: Limit ID register assertions to TCG | ||
| 26 | * configure: Clarify URL to source downloads | ||
| 27 | * contrib/elf2dmp: Build download.o with CURL_CFLAGS | ||
| 28 | 22 | ||
| 29 | ---------------------------------------------------------------- | 23 | ---------------------------------------------------------------- |
| 30 | Peter Maydell (4): | 24 | Michael Tokarev (1): |
| 31 | hw/arm/fsl-imx6ul.c: Remove dead SMP-related code | 25 | target/arm/tcg/cpu32.c: swap ATCM and BTCM register names |
| 32 | target/arm: Limit ID register assertions to TCG | ||
| 33 | configure: Clarify URL to source downloads | ||
| 34 | contrib/elf2dmp: Build download.o with CURL_CFLAGS | ||
| 35 | 26 | ||
| 36 | Philippe Mathieu-Daudé (1): | 27 | Pierrick Bouvier (8): |
| 37 | target/arm: Add missing break statement for Hypervisor Trap Exception | 28 | docs/system/arm/emulation: mention armv9 |
| 29 | docs/system/arm/emulation: fix typo in feature name | ||
| 30 | docs/system/arm/emulation: add FEAT_SSBS2 | ||
| 31 | target/arm/tcg/: fix typo in FEAT name | ||
| 32 | docs/system/arm/: add FEAT_MTE_ASYNC | ||
| 33 | docs/system/arm/: add FEAT_DoubleLock | ||
| 34 | docs/system/arm/fby35: update link to product page | ||
| 35 | docs/system/arm/aspeed: add missing model supermicrox11spi-bmc | ||
| 38 | 36 | ||
| 39 | configure | 2 +- | 37 | docs/system/arm/aspeed.rst | 7 ++++--- |
| 40 | Makefile | 1 - | 38 | docs/system/arm/emulation.rst | 11 +++++++---- |
| 41 | contrib/elf2dmp/Makefile.objs | 3 +++ | 39 | docs/system/arm/fby35.rst | 2 +- |
| 42 | include/hw/arm/fsl-imx6ul.h | 2 +- | 40 | target/arm/tcg/cpu32.c | 6 +++--- |
| 43 | hw/arm/fsl-imx6ul.c | 62 +++++++++++++------------------------------ | 41 | 4 files changed, 15 insertions(+), 11 deletions(-) |
| 44 | hw/arm/mcimx6ul-evk.c | 2 +- | ||
| 45 | target/arm/cpu.c | 7 +++-- | ||
| 46 | target/arm/helper.c | 1 + | ||
| 47 | 8 files changed, 30 insertions(+), 50 deletions(-) | ||
| 48 | diff view generated by jsdifflib |
| 1 | contrib/elf2dmp has a source file which uses curl/curl.h; | 1 | From: Michael Tokarev <mjt@tls.msk.ru> |
|---|---|---|---|
| 2 | although we link the final executable with CURL_LIBS, we | ||
| 3 | forgot to build this source file with CURL_CFLAGS, so if | ||
| 4 | the curl header is in a place that's not already on the | ||
| 5 | system include path then it will fail to build. | ||
| 6 | 2 | ||
| 7 | Add a line specifying the cflags needed for download.o; | 3 | According to Cortex-R5 r1p2 manual, register with opcode2=0 is |
| 8 | while we are here, bring the specification of the libs | 4 | BTCM and with opcode2=1 is ATCM, - exactly the opposite from how |
| 9 | into line with this, since using a per-object variable | 5 | qemu labels them. Just swap the labels to avoid confusion, - |
| 10 | setting is preferred over adding them to the final | 6 | both registers are implemented as always-zero. |
| 11 | executable link line. | ||
| 12 | 7 | ||
| 8 | Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> | ||
| 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 10 | Message-id: 20241121171602.3273252-1-mjt@tls.msk.ru | ||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 14 | Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> | ||
| 15 | Message-id: 20190719100955.17180-1-peter.maydell@linaro.org | ||
| 16 | --- | 12 | --- |
| 17 | Makefile | 1 - | 13 | target/arm/tcg/cpu32.c | 4 ++-- |
| 18 | contrib/elf2dmp/Makefile.objs | 3 +++ | 14 | 1 file changed, 2 insertions(+), 2 deletions(-) |
| 19 | 2 files changed, 3 insertions(+), 1 deletion(-) | ||
| 20 | 15 | ||
| 21 | diff --git a/Makefile b/Makefile | 16 | diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c |
| 22 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 23 | --- a/Makefile | 18 | --- a/target/arm/tcg/cpu32.c |
| 24 | +++ b/Makefile | 19 | +++ b/target/arm/tcg/cpu32.c |
| 25 | @@ -XXX,XX +XXX,XX @@ ifneq ($(EXESUF),) | 20 | @@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj) |
| 26 | qemu-ga: qemu-ga$(EXESUF) $(QGA_VSS_PROVIDER) $(QEMU_GA_MSI) | 21 | |
| 27 | endif | 22 | static const ARMCPRegInfo cortexr5_cp_reginfo[] = { |
| 28 | 23 | /* Dummy the TCM region regs for the moment */ | |
| 29 | -elf2dmp$(EXESUF): LIBS += $(CURL_LIBS) | 24 | - { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, |
| 30 | elf2dmp$(EXESUF): $(elf2dmp-obj-y) | 25 | + { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, |
| 31 | $(call LINK, $^) | 26 | .access = PL1_RW, .type = ARM_CP_CONST }, |
| 32 | 27 | - { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
| 33 | diff --git a/contrib/elf2dmp/Makefile.objs b/contrib/elf2dmp/Makefile.objs | 28 | + { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, |
| 34 | index XXXXXXX..XXXXXXX 100644 | 29 | .access = PL1_RW, .type = ARM_CP_CONST }, |
| 35 | --- a/contrib/elf2dmp/Makefile.objs | 30 | { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, |
| 36 | +++ b/contrib/elf2dmp/Makefile.objs | 31 | .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, |
| 37 | @@ -1 +1,4 @@ | ||
| 38 | elf2dmp-obj-y = main.o addrspace.o download.o pdb.o qemu_elf.o | ||
| 39 | + | ||
| 40 | +download.o-cflags := $(CURL_CFLAGS) | ||
| 41 | +download.o-libs := $(CURL_LIBS) | ||
| 42 | -- | 32 | -- |
| 43 | 2.20.1 | 33 | 2.34.1 |
| 44 | |||
| 45 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
| 1 | 2 | ||
| 3 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
| 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20241122225049.1617774-2-pierrick.bouvier@linaro.org | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | --- | ||
| 8 | docs/system/arm/emulation.rst | 6 +++--- | ||
| 9 | 1 file changed, 3 insertions(+), 3 deletions(-) | ||
| 10 | |||
| 11 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
| 12 | index XXXXXXX..XXXXXXX 100644 | ||
| 13 | --- a/docs/system/arm/emulation.rst | ||
| 14 | +++ b/docs/system/arm/emulation.rst | ||
| 15 | @@ -XXX,XX +XXX,XX @@ | ||
| 16 | A-profile CPU architecture support | ||
| 17 | ================================== | ||
| 18 | |||
| 19 | -QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7 and | ||
| 20 | -Armv8 versions of the A-profile architecture. It also has support for | ||
| 21 | +QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7, | ||
| 22 | +Armv8 and Armv9 versions of the A-profile architecture. It also has support for | ||
| 23 | the following architecture extensions: | ||
| 24 | |||
| 25 | - FEAT_AA32BF16 (AArch32 BFloat16 instructions) | ||
| 26 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
| 27 | - FEAT_XNX (Translation table stage 2 Unprivileged Execute-never) | ||
| 28 | |||
| 29 | For information on the specifics of these extensions, please refer | ||
| 30 | -to the `Armv8-A Arm Architecture Reference Manual | ||
| 31 | +to the `Arm Architecture Reference Manual for A-profile architecture | ||
| 32 | <https://developer.arm.com/documentation/ddi0487/latest>`_. | ||
| 33 | |||
| 34 | When a specific named CPU is being emulated, only those features which | ||
| 35 | -- | ||
| 36 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
| 1 | 2 | ||
| 3 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
| 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20241122225049.1617774-3-pierrick.bouvier@linaro.org | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | --- | ||
| 8 | docs/system/arm/emulation.rst | 2 +- | ||
| 9 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 10 | |||
| 11 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
| 12 | index XXXXXXX..XXXXXXX 100644 | ||
| 13 | --- a/docs/system/arm/emulation.rst | ||
| 14 | +++ b/docs/system/arm/emulation.rst | ||
| 15 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
| 16 | - FEAT_LSE2 (Large System Extensions v2) | ||
| 17 | - FEAT_LVA (Large Virtual Address space) | ||
| 18 | - FEAT_MixedEnd (Mixed-endian support) | ||
| 19 | -- FEAT_MixdEndEL0 (Mixed-endian support at EL0) | ||
| 20 | +- FEAT_MixedEndEL0 (Mixed-endian support at EL0) | ||
| 21 | - FEAT_MOPS (Standardization of memory operations) | ||
| 22 | - FEAT_MTE (Memory Tagging Extension) | ||
| 23 | - FEAT_MTE2 (Memory Tagging Extension) | ||
| 24 | -- | ||
| 25 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
| 1 | 2 | ||
| 3 | We implemented this at the same times as FEAT_SSBS, but forgot | ||
| 4 | to list it in the documentation. | ||
| 5 | |||
| 6 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20241122225049.1617774-4-pierrick.bouvier@linaro.org | ||
| 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | [PMM: improve commit message] | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 12 | --- | ||
| 13 | docs/system/arm/emulation.rst | 1 + | ||
| 14 | 1 file changed, 1 insertion(+) | ||
| 15 | |||
| 16 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/docs/system/arm/emulation.rst | ||
| 19 | +++ b/docs/system/arm/emulation.rst | ||
| 20 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
| 21 | - FEAT_SVE2 (Scalable Vector Extension version 2) | ||
| 22 | - FEAT_SPECRES (Speculation restriction instructions) | ||
| 23 | - FEAT_SSBS (Speculative Store Bypass Safe) | ||
| 24 | +- FEAT_SSBS2 (MRS and MSR instructions for SSBS version 2) | ||
| 25 | - FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1) | ||
| 26 | - FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1) | ||
| 27 | - FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1) | ||
| 28 | -- | ||
| 29 | 2.34.1 | diff view generated by jsdifflib |
| 1 | If configure detects that it's being run on a source tree which | 1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
|---|---|---|---|
| 2 | is missing git modules, it prints an error messages suggesting | ||
| 3 | that the user downloads a correct source archive from the project | ||
| 4 | website. However https://www.qemu.org/download/ is a link to a | ||
| 5 | page with multiple tabs, with the default being the one telling | ||
| 6 | users how to get binaries from their distro. Clarify the URL | ||
| 7 | we print to include the #source anchor, so that the browser will | ||
| 8 | go directly to the source-tarball instructions. | ||
| 9 | 2 | ||
| 10 | Reported-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 3 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
| 11 | Reviewed-by: Thomas Huth <thuth@redhat.com> | 4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 12 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 13 | Reviewed-by: Stefan Weil <sw@weilnetz.de> | 6 | Message-id: 20241122225049.1617774-5-pierrick.bouvier@linaro.org |
| 14 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | Message-id: 20190718131659.20783-1-peter.maydell@linaro.org | ||
| 17 | Suggested-by: Stefan Weil <sw@weilnetz.de> | ||
| 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 19 | --- | 8 | --- |
| 20 | configure | 2 +- | 9 | target/arm/tcg/cpu32.c | 2 +- |
| 21 | 1 file changed, 1 insertion(+), 1 deletion(-) | 10 | 1 file changed, 1 insertion(+), 1 deletion(-) |
| 22 | 11 | ||
| 23 | diff --git a/configure b/configure | 12 | diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c |
| 24 | index XXXXXXX..XXXXXXX 100755 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 25 | --- a/configure | 14 | --- a/target/arm/tcg/cpu32.c |
| 26 | +++ b/configure | 15 | +++ b/target/arm/tcg/cpu32.c |
| 27 | @@ -XXX,XX +XXX,XX @@ else | 16 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) |
| 28 | echo "to acquire QEMU source archives. Non-GIT builds are only" | 17 | cpu->isar.id_mmfr5 = t; |
| 29 | echo "supported with source archives linked from:" | 18 | |
| 30 | echo | 19 | t = cpu->isar.id_pfr0; |
| 31 | - echo " https://www.qemu.org/download/" | 20 | - t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ |
| 32 | + echo " https://www.qemu.org/download/#source" | 21 | + t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ |
| 33 | echo | 22 | t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ |
| 34 | echo "Developers working with GIT can use scripts/archive-source.sh" | 23 | t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ |
| 35 | echo "if they need to create valid source archives." | 24 | cpu->isar.id_pfr0 = t; |
| 36 | -- | 25 | -- |
| 37 | 2.20.1 | 26 | 2.34.1 |
| 38 | 27 | ||
| 39 | 28 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
| 1 | 2 | ||
| 3 | We already implement FEAT_MTE_ASYNC; we just forgot to list it | ||
| 4 | in the documentation. | ||
| 5 | |||
| 6 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20241122225049.1617774-6-pierrick.bouvier@linaro.org | ||
| 9 | [PMM: expand commit message] | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | docs/system/arm/emulation.rst | 1 + | ||
| 13 | 1 file changed, 1 insertion(+) | ||
| 14 | |||
| 15 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/docs/system/arm/emulation.rst | ||
| 18 | +++ b/docs/system/arm/emulation.rst | ||
| 19 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
| 20 | - FEAT_MTE2 (Memory Tagging Extension) | ||
| 21 | - FEAT_MTE3 (MTE Asymmetric Fault Handling) | ||
| 22 | - FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults) | ||
| 23 | +- FEAT_MTE_ASYNC (Asynchronous reporting of Tag Check Fault) | ||
| 24 | - FEAT_NMI (Non-maskable Interrupt) | ||
| 25 | - FEAT_NV (Nested Virtualization) | ||
| 26 | - FEAT_NV2 (Enhanced nested virtualization support) | ||
| 27 | -- | ||
| 28 | 2.34.1 | diff view generated by jsdifflib |
| 1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Reported by GCC9 when building with -Wimplicit-fallthrough=2: | 3 | We already implement FEAT_DoubleLock (see commit f94a6df5dd6a7) when |
| 4 | the ID registers call for it. This feature is actually one that must | ||
| 5 | *not* be implemented in v9.0, but since our documentation lists | ||
| 6 | everything we can emulate, we should include FEAT_DoubleLock in the | ||
| 7 | list. | ||
| 4 | 8 | ||
| 5 | target/arm/helper.c: In function ‘arm_cpu_do_interrupt_aarch32_hyp’: | 9 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
| 6 | target/arm/helper.c:7958:14: error: this statement may fall through [-Werror=implicit-fallthrough=] | 10 | Message-id: 20241122225049.1617774-7-pierrick.bouvier@linaro.org |
| 7 | 7958 | addr = 0x14; | ||
| 8 | | ~~~~~^~~~~~ | ||
| 9 | target/arm/helper.c:7959:5: note: here | ||
| 10 | 7959 | default: | ||
| 11 | | ^~~~~~~ | ||
| 12 | cc1: all warnings being treated as errors | ||
| 13 | |||
| 14 | Fixes: b9bc21ff9f9 | ||
| 15 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 16 | Reported-by: Stefan Weil <sw@weilnetz.de> | ||
| 17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 18 | Message-id: 20190719111451.12406-1-philmd@redhat.com | 12 | [PMM: expand commit message] |
| 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 20 | --- | 14 | --- |
| 21 | target/arm/helper.c | 1 + | 15 | docs/system/arm/emulation.rst | 1 + |
| 22 | 1 file changed, 1 insertion(+) | 16 | 1 file changed, 1 insertion(+) |
| 23 | 17 | ||
| 24 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 18 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
| 25 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
| 26 | --- a/target/arm/helper.c | 20 | --- a/docs/system/arm/emulation.rst |
| 27 | +++ b/target/arm/helper.c | 21 | +++ b/docs/system/arm/emulation.rst |
| 28 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) | 22 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
| 29 | break; | 23 | - FEAT_CSV3 (Cache speculation variant 3) |
| 30 | case EXCP_HYP_TRAP: | 24 | - FEAT_DGH (Data gathering hint) |
| 31 | addr = 0x14; | 25 | - FEAT_DIT (Data Independent Timing instructions) |
| 32 | + break; | 26 | +- FEAT_DoubleLock (Double Lock) |
| 33 | default: | 27 | - FEAT_DPB (DC CVAP instruction) |
| 34 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | 28 | - FEAT_DPB2 (DC CVADP instruction) |
| 35 | } | 29 | - FEAT_Debugv8p1 (Debug with VHE) |
| 36 | -- | 30 | -- |
| 37 | 2.20.1 | 31 | 2.34.1 |
| 38 | |||
| 39 | diff view generated by jsdifflib |
| 1 | In arm_cpu_realizefn() we make several assertions about the values of | 1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
|---|---|---|---|
| 2 | guest ID registers: | ||
| 3 | * if the CPU provides AArch32 v7VE or better it must advertise the | ||
| 4 | ARM_DIV feature | ||
| 5 | * if the CPU provides AArch32 A-profile v6 or better it must | ||
| 6 | advertise the Jazelle feature | ||
| 7 | 2 | ||
| 8 | These are essentially consistency checks that our ID register | 3 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
| 9 | specifications in cpu.c didn't accidentally miss out a feature, | 4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 10 | because increasingly the TCG emulation gates features on the values | ||
| 11 | in ID registers rather than using old-style checks of ARM_FEATURE_FOO | ||
| 12 | bits. | ||
| 13 | |||
| 14 | Unfortunately, these asserts can cause problems if we're running KVM, | ||
| 15 | because in that case we don't control the values of the ID registers | ||
| 16 | -- we read them from the host kernel. In particular, if the host | ||
| 17 | kernel is older than 4.15 then it doesn't expose the ID registers via | ||
| 18 | the KVM_GET_ONE_REG ioctl, and we set up dummy values for some | ||
| 19 | registers and leave the rest at zero. (See the comment in | ||
| 20 | target/arm/kvm64.c kvm_arm_get_host_cpu_features().) This set of | ||
| 21 | dummy values is not sufficient to pass our assertions, and so on | ||
| 22 | those kernels running an AArch32 guest on AArch64 will assert. | ||
| 23 | |||
| 24 | We could provide a more sophisticated set of dummy ID registers in | ||
| 25 | this case, but that still leaves the possibility of a host CPU which | ||
| 26 | reports bogus ID register values that would cause us to assert. It's | ||
| 27 | more robust to only do these ID register checks if we're using TCG, | ||
| 28 | as that is the only case where this is truly a QEMU code bug. | ||
| 29 | |||
| 30 | Reported-by: Laszlo Ersek <lersek@redhat.com> | ||
| 31 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 32 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 6 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 33 | Tested-by: Laszlo Ersek <lersek@redhat.com> | 7 | Message-id: 20241122225049.1617774-8-pierrick.bouvier@linaro.org |
| 34 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 35 | Message-id: 20190718125928.20147-1-peter.maydell@linaro.org | ||
| 36 | Fixes: https://bugs.launchpad.net/qemu/+bug/1830864 | ||
| 37 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 38 | --- | 9 | --- |
| 39 | target/arm/cpu.c | 7 +++++-- | 10 | docs/system/arm/fby35.rst | 2 +- |
| 40 | 1 file changed, 5 insertions(+), 2 deletions(-) | 11 | 1 file changed, 1 insertion(+), 1 deletion(-) |
| 41 | 12 | ||
| 42 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 13 | diff --git a/docs/system/arm/fby35.rst b/docs/system/arm/fby35.rst |
| 43 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
| 44 | --- a/target/arm/cpu.c | 15 | --- a/docs/system/arm/fby35.rst |
| 45 | +++ b/target/arm/cpu.c | 16 | +++ b/docs/system/arm/fby35.rst |
| 46 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 17 | @@ -XXX,XX +XXX,XX @@ include various compute accelerators (video, inferencing, etc). At the moment, |
| 47 | * There exist AArch64 cpus without AArch32 support. When KVM | 18 | only the first server slot's BIC is included. |
| 48 | * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. | 19 | |
| 49 | * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. | 20 | Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds |
| 50 | + * As a general principle, we also do not make ID register | 21 | -can be fit into a chassis. See `here <https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server>`__ |
| 51 | + * consistency checks anywhere unless using TCG, because only | 22 | +can be fit into a chassis. See `here <https://www.opencompute.org/products-chiplets/237/wiwynn-yosemite-v3-server>`__ |
| 52 | + * for TCG would a consistency-check failure be a QEMU bug. | 23 | for an example. |
| 53 | */ | 24 | |
| 54 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | 25 | In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC |
| 55 | no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); | ||
| 56 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
| 57 | * Presence of EL2 itself is ARM_FEATURE_EL2, and of the | ||
| 58 | * Security Extensions is ARM_FEATURE_EL3. | ||
| 59 | */ | ||
| 60 | - assert(no_aa32 || cpu_isar_feature(arm_div, cpu)); | ||
| 61 | + assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu)); | ||
| 62 | set_feature(env, ARM_FEATURE_LPAE); | ||
| 63 | set_feature(env, ARM_FEATURE_V7); | ||
| 64 | } | ||
| 65 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
| 66 | if (arm_feature(env, ARM_FEATURE_V6)) { | ||
| 67 | set_feature(env, ARM_FEATURE_V5); | ||
| 68 | if (!arm_feature(env, ARM_FEATURE_M)) { | ||
| 69 | - assert(no_aa32 || cpu_isar_feature(jazelle, cpu)); | ||
| 70 | + assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle, cpu)); | ||
| 71 | set_feature(env, ARM_FEATURE_AUXCR); | ||
| 72 | } | ||
| 73 | } | ||
| 74 | -- | 26 | -- |
| 75 | 2.20.1 | 27 | 2.34.1 |
| 76 | 28 | ||
| 77 | 29 | diff view generated by jsdifflib |
| 1 | The i.MX6UL always has a single Cortex-A7 CPU (we set FSL_IMX6UL_NUM_CPUS | 1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
|---|---|---|---|
| 2 | to 1 in line with this). This means that all the code in fsl-imx6ul.c to | ||
| 3 | handle multiple CPUs is dead code, and Coverity is now complaining that | ||
| 4 | it is unreachable (CID 1403008, 1403011). | ||
| 5 | 2 | ||
| 6 | Remove the unreachable code and the only-executes-once loops, | 3 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
| 7 | and replace the single-entry cpu[] array in the FSLIMX6ULState | 4 | Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> |
| 8 | with a simple cpu member. | 5 | Message-id: 20241122225049.1617774-13-pierrick.bouvier@linaro.org |
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | --- | ||
| 8 | docs/system/arm/aspeed.rst | 7 ++++--- | ||
| 9 | 1 file changed, 4 insertions(+), 3 deletions(-) | ||
| 9 | 10 | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst |
| 11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 12 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 13 | Message-id: 20190712115030.26895-1-peter.maydell@linaro.org | ||
| 14 | --- | ||
| 15 | include/hw/arm/fsl-imx6ul.h | 2 +- | ||
| 16 | hw/arm/fsl-imx6ul.c | 62 +++++++++++-------------------------- | ||
| 17 | hw/arm/mcimx6ul-evk.c | 2 +- | ||
| 18 | 3 files changed, 20 insertions(+), 46 deletions(-) | ||
| 19 | |||
| 20 | diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
| 22 | --- a/include/hw/arm/fsl-imx6ul.h | 13 | --- a/docs/system/arm/aspeed.rst |
| 23 | +++ b/include/hw/arm/fsl-imx6ul.h | 14 | +++ b/docs/system/arm/aspeed.rst |
| 24 | @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6ULState { | ||
| 25 | DeviceState parent_obj; | ||
| 26 | |||
| 27 | /*< public >*/ | ||
| 28 | - ARMCPU cpu[FSL_IMX6UL_NUM_CPUS]; | ||
| 29 | + ARMCPU cpu; | ||
| 30 | A15MPPrivState a7mpcore; | ||
| 31 | IMXGPTState gpt[FSL_IMX6UL_NUM_GPTS]; | ||
| 32 | IMXEPITState epit[FSL_IMX6UL_NUM_EPITS]; | ||
| 33 | diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c | ||
| 34 | index XXXXXXX..XXXXXXX 100644 | ||
| 35 | --- a/hw/arm/fsl-imx6ul.c | ||
| 36 | +++ b/hw/arm/fsl-imx6ul.c | ||
| 37 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ |
| 38 | 16 | -Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``) | |
| 39 | static void fsl_imx6ul_init(Object *obj) | 17 | -======================================================================================================================================================================================================================================================================================================================================================================================================== |
| 40 | { | 18 | +Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``) |
| 41 | - MachineState *ms = MACHINE(qdev_get_machine()); | 19 | +================================================================================================================================================================================================================================================================================================================================================================================================================================== |
| 42 | FslIMX6ULState *s = FSL_IMX6UL(obj); | 20 | |
| 43 | char name[NAME_SIZE]; | 21 | The QEMU Aspeed machines model BMCs of various OpenPOWER systems and |
| 44 | int i; | 22 | Aspeed evaluation boards. They are based on different releases of the |
| 45 | 23 | @@ -XXX,XX +XXX,XX @@ AST2400 SoC based machines : | |
| 46 | - for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6UL_NUM_CPUS); i++) { | 24 | |
| 47 | - snprintf(name, NAME_SIZE, "cpu%d", i); | 25 | - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC |
| 48 | - object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]), | 26 | - ``quanta-q71l-bmc`` OpenBMC Quanta BMC |
| 49 | - "cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL); | 27 | -- ``supermicrox11-bmc`` Supermicro X11 BMC |
| 50 | - } | 28 | +- ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S) |
| 51 | + object_initialize_child(obj, "cpu0", &s->cpu, sizeof(s->cpu), | 29 | +- ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176) |
| 52 | + "cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL); | 30 | |
| 53 | 31 | AST2500 SoC based machines : | |
| 54 | /* | ||
| 55 | * A7MPCORE | ||
| 56 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
| 57 | MachineState *ms = MACHINE(qdev_get_machine()); | ||
| 58 | FslIMX6ULState *s = FSL_IMX6UL(dev); | ||
| 59 | int i; | ||
| 60 | - qemu_irq irq; | ||
| 61 | char name[NAME_SIZE]; | ||
| 62 | - unsigned int smp_cpus = ms->smp.cpus; | ||
| 63 | + SysBusDevice *sbd; | ||
| 64 | + DeviceState *d; | ||
| 65 | |||
| 66 | - if (smp_cpus > FSL_IMX6UL_NUM_CPUS) { | ||
| 67 | - error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", | ||
| 68 | - TYPE_FSL_IMX6UL, FSL_IMX6UL_NUM_CPUS, smp_cpus); | ||
| 69 | + if (ms->smp.cpus > 1) { | ||
| 70 | + error_setg(errp, "%s: Only a single CPU is supported (%d requested)", | ||
| 71 | + TYPE_FSL_IMX6UL, ms->smp.cpus); | ||
| 72 | return; | ||
| 73 | } | ||
| 74 | |||
| 75 | - for (i = 0; i < smp_cpus; i++) { | ||
| 76 | - Object *o = OBJECT(&s->cpu[i]); | ||
| 77 | - | ||
| 78 | - object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC, | ||
| 79 | - "psci-conduit", &error_abort); | ||
| 80 | - | ||
| 81 | - /* On uniprocessor, the CBAR is set to 0 */ | ||
| 82 | - if (smp_cpus > 1) { | ||
| 83 | - object_property_set_int(o, FSL_IMX6UL_A7MPCORE_ADDR, | ||
| 84 | - "reset-cbar", &error_abort); | ||
| 85 | - } | ||
| 86 | - | ||
| 87 | - if (i) { | ||
| 88 | - /* Secondary CPUs start in PSCI powered-down state */ | ||
| 89 | - object_property_set_bool(o, true, | ||
| 90 | - "start-powered-off", &error_abort); | ||
| 91 | - } | ||
| 92 | - | ||
| 93 | - object_property_set_bool(o, true, "realized", &error_abort); | ||
| 94 | - } | ||
| 95 | + object_property_set_int(OBJECT(&s->cpu), QEMU_PSCI_CONDUIT_SMC, | ||
| 96 | + "psci-conduit", &error_abort); | ||
| 97 | + object_property_set_bool(OBJECT(&s->cpu), true, | ||
| 98 | + "realized", &error_abort); | ||
| 99 | |||
| 100 | /* | ||
| 101 | * A7MPCORE | ||
| 102 | */ | ||
| 103 | - object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu", | ||
| 104 | - &error_abort); | ||
| 105 | + object_property_set_int(OBJECT(&s->a7mpcore), 1, "num-cpu", &error_abort); | ||
| 106 | object_property_set_int(OBJECT(&s->a7mpcore), | ||
| 107 | FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL, | ||
| 108 | "num-irq", &error_abort); | ||
| 109 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
| 110 | &error_abort); | ||
| 111 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR); | ||
| 112 | |||
| 113 | - for (i = 0; i < smp_cpus; i++) { | ||
| 114 | - SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); | ||
| 115 | - DeviceState *d = DEVICE(qemu_get_cpu(i)); | ||
| 116 | + sbd = SYS_BUS_DEVICE(&s->a7mpcore); | ||
| 117 | + d = DEVICE(&s->cpu); | ||
| 118 | |||
| 119 | - irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); | ||
| 120 | - sysbus_connect_irq(sbd, i, irq); | ||
| 121 | - sysbus_connect_irq(sbd, i + smp_cpus, qdev_get_gpio_in(d, ARM_CPU_FIQ)); | ||
| 122 | - sysbus_connect_irq(sbd, i + 2 * smp_cpus, | ||
| 123 | - qdev_get_gpio_in(d, ARM_CPU_VIRQ)); | ||
| 124 | - sysbus_connect_irq(sbd, i + 3 * smp_cpus, | ||
| 125 | - qdev_get_gpio_in(d, ARM_CPU_VFIQ)); | ||
| 126 | - } | ||
| 127 | + sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ)); | ||
| 128 | + sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ)); | ||
| 129 | + sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(d, ARM_CPU_VIRQ)); | ||
| 130 | + sysbus_connect_irq(sbd, 3, qdev_get_gpio_in(d, ARM_CPU_VFIQ)); | ||
| 131 | |||
| 132 | /* | ||
| 133 | * A7MPCORE DAP | ||
| 134 | diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c | ||
| 135 | index XXXXXXX..XXXXXXX 100644 | ||
| 136 | --- a/hw/arm/mcimx6ul-evk.c | ||
| 137 | +++ b/hw/arm/mcimx6ul-evk.c | ||
| 138 | @@ -XXX,XX +XXX,XX @@ static void mcimx6ul_evk_init(MachineState *machine) | ||
| 139 | } | ||
| 140 | |||
| 141 | if (!qtest_enabled()) { | ||
| 142 | - arm_load_kernel(&s->soc.cpu[0], &boot_info); | ||
| 143 | + arm_load_kernel(&s->soc.cpu, &boot_info); | ||
| 144 | } | ||
| 145 | } | ||
| 146 | 32 | ||
| 147 | -- | 33 | -- |
| 148 | 2.20.1 | 34 | 2.34.1 |
| 149 | |||
| 150 | diff view generated by jsdifflib |