[Qemu-devel] [PULL 0/5] target-arm queue
[PULL 0/2] target-arm queue
1
target-arm queue for rc2. This has 3 Arm related bug fixes,
1
This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
2
and a couple of non-arm patches which don't have an obviously
2
we were using uninitialized data for the guarded bit when
3
better route into the tree.
3
combining stage 1 and stage 2 attrs.
4
4
5
thanks
5
thanks
6
-- PMM
6
-- PMM
7
7
8
The following changes since commit b9e02bb3f98174209dbd5c96858e65a31723221b:
8
The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
9
9
10
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2019-07-19' into staging (2019-07-22 10:11:28 +0100)
10
Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
11
11
12
are available in the Git repository at:
12
are available in the Git repository at:
13
13
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190722
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
15
15
16
for you to fetch changes up to ddb45afbfbc639365d6c934e4e29f6de5e5e2a0e:
16
for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
17
17
18
contrib/elf2dmp: Build download.o with CURL_CFLAGS (2019-07-22 14:07:39 +0100)
18
target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
19
19
20
----------------------------------------------------------------
20
----------------------------------------------------------------
21
target-arm queue:
21
target-arm: Fix bug where we weren't initializing
22
* target/arm: Add missing break statement for Hypervisor Trap Exception
22
guarded bit state when combining S1/S2 attrs
23
(fixes handling of SMC insn taken to AArch32 Hyp mode via HCR.TSC)
24
* hw/arm/fsl-imx6ul.c: Remove dead SMP-related code
25
* target/arm: Limit ID register assertions to TCG
26
* configure: Clarify URL to source downloads
27
* contrib/elf2dmp: Build download.o with CURL_CFLAGS
28
23
29
----------------------------------------------------------------
24
----------------------------------------------------------------
30
Peter Maydell (4):
25
Richard Henderson (2):
31
hw/arm/fsl-imx6ul.c: Remove dead SMP-related code
26
target/arm: PTE bit GP only applies to stage1
32
target/arm: Limit ID register assertions to TCG
27
target/arm: Copy guarded bit in combine_cacheattrs
33
configure: Clarify URL to source downloads
34
contrib/elf2dmp: Build download.o with CURL_CFLAGS
35
28
36
Philippe Mathieu-Daudé (1):
29
target/arm/ptw.c | 11 ++++++-----
37
target/arm: Add missing break statement for Hypervisor Trap Exception
30
1 file changed, 6 insertions(+), 5 deletions(-)
38
39
configure | 2 +-
40
Makefile | 1 -
41
contrib/elf2dmp/Makefile.objs | 3 +++
42
include/hw/arm/fsl-imx6ul.h | 2 +-
43
hw/arm/fsl-imx6ul.c | 62 +++++++++++++------------------------------
44
hw/arm/mcimx6ul-evk.c | 2 +-
45
target/arm/cpu.c | 7 +++--
46
target/arm/helper.c | 1 +
47
8 files changed, 30 insertions(+), 50 deletions(-)
48
diff view generated by jsdifflib
[Qemu-devel] [PULL 4/5] configure: Clarify URL to source downloads
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
1
If configure detects that it's being run on a source tree which
1
From: Richard Henderson <richard.henderson@linaro.org>
2
is missing git modules, it prints an error messages suggesting
3
that the user downloads a correct source archive from the project
4
website. However https://www.qemu.org/download/ is a link to a
5
page with multiple tabs, with the default being the one telling
6
users how to get binaries from their distro. Clarify the URL
7
we print to include the #source anchor, so that the browser will
8
go directly to the source-tarball instructions.
9
2
10
Reported-by: Philippe Mathieu-Daudé <philmd@redhat.com>
3
Only perform the extract of GP during the stage1 walk.
11
Reviewed-by: Thomas Huth <thuth@redhat.com>
4
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Reported-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Stefan Weil <sw@weilnetz.de>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
16
Message-id: 20190718131659.20783-1-peter.maydell@linaro.org
17
Suggested-by: Stefan Weil <sw@weilnetz.de>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
10
---
20
configure | 2 +-
11
target/arm/ptw.c | 10 +++++-----
21
1 file changed, 1 insertion(+), 1 deletion(-)
12
1 file changed, 5 insertions(+), 5 deletions(-)
22
13
23
diff --git a/configure b/configure
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
24
index XXXXXXX..XXXXXXX 100755
15
index XXXXXXX..XXXXXXX 100644
25
--- a/configure
16
--- a/target/arm/ptw.c
26
+++ b/configure
17
+++ b/target/arm/ptw.c
27
@@ -XXX,XX +XXX,XX @@ else
18
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
28
echo "to acquire QEMU source archives. Non-GIT builds are only"
19
result->f.attrs.secure = false;
29
echo "supported with source archives linked from:"
20
}
30
echo
21
31
- echo " https://www.qemu.org/download/"
22
- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
32
+ echo " https://www.qemu.org/download/#source"
23
- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
33
echo
24
- result->f.guarded = extract64(attrs, 50, 1); /* GP */
34
echo "Developers working with GIT can use scripts/archive-source.sh"
25
- }
35
echo "if they need to create valid source archives."
26
-
27
if (regime_is_stage2(mmu_idx)) {
28
result->cacheattrs.is_s2_format = true;
29
result->cacheattrs.attrs = extract32(attrs, 2, 4);
30
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
31
assert(attrindx <= 7);
32
result->cacheattrs.is_s2_format = false;
33
result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
34
+
35
+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
36
+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
37
+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
38
+ }
39
}
40
41
/*
36
--
42
--
37
2.20.1
43
2.34.1
38
39
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/5] target/arm: Add missing break statement for Hypervisor Trap Exception
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Reported by GCC9 when building with -Wimplicit-fallthrough=2:
3
The guarded bit comes from the stage1 walk.
4
4
5
target/arm/helper.c: In function ‘arm_cpu_do_interrupt_aarch32_hyp’:
5
Fixes: Coverity CID 1507929
6
target/arm/helper.c:7958:14: error: this statement may fall through [-Werror=implicit-fallthrough=]
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
7958 | addr = 0x14;
8
| ~~~~~^~~~~~
9
target/arm/helper.c:7959:5: note: here
10
7959 | default:
11
| ^~~~~~~
12
cc1: all warnings being treated as errors
13
14
Fixes: b9bc21ff9f9
15
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
16
Reported-by: Stefan Weil <sw@weilnetz.de>
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Message-id: 20190719111451.12406-1-philmd@redhat.com
8
Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
10
---
21
target/arm/helper.c | 1 +
11
target/arm/ptw.c | 1 +
22
1 file changed, 1 insertion(+)
12
1 file changed, 1 insertion(+)
23
13
24
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
25
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/helper.c
16
--- a/target/arm/ptw.c
27
+++ b/target/arm/helper.c
17
+++ b/target/arm/ptw.c
28
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
18
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
29
break;
19
30
case EXCP_HYP_TRAP:
20
assert(!s1.is_s2_format);
31
addr = 0x14;
21
ret.is_s2_format = false;
32
+ break;
22
+ ret.guarded = s1.guarded;
33
default:
23
34
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
24
if (s1.attrs == 0xf0) {
35
}
25
tagged = true;
36
--
26
--
37
2.20.1
27
2.34.1
38
39
diff view generated by jsdifflib
[Qemu-devel] [PULL 2/5] hw/arm/fsl-imx6ul.c: Remove dead SMP-related code
Deleted patch
1
The i.MX6UL always has a single Cortex-A7 CPU (we set FSL_IMX6UL_NUM_CPUS
2
to 1 in line with this). This means that all the code in fsl-imx6ul.c to
3
handle multiple CPUs is dead code, and Coverity is now complaining that
4
it is unreachable (CID 1403008, 1403011).
5
1
6
Remove the unreachable code and the only-executes-once loops,
7
and replace the single-entry cpu[] array in the FSLIMX6ULState
8
with a simple cpu member.
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Message-id: 20190712115030.26895-1-peter.maydell@linaro.org
14
---
15
include/hw/arm/fsl-imx6ul.h | 2 +-
16
hw/arm/fsl-imx6ul.c | 62 +++++++++++--------------------------
17
hw/arm/mcimx6ul-evk.c | 2 +-
18
3 files changed, 20 insertions(+), 46 deletions(-)
19
20
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/arm/fsl-imx6ul.h
23
+++ b/include/hw/arm/fsl-imx6ul.h
24
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6ULState {
25
DeviceState parent_obj;
26
27
/*< public >*/
28
- ARMCPU cpu[FSL_IMX6UL_NUM_CPUS];
29
+ ARMCPU cpu;
30
A15MPPrivState a7mpcore;
31
IMXGPTState gpt[FSL_IMX6UL_NUM_GPTS];
32
IMXEPITState epit[FSL_IMX6UL_NUM_EPITS];
33
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/arm/fsl-imx6ul.c
36
+++ b/hw/arm/fsl-imx6ul.c
37
@@ -XXX,XX +XXX,XX @@
38
39
static void fsl_imx6ul_init(Object *obj)
40
{
41
- MachineState *ms = MACHINE(qdev_get_machine());
42
FslIMX6ULState *s = FSL_IMX6UL(obj);
43
char name[NAME_SIZE];
44
int i;
45
46
- for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6UL_NUM_CPUS); i++) {
47
- snprintf(name, NAME_SIZE, "cpu%d", i);
48
- object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
49
- "cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL);
50
- }
51
+ object_initialize_child(obj, "cpu0", &s->cpu, sizeof(s->cpu),
52
+ "cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL);
53
54
/*
55
* A7MPCORE
56
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
57
MachineState *ms = MACHINE(qdev_get_machine());
58
FslIMX6ULState *s = FSL_IMX6UL(dev);
59
int i;
60
- qemu_irq irq;
61
char name[NAME_SIZE];
62
- unsigned int smp_cpus = ms->smp.cpus;
63
+ SysBusDevice *sbd;
64
+ DeviceState *d;
65
66
- if (smp_cpus > FSL_IMX6UL_NUM_CPUS) {
67
- error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
68
- TYPE_FSL_IMX6UL, FSL_IMX6UL_NUM_CPUS, smp_cpus);
69
+ if (ms->smp.cpus > 1) {
70
+ error_setg(errp, "%s: Only a single CPU is supported (%d requested)",
71
+ TYPE_FSL_IMX6UL, ms->smp.cpus);
72
return;
73
}
74
75
- for (i = 0; i < smp_cpus; i++) {
76
- Object *o = OBJECT(&s->cpu[i]);
77
-
78
- object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC,
79
- "psci-conduit", &error_abort);
80
-
81
- /* On uniprocessor, the CBAR is set to 0 */
82
- if (smp_cpus > 1) {
83
- object_property_set_int(o, FSL_IMX6UL_A7MPCORE_ADDR,
84
- "reset-cbar", &error_abort);
85
- }
86
-
87
- if (i) {
88
- /* Secondary CPUs start in PSCI powered-down state */
89
- object_property_set_bool(o, true,
90
- "start-powered-off", &error_abort);
91
- }
92
-
93
- object_property_set_bool(o, true, "realized", &error_abort);
94
- }
95
+ object_property_set_int(OBJECT(&s->cpu), QEMU_PSCI_CONDUIT_SMC,
96
+ "psci-conduit", &error_abort);
97
+ object_property_set_bool(OBJECT(&s->cpu), true,
98
+ "realized", &error_abort);
99
100
/*
101
* A7MPCORE
102
*/
103
- object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu",
104
- &error_abort);
105
+ object_property_set_int(OBJECT(&s->a7mpcore), 1, "num-cpu", &error_abort);
106
object_property_set_int(OBJECT(&s->a7mpcore),
107
FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL,
108
"num-irq", &error_abort);
109
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
110
&error_abort);
111
sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
112
113
- for (i = 0; i < smp_cpus; i++) {
114
- SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
115
- DeviceState *d = DEVICE(qemu_get_cpu(i));
116
+ sbd = SYS_BUS_DEVICE(&s->a7mpcore);
117
+ d = DEVICE(&s->cpu);
118
119
- irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
120
- sysbus_connect_irq(sbd, i, irq);
121
- sysbus_connect_irq(sbd, i + smp_cpus, qdev_get_gpio_in(d, ARM_CPU_FIQ));
122
- sysbus_connect_irq(sbd, i + 2 * smp_cpus,
123
- qdev_get_gpio_in(d, ARM_CPU_VIRQ));
124
- sysbus_connect_irq(sbd, i + 3 * smp_cpus,
125
- qdev_get_gpio_in(d, ARM_CPU_VFIQ));
126
- }
127
+ sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ));
128
+ sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ));
129
+ sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(d, ARM_CPU_VIRQ));
130
+ sysbus_connect_irq(sbd, 3, qdev_get_gpio_in(d, ARM_CPU_VFIQ));
131
132
/*
133
* A7MPCORE DAP
134
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
135
index XXXXXXX..XXXXXXX 100644
136
--- a/hw/arm/mcimx6ul-evk.c
137
+++ b/hw/arm/mcimx6ul-evk.c
138
@@ -XXX,XX +XXX,XX @@ static void mcimx6ul_evk_init(MachineState *machine)
139
}
140
141
if (!qtest_enabled()) {
142
- arm_load_kernel(&s->soc.cpu[0], &boot_info);
143
+ arm_load_kernel(&s->soc.cpu, &boot_info);
144
}
145
}
146
147
--
148
2.20.1
149
150
diff view generated by jsdifflib
[Qemu-devel] [PULL 3/5] target/arm: Limit ID register assertions to TCG
Deleted patch
1
In arm_cpu_realizefn() we make several assertions about the values of
2
guest ID registers:
3
* if the CPU provides AArch32 v7VE or better it must advertise the
4
ARM_DIV feature
5
* if the CPU provides AArch32 A-profile v6 or better it must
6
advertise the Jazelle feature
7
1
8
These are essentially consistency checks that our ID register
9
specifications in cpu.c didn't accidentally miss out a feature,
10
because increasingly the TCG emulation gates features on the values
11
in ID registers rather than using old-style checks of ARM_FEATURE_FOO
12
bits.
13
14
Unfortunately, these asserts can cause problems if we're running KVM,
15
because in that case we don't control the values of the ID registers
16
-- we read them from the host kernel. In particular, if the host
17
kernel is older than 4.15 then it doesn't expose the ID registers via
18
the KVM_GET_ONE_REG ioctl, and we set up dummy values for some
19
registers and leave the rest at zero. (See the comment in
20
target/arm/kvm64.c kvm_arm_get_host_cpu_features().) This set of
21
dummy values is not sufficient to pass our assertions, and so on
22
those kernels running an AArch32 guest on AArch64 will assert.
23
24
We could provide a more sophisticated set of dummy ID registers in
25
this case, but that still leaves the possibility of a host CPU which
26
reports bogus ID register values that would cause us to assert. It's
27
more robust to only do these ID register checks if we're using TCG,
28
as that is the only case where this is truly a QEMU code bug.
29
30
Reported-by: Laszlo Ersek <lersek@redhat.com>
31
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
32
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
33
Tested-by: Laszlo Ersek <lersek@redhat.com>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Message-id: 20190718125928.20147-1-peter.maydell@linaro.org
36
Fixes: https://bugs.launchpad.net/qemu/+bug/1830864
37
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
38
---
39
target/arm/cpu.c | 7 +++++--
40
1 file changed, 5 insertions(+), 2 deletions(-)
41
42
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/cpu.c
45
+++ b/target/arm/cpu.c
46
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
47
* There exist AArch64 cpus without AArch32 support. When KVM
48
* queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
49
* Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
50
+ * As a general principle, we also do not make ID register
51
+ * consistency checks anywhere unless using TCG, because only
52
+ * for TCG would a consistency-check failure be a QEMU bug.
53
*/
54
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
55
no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
56
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
57
* Presence of EL2 itself is ARM_FEATURE_EL2, and of the
58
* Security Extensions is ARM_FEATURE_EL3.
59
*/
60
- assert(no_aa32 || cpu_isar_feature(arm_div, cpu));
61
+ assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu));
62
set_feature(env, ARM_FEATURE_LPAE);
63
set_feature(env, ARM_FEATURE_V7);
64
}
65
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
66
if (arm_feature(env, ARM_FEATURE_V6)) {
67
set_feature(env, ARM_FEATURE_V5);
68
if (!arm_feature(env, ARM_FEATURE_M)) {
69
- assert(no_aa32 || cpu_isar_feature(jazelle, cpu));
70
+ assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle, cpu));
71
set_feature(env, ARM_FEATURE_AUXCR);
72
}
73
}
74
--
75
2.20.1
76
77
diff view generated by jsdifflib
[Qemu-devel] [PULL 5/5] contrib/elf2dmp: Build download.o with CURL_CFLAGS
Deleted patch
1
contrib/elf2dmp has a source file which uses curl/curl.h;
2
although we link the final executable with CURL_LIBS, we
3
forgot to build this source file with CURL_CFLAGS, so if
4
the curl header is in a place that's not already on the
5
system include path then it will fail to build.
6
1
7
Add a line specifying the cflags needed for download.o;
8
while we are here, bring the specification of the libs
9
into line with this, since using a per-object variable
10
setting is preferred over adding them to the final
11
executable link line.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
15
Message-id: 20190719100955.17180-1-peter.maydell@linaro.org
16
---
17
Makefile | 1 -
18
contrib/elf2dmp/Makefile.objs | 3 +++
19
2 files changed, 3 insertions(+), 1 deletion(-)
20
21
diff --git a/Makefile b/Makefile
22
index XXXXXXX..XXXXXXX 100644
23
--- a/Makefile
24
+++ b/Makefile
25
@@ -XXX,XX +XXX,XX @@ ifneq ($(EXESUF),)
26
qemu-ga: qemu-ga$(EXESUF) $(QGA_VSS_PROVIDER) $(QEMU_GA_MSI)
27
endif
28
29
-elf2dmp$(EXESUF): LIBS += $(CURL_LIBS)
30
elf2dmp$(EXESUF): $(elf2dmp-obj-y)
31
    $(call LINK, $^)
32
33
diff --git a/contrib/elf2dmp/Makefile.objs b/contrib/elf2dmp/Makefile.objs
34
index XXXXXXX..XXXXXXX 100644
35
--- a/contrib/elf2dmp/Makefile.objs
36
+++ b/contrib/elf2dmp/Makefile.objs
37
@@ -1 +1,4 @@
38
elf2dmp-obj-y = main.o addrspace.o download.o pdb.o qemu_elf.o
39
+
40
+download.o-cflags := $(CURL_CFLAGS)
41
+download.o-libs := $(CURL_LIBS)
42
--
43
2.20.1
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45
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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