1 | target-arm queue for rc1 -- these are all bug fixes. | 1 | target-arm queue: just bugfixes, mostly mine. |
---|---|---|---|
2 | 2 | ||
3 | thanks | 3 | thanks |
4 | -- PMM | 4 | -- PMM |
5 | 5 | ||
6 | The following changes since commit b9404bf592e7ba74180e1a54ed7a266ec6ee67f2: | 6 | The following changes since commit 885fc169f09f5915ce037263d20a59eb226d473d: |
7 | 7 | ||
8 | Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20190715' into staging (2019-07-15 12:22:07 +0100) | 8 | Merge tag 'pull-riscv-to-apply-20230723-3' of https://github.com/alistair23/qemu into staging (2023-07-24 11:34:35 +0100) |
9 | 9 | ||
10 | are available in the Git repository at: | 10 | are available in the Git repository at: |
11 | 11 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190715 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230725 |
13 | 13 | ||
14 | for you to fetch changes up to 51c9122e92b776a3f16af0b9282f1dc5012e2a19: | 14 | for you to fetch changes up to 78cc90346ec680a7f1bb9f138bf7c9654cf526d5: |
15 | 15 | ||
16 | target/arm: NS BusFault on vector table fetch escalates to NS HardFault (2019-07-15 14:17:04 +0100) | 16 | tests/decode: Suppress "error: " string for expected-failure tests (2023-07-25 10:56:52 +0100) |
17 | 17 | ||
18 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
19 | target-arm queue: | 19 | target-arm queue: |
20 | * report ARMv8-A FP support for AArch32 -cpu max | 20 | * tests/decode: Suppress "error: " string for expected-failure tests |
21 | * hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory | 21 | * ui/curses: For curses display, recognize a few more control keys |
22 | * hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[] | 22 | * target/arm: Special case M-profile in debug_helper.c code |
23 | * hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO | 23 | * scripts/git-submodule.sh: Don't rely on non-POSIX 'read' behaviour |
24 | * hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO | 24 | * hw/arm/smmu: Handle big-endian hosts correctly |
25 | * hw/arm/virt: Fix non-secure flash mode | ||
26 | * pl031: Correctly migrate state when using -rtc clock=host | ||
27 | * fix regression that meant arm926 and arm1026 lost VFP | ||
28 | double-precision support | ||
29 | * v8M: NS BusFault on vector table fetch escalates to NS HardFault | ||
30 | 25 | ||
31 | ---------------------------------------------------------------- | 26 | ---------------------------------------------------------------- |
32 | Alex Bennée (1): | 27 | Peter Maydell (4): |
33 | target/arm: report ARMv8-A FP support for AArch32 -cpu max | 28 | hw/arm/smmu: Handle big-endian hosts correctly |
29 | scripts/git-submodule.sh: Don't rely on non-POSIX 'read' behaviour | ||
30 | target/arm: Special case M-profile in debug_helper.c code | ||
31 | tests/decode: Suppress "error: " string for expected-failure tests | ||
34 | 32 | ||
35 | David Engraf (1): | 33 | Sean Estabrooks (1): |
36 | hw/arm/virt: Fix non-secure flash mode | 34 | For curses display, recognize a few more control keys |
37 | 35 | ||
38 | Peter Maydell (3): | 36 | ui/curses_keys.h | 6 ++++++ |
39 | pl031: Correctly migrate state when using -rtc clock=host | 37 | hw/arm/smmu-common.c | 3 +-- |
40 | target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026 | 38 | hw/arm/smmuv3.c | 39 +++++++++++++++++++++++++++++++-------- |
41 | target/arm: NS BusFault on vector table fetch escalates to NS HardFault | 39 | target/arm/debug_helper.c | 18 ++++++++++++------ |
42 | 40 | scripts/decodetree.py | 6 +++++- | |
43 | Philippe Mathieu-Daudé (5): | 41 | scripts/git-submodule.sh | 2 +- |
44 | hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs | 42 | 6 files changed, 56 insertions(+), 18 deletions(-) |
45 | hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory | ||
46 | hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[] | ||
47 | hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO | ||
48 | hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO | ||
49 | |||
50 | include/hw/timer/pl031.h | 2 ++ | ||
51 | hw/arm/virt.c | 2 +- | ||
52 | hw/core/machine.c | 1 + | ||
53 | hw/display/xlnx_dp.c | 15 +++++--- | ||
54 | hw/ssi/mss-spi.c | 8 ++++- | ||
55 | hw/ssi/xilinx_spips.c | 43 +++++++++++++++------- | ||
56 | hw/timer/pl031.c | 92 +++++++++++++++++++++++++++++++++++++++++++++--- | ||
57 | target/arm/cpu.c | 16 +++++++++ | ||
58 | target/arm/m_helper.c | 21 ++++++++--- | ||
59 | 9 files changed, 174 insertions(+), 26 deletions(-) | ||
60 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Alex Bennée <alex.bennee@linaro.org> | ||
2 | 1 | ||
3 | When we converted to using feature bits in 602f6e42cfbf we missed out | ||
4 | the fact (dp && arm_dc_feature(s, ARM_FEATURE_V8)) was supported for | ||
5 | -cpu max configurations. This caused a regression in the GCC test | ||
6 | suite. Fix this by setting the appropriate bits in mvfr1.FPHP to | ||
7 | report ARMv8-A with FP support (but not ARMv8.2-FP16). | ||
8 | |||
9 | Fixes: https://bugs.launchpad.net/qemu/+bug/1836078 | ||
10 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20190711103737.10017-1-alex.bennee@linaro.org | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | target/arm/cpu.c | 4 ++++ | ||
16 | 1 file changed, 4 insertions(+) | ||
17 | |||
18 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/arm/cpu.c | ||
21 | +++ b/target/arm/cpu.c | ||
22 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | ||
23 | t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
24 | cpu->isar.id_isar6 = t; | ||
25 | |||
26 | + t = cpu->isar.mvfr1; | ||
27 | + t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */ | ||
28 | + cpu->isar.mvfr1 = t; | ||
29 | + | ||
30 | t = cpu->isar.mvfr2; | ||
31 | t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
32 | t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
33 | -- | ||
34 | 2.20.1 | ||
35 | |||
36 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
2 | 1 | ||
3 | In the next commit we will implement the write_with_attrs() | ||
4 | handler. To avoid using different APIs, convert the read() | ||
5 | handler first. | ||
6 | |||
7 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
8 | Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
9 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | hw/ssi/xilinx_spips.c | 23 +++++++++++------------ | ||
13 | 1 file changed, 11 insertions(+), 12 deletions(-) | ||
14 | |||
15 | diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/hw/ssi/xilinx_spips.c | ||
18 | +++ b/hw/ssi/xilinx_spips.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void lqspi_load_cache(void *opaque, hwaddr addr) | ||
20 | } | ||
21 | } | ||
22 | |||
23 | -static uint64_t | ||
24 | -lqspi_read(void *opaque, hwaddr addr, unsigned int size) | ||
25 | +static MemTxResult lqspi_read(void *opaque, hwaddr addr, uint64_t *value, | ||
26 | + unsigned size, MemTxAttrs attrs) | ||
27 | { | ||
28 | - XilinxQSPIPS *q = opaque; | ||
29 | - uint32_t ret; | ||
30 | + XilinxQSPIPS *q = XILINX_QSPIPS(opaque); | ||
31 | |||
32 | if (addr >= q->lqspi_cached_addr && | ||
33 | addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { | ||
34 | uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr]; | ||
35 | - ret = cpu_to_le32(*(uint32_t *)retp); | ||
36 | - DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, | ||
37 | - (unsigned)ret); | ||
38 | - return ret; | ||
39 | - } else { | ||
40 | - lqspi_load_cache(opaque, addr); | ||
41 | - return lqspi_read(opaque, addr, size); | ||
42 | + *value = cpu_to_le32(*(uint32_t *)retp); | ||
43 | + DB_PRINT_L(1, "addr: %08" HWADDR_PRIx ", data: %08" PRIx64 "\n", | ||
44 | + addr, *value); | ||
45 | + return MEMTX_OK; | ||
46 | } | ||
47 | + | ||
48 | + lqspi_load_cache(opaque, addr); | ||
49 | + return lqspi_read(opaque, addr, value, size, attrs); | ||
50 | } | ||
51 | |||
52 | static const MemoryRegionOps lqspi_ops = { | ||
53 | - .read = lqspi_read, | ||
54 | + .read_with_attrs = lqspi_read, | ||
55 | .endianness = DEVICE_NATIVE_ENDIAN, | ||
56 | .valid = { | ||
57 | .min_access_size = 1, | ||
58 | -- | ||
59 | 2.20.1 | ||
60 | |||
61 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
2 | 1 | ||
3 | Lei Sun found while auditing the code that a CPU write would | ||
4 | trigger a NULL pointer dereference. | ||
5 | |||
6 | >From UG1085 datasheet [*] AXI writes in this region are ignored | ||
7 | and generates an AXI Slave Error (SLVERR). | ||
8 | |||
9 | Fix by implementing the write_with_attrs() handler. | ||
10 | Return MEMTX_ERROR when the region is accessed (this error maps | ||
11 | to an AXI slave error). | ||
12 | |||
13 | [*] https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf | ||
14 | |||
15 | Reported-by: Lei Sun <slei.casper@gmail.com> | ||
16 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
17 | Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
18 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
20 | --- | ||
21 | hw/ssi/xilinx_spips.c | 16 ++++++++++++++++ | ||
22 | 1 file changed, 16 insertions(+) | ||
23 | |||
24 | diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/hw/ssi/xilinx_spips.c | ||
27 | +++ b/hw/ssi/xilinx_spips.c | ||
28 | @@ -XXX,XX +XXX,XX @@ static MemTxResult lqspi_read(void *opaque, hwaddr addr, uint64_t *value, | ||
29 | return lqspi_read(opaque, addr, value, size, attrs); | ||
30 | } | ||
31 | |||
32 | +static MemTxResult lqspi_write(void *opaque, hwaddr offset, uint64_t value, | ||
33 | + unsigned size, MemTxAttrs attrs) | ||
34 | +{ | ||
35 | + /* | ||
36 | + * From UG1085, Chapter 24 (Quad-SPI controllers): | ||
37 | + * - Writes are ignored | ||
38 | + * - AXI writes generate an external AXI slave error (SLVERR) | ||
39 | + */ | ||
40 | + qemu_log_mask(LOG_GUEST_ERROR, "%s Unexpected %u-bit access to 0x%" PRIx64 | ||
41 | + " (value: 0x%" PRIx64 "\n", | ||
42 | + __func__, size << 3, offset, value); | ||
43 | + | ||
44 | + return MEMTX_ERROR; | ||
45 | +} | ||
46 | + | ||
47 | static const MemoryRegionOps lqspi_ops = { | ||
48 | .read_with_attrs = lqspi_read, | ||
49 | + .write_with_attrs = lqspi_write, | ||
50 | .endianness = DEVICE_NATIVE_ENDIAN, | ||
51 | .valid = { | ||
52 | .min_access_size = 1, | ||
53 | -- | ||
54 | 2.20.1 | ||
55 | |||
56 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
2 | 1 | ||
3 | Both lqspi_read() and lqspi_load_cache() expect a 32-bit | ||
4 | aligned address. | ||
5 | |||
6 | >From UG1085 datasheet [*] chapter on 'Quad-SPI Controller': | ||
7 | |||
8 | Transfer Size Limitations | ||
9 | |||
10 | Because of the 32-bit wide TX, RX, and generic FIFO, all | ||
11 | APB/AXI transfers must be an integer multiple of 4-bytes. | ||
12 | Shorter transfers are not possible. | ||
13 | |||
14 | Set MemoryRegionOps.impl values to force 32-bit accesses, | ||
15 | this way we are sure we do not access the lqspi_buf[] array | ||
16 | out of bound. | ||
17 | |||
18 | [*] https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf | ||
19 | |||
20 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
21 | Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
22 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
24 | --- | ||
25 | hw/ssi/xilinx_spips.c | 4 ++++ | ||
26 | 1 file changed, 4 insertions(+) | ||
27 | |||
28 | diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/hw/ssi/xilinx_spips.c | ||
31 | +++ b/hw/ssi/xilinx_spips.c | ||
32 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps lqspi_ops = { | ||
33 | .read_with_attrs = lqspi_read, | ||
34 | .write_with_attrs = lqspi_write, | ||
35 | .endianness = DEVICE_NATIVE_ENDIAN, | ||
36 | + .impl = { | ||
37 | + .min_access_size = 4, | ||
38 | + .max_access_size = 4, | ||
39 | + }, | ||
40 | .valid = { | ||
41 | .min_access_size = 1, | ||
42 | .max_access_size = 4 | ||
43 | -- | ||
44 | 2.20.1 | ||
45 | |||
46 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
2 | 1 | ||
3 | Reading the RX_DATA register when the RX_FIFO is empty triggers | ||
4 | an abort. This can be easily reproduced: | ||
5 | |||
6 | $ qemu-system-arm -M emcraft-sf2 -monitor stdio -S | ||
7 | QEMU 4.0.50 monitor - type 'help' for more information | ||
8 | (qemu) x 0x40001010 | ||
9 | Aborted (core dumped) | ||
10 | |||
11 | (gdb) bt | ||
12 | #1 0x00007f035874f895 in abort () at /lib64/libc.so.6 | ||
13 | #2 0x00005628686591ff in fifo8_pop (fifo=0x56286a9a4c68) at util/fifo8.c:66 | ||
14 | #3 0x00005628683e0b8e in fifo32_pop (fifo=0x56286a9a4c68) at include/qemu/fifo32.h:137 | ||
15 | #4 0x00005628683e0efb in spi_read (opaque=0x56286a9a4850, addr=4, size=4) at hw/ssi/mss-spi.c:168 | ||
16 | #5 0x0000562867f96801 in memory_region_read_accessor (mr=0x56286a9a4b60, addr=16, value=0x7ffeecb0c5c8, size=4, shift=0, mask=4294967295, attrs=...) at memory.c:439 | ||
17 | #6 0x0000562867f96cdb in access_with_adjusted_size (addr=16, value=0x7ffeecb0c5c8, size=4, access_size_min=1, access_size_max=4, access_fn=0x562867f967c3 <memory_region_read_accessor>, mr=0x56286a9a4b60, attrs=...) at memory.c:569 | ||
18 | #7 0x0000562867f99940 in memory_region_dispatch_read1 (mr=0x56286a9a4b60, addr=16, pval=0x7ffeecb0c5c8, size=4, attrs=...) at memory.c:1420 | ||
19 | #8 0x0000562867f99a08 in memory_region_dispatch_read (mr=0x56286a9a4b60, addr=16, pval=0x7ffeecb0c5c8, size=4, attrs=...) at memory.c:1447 | ||
20 | #9 0x0000562867f38721 in flatview_read_continue (fv=0x56286aec6360, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4, addr1=16, l=4, mr=0x56286a9a4b60) at exec.c:3385 | ||
21 | #10 0x0000562867f38874 in flatview_read (fv=0x56286aec6360, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4) at exec.c:3423 | ||
22 | #11 0x0000562867f388ea in address_space_read_full (as=0x56286aa3e890, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4) at exec.c:3436 | ||
23 | #12 0x0000562867f389c5 in address_space_rw (as=0x56286aa3e890, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4, is_write=false) at exec.c:3466 | ||
24 | #13 0x0000562867f3bdd7 in cpu_memory_rw_debug (cpu=0x56286aa19d00, addr=1073745936, buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4, is_write=0) at exec.c:3976 | ||
25 | #14 0x000056286811ed51 in memory_dump (mon=0x56286a8c32d0, count=1, format=120, wsize=4, addr=1073745936, is_physical=0) at monitor/misc.c:730 | ||
26 | #15 0x000056286811eff1 in hmp_memory_dump (mon=0x56286a8c32d0, qdict=0x56286b15c400) at monitor/misc.c:785 | ||
27 | #16 0x00005628684740ee in handle_hmp_command (mon=0x56286a8c32d0, cmdline=0x56286a8caeb2 "0x40001010") at monitor/hmp.c:1082 | ||
28 | |||
29 | From the datasheet "Actel SmartFusion Microcontroller Subsystem | ||
30 | User's Guide" Rev.1, Table 13-3 "SPI Register Summary", this | ||
31 | register has a reset value of 0. | ||
32 | |||
33 | Check the FIFO is not empty before accessing it, else log an | ||
34 | error message. | ||
35 | |||
36 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
37 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
38 | Message-id: 20190709113715.7761-3-philmd@redhat.com | ||
39 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
40 | --- | ||
41 | hw/ssi/mss-spi.c | 8 +++++++- | ||
42 | 1 file changed, 7 insertions(+), 1 deletion(-) | ||
43 | |||
44 | diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/hw/ssi/mss-spi.c | ||
47 | +++ b/hw/ssi/mss-spi.c | ||
48 | @@ -XXX,XX +XXX,XX @@ spi_read(void *opaque, hwaddr addr, unsigned int size) | ||
49 | case R_SPI_RX: | ||
50 | s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL; | ||
51 | s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF; | ||
52 | - ret = fifo32_pop(&s->rx_fifo); | ||
53 | + if (fifo32_is_empty(&s->rx_fifo)) { | ||
54 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
55 | + "%s: Reading empty RX_FIFO\n", | ||
56 | + __func__); | ||
57 | + } else { | ||
58 | + ret = fifo32_pop(&s->rx_fifo); | ||
59 | + } | ||
60 | if (fifo32_is_empty(&s->rx_fifo)) { | ||
61 | s->regs[R_SPI_STATUS] |= S_RXFIFOEMP; | ||
62 | } | ||
63 | -- | ||
64 | 2.20.1 | ||
65 | |||
66 | diff view generated by jsdifflib |
1 | The PL031 RTC tracks the difference between the guest RTC | 1 | The implementation of the SMMUv3 has multiple places where it reads a |
---|---|---|---|
2 | and the host RTC using a tick_offset field. For migration, | 2 | data structure from the guest and directly operates on it without |
3 | however, we currently always migrate the offset between | 3 | doing a guest-to-host endianness conversion. Since all SMMU data |
4 | the guest and the vm_clock, even if the RTC clock is not | 4 | structures are little-endian, this means that the SMMU doesn't work |
5 | the same as the vm_clock; this was an attempt to retain | 5 | on a big-endian host. In particular, this causes the Avocado test |
6 | migration backwards compatibility. | 6 | machine_aarch64_virt.py:Aarch64VirtMachine.test_alpine_virt_tcg_gic_max |
7 | to fail on an s390x host. | ||
7 | 8 | ||
8 | Unfortunately this results in the RTC behaving oddly across | 9 | Add appropriate byte-swapping on reads and writes of guest in-memory |
9 | a VM state save and restore -- since the VM clock stands still | 10 | data structures so that the device works correctly on big-endian |
10 | across save-then-restore, regardless of how much real world | 11 | hosts. |
11 | time has elapsed, the guest RTC ends up out of sync with the | ||
12 | host RTC in the restored VM. | ||
13 | 12 | ||
14 | Fix this by migrating the raw tick_offset. To retain migration | 13 | As part of this we constrain queue_read() to operate only on Cmd |
15 | compatibility as far as possible, we have a new property | 14 | structs and queue_write() on Evt structs, because in practice these |
16 | migrate-tick-offset; by default this is 'true' and we will | 15 | are the only data structures the two functions are used with, and we |
17 | migrate the true tick offset in a new subsection; if the | 16 | need to know what the data structure is to be able to byte-swap its |
18 | incoming data has no subsection we fall back to the old | 17 | parts correctly. |
19 | vm_clock-based offset information, so old->new migration | ||
20 | compatibility is preserved. For complete new->old migration | ||
21 | compatibility, the property is set to 'false' for 4.0 and | ||
22 | earlier machine types (this will only affect 'virt-4.0' | ||
23 | and below, as none of the other pl031-using machines are | ||
24 | versioned). | ||
25 | 18 | ||
26 | Reported-by: Russell King <rmk@armlinux.org.uk> | ||
27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
28 | Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> | 20 | Tested-by: Thomas Huth <thuth@redhat.com> |
29 | Message-id: 20190709143912.28905-1-peter.maydell@linaro.org | 21 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
22 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
23 | Message-id: 20230717132641.764660-1-peter.maydell@linaro.org | ||
24 | Cc: qemu-stable@nongnu.org | ||
30 | --- | 25 | --- |
31 | include/hw/timer/pl031.h | 2 + | 26 | hw/arm/smmu-common.c | 3 +-- |
32 | hw/core/machine.c | 1 + | 27 | hw/arm/smmuv3.c | 39 +++++++++++++++++++++++++++++++-------- |
33 | hw/timer/pl031.c | 92 ++++++++++++++++++++++++++++++++++++++-- | 28 | 2 files changed, 32 insertions(+), 10 deletions(-) |
34 | 3 files changed, 91 insertions(+), 4 deletions(-) | ||
35 | 29 | ||
36 | diff --git a/include/hw/timer/pl031.h b/include/hw/timer/pl031.h | 30 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c |
37 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/include/hw/timer/pl031.h | 32 | --- a/hw/arm/smmu-common.c |
39 | +++ b/include/hw/timer/pl031.h | 33 | +++ b/hw/arm/smmu-common.c |
40 | @@ -XXX,XX +XXX,XX @@ typedef struct PL031State { | 34 | @@ -XXX,XX +XXX,XX @@ static int get_pte(dma_addr_t baseaddr, uint32_t index, uint64_t *pte, |
41 | */ | 35 | dma_addr_t addr = baseaddr + index * sizeof(*pte); |
42 | uint32_t tick_offset_vmstate; | 36 | |
43 | uint32_t tick_offset; | 37 | /* TODO: guarantee 64-bit single-copy atomicity */ |
44 | + bool tick_offset_migrated; | 38 | - ret = dma_memory_read(&address_space_memory, addr, pte, sizeof(*pte), |
45 | + bool migrate_tick_offset; | 39 | - MEMTXATTRS_UNSPECIFIED); |
46 | 40 | + ret = ldq_le_dma(&address_space_memory, addr, pte, MEMTXATTRS_UNSPECIFIED); | |
47 | uint32_t mr; | 41 | |
48 | uint32_t lr; | 42 | if (ret != MEMTX_OK) { |
49 | diff --git a/hw/core/machine.c b/hw/core/machine.c | 43 | info->type = SMMU_PTW_ERR_WALK_EABT; |
44 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | 45 | index XXXXXXX..XXXXXXX 100644 |
51 | --- a/hw/core/machine.c | 46 | --- a/hw/arm/smmuv3.c |
52 | +++ b/hw/core/machine.c | 47 | +++ b/hw/arm/smmuv3.c |
53 | @@ -XXX,XX +XXX,XX @@ GlobalProperty hw_compat_4_0[] = { | 48 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn) |
54 | { "virtio-gpu-pci", "edid", "false" }, | 49 | trace_smmuv3_write_gerrorn(toggled & pending, s->gerrorn); |
55 | { "virtio-device", "use-started", "false" }, | 50 | } |
56 | { "virtio-balloon-device", "qemu-4-0-config-size", "true" }, | 51 | |
57 | + { "pl031", "migrate-tick-offset", "false" }, | 52 | -static inline MemTxResult queue_read(SMMUQueue *q, void *data) |
58 | }; | 53 | +static inline MemTxResult queue_read(SMMUQueue *q, Cmd *cmd) |
59 | const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0); | ||
60 | |||
61 | diff --git a/hw/timer/pl031.c b/hw/timer/pl031.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/hw/timer/pl031.c | ||
64 | +++ b/hw/timer/pl031.c | ||
65 | @@ -XXX,XX +XXX,XX @@ static int pl031_pre_save(void *opaque) | ||
66 | { | 54 | { |
67 | PL031State *s = opaque; | 55 | dma_addr_t addr = Q_CONS_ENTRY(q); |
68 | 56 | + MemTxResult ret; | |
69 | - /* tick_offset is base_time - rtc_clock base time. Instead, we want to | 57 | + int i; |
70 | - * store the base time relative to the QEMU_CLOCK_VIRTUAL for backwards-compatibility. */ | 58 | |
71 | + /* | 59 | - return dma_memory_read(&address_space_memory, addr, data, q->entry_size, |
72 | + * The PL031 device model code uses the tick_offset field, which is | 60 | - MEMTXATTRS_UNSPECIFIED); |
73 | + * the offset between what the guest RTC should read and what the | 61 | + ret = dma_memory_read(&address_space_memory, addr, cmd, sizeof(Cmd), |
74 | + * QEMU rtc_clock reads: | 62 | + MEMTXATTRS_UNSPECIFIED); |
75 | + * guest_rtc = rtc_clock + tick_offset | 63 | + if (ret != MEMTX_OK) { |
76 | + * and so | 64 | + return ret; |
77 | + * tick_offset = guest_rtc - rtc_clock | 65 | + } |
78 | + * | 66 | + for (i = 0; i < ARRAY_SIZE(cmd->word); i++) { |
79 | + * We want to migrate this offset, which sounds straightforward. | 67 | + le32_to_cpus(&cmd->word[i]); |
80 | + * Unfortunately older versions of QEMU migrated a conversion of this | 68 | + } |
81 | + * offset into an offset from the vm_clock. (This was in turn an | 69 | + return ret; |
82 | + * attempt to be compatible with even older QEMU versions, but it | 70 | } |
83 | + * has incorrect behaviour if the rtc_clock is not the same as the | 71 | |
84 | + * vm_clock.) So we put the actual tick_offset into a migration | 72 | -static MemTxResult queue_write(SMMUQueue *q, void *data) |
85 | + * subsection, and the backwards-compatible time-relative-to-vm_clock | 73 | +static MemTxResult queue_write(SMMUQueue *q, Evt *evt_in) |
86 | + * in the main migration state. | 74 | { |
87 | + * | 75 | dma_addr_t addr = Q_PROD_ENTRY(q); |
88 | + * Calculate base time relative to QEMU_CLOCK_VIRTUAL: | 76 | MemTxResult ret; |
89 | + */ | 77 | + Evt evt = *evt_in; |
90 | int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | 78 | + int i; |
91 | s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND; | 79 | |
92 | 80 | - ret = dma_memory_write(&address_space_memory, addr, data, q->entry_size, | |
81 | + for (i = 0; i < ARRAY_SIZE(evt.word); i++) { | ||
82 | + cpu_to_le32s(&evt.word[i]); | ||
83 | + } | ||
84 | + ret = dma_memory_write(&address_space_memory, addr, &evt, sizeof(Evt), | ||
85 | MEMTXATTRS_UNSPECIFIED); | ||
86 | if (ret != MEMTX_OK) { | ||
87 | return ret; | ||
88 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s) | ||
89 | static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, | ||
90 | SMMUEventInfo *event) | ||
91 | { | ||
92 | - int ret; | ||
93 | + int ret, i; | ||
94 | |||
95 | trace_smmuv3_get_ste(addr); | ||
96 | /* TODO: guarantee 64-bit single-copy atomicity */ | ||
97 | @@ -XXX,XX +XXX,XX @@ static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, | ||
98 | event->u.f_ste_fetch.addr = addr; | ||
99 | return -EINVAL; | ||
100 | } | ||
101 | + for (i = 0; i < ARRAY_SIZE(buf->word); i++) { | ||
102 | + le32_to_cpus(&buf->word[i]); | ||
103 | + } | ||
104 | return 0; | ||
105 | |||
106 | } | ||
107 | @@ -XXX,XX +XXX,XX @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid, | ||
108 | CD *buf, SMMUEventInfo *event) | ||
109 | { | ||
110 | dma_addr_t addr = STE_CTXPTR(ste); | ||
111 | - int ret; | ||
112 | + int ret, i; | ||
113 | |||
114 | trace_smmuv3_get_cd(addr); | ||
115 | /* TODO: guarantee 64-bit single-copy atomicity */ | ||
116 | @@ -XXX,XX +XXX,XX @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid, | ||
117 | event->u.f_ste_fetch.addr = addr; | ||
118 | return -EINVAL; | ||
119 | } | ||
120 | + for (i = 0; i < ARRAY_SIZE(buf->word); i++) { | ||
121 | + le32_to_cpus(&buf->word[i]); | ||
122 | + } | ||
93 | return 0; | 123 | return 0; |
94 | } | 124 | } |
95 | 125 | ||
96 | +static int pl031_pre_load(void *opaque) | 126 | @@ -XXX,XX +XXX,XX @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, |
97 | +{ | 127 | return -EINVAL; |
98 | + PL031State *s = opaque; | ||
99 | + | ||
100 | + s->tick_offset_migrated = false; | ||
101 | + return 0; | ||
102 | +} | ||
103 | + | ||
104 | static int pl031_post_load(void *opaque, int version_id) | ||
105 | { | ||
106 | PL031State *s = opaque; | ||
107 | |||
108 | - int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
109 | - s->tick_offset = s->tick_offset_vmstate - delta / NANOSECONDS_PER_SECOND; | ||
110 | + /* | ||
111 | + * If we got the tick_offset subsection, then we can just use | ||
112 | + * the value in that. Otherwise the source is an older QEMU and | ||
113 | + * has given us the offset from the vm_clock; convert it back to | ||
114 | + * an offset from the rtc_clock. This will cause time to incorrectly | ||
115 | + * go backwards compared to the host RTC, but this is unavoidable. | ||
116 | + */ | ||
117 | + | ||
118 | + if (!s->tick_offset_migrated) { | ||
119 | + int64_t delta = qemu_clock_get_ns(rtc_clock) - | ||
120 | + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
121 | + s->tick_offset = s->tick_offset_vmstate - | ||
122 | + delta / NANOSECONDS_PER_SECOND; | ||
123 | + } | ||
124 | pl031_set_alarm(s); | ||
125 | return 0; | ||
126 | } | ||
127 | |||
128 | +static int pl031_tick_offset_post_load(void *opaque, int version_id) | ||
129 | +{ | ||
130 | + PL031State *s = opaque; | ||
131 | + | ||
132 | + s->tick_offset_migrated = true; | ||
133 | + return 0; | ||
134 | +} | ||
135 | + | ||
136 | +static bool pl031_tick_offset_needed(void *opaque) | ||
137 | +{ | ||
138 | + PL031State *s = opaque; | ||
139 | + | ||
140 | + return s->migrate_tick_offset; | ||
141 | +} | ||
142 | + | ||
143 | +static const VMStateDescription vmstate_pl031_tick_offset = { | ||
144 | + .name = "pl031/tick-offset", | ||
145 | + .version_id = 1, | ||
146 | + .minimum_version_id = 1, | ||
147 | + .needed = pl031_tick_offset_needed, | ||
148 | + .post_load = pl031_tick_offset_post_load, | ||
149 | + .fields = (VMStateField[]) { | ||
150 | + VMSTATE_UINT32(tick_offset, PL031State), | ||
151 | + VMSTATE_END_OF_LIST() | ||
152 | + } | ||
153 | +}; | ||
154 | + | ||
155 | static const VMStateDescription vmstate_pl031 = { | ||
156 | .name = "pl031", | ||
157 | .version_id = 1, | ||
158 | .minimum_version_id = 1, | ||
159 | .pre_save = pl031_pre_save, | ||
160 | + .pre_load = pl031_pre_load, | ||
161 | .post_load = pl031_post_load, | ||
162 | .fields = (VMStateField[]) { | ||
163 | VMSTATE_UINT32(tick_offset_vmstate, PL031State), | ||
164 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl031 = { | ||
165 | VMSTATE_UINT32(im, PL031State), | ||
166 | VMSTATE_UINT32(is, PL031State), | ||
167 | VMSTATE_END_OF_LIST() | ||
168 | + }, | ||
169 | + .subsections = (const VMStateDescription*[]) { | ||
170 | + &vmstate_pl031_tick_offset, | ||
171 | + NULL | ||
172 | } | 128 | } |
173 | }; | 129 | if (s->features & SMMU_FEATURE_2LVL_STE) { |
174 | 130 | - int l1_ste_offset, l2_ste_offset, max_l2_ste, span; | |
175 | +static Property pl031_properties[] = { | 131 | + int l1_ste_offset, l2_ste_offset, max_l2_ste, span, i; |
176 | + /* | 132 | dma_addr_t l1ptr, l2ptr; |
177 | + * True to correctly migrate the tick offset of the RTC. False to | 133 | STEDesc l1std; |
178 | + * obtain backward migration compatibility with older QEMU versions, | 134 | |
179 | + * at the expense of the guest RTC going backwards compared with the | 135 | @@ -XXX,XX +XXX,XX @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, |
180 | + * host RTC when the VM is saved/restored if using -rtc host. | 136 | event->u.f_ste_fetch.addr = l1ptr; |
181 | + * (Even if set to 'true' older QEMU can migrate forward to newer QEMU; | 137 | return -EINVAL; |
182 | + * 'false' also permits newer QEMU to migrate to older QEMU.) | 138 | } |
183 | + */ | 139 | + for (i = 0; i < ARRAY_SIZE(l1std.word); i++) { |
184 | + DEFINE_PROP_BOOL("migrate-tick-offset", | 140 | + le32_to_cpus(&l1std.word[i]); |
185 | + PL031State, migrate_tick_offset, true), | 141 | + } |
186 | + DEFINE_PROP_END_OF_LIST() | 142 | |
187 | +}; | 143 | span = L1STD_SPAN(&l1std); |
188 | + | 144 | |
189 | static void pl031_class_init(ObjectClass *klass, void *data) | ||
190 | { | ||
191 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
192 | |||
193 | dc->vmsd = &vmstate_pl031; | ||
194 | + dc->props = pl031_properties; | ||
195 | } | ||
196 | |||
197 | static const TypeInfo pl031_info = { | ||
198 | -- | 145 | -- |
199 | 2.20.1 | 146 | 2.34.1 |
200 | 147 | ||
201 | 148 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | The POSIX definition of the 'read' utility requires that you |
---|---|---|---|
2 | specify the variable name to set; omitting the name and | ||
3 | having it default to 'REPLY' is a bashism. If your system | ||
4 | sh is dash, then it will print an error message during build: | ||
2 | 5 | ||
3 | In the previous commit we fixed a crash when the guest read a | 6 | qemu/pc-bios/s390-ccw/../../scripts/git-submodule.sh: 106: read: arg count |
4 | register that pop from an empty FIFO. | ||
5 | By auditing the repository, we found another similar use with | ||
6 | an easy way to reproduce: | ||
7 | 7 | ||
8 | $ qemu-system-aarch64 -M xlnx-zcu102 -monitor stdio -S | 8 | Specify the variable name explicitly. |
9 | QEMU 4.0.50 monitor - type 'help' for more information | ||
10 | (qemu) xp/b 0xfd4a0134 | ||
11 | Aborted (core dumped) | ||
12 | 9 | ||
13 | (gdb) bt | 10 | Fixes: fdb8fd8cb915647b ("git-submodule: allow partial update of .git-submodule-status") |
14 | #0 0x00007f6936dea57f in raise () at /lib64/libc.so.6 | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | #1 0x00007f6936dd4895 in abort () at /lib64/libc.so.6 | 12 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> |
16 | #2 0x0000561ad32975ec in xlnx_dp_aux_pop_rx_fifo (s=0x7f692babee70) at hw/display/xlnx_dp.c:431 | 13 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
17 | #3 0x0000561ad3297dc0 in xlnx_dp_read (opaque=0x7f692babee70, offset=77, size=4) at hw/display/xlnx_dp.c:667 | 14 | Message-id: 20230720153038.1587196-1-peter.maydell@linaro.org |
18 | #4 0x0000561ad321b896 in memory_region_read_accessor (mr=0x7f692babf620, addr=308, value=0x7ffe05c1db88, size=4, shift=0, mask=4294967295, attrs=...) at memory.c:439 | 15 | --- |
19 | #5 0x0000561ad321bd70 in access_with_adjusted_size (addr=308, value=0x7ffe05c1db88, size=1, access_size_min=4, access_size_max=4, access_fn=0x561ad321b858 <memory_region_read_accessor>, mr=0x7f692babf620, attrs=...) at memory.c:569 | 16 | scripts/git-submodule.sh | 2 +- |
20 | #6 0x0000561ad321e9d5 in memory_region_dispatch_read1 (mr=0x7f692babf620, addr=308, pval=0x7ffe05c1db88, size=1, attrs=...) at memory.c:1420 | 17 | 1 file changed, 1 insertion(+), 1 deletion(-) |
21 | #7 0x0000561ad321ea9d in memory_region_dispatch_read (mr=0x7f692babf620, addr=308, pval=0x7ffe05c1db88, size=1, attrs=...) at memory.c:1447 | ||
22 | #8 0x0000561ad31bd742 in flatview_read_continue (fv=0x561ad69c04f0, addr=4249485620, attrs=..., buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", len=1, addr1=308, l=1, mr=0x7f692babf620) at exec.c:3385 | ||
23 | #9 0x0000561ad31bd895 in flatview_read (fv=0x561ad69c04f0, addr=4249485620, attrs=..., buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", len=1) at exec.c:3423 | ||
24 | #10 0x0000561ad31bd90b in address_space_read_full (as=0x561ad5bb3020, addr=4249485620, attrs=..., buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", len=1) at exec.c:3436 | ||
25 | #11 0x0000561ad33b1c42 in address_space_read (len=1, buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", attrs=..., addr=4249485620, as=0x561ad5bb3020) at include/exec/memory.h:2131 | ||
26 | #12 0x0000561ad33b1c42 in memory_dump (mon=0x561ad59c4530, count=1, format=120, wsize=1, addr=4249485620, is_physical=1) at monitor/misc.c:723 | ||
27 | #13 0x0000561ad33b1fc1 in hmp_physical_memory_dump (mon=0x561ad59c4530, qdict=0x561ad6c6fd00) at monitor/misc.c:795 | ||
28 | #14 0x0000561ad37b4a9f in handle_hmp_command (mon=0x561ad59c4530, cmdline=0x561ad59d0f22 "/b 0x00000000fd4a0134") at monitor/hmp.c:1082 | ||
29 | 18 | ||
30 | Fix by checking the FIFO is not empty before popping from it. | 19 | diff --git a/scripts/git-submodule.sh b/scripts/git-submodule.sh |
31 | 20 | index XXXXXXX..XXXXXXX 100755 | |
32 | The datasheet is not clear about the reset value of this register, | 21 | --- a/scripts/git-submodule.sh |
33 | we choose to return '0'. | 22 | +++ b/scripts/git-submodule.sh |
34 | 23 | @@ -XXX,XX +XXX,XX @@ update) | |
35 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 24 | check_updated $module || echo Updated "$module" |
36 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 25 | done |
37 | Message-id: 20190709113715.7761-4-philmd@redhat.com | 26 | |
38 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 27 | - (while read -r; do |
39 | --- | 28 | + (while read -r REPLY; do |
40 | hw/display/xlnx_dp.c | 15 +++++++++++---- | 29 | for module in $modules; do |
41 | 1 file changed, 11 insertions(+), 4 deletions(-) | 30 | case $REPLY in |
42 | 31 | *" $module "*) continue 2 ;; | |
43 | diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/hw/display/xlnx_dp.c | ||
46 | +++ b/hw/display/xlnx_dp.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static uint8_t xlnx_dp_aux_pop_rx_fifo(XlnxDPState *s) | ||
48 | uint8_t ret; | ||
49 | |||
50 | if (fifo8_is_empty(&s->rx_fifo)) { | ||
51 | - DPRINTF("rx_fifo underflow..\n"); | ||
52 | - abort(); | ||
53 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
54 | + "%s: Reading empty RX_FIFO\n", | ||
55 | + __func__); | ||
56 | + /* | ||
57 | + * The datasheet is not clear about the reset value, it seems | ||
58 | + * to be unspecified. We choose to return '0'. | ||
59 | + */ | ||
60 | + ret = 0; | ||
61 | + } else { | ||
62 | + ret = fifo8_pop(&s->rx_fifo); | ||
63 | + DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret); | ||
64 | } | ||
65 | - ret = fifo8_pop(&s->rx_fifo); | ||
66 | - DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret); | ||
67 | return ret; | ||
68 | } | ||
69 | |||
70 | -- | 32 | -- |
71 | 2.20.1 | 33 | 2.34.1 |
72 | 34 | ||
73 | 35 | diff view generated by jsdifflib |
1 | The ARMv5 architecture didn't specify detailed per-feature ID | 1 | A lot of the code called from helper_exception_bkpt_insn() is written |
---|---|---|---|
2 | registers. Now that we're using the MVFR0 register fields to | 2 | assuming A-profile, but we will also call this helper on M-profile |
3 | gate the existence of VFP instructions, we need to set up | 3 | CPUs when they execute a BKPT insn. This used to work by accident, |
4 | the correct values in the cpu->isar structure so that we still | 4 | but recent changes mean that we will hit an assert when some of this |
5 | provide an FPU to the guest. | 5 | code calls down into lower level functions that end up calling |
6 | arm_security_space_below_el3(), arm_el_is_aa64(), and other functions | ||
7 | that now explicitly assert that the guest CPU is not M-profile. | ||
6 | 8 | ||
7 | This fixes a regression in the arm926 and arm1026 CPUs, which | 9 | Handle M-profile directly to avoid the assertions: |
8 | are the only ones that both have VFP and are ARMv5 or earlier. | 10 | * in arm_debug_target_el(), M-profile debug exceptions always |
9 | This regression was introduced by the VFP refactoring, and more | 11 | go to EL1 |
10 | specifically by commits 1120827fa182f0e76 and 266bd25c485597c, | 12 | * in arm_debug_exception_fsr(), M-profile always uses the short |
11 | which accidentally disabled VFP short-vector support and | 13 | format FSR (compare commit d7fe699be54b2, though in this case |
12 | double-precision support on these CPUs. | 14 | the code in arm_v7m_cpu_do_interrupt() does not need to |
15 | look at the FSR value at all) | ||
13 | 16 | ||
14 | Fixes: 1120827fa182f0e | 17 | Cc: qemu-stable@nongnu.org |
15 | Fixes: 266bd25c485597c | 18 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1775 |
16 | Fixes: https://bugs.launchpad.net/qemu/+bug/1836192 | ||
17 | Reported-by: Christophe Lyon <christophe.lyon@linaro.org> | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
20 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 21 | Message-id: 20230721143239.1753066-1-peter.maydell@linaro.org |
21 | Tested-by: Christophe Lyon <christophe.lyon@linaro.org> | ||
22 | Message-id: 20190711131241.22231-1-peter.maydell@linaro.org | ||
23 | --- | 22 | --- |
24 | target/arm/cpu.c | 12 ++++++++++++ | 23 | target/arm/debug_helper.c | 18 ++++++++++++------ |
25 | 1 file changed, 12 insertions(+) | 24 | 1 file changed, 12 insertions(+), 6 deletions(-) |
26 | 25 | ||
27 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 26 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c |
28 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/target/arm/cpu.c | 28 | --- a/target/arm/debug_helper.c |
30 | +++ b/target/arm/cpu.c | 29 | +++ b/target/arm/debug_helper.c |
31 | @@ -XXX,XX +XXX,XX @@ static void arm926_initfn(Object *obj) | 30 | @@ -XXX,XX +XXX,XX @@ static int arm_debug_target_el(CPUARMState *env) |
32 | * set the field to indicate Jazelle support within QEMU. | 31 | bool secure = arm_is_secure(env); |
33 | */ | 32 | bool route_to_el2 = false; |
34 | cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); | 33 | |
35 | + /* | 34 | + if (arm_feature(env, ARM_FEATURE_M)) { |
36 | + * Similarly, we need to set MVFR0 fields to enable double precision | 35 | + return 1; |
37 | + * and short vector support even though ARMv5 doesn't have this register. | 36 | + } |
38 | + */ | 37 | + |
39 | + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); | 38 | if (arm_is_el2_enabled(env)) { |
40 | + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); | 39 | route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || |
41 | } | 40 | env->cp15.mdcr_el2 & MDCR_TDE; |
42 | 41 | @@ -XXX,XX +XXX,XX @@ static uint32_t arm_debug_exception_fsr(CPUARMState *env) | |
43 | static void arm946_initfn(Object *obj) | 42 | { |
44 | @@ -XXX,XX +XXX,XX @@ static void arm1026_initfn(Object *obj) | 43 | ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; |
45 | * set the field to indicate Jazelle support within QEMU. | 44 | int target_el = arm_debug_target_el(env); |
46 | */ | 45 | - bool using_lpae = false; |
47 | cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); | 46 | + bool using_lpae; |
48 | + /* | 47 | |
49 | + * Similarly, we need to set MVFR0 fields to enable double precision | 48 | - if (target_el == 2 || arm_el_is_aa64(env, target_el)) { |
50 | + * and short vector support even though ARMv5 doesn't have this register. | 49 | + if (arm_feature(env, ARM_FEATURE_M)) { |
51 | + */ | 50 | + using_lpae = false; |
52 | + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); | 51 | + } else if (target_el == 2 || arm_el_is_aa64(env, target_el)) { |
53 | + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); | 52 | using_lpae = true; |
54 | 53 | } else if (arm_feature(env, ARM_FEATURE_PMSA) && | |
55 | { | 54 | arm_feature(env, ARM_FEATURE_V8)) { |
56 | /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ | 55 | using_lpae = true; |
56 | + } else if (arm_feature(env, ARM_FEATURE_LPAE) && | ||
57 | + (env->cp15.tcr_el[target_el] & TTBCR_EAE)) { | ||
58 | + using_lpae = true; | ||
59 | } else { | ||
60 | - if (arm_feature(env, ARM_FEATURE_LPAE) && | ||
61 | - (env->cp15.tcr_el[target_el] & TTBCR_EAE)) { | ||
62 | - using_lpae = true; | ||
63 | - } | ||
64 | + using_lpae = false; | ||
65 | } | ||
66 | |||
67 | if (using_lpae) { | ||
57 | -- | 68 | -- |
58 | 2.20.1 | 69 | 2.34.1 |
59 | |||
60 | diff view generated by jsdifflib |
1 | From: David Engraf <david.engraf@sysgo.com> | 1 | From: Sean Estabrooks <sean.estabrooks@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | Using the whole 128 MiB flash in non-secure mode is not working because | 3 | The curses display handles most control-X keys, and translates |
4 | virt_flash_fdt() expects the same address for secure_sysmem and sysmem. | 4 | them into their corresponding keycode. Here we recognize |
5 | This is not correctly handled by caller because it forwards NULL for | 5 | a few that are missing, Ctrl-@ (null), Ctrl-\ (backslash), |
6 | secure_sysmem in non-secure flash mode. | 6 | Ctrl-] (right bracket), Ctrl-^ (caret), Ctrl-_ (underscore). |
7 | 7 | ||
8 | Fixed by using sysmem when secure_sysmem is NULL. | 8 | Signed-off-by: Sean Estabrooks <sean.estabrooks@gmail.com> |
9 | 9 | Message-id: CAHyVn3Bh9CRgDuOmf7G7Ngwamu8d4cVozAcB2i4ymnnggBXNmg@mail.gmail.com | |
10 | Signed-off-by: David Engraf <david.engraf@sysgo.com> | ||
11 | Message-id: 20190712075002.14326-1-david.engraf@sysgo.com | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 12 | --- |
15 | hw/arm/virt.c | 2 +- | 13 | ui/curses_keys.h | 6 ++++++ |
16 | 1 file changed, 1 insertion(+), 1 deletion(-) | 14 | 1 file changed, 6 insertions(+) |
17 | 15 | ||
18 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 16 | diff --git a/ui/curses_keys.h b/ui/curses_keys.h |
19 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/hw/arm/virt.c | 18 | --- a/ui/curses_keys.h |
21 | +++ b/hw/arm/virt.c | 19 | +++ b/ui/curses_keys.h |
22 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | 20 | @@ -XXX,XX +XXX,XX @@ static const int _curses2keycode[CURSES_CHARS] = { |
23 | &machine->device_memory->mr); | 21 | ['N' - '@'] = 49 | CNTRL, /* Control + n */ |
24 | } | 22 | /* Control + m collides with the keycode for Enter */ |
25 | 23 | ||
26 | - virt_flash_fdt(vms, sysmem, secure_sysmem); | 24 | + ['@' - '@'] = 3 | CNTRL, /* Control + @ */ |
27 | + virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); | 25 | + /* Control + [ collides with the keycode for Escape */ |
28 | 26 | + ['\\' - '@'] = 43 | CNTRL, /* Control + Backslash */ | |
29 | create_gic(vms, pic); | 27 | + [']' - '@'] = 27 | CNTRL, /* Control + ] */ |
30 | 28 | + ['^' - '@'] = 7 | CNTRL, /* Control + ^ */ | |
29 | + ['_' - '@'] = 12 | CNTRL, /* Control + Underscore */ | ||
30 | }; | ||
31 | |||
32 | static const int _curseskey2keycode[CURSES_KEYS] = { | ||
31 | -- | 33 | -- |
32 | 2.20.1 | 34 | 2.34.1 |
33 | |||
34 | diff view generated by jsdifflib |
1 | In the M-profile architecture, when we do a vector table fetch and it | 1 | The "expected failure" tests for decodetree result in the |
---|---|---|---|
2 | fails, we need to report a HardFault. Whether this is a Secure HF or | 2 | error messages from decodetree ending up in logs and in |
3 | a NonSecure HF depends on several things. If AIRCR.BFHFNMINS is 0 | 3 | V=1 output: |
4 | then HF is always Secure, because there is no NonSecure HardFault. | ||
5 | Otherwise, the answer depends on whether the 'underlying exception' | ||
6 | (MemManage, BusFault, SecureFault) targets Secure or NonSecure. (In | ||
7 | the pseudocode, this is handled in the Vector() function: the final | ||
8 | exc.isSecure is calculated by looking at the exc.isSecure from the | ||
9 | exception returned from the memory access, not the isSecure input | ||
10 | argument.) | ||
11 | 4 | ||
12 | We weren't doing this correctly, because we were looking at | 5 | >>> MALLOC_PERTURB_=226 /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/x86/pyvenv/bin/python3 /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/scripts/decodetree.py --output-null --test-for-error /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/x86/../../tests/decode/err_argset1.decode |
13 | the target security domain of the exception we were trying to | 6 | ――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――― ✀ ―――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――― |
14 | load the vector table entry for. This produces errors of two kinds: | 7 | /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/x86/../../tests/decode/err_argset1.decode:5: error: duplicate argument "a" |
15 | * a load from the NS vector table which hits the "NS access | 8 | ――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――― |
16 | to S memory" SecureFault should end up as a Secure HardFault, | 9 | 1/44 qemu:decodetree / err_argset1 OK 0.05s |
17 | but we were raising an NS HardFault | ||
18 | * a load from the S vector table which causes a BusFault | ||
19 | should raise an NS HardFault if BFHFNMINS == 1 (because | ||
20 | in that case all BusFaults are NonSecure), but we were raising | ||
21 | a Secure HardFault | ||
22 | 10 | ||
23 | Correct the logic. | 11 | This then produces false positives when scanning the |
12 | logfiles for strings like "error: ". | ||
24 | 13 | ||
25 | We also fix a comment error where we claimed that we might | 14 | For the expected-failure tests, make decodetree print |
26 | be escalating MemManage to HardFault, and forgot about SecureFault. | 15 | "detected:" instead of "error:". |
27 | (Vector loads can never hit MPU access faults, because they're | ||
28 | always aligned and always use the default address map.) | ||
29 | 16 | ||
30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
31 | Message-id: 20190705094823.28905-1-peter.maydell@linaro.org | 18 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
20 | Message-id: 20230720131521.1325905-1-peter.maydell@linaro.org | ||
32 | --- | 21 | --- |
33 | target/arm/m_helper.c | 21 +++++++++++++++++---- | 22 | scripts/decodetree.py | 6 +++++- |
34 | 1 file changed, 17 insertions(+), 4 deletions(-) | 23 | 1 file changed, 5 insertions(+), 1 deletion(-) |
35 | 24 | ||
36 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | 25 | diff --git a/scripts/decodetree.py b/scripts/decodetree.py |
37 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/target/arm/m_helper.c | 27 | --- a/scripts/decodetree.py |
39 | +++ b/target/arm/m_helper.c | 28 | +++ b/scripts/decodetree.py |
40 | @@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure, | 29 | @@ -XXX,XX +XXX,XX @@ def error_with_file(file, lineno, *args): |
41 | if (sattrs.ns) { | 30 | global output_file |
42 | attrs.secure = false; | 31 | global output_fd |
43 | } else if (!targets_secure) { | 32 | |
44 | - /* NS access to S memory */ | 33 | + # For the test suite expected-errors case, don't print the |
45 | + /* | 34 | + # string "error: ", so they don't turn up as false positives |
46 | + * NS access to S memory: the underlying exception which we escalate | 35 | + # if you grep the meson logs for strings like that. |
47 | + * to HardFault is SecureFault, which always targets Secure. | 36 | + end = 'error: ' if not testforerror else 'detected: ' |
48 | + */ | 37 | prefix = '' |
49 | + exc_secure = true; | 38 | if file: |
50 | goto load_fail; | 39 | prefix += f'{file}:' |
51 | } | 40 | @@ -XXX,XX +XXX,XX @@ def error_with_file(file, lineno, *args): |
52 | } | 41 | prefix += f'{lineno}:' |
53 | @@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure, | 42 | if prefix: |
54 | vector_entry = address_space_ldl(arm_addressspace(cs, attrs), addr, | 43 | prefix += ' ' |
55 | attrs, &result); | 44 | - print(prefix, end='error: ', file=sys.stderr) |
56 | if (result != MEMTX_OK) { | 45 | + print(prefix, end=end, file=sys.stderr) |
57 | + /* | 46 | print(*args, file=sys.stderr) |
58 | + * Underlying exception is BusFault: its target security state | 47 | |
59 | + * depends on BFHFNMINS. | 48 | if output_file and output_fd: |
60 | + */ | ||
61 | + exc_secure = !(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK); | ||
62 | goto load_fail; | ||
63 | } | ||
64 | *pvec = vector_entry; | ||
65 | @@ -XXX,XX +XXX,XX @@ load_fail: | ||
66 | /* | ||
67 | * All vector table fetch fails are reported as HardFault, with | ||
68 | * HFSR.VECTTBL and .FORCED set. (FORCED is set because | ||
69 | - * technically the underlying exception is a MemManage or BusFault | ||
70 | + * technically the underlying exception is a SecureFault or BusFault | ||
71 | * that is escalated to HardFault.) This is a terminal exception, | ||
72 | * so we will either take the HardFault immediately or else enter | ||
73 | * lockup (the latter case is handled in armv7m_nvic_set_pending_derived()). | ||
74 | + * The HardFault is Secure if BFHFNMINS is 0 (meaning that all HFs are | ||
75 | + * secure); otherwise it targets the same security state as the | ||
76 | + * underlying exception. | ||
77 | */ | ||
78 | - exc_secure = targets_secure || | ||
79 | - !(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK); | ||
80 | + if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { | ||
81 | + exc_secure = true; | ||
82 | + } | ||
83 | env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK | R_V7M_HFSR_FORCED_MASK; | ||
84 | armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secure); | ||
85 | return false; | ||
86 | -- | 49 | -- |
87 | 2.20.1 | 50 | 2.34.1 |
88 | 51 | ||
89 | 52 | diff view generated by jsdifflib |