[Qemu-devel] [PULL 00/10] target-arm queue
[PULL 00/54] target-arm queue
1
target-arm queue for rc1 -- these are all bug fixes.
1
This is mostly RTH's tcg_constant refactoring work, plus a few
2
other things.
2
3
3
thanks
4
thanks
4
-- PMM
5
-- PMM
5
6
6
The following changes since commit b9404bf592e7ba74180e1a54ed7a266ec6ee67f2:
7
The following changes since commit cf6f26d6f9b2015ee12b4604b79359e76784163a:
7
8
8
Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20190715' into staging (2019-07-15 12:22:07 +0100)
9
Merge tag 'kraxel-20220427-pull-request' of git://git.kraxel.org/qemu into staging (2022-04-27 10:49:28 -0700)
9
10
10
are available in the Git repository at:
11
are available in the Git repository at:
11
12
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190715
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220428
13
14
14
for you to fetch changes up to 51c9122e92b776a3f16af0b9282f1dc5012e2a19:
15
for you to fetch changes up to f8e7163d9e6740b5cef02bf73a17a59d0bef8bdb:
15
16
16
target/arm: NS BusFault on vector table fetch escalates to NS HardFault (2019-07-15 14:17:04 +0100)
17
hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2 (2022-04-28 13:59:23 +0100)
17
18
18
----------------------------------------------------------------
19
----------------------------------------------------------------
19
target-arm queue:
20
target-arm queue:
20
* report ARMv8-A FP support for AArch32 -cpu max
21
* refactor to use tcg_constant where appropriate
21
* hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
22
* Advertise support for FEAT_TTL and FEAT_BBM level 2
22
* hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
23
* smmuv3: Cache event fault record
23
* hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
24
* smmuv3: Add space in guest error message
24
* hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
25
* smmuv3: Advertise support for SMMUv3.2-BBML2
25
* hw/arm/virt: Fix non-secure flash mode
26
* pl031: Correctly migrate state when using -rtc clock=host
27
* fix regression that meant arm926 and arm1026 lost VFP
28
double-precision support
29
* v8M: NS BusFault on vector table fetch escalates to NS HardFault
30
26
31
----------------------------------------------------------------
27
----------------------------------------------------------------
32
Alex Bennée (1):
28
Damien Hedde (1):
33
target/arm: report ARMv8-A FP support for AArch32 -cpu max
29
target/arm: Disable cryptographic instructions when neon is disabled
34
30
35
David Engraf (1):
31
Jean-Philippe Brucker (2):
36
hw/arm/virt: Fix non-secure flash mode
32
hw/arm/smmuv3: Cache event fault record
33
hw/arm/smmuv3: Add space in guest error message
37
34
38
Peter Maydell (3):
35
Peter Maydell (3):
39
pl031: Correctly migrate state when using -rtc clock=host
36
target/arm: Advertise support for FEAT_TTL
40
target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026
37
target/arm: Advertise support for FEAT_BBM level 2
41
target/arm: NS BusFault on vector table fetch escalates to NS HardFault
38
hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2
42
39
43
Philippe Mathieu-Daudé (5):
40
Richard Henderson (48):
44
hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs
41
target/arm: Use tcg_constant in gen_probe_access
45
hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
42
target/arm: Use tcg_constant in gen_mte_check*
46
hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
43
target/arm: Use tcg_constant in gen_exception*
47
hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
44
target/arm: Use tcg_constant in gen_adc_CC
48
hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
45
target/arm: Use tcg_constant in handle_msr_i
46
target/arm: Use tcg_constant in handle_sys
47
target/arm: Use tcg_constant in disas_exc
48
target/arm: Use tcg_constant in gen_compare_and_swap_pair
49
target/arm: Use tcg_constant in disas_ld_lit
50
target/arm: Use tcg_constant in disas_ldst_*
51
target/arm: Use tcg_constant in disas_add_sum_imm*
52
target/arm: Use tcg_constant in disas_movw_imm
53
target/arm: Use tcg_constant in shift_reg_imm
54
target/arm: Use tcg_constant in disas_cond_select
55
target/arm: Use tcg_constant in handle_{rev16,crc32}
56
target/arm: Use tcg_constant in disas_data_proc_2src
57
target/arm: Use tcg_constant in disas_fp*
58
target/arm: Use tcg_constant in simd shift expanders
59
target/arm: Use tcg_constant in simd fp/int conversion
60
target/arm: Use tcg_constant in 2misc expanders
61
target/arm: Use tcg_constant in balance of translate-a64.c
62
target/arm: Use tcg_constant for aa32 exceptions
63
target/arm: Use tcg_constant for disas_iwmmxt_insn
64
target/arm: Use tcg_constant for gen_{msr,mrs}
65
target/arm: Use tcg_constant for vector shift expanders
66
target/arm: Use tcg_constant for do_coproc_insn
67
target/arm: Use tcg_constant for gen_srs
68
target/arm: Use tcg_constant for op_s_{rri,rxi}_rot
69
target/arm: Use tcg_constant for MOVW, UMAAL, CRC32
70
target/arm: Use tcg_constant for v7m MRS, MSR
71
target/arm: Use tcg_constant for TT, SAT, SMMLA
72
target/arm: Use tcg_constant in LDM, STM
73
target/arm: Use tcg_constant in CLRM, DLS, WLS, LE
74
target/arm: Use tcg_constant in trans_CPS_v7m
75
target/arm: Use tcg_constant in trans_CSEL
76
target/arm: Use tcg_constant for trans_INDEX_*
77
target/arm: Use tcg_constant in SINCDEC, INCDEC
78
target/arm: Use tcg_constant in FCPY, CPY
79
target/arm: Use tcg_constant in {incr, wrap}_last_active
80
target/arm: Use tcg_constant in do_clast_scalar
81
target/arm: Use tcg_constant in WHILE
82
target/arm: Use tcg_constant in LD1, ST1
83
target/arm: Use tcg_constant in SUBR
84
target/arm: Use tcg_constant in do_zzi_{sat, ool}, do_fp_imm
85
target/arm: Use tcg_constant for predicate descriptors
86
target/arm: Use tcg_constant for do_brk{2,3}
87
target/arm: Use tcg_constant for vector descriptor
88
target/arm: Use field names for accessing DBGWCRn
49
89
50
include/hw/timer/pl031.h | 2 ++
90
docs/system/arm/emulation.rst | 2 +
51
hw/arm/virt.c | 2 +-
91
hw/arm/smmuv3-internal.h | 2 +-
52
hw/core/machine.c | 1 +
92
include/hw/arm/smmu-common.h | 1 +
53
hw/display/xlnx_dp.c | 15 +++++---
93
target/arm/internals.h | 12 ++
54
hw/ssi/mss-spi.c | 8 ++++-
94
hw/arm/smmuv3.c | 17 +--
55
hw/ssi/xilinx_spips.c | 43 +++++++++++++++-------
95
target/arm/cpu.c | 9 ++
56
hw/timer/pl031.c | 92 +++++++++++++++++++++++++++++++++++++++++++++---
96
target/arm/cpu64.c | 2 +
57
target/arm/cpu.c | 16 +++++++++
97
target/arm/debug_helper.c | 10 +-
58
target/arm/m_helper.c | 21 ++++++++---
98
target/arm/helper.c | 8 +-
59
9 files changed, 174 insertions(+), 26 deletions(-)
99
target/arm/kvm64.c | 14 +-
60
100
target/arm/translate-a64.c | 301 +++++++++++++-----------------------------
101
target/arm/translate-sve.c | 202 ++++++++++------------------
102
target/arm/translate.c | 244 ++++++++++++----------------------
103
13 files changed, 293 insertions(+), 531 deletions(-)
diff view generated by jsdifflib
New patch
[PULL 01/54] target/arm: Use tcg_constant in gen_probe_access
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-2-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 12 ++++--------
9
1 file changed, 4 insertions(+), 8 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void gen_address_with_allocation_tag0(TCGv_i64 dst, TCGv_i64 src)
16
static void gen_probe_access(DisasContext *s, TCGv_i64 ptr,
17
MMUAccessType acc, int log2_size)
18
{
19
- TCGv_i32 t_acc = tcg_const_i32(acc);
20
- TCGv_i32 t_idx = tcg_const_i32(get_mem_index(s));
21
- TCGv_i32 t_size = tcg_const_i32(1 << log2_size);
22
-
23
- gen_helper_probe_access(cpu_env, ptr, t_acc, t_idx, t_size);
24
- tcg_temp_free_i32(t_acc);
25
- tcg_temp_free_i32(t_idx);
26
- tcg_temp_free_i32(t_size);
27
+ gen_helper_probe_access(cpu_env, ptr,
28
+ tcg_constant_i32(acc),
29
+ tcg_constant_i32(get_mem_index(s)),
30
+ tcg_constant_i32(1 << log2_size));
31
}
32
33
/*
34
--
35
2.25.1
diff view generated by jsdifflib
New patch
[PULL 02/54] target/arm: Use tcg_constant in gen_mte_check*
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-3-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 10 ++--------
9
1 file changed, 2 insertions(+), 8 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr,
16
int core_idx)
17
{
18
if (tag_checked && s->mte_active[is_unpriv]) {
19
- TCGv_i32 tcg_desc;
20
TCGv_i64 ret;
21
int desc = 0;
22
23
@@ -XXX,XX +XXX,XX @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr,
24
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
25
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
26
desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << log2_size) - 1);
27
- tcg_desc = tcg_const_i32(desc);
28
29
ret = new_tmp_a64(s);
30
- gen_helper_mte_check(ret, cpu_env, tcg_desc, addr);
31
- tcg_temp_free_i32(tcg_desc);
32
+ gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr);
33
34
return ret;
35
}
36
@@ -XXX,XX +XXX,XX @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
37
bool tag_checked, int size)
38
{
39
if (tag_checked && s->mte_active[0]) {
40
- TCGv_i32 tcg_desc;
41
TCGv_i64 ret;
42
int desc = 0;
43
44
@@ -XXX,XX +XXX,XX @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
45
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
46
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
47
desc = FIELD_DP32(desc, MTEDESC, SIZEM1, size - 1);
48
- tcg_desc = tcg_const_i32(desc);
49
50
ret = new_tmp_a64(s);
51
- gen_helper_mte_check(ret, cpu_env, tcg_desc, addr);
52
- tcg_temp_free_i32(tcg_desc);
53
+ gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr);
54
55
return ret;
56
}
57
--
58
2.25.1
diff view generated by jsdifflib
New patch
[PULL 03/54] target/arm: Use tcg_constant in gen_exception*
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-4-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 11 ++---------
9
1 file changed, 2 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void gen_rebuild_hflags(DisasContext *s)
16
17
static void gen_exception_internal(int excp)
18
{
19
- TCGv_i32 tcg_excp = tcg_const_i32(excp);
20
-
21
assert(excp_is_internal(excp));
22
- gen_helper_exception_internal(cpu_env, tcg_excp);
23
- tcg_temp_free_i32(tcg_excp);
24
+ gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp));
25
}
26
27
static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
28
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
29
30
static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome)
31
{
32
- TCGv_i32 tcg_syn;
33
-
34
gen_a64_set_pc_im(s->pc_curr);
35
- tcg_syn = tcg_const_i32(syndrome);
36
- gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
37
- tcg_temp_free_i32(tcg_syn);
38
+ gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome));
39
s->base.is_jmp = DISAS_NORETURN;
40
}
41
42
--
43
2.25.1
diff view generated by jsdifflib
New patch
[PULL 04/54] target/arm: Use tcg_constant in gen_adc_CC
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Note that tmp was doing double-duty as zero
4
and then later as a temporary in its own right.
5
Split the use of 0 to a new variable 'zero'.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220426163043.100432-5-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-a64.c | 26 +++++++++++++-------------
13
1 file changed, 13 insertions(+), 13 deletions(-)
14
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
19
@@ -XXX,XX +XXX,XX @@ static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
20
static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
21
{
22
if (sf) {
23
- TCGv_i64 result, cf_64, vf_64, tmp;
24
- result = tcg_temp_new_i64();
25
- cf_64 = tcg_temp_new_i64();
26
- vf_64 = tcg_temp_new_i64();
27
- tmp = tcg_const_i64(0);
28
+ TCGv_i64 result = tcg_temp_new_i64();
29
+ TCGv_i64 cf_64 = tcg_temp_new_i64();
30
+ TCGv_i64 vf_64 = tcg_temp_new_i64();
31
+ TCGv_i64 tmp = tcg_temp_new_i64();
32
+ TCGv_i64 zero = tcg_constant_i64(0);
33
34
tcg_gen_extu_i32_i64(cf_64, cpu_CF);
35
- tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp);
36
- tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp);
37
+ tcg_gen_add2_i64(result, cf_64, t0, zero, cf_64, zero);
38
+ tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, zero);
39
tcg_gen_extrl_i64_i32(cpu_CF, cf_64);
40
gen_set_NZ64(result);
41
42
@@ -XXX,XX +XXX,XX @@ static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
43
tcg_temp_free_i64(cf_64);
44
tcg_temp_free_i64(result);
45
} else {
46
- TCGv_i32 t0_32, t1_32, tmp;
47
- t0_32 = tcg_temp_new_i32();
48
- t1_32 = tcg_temp_new_i32();
49
- tmp = tcg_const_i32(0);
50
+ TCGv_i32 t0_32 = tcg_temp_new_i32();
51
+ TCGv_i32 t1_32 = tcg_temp_new_i32();
52
+ TCGv_i32 tmp = tcg_temp_new_i32();
53
+ TCGv_i32 zero = tcg_constant_i32(0);
54
55
tcg_gen_extrl_i64_i32(t0_32, t0);
56
tcg_gen_extrl_i64_i32(t1_32, t1);
57
- tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp);
58
- tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp);
59
+ tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, zero, cpu_CF, zero);
60
+ tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, zero);
61
62
tcg_gen_mov_i32(cpu_ZF, cpu_NF);
63
tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
64
--
65
2.25.1
diff view generated by jsdifflib
New patch
[PULL 05/54] target/arm: Use tcg_constant in handle_msr_i
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-6-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 13 +++----------
9
1 file changed, 3 insertions(+), 10 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void gen_axflag(void)
16
static void handle_msr_i(DisasContext *s, uint32_t insn,
17
unsigned int op1, unsigned int op2, unsigned int crm)
18
{
19
- TCGv_i32 t1;
20
int op = op1 << 3 | op2;
21
22
/* End the TB by default, chaining is ok. */
23
@@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
24
if (s->current_el == 0) {
25
goto do_unallocated;
26
}
27
- t1 = tcg_const_i32(crm & PSTATE_SP);
28
- gen_helper_msr_i_spsel(cpu_env, t1);
29
- tcg_temp_free_i32(t1);
30
+ gen_helper_msr_i_spsel(cpu_env, tcg_constant_i32(crm & PSTATE_SP));
31
break;
32
33
case 0x19: /* SSBS */
34
@@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
35
break;
36
37
case 0x1e: /* DAIFSet */
38
- t1 = tcg_const_i32(crm);
39
- gen_helper_msr_i_daifset(cpu_env, t1);
40
- tcg_temp_free_i32(t1);
41
+ gen_helper_msr_i_daifset(cpu_env, tcg_constant_i32(crm));
42
break;
43
44
case 0x1f: /* DAIFClear */
45
- t1 = tcg_const_i32(crm);
46
- gen_helper_msr_i_daifclear(cpu_env, t1);
47
- tcg_temp_free_i32(t1);
48
+ gen_helper_msr_i_daifclear(cpu_env, tcg_constant_i32(crm));
49
/* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
50
s->base.is_jmp = DISAS_UPDATE_EXIT;
51
break;
52
--
53
2.25.1
diff view generated by jsdifflib
New patch
[PULL 06/54] target/arm: Use tcg_constant in handle_sys
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-7-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 31 +++++++++----------------------
9
1 file changed, 9 insertions(+), 22 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
16
/* Emit code to perform further access permissions checks at
17
* runtime; this may result in an exception.
18
*/
19
- TCGv_ptr tmpptr;
20
- TCGv_i32 tcg_syn, tcg_isread;
21
uint32_t syndrome;
22
23
- gen_a64_set_pc_im(s->pc_curr);
24
- tmpptr = tcg_const_ptr(ri);
25
syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
26
- tcg_syn = tcg_const_i32(syndrome);
27
- tcg_isread = tcg_const_i32(isread);
28
- gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_isread);
29
- tcg_temp_free_ptr(tmpptr);
30
- tcg_temp_free_i32(tcg_syn);
31
- tcg_temp_free_i32(tcg_isread);
32
+ gen_a64_set_pc_im(s->pc_curr);
33
+ gen_helper_access_check_cp_reg(cpu_env,
34
+ tcg_constant_ptr(ri),
35
+ tcg_constant_i32(syndrome),
36
+ tcg_constant_i32(isread));
37
} else if (ri->type & ARM_CP_RAISES_EXC) {
38
/*
39
* The readfn or writefn might raise an exception;
40
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
41
case ARM_CP_DC_ZVA:
42
/* Writes clear the aligned block of memory which rt points into. */
43
if (s->mte_active[0]) {
44
- TCGv_i32 t_desc;
45
int desc = 0;
46
47
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
48
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
49
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
50
- t_desc = tcg_const_i32(desc);
51
52
tcg_rt = new_tmp_a64(s);
53
- gen_helper_mte_check_zva(tcg_rt, cpu_env, t_desc, cpu_reg(s, rt));
54
- tcg_temp_free_i32(t_desc);
55
+ gen_helper_mte_check_zva(tcg_rt, cpu_env,
56
+ tcg_constant_i32(desc), cpu_reg(s, rt));
57
} else {
58
tcg_rt = clean_data_tbi(s, cpu_reg(s, rt));
59
}
60
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
61
if (ri->type & ARM_CP_CONST) {
62
tcg_gen_movi_i64(tcg_rt, ri->resetvalue);
63
} else if (ri->readfn) {
64
- TCGv_ptr tmpptr;
65
- tmpptr = tcg_const_ptr(ri);
66
- gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr);
67
- tcg_temp_free_ptr(tmpptr);
68
+ gen_helper_get_cp_reg64(tcg_rt, cpu_env, tcg_constant_ptr(ri));
69
} else {
70
tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset);
71
}
72
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
73
/* If not forbidden by access permissions, treat as WI */
74
return;
75
} else if (ri->writefn) {
76
- TCGv_ptr tmpptr;
77
- tmpptr = tcg_const_ptr(ri);
78
- gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt);
79
- tcg_temp_free_ptr(tmpptr);
80
+ gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri), tcg_rt);
81
} else {
82
tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset);
83
}
84
--
85
2.25.1
diff view generated by jsdifflib
New patch
[PULL 07/54] target/arm: Use tcg_constant in disas_exc
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-8-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 5 +----
9
1 file changed, 1 insertion(+), 4 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
16
int opc = extract32(insn, 21, 3);
17
int op2_ll = extract32(insn, 0, 5);
18
int imm16 = extract32(insn, 5, 16);
19
- TCGv_i32 tmp;
20
21
switch (opc) {
22
case 0:
23
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
24
break;
25
}
26
gen_a64_set_pc_im(s->pc_curr);
27
- tmp = tcg_const_i32(syn_aa64_smc(imm16));
28
- gen_helper_pre_smc(cpu_env, tmp);
29
- tcg_temp_free_i32(tmp);
30
+ gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16)));
31
gen_ss_advance(s);
32
gen_exception_insn(s, s->base.pc_next, EXCP_SMC,
33
syn_aa64_smc(imm16), 3);
34
--
35
2.25.1
diff view generated by jsdifflib
New patch
[PULL 08/54] target/arm: Use tcg_constant in gen_compare_and_swap_pair
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-9-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 6 ++----
9
1 file changed, 2 insertions(+), 4 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
16
tcg_temp_free_i64(cmp);
17
} else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
18
if (HAVE_CMPXCHG128) {
19
- TCGv_i32 tcg_rs = tcg_const_i32(rs);
20
+ TCGv_i32 tcg_rs = tcg_constant_i32(rs);
21
if (s->be_data == MO_LE) {
22
gen_helper_casp_le_parallel(cpu_env, tcg_rs,
23
clean_addr, t1, t2);
24
@@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
25
gen_helper_casp_be_parallel(cpu_env, tcg_rs,
26
clean_addr, t1, t2);
27
}
28
- tcg_temp_free_i32(tcg_rs);
29
} else {
30
gen_helper_exit_atomic(cpu_env);
31
s->base.is_jmp = DISAS_NORETURN;
32
@@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
33
TCGv_i64 a2 = tcg_temp_new_i64();
34
TCGv_i64 c1 = tcg_temp_new_i64();
35
TCGv_i64 c2 = tcg_temp_new_i64();
36
- TCGv_i64 zero = tcg_const_i64(0);
37
+ TCGv_i64 zero = tcg_constant_i64(0);
38
39
/* Load the two words, in memory order. */
40
tcg_gen_qemu_ld_i64(d1, clean_addr, memidx,
41
@@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
42
tcg_temp_free_i64(a2);
43
tcg_temp_free_i64(c1);
44
tcg_temp_free_i64(c2);
45
- tcg_temp_free_i64(zero);
46
47
/* Write back the data from memory to Rs. */
48
tcg_gen_mov_i64(s1, d1);
49
--
50
2.25.1
diff view generated by jsdifflib
New patch
[PULL 09/54] target/arm: Use tcg_constant in disas_ld_lit
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-10-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 3 +--
9
1 file changed, 1 insertion(+), 2 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
16
17
tcg_rt = cpu_reg(s, rt);
18
19
- clean_addr = tcg_const_i64(s->pc_curr + imm);
20
+ clean_addr = tcg_constant_i64(s->pc_curr + imm);
21
if (is_vector) {
22
do_fp_ld(s, rt, clean_addr, size);
23
} else {
24
@@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
25
do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN,
26
false, true, rt, iss_sf, false);
27
}
28
- tcg_temp_free_i64(clean_addr);
29
}
30
31
/*
32
--
33
2.25.1
diff view generated by jsdifflib
New patch
[PULL 10/54] target/arm: Use tcg_constant in disas_ldst_*
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-11-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 9 +++------
9
1 file changed, 3 insertions(+), 6 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
16
mop = endian | size | align;
17
18
elements = (is_q ? 16 : 8) >> size;
19
- tcg_ebytes = tcg_const_i64(1 << size);
20
+ tcg_ebytes = tcg_constant_i64(1 << size);
21
for (r = 0; r < rpt; r++) {
22
int e;
23
for (e = 0; e < elements; e++) {
24
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
25
}
26
}
27
}
28
- tcg_temp_free_i64(tcg_ebytes);
29
30
if (!is_store) {
31
/* For non-quad operations, setting a slice of the low
32
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
33
total);
34
mop = finalize_memop(s, scale);
35
36
- tcg_ebytes = tcg_const_i64(1 << scale);
37
+ tcg_ebytes = tcg_constant_i64(1 << scale);
38
for (xs = 0; xs < selem; xs++) {
39
if (replicate) {
40
/* Load and replicate to all elements */
41
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
42
tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
43
rt = (rt + 1) % 32;
44
}
45
- tcg_temp_free_i64(tcg_ebytes);
46
47
if (is_postidx) {
48
if (rm == 31) {
49
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
50
51
if (is_zero) {
52
TCGv_i64 clean_addr = clean_data_tbi(s, addr);
53
- TCGv_i64 tcg_zero = tcg_const_i64(0);
54
+ TCGv_i64 tcg_zero = tcg_constant_i64(0);
55
int mem_index = get_mem_index(s);
56
int i, n = (1 + is_pair) << LOG2_TAG_GRANULE;
57
58
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
59
tcg_gen_addi_i64(clean_addr, clean_addr, 8);
60
tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_UQ);
61
}
62
- tcg_temp_free_i64(tcg_zero);
63
}
64
65
if (index != 0) {
66
--
67
2.25.1
diff view generated by jsdifflib
New patch
[PULL 11/54] target/arm: Use tcg_constant in disas_add_sum_imm*
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-12-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 12 ++++--------
9
1 file changed, 4 insertions(+), 8 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
16
tcg_gen_addi_i64(tcg_result, tcg_rn, imm);
17
}
18
} else {
19
- TCGv_i64 tcg_imm = tcg_const_i64(imm);
20
+ TCGv_i64 tcg_imm = tcg_constant_i64(imm);
21
if (sub_op) {
22
gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
23
} else {
24
gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
25
}
26
- tcg_temp_free_i64(tcg_imm);
27
}
28
29
if (is_64bit) {
30
@@ -XXX,XX +XXX,XX @@ static void disas_add_sub_imm_with_tags(DisasContext *s, uint32_t insn)
31
tcg_rd = cpu_reg_sp(s, rd);
32
33
if (s->ata) {
34
- TCGv_i32 offset = tcg_const_i32(imm);
35
- TCGv_i32 tag_offset = tcg_const_i32(uimm4);
36
-
37
- gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset);
38
- tcg_temp_free_i32(tag_offset);
39
- tcg_temp_free_i32(offset);
40
+ gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn,
41
+ tcg_constant_i32(imm),
42
+ tcg_constant_i32(uimm4));
43
} else {
44
tcg_gen_addi_i64(tcg_rd, tcg_rn, imm);
45
gen_address_with_allocation_tag0(tcg_rd, tcg_rd);
46
--
47
2.25.1
diff view generated by jsdifflib
New patch
[PULL 12/54] target/arm: Use tcg_constant in disas_movw_imm
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-13-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 5 +----
9
1 file changed, 1 insertion(+), 4 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_movw_imm(DisasContext *s, uint32_t insn)
16
int opc = extract32(insn, 29, 2);
17
int pos = extract32(insn, 21, 2) << 4;
18
TCGv_i64 tcg_rd = cpu_reg(s, rd);
19
- TCGv_i64 tcg_imm;
20
21
if (!sf && (pos >= 32)) {
22
unallocated_encoding(s);
23
@@ -XXX,XX +XXX,XX @@ static void disas_movw_imm(DisasContext *s, uint32_t insn)
24
tcg_gen_movi_i64(tcg_rd, imm);
25
break;
26
case 3: /* MOVK */
27
- tcg_imm = tcg_const_i64(imm);
28
- tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16);
29
- tcg_temp_free_i64(tcg_imm);
30
+ tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_constant_i64(imm), pos, 16);
31
if (!sf) {
32
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
33
}
34
--
35
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/10] hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
[PULL 13/54] target/arm: Use tcg_constant in shift_reg_imm
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
In the previous commit we fixed a crash when the guest read a
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
register that pop from an empty FIFO.
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
By auditing the repository, we found another similar use with
5
Message-id: 20220426163043.100432-14-richard.henderson@linaro.org
6
an easy way to reproduce:
7
8
$ qemu-system-aarch64 -M xlnx-zcu102 -monitor stdio -S
9
QEMU 4.0.50 monitor - type 'help' for more information
10
(qemu) xp/b 0xfd4a0134
11
Aborted (core dumped)
12
13
(gdb) bt
14
#0 0x00007f6936dea57f in raise () at /lib64/libc.so.6
15
#1 0x00007f6936dd4895 in abort () at /lib64/libc.so.6
16
#2 0x0000561ad32975ec in xlnx_dp_aux_pop_rx_fifo (s=0x7f692babee70) at hw/display/xlnx_dp.c:431
17
#3 0x0000561ad3297dc0 in xlnx_dp_read (opaque=0x7f692babee70, offset=77, size=4) at hw/display/xlnx_dp.c:667
18
#4 0x0000561ad321b896 in memory_region_read_accessor (mr=0x7f692babf620, addr=308, value=0x7ffe05c1db88, size=4, shift=0, mask=4294967295, attrs=...) at memory.c:439
19
#5 0x0000561ad321bd70 in access_with_adjusted_size (addr=308, value=0x7ffe05c1db88, size=1, access_size_min=4, access_size_max=4, access_fn=0x561ad321b858 <memory_region_read_accessor>, mr=0x7f692babf620, attrs=...) at memory.c:569
20
#6 0x0000561ad321e9d5 in memory_region_dispatch_read1 (mr=0x7f692babf620, addr=308, pval=0x7ffe05c1db88, size=1, attrs=...) at memory.c:1420
21
#7 0x0000561ad321ea9d in memory_region_dispatch_read (mr=0x7f692babf620, addr=308, pval=0x7ffe05c1db88, size=1, attrs=...) at memory.c:1447
22
#8 0x0000561ad31bd742 in flatview_read_continue (fv=0x561ad69c04f0, addr=4249485620, attrs=..., buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", len=1, addr1=308, l=1, mr=0x7f692babf620) at exec.c:3385
23
#9 0x0000561ad31bd895 in flatview_read (fv=0x561ad69c04f0, addr=4249485620, attrs=..., buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", len=1) at exec.c:3423
24
#10 0x0000561ad31bd90b in address_space_read_full (as=0x561ad5bb3020, addr=4249485620, attrs=..., buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", len=1) at exec.c:3436
25
#11 0x0000561ad33b1c42 in address_space_read (len=1, buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", attrs=..., addr=4249485620, as=0x561ad5bb3020) at include/exec/memory.h:2131
26
#12 0x0000561ad33b1c42 in memory_dump (mon=0x561ad59c4530, count=1, format=120, wsize=1, addr=4249485620, is_physical=1) at monitor/misc.c:723
27
#13 0x0000561ad33b1fc1 in hmp_physical_memory_dump (mon=0x561ad59c4530, qdict=0x561ad6c6fd00) at monitor/misc.c:795
28
#14 0x0000561ad37b4a9f in handle_hmp_command (mon=0x561ad59c4530, cmdline=0x561ad59d0f22 "/b 0x00000000fd4a0134") at monitor/hmp.c:1082
29
30
Fix by checking the FIFO is not empty before popping from it.
31
32
The datasheet is not clear about the reset value of this register,
33
we choose to return '0'.
34
35
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
36
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
37
Message-id: 20190709113715.7761-4-philmd@redhat.com
38
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
39
---
7
---
40
hw/display/xlnx_dp.c | 15 +++++++++++----
8
target/arm/translate-a64.c | 6 +-----
41
1 file changed, 11 insertions(+), 4 deletions(-)
9
1 file changed, 1 insertion(+), 5 deletions(-)
42
10
43
diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
44
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/display/xlnx_dp.c
13
--- a/target/arm/translate-a64.c
46
+++ b/hw/display/xlnx_dp.c
14
+++ b/target/arm/translate-a64.c
47
@@ -XXX,XX +XXX,XX @@ static uint8_t xlnx_dp_aux_pop_rx_fifo(XlnxDPState *s)
15
@@ -XXX,XX +XXX,XX @@ static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,
48
uint8_t ret;
16
if (shift_i == 0) {
49
17
tcg_gen_mov_i64(dst, src);
50
if (fifo8_is_empty(&s->rx_fifo)) {
18
} else {
51
- DPRINTF("rx_fifo underflow..\n");
19
- TCGv_i64 shift_const;
52
- abort();
20
-
53
+ qemu_log_mask(LOG_GUEST_ERROR,
21
- shift_const = tcg_const_i64(shift_i);
54
+ "%s: Reading empty RX_FIFO\n",
22
- shift_reg(dst, src, sf, shift_type, shift_const);
55
+ __func__);
23
- tcg_temp_free_i64(shift_const);
56
+ /*
24
+ shift_reg(dst, src, sf, shift_type, tcg_constant_i64(shift_i));
57
+ * The datasheet is not clear about the reset value, it seems
58
+ * to be unspecified. We choose to return '0'.
59
+ */
60
+ ret = 0;
61
+ } else {
62
+ ret = fifo8_pop(&s->rx_fifo);
63
+ DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret);
64
}
25
}
65
- ret = fifo8_pop(&s->rx_fifo);
66
- DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret);
67
return ret;
68
}
26
}
69
27
70
--
28
--
71
2.20.1
29
2.25.1
72
73
diff view generated by jsdifflib
New patch
[PULL 14/54] target/arm: Use tcg_constant in disas_cond_select
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-15-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 3 +--
9
1 file changed, 1 insertion(+), 2 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_cond_select(DisasContext *s, uint32_t insn)
16
tcg_rd = cpu_reg(s, rd);
17
18
a64_test_cc(&c, cond);
19
- zero = tcg_const_i64(0);
20
+ zero = tcg_constant_i64(0);
21
22
if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) {
23
/* CSET & CSETM. */
24
@@ -XXX,XX +XXX,XX @@ static void disas_cond_select(DisasContext *s, uint32_t insn)
25
tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false);
26
}
27
28
- tcg_temp_free_i64(zero);
29
a64_free_cc(&c);
30
31
if (!sf) {
32
--
33
2.25.1
diff view generated by jsdifflib
New patch
[PULL 15/54] target/arm: Use tcg_constant in handle_{rev16,crc32}
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-16-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 7 ++-----
9
1 file changed, 2 insertions(+), 5 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void handle_rev16(DisasContext *s, unsigned int sf,
16
TCGv_i64 tcg_rd = cpu_reg(s, rd);
17
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
18
TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
19
- TCGv_i64 mask = tcg_const_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff);
20
+ TCGv_i64 mask = tcg_constant_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff);
21
22
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8);
23
tcg_gen_and_i64(tcg_rd, tcg_rn, mask);
24
@@ -XXX,XX +XXX,XX @@ static void handle_rev16(DisasContext *s, unsigned int sf,
25
tcg_gen_shli_i64(tcg_rd, tcg_rd, 8);
26
tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp);
27
28
- tcg_temp_free_i64(mask);
29
tcg_temp_free_i64(tcg_tmp);
30
}
31
32
@@ -XXX,XX +XXX,XX @@ static void handle_crc32(DisasContext *s,
33
}
34
35
tcg_acc = cpu_reg(s, rn);
36
- tcg_bytes = tcg_const_i32(1 << sz);
37
+ tcg_bytes = tcg_constant_i32(1 << sz);
38
39
if (crc32c) {
40
gen_helper_crc32c_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
41
} else {
42
gen_helper_crc32_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
43
}
44
-
45
- tcg_temp_free_i32(tcg_bytes);
46
}
47
48
/* Data-processing (2 source)
49
--
50
2.25.1
diff view generated by jsdifflib
New patch
[PULL 16/54] target/arm: Use tcg_constant in disas_data_proc_2src
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Existing temp usage treats t1 as both zero and as a
4
temporary. Rearrange to only require one temporary,
5
so remove t1 and rename t2.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220426163043.100432-17-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-a64.c | 12 +++++-------
13
1 file changed, 5 insertions(+), 7 deletions(-)
14
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
19
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
20
if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
21
goto do_unallocated;
22
} else {
23
- TCGv_i64 t1 = tcg_const_i64(1);
24
- TCGv_i64 t2 = tcg_temp_new_i64();
25
+ TCGv_i64 t = tcg_temp_new_i64();
26
27
- tcg_gen_extract_i64(t2, cpu_reg_sp(s, rn), 56, 4);
28
- tcg_gen_shl_i64(t1, t1, t2);
29
- tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t1);
30
+ tcg_gen_extract_i64(t, cpu_reg_sp(s, rn), 56, 4);
31
+ tcg_gen_shl_i64(t, tcg_constant_i64(1), t);
32
+ tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t);
33
34
- tcg_temp_free_i64(t1);
35
- tcg_temp_free_i64(t2);
36
+ tcg_temp_free_i64(t);
37
}
38
break;
39
case 8: /* LSLV */
40
--
41
2.25.1
diff view generated by jsdifflib
New patch
[PULL 17/54] target/arm: Use tcg_constant in disas_fp*
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-18-richard.henderson@linaro.org
6
[PMM: Restore incorrectly removed free of t_false in disas_fp_csel()]
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
target/arm/translate-a64.c | 23 +++++++----------------
10
1 file changed, 7 insertions(+), 16 deletions(-)
11
12
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/translate-a64.c
15
+++ b/target/arm/translate-a64.c
16
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, int size,
17
18
tcg_vn = read_fp_dreg(s, rn);
19
if (cmp_with_zero) {
20
- tcg_vm = tcg_const_i64(0);
21
+ tcg_vm = tcg_constant_i64(0);
22
} else {
23
tcg_vm = read_fp_dreg(s, rm);
24
}
25
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
26
static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
27
{
28
unsigned int mos, type, rm, cond, rn, op, nzcv;
29
- TCGv_i64 tcg_flags;
30
TCGLabel *label_continue = NULL;
31
int size;
32
33
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
34
label_continue = gen_new_label();
35
arm_gen_test_cc(cond, label_match);
36
/* nomatch: */
37
- tcg_flags = tcg_const_i64(nzcv << 28);
38
- gen_set_nzcv(tcg_flags);
39
- tcg_temp_free_i64(tcg_flags);
40
+ gen_set_nzcv(tcg_constant_i64(nzcv << 28));
41
tcg_gen_br(label_continue);
42
gen_set_label(label_match);
43
}
44
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
45
static void disas_fp_csel(DisasContext *s, uint32_t insn)
46
{
47
unsigned int mos, type, rm, cond, rn, rd;
48
- TCGv_i64 t_true, t_false, t_zero;
49
+ TCGv_i64 t_true, t_false;
50
DisasCompare64 c;
51
MemOp sz;
52
53
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
54
read_vec_element(s, t_false, rm, 0, sz);
55
56
a64_test_cc(&c, cond);
57
- t_zero = tcg_const_i64(0);
58
- tcg_gen_movcond_i64(c.cond, t_true, c.value, t_zero, t_true, t_false);
59
- tcg_temp_free_i64(t_zero);
60
+ tcg_gen_movcond_i64(c.cond, t_true, c.value, tcg_constant_i64(0),
61
+ t_true, t_false);
62
tcg_temp_free_i64(t_false);
63
a64_free_cc(&c);
64
65
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
66
int type = extract32(insn, 22, 2);
67
int mos = extract32(insn, 29, 3);
68
uint64_t imm;
69
- TCGv_i64 tcg_res;
70
MemOp sz;
71
72
if (mos || imm5) {
73
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
74
}
75
76
imm = vfp_expand_imm(sz, imm8);
77
-
78
- tcg_res = tcg_const_i64(imm);
79
- write_fp_dreg(s, rd, tcg_res);
80
- tcg_temp_free_i64(tcg_res);
81
+ write_fp_dreg(s, rd, tcg_constant_i64(imm));
82
}
83
84
/* Handle floating point <=> fixed point conversions. Note that we can
85
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
86
87
tcg_fpstatus = fpstatus_ptr(type == 3 ? FPST_FPCR_F16 : FPST_FPCR);
88
89
- tcg_shift = tcg_const_i32(64 - scale);
90
+ tcg_shift = tcg_constant_i32(64 - scale);
91
92
if (itof) {
93
TCGv_i64 tcg_int = cpu_reg(s, rn);
94
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
95
}
96
97
tcg_temp_free_ptr(tcg_fpstatus);
98
- tcg_temp_free_i32(tcg_shift);
99
}
100
101
/* Floating point <-> fixed point conversions
102
--
103
2.25.1
diff view generated by jsdifflib
New patch
[PULL 18/54] target/arm: Use tcg_constant in simd shift expanders
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-19-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 21 +++++----------------
9
1 file changed, 5 insertions(+), 16 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
16
/* Deal with the rounding step */
17
if (round) {
18
if (extended_result) {
19
- TCGv_i64 tcg_zero = tcg_const_i64(0);
20
+ TCGv_i64 tcg_zero = tcg_constant_i64(0);
21
if (!is_u) {
22
/* take care of sign extending tcg_res */
23
tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63);
24
@@ -XXX,XX +XXX,XX @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
25
tcg_src, tcg_zero,
26
tcg_rnd, tcg_zero);
27
}
28
- tcg_temp_free_i64(tcg_zero);
29
} else {
30
tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd);
31
}
32
@@ -XXX,XX +XXX,XX @@ static void handle_scalar_simd_shri(DisasContext *s,
33
}
34
35
if (round) {
36
- uint64_t round_const = 1ULL << (shift - 1);
37
- tcg_round = tcg_const_i64(round_const);
38
+ tcg_round = tcg_constant_i64(1ULL << (shift - 1));
39
} else {
40
tcg_round = NULL;
41
}
42
@@ -XXX,XX +XXX,XX @@ static void handle_scalar_simd_shri(DisasContext *s,
43
44
tcg_temp_free_i64(tcg_rn);
45
tcg_temp_free_i64(tcg_rd);
46
- if (round) {
47
- tcg_temp_free_i64(tcg_round);
48
- }
49
}
50
51
/* SHL/SLI - Scalar shift left */
52
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
53
tcg_final = tcg_const_i64(0);
54
55
if (round) {
56
- uint64_t round_const = 1ULL << (shift - 1);
57
- tcg_round = tcg_const_i64(round_const);
58
+ tcg_round = tcg_constant_i64(1ULL << (shift - 1));
59
} else {
60
tcg_round = NULL;
61
}
62
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
63
write_vec_element(s, tcg_final, rd, 1, MO_64);
64
}
65
66
- if (round) {
67
- tcg_temp_free_i64(tcg_round);
68
- }
69
tcg_temp_free_i64(tcg_rn);
70
tcg_temp_free_i64(tcg_rd);
71
tcg_temp_free_i32(tcg_rd_narrowed);
72
@@ -XXX,XX +XXX,XX @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
73
}
74
75
if (size == 3) {
76
- TCGv_i64 tcg_shift = tcg_const_i64(shift);
77
+ TCGv_i64 tcg_shift = tcg_constant_i64(shift);
78
static NeonGenTwo64OpEnvFn * const fns[2][2] = {
79
{ gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 },
80
{ NULL, gen_helper_neon_qshl_u64 },
81
@@ -XXX,XX +XXX,XX @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
82
83
tcg_temp_free_i64(tcg_op);
84
}
85
- tcg_temp_free_i64(tcg_shift);
86
clear_vec_high(s, is_q, rd);
87
} else {
88
- TCGv_i32 tcg_shift = tcg_const_i32(shift);
89
+ TCGv_i32 tcg_shift = tcg_constant_i32(shift);
90
static NeonGenTwoOpEnvFn * const fns[2][2][3] = {
91
{
92
{ gen_helper_neon_qshl_s8,
93
@@ -XXX,XX +XXX,XX @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
94
95
tcg_temp_free_i32(tcg_op);
96
}
97
- tcg_temp_free_i32(tcg_shift);
98
99
if (!scalar) {
100
clear_vec_high(s, is_q, rd);
101
--
102
2.25.1
diff view generated by jsdifflib
New patch
[PULL 19/54] target/arm: Use tcg_constant in simd fp/int conversion
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-20-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 26 ++++++--------------------
9
1 file changed, 6 insertions(+), 20 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
16
int pass;
17
18
if (fracbits || size == MO_64) {
19
- tcg_shift = tcg_const_i32(fracbits);
20
+ tcg_shift = tcg_constant_i32(fracbits);
21
}
22
23
if (size == MO_64) {
24
@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
25
}
26
27
tcg_temp_free_ptr(tcg_fpst);
28
- if (tcg_shift) {
29
- tcg_temp_free_i32(tcg_shift);
30
- }
31
32
clear_vec_high(s, elements << size == 16, rd);
33
}
34
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
35
tcg_fpstatus = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
36
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
37
fracbits = (16 << size) - immhb;
38
- tcg_shift = tcg_const_i32(fracbits);
39
+ tcg_shift = tcg_constant_i32(fracbits);
40
41
if (size == MO_64) {
42
int maxpass = is_scalar ? 1 : 2;
43
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
44
}
45
}
46
47
- tcg_temp_free_i32(tcg_shift);
48
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
49
tcg_temp_free_ptr(tcg_fpstatus);
50
tcg_temp_free_i32(tcg_rmode);
51
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
52
case 0x1c: /* FCVTAS */
53
case 0x3a: /* FCVTPS */
54
case 0x3b: /* FCVTZS */
55
- {
56
- TCGv_i32 tcg_shift = tcg_const_i32(0);
57
- gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
58
- tcg_temp_free_i32(tcg_shift);
59
+ gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_constant_i32(0), tcg_fpstatus);
60
break;
61
- }
62
case 0x5a: /* FCVTNU */
63
case 0x5b: /* FCVTMU */
64
case 0x5c: /* FCVTAU */
65
case 0x7a: /* FCVTPU */
66
case 0x7b: /* FCVTZU */
67
- {
68
- TCGv_i32 tcg_shift = tcg_const_i32(0);
69
- gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
70
- tcg_temp_free_i32(tcg_shift);
71
+ gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_constant_i32(0), tcg_fpstatus);
72
break;
73
- }
74
case 0x18: /* FRINTN */
75
case 0x19: /* FRINTM */
76
case 0x38: /* FRINTP */
77
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
78
79
if (is_double) {
80
TCGv_i64 tcg_op = tcg_temp_new_i64();
81
- TCGv_i64 tcg_zero = tcg_const_i64(0);
82
+ TCGv_i64 tcg_zero = tcg_constant_i64(0);
83
TCGv_i64 tcg_res = tcg_temp_new_i64();
84
NeonGenTwoDoubleOpFn *genfn;
85
bool swap = false;
86
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
87
write_vec_element(s, tcg_res, rd, pass, MO_64);
88
}
89
tcg_temp_free_i64(tcg_res);
90
- tcg_temp_free_i64(tcg_zero);
91
tcg_temp_free_i64(tcg_op);
92
93
clear_vec_high(s, !is_scalar, rd);
94
} else {
95
TCGv_i32 tcg_op = tcg_temp_new_i32();
96
- TCGv_i32 tcg_zero = tcg_const_i32(0);
97
+ TCGv_i32 tcg_zero = tcg_constant_i32(0);
98
TCGv_i32 tcg_res = tcg_temp_new_i32();
99
NeonGenTwoSingleOpFn *genfn;
100
bool swap = false;
101
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
102
}
103
}
104
tcg_temp_free_i32(tcg_res);
105
- tcg_temp_free_i32(tcg_zero);
106
tcg_temp_free_i32(tcg_op);
107
if (!is_scalar) {
108
clear_vec_high(s, is_q, rd);
109
--
110
2.25.1
diff view generated by jsdifflib
New patch
[PULL 20/54] target/arm: Use tcg_constant in 2misc expanders
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-21-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 40 ++++++++++----------------------------
9
1 file changed, 10 insertions(+), 30 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
16
int passes = scalar ? 1 : 2;
17
18
if (scalar) {
19
- tcg_res[1] = tcg_const_i32(0);
20
+ tcg_res[1] = tcg_constant_i32(0);
21
}
22
23
for (pass = 0; pass < passes; pass++) {
24
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
25
}
26
27
if (is_scalar) {
28
- TCGv_i64 tcg_zero = tcg_const_i64(0);
29
- write_vec_element(s, tcg_zero, rd, 0, MO_64);
30
- tcg_temp_free_i64(tcg_zero);
31
+ write_vec_element(s, tcg_constant_i64(0), rd, 0, MO_64);
32
}
33
write_vec_element_i32(s, tcg_rd, rd, pass, MO_32);
34
}
35
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
36
case 0x1c: /* FCVTAS */
37
case 0x3a: /* FCVTPS */
38
case 0x3b: /* FCVTZS */
39
- {
40
- TCGv_i32 tcg_shift = tcg_const_i32(0);
41
- gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
42
- tcg_temp_free_i32(tcg_shift);
43
+ gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_constant_i32(0),
44
+ tcg_fpstatus);
45
break;
46
- }
47
case 0x5a: /* FCVTNU */
48
case 0x5b: /* FCVTMU */
49
case 0x5c: /* FCVTAU */
50
case 0x7a: /* FCVTPU */
51
case 0x7b: /* FCVTZU */
52
- {
53
- TCGv_i32 tcg_shift = tcg_const_i32(0);
54
- gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
55
- tcg_temp_free_i32(tcg_shift);
56
+ gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_constant_i32(0),
57
+ tcg_fpstatus);
58
break;
59
- }
60
default:
61
g_assert_not_reached();
62
}
63
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
64
read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64);
65
66
if (round) {
67
- uint64_t round_const = 1ULL << (shift - 1);
68
- tcg_round = tcg_const_i64(round_const);
69
+ tcg_round = tcg_constant_i64(1ULL << (shift - 1));
70
} else {
71
tcg_round = NULL;
72
}
73
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
74
} else {
75
write_vec_element(s, tcg_final, rd, 1, MO_64);
76
}
77
- if (round) {
78
- tcg_temp_free_i64(tcg_round);
79
- }
80
tcg_temp_free_i64(tcg_rn);
81
tcg_temp_free_i64(tcg_rd);
82
tcg_temp_free_i64(tcg_final);
83
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
84
}
85
}
86
if (!is_q) {
87
- tcg_res[1] = tcg_const_i64(0);
88
+ tcg_res[1] = tcg_constant_i64(0);
89
}
90
for (pass = 0; pass < 2; pass++) {
91
write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
92
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
93
case 0x1c: /* FCVTAS */
94
case 0x3a: /* FCVTPS */
95
case 0x3b: /* FCVTZS */
96
- {
97
- TCGv_i32 tcg_shift = tcg_const_i32(0);
98
gen_helper_vfp_tosls(tcg_res, tcg_op,
99
- tcg_shift, tcg_fpstatus);
100
- tcg_temp_free_i32(tcg_shift);
101
+ tcg_constant_i32(0), tcg_fpstatus);
102
break;
103
- }
104
case 0x5a: /* FCVTNU */
105
case 0x5b: /* FCVTMU */
106
case 0x5c: /* FCVTAU */
107
case 0x7a: /* FCVTPU */
108
case 0x7b: /* FCVTZU */
109
- {
110
- TCGv_i32 tcg_shift = tcg_const_i32(0);
111
gen_helper_vfp_touls(tcg_res, tcg_op,
112
- tcg_shift, tcg_fpstatus);
113
- tcg_temp_free_i32(tcg_shift);
114
+ tcg_constant_i32(0), tcg_fpstatus);
115
break;
116
- }
117
case 0x18: /* FRINTN */
118
case 0x19: /* FRINTM */
119
case 0x38: /* FRINTP */
120
--
121
2.25.1
diff view generated by jsdifflib
New patch
[PULL 21/54] target/arm: Use tcg_constant in balance of translate-a64.c
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Finish conversion of the file to tcg_constant_*.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20220426163043.100432-22-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-a64.c | 20 ++++++++------------
11
1 file changed, 8 insertions(+), 12 deletions(-)
12
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
16
+++ b/target/arm/translate-a64.c
17
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
18
}
19
20
if (is_scalar) {
21
- tcg_res[1] = tcg_const_i64(0);
22
+ tcg_res[1] = tcg_constant_i64(0);
23
}
24
25
for (pass = 0; pass < 2; pass++) {
26
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)
27
tcg_op2 = tcg_temp_new_i32();
28
tcg_op3 = tcg_temp_new_i32();
29
tcg_res = tcg_temp_new_i32();
30
- tcg_zero = tcg_const_i32(0);
31
+ tcg_zero = tcg_constant_i32(0);
32
33
read_vec_element_i32(s, tcg_op1, rn, 3, MO_32);
34
read_vec_element_i32(s, tcg_op2, rm, 3, MO_32);
35
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)
36
tcg_temp_free_i32(tcg_op2);
37
tcg_temp_free_i32(tcg_op3);
38
tcg_temp_free_i32(tcg_res);
39
- tcg_temp_free_i32(tcg_zero);
40
}
41
}
42
43
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
44
gen_helper_yield(cpu_env);
45
break;
46
case DISAS_WFI:
47
- {
48
- /* This is a special case because we don't want to just halt the CPU
49
- * if trying to debug across a WFI.
50
+ /*
51
+ * This is a special case because we don't want to just halt
52
+ * the CPU if trying to debug across a WFI.
53
*/
54
- TCGv_i32 tmp = tcg_const_i32(4);
55
-
56
gen_a64_set_pc_im(dc->base.pc_next);
57
- gen_helper_wfi(cpu_env, tmp);
58
- tcg_temp_free_i32(tmp);
59
- /* The helper doesn't necessarily throw an exception, but we
60
+ gen_helper_wfi(cpu_env, tcg_constant_i32(4));
61
+ /*
62
+ * The helper doesn't necessarily throw an exception, but we
63
* must go back to the main loop to check for interrupts anyway.
64
*/
65
tcg_gen_exit_tb(NULL, 0);
66
break;
67
}
68
- }
69
}
70
}
71
72
--
73
2.25.1
diff view generated by jsdifflib
New patch
[PULL 22/54] target/arm: Use tcg_constant for aa32 exceptions
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-23-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 32 +++++++-------------------------
9
1 file changed, 7 insertions(+), 25 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static void store_sp_checked(DisasContext *s, TCGv_i32 var)
16
17
void gen_set_cpsr(TCGv_i32 var, uint32_t mask)
18
{
19
- TCGv_i32 tmp_mask = tcg_const_i32(mask);
20
- gen_helper_cpsr_write(cpu_env, var, tmp_mask);
21
- tcg_temp_free_i32(tmp_mask);
22
+ gen_helper_cpsr_write(cpu_env, var, tcg_constant_i32(mask));
23
}
24
25
static void gen_rebuild_hflags(DisasContext *s, bool new_el)
26
@@ -XXX,XX +XXX,XX @@ static void gen_rebuild_hflags(DisasContext *s, bool new_el)
27
28
static void gen_exception_internal(int excp)
29
{
30
- TCGv_i32 tcg_excp = tcg_const_i32(excp);
31
-
32
assert(excp_is_internal(excp));
33
- gen_helper_exception_internal(cpu_env, tcg_excp);
34
- tcg_temp_free_i32(tcg_excp);
35
+ gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp));
36
}
37
38
static void gen_singlestep_exception(DisasContext *s)
39
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
40
/* As with HVC, we may take an exception either before or after
41
* the insn executes.
42
*/
43
- TCGv_i32 tmp;
44
-
45
gen_set_pc_im(s, s->pc_curr);
46
- tmp = tcg_const_i32(syn_aa32_smc());
47
- gen_helper_pre_smc(cpu_env, tmp);
48
- tcg_temp_free_i32(tmp);
49
+ gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa32_smc()));
50
gen_set_pc_im(s, s->base.pc_next);
51
s->base.is_jmp = DISAS_SMC;
52
}
53
@@ -XXX,XX +XXX,XX @@ void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
54
55
static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
56
{
57
- TCGv_i32 tcg_syn;
58
-
59
gen_set_condexec(s);
60
gen_set_pc_im(s, s->pc_curr);
61
- tcg_syn = tcg_const_i32(syn);
62
- gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
63
- tcg_temp_free_i32(tcg_syn);
64
+ gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syn));
65
s->base.is_jmp = DISAS_NORETURN;
66
}
67
68
@@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s)
69
static void gen_exception_el(DisasContext *s, int excp, uint32_t syn,
70
TCGv_i32 tcg_el)
71
{
72
- TCGv_i32 tcg_excp;
73
- TCGv_i32 tcg_syn;
74
-
75
gen_set_condexec(s);
76
gen_set_pc_im(s, s->pc_curr);
77
- tcg_excp = tcg_const_i32(excp);
78
- tcg_syn = tcg_const_i32(syn);
79
- gen_helper_exception_with_syndrome(cpu_env, tcg_excp, tcg_syn, tcg_el);
80
- tcg_temp_free_i32(tcg_syn);
81
- tcg_temp_free_i32(tcg_excp);
82
+ gen_helper_exception_with_syndrome(cpu_env,
83
+ tcg_constant_i32(excp),
84
+ tcg_constant_i32(syn), tcg_el);
85
s->base.is_jmp = DISAS_NORETURN;
86
}
87
88
--
89
2.25.1
diff view generated by jsdifflib
New patch
[PULL 23/54] target/arm: Use tcg_constant for disas_iwmmxt_insn
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-24-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 25 ++++++++++---------------
9
1 file changed, 10 insertions(+), 15 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
16
gen_op_iwmmxt_movq_M0_wRn(wrd);
17
switch ((insn >> 6) & 3) {
18
case 0:
19
- tmp2 = tcg_const_i32(0xff);
20
- tmp3 = tcg_const_i32((insn & 7) << 3);
21
+ tmp2 = tcg_constant_i32(0xff);
22
+ tmp3 = tcg_constant_i32((insn & 7) << 3);
23
break;
24
case 1:
25
- tmp2 = tcg_const_i32(0xffff);
26
- tmp3 = tcg_const_i32((insn & 3) << 4);
27
+ tmp2 = tcg_constant_i32(0xffff);
28
+ tmp3 = tcg_constant_i32((insn & 3) << 4);
29
break;
30
case 2:
31
- tmp2 = tcg_const_i32(0xffffffff);
32
- tmp3 = tcg_const_i32((insn & 1) << 5);
33
+ tmp2 = tcg_constant_i32(0xffffffff);
34
+ tmp3 = tcg_constant_i32((insn & 1) << 5);
35
break;
36
default:
37
- tmp2 = NULL;
38
- tmp3 = NULL;
39
+ g_assert_not_reached();
40
}
41
gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
42
- tcg_temp_free_i32(tmp3);
43
- tcg_temp_free_i32(tmp2);
44
tcg_temp_free_i32(tmp);
45
gen_op_iwmmxt_movq_wRn_M0(wrd);
46
gen_op_iwmmxt_set_mup();
47
@@ -XXX,XX +XXX,XX @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
48
rd0 = (insn >> 16) & 0xf;
49
rd1 = (insn >> 0) & 0xf;
50
gen_op_iwmmxt_movq_M0_wRn(rd0);
51
- tmp = tcg_const_i32((insn >> 20) & 3);
52
iwmmxt_load_reg(cpu_V1, rd1);
53
- gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
54
- tcg_temp_free_i32(tmp);
55
+ gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1,
56
+ tcg_constant_i32((insn >> 20) & 3));
57
gen_op_iwmmxt_movq_wRn_M0(wrd);
58
gen_op_iwmmxt_set_mup();
59
break;
60
@@ -XXX,XX +XXX,XX @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
61
wrd = (insn >> 12) & 0xf;
62
rd0 = (insn >> 16) & 0xf;
63
gen_op_iwmmxt_movq_M0_wRn(rd0);
64
- tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
65
+ tmp = tcg_constant_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
66
gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp);
67
- tcg_temp_free_i32(tmp);
68
gen_op_iwmmxt_movq_wRn_M0(wrd);
69
gen_op_iwmmxt_set_mup();
70
gen_op_iwmmxt_set_cup();
71
--
72
2.25.1
diff view generated by jsdifflib
New patch
[PULL 24/54] target/arm: Use tcg_constant for gen_{msr,mrs}
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-25-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 22 +++++++++-------------
9
1 file changed, 9 insertions(+), 13 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
16
tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), 1);
17
tcg_gen_addi_i32(tcg_el, tcg_el, 3);
18
} else {
19
- tcg_el = tcg_const_i32(3);
20
+ tcg_el = tcg_constant_i32(3);
21
}
22
23
gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el);
24
@@ -XXX,XX +XXX,XX @@ undef:
25
26
static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
27
{
28
- TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno;
29
+ TCGv_i32 tcg_reg;
30
int tgtmode = 0, regno = 0;
31
32
if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, &regno)) {
33
@@ -XXX,XX +XXX,XX @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
34
gen_set_condexec(s);
35
gen_set_pc_im(s, s->pc_curr);
36
tcg_reg = load_reg(s, rn);
37
- tcg_tgtmode = tcg_const_i32(tgtmode);
38
- tcg_regno = tcg_const_i32(regno);
39
- gen_helper_msr_banked(cpu_env, tcg_reg, tcg_tgtmode, tcg_regno);
40
- tcg_temp_free_i32(tcg_tgtmode);
41
- tcg_temp_free_i32(tcg_regno);
42
+ gen_helper_msr_banked(cpu_env, tcg_reg,
43
+ tcg_constant_i32(tgtmode),
44
+ tcg_constant_i32(regno));
45
tcg_temp_free_i32(tcg_reg);
46
s->base.is_jmp = DISAS_UPDATE_EXIT;
47
}
48
49
static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
50
{
51
- TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno;
52
+ TCGv_i32 tcg_reg;
53
int tgtmode = 0, regno = 0;
54
55
if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, &regno)) {
56
@@ -XXX,XX +XXX,XX @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
57
gen_set_condexec(s);
58
gen_set_pc_im(s, s->pc_curr);
59
tcg_reg = tcg_temp_new_i32();
60
- tcg_tgtmode = tcg_const_i32(tgtmode);
61
- tcg_regno = tcg_const_i32(regno);
62
- gen_helper_mrs_banked(tcg_reg, cpu_env, tcg_tgtmode, tcg_regno);
63
- tcg_temp_free_i32(tcg_tgtmode);
64
- tcg_temp_free_i32(tcg_regno);
65
+ gen_helper_mrs_banked(tcg_reg, cpu_env,
66
+ tcg_constant_i32(tgtmode),
67
+ tcg_constant_i32(regno));
68
store_reg(s, rn, tcg_reg);
69
s->base.is_jmp = DISAS_UPDATE_EXIT;
70
}
71
--
72
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/10] pl031: Correctly migrate state when using -rtc clock=host
[PULL 25/54] target/arm: Use tcg_constant for vector shift expanders
1
The PL031 RTC tracks the difference between the guest RTC
1
From: Richard Henderson <richard.henderson@linaro.org>
2
and the host RTC using a tick_offset field. For migration,
3
however, we currently always migrate the offset between
4
the guest and the vm_clock, even if the RTC clock is not
5
the same as the vm_clock; this was an attempt to retain
6
migration backwards compatibility.
7
2
8
Unfortunately this results in the RTC behaving oddly across
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
a VM state save and restore -- since the VM clock stands still
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
across save-then-restore, regardless of how much real world
5
Message-id: 20220426163043.100432-26-richard.henderson@linaro.org
11
time has elapsed, the guest RTC ends up out of sync with the
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
host RTC in the restored VM.
7
---
8
target/arm/translate.c | 27 +++++++++------------------
9
1 file changed, 9 insertions(+), 18 deletions(-)
13
10
14
Fix this by migrating the raw tick_offset. To retain migration
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
compatibility as far as possible, we have a new property
16
migrate-tick-offset; by default this is 'true' and we will
17
migrate the true tick offset in a new subsection; if the
18
incoming data has no subsection we fall back to the old
19
vm_clock-based offset information, so old->new migration
20
compatibility is preserved. For complete new->old migration
21
compatibility, the property is set to 'false' for 4.0 and
22
earlier machine types (this will only affect 'virt-4.0'
23
and below, as none of the other pl031-using machines are
24
versioned).
25
26
Reported-by: Russell King <rmk@armlinux.org.uk>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
29
Message-id: 20190709143912.28905-1-peter.maydell@linaro.org
30
---
31
include/hw/timer/pl031.h | 2 +
32
hw/core/machine.c | 1 +
33
hw/timer/pl031.c | 92 ++++++++++++++++++++++++++++++++++++++--
34
3 files changed, 91 insertions(+), 4 deletions(-)
35
36
diff --git a/include/hw/timer/pl031.h b/include/hw/timer/pl031.h
37
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/timer/pl031.h
13
--- a/target/arm/translate.c
39
+++ b/include/hw/timer/pl031.h
14
+++ b/target/arm/translate.c
40
@@ -XXX,XX +XXX,XX @@ typedef struct PL031State {
15
@@ -XXX,XX +XXX,XX @@ void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
41
*/
16
} \
42
uint32_t tick_offset_vmstate;
17
static void gen_##NAME##0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) \
43
uint32_t tick_offset;
18
{ \
44
+ bool tick_offset_migrated;
19
- TCGv_vec zero = tcg_const_zeros_vec_matching(d); \
45
+ bool migrate_tick_offset;
20
+ TCGv_vec zero = tcg_constant_vec_matching(d, vece, 0); \
46
21
tcg_gen_cmp_vec(COND, vece, d, a, zero); \
47
uint32_t mr;
22
- tcg_temp_free_vec(zero); \
48
uint32_t lr;
23
} \
49
diff --git a/hw/core/machine.c b/hw/core/machine.c
24
void gen_gvec_##NAME##0(unsigned vece, uint32_t d, uint32_t m, \
50
index XXXXXXX..XXXXXXX 100644
25
uint32_t opr_sz, uint32_t max_sz) \
51
--- a/hw/core/machine.c
26
@@ -XXX,XX +XXX,XX @@ void gen_ushl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
52
+++ b/hw/core/machine.c
27
TCGv_i32 rval = tcg_temp_new_i32();
53
@@ -XXX,XX +XXX,XX @@ GlobalProperty hw_compat_4_0[] = {
28
TCGv_i32 lsh = tcg_temp_new_i32();
54
{ "virtio-gpu-pci", "edid", "false" },
29
TCGv_i32 rsh = tcg_temp_new_i32();
55
{ "virtio-device", "use-started", "false" },
30
- TCGv_i32 zero = tcg_const_i32(0);
56
{ "virtio-balloon-device", "qemu-4-0-config-size", "true" },
31
- TCGv_i32 max = tcg_const_i32(32);
57
+ { "pl031", "migrate-tick-offset", "false" },
32
+ TCGv_i32 zero = tcg_constant_i32(0);
58
};
33
+ TCGv_i32 max = tcg_constant_i32(32);
59
const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0);
34
60
35
/*
61
diff --git a/hw/timer/pl031.c b/hw/timer/pl031.c
36
* Rely on the TCG guarantee that out of range shifts produce
62
index XXXXXXX..XXXXXXX 100644
37
@@ -XXX,XX +XXX,XX @@ void gen_ushl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
63
--- a/hw/timer/pl031.c
38
tcg_temp_free_i32(rval);
64
+++ b/hw/timer/pl031.c
39
tcg_temp_free_i32(lsh);
65
@@ -XXX,XX +XXX,XX @@ static int pl031_pre_save(void *opaque)
40
tcg_temp_free_i32(rsh);
66
{
41
- tcg_temp_free_i32(zero);
67
PL031State *s = opaque;
42
- tcg_temp_free_i32(max);
68
69
- /* tick_offset is base_time - rtc_clock base time. Instead, we want to
70
- * store the base time relative to the QEMU_CLOCK_VIRTUAL for backwards-compatibility. */
71
+ /*
72
+ * The PL031 device model code uses the tick_offset field, which is
73
+ * the offset between what the guest RTC should read and what the
74
+ * QEMU rtc_clock reads:
75
+ * guest_rtc = rtc_clock + tick_offset
76
+ * and so
77
+ * tick_offset = guest_rtc - rtc_clock
78
+ *
79
+ * We want to migrate this offset, which sounds straightforward.
80
+ * Unfortunately older versions of QEMU migrated a conversion of this
81
+ * offset into an offset from the vm_clock. (This was in turn an
82
+ * attempt to be compatible with even older QEMU versions, but it
83
+ * has incorrect behaviour if the rtc_clock is not the same as the
84
+ * vm_clock.) So we put the actual tick_offset into a migration
85
+ * subsection, and the backwards-compatible time-relative-to-vm_clock
86
+ * in the main migration state.
87
+ *
88
+ * Calculate base time relative to QEMU_CLOCK_VIRTUAL:
89
+ */
90
int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
91
s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND;
92
93
return 0;
94
}
43
}
95
44
96
+static int pl031_pre_load(void *opaque)
45
void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
97
+{
46
@@ -XXX,XX +XXX,XX @@ void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
98
+ PL031State *s = opaque;
47
TCGv_i64 rval = tcg_temp_new_i64();
99
+
48
TCGv_i64 lsh = tcg_temp_new_i64();
100
+ s->tick_offset_migrated = false;
49
TCGv_i64 rsh = tcg_temp_new_i64();
101
+ return 0;
50
- TCGv_i64 zero = tcg_const_i64(0);
102
+}
51
- TCGv_i64 max = tcg_const_i64(64);
103
+
52
+ TCGv_i64 zero = tcg_constant_i64(0);
104
static int pl031_post_load(void *opaque, int version_id)
53
+ TCGv_i64 max = tcg_constant_i64(64);
105
{
54
106
PL031State *s = opaque;
55
/*
107
56
* Rely on the TCG guarantee that out of range shifts produce
108
- int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
57
@@ -XXX,XX +XXX,XX @@ void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
109
- s->tick_offset = s->tick_offset_vmstate - delta / NANOSECONDS_PER_SECOND;
58
tcg_temp_free_i64(rval);
110
+ /*
59
tcg_temp_free_i64(lsh);
111
+ * If we got the tick_offset subsection, then we can just use
60
tcg_temp_free_i64(rsh);
112
+ * the value in that. Otherwise the source is an older QEMU and
61
- tcg_temp_free_i64(zero);
113
+ * has given us the offset from the vm_clock; convert it back to
62
- tcg_temp_free_i64(max);
114
+ * an offset from the rtc_clock. This will cause time to incorrectly
115
+ * go backwards compared to the host RTC, but this is unavoidable.
116
+ */
117
+
118
+ if (!s->tick_offset_migrated) {
119
+ int64_t delta = qemu_clock_get_ns(rtc_clock) -
120
+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
121
+ s->tick_offset = s->tick_offset_vmstate -
122
+ delta / NANOSECONDS_PER_SECOND;
123
+ }
124
pl031_set_alarm(s);
125
return 0;
126
}
63
}
127
64
128
+static int pl031_tick_offset_post_load(void *opaque, int version_id)
65
static void gen_ushl_vec(unsigned vece, TCGv_vec dst,
129
+{
66
@@ -XXX,XX +XXX,XX @@ void gen_sshl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
130
+ PL031State *s = opaque;
67
TCGv_i32 rval = tcg_temp_new_i32();
131
+
68
TCGv_i32 lsh = tcg_temp_new_i32();
132
+ s->tick_offset_migrated = true;
69
TCGv_i32 rsh = tcg_temp_new_i32();
133
+ return 0;
70
- TCGv_i32 zero = tcg_const_i32(0);
134
+}
71
- TCGv_i32 max = tcg_const_i32(31);
135
+
72
+ TCGv_i32 zero = tcg_constant_i32(0);
136
+static bool pl031_tick_offset_needed(void *opaque)
73
+ TCGv_i32 max = tcg_constant_i32(31);
137
+{
74
138
+ PL031State *s = opaque;
75
/*
139
+
76
* Rely on the TCG guarantee that out of range shifts produce
140
+ return s->migrate_tick_offset;
77
@@ -XXX,XX +XXX,XX @@ void gen_sshl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
141
+}
78
tcg_temp_free_i32(rval);
142
+
79
tcg_temp_free_i32(lsh);
143
+static const VMStateDescription vmstate_pl031_tick_offset = {
80
tcg_temp_free_i32(rsh);
144
+ .name = "pl031/tick-offset",
81
- tcg_temp_free_i32(zero);
145
+ .version_id = 1,
82
- tcg_temp_free_i32(max);
146
+ .minimum_version_id = 1,
147
+ .needed = pl031_tick_offset_needed,
148
+ .post_load = pl031_tick_offset_post_load,
149
+ .fields = (VMStateField[]) {
150
+ VMSTATE_UINT32(tick_offset, PL031State),
151
+ VMSTATE_END_OF_LIST()
152
+ }
153
+};
154
+
155
static const VMStateDescription vmstate_pl031 = {
156
.name = "pl031",
157
.version_id = 1,
158
.minimum_version_id = 1,
159
.pre_save = pl031_pre_save,
160
+ .pre_load = pl031_pre_load,
161
.post_load = pl031_post_load,
162
.fields = (VMStateField[]) {
163
VMSTATE_UINT32(tick_offset_vmstate, PL031State),
164
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl031 = {
165
VMSTATE_UINT32(im, PL031State),
166
VMSTATE_UINT32(is, PL031State),
167
VMSTATE_END_OF_LIST()
168
+ },
169
+ .subsections = (const VMStateDescription*[]) {
170
+ &vmstate_pl031_tick_offset,
171
+ NULL
172
}
173
};
174
175
+static Property pl031_properties[] = {
176
+ /*
177
+ * True to correctly migrate the tick offset of the RTC. False to
178
+ * obtain backward migration compatibility with older QEMU versions,
179
+ * at the expense of the guest RTC going backwards compared with the
180
+ * host RTC when the VM is saved/restored if using -rtc host.
181
+ * (Even if set to 'true' older QEMU can migrate forward to newer QEMU;
182
+ * 'false' also permits newer QEMU to migrate to older QEMU.)
183
+ */
184
+ DEFINE_PROP_BOOL("migrate-tick-offset",
185
+ PL031State, migrate_tick_offset, true),
186
+ DEFINE_PROP_END_OF_LIST()
187
+};
188
+
189
static void pl031_class_init(ObjectClass *klass, void *data)
190
{
191
DeviceClass *dc = DEVICE_CLASS(klass);
192
193
dc->vmsd = &vmstate_pl031;
194
+ dc->props = pl031_properties;
195
}
83
}
196
84
197
static const TypeInfo pl031_info = {
85
void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
86
@@ -XXX,XX +XXX,XX @@ void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
87
TCGv_i64 rval = tcg_temp_new_i64();
88
TCGv_i64 lsh = tcg_temp_new_i64();
89
TCGv_i64 rsh = tcg_temp_new_i64();
90
- TCGv_i64 zero = tcg_const_i64(0);
91
- TCGv_i64 max = tcg_const_i64(63);
92
+ TCGv_i64 zero = tcg_constant_i64(0);
93
+ TCGv_i64 max = tcg_constant_i64(63);
94
95
/*
96
* Rely on the TCG guarantee that out of range shifts produce
97
@@ -XXX,XX +XXX,XX @@ void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
98
tcg_temp_free_i64(rval);
99
tcg_temp_free_i64(lsh);
100
tcg_temp_free_i64(rsh);
101
- tcg_temp_free_i64(zero);
102
- tcg_temp_free_i64(max);
103
}
104
105
static void gen_sshl_vec(unsigned vece, TCGv_vec dst,
198
--
106
--
199
2.20.1
107
2.25.1
200
201
diff view generated by jsdifflib
New patch
[PULL 26/54] target/arm: Use tcg_constant for do_coproc_insn
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-27-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 43 +++++++++++++-----------------------------
9
1 file changed, 13 insertions(+), 30 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
16
* Note that on XScale all cp0..c13 registers do an access check
17
* call in order to handle c15_cpar.
18
*/
19
- TCGv_ptr tmpptr;
20
- TCGv_i32 tcg_syn, tcg_isread;
21
uint32_t syndrome;
22
23
/* Note that since we are an implementation which takes an
24
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
25
26
gen_set_condexec(s);
27
gen_set_pc_im(s, s->pc_curr);
28
- tmpptr = tcg_const_ptr(ri);
29
- tcg_syn = tcg_const_i32(syndrome);
30
- tcg_isread = tcg_const_i32(isread);
31
- gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn,
32
- tcg_isread);
33
- tcg_temp_free_ptr(tmpptr);
34
- tcg_temp_free_i32(tcg_syn);
35
- tcg_temp_free_i32(tcg_isread);
36
+ gen_helper_access_check_cp_reg(cpu_env,
37
+ tcg_constant_ptr(ri),
38
+ tcg_constant_i32(syndrome),
39
+ tcg_constant_i32(isread));
40
} else if (ri->type & ARM_CP_RAISES_EXC) {
41
/*
42
* The readfn or writefn might raise an exception;
43
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
44
TCGv_i64 tmp64;
45
TCGv_i32 tmp;
46
if (ri->type & ARM_CP_CONST) {
47
- tmp64 = tcg_const_i64(ri->resetvalue);
48
+ tmp64 = tcg_constant_i64(ri->resetvalue);
49
} else if (ri->readfn) {
50
- TCGv_ptr tmpptr;
51
tmp64 = tcg_temp_new_i64();
52
- tmpptr = tcg_const_ptr(ri);
53
- gen_helper_get_cp_reg64(tmp64, cpu_env, tmpptr);
54
- tcg_temp_free_ptr(tmpptr);
55
+ gen_helper_get_cp_reg64(tmp64, cpu_env,
56
+ tcg_constant_ptr(ri));
57
} else {
58
tmp64 = tcg_temp_new_i64();
59
tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset);
60
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
61
} else {
62
TCGv_i32 tmp;
63
if (ri->type & ARM_CP_CONST) {
64
- tmp = tcg_const_i32(ri->resetvalue);
65
+ tmp = tcg_constant_i32(ri->resetvalue);
66
} else if (ri->readfn) {
67
- TCGv_ptr tmpptr;
68
tmp = tcg_temp_new_i32();
69
- tmpptr = tcg_const_ptr(ri);
70
- gen_helper_get_cp_reg(tmp, cpu_env, tmpptr);
71
- tcg_temp_free_ptr(tmpptr);
72
+ gen_helper_get_cp_reg(tmp, cpu_env, tcg_constant_ptr(ri));
73
} else {
74
tmp = load_cpu_offset(ri->fieldoffset);
75
}
76
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
77
tcg_temp_free_i32(tmplo);
78
tcg_temp_free_i32(tmphi);
79
if (ri->writefn) {
80
- TCGv_ptr tmpptr = tcg_const_ptr(ri);
81
- gen_helper_set_cp_reg64(cpu_env, tmpptr, tmp64);
82
- tcg_temp_free_ptr(tmpptr);
83
+ gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri),
84
+ tmp64);
85
} else {
86
tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset);
87
}
88
tcg_temp_free_i64(tmp64);
89
} else {
90
+ TCGv_i32 tmp = load_reg(s, rt);
91
if (ri->writefn) {
92
- TCGv_i32 tmp;
93
- TCGv_ptr tmpptr;
94
- tmp = load_reg(s, rt);
95
- tmpptr = tcg_const_ptr(ri);
96
- gen_helper_set_cp_reg(cpu_env, tmpptr, tmp);
97
- tcg_temp_free_ptr(tmpptr);
98
+ gen_helper_set_cp_reg(cpu_env, tcg_constant_ptr(ri), tmp);
99
tcg_temp_free_i32(tmp);
100
} else {
101
- TCGv_i32 tmp = load_reg(s, rt);
102
store_cpu_offset(tmp, ri->fieldoffset, 4);
103
}
104
}
105
--
106
2.25.1
diff view generated by jsdifflib
New patch
[PULL 27/54] target/arm: Use tcg_constant for gen_srs
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-28-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 8 ++------
9
1 file changed, 2 insertions(+), 6 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
16
}
17
18
addr = tcg_temp_new_i32();
19
- tmp = tcg_const_i32(mode);
20
/* get_r13_banked() will raise an exception if called from System mode */
21
gen_set_condexec(s);
22
gen_set_pc_im(s, s->pc_curr);
23
- gen_helper_get_r13_banked(addr, cpu_env, tmp);
24
- tcg_temp_free_i32(tmp);
25
+ gen_helper_get_r13_banked(addr, cpu_env, tcg_constant_i32(mode));
26
switch (amode) {
27
case 0: /* DA */
28
offset = -4;
29
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
30
abort();
31
}
32
tcg_gen_addi_i32(addr, addr, offset);
33
- tmp = tcg_const_i32(mode);
34
- gen_helper_set_r13_banked(cpu_env, tmp, addr);
35
- tcg_temp_free_i32(tmp);
36
+ gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr);
37
}
38
tcg_temp_free_i32(addr);
39
s->base.is_jmp = DISAS_UPDATE_EXIT;
40
--
41
2.25.1
diff view generated by jsdifflib
New patch
[PULL 28/54] target/arm: Use tcg_constant for op_s_{rri,rxi}_rot
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-29-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 11 +++++------
9
1 file changed, 5 insertions(+), 6 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static bool op_s_rri_rot(DisasContext *s, arg_s_rri_rot *a,
16
void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32),
17
int logic_cc, StoreRegKind kind)
18
{
19
- TCGv_i32 tmp1, tmp2;
20
+ TCGv_i32 tmp1;
21
uint32_t imm;
22
23
imm = ror32(a->imm, a->rot);
24
if (logic_cc && a->rot) {
25
tcg_gen_movi_i32(cpu_CF, imm >> 31);
26
}
27
- tmp2 = tcg_const_i32(imm);
28
tmp1 = load_reg(s, a->rn);
29
30
- gen(tmp1, tmp1, tmp2);
31
- tcg_temp_free_i32(tmp2);
32
+ gen(tmp1, tmp1, tcg_constant_i32(imm));
33
34
if (logic_cc) {
35
gen_logic_CC(tmp1);
36
@@ -XXX,XX +XXX,XX @@ static bool op_s_rxi_rot(DisasContext *s, arg_s_rri_rot *a,
37
if (logic_cc && a->rot) {
38
tcg_gen_movi_i32(cpu_CF, imm >> 31);
39
}
40
- tmp = tcg_const_i32(imm);
41
42
- gen(tmp, tmp);
43
+ tmp = tcg_temp_new_i32();
44
+ gen(tmp, tcg_constant_i32(imm));
45
+
46
if (logic_cc) {
47
gen_logic_CC(tmp);
48
}
49
--
50
2.25.1
diff view generated by jsdifflib
New patch
[PULL 29/54] target/arm: Use tcg_constant for MOVW, UMAAL, CRC32
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-30-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 11 +++--------
9
1 file changed, 3 insertions(+), 8 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_ADR(DisasContext *s, arg_ri *a)
16
17
static bool trans_MOVW(DisasContext *s, arg_MOVW *a)
18
{
19
- TCGv_i32 tmp;
20
-
21
if (!ENABLE_ARCH_6T2) {
22
return false;
23
}
24
25
- tmp = tcg_const_i32(a->imm);
26
- store_reg(s, a->rd, tmp);
27
+ store_reg(s, a->rd, tcg_constant_i32(a->imm));
28
return true;
29
}
30
31
@@ -XXX,XX +XXX,XX @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a)
32
t0 = load_reg(s, a->rm);
33
t1 = load_reg(s, a->rn);
34
tcg_gen_mulu2_i32(t0, t1, t0, t1);
35
- zero = tcg_const_i32(0);
36
+ zero = tcg_constant_i32(0);
37
t2 = load_reg(s, a->ra);
38
tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero);
39
tcg_temp_free_i32(t2);
40
t2 = load_reg(s, a->rd);
41
tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero);
42
tcg_temp_free_i32(t2);
43
- tcg_temp_free_i32(zero);
44
store_reg(s, a->ra, t0);
45
store_reg(s, a->rd, t1);
46
return true;
47
@@ -XXX,XX +XXX,XX @@ static bool op_crc32(DisasContext *s, arg_rrr *a, bool c, MemOp sz)
48
default:
49
g_assert_not_reached();
50
}
51
- t3 = tcg_const_i32(1 << sz);
52
+ t3 = tcg_constant_i32(1 << sz);
53
if (c) {
54
gen_helper_crc32c(t1, t1, t2, t3);
55
} else {
56
gen_helper_crc32(t1, t1, t2, t3);
57
}
58
tcg_temp_free_i32(t2);
59
- tcg_temp_free_i32(t3);
60
store_reg(s, a->rd, t1);
61
return true;
62
}
63
--
64
2.25.1
diff view generated by jsdifflib
New patch
[PULL 30/54] target/arm: Use tcg_constant for v7m MRS, MSR
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-31-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 7 +++----
9
1 file changed, 3 insertions(+), 4 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a)
16
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
17
return false;
18
}
19
- tmp = tcg_const_i32(a->sysm);
20
- gen_helper_v7m_mrs(tmp, cpu_env, tmp);
21
+ tmp = tcg_temp_new_i32();
22
+ gen_helper_v7m_mrs(tmp, cpu_env, tcg_constant_i32(a->sysm));
23
store_reg(s, a->rd, tmp);
24
return true;
25
}
26
@@ -XXX,XX +XXX,XX @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
27
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
28
return false;
29
}
30
- addr = tcg_const_i32((a->mask << 10) | a->sysm);
31
+ addr = tcg_constant_i32((a->mask << 10) | a->sysm);
32
reg = load_reg(s, a->rn);
33
gen_helper_v7m_msr(cpu_env, addr, reg);
34
- tcg_temp_free_i32(addr);
35
tcg_temp_free_i32(reg);
36
/* If we wrote to CONTROL, the EL might have changed */
37
gen_rebuild_hflags(s, true);
38
--
39
2.25.1
diff view generated by jsdifflib
New patch
[PULL 31/54] target/arm: Use tcg_constant for TT, SAT, SMMLA
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-32-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 14 +++++---------
9
1 file changed, 5 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_TT(DisasContext *s, arg_TT *a)
16
}
17
18
addr = load_reg(s, a->rn);
19
- tmp = tcg_const_i32((a->A << 1) | a->T);
20
- gen_helper_v7m_tt(tmp, cpu_env, addr, tmp);
21
+ tmp = tcg_temp_new_i32();
22
+ gen_helper_v7m_tt(tmp, cpu_env, addr, tcg_constant_i32((a->A << 1) | a->T));
23
tcg_temp_free_i32(addr);
24
store_reg(s, a->rd, tmp);
25
return true;
26
@@ -XXX,XX +XXX,XX @@ static bool trans_PKH(DisasContext *s, arg_PKH *a)
27
static bool op_sat(DisasContext *s, arg_sat *a,
28
void (*gen)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32))
29
{
30
- TCGv_i32 tmp, satimm;
31
+ TCGv_i32 tmp;
32
int shift = a->imm;
33
34
if (!ENABLE_ARCH_6) {
35
@@ -XXX,XX +XXX,XX @@ static bool op_sat(DisasContext *s, arg_sat *a,
36
tcg_gen_shli_i32(tmp, tmp, shift);
37
}
38
39
- satimm = tcg_const_i32(a->satimm);
40
- gen(tmp, cpu_env, tmp, satimm);
41
- tcg_temp_free_i32(satimm);
42
+ gen(tmp, cpu_env, tmp, tcg_constant_i32(a->satimm));
43
44
store_reg(s, a->rd, tmp);
45
return true;
46
@@ -XXX,XX +XXX,XX @@ static bool op_smmla(DisasContext *s, arg_rrrr *a, bool round, bool sub)
47
* a non-zero multiplicand lowpart, and the correct result
48
* lowpart for rounding.
49
*/
50
- TCGv_i32 zero = tcg_const_i32(0);
51
- tcg_gen_sub2_i32(t2, t1, zero, t3, t2, t1);
52
- tcg_temp_free_i32(zero);
53
+ tcg_gen_sub2_i32(t2, t1, tcg_constant_i32(0), t3, t2, t1);
54
} else {
55
tcg_gen_add_i32(t1, t1, t3);
56
}
57
--
58
2.25.1
diff view generated by jsdifflib
New patch
[PULL 32/54] target/arm: Use tcg_constant in LDM, STM
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-33-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 12 ++++--------
9
1 file changed, 4 insertions(+), 8 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
16
{
17
int i, j, n, list, mem_idx;
18
bool user = a->u;
19
- TCGv_i32 addr, tmp, tmp2;
20
+ TCGv_i32 addr, tmp;
21
22
if (user) {
23
/* STM (user) */
24
@@ -XXX,XX +XXX,XX @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
25
26
if (user && i != 15) {
27
tmp = tcg_temp_new_i32();
28
- tmp2 = tcg_const_i32(i);
29
- gen_helper_get_user_reg(tmp, cpu_env, tmp2);
30
- tcg_temp_free_i32(tmp2);
31
+ gen_helper_get_user_reg(tmp, cpu_env, tcg_constant_i32(i));
32
} else {
33
tmp = load_reg(s, i);
34
}
35
@@ -XXX,XX +XXX,XX @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
36
bool loaded_base;
37
bool user = a->u;
38
bool exc_return = false;
39
- TCGv_i32 addr, tmp, tmp2, loaded_var;
40
+ TCGv_i32 addr, tmp, loaded_var;
41
42
if (user) {
43
/* LDM (user), LDM (exception return) */
44
@@ -XXX,XX +XXX,XX @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
45
tmp = tcg_temp_new_i32();
46
gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
47
if (user) {
48
- tmp2 = tcg_const_i32(i);
49
- gen_helper_set_user_reg(cpu_env, tmp2, tmp);
50
- tcg_temp_free_i32(tmp2);
51
+ gen_helper_set_user_reg(cpu_env, tcg_constant_i32(i), tmp);
52
tcg_temp_free_i32(tmp);
53
} else if (i == a->rn) {
54
loaded_var = tmp;
55
--
56
2.25.1
diff view generated by jsdifflib
New patch
[PULL 33/54] target/arm: Use tcg_constant in CLRM, DLS, WLS, LE
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-34-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 16 +++++-----------
9
1 file changed, 5 insertions(+), 11 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
16
17
s->eci_handled = true;
18
19
- zero = tcg_const_i32(0);
20
+ zero = tcg_constant_i32(0);
21
for (i = 0; i < 15; i++) {
22
if (extract32(a->list, i, 1)) {
23
/* Clear R[i] */
24
@@ -XXX,XX +XXX,XX @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
25
* Clear APSR (by calling the MSR helper with the same argument
26
* as for "MSR APSR_nzcvqg, Rn": mask = 0b1100, SYSM=0)
27
*/
28
- TCGv_i32 maskreg = tcg_const_i32(0xc << 8);
29
- gen_helper_v7m_msr(cpu_env, maskreg, zero);
30
- tcg_temp_free_i32(maskreg);
31
+ gen_helper_v7m_msr(cpu_env, tcg_constant_i32(0xc00), zero);
32
}
33
- tcg_temp_free_i32(zero);
34
clear_eci_state(s);
35
return true;
36
}
37
@@ -XXX,XX +XXX,XX @@ static bool trans_DLS(DisasContext *s, arg_DLS *a)
38
store_reg(s, 14, tmp);
39
if (a->size != 4) {
40
/* DLSTP: set FPSCR.LTPSIZE */
41
- tmp = tcg_const_i32(a->size);
42
- store_cpu_field(tmp, v7m.ltpsize);
43
+ store_cpu_field(tcg_constant_i32(a->size), v7m.ltpsize);
44
s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
45
}
46
return true;
47
@@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
48
*/
49
bool ok = vfp_access_check(s);
50
assert(ok);
51
- tmp = tcg_const_i32(a->size);
52
- store_cpu_field(tmp, v7m.ltpsize);
53
+ store_cpu_field(tcg_constant_i32(a->size), v7m.ltpsize);
54
/*
55
* LTPSIZE updated, but MVE_NO_PRED will always be the same thing (0)
56
* when we take this upcoming exit from this TB, so gen_jmp_tb() is OK.
57
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
58
gen_set_label(loopend);
59
if (a->tp) {
60
/* Exits from tail-pred loops must reset LTPSIZE to 4 */
61
- tmp = tcg_const_i32(4);
62
- store_cpu_field(tmp, v7m.ltpsize);
63
+ store_cpu_field(tcg_constant_i32(4), v7m.ltpsize);
64
}
65
/* End TB, continuing to following insn */
66
gen_jmp_tb(s, s->base.pc_next, 1);
67
--
68
2.25.1
diff view generated by jsdifflib
New patch
[PULL 34/54] target/arm: Use tcg_constant in trans_CPS_v7m
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-35-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 9 +++------
9
1 file changed, 3 insertions(+), 6 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a)
16
return true;
17
}
18
19
- tmp = tcg_const_i32(a->im);
20
+ tmp = tcg_constant_i32(a->im);
21
/* FAULTMASK */
22
if (a->F) {
23
- addr = tcg_const_i32(19);
24
+ addr = tcg_constant_i32(19);
25
gen_helper_v7m_msr(cpu_env, addr, tmp);
26
- tcg_temp_free_i32(addr);
27
}
28
/* PRIMASK */
29
if (a->I) {
30
- addr = tcg_const_i32(16);
31
+ addr = tcg_constant_i32(16);
32
gen_helper_v7m_msr(cpu_env, addr, tmp);
33
- tcg_temp_free_i32(addr);
34
}
35
gen_rebuild_hflags(s, false);
36
- tcg_temp_free_i32(tmp);
37
gen_lookup_tb(s);
38
return true;
39
}
40
--
41
2.25.1
diff view generated by jsdifflib
New patch
[PULL 35/54] target/arm: Use tcg_constant in trans_CSEL
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-36-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 7 +++----
9
1 file changed, 3 insertions(+), 4 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
16
}
17
18
/* In this insn input reg fields of 0b1111 mean "zero", not "PC" */
19
+ zero = tcg_constant_i32(0);
20
if (a->rn == 15) {
21
- rn = tcg_const_i32(0);
22
+ rn = zero;
23
} else {
24
rn = load_reg(s, a->rn);
25
}
26
if (a->rm == 15) {
27
- rm = tcg_const_i32(0);
28
+ rm = zero;
29
} else {
30
rm = load_reg(s, a->rm);
31
}
32
@@ -XXX,XX +XXX,XX @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
33
}
34
35
arm_test_cc(&c, a->fcond);
36
- zero = tcg_const_i32(0);
37
tcg_gen_movcond_i32(c.cond, rn, c.value, zero, rn, rm);
38
arm_free_cc(&c);
39
- tcg_temp_free_i32(zero);
40
41
store_reg(s, a->rd, rn);
42
tcg_temp_free_i32(rm);
43
--
44
2.25.1
diff view generated by jsdifflib
New patch
[PULL 36/54] target/arm: Use tcg_constant for trans_INDEX_*
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-37-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 12 ++++--------
9
1 file changed, 4 insertions(+), 8 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static void do_index(DisasContext *s, int esz, int rd,
16
static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a)
17
{
18
if (sve_access_check(s)) {
19
- TCGv_i64 start = tcg_const_i64(a->imm1);
20
- TCGv_i64 incr = tcg_const_i64(a->imm2);
21
+ TCGv_i64 start = tcg_constant_i64(a->imm1);
22
+ TCGv_i64 incr = tcg_constant_i64(a->imm2);
23
do_index(s, a->esz, a->rd, start, incr);
24
- tcg_temp_free_i64(start);
25
- tcg_temp_free_i64(incr);
26
}
27
return true;
28
}
29
@@ -XXX,XX +XXX,XX @@ static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a)
30
static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a)
31
{
32
if (sve_access_check(s)) {
33
- TCGv_i64 start = tcg_const_i64(a->imm);
34
+ TCGv_i64 start = tcg_constant_i64(a->imm);
35
TCGv_i64 incr = cpu_reg(s, a->rm);
36
do_index(s, a->esz, a->rd, start, incr);
37
- tcg_temp_free_i64(start);
38
}
39
return true;
40
}
41
@@ -XXX,XX +XXX,XX @@ static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a)
42
{
43
if (sve_access_check(s)) {
44
TCGv_i64 start = cpu_reg(s, a->rn);
45
- TCGv_i64 incr = tcg_const_i64(a->imm);
46
+ TCGv_i64 incr = tcg_constant_i64(a->imm);
47
do_index(s, a->esz, a->rd, start, incr);
48
- tcg_temp_free_i64(incr);
49
}
50
return true;
51
}
52
--
53
2.25.1
diff view generated by jsdifflib
New patch
[PULL 37/54] target/arm: Use tcg_constant in SINCDEC, INCDEC
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-38-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 18 ++++++------------
9
1 file changed, 6 insertions(+), 12 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_SINCDEC_r_32(DisasContext *s, arg_incdec_cnt *a)
16
tcg_gen_ext32s_i64(reg, reg);
17
}
18
} else {
19
- TCGv_i64 t = tcg_const_i64(inc);
20
- do_sat_addsub_32(reg, t, a->u, a->d);
21
- tcg_temp_free_i64(t);
22
+ do_sat_addsub_32(reg, tcg_constant_i64(inc), a->u, a->d);
23
}
24
return true;
25
}
26
@@ -XXX,XX +XXX,XX @@ static bool trans_SINCDEC_r_64(DisasContext *s, arg_incdec_cnt *a)
27
TCGv_i64 reg = cpu_reg(s, a->rd);
28
29
if (inc != 0) {
30
- TCGv_i64 t = tcg_const_i64(inc);
31
- do_sat_addsub_64(reg, t, a->u, a->d);
32
- tcg_temp_free_i64(t);
33
+ do_sat_addsub_64(reg, tcg_constant_i64(inc), a->u, a->d);
34
}
35
return true;
36
}
37
@@ -XXX,XX +XXX,XX @@ static bool trans_INCDEC_v(DisasContext *s, arg_incdec2_cnt *a)
38
39
if (inc != 0) {
40
if (sve_access_check(s)) {
41
- TCGv_i64 t = tcg_const_i64(a->d ? -inc : inc);
42
tcg_gen_gvec_adds(a->esz, vec_full_reg_offset(s, a->rd),
43
vec_full_reg_offset(s, a->rn),
44
- t, fullsz, fullsz);
45
- tcg_temp_free_i64(t);
46
+ tcg_constant_i64(a->d ? -inc : inc),
47
+ fullsz, fullsz);
48
}
49
} else {
50
do_mov_z(s, a->rd, a->rn);
51
@@ -XXX,XX +XXX,XX @@ static bool trans_SINCDEC_v(DisasContext *s, arg_incdec2_cnt *a)
52
53
if (inc != 0) {
54
if (sve_access_check(s)) {
55
- TCGv_i64 t = tcg_const_i64(inc);
56
- do_sat_addsub_vec(s, a->esz, a->rd, a->rn, t, a->u, a->d);
57
- tcg_temp_free_i64(t);
58
+ do_sat_addsub_vec(s, a->esz, a->rd, a->rn,
59
+ tcg_constant_i64(inc), a->u, a->d);
60
}
61
} else {
62
do_mov_z(s, a->rd, a->rn);
63
--
64
2.25.1
diff view generated by jsdifflib
New patch
[PULL 38/54] target/arm: Use tcg_constant in FCPY, CPY
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-39-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 13 ++++---------
9
1 file changed, 4 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_FCPY(DisasContext *s, arg_FCPY *a)
16
if (sve_access_check(s)) {
17
/* Decode the VFP immediate. */
18
uint64_t imm = vfp_expand_imm(a->esz, a->imm);
19
- TCGv_i64 t_imm = tcg_const_i64(imm);
20
- do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, t_imm);
21
- tcg_temp_free_i64(t_imm);
22
+ do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(imm));
23
}
24
return true;
25
}
26
@@ -XXX,XX +XXX,XX @@ static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a)
27
return false;
28
}
29
if (sve_access_check(s)) {
30
- TCGv_i64 t_imm = tcg_const_i64(a->imm);
31
- do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, t_imm);
32
- tcg_temp_free_i64(t_imm);
33
+ do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(a->imm));
34
}
35
return true;
36
}
37
@@ -XXX,XX +XXX,XX @@ static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a)
38
}
39
if (sve_access_check(s)) {
40
unsigned vsz = vec_full_reg_size(s);
41
- TCGv_i64 t_imm = tcg_const_i64(a->imm);
42
tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd),
43
pred_full_reg_offset(s, a->pg),
44
- t_imm, vsz, vsz, 0, fns[a->esz]);
45
- tcg_temp_free_i64(t_imm);
46
+ tcg_constant_i64(a->imm),
47
+ vsz, vsz, 0, fns[a->esz]);
48
}
49
return true;
50
}
51
--
52
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/10] hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs
[PULL 39/54] target/arm: Use tcg_constant in {incr, wrap}_last_active
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
In the next commit we will implement the write_with_attrs()
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
handler. To avoid using different APIs, convert the read()
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
handler first.
5
Message-id: 20220426163043.100432-40-richard.henderson@linaro.org
6
7
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
8
Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
7
---
12
hw/ssi/xilinx_spips.c | 23 +++++++++++------------
8
target/arm/translate-sve.c | 12 ++++--------
13
1 file changed, 11 insertions(+), 12 deletions(-)
9
1 file changed, 4 insertions(+), 8 deletions(-)
14
10
15
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/ssi/xilinx_spips.c
13
--- a/target/arm/translate-sve.c
18
+++ b/hw/ssi/xilinx_spips.c
14
+++ b/target/arm/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@ static void lqspi_load_cache(void *opaque, hwaddr addr)
15
@@ -XXX,XX +XXX,XX @@ static void incr_last_active(DisasContext *s, TCGv_i32 last, int esz)
16
if (is_power_of_2(vsz)) {
17
tcg_gen_andi_i32(last, last, vsz - 1);
18
} else {
19
- TCGv_i32 max = tcg_const_i32(vsz);
20
- TCGv_i32 zero = tcg_const_i32(0);
21
+ TCGv_i32 max = tcg_constant_i32(vsz);
22
+ TCGv_i32 zero = tcg_constant_i32(0);
23
tcg_gen_movcond_i32(TCG_COND_GEU, last, last, max, zero, last);
24
- tcg_temp_free_i32(max);
25
- tcg_temp_free_i32(zero);
20
}
26
}
21
}
27
}
22
28
23
-static uint64_t
29
@@ -XXX,XX +XXX,XX @@ static void wrap_last_active(DisasContext *s, TCGv_i32 last, int esz)
24
-lqspi_read(void *opaque, hwaddr addr, unsigned int size)
30
if (is_power_of_2(vsz)) {
25
+static MemTxResult lqspi_read(void *opaque, hwaddr addr, uint64_t *value,
31
tcg_gen_andi_i32(last, last, vsz - 1);
26
+ unsigned size, MemTxAttrs attrs)
32
} else {
27
{
33
- TCGv_i32 max = tcg_const_i32(vsz - (1 << esz));
28
- XilinxQSPIPS *q = opaque;
34
- TCGv_i32 zero = tcg_const_i32(0);
29
- uint32_t ret;
35
+ TCGv_i32 max = tcg_constant_i32(vsz - (1 << esz));
30
+ XilinxQSPIPS *q = XILINX_QSPIPS(opaque);
36
+ TCGv_i32 zero = tcg_constant_i32(0);
31
37
tcg_gen_movcond_i32(TCG_COND_LT, last, last, zero, max, last);
32
if (addr >= q->lqspi_cached_addr &&
38
- tcg_temp_free_i32(max);
33
addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
39
- tcg_temp_free_i32(zero);
34
uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr];
35
- ret = cpu_to_le32(*(uint32_t *)retp);
36
- DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr,
37
- (unsigned)ret);
38
- return ret;
39
- } else {
40
- lqspi_load_cache(opaque, addr);
41
- return lqspi_read(opaque, addr, size);
42
+ *value = cpu_to_le32(*(uint32_t *)retp);
43
+ DB_PRINT_L(1, "addr: %08" HWADDR_PRIx ", data: %08" PRIx64 "\n",
44
+ addr, *value);
45
+ return MEMTX_OK;
46
}
40
}
47
+
48
+ lqspi_load_cache(opaque, addr);
49
+ return lqspi_read(opaque, addr, value, size, attrs);
50
}
41
}
51
42
52
static const MemoryRegionOps lqspi_ops = {
53
- .read = lqspi_read,
54
+ .read_with_attrs = lqspi_read,
55
.endianness = DEVICE_NATIVE_ENDIAN,
56
.valid = {
57
.min_access_size = 1,
58
--
43
--
59
2.20.1
44
2.25.1
60
61
diff view generated by jsdifflib
New patch
[PULL 40/54] target/arm: Use tcg_constant in do_clast_scalar
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-41-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 7 +++----
9
1 file changed, 3 insertions(+), 4 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm,
16
bool before, TCGv_i64 reg_val)
17
{
18
TCGv_i32 last = tcg_temp_new_i32();
19
- TCGv_i64 ele, cmp, zero;
20
+ TCGv_i64 ele, cmp;
21
22
find_last_active(s, last, esz, pg);
23
24
@@ -XXX,XX +XXX,XX @@ static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm,
25
ele = load_last_active(s, last, rm, esz);
26
tcg_temp_free_i32(last);
27
28
- zero = tcg_const_i64(0);
29
- tcg_gen_movcond_i64(TCG_COND_GE, reg_val, cmp, zero, ele, reg_val);
30
+ tcg_gen_movcond_i64(TCG_COND_GE, reg_val, cmp, tcg_constant_i64(0),
31
+ ele, reg_val);
32
33
- tcg_temp_free_i64(zero);
34
tcg_temp_free_i64(cmp);
35
tcg_temp_free_i64(ele);
36
}
37
--
38
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/10] hw/arm/virt: Fix non-secure flash mode
[PULL 41/54] target/arm: Use tcg_constant in WHILE
1
From: David Engraf <david.engraf@sysgo.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Using the whole 128 MiB flash in non-secure mode is not working because
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
virt_flash_fdt() expects the same address for secure_sysmem and sysmem.
5
This is not correctly handled by caller because it forwards NULL for
6
secure_sysmem in non-secure flash mode.
7
8
Fixed by using sysmem when secure_sysmem is NULL.
9
10
Signed-off-by: David Engraf <david.engraf@sysgo.com>
11
Message-id: 20190712075002.14326-1-david.engraf@sysgo.com
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-42-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
7
---
15
hw/arm/virt.c | 2 +-
8
target/arm/translate-sve.c | 20 +++++++-------------
16
1 file changed, 1 insertion(+), 1 deletion(-)
9
1 file changed, 7 insertions(+), 13 deletions(-)
17
10
18
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
19
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/virt.c
13
--- a/target/arm/translate-sve.c
21
+++ b/hw/arm/virt.c
14
+++ b/target/arm/translate-sve.c
22
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
15
@@ -XXX,XX +XXX,XX @@ static bool trans_CTERM(DisasContext *s, arg_CTERM *a)
23
&machine->device_memory->mr);
16
static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
17
{
18
TCGv_i64 op0, op1, t0, t1, tmax;
19
- TCGv_i32 t2, t3;
20
+ TCGv_i32 t2;
21
TCGv_ptr ptr;
22
unsigned vsz = vec_full_reg_size(s);
23
unsigned desc = 0;
24
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
25
}
24
}
26
}
25
27
26
- virt_flash_fdt(vms, sysmem, secure_sysmem);
28
- tmax = tcg_const_i64(vsz >> a->esz);
27
+ virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
29
+ tmax = tcg_constant_i64(vsz >> a->esz);
28
30
if (eq) {
29
create_gic(vms, pic);
31
/* Equality means one more iteration. */
32
tcg_gen_addi_i64(t0, t0, 1);
33
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
34
35
/* Bound to the maximum. */
36
tcg_gen_umin_i64(t0, t0, tmax);
37
- tcg_temp_free_i64(tmax);
38
39
/* Set the count to zero if the condition is false. */
40
tcg_gen_movi_i64(t1, 0);
41
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
42
43
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8);
44
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
45
- t3 = tcg_const_i32(desc);
46
47
ptr = tcg_temp_new_ptr();
48
tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd));
49
50
if (a->lt) {
51
- gen_helper_sve_whilel(t2, ptr, t2, t3);
52
+ gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc));
53
} else {
54
- gen_helper_sve_whileg(t2, ptr, t2, t3);
55
+ gen_helper_sve_whileg(t2, ptr, t2, tcg_constant_i32(desc));
56
}
57
do_pred_flags(t2);
58
59
tcg_temp_free_ptr(ptr);
60
tcg_temp_free_i32(t2);
61
- tcg_temp_free_i32(t3);
62
return true;
63
}
64
65
static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
66
{
67
TCGv_i64 op0, op1, diff, t1, tmax;
68
- TCGv_i32 t2, t3;
69
+ TCGv_i32 t2;
70
TCGv_ptr ptr;
71
unsigned vsz = vec_full_reg_size(s);
72
unsigned desc = 0;
73
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
74
op0 = read_cpu_reg(s, a->rn, 1);
75
op1 = read_cpu_reg(s, a->rm, 1);
76
77
- tmax = tcg_const_i64(vsz);
78
+ tmax = tcg_constant_i64(vsz);
79
diff = tcg_temp_new_i64();
80
81
if (a->rw) {
82
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
83
84
/* Bound to the maximum. */
85
tcg_gen_umin_i64(diff, diff, tmax);
86
- tcg_temp_free_i64(tmax);
87
88
/* Since we're bounded, pass as a 32-bit type. */
89
t2 = tcg_temp_new_i32();
90
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
91
92
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8);
93
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
94
- t3 = tcg_const_i32(desc);
95
96
ptr = tcg_temp_new_ptr();
97
tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd));
98
99
- gen_helper_sve_whilel(t2, ptr, t2, t3);
100
+ gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc));
101
do_pred_flags(t2);
102
103
tcg_temp_free_ptr(ptr);
104
tcg_temp_free_i32(t2);
105
- tcg_temp_free_i32(t3);
106
return true;
107
}
30
108
31
--
109
--
32
2.20.1
110
2.25.1
33
34
diff view generated by jsdifflib
New patch
[PULL 42/54] target/arm: Use tcg_constant in LD1, ST1
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-43-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 12 ++++--------
9
1 file changed, 4 insertions(+), 8 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a)
16
gen_helper_gvec_mem_scatter *fn = NULL;
17
bool be = s->be_data == MO_BE;
18
bool mte = s->mte_active[0];
19
- TCGv_i64 imm;
20
21
if (a->esz < a->msz || (a->esz == a->msz && !a->u)) {
22
return false;
23
@@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a)
24
/* Treat LD1_zpiz (zn[x] + imm) the same way as LD1_zprz (rn + zm[x])
25
* by loading the immediate into the scalar parameter.
26
*/
27
- imm = tcg_const_i64(a->imm << a->msz);
28
- do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, false, fn);
29
- tcg_temp_free_i64(imm);
30
+ do_mem_zpz(s, a->rd, a->pg, a->rn, 0,
31
+ tcg_constant_i64(a->imm << a->msz), a->msz, false, fn);
32
return true;
33
}
34
35
@@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)
36
gen_helper_gvec_mem_scatter *fn = NULL;
37
bool be = s->be_data == MO_BE;
38
bool mte = s->mte_active[0];
39
- TCGv_i64 imm;
40
41
if (a->esz < a->msz) {
42
return false;
43
@@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)
44
/* Treat ST1_zpiz (zn[x] + imm) the same way as ST1_zprz (rn + zm[x])
45
* by loading the immediate into the scalar parameter.
46
*/
47
- imm = tcg_const_i64(a->imm << a->msz);
48
- do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, true, fn);
49
- tcg_temp_free_i64(imm);
50
+ do_mem_zpz(s, a->rd, a->pg, a->rn, 0,
51
+ tcg_constant_i64(a->imm << a->msz), a->msz, true, fn);
52
return true;
53
}
54
55
--
56
2.25.1
diff view generated by jsdifflib
New patch
[PULL 43/54] target/arm: Use tcg_constant in SUBR
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-44-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 4 +---
9
1 file changed, 1 insertion(+), 3 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)
16
}
17
if (sve_access_check(s)) {
18
unsigned vsz = vec_full_reg_size(s);
19
- TCGv_i64 c = tcg_const_i64(a->imm);
20
tcg_gen_gvec_2s(vec_full_reg_offset(s, a->rd),
21
vec_full_reg_offset(s, a->rn),
22
- vsz, vsz, c, &op[a->esz]);
23
- tcg_temp_free_i64(c);
24
+ vsz, vsz, tcg_constant_i64(a->imm), &op[a->esz]);
25
}
26
return true;
27
}
28
--
29
2.25.1
diff view generated by jsdifflib
New patch
[PULL 44/54] target/arm: Use tcg_constant in do_zzi_{sat, ool}, do_fp_imm
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-45-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 15 +++++----------
9
1 file changed, 5 insertions(+), 10 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d)
16
return false;
17
}
18
if (sve_access_check(s)) {
19
- TCGv_i64 val = tcg_const_i64(a->imm);
20
- do_sat_addsub_vec(s, a->esz, a->rd, a->rn, val, u, d);
21
- tcg_temp_free_i64(val);
22
+ do_sat_addsub_vec(s, a->esz, a->rd, a->rn,
23
+ tcg_constant_i64(a->imm), u, d);
24
}
25
return true;
26
}
27
@@ -XXX,XX +XXX,XX @@ static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i *fn)
28
{
29
if (sve_access_check(s)) {
30
unsigned vsz = vec_full_reg_size(s);
31
- TCGv_i64 c = tcg_const_i64(a->imm);
32
-
33
tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd),
34
vec_full_reg_offset(s, a->rn),
35
- c, vsz, vsz, 0, fn);
36
- tcg_temp_free_i64(c);
37
+ tcg_constant_i64(a->imm), vsz, vsz, 0, fn);
38
}
39
return true;
40
}
41
@@ -XXX,XX +XXX,XX @@ static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16,
42
static void do_fp_imm(DisasContext *s, arg_rpri_esz *a, uint64_t imm,
43
gen_helper_sve_fp2scalar *fn)
44
{
45
- TCGv_i64 temp = tcg_const_i64(imm);
46
- do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz == MO_16, temp, fn);
47
- tcg_temp_free_i64(temp);
48
+ do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz == MO_16,
49
+ tcg_constant_i64(imm), fn);
50
}
51
52
#define DO_FP_IMM(NAME, name, const0, const1) \
53
--
54
2.25.1
diff view generated by jsdifflib
New patch
[PULL 45/54] target/arm: Use tcg_constant for predicate descriptors
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
In these cases, 't' did double-duty as zero source and
4
temporary destination. Split the two uses.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20220426163043.100432-46-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 17 ++++++++---------
12
1 file changed, 8 insertions(+), 9 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static void do_predtest(DisasContext *s, int dofs, int gofs, int words)
19
{
20
TCGv_ptr dptr = tcg_temp_new_ptr();
21
TCGv_ptr gptr = tcg_temp_new_ptr();
22
- TCGv_i32 t;
23
+ TCGv_i32 t = tcg_temp_new_i32();
24
25
tcg_gen_addi_ptr(dptr, cpu_env, dofs);
26
tcg_gen_addi_ptr(gptr, cpu_env, gofs);
27
- t = tcg_const_i32(words);
28
29
- gen_helper_sve_predtest(t, dptr, gptr, t);
30
+ gen_helper_sve_predtest(t, dptr, gptr, tcg_constant_i32(words));
31
tcg_temp_free_ptr(dptr);
32
tcg_temp_free_ptr(gptr);
33
34
@@ -XXX,XX +XXX,XX @@ static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a,
35
36
tcg_gen_addi_ptr(t_pd, cpu_env, pred_full_reg_offset(s, a->rd));
37
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->rn));
38
- t = tcg_const_i32(desc);
39
+ t = tcg_temp_new_i32();
40
41
- gen_fn(t, t_pd, t_pg, t);
42
+ gen_fn(t, t_pd, t_pg, tcg_constant_i32(desc));
43
tcg_temp_free_ptr(t_pd);
44
tcg_temp_free_ptr(t_pg);
45
46
@@ -XXX,XX +XXX,XX @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
47
}
48
49
vsz = vec_full_reg_size(s);
50
- t = tcg_const_i32(simd_desc(vsz, vsz, 0));
51
+ t = tcg_temp_new_i32();
52
pd = tcg_temp_new_ptr();
53
zn = tcg_temp_new_ptr();
54
zm = tcg_temp_new_ptr();
55
@@ -XXX,XX +XXX,XX @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
56
tcg_gen_addi_ptr(zm, cpu_env, vec_full_reg_offset(s, a->rm));
57
tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
58
59
- gen_fn(t, pd, zn, zm, pg, t);
60
+ gen_fn(t, pd, zn, zm, pg, tcg_constant_i32(simd_desc(vsz, vsz, 0)));
61
62
tcg_temp_free_ptr(pd);
63
tcg_temp_free_ptr(zn);
64
@@ -XXX,XX +XXX,XX @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a,
65
}
66
67
vsz = vec_full_reg_size(s);
68
- t = tcg_const_i32(simd_desc(vsz, vsz, a->imm));
69
+ t = tcg_temp_new_i32();
70
pd = tcg_temp_new_ptr();
71
zn = tcg_temp_new_ptr();
72
pg = tcg_temp_new_ptr();
73
@@ -XXX,XX +XXX,XX @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a,
74
tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn));
75
tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
76
77
- gen_fn(t, pd, zn, pg, t);
78
+ gen_fn(t, pd, zn, pg, tcg_constant_i32(simd_desc(vsz, vsz, a->imm)));
79
80
tcg_temp_free_ptr(pd);
81
tcg_temp_free_ptr(zn);
82
--
83
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/10] hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
[PULL 46/54] target/arm: Use tcg_constant for do_brk{2,3}
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Lei Sun found while auditing the code that a CPU write would
3
In these cases, 't' did double-duty as zero source and
4
trigger a NULL pointer dereference.
4
temporary destination. Split the two uses and narrow
5
the scope of the temp.
5
6
6
>From UG1085 datasheet [*] AXI writes in this region are ignored
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
and generates an AXI Slave Error (SLVERR).
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
9
Message-id: 20220426163043.100432-47-richard.henderson@linaro.org
9
Fix by implementing the write_with_attrs() handler.
10
Return MEMTX_ERROR when the region is accessed (this error maps
11
to an AXI slave error).
12
13
[*] https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
14
15
Reported-by: Lei Sun <slei.casper@gmail.com>
16
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
17
Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
18
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
11
---
21
hw/ssi/xilinx_spips.c | 16 ++++++++++++++++
12
target/arm/translate-sve.c | 18 ++++++++++--------
22
1 file changed, 16 insertions(+)
13
1 file changed, 10 insertions(+), 8 deletions(-)
23
14
24
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
25
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/ssi/xilinx_spips.c
17
--- a/target/arm/translate-sve.c
27
+++ b/hw/ssi/xilinx_spips.c
18
+++ b/target/arm/translate-sve.c
28
@@ -XXX,XX +XXX,XX @@ static MemTxResult lqspi_read(void *opaque, hwaddr addr, uint64_t *value,
19
@@ -XXX,XX +XXX,XX @@ static bool do_brk3(DisasContext *s, arg_rprr_s *a,
29
return lqspi_read(opaque, addr, value, size, attrs);
20
TCGv_ptr n = tcg_temp_new_ptr();
21
TCGv_ptr m = tcg_temp_new_ptr();
22
TCGv_ptr g = tcg_temp_new_ptr();
23
- TCGv_i32 t = tcg_const_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
24
+ TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
25
26
tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd));
27
tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn));
28
@@ -XXX,XX +XXX,XX @@ static bool do_brk3(DisasContext *s, arg_rprr_s *a,
29
tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg));
30
31
if (a->s) {
32
- fn_s(t, d, n, m, g, t);
33
+ TCGv_i32 t = tcg_temp_new_i32();
34
+ fn_s(t, d, n, m, g, desc);
35
do_pred_flags(t);
36
+ tcg_temp_free_i32(t);
37
} else {
38
- fn(d, n, m, g, t);
39
+ fn(d, n, m, g, desc);
40
}
41
tcg_temp_free_ptr(d);
42
tcg_temp_free_ptr(n);
43
tcg_temp_free_ptr(m);
44
tcg_temp_free_ptr(g);
45
- tcg_temp_free_i32(t);
46
return true;
30
}
47
}
31
48
32
+static MemTxResult lqspi_write(void *opaque, hwaddr offset, uint64_t value,
49
@@ -XXX,XX +XXX,XX @@ static bool do_brk2(DisasContext *s, arg_rpr_s *a,
33
+ unsigned size, MemTxAttrs attrs)
50
TCGv_ptr d = tcg_temp_new_ptr();
34
+{
51
TCGv_ptr n = tcg_temp_new_ptr();
35
+ /*
52
TCGv_ptr g = tcg_temp_new_ptr();
36
+ * From UG1085, Chapter 24 (Quad-SPI controllers):
53
- TCGv_i32 t = tcg_const_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
37
+ * - Writes are ignored
54
+ TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
38
+ * - AXI writes generate an external AXI slave error (SLVERR)
55
39
+ */
56
tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd));
40
+ qemu_log_mask(LOG_GUEST_ERROR, "%s Unexpected %u-bit access to 0x%" PRIx64
57
tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn));
41
+ " (value: 0x%" PRIx64 "\n",
58
tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg));
42
+ __func__, size << 3, offset, value);
59
43
+
60
if (a->s) {
44
+ return MEMTX_ERROR;
61
- fn_s(t, d, n, g, t);
45
+}
62
+ TCGv_i32 t = tcg_temp_new_i32();
46
+
63
+ fn_s(t, d, n, g, desc);
47
static const MemoryRegionOps lqspi_ops = {
64
do_pred_flags(t);
48
.read_with_attrs = lqspi_read,
65
+ tcg_temp_free_i32(t);
49
+ .write_with_attrs = lqspi_write,
66
} else {
50
.endianness = DEVICE_NATIVE_ENDIAN,
67
- fn(d, n, g, t);
51
.valid = {
68
+ fn(d, n, g, desc);
52
.min_access_size = 1,
69
}
70
tcg_temp_free_ptr(d);
71
tcg_temp_free_ptr(n);
72
tcg_temp_free_ptr(g);
73
- tcg_temp_free_i32(t);
74
return true;
75
}
76
53
--
77
--
54
2.20.1
78
2.25.1
55
56
diff view generated by jsdifflib
New patch
[PULL 47/54] target/arm: Use tcg_constant for vector descriptor
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-48-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 54 ++++++++++----------------------------
9
1 file changed, 14 insertions(+), 40 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a,
16
return true;
17
}
18
19
- desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
20
+ desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
21
temp = tcg_temp_new_i64();
22
t_zn = tcg_temp_new_ptr();
23
t_pg = tcg_temp_new_ptr();
24
@@ -XXX,XX +XXX,XX @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a,
25
fn(temp, t_zn, t_pg, desc);
26
tcg_temp_free_ptr(t_zn);
27
tcg_temp_free_ptr(t_pg);
28
- tcg_temp_free_i32(desc);
29
30
write_fp_dreg(s, a->rd, temp);
31
tcg_temp_free_i64(temp);
32
@@ -XXX,XX +XXX,XX @@ static void do_index(DisasContext *s, int esz, int rd,
33
TCGv_i64 start, TCGv_i64 incr)
34
{
35
unsigned vsz = vec_full_reg_size(s);
36
- TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
37
+ TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
38
TCGv_ptr t_zd = tcg_temp_new_ptr();
39
40
tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd));
41
@@ -XXX,XX +XXX,XX @@ static void do_index(DisasContext *s, int esz, int rd,
42
tcg_temp_free_i32(i32);
43
}
44
tcg_temp_free_ptr(t_zd);
45
- tcg_temp_free_i32(desc);
46
}
47
48
static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a)
49
@@ -XXX,XX +XXX,XX @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn,
50
nptr = tcg_temp_new_ptr();
51
tcg_gen_addi_ptr(dptr, cpu_env, vec_full_reg_offset(s, rd));
52
tcg_gen_addi_ptr(nptr, cpu_env, vec_full_reg_offset(s, rn));
53
- desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
54
+ desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
55
56
switch (esz) {
57
case MO_8:
58
@@ -XXX,XX +XXX,XX @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn,
59
60
tcg_temp_free_ptr(dptr);
61
tcg_temp_free_ptr(nptr);
62
- tcg_temp_free_i32(desc);
63
}
64
65
static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a)
66
@@ -XXX,XX +XXX,XX @@ static void do_cpy_m(DisasContext *s, int esz, int rd, int rn, int pg,
67
gen_helper_sve_cpy_m_s, gen_helper_sve_cpy_m_d,
68
};
69
unsigned vsz = vec_full_reg_size(s);
70
- TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
71
+ TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
72
TCGv_ptr t_zd = tcg_temp_new_ptr();
73
TCGv_ptr t_zn = tcg_temp_new_ptr();
74
TCGv_ptr t_pg = tcg_temp_new_ptr();
75
@@ -XXX,XX +XXX,XX @@ static void do_cpy_m(DisasContext *s, int esz, int rd, int rn, int pg,
76
tcg_temp_free_ptr(t_zd);
77
tcg_temp_free_ptr(t_zn);
78
tcg_temp_free_ptr(t_pg);
79
- tcg_temp_free_i32(desc);
80
}
81
82
static bool trans_FCPY(DisasContext *s, arg_FCPY *a)
83
@@ -XXX,XX +XXX,XX @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz *a, TCGv_i64 val)
84
gen_helper_sve_insr_s, gen_helper_sve_insr_d,
85
};
86
unsigned vsz = vec_full_reg_size(s);
87
- TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
88
+ TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
89
TCGv_ptr t_zd = tcg_temp_new_ptr();
90
TCGv_ptr t_zn = tcg_temp_new_ptr();
91
92
@@ -XXX,XX +XXX,XX @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz *a, TCGv_i64 val)
93
94
tcg_temp_free_ptr(t_zd);
95
tcg_temp_free_ptr(t_zn);
96
- tcg_temp_free_i32(desc);
97
}
98
99
static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a)
100
@@ -XXX,XX +XXX,XX @@ static bool do_perm_pred3(DisasContext *s, arg_rrr_esz *a, bool high_odd,
101
TCGv_ptr t_d = tcg_temp_new_ptr();
102
TCGv_ptr t_n = tcg_temp_new_ptr();
103
TCGv_ptr t_m = tcg_temp_new_ptr();
104
- TCGv_i32 t_desc;
105
uint32_t desc = 0;
106
107
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz);
108
@@ -XXX,XX +XXX,XX @@ static bool do_perm_pred3(DisasContext *s, arg_rrr_esz *a, bool high_odd,
109
tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd));
110
tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn));
111
tcg_gen_addi_ptr(t_m, cpu_env, pred_full_reg_offset(s, a->rm));
112
- t_desc = tcg_const_i32(desc);
113
114
- fn(t_d, t_n, t_m, t_desc);
115
+ fn(t_d, t_n, t_m, tcg_constant_i32(desc));
116
117
tcg_temp_free_ptr(t_d);
118
tcg_temp_free_ptr(t_n);
119
tcg_temp_free_ptr(t_m);
120
- tcg_temp_free_i32(t_desc);
121
return true;
122
}
123
124
@@ -XXX,XX +XXX,XX @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd,
125
unsigned vsz = pred_full_reg_size(s);
126
TCGv_ptr t_d = tcg_temp_new_ptr();
127
TCGv_ptr t_n = tcg_temp_new_ptr();
128
- TCGv_i32 t_desc;
129
uint32_t desc = 0;
130
131
tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd));
132
@@ -XXX,XX +XXX,XX @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd,
133
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz);
134
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
135
desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd);
136
- t_desc = tcg_const_i32(desc);
137
138
- fn(t_d, t_n, t_desc);
139
+ fn(t_d, t_n, tcg_constant_i32(desc));
140
141
- tcg_temp_free_i32(t_desc);
142
tcg_temp_free_ptr(t_d);
143
tcg_temp_free_ptr(t_n);
144
return true;
145
@@ -XXX,XX +XXX,XX @@ static void find_last_active(DisasContext *s, TCGv_i32 ret, int esz, int pg)
146
* round up, as we do elsewhere, because we need the exact size.
147
*/
148
TCGv_ptr t_p = tcg_temp_new_ptr();
149
- TCGv_i32 t_desc;
150
unsigned desc = 0;
151
152
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s));
153
desc = FIELD_DP32(desc, PREDDESC, ESZ, esz);
154
155
tcg_gen_addi_ptr(t_p, cpu_env, pred_full_reg_offset(s, pg));
156
- t_desc = tcg_const_i32(desc);
157
158
- gen_helper_sve_last_active_element(ret, t_p, t_desc);
159
+ gen_helper_sve_last_active_element(ret, t_p, tcg_constant_i32(desc));
160
161
- tcg_temp_free_i32(t_desc);
162
tcg_temp_free_ptr(t_p);
163
}
164
165
@@ -XXX,XX +XXX,XX @@ static void do_cntp(DisasContext *s, TCGv_i64 val, int esz, int pn, int pg)
166
TCGv_ptr t_pn = tcg_temp_new_ptr();
167
TCGv_ptr t_pg = tcg_temp_new_ptr();
168
unsigned desc = 0;
169
- TCGv_i32 t_desc;
170
171
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, psz);
172
desc = FIELD_DP32(desc, PREDDESC, ESZ, esz);
173
174
tcg_gen_addi_ptr(t_pn, cpu_env, pred_full_reg_offset(s, pn));
175
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
176
- t_desc = tcg_const_i32(desc);
177
178
- gen_helper_sve_cntp(val, t_pn, t_pg, t_desc);
179
+ gen_helper_sve_cntp(val, t_pn, t_pg, tcg_constant_i32(desc));
180
tcg_temp_free_ptr(t_pn);
181
tcg_temp_free_ptr(t_pg);
182
- tcg_temp_free_i32(t_desc);
183
}
184
}
185
186
@@ -XXX,XX +XXX,XX @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a,
187
{
188
unsigned vsz = vec_full_reg_size(s);
189
unsigned p2vsz = pow2ceil(vsz);
190
- TCGv_i32 t_desc = tcg_const_i32(simd_desc(vsz, vsz, p2vsz));
191
+ TCGv_i32 t_desc = tcg_constant_i32(simd_desc(vsz, vsz, p2vsz));
192
TCGv_ptr t_zn, t_pg, status;
193
TCGv_i64 temp;
194
195
@@ -XXX,XX +XXX,XX @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a,
196
tcg_temp_free_ptr(t_zn);
197
tcg_temp_free_ptr(t_pg);
198
tcg_temp_free_ptr(status);
199
- tcg_temp_free_i32(t_desc);
200
201
write_fp_dreg(s, a->rd, temp);
202
tcg_temp_free_i64(temp);
203
@@ -XXX,XX +XXX,XX @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
204
tcg_gen_addi_ptr(t_rm, cpu_env, vec_full_reg_offset(s, a->rm));
205
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg));
206
t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
207
- t_desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
208
+ t_desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
209
210
fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc);
211
212
- tcg_temp_free_i32(t_desc);
213
tcg_temp_free_ptr(t_fpst);
214
tcg_temp_free_ptr(t_pg);
215
tcg_temp_free_ptr(t_rm);
216
@@ -XXX,XX +XXX,XX @@ static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16,
217
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
218
219
status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR);
220
- desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
221
+ desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
222
fn(t_zd, t_zn, t_pg, scalar, status, desc);
223
224
- tcg_temp_free_i32(desc);
225
tcg_temp_free_ptr(status);
226
tcg_temp_free_ptr(t_pg);
227
tcg_temp_free_ptr(t_zn);
228
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
229
{
230
unsigned vsz = vec_full_reg_size(s);
231
TCGv_ptr t_pg;
232
- TCGv_i32 t_desc;
233
int desc = 0;
234
235
/*
236
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
237
}
238
239
desc = simd_desc(vsz, vsz, zt | desc);
240
- t_desc = tcg_const_i32(desc);
241
t_pg = tcg_temp_new_ptr();
242
243
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
244
- fn(cpu_env, t_pg, addr, t_desc);
245
+ fn(cpu_env, t_pg, addr, tcg_constant_i32(desc));
246
247
tcg_temp_free_ptr(t_pg);
248
- tcg_temp_free_i32(t_desc);
249
}
250
251
/* Indexed by [mte][be][dtype][nreg] */
252
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
253
TCGv_ptr t_zm = tcg_temp_new_ptr();
254
TCGv_ptr t_pg = tcg_temp_new_ptr();
255
TCGv_ptr t_zt = tcg_temp_new_ptr();
256
- TCGv_i32 t_desc;
257
int desc = 0;
258
259
if (s->mte_active[0]) {
260
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
261
desc <<= SVE_MTEDESC_SHIFT;
262
}
263
desc = simd_desc(vsz, vsz, desc | scale);
264
- t_desc = tcg_const_i32(desc);
265
266
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
267
tcg_gen_addi_ptr(t_zm, cpu_env, vec_full_reg_offset(s, zm));
268
tcg_gen_addi_ptr(t_zt, cpu_env, vec_full_reg_offset(s, zt));
269
- fn(cpu_env, t_zt, t_pg, t_zm, scalar, t_desc);
270
+ fn(cpu_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc));
271
272
tcg_temp_free_ptr(t_zt);
273
tcg_temp_free_ptr(t_zm);
274
tcg_temp_free_ptr(t_pg);
275
- tcg_temp_free_i32(t_desc);
276
}
277
278
/* Indexed by [mte][be][ff][xs][u][msz]. */
279
--
280
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/10] target/arm: report ARMv8-A FP support for AArch32 -cpu max
[PULL 48/54] target/arm: Disable cryptographic instructions when neon is disabled
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Damien Hedde <damien.hedde@greensocs.com>
2
2
3
When we converted to using feature bits in 602f6e42cfbf we missed out
3
As of now, cryptographic instructions ISAR fields are never cleared so
4
the fact (dp && arm_dc_feature(s, ARM_FEATURE_V8)) was supported for
4
we can end up with a cpu with cryptographic instructions but no
5
-cpu max configurations. This caused a regression in the GCC test
5
floating-point/neon instructions which is not a possible configuration
6
suite. Fix this by setting the appropriate bits in mvfr1.FPHP to
6
according to Arm specifications.
7
report ARMv8-A with FP support (but not ARMv8.2-FP16).
8
7
9
Fixes: https://bugs.launchpad.net/qemu/+bug/1836078
8
In QEMU, we have 3 kinds of cpus regarding cryptographic instructions:
10
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
+ no support
10
+ cortex-a57/a72: cryptographic extension is optional,
11
floating-point/neon is not.
12
+ cortex-a53: crytographic extension is optional as well as
13
floating-point/neon. But cryptographic requires
14
floating-point/neon support.
15
16
Therefore we can safely clear the ISAR fields when neon is disabled.
17
18
Note that other Arm cpus seem to follow this. For example cortex-a55 is
19
like cortex-a53 and cortex-a76/cortex-a710 are like cortex-a57/a72.
20
21
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20190711103737.10017-1-alex.bennee@linaro.org
23
Message-id: 20220427090117.6954-1-damien.hedde@greensocs.com
24
[PMM: fixed commit message typos]
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
26
---
15
target/arm/cpu.c | 4 ++++
27
target/arm/cpu.c | 9 +++++++++
16
1 file changed, 4 insertions(+)
28
1 file changed, 9 insertions(+)
17
29
18
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
30
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
19
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.c
32
--- a/target/arm/cpu.c
21
+++ b/target/arm/cpu.c
33
+++ b/target/arm/cpu.c
22
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
34
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
23
t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
35
unset_feature(env, ARM_FEATURE_NEON);
24
cpu->isar.id_isar6 = t;
36
25
37
t = cpu->isar.id_aa64isar0;
26
+ t = cpu->isar.mvfr1;
38
+ t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0);
27
+ t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */
39
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0);
28
+ cpu->isar.mvfr1 = t;
40
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0);
29
+
41
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0);
30
t = cpu->isar.mvfr2;
42
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0);
31
t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
43
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0);
32
t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
44
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
45
cpu->isar.id_aa64isar0 = t;
46
47
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
48
cpu->isar.id_aa64pfr0 = t;
49
50
u = cpu->isar.id_isar5;
51
+ u = FIELD_DP32(u, ID_ISAR5, AES, 0);
52
+ u = FIELD_DP32(u, ID_ISAR5, SHA1, 0);
53
+ u = FIELD_DP32(u, ID_ISAR5, SHA2, 0);
54
u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
55
u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
56
cpu->isar.id_isar5 = u;
33
--
57
--
34
2.20.1
58
2.25.1
35
36
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/10] hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
[PULL 49/54] target/arm: Use field names for accessing DBGWCRn
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Reading the RX_DATA register when the RX_FIFO is empty triggers
3
While defining these names, use the correct field width of 5 not 4 for
4
an abort. This can be easily reproduced:
4
DBGWCR.MASK. This typo prevented setting a watchpoint larger than 32k.
5
5
6
$ qemu-system-arm -M emcraft-sf2 -monitor stdio -S
6
Reported-by: Chris Howard <cvz185@web.de>
7
QEMU 4.0.50 monitor - type 'help' for more information
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
(qemu) x 0x40001010
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Aborted (core dumped)
9
Message-id: 20220427051926.295223-1-richard.henderson@linaro.org
10
11
(gdb) bt
12
#1 0x00007f035874f895 in abort () at /lib64/libc.so.6
13
#2 0x00005628686591ff in fifo8_pop (fifo=0x56286a9a4c68) at util/fifo8.c:66
14
#3 0x00005628683e0b8e in fifo32_pop (fifo=0x56286a9a4c68) at include/qemu/fifo32.h:137
15
#4 0x00005628683e0efb in spi_read (opaque=0x56286a9a4850, addr=4, size=4) at hw/ssi/mss-spi.c:168
16
#5 0x0000562867f96801 in memory_region_read_accessor (mr=0x56286a9a4b60, addr=16, value=0x7ffeecb0c5c8, size=4, shift=0, mask=4294967295, attrs=...) at memory.c:439
17
#6 0x0000562867f96cdb in access_with_adjusted_size (addr=16, value=0x7ffeecb0c5c8, size=4, access_size_min=1, access_size_max=4, access_fn=0x562867f967c3 <memory_region_read_accessor>, mr=0x56286a9a4b60, attrs=...) at memory.c:569
18
#7 0x0000562867f99940 in memory_region_dispatch_read1 (mr=0x56286a9a4b60, addr=16, pval=0x7ffeecb0c5c8, size=4, attrs=...) at memory.c:1420
19
#8 0x0000562867f99a08 in memory_region_dispatch_read (mr=0x56286a9a4b60, addr=16, pval=0x7ffeecb0c5c8, size=4, attrs=...) at memory.c:1447
20
#9 0x0000562867f38721 in flatview_read_continue (fv=0x56286aec6360, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4, addr1=16, l=4, mr=0x56286a9a4b60) at exec.c:3385
21
#10 0x0000562867f38874 in flatview_read (fv=0x56286aec6360, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4) at exec.c:3423
22
#11 0x0000562867f388ea in address_space_read_full (as=0x56286aa3e890, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4) at exec.c:3436
23
#12 0x0000562867f389c5 in address_space_rw (as=0x56286aa3e890, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4, is_write=false) at exec.c:3466
24
#13 0x0000562867f3bdd7 in cpu_memory_rw_debug (cpu=0x56286aa19d00, addr=1073745936, buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4, is_write=0) at exec.c:3976
25
#14 0x000056286811ed51 in memory_dump (mon=0x56286a8c32d0, count=1, format=120, wsize=4, addr=1073745936, is_physical=0) at monitor/misc.c:730
26
#15 0x000056286811eff1 in hmp_memory_dump (mon=0x56286a8c32d0, qdict=0x56286b15c400) at monitor/misc.c:785
27
#16 0x00005628684740ee in handle_hmp_command (mon=0x56286a8c32d0, cmdline=0x56286a8caeb2 "0x40001010") at monitor/hmp.c:1082
28
29
From the datasheet "Actel SmartFusion Microcontroller Subsystem
30
User's Guide" Rev.1, Table 13-3 "SPI Register Summary", this
31
register has a reset value of 0.
32
33
Check the FIFO is not empty before accessing it, else log an
34
error message.
35
36
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
37
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
38
Message-id: 20190709113715.7761-3-philmd@redhat.com
39
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
40
---
11
---
41
hw/ssi/mss-spi.c | 8 +++++++-
12
target/arm/internals.h | 12 ++++++++++++
42
1 file changed, 7 insertions(+), 1 deletion(-)
13
target/arm/debug_helper.c | 10 +++++-----
14
target/arm/helper.c | 8 ++++----
15
target/arm/kvm64.c | 14 +++++++-------
16
4 files changed, 28 insertions(+), 16 deletions(-)
43
17
44
diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
45
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/ssi/mss-spi.c
20
--- a/target/arm/internals.h
47
+++ b/hw/ssi/mss-spi.c
21
+++ b/target/arm/internals.h
48
@@ -XXX,XX +XXX,XX @@ spi_read(void *opaque, hwaddr addr, unsigned int size)
22
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
49
case R_SPI_RX:
23
*/
50
s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
24
#define FNC_RETURN_MIN_MAGIC 0xfefffffe
51
s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF;
25
52
- ret = fifo32_pop(&s->rx_fifo);
26
+/* Bit definitions for DBGWCRn and DBGWCRn_EL1 */
53
+ if (fifo32_is_empty(&s->rx_fifo)) {
27
+FIELD(DBGWCR, E, 0, 1)
54
+ qemu_log_mask(LOG_GUEST_ERROR,
28
+FIELD(DBGWCR, PAC, 1, 2)
55
+ "%s: Reading empty RX_FIFO\n",
29
+FIELD(DBGWCR, LSC, 3, 2)
56
+ __func__);
30
+FIELD(DBGWCR, BAS, 5, 8)
57
+ } else {
31
+FIELD(DBGWCR, HMC, 13, 1)
58
+ ret = fifo32_pop(&s->rx_fifo);
32
+FIELD(DBGWCR, SSC, 14, 2)
59
+ }
33
+FIELD(DBGWCR, LBN, 16, 4)
60
if (fifo32_is_empty(&s->rx_fifo)) {
34
+FIELD(DBGWCR, WT, 20, 1)
61
s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
35
+FIELD(DBGWCR, MASK, 24, 5)
36
+FIELD(DBGWCR, SSCE, 29, 1)
37
+
38
/* We use a few fake FSR values for internal purposes in M profile.
39
* M profile cores don't have A/R format FSRs, but currently our
40
* get_phys_addr() code assumes A/R profile and reports failures via
41
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/debug_helper.c
44
+++ b/target/arm/debug_helper.c
45
@@ -XXX,XX +XXX,XX @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
46
* Non-Secure to simplify the code slightly compared to the full
47
* table in the ARM ARM.
48
*/
49
- pac = extract64(cr, 1, 2);
50
- hmc = extract64(cr, 13, 1);
51
- ssc = extract64(cr, 14, 2);
52
+ pac = FIELD_EX64(cr, DBGWCR, PAC);
53
+ hmc = FIELD_EX64(cr, DBGWCR, HMC);
54
+ ssc = FIELD_EX64(cr, DBGWCR, SSC);
55
56
switch (ssc) {
57
case 0:
58
@@ -XXX,XX +XXX,XX @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
59
g_assert_not_reached();
60
}
61
62
- wt = extract64(cr, 20, 1);
63
- lbn = extract64(cr, 16, 4);
64
+ wt = FIELD_EX64(cr, DBGWCR, WT);
65
+ lbn = FIELD_EX64(cr, DBGWCR, LBN);
66
67
if (wt && !linked_bp_matches(cpu, lbn)) {
68
return false;
69
diff --git a/target/arm/helper.c b/target/arm/helper.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/target/arm/helper.c
72
+++ b/target/arm/helper.c
73
@@ -XXX,XX +XXX,XX @@ void hw_watchpoint_update(ARMCPU *cpu, int n)
74
env->cpu_watchpoint[n] = NULL;
75
}
76
77
- if (!extract64(wcr, 0, 1)) {
78
+ if (!FIELD_EX64(wcr, DBGWCR, E)) {
79
/* E bit clear : watchpoint disabled */
80
return;
81
}
82
83
- switch (extract64(wcr, 3, 2)) {
84
+ switch (FIELD_EX64(wcr, DBGWCR, LSC)) {
85
case 0:
86
/* LSC 00 is reserved and must behave as if the wp is disabled */
87
return;
88
@@ -XXX,XX +XXX,XX @@ void hw_watchpoint_update(ARMCPU *cpu, int n)
89
* CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
90
* thus generating a watchpoint for every byte in the masked region.
91
*/
92
- mask = extract64(wcr, 24, 4);
93
+ mask = FIELD_EX64(wcr, DBGWCR, MASK);
94
if (mask == 1 || mask == 2) {
95
/* Reserved values of MASK; we must act as if the mask value was
96
* some non-reserved value, or as if the watchpoint were disabled.
97
@@ -XXX,XX +XXX,XX @@ void hw_watchpoint_update(ARMCPU *cpu, int n)
98
wvr &= ~(len - 1);
99
} else {
100
/* Watchpoint covers bytes defined by the byte address select bits */
101
- int bas = extract64(wcr, 5, 8);
102
+ int bas = FIELD_EX64(wcr, DBGWCR, BAS);
103
int basstart;
104
105
if (extract64(wvr, 2, 1)) {
106
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/kvm64.c
109
+++ b/target/arm/kvm64.c
110
@@ -XXX,XX +XXX,XX @@ static int insert_hw_watchpoint(target_ulong addr,
111
target_ulong len, int type)
112
{
113
HWWatchpoint wp = {
114
- .wcr = 1, /* E=1, enable */
115
+ .wcr = R_DBGWCR_E_MASK, /* E=1, enable */
116
.wvr = addr & (~0x7ULL),
117
.details = { .vaddr = addr, .len = len }
118
};
119
@@ -XXX,XX +XXX,XX @@ static int insert_hw_watchpoint(target_ulong addr,
120
* HMC=0 SSC=0 PAC=3 will hit EL0 or EL1, any security state,
121
* valid whether EL3 is implemented or not
122
*/
123
- wp.wcr = deposit32(wp.wcr, 1, 2, 3);
124
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, PAC, 3);
125
126
switch (type) {
127
case GDB_WATCHPOINT_READ:
128
- wp.wcr = deposit32(wp.wcr, 3, 2, 1);
129
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 1);
130
wp.details.flags = BP_MEM_READ;
131
break;
132
case GDB_WATCHPOINT_WRITE:
133
- wp.wcr = deposit32(wp.wcr, 3, 2, 2);
134
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 2);
135
wp.details.flags = BP_MEM_WRITE;
136
break;
137
case GDB_WATCHPOINT_ACCESS:
138
- wp.wcr = deposit32(wp.wcr, 3, 2, 3);
139
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 3);
140
wp.details.flags = BP_MEM_ACCESS;
141
break;
142
default:
143
@@ -XXX,XX +XXX,XX @@ static int insert_hw_watchpoint(target_ulong addr,
144
int bits = ctz64(len);
145
146
wp.wvr &= ~((1 << bits) - 1);
147
- wp.wcr = deposit32(wp.wcr, 24, 4, bits);
148
- wp.wcr = deposit32(wp.wcr, 5, 8, 0xff);
149
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, MASK, bits);
150
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, BAS, 0xff);
151
} else {
152
return -ENOBUFS;
62
}
153
}
63
--
154
--
64
2.20.1
155
2.25.1
65
156
66
157
diff view generated by jsdifflib
New patch
[PULL 50/54] hw/arm/smmuv3: Cache event fault record
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
2
3
The Record bit in the Context Descriptor tells the SMMU to report fault
4
events to the event queue. Since we don't cache the Record bit at the
5
moment, access faults from a cached Context Descriptor are never
6
reported. Store the Record bit in the cached SMMUTransCfg.
7
8
Fixes: 9bde7f0674fe ("hw/arm/smmuv3: Implement translate callback")
9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
12
Message-id: 20220427111543.124620-1-jean-philippe@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/arm/smmuv3-internal.h | 1 -
16
include/hw/arm/smmu-common.h | 1 +
17
hw/arm/smmuv3.c | 14 +++++++-------
18
3 files changed, 8 insertions(+), 8 deletions(-)
19
20
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/smmuv3-internal.h
23
+++ b/hw/arm/smmuv3-internal.h
24
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUEventInfo {
25
SMMUEventType type;
26
uint32_t sid;
27
bool recorded;
28
- bool record_trans_faults;
29
bool inval_ste_allowed;
30
union {
31
struct {
32
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/include/hw/arm/smmu-common.h
35
+++ b/include/hw/arm/smmu-common.h
36
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg {
37
bool disabled; /* smmu is disabled */
38
bool bypassed; /* translation is bypassed */
39
bool aborted; /* translation is aborted */
40
+ bool record_faults; /* record fault events */
41
uint64_t ttb; /* TT base address */
42
uint8_t oas; /* output address width */
43
uint8_t tbi; /* Top Byte Ignore */
44
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/arm/smmuv3.c
47
+++ b/hw/arm/smmuv3.c
48
@@ -XXX,XX +XXX,XX @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
49
trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, tt->granule_sz, tt->had);
50
}
51
52
- event->record_trans_faults = CD_R(cd);
53
+ cfg->record_faults = CD_R(cd);
54
55
return 0;
56
57
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
58
59
tt = select_tt(cfg, addr);
60
if (!tt) {
61
- if (event.record_trans_faults) {
62
+ if (cfg->record_faults) {
63
event.type = SMMU_EVT_F_TRANSLATION;
64
event.u.f_translation.addr = addr;
65
event.u.f_translation.rnw = flag & 0x1;
66
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
67
if (cached_entry) {
68
if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) {
69
status = SMMU_TRANS_ERROR;
70
- if (event.record_trans_faults) {
71
+ if (cfg->record_faults) {
72
event.type = SMMU_EVT_F_PERMISSION;
73
event.u.f_permission.addr = addr;
74
event.u.f_permission.rnw = flag & 0x1;
75
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
76
event.u.f_walk_eabt.addr2 = ptw_info.addr;
77
break;
78
case SMMU_PTW_ERR_TRANSLATION:
79
- if (event.record_trans_faults) {
80
+ if (cfg->record_faults) {
81
event.type = SMMU_EVT_F_TRANSLATION;
82
event.u.f_translation.addr = addr;
83
event.u.f_translation.rnw = flag & 0x1;
84
}
85
break;
86
case SMMU_PTW_ERR_ADDR_SIZE:
87
- if (event.record_trans_faults) {
88
+ if (cfg->record_faults) {
89
event.type = SMMU_EVT_F_ADDR_SIZE;
90
event.u.f_addr_size.addr = addr;
91
event.u.f_addr_size.rnw = flag & 0x1;
92
}
93
break;
94
case SMMU_PTW_ERR_ACCESS:
95
- if (event.record_trans_faults) {
96
+ if (cfg->record_faults) {
97
event.type = SMMU_EVT_F_ACCESS;
98
event.u.f_access.addr = addr;
99
event.u.f_access.rnw = flag & 0x1;
100
}
101
break;
102
case SMMU_PTW_ERR_PERMISSION:
103
- if (event.record_trans_faults) {
104
+ if (cfg->record_faults) {
105
event.type = SMMU_EVT_F_PERMISSION;
106
event.u.f_permission.addr = addr;
107
event.u.f_permission.rnw = flag & 0x1;
108
--
109
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/10] hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
[PULL 51/54] hw/arm/smmuv3: Add space in guest error message
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
Both lqspi_read() and lqspi_load_cache() expect a 32-bit
3
Make the translation error message prettier by adding a missing space
4
aligned address.
4
before the parenthesis.
5
5
6
>From UG1085 datasheet [*] chapter on 'Quad-SPI Controller':
6
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
7
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Transfer Size Limitations
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
9
Message-id: 20220427111543.124620-2-jean-philippe@linaro.org
10
Because of the 32-bit wide TX, RX, and generic FIFO, all
11
APB/AXI transfers must be an integer multiple of 4-bytes.
12
Shorter transfers are not possible.
13
14
Set MemoryRegionOps.impl values to force 32-bit accesses,
15
this way we are sure we do not access the lqspi_buf[] array
16
out of bound.
17
18
[*] https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
19
20
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
21
Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
22
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
---
11
---
25
hw/ssi/xilinx_spips.c | 4 ++++
12
hw/arm/smmuv3.c | 2 +-
26
1 file changed, 4 insertions(+)
13
1 file changed, 1 insertion(+), 1 deletion(-)
27
14
28
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
15
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
29
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/ssi/xilinx_spips.c
17
--- a/hw/arm/smmuv3.c
31
+++ b/hw/ssi/xilinx_spips.c
18
+++ b/hw/arm/smmuv3.c
32
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps lqspi_ops = {
19
@@ -XXX,XX +XXX,XX @@ epilogue:
33
.read_with_attrs = lqspi_read,
20
break;
34
.write_with_attrs = lqspi_write,
21
case SMMU_TRANS_ERROR:
35
.endianness = DEVICE_NATIVE_ENDIAN,
22
qemu_log_mask(LOG_GUEST_ERROR,
36
+ .impl = {
23
- "%s translation failed for iova=0x%"PRIx64"(%s)\n",
37
+ .min_access_size = 4,
24
+ "%s translation failed for iova=0x%"PRIx64" (%s)\n",
38
+ .max_access_size = 4,
25
mr->parent_obj.name, addr, smmu_event_string(event.type));
39
+ },
26
smmuv3_record_event(s, &event);
40
.valid = {
27
break;
41
.min_access_size = 1,
42
.max_access_size = 4
43
--
28
--
44
2.20.1
29
2.25.1
45
46
diff view generated by jsdifflib
New patch
[PULL 52/54] target/arm: Advertise support for FEAT_TTL
1
The Arm FEAT_TTL architectural feature allows the guest to provide an
2
optional hint in an AArch64 TLB invalidate operation about which
3
translation table level holds the leaf entry for the address being
4
invalidated. QEMU's TLB implementation doesn't need that hint, and
5
we correctly ignore the (previously RES0) bits in TLB invalidate
6
operation values that are now used for the TTL field. So we can
7
simply advertise support for it in our 'max' CPU.
1
8
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20220426160422.2353158-2-peter.maydell@linaro.org
12
---
13
docs/system/arm/emulation.rst | 1 +
14
target/arm/cpu64.c | 1 +
15
2 files changed, 2 insertions(+)
16
17
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
18
index XXXXXXX..XXXXXXX 100644
19
--- a/docs/system/arm/emulation.rst
20
+++ b/docs/system/arm/emulation.rst
21
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
22
- FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
23
- FEAT_TLBIRANGE (TLB invalidate range instructions)
24
- FEAT_TTCNP (Translation table Common not private translations)
25
+- FEAT_TTL (Translation Table Level)
26
- FEAT_TTST (Small translation tables)
27
- FEAT_UAO (Unprivileged Access Override control)
28
- FEAT_VHE (Virtualization Host Extensions)
29
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/cpu64.c
32
+++ b/target/arm/cpu64.c
33
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
34
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
35
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
36
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
37
+ t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
38
cpu->isar.id_aa64mmfr2 = t;
39
40
t = cpu->isar.id_aa64zfr0;
41
--
42
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/10] target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026
[PULL 53/54] target/arm: Advertise support for FEAT_BBM level 2
1
The ARMv5 architecture didn't specify detailed per-feature ID
1
The description in the Arm ARM of the requirements of FEAT_BBM is
2
registers. Now that we're using the MVFR0 register fields to
2
admirably clear on the guarantees it provides software, but slightly
3
gate the existence of VFP instructions, we need to set up
3
more obscure on what that means for implementations. The description
4
the correct values in the cpu->isar structure so that we still
4
of the equivalent SMMU feature in the SMMU specification (IHI0070D.b
5
provide an FPU to the guest.
5
section 3.21.1) is perhaps a bit more detailed and includes some
6
example valid implementation choices. (The SMMU version of this
7
feature is slightly tighter than the CPU version: the CPU is permitted
8
to raise TLB Conflict aborts in some situations that the SMMU may
9
not. This doesn't matter for QEMU because we don't want to do TLB
10
Conflict aborts anyway.)
6
11
7
This fixes a regression in the arm926 and arm1026 CPUs, which
12
The informal summary of FEAT_BBM is that it is about permitting an OS
8
are the only ones that both have VFP and are ARMv5 or earlier.
13
to switch a range of memory between "covered by a huge page" and
9
This regression was introduced by the VFP refactoring, and more
14
"covered by a sequence of normal pages" without having to engage in
10
specifically by commits 1120827fa182f0e76 and 266bd25c485597c,
15
the 'break-before-make' dance that has traditionally been
11
which accidentally disabled VFP short-vector support and
16
necessary. The 'break-before-make' sequence is:
12
double-precision support on these CPUs.
13
17
14
Fixes: 1120827fa182f0e
18
* replace the old translation table entry with an invalid entry
15
Fixes: 266bd25c485597c
19
* execute a DSB insn
16
Fixes: https://bugs.launchpad.net/qemu/+bug/1836192
20
* execute a broadcast TLB invalidate insn
17
Reported-by: Christophe Lyon <christophe.lyon@linaro.org>
21
* execute a DSB insn
22
* write the new translation table entry
23
* execute a DSB insn
24
25
The point of this is to ensure that no TLB can simultaneously contain
26
TLB entries for the old and the new entry, which would traditionally
27
be UNPREDICTABLE (allowing the CPU to generate a TLB Conflict fault
28
or to use a random mishmash of values from the old and the new
29
entry). FEAT_BBM level 2 says "for the specific case where the only
30
thing that changed is the size of the block, the TLB is guaranteed
31
not to do weird things even if there are multiple entries for an
32
address", which means that software can now do:
33
34
* replace old translation table entry with new entry
35
* DSB
36
* broadcast TLB invalidate
37
* DSB
38
39
As the SMMU spec notes, valid ways to do this include:
40
41
* if there are multiple entries in the TLB for an address,
42
choose one of them and use it, ignoring the others
43
* if there are multiple entries in the TLB for an address,
44
throw them all out and do a page table walk to get a new one
45
46
QEMU's page table walk implementation for Arm CPUs already meets the
47
requirements for FEAT_BBM level 2. When we cache an entry in our TCG
48
TLB, we do so only for the specific (non-huge) page that the address
49
is in, and there is no way for the TLB data structure to ever have
50
more than one TLB entry for that page. (We handle huge pages only in
51
that we track what part of the address space is covered by huge pages
52
so that a TLB invalidate operation for an address in a huge page
53
results in an invalidation of the whole TLB.) We ignore the Contiguous
54
bit in page table entries, so we don't have to do anything for the
55
parts of FEAT_BBM that deal with changis to the Contiguous bit.
56
57
FEAT_BBM level 2 also requires that the nT bit in block descriptors
58
must be ignored; since commit 39a1fd25287f5dece5 we do this.
59
60
It's therefore safe for QEMU to advertise FEAT_BBM level 2 by
61
setting ID_AA64MMFR2_EL1.BBM to 2.
62
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
63
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
64
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
65
Message-id: 20220426160422.2353158-3-peter.maydell@linaro.org
21
Tested-by: Christophe Lyon <christophe.lyon@linaro.org>
22
Message-id: 20190711131241.22231-1-peter.maydell@linaro.org
23
---
66
---
24
target/arm/cpu.c | 12 ++++++++++++
67
docs/system/arm/emulation.rst | 1 +
25
1 file changed, 12 insertions(+)
68
target/arm/cpu64.c | 1 +
69
2 files changed, 2 insertions(+)
26
70
27
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
71
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
28
index XXXXXXX..XXXXXXX 100644
72
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/cpu.c
73
--- a/docs/system/arm/emulation.rst
30
+++ b/target/arm/cpu.c
74
+++ b/docs/system/arm/emulation.rst
31
@@ -XXX,XX +XXX,XX @@ static void arm926_initfn(Object *obj)
75
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
32
* set the field to indicate Jazelle support within QEMU.
76
- FEAT_AA32HPD (AArch32 hierarchical permission disables)
33
*/
77
- FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
34
cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
78
- FEAT_AES (AESD and AESE instructions)
35
+ /*
79
+- FEAT_BBM at level 2 (Translation table break-before-make levels)
36
+ * Similarly, we need to set MVFR0 fields to enable double precision
80
- FEAT_BF16 (AArch64 BFloat16 instructions)
37
+ * and short vector support even though ARMv5 doesn't have this register.
81
- FEAT_BTI (Branch Target Identification)
38
+ */
82
- FEAT_DIT (Data Independent Timing instructions)
39
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
83
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
40
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
84
index XXXXXXX..XXXXXXX 100644
41
}
85
--- a/target/arm/cpu64.c
42
86
+++ b/target/arm/cpu64.c
43
static void arm946_initfn(Object *obj)
87
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
44
@@ -XXX,XX +XXX,XX @@ static void arm1026_initfn(Object *obj)
88
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
45
* set the field to indicate Jazelle support within QEMU.
89
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
46
*/
90
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
47
cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
91
+ t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
48
+ /*
92
cpu->isar.id_aa64mmfr2 = t;
49
+ * Similarly, we need to set MVFR0 fields to enable double precision
93
50
+ * and short vector support even though ARMv5 doesn't have this register.
94
t = cpu->isar.id_aa64zfr0;
51
+ */
52
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
53
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
54
55
{
56
/* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
57
--
95
--
58
2.20.1
96
2.25.1
59
60
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/10] target/arm: NS BusFault on vector table fetch escalates to NS HardFault
[PULL 54/54] hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2
1
In the M-profile architecture, when we do a vector table fetch and it
1
The Arm SMMUv3 includes an optional feature equivalent to the CPU
2
fails, we need to report a HardFault. Whether this is a Secure HF or
2
FEAT_BBM, which permits an OS to switch a range of memory between
3
a NonSecure HF depends on several things. If AIRCR.BFHFNMINS is 0
3
"covered by a huge page" and "covered by a sequence of normal pages"
4
then HF is always Secure, because there is no NonSecure HardFault.
4
without having to engage in the traditional 'break-before-make'
5
Otherwise, the answer depends on whether the 'underlying exception'
5
dance. (This is particularly important for the SMMU, because devices
6
(MemManage, BusFault, SecureFault) targets Secure or NonSecure. (In
6
performing I/O through an SMMU are less likely to be able to cope with
7
the pseudocode, this is handled in the Vector() function: the final
7
the window in the sequence where an access results in a translation
8
exc.isSecure is calculated by looking at the exc.isSecure from the
8
fault.) The SMMU spec explicitly notes that one of the valid ways to
9
exception returned from the memory access, not the isSecure input
9
be a BBM level 2 compliant implementation is:
10
argument.)
10
* if there are multiple entries in the TLB for an address,
11
choose one of them and use it, ignoring the others
11
12
12
We weren't doing this correctly, because we were looking at
13
Our SMMU TLB implementation (unlike our CPU TLB) does allow multiple
13
the target security domain of the exception we were trying to
14
TLB entries for an address, because the translation table level is
14
load the vector table entry for. This produces errors of two kinds:
15
part of the SMMUIOTLBKey, and so our IOTLB hashtable can include
15
* a load from the NS vector table which hits the "NS access
16
entries for the same address where the leaf was at different levels
16
to S memory" SecureFault should end up as a Secure HardFault,
17
(i.e. both hugepage and normal page). Our TLB lookup implementation in
17
but we were raising an NS HardFault
18
smmu_iotlb_lookup() will always find the entry with the lowest level
18
* a load from the S vector table which causes a BusFault
19
(i.e. it prefers the hugepage over the normal page) and ignore any
19
should raise an NS HardFault if BFHFNMINS == 1 (because
20
others. TLB invalidation correctly removes all TLB entries matching
20
in that case all BusFaults are NonSecure), but we were raising
21
the specified address or address range (unless the guest specifies the
21
a Secure HardFault
22
leaf level explicitly, in which case it gets what it asked for). So we
23
can validly advertise support for BBML level 2.
22
24
23
Correct the logic.
25
Note that we still can't yet advertise ourselves as an SMMU v3.2,
24
26
because v3.2 requires support for the S2FWB feature, which we don't
25
We also fix a comment error where we claimed that we might
27
yet implement.
26
be escalating MemManage to HardFault, and forgot about SecureFault.
27
(Vector loads can never hit MPU access faults, because they're
28
always aligned and always use the default address map.)
29
28
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
Message-id: 20190705094823.28905-1-peter.maydell@linaro.org
30
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
31
Reviewed-by: Eric Auger <eric.auger@redhat.com>
32
Message-id: 20220426160422.2353158-4-peter.maydell@linaro.org
32
---
33
---
33
target/arm/m_helper.c | 21 +++++++++++++++++----
34
hw/arm/smmuv3-internal.h | 1 +
34
1 file changed, 17 insertions(+), 4 deletions(-)
35
hw/arm/smmuv3.c | 1 +
36
2 files changed, 2 insertions(+)
35
37
36
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
38
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
37
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/m_helper.c
40
--- a/hw/arm/smmuv3-internal.h
39
+++ b/target/arm/m_helper.c
41
+++ b/hw/arm/smmuv3-internal.h
40
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
42
@@ -XXX,XX +XXX,XX @@ REG32(IDR2, 0x8)
41
if (sattrs.ns) {
43
REG32(IDR3, 0xc)
42
attrs.secure = false;
44
FIELD(IDR3, HAD, 2, 1);
43
} else if (!targets_secure) {
45
FIELD(IDR3, RIL, 10, 1);
44
- /* NS access to S memory */
46
+ FIELD(IDR3, BBML, 11, 2);
45
+ /*
47
REG32(IDR4, 0x10)
46
+ * NS access to S memory: the underlying exception which we escalate
48
REG32(IDR5, 0x14)
47
+ * to HardFault is SecureFault, which always targets Secure.
49
FIELD(IDR5, OAS, 0, 3);
48
+ */
50
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
49
+ exc_secure = true;
51
index XXXXXXX..XXXXXXX 100644
50
goto load_fail;
52
--- a/hw/arm/smmuv3.c
51
}
53
+++ b/hw/arm/smmuv3.c
52
}
54
@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
53
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
55
54
vector_entry = address_space_ldl(arm_addressspace(cs, attrs), addr,
56
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
55
attrs, &result);
57
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1);
56
if (result != MEMTX_OK) {
58
+ s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2);
57
+ /*
59
58
+ * Underlying exception is BusFault: its target security state
60
/* 4K, 16K and 64K granule support */
59
+ * depends on BFHFNMINS.
61
s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
60
+ */
61
+ exc_secure = !(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
62
goto load_fail;
63
}
64
*pvec = vector_entry;
65
@@ -XXX,XX +XXX,XX @@ load_fail:
66
/*
67
* All vector table fetch fails are reported as HardFault, with
68
* HFSR.VECTTBL and .FORCED set. (FORCED is set because
69
- * technically the underlying exception is a MemManage or BusFault
70
+ * technically the underlying exception is a SecureFault or BusFault
71
* that is escalated to HardFault.) This is a terminal exception,
72
* so we will either take the HardFault immediately or else enter
73
* lockup (the latter case is handled in armv7m_nvic_set_pending_derived()).
74
+ * The HardFault is Secure if BFHFNMINS is 0 (meaning that all HFs are
75
+ * secure); otherwise it targets the same security state as the
76
+ * underlying exception.
77
*/
78
- exc_secure = targets_secure ||
79
- !(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
80
+ if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
81
+ exc_secure = true;
82
+ }
83
env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK | R_V7M_HFSR_FORCED_MASK;
84
armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secure);
85
return false;
86
--
62
--
87
2.20.1
63
2.25.1
88
89
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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