1
target-arm queue for rc1 -- these are all bug fixes.
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Hi; here's the first target-arm pullreq for the 7.0 cycle.
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thanks
3
thanks
4
-- PMM
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-- PMM
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The following changes since commit b9404bf592e7ba74180e1a54ed7a266ec6ee67f2:
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The following changes since commit 76b56fdfc9fa43ec6e5986aee33f108c6c6a511e:
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Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20190715' into staging (2019-07-15 12:22:07 +0100)
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Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2021-12-14 12:46:18 -0800)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190715
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211215
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for you to fetch changes up to 51c9122e92b776a3f16af0b9282f1dc5012e2a19:
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for you to fetch changes up to aed176558806674d030a8305d989d4e6a5073359:
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target/arm: NS BusFault on vector table fetch escalates to NS HardFault (2019-07-15 14:17:04 +0100)
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tests/acpi: add expected blob for VIOT test on virt machine (2021-12-15 10:35:26 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
19
target-arm queue:
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target-arm queue:
20
* report ARMv8-A FP support for AArch32 -cpu max
20
* ITS: error reporting cleanup
21
* hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
21
* aspeed: improve documentation
22
* hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
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* Fix STM32F2XX USART data register readout
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* hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
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* allow emulated GICv3 to be disabled in non-TCG builds
24
* hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
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* fix exception priority for singlestep, misaligned PC, bp, etc
25
* hw/arm/virt: Fix non-secure flash mode
25
* Correct calculation of tlb range invalidate length
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* pl031: Correctly migrate state when using -rtc clock=host
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* npcm7xx_emc: fix missing queue_flush
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* fix regression that meant arm926 and arm1026 lost VFP
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* virt: Add VIOT ACPI table for virtio-iommu
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double-precision support
28
* target/i386: Use assert() to sanity-check b1 in SSE decode
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* v8M: NS BusFault on vector table fetch escalates to NS HardFault
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* Don't include qemu-common unnecessarily
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----------------------------------------------------------------
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----------------------------------------------------------------
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Alex Bennée (1):
32
Alex Bennée (1):
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target/arm: report ARMv8-A FP support for AArch32 -cpu max
33
hw/intc: clean-up error reporting for failed ITS cmd
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34
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David Engraf (1):
35
Jean-Philippe Brucker (8):
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hw/arm/virt: Fix non-secure flash mode
36
hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu
37
hw/arm/virt: Remove device tree restriction for virtio-iommu
38
hw/arm/virt: Reject instantiation of multiple IOMMUs
39
hw/arm/virt: Use object_property_set instead of qdev_prop_set
40
tests/acpi: allow updates of VIOT expected data files
41
tests/acpi: add test case for VIOT
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tests/acpi: add expected blobs for VIOT test on q35 machine
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tests/acpi: add expected blob for VIOT test on virt machine
37
44
38
Peter Maydell (3):
45
Joel Stanley (4):
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pl031: Correctly migrate state when using -rtc clock=host
46
docs: aspeed: Add new boards
40
target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026
47
docs: aspeed: Update OpenBMC image URL
41
target/arm: NS BusFault on vector table fetch escalates to NS HardFault
48
docs: aspeed: Give an example of booting a kernel
49
docs: aspeed: ADC is now modelled
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43
Philippe Mathieu-Daudé (5):
51
Olivier Hériveaux (1):
44
hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs
52
Fix STM32F2XX USART data register readout
45
hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
46
hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
47
hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
48
hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
49
53
50
include/hw/timer/pl031.h | 2 ++
54
Patrick Venture (1):
51
hw/arm/virt.c | 2 +-
55
hw/net: npcm7xx_emc fix missing queue_flush
52
hw/core/machine.c | 1 +
53
hw/display/xlnx_dp.c | 15 +++++---
54
hw/ssi/mss-spi.c | 8 ++++-
55
hw/ssi/xilinx_spips.c | 43 +++++++++++++++-------
56
hw/timer/pl031.c | 92 +++++++++++++++++++++++++++++++++++++++++++++---
57
target/arm/cpu.c | 16 +++++++++
58
target/arm/m_helper.c | 21 ++++++++---
59
9 files changed, 174 insertions(+), 26 deletions(-)
60
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Peter Maydell (6):
58
target/i386: Use assert() to sanity-check b1 in SSE decode
59
include/hw/i386: Don't include qemu-common.h in .h files
60
target/hexagon/cpu.h: don't include qemu-common.h
61
target/rx/cpu.h: Don't include qemu-common.h
62
hw/arm: Don't include qemu-common.h unnecessarily
63
target/arm: Correct calculation of tlb range invalidate length
64
65
Philippe Mathieu-Daudé (2):
66
hw/intc/arm_gicv3: Extract gicv3_set_gicv3state from arm_gicv3_cpuif.c
67
hw/intc/arm_gicv3: Introduce CONFIG_ARM_GIC_TCG Kconfig selector
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Richard Henderson (10):
70
target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn
71
target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn
72
target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn
73
target/arm: Split arm_pre_translate_insn
74
target/arm: Advance pc for arch single-step exception
75
target/arm: Split compute_fsr_fsc out of arm_deliver_fault
76
target/arm: Take an exception if PC is misaligned
77
target/arm: Assert thumb pc is aligned
78
target/arm: Suppress bp for exceptions with more priority
79
tests/tcg: Add arm and aarch64 pc alignment tests
80
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docs/system/arm/aspeed.rst | 26 ++++++++++++----
82
include/hw/i386/microvm.h | 1 -
83
include/hw/i386/x86.h | 1 -
84
target/arm/helper.h | 1 +
85
target/arm/syndrome.h | 5 +++
86
target/hexagon/cpu.h | 1 -
87
target/rx/cpu.h | 1 -
88
hw/arm/boot.c | 1 -
89
hw/arm/digic_boards.c | 1 -
90
hw/arm/highbank.c | 1 -
91
hw/arm/npcm7xx_boards.c | 1 -
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hw/arm/sbsa-ref.c | 1 -
93
hw/arm/stm32f405_soc.c | 1 -
94
hw/arm/vexpress.c | 1 -
95
hw/arm/virt-acpi-build.c | 7 +++++
96
hw/arm/virt.c | 21 ++++++-------
97
hw/char/stm32f2xx_usart.c | 3 +-
98
hw/intc/arm_gicv3.c | 2 +-
99
hw/intc/arm_gicv3_cpuif.c | 10 +-----
100
hw/intc/arm_gicv3_cpuif_common.c | 22 +++++++++++++
101
hw/intc/arm_gicv3_its.c | 39 +++++++++++++++--------
102
hw/net/npcm7xx_emc.c | 18 +++++------
103
hw/virtio/virtio-iommu-pci.c | 12 ++------
104
linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++------------
105
linux-user/hexagon/cpu_loop.c | 1 +
106
target/arm/debug_helper.c | 23 ++++++++++++++
107
target/arm/gdbstub.c | 9 ++++--
108
target/arm/helper.c | 6 ++--
109
target/arm/machine.c | 10 ++++++
110
target/arm/tlb_helper.c | 63 ++++++++++++++++++++++++++++----------
111
target/arm/translate-a64.c | 23 ++++++++++++--
112
target/arm/translate.c | 58 ++++++++++++++++++++++++++---------
113
target/i386/tcg/translate.c | 12 ++------
114
tests/qtest/bios-tables-test.c | 38 +++++++++++++++++++++++
115
tests/tcg/aarch64/pcalign-a64.c | 37 ++++++++++++++++++++++
116
tests/tcg/arm/pcalign-a32.c | 46 ++++++++++++++++++++++++++++
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hw/arm/Kconfig | 1 +
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hw/intc/Kconfig | 5 +++
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hw/intc/meson.build | 11 ++++---
120
tests/data/acpi/q35/DSDT.viot | Bin 0 -> 9398 bytes
121
tests/data/acpi/q35/VIOT.viot | Bin 0 -> 112 bytes
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tests/data/acpi/virt/VIOT | Bin 0 -> 88 bytes
123
tests/tcg/aarch64/Makefile.target | 4 +--
124
tests/tcg/arm/Makefile.target | 4 +++
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44 files changed, 429 insertions(+), 145 deletions(-)
126
create mode 100644 hw/intc/arm_gicv3_cpuif_common.c
127
create mode 100644 tests/tcg/aarch64/pcalign-a64.c
128
create mode 100644 tests/tcg/arm/pcalign-a32.c
129
create mode 100644 tests/data/acpi/q35/DSDT.viot
130
create mode 100644 tests/data/acpi/q35/VIOT.viot
131
create mode 100644 tests/data/acpi/virt/VIOT
132
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
When we converted to using feature bits in 602f6e42cfbf we missed out
3
While trying to debug a GIC ITS failure I saw some guest errors that
4
the fact (dp && arm_dc_feature(s, ARM_FEATURE_V8)) was supported for
4
had poor formatting as well as leaving me confused as to what failed.
5
-cpu max configurations. This caused a regression in the GCC test
5
As most of the checks aren't possible without a valid dte split that
6
suite. Fix this by setting the appropriate bits in mvfr1.FPHP to
6
check apart and then check the other conditions in steps. This avoids
7
report ARMv8-A with FP support (but not ARMv8.2-FP16).
7
us relying on undefined data.
8
8
9
Fixes: https://bugs.launchpad.net/qemu/+bug/1836078
9
I still get a failure with the current kvm-unit-tests but at least I
10
know (partially) why now:
11
12
Exception return from AArch64 EL1 to AArch64 EL1 PC 0x40080588
13
PASS: gicv3: its-trigger: inv/invall: dev2/eventid=20 now triggers an LPI
14
ITS: MAPD devid=2 size = 0x8 itt=0x40430000 valid=0
15
INT dev_id=2 event_id=20
16
process_its_cmd: invalid command attributes: invalid dte: 0 for 2 (MEM_TX: 0)
17
PASS: gicv3: its-trigger: mapd valid=false: no LPI after device unmap
18
SUMMARY: 6 tests, 1 unexpected failures
19
10
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
20
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20190711103737.10017-1-alex.bennee@linaro.org
22
Message-id: 20211112170454.3158925-1-alex.bennee@linaro.org
23
Cc: Shashi Mallela <shashi.mallela@linaro.org>
24
Cc: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
26
---
15
target/arm/cpu.c | 4 ++++
27
hw/intc/arm_gicv3_its.c | 39 +++++++++++++++++++++++++++------------
16
1 file changed, 4 insertions(+)
28
1 file changed, 27 insertions(+), 12 deletions(-)
17
29
18
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
30
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
19
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.c
32
--- a/hw/intc/arm_gicv3_its.c
21
+++ b/target/arm/cpu.c
33
+++ b/hw/intc/arm_gicv3_its.c
22
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
34
@@ -XXX,XX +XXX,XX @@ static bool process_its_cmd(GICv3ITSState *s, uint64_t value, uint32_t offset,
23
t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
35
if (res != MEMTX_OK) {
24
cpu->isar.id_isar6 = t;
36
return result;
25
37
}
26
+ t = cpu->isar.mvfr1;
38
+ } else {
27
+ t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */
39
+ qemu_log_mask(LOG_GUEST_ERROR,
28
+ cpu->isar.mvfr1 = t;
40
+ "%s: invalid command attributes: "
41
+ "invalid dte: %"PRIx64" for %d (MEM_TX: %d)\n",
42
+ __func__, dte, devid, res);
43
+ return result;
44
}
45
46
- if ((devid > s->dt.maxids.max_devids) || !dte_valid || !ite_valid ||
47
- !cte_valid || (eventid > max_eventid)) {
29
+
48
+
30
t = cpu->isar.mvfr2;
49
+ /*
31
t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
50
+ * In this implementation, in case of guest errors we ignore the
32
t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
51
+ * command and move onto the next command in the queue.
52
+ */
53
+ if (devid > s->dt.maxids.max_devids) {
54
qemu_log_mask(LOG_GUEST_ERROR,
55
- "%s: invalid command attributes "
56
- "devid %d or eventid %d or invalid dte %d or"
57
- "invalid cte %d or invalid ite %d\n",
58
- __func__, devid, eventid, dte_valid, cte_valid,
59
- ite_valid);
60
- /*
61
- * in this implementation, in case of error
62
- * we ignore this command and move onto the next
63
- * command in the queue
64
- */
65
+ "%s: invalid command attributes: devid %d>%d",
66
+ __func__, devid, s->dt.maxids.max_devids);
67
+
68
+ } else if (!dte_valid || !ite_valid || !cte_valid) {
69
+ qemu_log_mask(LOG_GUEST_ERROR,
70
+ "%s: invalid command attributes: "
71
+ "dte: %s, ite: %s, cte: %s\n",
72
+ __func__,
73
+ dte_valid ? "valid" : "invalid",
74
+ ite_valid ? "valid" : "invalid",
75
+ cte_valid ? "valid" : "invalid");
76
+ } else if (eventid > max_eventid) {
77
+ qemu_log_mask(LOG_GUEST_ERROR,
78
+ "%s: invalid command attributes: eventid %d > %d\n",
79
+ __func__, eventid, max_eventid);
80
} else {
81
/*
82
* Current implementation only supports rdbase == procnum
33
--
83
--
34
2.20.1
84
2.25.1
35
85
36
86
diff view generated by jsdifflib
New patch
1
From: Joel Stanley <joel@jms.id.au>
1
2
3
Add X11, FP5280G2, G220A, Rainier and Fuji. Mention that Swift will be
4
removed in v7.0.
5
6
Signed-off-by: Joel Stanley <joel@jms.id.au>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: 20211117065752.330632-2-joel@jms.id.au
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
docs/system/arm/aspeed.rst | 7 ++++++-
12
1 file changed, 6 insertions(+), 1 deletion(-)
13
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
15
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/aspeed.rst
17
+++ b/docs/system/arm/aspeed.rst
18
@@ -XXX,XX +XXX,XX @@ AST2400 SoC based machines :
19
20
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
21
- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
22
+- ``supermicrox11-bmc`` Supermicro X11 BMC
23
24
AST2500 SoC based machines :
25
26
@@ -XXX,XX +XXX,XX @@ AST2500 SoC based machines :
27
- ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC
28
- ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC
29
- ``sonorapass-bmc`` OCP SonoraPass BMC
30
-- ``swift-bmc`` OpenPOWER Swift BMC POWER9
31
+- ``swift-bmc`` OpenPOWER Swift BMC POWER9 (to be removed in v7.0)
32
+- ``fp5280g2-bmc`` Inspur FP5280G2 BMC
33
+- ``g220a-bmc`` Bytedance G220A BMC
34
35
AST2600 SoC based machines :
36
37
- ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex-A7)
38
- ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC
39
+- ``rainier-bmc`` IBM Rainier POWER10 BMC
40
+- ``fuji-bmc`` Facebook Fuji BMC
41
42
Supported devices
43
-----------------
44
--
45
2.25.1
46
47
diff view generated by jsdifflib
New patch
1
From: Joel Stanley <joel@jms.id.au>
1
2
3
This is the latest URL for the OpenBMC CI. The old URL still works, but
4
redirects.
5
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
7
Signed-off-by: Joel Stanley <joel@jms.id.au>
8
Message-id: 20211117065752.330632-3-joel@jms.id.au
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
docs/system/arm/aspeed.rst | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
15
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/aspeed.rst
17
+++ b/docs/system/arm/aspeed.rst
18
@@ -XXX,XX +XXX,XX @@ The Aspeed machines can be started using the ``-kernel`` option to
19
load a Linux kernel or from a firmware. Images can be downloaded from
20
the OpenBMC jenkins :
21
22
- https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/distro=ubuntu,label=docker-builder
23
+ https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/
24
25
or directly from the OpenBMC GitHub release repository :
26
27
--
28
2.25.1
29
30
diff view generated by jsdifflib
New patch
1
From: Joel Stanley <joel@jms.id.au>
1
2
3
A common use case for the ASPEED machine is to boot a Linux kernel.
4
Provide a full example command line.
5
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
7
Signed-off-by: Joel Stanley <joel@jms.id.au>
8
Message-id: 20211117065752.330632-4-joel@jms.id.au
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
docs/system/arm/aspeed.rst | 15 ++++++++++++---
12
1 file changed, 12 insertions(+), 3 deletions(-)
13
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
15
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/aspeed.rst
17
+++ b/docs/system/arm/aspeed.rst
18
@@ -XXX,XX +XXX,XX @@ Missing devices
19
Boot options
20
------------
21
22
-The Aspeed machines can be started using the ``-kernel`` option to
23
-load a Linux kernel or from a firmware. Images can be downloaded from
24
-the OpenBMC jenkins :
25
+The Aspeed machines can be started using the ``-kernel`` and ``-dtb`` options
26
+to load a Linux kernel or from a firmware. Images can be downloaded from the
27
+OpenBMC jenkins :
28
29
https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/
30
31
@@ -XXX,XX +XXX,XX @@ or directly from the OpenBMC GitHub release repository :
32
33
https://github.com/openbmc/openbmc/releases
34
35
+To boot a kernel directly from a Linux build tree:
36
+
37
+.. code-block:: bash
38
+
39
+ $ qemu-system-arm -M ast2600-evb -nographic \
40
+ -kernel arch/arm/boot/zImage \
41
+ -dtb arch/arm/boot/dts/aspeed-ast2600-evb.dtb \
42
+ -initrd rootfs.cpio
43
+
44
The image should be attached as an MTD drive. Run :
45
46
.. code-block:: bash
47
--
48
2.25.1
49
50
diff view generated by jsdifflib
New patch
1
From: Joel Stanley <joel@jms.id.au>
1
2
3
Move it to the supported list.
4
5
Signed-off-by: Joel Stanley <joel@jms.id.au>
6
Message-id: 20211117065752.330632-5-joel@jms.id.au
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
docs/system/arm/aspeed.rst | 2 +-
10
1 file changed, 1 insertion(+), 1 deletion(-)
11
12
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
13
index XXXXXXX..XXXXXXX 100644
14
--- a/docs/system/arm/aspeed.rst
15
+++ b/docs/system/arm/aspeed.rst
16
@@ -XXX,XX +XXX,XX @@ Supported devices
17
* Front LEDs (PCA9552 on I2C bus)
18
* LPC Peripheral Controller (a subset of subdevices are supported)
19
* Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA
20
+ * ADC
21
22
23
Missing devices
24
---------------
25
26
* Coprocessor support
27
- * ADC (out of tree implementation)
28
* PWM and Fan Controller
29
* Slave GPIO Controller
30
* Super I/O Controller
31
--
32
2.25.1
33
34
diff view generated by jsdifflib
New patch
1
From: Olivier Hériveaux <olivier.heriveaux@ledger.fr>
1
2
3
Fix issue where the data register may be overwritten by next character
4
reception before being read and returned.
5
6
Signed-off-by: Olivier Hériveaux <olivier.heriveaux@ledger.fr>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20211128120723.4053-1-olivier.heriveaux@ledger.fr
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/char/stm32f2xx_usart.c | 3 ++-
13
1 file changed, 2 insertions(+), 1 deletion(-)
14
15
diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/char/stm32f2xx_usart.c
18
+++ b/hw/char/stm32f2xx_usart.c
19
@@ -XXX,XX +XXX,XX @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
20
return retvalue;
21
case USART_DR:
22
DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
23
+ retvalue = s->usart_dr & 0x3FF;
24
s->usart_sr &= ~USART_SR_RXNE;
25
qemu_chr_fe_accept_input(&s->chr);
26
qemu_set_irq(s->irq, 0);
27
- return s->usart_dr & 0x3FF;
28
+ return retvalue;
29
case USART_BRR:
30
return s->usart_brr;
31
case USART_CR1:
32
--
33
2.25.1
34
35
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
In the previous commit we fixed a crash when the guest read a
3
gicv3_set_gicv3state() is used by arm_gicv3_common.c in
4
register that pop from an empty FIFO.
4
arm_gicv3_common_realize(). Since we want to restrict
5
By auditing the repository, we found another similar use with
5
arm_gicv3_cpuif.c to TCG, extract gicv3_set_gicv3state()
6
an easy way to reproduce:
6
to a new file. Add this file to the meson 'specific'
7
7
source set, since it needs access to "cpu.h".
8
$ qemu-system-aarch64 -M xlnx-zcu102 -monitor stdio -S
9
QEMU 4.0.50 monitor - type 'help' for more information
10
(qemu) xp/b 0xfd4a0134
11
Aborted (core dumped)
12
13
(gdb) bt
14
#0 0x00007f6936dea57f in raise () at /lib64/libc.so.6
15
#1 0x00007f6936dd4895 in abort () at /lib64/libc.so.6
16
#2 0x0000561ad32975ec in xlnx_dp_aux_pop_rx_fifo (s=0x7f692babee70) at hw/display/xlnx_dp.c:431
17
#3 0x0000561ad3297dc0 in xlnx_dp_read (opaque=0x7f692babee70, offset=77, size=4) at hw/display/xlnx_dp.c:667
18
#4 0x0000561ad321b896 in memory_region_read_accessor (mr=0x7f692babf620, addr=308, value=0x7ffe05c1db88, size=4, shift=0, mask=4294967295, attrs=...) at memory.c:439
19
#5 0x0000561ad321bd70 in access_with_adjusted_size (addr=308, value=0x7ffe05c1db88, size=1, access_size_min=4, access_size_max=4, access_fn=0x561ad321b858 <memory_region_read_accessor>, mr=0x7f692babf620, attrs=...) at memory.c:569
20
#6 0x0000561ad321e9d5 in memory_region_dispatch_read1 (mr=0x7f692babf620, addr=308, pval=0x7ffe05c1db88, size=1, attrs=...) at memory.c:1420
21
#7 0x0000561ad321ea9d in memory_region_dispatch_read (mr=0x7f692babf620, addr=308, pval=0x7ffe05c1db88, size=1, attrs=...) at memory.c:1447
22
#8 0x0000561ad31bd742 in flatview_read_continue (fv=0x561ad69c04f0, addr=4249485620, attrs=..., buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", len=1, addr1=308, l=1, mr=0x7f692babf620) at exec.c:3385
23
#9 0x0000561ad31bd895 in flatview_read (fv=0x561ad69c04f0, addr=4249485620, attrs=..., buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", len=1) at exec.c:3423
24
#10 0x0000561ad31bd90b in address_space_read_full (as=0x561ad5bb3020, addr=4249485620, attrs=..., buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", len=1) at exec.c:3436
25
#11 0x0000561ad33b1c42 in address_space_read (len=1, buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", attrs=..., addr=4249485620, as=0x561ad5bb3020) at include/exec/memory.h:2131
26
#12 0x0000561ad33b1c42 in memory_dump (mon=0x561ad59c4530, count=1, format=120, wsize=1, addr=4249485620, is_physical=1) at monitor/misc.c:723
27
#13 0x0000561ad33b1fc1 in hmp_physical_memory_dump (mon=0x561ad59c4530, qdict=0x561ad6c6fd00) at monitor/misc.c:795
28
#14 0x0000561ad37b4a9f in handle_hmp_command (mon=0x561ad59c4530, cmdline=0x561ad59d0f22 "/b 0x00000000fd4a0134") at monitor/hmp.c:1082
29
30
Fix by checking the FIFO is not empty before popping from it.
31
32
The datasheet is not clear about the reset value of this register,
33
we choose to return '0'.
34
8
35
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
36
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
37
Message-id: 20190709113715.7761-4-philmd@redhat.com
11
Message-id: 20211115223619.2599282-2-philmd@redhat.com
38
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
39
---
13
---
40
hw/display/xlnx_dp.c | 15 +++++++++++----
14
hw/intc/arm_gicv3_cpuif.c | 10 +---------
41
1 file changed, 11 insertions(+), 4 deletions(-)
15
hw/intc/arm_gicv3_cpuif_common.c | 22 ++++++++++++++++++++++
16
hw/intc/meson.build | 1 +
17
3 files changed, 24 insertions(+), 9 deletions(-)
18
create mode 100644 hw/intc/arm_gicv3_cpuif_common.c
42
19
43
diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c
20
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
44
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/display/xlnx_dp.c
22
--- a/hw/intc/arm_gicv3_cpuif.c
46
+++ b/hw/display/xlnx_dp.c
23
+++ b/hw/intc/arm_gicv3_cpuif.c
47
@@ -XXX,XX +XXX,XX @@ static uint8_t xlnx_dp_aux_pop_rx_fifo(XlnxDPState *s)
24
@@ -XXX,XX +XXX,XX @@
48
uint8_t ret;
25
/*
49
26
- * ARM Generic Interrupt Controller v3
50
if (fifo8_is_empty(&s->rx_fifo)) {
27
+ * ARM Generic Interrupt Controller v3 (emulation)
51
- DPRINTF("rx_fifo underflow..\n");
28
*
52
- abort();
29
* Copyright (c) 2016 Linaro Limited
53
+ qemu_log_mask(LOG_GUEST_ERROR,
30
* Written by Peter Maydell
54
+ "%s: Reading empty RX_FIFO\n",
31
@@ -XXX,XX +XXX,XX @@
55
+ __func__);
32
#include "hw/irq.h"
56
+ /*
33
#include "cpu.h"
57
+ * The datasheet is not clear about the reset value, it seems
34
58
+ * to be unspecified. We choose to return '0'.
35
-void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
59
+ */
36
-{
60
+ ret = 0;
37
- ARMCPU *arm_cpu = ARM_CPU(cpu);
61
+ } else {
38
- CPUARMState *env = &arm_cpu->env;
62
+ ret = fifo8_pop(&s->rx_fifo);
39
-
63
+ DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret);
40
- env->gicv3state = (void *)s;
64
}
41
-};
65
- ret = fifo8_pop(&s->rx_fifo);
42
-
66
- DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret);
43
static GICv3CPUState *icc_cs_from_env(CPUARMState *env)
67
return ret;
44
{
68
}
45
return env->gicv3state;
69
46
diff --git a/hw/intc/arm_gicv3_cpuif_common.c b/hw/intc/arm_gicv3_cpuif_common.c
47
new file mode 100644
48
index XXXXXXX..XXXXXXX
49
--- /dev/null
50
+++ b/hw/intc/arm_gicv3_cpuif_common.c
51
@@ -XXX,XX +XXX,XX @@
52
+/* SPDX-License-Identifier: GPL-2.0-or-later */
53
+/*
54
+ * ARM Generic Interrupt Controller v3
55
+ *
56
+ * Copyright (c) 2016 Linaro Limited
57
+ * Written by Peter Maydell
58
+ *
59
+ * This code is licensed under the GPL, version 2 or (at your option)
60
+ * any later version.
61
+ */
62
+
63
+#include "qemu/osdep.h"
64
+#include "gicv3_internal.h"
65
+#include "cpu.h"
66
+
67
+void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
68
+{
69
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
70
+ CPUARMState *env = &arm_cpu->env;
71
+
72
+ env->gicv3state = (void *)s;
73
+};
74
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
75
index XXXXXXX..XXXXXXX 100644
76
--- a/hw/intc/meson.build
77
+++ b/hw/intc/meson.build
78
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in
79
80
specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c'))
81
specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c'))
82
+specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c'))
83
specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c'))
84
specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'))
85
specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
70
--
86
--
71
2.20.1
87
2.25.1
72
88
73
89
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
Reading the RX_DATA register when the RX_FIFO is empty triggers
3
The TYPE_ARM_GICV3 device is an emulated one. When using
4
an abort. This can be easily reproduced:
4
KVM, it is recommended to use the TYPE_KVM_ARM_GICV3 device
5
(which uses in-kernel support).
5
6
6
$ qemu-system-arm -M emcraft-sf2 -monitor stdio -S
7
When using --with-devices-FOO, it is possible to build a
7
QEMU 4.0.50 monitor - type 'help' for more information
8
binary with a specific set of devices. When this binary is
8
(qemu) x 0x40001010
9
restricted to KVM accelerator, the TYPE_ARM_GICV3 device is
9
Aborted (core dumped)
10
irrelevant, and it is desirable to remove it from the binary.
10
11
11
(gdb) bt
12
Therefore introduce the CONFIG_ARM_GIC_TCG Kconfig selector
12
#1 0x00007f035874f895 in abort () at /lib64/libc.so.6
13
which select the files required to have the TYPE_ARM_GICV3
13
#2 0x00005628686591ff in fifo8_pop (fifo=0x56286a9a4c68) at util/fifo8.c:66
14
device, but also allowing to de-select this device.
14
#3 0x00005628683e0b8e in fifo32_pop (fifo=0x56286a9a4c68) at include/qemu/fifo32.h:137
15
#4 0x00005628683e0efb in spi_read (opaque=0x56286a9a4850, addr=4, size=4) at hw/ssi/mss-spi.c:168
16
#5 0x0000562867f96801 in memory_region_read_accessor (mr=0x56286a9a4b60, addr=16, value=0x7ffeecb0c5c8, size=4, shift=0, mask=4294967295, attrs=...) at memory.c:439
17
#6 0x0000562867f96cdb in access_with_adjusted_size (addr=16, value=0x7ffeecb0c5c8, size=4, access_size_min=1, access_size_max=4, access_fn=0x562867f967c3 <memory_region_read_accessor>, mr=0x56286a9a4b60, attrs=...) at memory.c:569
18
#7 0x0000562867f99940 in memory_region_dispatch_read1 (mr=0x56286a9a4b60, addr=16, pval=0x7ffeecb0c5c8, size=4, attrs=...) at memory.c:1420
19
#8 0x0000562867f99a08 in memory_region_dispatch_read (mr=0x56286a9a4b60, addr=16, pval=0x7ffeecb0c5c8, size=4, attrs=...) at memory.c:1447
20
#9 0x0000562867f38721 in flatview_read_continue (fv=0x56286aec6360, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4, addr1=16, l=4, mr=0x56286a9a4b60) at exec.c:3385
21
#10 0x0000562867f38874 in flatview_read (fv=0x56286aec6360, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4) at exec.c:3423
22
#11 0x0000562867f388ea in address_space_read_full (as=0x56286aa3e890, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4) at exec.c:3436
23
#12 0x0000562867f389c5 in address_space_rw (as=0x56286aa3e890, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4, is_write=false) at exec.c:3466
24
#13 0x0000562867f3bdd7 in cpu_memory_rw_debug (cpu=0x56286aa19d00, addr=1073745936, buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4, is_write=0) at exec.c:3976
25
#14 0x000056286811ed51 in memory_dump (mon=0x56286a8c32d0, count=1, format=120, wsize=4, addr=1073745936, is_physical=0) at monitor/misc.c:730
26
#15 0x000056286811eff1 in hmp_memory_dump (mon=0x56286a8c32d0, qdict=0x56286b15c400) at monitor/misc.c:785
27
#16 0x00005628684740ee in handle_hmp_command (mon=0x56286a8c32d0, cmdline=0x56286a8caeb2 "0x40001010") at monitor/hmp.c:1082
28
29
From the datasheet "Actel SmartFusion Microcontroller Subsystem
30
User's Guide" Rev.1, Table 13-3 "SPI Register Summary", this
31
register has a reset value of 0.
32
33
Check the FIFO is not empty before accessing it, else log an
34
error message.
35
15
36
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
16
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
37
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
38
Message-id: 20190709113715.7761-3-philmd@redhat.com
18
Message-id: 20211115223619.2599282-3-philmd@redhat.com
39
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
40
---
20
---
41
hw/ssi/mss-spi.c | 8 +++++++-
21
hw/intc/arm_gicv3.c | 2 +-
42
1 file changed, 7 insertions(+), 1 deletion(-)
22
hw/intc/Kconfig | 5 +++++
23
hw/intc/meson.build | 10 ++++++----
24
3 files changed, 12 insertions(+), 5 deletions(-)
43
25
44
diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
26
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
45
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/ssi/mss-spi.c
28
--- a/hw/intc/arm_gicv3.c
47
+++ b/hw/ssi/mss-spi.c
29
+++ b/hw/intc/arm_gicv3.c
48
@@ -XXX,XX +XXX,XX @@ spi_read(void *opaque, hwaddr addr, unsigned int size)
30
@@ -XXX,XX +XXX,XX @@
49
case R_SPI_RX:
31
/*
50
s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
32
- * ARM Generic Interrupt Controller v3
51
s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF;
33
+ * ARM Generic Interrupt Controller v3 (emulation)
52
- ret = fifo32_pop(&s->rx_fifo);
34
*
53
+ if (fifo32_is_empty(&s->rx_fifo)) {
35
* Copyright (c) 2015 Huawei.
54
+ qemu_log_mask(LOG_GUEST_ERROR,
36
* Copyright (c) 2016 Linaro Limited
55
+ "%s: Reading empty RX_FIFO\n",
37
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
56
+ __func__);
38
index XXXXXXX..XXXXXXX 100644
57
+ } else {
39
--- a/hw/intc/Kconfig
58
+ ret = fifo32_pop(&s->rx_fifo);
40
+++ b/hw/intc/Kconfig
59
+ }
41
@@ -XXX,XX +XXX,XX @@ config APIC
60
if (fifo32_is_empty(&s->rx_fifo)) {
42
select MSI_NONBROKEN
61
s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
43
select I8259
62
}
44
45
+config ARM_GIC_TCG
46
+ bool
47
+ default y
48
+ depends on ARM_GIC && TCG
49
+
50
config ARM_GIC_KVM
51
bool
52
default y
53
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
54
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/intc/meson.build
56
+++ b/hw/intc/meson.build
57
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files(
58
'arm_gic.c',
59
'arm_gic_common.c',
60
'arm_gicv2m.c',
61
- 'arm_gicv3.c',
62
'arm_gicv3_common.c',
63
- 'arm_gicv3_dist.c',
64
'arm_gicv3_its_common.c',
65
- 'arm_gicv3_redist.c',
66
+))
67
+softmmu_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files(
68
+ 'arm_gicv3.c',
69
+ 'arm_gicv3_dist.c',
70
'arm_gicv3_its.c',
71
+ 'arm_gicv3_redist.c',
72
))
73
softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_pic.c'))
74
softmmu_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true: files('heathrow_pic.c'))
75
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in
76
specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c'))
77
specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c'))
78
specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c'))
79
-specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c'))
80
+specific_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files('arm_gicv3_cpuif.c'))
81
specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'))
82
specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
83
specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
63
--
84
--
64
2.20.1
85
2.25.1
65
86
66
87
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
---
7
target/arm/translate-a64.c | 7 ++++---
8
1 file changed, 4 insertions(+), 3 deletions(-)
9
10
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/arm/translate-a64.c
13
+++ b/target/arm/translate-a64.c
14
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
15
{
16
DisasContext *s = container_of(dcbase, DisasContext, base);
17
CPUARMState *env = cpu->env_ptr;
18
+ uint64_t pc = s->base.pc_next;
19
uint32_t insn;
20
21
if (s->ss_active && !s->pstate_ss) {
22
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
23
return;
24
}
25
26
- s->pc_curr = s->base.pc_next;
27
- insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b);
28
+ s->pc_curr = pc;
29
+ insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b);
30
s->insn = insn;
31
- s->base.pc_next += 4;
32
+ s->base.pc_next = pc + 4;
33
34
s->fp_access_checked = false;
35
s->sve_access_checked = false;
36
--
37
2.25.1
38
39
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
---
7
target/arm/translate.c | 9 +++++----
8
1 file changed, 5 insertions(+), 4 deletions(-)
9
10
diff --git a/target/arm/translate.c b/target/arm/translate.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/arm/translate.c
13
+++ b/target/arm/translate.c
14
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
15
{
16
DisasContext *dc = container_of(dcbase, DisasContext, base);
17
CPUARMState *env = cpu->env_ptr;
18
+ uint32_t pc = dc->base.pc_next;
19
unsigned int insn;
20
21
if (arm_pre_translate_insn(dc)) {
22
- dc->base.pc_next += 4;
23
+ dc->base.pc_next = pc + 4;
24
return;
25
}
26
27
- dc->pc_curr = dc->base.pc_next;
28
- insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
29
+ dc->pc_curr = pc;
30
+ insn = arm_ldl_code(env, &dc->base, pc, dc->sctlr_b);
31
dc->insn = insn;
32
- dc->base.pc_next += 4;
33
+ dc->base.pc_next = pc + 4;
34
disas_arm_insn(dc, insn);
35
36
arm_post_translate_insn(dc);
37
--
38
2.25.1
39
40
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
---
7
target/arm/translate.c | 16 ++++++++--------
8
1 file changed, 8 insertions(+), 8 deletions(-)
9
10
diff --git a/target/arm/translate.c b/target/arm/translate.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/arm/translate.c
13
+++ b/target/arm/translate.c
14
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
15
{
16
DisasContext *dc = container_of(dcbase, DisasContext, base);
17
CPUARMState *env = cpu->env_ptr;
18
+ uint32_t pc = dc->base.pc_next;
19
uint32_t insn;
20
bool is_16bit;
21
22
if (arm_pre_translate_insn(dc)) {
23
- dc->base.pc_next += 2;
24
+ dc->base.pc_next = pc + 2;
25
return;
26
}
27
28
- dc->pc_curr = dc->base.pc_next;
29
- insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
30
+ dc->pc_curr = pc;
31
+ insn = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b);
32
is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn);
33
- dc->base.pc_next += 2;
34
+ pc += 2;
35
if (!is_16bit) {
36
- uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next,
37
- dc->sctlr_b);
38
-
39
+ uint32_t insn2 = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b);
40
insn = insn << 16 | insn2;
41
- dc->base.pc_next += 2;
42
+ pc += 2;
43
}
44
+ dc->base.pc_next = pc;
45
dc->insn = insn;
46
47
if (dc->pstate_il) {
48
--
49
2.25.1
50
51
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Create arm_check_ss_active and arm_check_kernelpage.
4
5
Reverse the order of the tests. While it doesn't matter in practice,
6
because only user-only has a kernel page and user-only never sets
7
ss_active, ss_active has priority over execution exceptions and it
8
is best to keep them in the proper order.
9
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/translate.c | 10 +++++++---
15
1 file changed, 7 insertions(+), 3 deletions(-)
16
17
diff --git a/target/arm/translate.c b/target/arm/translate.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate.c
20
+++ b/target/arm/translate.c
21
@@ -XXX,XX +XXX,XX @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
22
dc->insn_start = tcg_last_op();
23
}
24
25
-static bool arm_pre_translate_insn(DisasContext *dc)
26
+static bool arm_check_kernelpage(DisasContext *dc)
27
{
28
#ifdef CONFIG_USER_ONLY
29
/* Intercept jump to the magic kernel page. */
30
@@ -XXX,XX +XXX,XX @@ static bool arm_pre_translate_insn(DisasContext *dc)
31
return true;
32
}
33
#endif
34
+ return false;
35
+}
36
37
+static bool arm_check_ss_active(DisasContext *dc)
38
+{
39
if (dc->ss_active && !dc->pstate_ss) {
40
/* Singlestep state is Active-pending.
41
* If we're in this state at the start of a TB then either
42
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
43
uint32_t pc = dc->base.pc_next;
44
unsigned int insn;
45
46
- if (arm_pre_translate_insn(dc)) {
47
+ if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
48
dc->base.pc_next = pc + 4;
49
return;
50
}
51
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
52
uint32_t insn;
53
bool is_16bit;
54
55
- if (arm_pre_translate_insn(dc)) {
56
+ if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
57
dc->base.pc_next = pc + 2;
58
return;
59
}
60
--
61
2.25.1
62
63
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The size of the code covered by a TranslationBlock cannot be 0;
4
this is checked via assert in tb_gen_code.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-a64.c | 1 +
11
1 file changed, 1 insertion(+)
12
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
16
+++ b/target/arm/translate-a64.c
17
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
18
assert(s->base.num_insns == 1);
19
gen_swstep_exception(s, 0, 0);
20
s->base.is_jmp = DISAS_NORETURN;
21
+ s->base.pc_next = pc + 4;
22
return;
23
}
24
25
--
26
2.25.1
27
28
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
We will reuse this section of arm_deliver_fault for
4
raising pc alignment faults.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/tlb_helper.c | 45 +++++++++++++++++++++++++----------------
11
1 file changed, 28 insertions(+), 17 deletions(-)
12
13
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/tlb_helper.c
16
+++ b/target/arm/tlb_helper.c
17
@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
18
return syn;
19
}
20
21
-static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
22
- MMUAccessType access_type,
23
- int mmu_idx, ARMMMUFaultInfo *fi)
24
+static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi,
25
+ int target_el, int mmu_idx, uint32_t *ret_fsc)
26
{
27
- CPUARMState *env = &cpu->env;
28
- int target_el;
29
- bool same_el;
30
- uint32_t syn, exc, fsr, fsc;
31
ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
32
-
33
- target_el = exception_target_el(env);
34
- if (fi->stage2) {
35
- target_el = 2;
36
- env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
37
- if (arm_is_secure_below_el3(env) && fi->s1ns) {
38
- env->cp15.hpfar_el2 |= HPFAR_NS;
39
- }
40
- }
41
- same_el = (arm_current_el(env) == target_el);
42
+ uint32_t fsr, fsc;
43
44
if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
45
arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
46
@@ -XXX,XX +XXX,XX @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
47
fsc = 0x3f;
48
}
49
50
+ *ret_fsc = fsc;
51
+ return fsr;
52
+}
53
+
54
+static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
55
+ MMUAccessType access_type,
56
+ int mmu_idx, ARMMMUFaultInfo *fi)
57
+{
58
+ CPUARMState *env = &cpu->env;
59
+ int target_el;
60
+ bool same_el;
61
+ uint32_t syn, exc, fsr, fsc;
62
+
63
+ target_el = exception_target_el(env);
64
+ if (fi->stage2) {
65
+ target_el = 2;
66
+ env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
67
+ if (arm_is_secure_below_el3(env) && fi->s1ns) {
68
+ env->cp15.hpfar_el2 |= HPFAR_NS;
69
+ }
70
+ }
71
+ same_el = (arm_current_el(env) == target_el);
72
+
73
+ fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc);
74
+
75
if (access_type == MMU_INST_FETCH) {
76
syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc);
77
exc = EXCP_PREFETCH_ABORT;
78
--
79
2.25.1
80
81
diff view generated by jsdifflib
New patch
1
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
For A64, any input to an indirect branch can cause this.
4
5
For A32, many indirect branch paths force the branch to be aligned,
6
but BXWritePC does not. This includes the BX instruction but also
7
other interworking changes to PC. Prior to v8, this case is UNDEFINED.
8
With v8, this is CONSTRAINED UNPREDICTABLE and may either raise an
9
exception or force align the PC.
10
11
We choose to raise an exception because we have the infrastructure,
12
it makes the generated code for gen_bx simpler, and it has the
13
possibility of catching more guest bugs.
14
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
target/arm/helper.h | 1 +
20
target/arm/syndrome.h | 5 ++++
21
linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++++++---------------
22
target/arm/tlb_helper.c | 18 ++++++++++++++
23
target/arm/translate-a64.c | 15 ++++++++++++
24
target/arm/translate.c | 22 ++++++++++++++++-
25
6 files changed, 87 insertions(+), 20 deletions(-)
26
27
diff --git a/target/arm/helper.h b/target/arm/helper.h
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/helper.h
30
+++ b/target/arm/helper.h
31
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
32
DEF_HELPER_2(exception_internal, void, env, i32)
33
DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32)
34
DEF_HELPER_2(exception_bkpt_insn, void, env, i32)
35
+DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl)
36
DEF_HELPER_1(setend, void, env)
37
DEF_HELPER_2(wfi, void, env, i32)
38
DEF_HELPER_1(wfe, void, env)
39
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/syndrome.h
42
+++ b/target/arm/syndrome.h
43
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_illegalstate(void)
44
return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL;
45
}
46
47
+static inline uint32_t syn_pcalignment(void)
48
+{
49
+ return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
50
+}
51
+
52
#endif /* TARGET_ARM_SYNDROME_H */
53
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/linux-user/aarch64/cpu_loop.c
56
+++ b/linux-user/aarch64/cpu_loop.c
57
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
58
break;
59
case EXCP_PREFETCH_ABORT:
60
case EXCP_DATA_ABORT:
61
- /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */
62
ec = syn_get_ec(env->exception.syndrome);
63
- assert(ec == EC_DATAABORT || ec == EC_INSNABORT);
64
-
65
- /* Both EC have the same format for FSC, or close enough. */
66
- fsc = extract32(env->exception.syndrome, 0, 6);
67
- switch (fsc) {
68
- case 0x04 ... 0x07: /* Translation fault, level {0-3} */
69
- si_signo = TARGET_SIGSEGV;
70
- si_code = TARGET_SEGV_MAPERR;
71
+ switch (ec) {
72
+ case EC_DATAABORT:
73
+ case EC_INSNABORT:
74
+ /* Both EC have the same format for FSC, or close enough. */
75
+ fsc = extract32(env->exception.syndrome, 0, 6);
76
+ switch (fsc) {
77
+ case 0x04 ... 0x07: /* Translation fault, level {0-3} */
78
+ si_signo = TARGET_SIGSEGV;
79
+ si_code = TARGET_SEGV_MAPERR;
80
+ break;
81
+ case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
82
+ case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
83
+ si_signo = TARGET_SIGSEGV;
84
+ si_code = TARGET_SEGV_ACCERR;
85
+ break;
86
+ case 0x11: /* Synchronous Tag Check Fault */
87
+ si_signo = TARGET_SIGSEGV;
88
+ si_code = TARGET_SEGV_MTESERR;
89
+ break;
90
+ case 0x21: /* Alignment fault */
91
+ si_signo = TARGET_SIGBUS;
92
+ si_code = TARGET_BUS_ADRALN;
93
+ break;
94
+ default:
95
+ g_assert_not_reached();
96
+ }
97
break;
98
- case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
99
- case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
100
- si_signo = TARGET_SIGSEGV;
101
- si_code = TARGET_SEGV_ACCERR;
102
- break;
103
- case 0x11: /* Synchronous Tag Check Fault */
104
- si_signo = TARGET_SIGSEGV;
105
- si_code = TARGET_SEGV_MTESERR;
106
- break;
107
- case 0x21: /* Alignment fault */
108
+ case EC_PCALIGNMENT:
109
si_signo = TARGET_SIGBUS;
110
si_code = TARGET_BUS_ADRALN;
111
break;
112
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
113
index XXXXXXX..XXXXXXX 100644
114
--- a/target/arm/tlb_helper.c
115
+++ b/target/arm/tlb_helper.c
116
@@ -XXX,XX +XXX,XX @@
117
#include "cpu.h"
118
#include "internals.h"
119
#include "exec/exec-all.h"
120
+#include "exec/helper-proto.h"
121
122
static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
123
unsigned int target_el,
124
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
125
arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
126
}
127
128
+void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc)
129
+{
130
+ ARMMMUFaultInfo fi = { .type = ARMFault_Alignment };
131
+ int target_el = exception_target_el(env);
132
+ int mmu_idx = cpu_mmu_index(env, true);
133
+ uint32_t fsc;
134
+
135
+ env->exception.vaddress = pc;
136
+
137
+ /*
138
+ * Note that the fsc is not applicable to this exception,
139
+ * since any syndrome is pcalignment not insn_abort.
140
+ */
141
+ env->exception.fsr = compute_fsr_fsc(env, &fi, target_el, mmu_idx, &fsc);
142
+ raise_exception(env, EXCP_PREFETCH_ABORT, syn_pcalignment(), target_el);
143
+}
144
+
145
#if !defined(CONFIG_USER_ONLY)
146
147
/*
148
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
149
index XXXXXXX..XXXXXXX 100644
150
--- a/target/arm/translate-a64.c
151
+++ b/target/arm/translate-a64.c
152
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
153
uint64_t pc = s->base.pc_next;
154
uint32_t insn;
155
156
+ /* Singlestep exceptions have the highest priority. */
157
if (s->ss_active && !s->pstate_ss) {
158
/* Singlestep state is Active-pending.
159
* If we're in this state at the start of a TB then either
160
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
161
return;
162
}
163
164
+ if (pc & 3) {
165
+ /*
166
+ * PC alignment fault. This has priority over the instruction abort
167
+ * that we would receive from a translation fault via arm_ldl_code.
168
+ * This should only be possible after an indirect branch, at the
169
+ * start of the TB.
170
+ */
171
+ assert(s->base.num_insns == 1);
172
+ gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc));
173
+ s->base.is_jmp = DISAS_NORETURN;
174
+ s->base.pc_next = QEMU_ALIGN_UP(pc, 4);
175
+ return;
176
+ }
177
+
178
s->pc_curr = pc;
179
insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b);
180
s->insn = insn;
181
diff --git a/target/arm/translate.c b/target/arm/translate.c
182
index XXXXXXX..XXXXXXX 100644
183
--- a/target/arm/translate.c
184
+++ b/target/arm/translate.c
185
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
186
uint32_t pc = dc->base.pc_next;
187
unsigned int insn;
188
189
- if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
190
+ /* Singlestep exceptions have the highest priority. */
191
+ if (arm_check_ss_active(dc)) {
192
+ dc->base.pc_next = pc + 4;
193
+ return;
194
+ }
195
+
196
+ if (pc & 3) {
197
+ /*
198
+ * PC alignment fault. This has priority over the instruction abort
199
+ * that we would receive from a translation fault via arm_ldl_code
200
+ * (or the execution of the kernelpage entrypoint). This should only
201
+ * be possible after an indirect branch, at the start of the TB.
202
+ */
203
+ assert(dc->base.num_insns == 1);
204
+ gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc));
205
+ dc->base.is_jmp = DISAS_NORETURN;
206
+ dc->base.pc_next = QEMU_ALIGN_UP(pc, 4);
207
+ return;
208
+ }
209
+
210
+ if (arm_check_kernelpage(dc)) {
211
dc->base.pc_next = pc + 4;
212
return;
213
}
214
--
215
2.25.1
216
217
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Misaligned thumb PC is architecturally impossible.
4
Assert is better than proceeding, in case we've missed
5
something somewhere.
6
7
Expand a comment about aligning the pc in gdbstub.
8
Fail an incoming migrate if a thumb pc is misaligned.
9
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/gdbstub.c | 9 +++++++--
15
target/arm/machine.c | 10 ++++++++++
16
target/arm/translate.c | 3 +++
17
3 files changed, 20 insertions(+), 2 deletions(-)
18
19
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/gdbstub.c
22
+++ b/target/arm/gdbstub.c
23
@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
24
25
tmp = ldl_p(mem_buf);
26
27
- /* Mask out low bit of PC to workaround gdb bugs. This will probably
28
- cause problems if we ever implement the Jazelle DBX extensions. */
29
+ /*
30
+ * Mask out low bits of PC to workaround gdb bugs.
31
+ * This avoids an assert in thumb_tr_translate_insn, because it is
32
+ * architecturally impossible to misalign the pc.
33
+ * This will probably cause problems if we ever implement the
34
+ * Jazelle DBX extensions.
35
+ */
36
if (n == 15) {
37
tmp &= ~1;
38
}
39
diff --git a/target/arm/machine.c b/target/arm/machine.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/machine.c
42
+++ b/target/arm/machine.c
43
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
44
return -1;
45
}
46
}
47
+
48
+ /*
49
+ * Misaligned thumb pc is architecturally impossible.
50
+ * We have an assert in thumb_tr_translate_insn to verify this.
51
+ * Fail an incoming migrate to avoid this assert.
52
+ */
53
+ if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
54
+ return -1;
55
+ }
56
+
57
if (!kvm_enabled()) {
58
pmu_op_finish(&cpu->env);
59
}
60
diff --git a/target/arm/translate.c b/target/arm/translate.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/target/arm/translate.c
63
+++ b/target/arm/translate.c
64
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
65
uint32_t insn;
66
bool is_16bit;
67
68
+ /* Misaligned thumb PC is architecturally impossible. */
69
+ assert((dc->base.pc_next & 1) == 0);
70
+
71
if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
72
dc->base.pc_next = pc + 2;
73
return;
74
--
75
2.25.1
76
77
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Both single-step and pc alignment faults have priority over
4
breakpoint exceptions.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/debug_helper.c | 23 +++++++++++++++++++++++
11
1 file changed, 23 insertions(+)
12
13
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/debug_helper.c
16
+++ b/target/arm/debug_helper.c
17
@@ -XXX,XX +XXX,XX @@ bool arm_debug_check_breakpoint(CPUState *cs)
18
{
19
ARMCPU *cpu = ARM_CPU(cs);
20
CPUARMState *env = &cpu->env;
21
+ target_ulong pc;
22
int n;
23
24
/*
25
@@ -XXX,XX +XXX,XX @@ bool arm_debug_check_breakpoint(CPUState *cs)
26
return false;
27
}
28
29
+ /*
30
+ * Single-step exceptions have priority over breakpoint exceptions.
31
+ * If single-step state is active-pending, suppress the bp.
32
+ */
33
+ if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) {
34
+ return false;
35
+ }
36
+
37
+ /*
38
+ * PC alignment faults have priority over breakpoint exceptions.
39
+ */
40
+ pc = is_a64(env) ? env->pc : env->regs[15];
41
+ if ((is_a64(env) || !env->thumb) && (pc & 3) != 0) {
42
+ return false;
43
+ }
44
+
45
+ /*
46
+ * Instruction aborts have priority over breakpoint exceptions.
47
+ * TODO: We would need to look up the page for PC and verify that
48
+ * it is present and executable.
49
+ */
50
+
51
for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
52
if (bp_wp_matches(cpu, n, false)) {
53
return true;
54
--
55
2.25.1
56
57
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
---
7
tests/tcg/aarch64/pcalign-a64.c | 37 +++++++++++++++++++++++++
8
tests/tcg/arm/pcalign-a32.c | 46 +++++++++++++++++++++++++++++++
9
tests/tcg/aarch64/Makefile.target | 4 +--
10
tests/tcg/arm/Makefile.target | 4 +++
11
4 files changed, 89 insertions(+), 2 deletions(-)
12
create mode 100644 tests/tcg/aarch64/pcalign-a64.c
13
create mode 100644 tests/tcg/arm/pcalign-a32.c
14
15
diff --git a/tests/tcg/aarch64/pcalign-a64.c b/tests/tcg/aarch64/pcalign-a64.c
16
new file mode 100644
17
index XXXXXXX..XXXXXXX
18
--- /dev/null
19
+++ b/tests/tcg/aarch64/pcalign-a64.c
20
@@ -XXX,XX +XXX,XX @@
21
+/* Test PC misalignment exception */
22
+
23
+#include <assert.h>
24
+#include <signal.h>
25
+#include <stdlib.h>
26
+#include <stdio.h>
27
+
28
+static void *expected;
29
+
30
+static void sigbus(int sig, siginfo_t *info, void *vuc)
31
+{
32
+ assert(info->si_code == BUS_ADRALN);
33
+ assert(info->si_addr == expected);
34
+ exit(EXIT_SUCCESS);
35
+}
36
+
37
+int main()
38
+{
39
+ void *tmp;
40
+
41
+ struct sigaction sa = {
42
+ .sa_sigaction = sigbus,
43
+ .sa_flags = SA_SIGINFO
44
+ };
45
+
46
+ if (sigaction(SIGBUS, &sa, NULL) < 0) {
47
+ perror("sigaction");
48
+ return EXIT_FAILURE;
49
+ }
50
+
51
+ asm volatile("adr %0, 1f + 1\n\t"
52
+ "str %0, %1\n\t"
53
+ "br %0\n"
54
+ "1:"
55
+ : "=&r"(tmp), "=m"(expected));
56
+ abort();
57
+}
58
diff --git a/tests/tcg/arm/pcalign-a32.c b/tests/tcg/arm/pcalign-a32.c
59
new file mode 100644
60
index XXXXXXX..XXXXXXX
61
--- /dev/null
62
+++ b/tests/tcg/arm/pcalign-a32.c
63
@@ -XXX,XX +XXX,XX @@
64
+/* Test PC misalignment exception */
65
+
66
+#ifdef __thumb__
67
+#error "This test must be compiled for ARM"
68
+#endif
69
+
70
+#include <assert.h>
71
+#include <signal.h>
72
+#include <stdlib.h>
73
+#include <stdio.h>
74
+
75
+static void *expected;
76
+
77
+static void sigbus(int sig, siginfo_t *info, void *vuc)
78
+{
79
+ assert(info->si_code == BUS_ADRALN);
80
+ assert(info->si_addr == expected);
81
+ exit(EXIT_SUCCESS);
82
+}
83
+
84
+int main()
85
+{
86
+ void *tmp;
87
+
88
+ struct sigaction sa = {
89
+ .sa_sigaction = sigbus,
90
+ .sa_flags = SA_SIGINFO
91
+ };
92
+
93
+ if (sigaction(SIGBUS, &sa, NULL) < 0) {
94
+ perror("sigaction");
95
+ return EXIT_FAILURE;
96
+ }
97
+
98
+ asm volatile("adr %0, 1f + 2\n\t"
99
+ "str %0, %1\n\t"
100
+ "bx %0\n"
101
+ "1:"
102
+ : "=&r"(tmp), "=m"(expected));
103
+
104
+ /*
105
+ * From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns
106
+ * the address or not. If so, we can legitimately fall through.
107
+ */
108
+ return EXIT_SUCCESS;
109
+}
110
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
111
index XXXXXXX..XXXXXXX 100644
112
--- a/tests/tcg/aarch64/Makefile.target
113
+++ b/tests/tcg/aarch64/Makefile.target
114
@@ -XXX,XX +XXX,XX @@ VPATH         += $(ARM_SRC)
115
AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64
116
VPATH         += $(AARCH64_SRC)
117
118
-# Float-convert Tests
119
-AARCH64_TESTS=fcvt
120
+# Base architecture tests
121
+AARCH64_TESTS=fcvt pcalign-a64
122
123
fcvt: LDFLAGS+=-lm
124
125
diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target
126
index XXXXXXX..XXXXXXX 100644
127
--- a/tests/tcg/arm/Makefile.target
128
+++ b/tests/tcg/arm/Makefile.target
129
@@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt
130
    $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)")
131
    $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref)
132
133
+# PC alignment test
134
+ARM_TESTS += pcalign-a32
135
+pcalign-a32: CFLAGS+=-marm
136
+
137
ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y)
138
139
# Semihosting smoke test for linux-user
140
--
141
2.25.1
142
143
diff view generated by jsdifflib
New patch
1
In the SSE decode function gen_sse(), we combine a byte
2
'b' and a value 'b1' which can be [0..3], and switch on them:
3
b |= (b1 << 8);
4
switch (b) {
5
...
6
default:
7
unknown_op:
8
gen_unknown_opcode(env, s);
9
return;
10
}
1
11
12
In three cases inside this switch, we were then also checking for
13
"if (b1 >= 2) { goto unknown_op; }".
14
However, this can never happen, because the 'case' values in each place
15
are 0x0nn or 0x1nn and the switch will have directed the b1 == (2, 3)
16
cases to the default already.
17
18
This check was added in commit c045af25a52e9 in 2010; the added code
19
was unnecessary then as well, and was apparently intended only to
20
ensure that we never accidentally ended up indexing off the end
21
of an sse_op_table with only 2 entries as a result of future bugs
22
in the decode logic.
23
24
Change the checks to assert() instead, and make sure they're always
25
immediately before the array access they are protecting.
26
27
Fixes: Coverity CID 1460207
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
30
---
31
target/i386/tcg/translate.c | 12 +++---------
32
1 file changed, 3 insertions(+), 9 deletions(-)
33
34
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/i386/tcg/translate.c
37
+++ b/target/i386/tcg/translate.c
38
@@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
39
case 0x171: /* shift xmm, im */
40
case 0x172:
41
case 0x173:
42
- if (b1 >= 2) {
43
- goto unknown_op;
44
- }
45
val = x86_ldub_code(env, s);
46
if (is_xmm) {
47
tcg_gen_movi_tl(s->T0, val);
48
@@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
49
offsetof(CPUX86State, mmx_t0.MMX_L(1)));
50
op1_offset = offsetof(CPUX86State,mmx_t0);
51
}
52
+ assert(b1 < 2);
53
sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 +
54
(((modrm >> 3)) & 7)][b1];
55
if (!sse_fn_epp) {
56
@@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
57
rm = modrm & 7;
58
reg = ((modrm >> 3) & 7) | REX_R(s);
59
mod = (modrm >> 6) & 3;
60
- if (b1 >= 2) {
61
- goto unknown_op;
62
- }
63
64
+ assert(b1 < 2);
65
sse_fn_epp = sse_op_table6[b].op[b1];
66
if (!sse_fn_epp) {
67
goto unknown_op;
68
@@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
69
rm = modrm & 7;
70
reg = ((modrm >> 3) & 7) | REX_R(s);
71
mod = (modrm >> 6) & 3;
72
- if (b1 >= 2) {
73
- goto unknown_op;
74
- }
75
76
+ assert(b1 < 2);
77
sse_fn_eppi = sse_op_table7[b].op[b1];
78
if (!sse_fn_eppi) {
79
goto unknown_op;
80
--
81
2.25.1
82
83
diff view generated by jsdifflib
New patch
1
The qemu-common.h header is not supposed to be included from any
2
other header files, only from .c files (as documented in a comment at
3
the start of it).
1
4
5
include/hw/i386/x86.h and include/hw/i386/microvm.h break this rule.
6
In fact, the include is not required at all, so we can just drop it
7
from both files.
8
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20211129200510.1233037-2-peter.maydell@linaro.org
13
---
14
include/hw/i386/microvm.h | 1 -
15
include/hw/i386/x86.h | 1 -
16
2 files changed, 2 deletions(-)
17
18
diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/i386/microvm.h
21
+++ b/include/hw/i386/microvm.h
22
@@ -XXX,XX +XXX,XX @@
23
#ifndef HW_I386_MICROVM_H
24
#define HW_I386_MICROVM_H
25
26
-#include "qemu-common.h"
27
#include "exec/hwaddr.h"
28
#include "qemu/notify.h"
29
30
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
31
index XXXXXXX..XXXXXXX 100644
32
--- a/include/hw/i386/x86.h
33
+++ b/include/hw/i386/x86.h
34
@@ -XXX,XX +XXX,XX @@
35
#ifndef HW_I386_X86_H
36
#define HW_I386_X86_H
37
38
-#include "qemu-common.h"
39
#include "exec/hwaddr.h"
40
#include "qemu/notify.h"
41
42
--
43
2.25.1
44
45
diff view generated by jsdifflib
New patch
1
The qemu-common.h header is not supposed to be included from any
2
other header files, only from .c files (as documented in a comment at
3
the start of it).
1
4
5
Move the include to linux-user/hexagon/cpu_loop.c, which needs it for
6
the declaration of cpu_exec_step_atomic().
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
12
Message-id: 20211129200510.1233037-3-peter.maydell@linaro.org
13
---
14
target/hexagon/cpu.h | 1 -
15
linux-user/hexagon/cpu_loop.c | 1 +
16
2 files changed, 1 insertion(+), 1 deletion(-)
17
18
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/hexagon/cpu.h
21
+++ b/target/hexagon/cpu.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct CPUHexagonState CPUHexagonState;
23
24
#include "fpu/softfloat-types.h"
25
26
-#include "qemu-common.h"
27
#include "exec/cpu-defs.h"
28
#include "hex_regs.h"
29
#include "mmvec/mmvec.h"
30
diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/linux-user/hexagon/cpu_loop.c
33
+++ b/linux-user/hexagon/cpu_loop.c
34
@@ -XXX,XX +XXX,XX @@
35
*/
36
37
#include "qemu/osdep.h"
38
+#include "qemu-common.h"
39
#include "qemu.h"
40
#include "user-internals.h"
41
#include "cpu_loop-common.h"
42
--
43
2.25.1
44
45
diff view generated by jsdifflib
New patch
1
The qemu-common.h header is not supposed to be included from any
2
other header files, only from .c files (as documented in a comment at
3
the start of it).
1
4
5
Nothing actually relies on target/rx/cpu.h including it, so we can
6
just drop the include.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
12
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
13
Message-id: 20211129200510.1233037-4-peter.maydell@linaro.org
14
---
15
target/rx/cpu.h | 1 -
16
1 file changed, 1 deletion(-)
17
18
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/rx/cpu.h
21
+++ b/target/rx/cpu.h
22
@@ -XXX,XX +XXX,XX @@
23
#define RX_CPU_H
24
25
#include "qemu/bitops.h"
26
-#include "qemu-common.h"
27
#include "hw/registerfields.h"
28
#include "cpu-qom.h"
29
30
--
31
2.25.1
32
33
diff view generated by jsdifflib
1
In the M-profile architecture, when we do a vector table fetch and it
1
A lot of C files in hw/arm include qemu-common.h when they don't
2
fails, we need to report a HardFault. Whether this is a Secure HF or
2
need anything from it. Drop the include lines.
3
a NonSecure HF depends on several things. If AIRCR.BFHFNMINS is 0
4
then HF is always Secure, because there is no NonSecure HardFault.
5
Otherwise, the answer depends on whether the 'underlying exception'
6
(MemManage, BusFault, SecureFault) targets Secure or NonSecure. (In
7
the pseudocode, this is handled in the Vector() function: the final
8
exc.isSecure is calculated by looking at the exc.isSecure from the
9
exception returned from the memory access, not the isSecure input
10
argument.)
11
3
12
We weren't doing this correctly, because we were looking at
4
omap1.c, pxa2xx.c and strongarm.c retain the include because they
13
the target security domain of the exception we were trying to
5
use it for the prototype of qemu_get_timedate().
14
load the vector table entry for. This produces errors of two kinds:
15
* a load from the NS vector table which hits the "NS access
16
to S memory" SecureFault should end up as a Secure HardFault,
17
but we were raising an NS HardFault
18
* a load from the S vector table which causes a BusFault
19
should raise an NS HardFault if BFHFNMINS == 1 (because
20
in that case all BusFaults are NonSecure), but we were raising
21
a Secure HardFault
22
23
Correct the logic.
24
25
We also fix a comment error where we claimed that we might
26
be escalating MemManage to HardFault, and forgot about SecureFault.
27
(Vector loads can never hit MPU access faults, because they're
28
always aligned and always use the default address map.)
29
6
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
Message-id: 20190705094823.28905-1-peter.maydell@linaro.org
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
11
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
12
Message-id: 20211129200510.1233037-5-peter.maydell@linaro.org
32
---
13
---
33
target/arm/m_helper.c | 21 +++++++++++++++++----
14
hw/arm/boot.c | 1 -
34
1 file changed, 17 insertions(+), 4 deletions(-)
15
hw/arm/digic_boards.c | 1 -
16
hw/arm/highbank.c | 1 -
17
hw/arm/npcm7xx_boards.c | 1 -
18
hw/arm/sbsa-ref.c | 1 -
19
hw/arm/stm32f405_soc.c | 1 -
20
hw/arm/vexpress.c | 1 -
21
hw/arm/virt.c | 1 -
22
8 files changed, 8 deletions(-)
35
23
36
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
24
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
37
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/m_helper.c
26
--- a/hw/arm/boot.c
39
+++ b/target/arm/m_helper.c
27
+++ b/hw/arm/boot.c
40
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
28
@@ -XXX,XX +XXX,XX @@
41
if (sattrs.ns) {
29
*/
42
attrs.secure = false;
30
43
} else if (!targets_secure) {
31
#include "qemu/osdep.h"
44
- /* NS access to S memory */
32
-#include "qemu-common.h"
45
+ /*
33
#include "qemu/datadir.h"
46
+ * NS access to S memory: the underlying exception which we escalate
34
#include "qemu/error-report.h"
47
+ * to HardFault is SecureFault, which always targets Secure.
35
#include "qapi/error.h"
48
+ */
36
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
49
+ exc_secure = true;
37
index XXXXXXX..XXXXXXX 100644
50
goto load_fail;
38
--- a/hw/arm/digic_boards.c
51
}
39
+++ b/hw/arm/digic_boards.c
52
}
40
@@ -XXX,XX +XXX,XX @@
53
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
41
54
vector_entry = address_space_ldl(arm_addressspace(cs, attrs), addr,
42
#include "qemu/osdep.h"
55
attrs, &result);
43
#include "qapi/error.h"
56
if (result != MEMTX_OK) {
44
-#include "qemu-common.h"
57
+ /*
45
#include "qemu/datadir.h"
58
+ * Underlying exception is BusFault: its target security state
46
#include "hw/boards.h"
59
+ * depends on BFHFNMINS.
47
#include "qemu/error-report.h"
60
+ */
48
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
61
+ exc_secure = !(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
49
index XXXXXXX..XXXXXXX 100644
62
goto load_fail;
50
--- a/hw/arm/highbank.c
63
}
51
+++ b/hw/arm/highbank.c
64
*pvec = vector_entry;
52
@@ -XXX,XX +XXX,XX @@
65
@@ -XXX,XX +XXX,XX @@ load_fail:
53
*/
66
/*
54
67
* All vector table fetch fails are reported as HardFault, with
55
#include "qemu/osdep.h"
68
* HFSR.VECTTBL and .FORCED set. (FORCED is set because
56
-#include "qemu-common.h"
69
- * technically the underlying exception is a MemManage or BusFault
57
#include "qemu/datadir.h"
70
+ * technically the underlying exception is a SecureFault or BusFault
58
#include "qapi/error.h"
71
* that is escalated to HardFault.) This is a terminal exception,
59
#include "hw/sysbus.h"
72
* so we will either take the HardFault immediately or else enter
60
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
73
* lockup (the latter case is handled in armv7m_nvic_set_pending_derived()).
61
index XXXXXXX..XXXXXXX 100644
74
+ * The HardFault is Secure if BFHFNMINS is 0 (meaning that all HFs are
62
--- a/hw/arm/npcm7xx_boards.c
75
+ * secure); otherwise it targets the same security state as the
63
+++ b/hw/arm/npcm7xx_boards.c
76
+ * underlying exception.
64
@@ -XXX,XX +XXX,XX @@
77
*/
65
#include "hw/qdev-core.h"
78
- exc_secure = targets_secure ||
66
#include "hw/qdev-properties.h"
79
- !(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
67
#include "qapi/error.h"
80
+ if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
68
-#include "qemu-common.h"
81
+ exc_secure = true;
69
#include "qemu/datadir.h"
82
+ }
70
#include "qemu/units.h"
83
env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK | R_V7M_HFSR_FORCED_MASK;
71
#include "sysemu/blockdev.h"
84
armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secure);
72
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
85
return false;
73
index XXXXXXX..XXXXXXX 100644
74
--- a/hw/arm/sbsa-ref.c
75
+++ b/hw/arm/sbsa-ref.c
76
@@ -XXX,XX +XXX,XX @@
77
*/
78
79
#include "qemu/osdep.h"
80
-#include "qemu-common.h"
81
#include "qemu/datadir.h"
82
#include "qapi/error.h"
83
#include "qemu/error-report.h"
84
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/hw/arm/stm32f405_soc.c
87
+++ b/hw/arm/stm32f405_soc.c
88
@@ -XXX,XX +XXX,XX @@
89
90
#include "qemu/osdep.h"
91
#include "qapi/error.h"
92
-#include "qemu-common.h"
93
#include "exec/address-spaces.h"
94
#include "sysemu/sysemu.h"
95
#include "hw/arm/stm32f405_soc.h"
96
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
97
index XXXXXXX..XXXXXXX 100644
98
--- a/hw/arm/vexpress.c
99
+++ b/hw/arm/vexpress.c
100
@@ -XXX,XX +XXX,XX @@
101
102
#include "qemu/osdep.h"
103
#include "qapi/error.h"
104
-#include "qemu-common.h"
105
#include "qemu/datadir.h"
106
#include "cpu.h"
107
#include "hw/sysbus.h"
108
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
109
index XXXXXXX..XXXXXXX 100644
110
--- a/hw/arm/virt.c
111
+++ b/hw/arm/virt.c
112
@@ -XXX,XX +XXX,XX @@
113
*/
114
115
#include "qemu/osdep.h"
116
-#include "qemu-common.h"
117
#include "qemu/datadir.h"
118
#include "qemu/units.h"
119
#include "qemu/option.h"
86
--
120
--
87
2.20.1
121
2.25.1
88
122
89
123
diff view generated by jsdifflib
1
The ARMv5 architecture didn't specify detailed per-feature ID
1
The calculation of the length of TLB range invalidate operations
2
registers. Now that we're using the MVFR0 register fields to
2
in tlbi_aa64_range_get_length() is incorrect in two ways:
3
gate the existence of VFP instructions, we need to set up
3
* the NUM field is 5 bits, but we read only 4 bits
4
the correct values in the cpu->isar structure so that we still
4
* we miscalculate the page_shift value, because of an
5
provide an FPU to the guest.
5
off-by-one error:
6
TG 0b00 is invalid
7
TG 0b01 is 4K granule size == 4096 == 2^12
8
TG 0b10 is 16K granule size == 16384 == 2^14
9
TG 0b11 is 64K granule size == 65536 == 2^16
10
so page_shift should be (TG - 1) * 2 + 12
6
11
7
This fixes a regression in the arm926 and arm1026 CPUs, which
12
Thanks to the bug report submitter Cha HyunSoo for identifying
8
are the only ones that both have VFP and are ARMv5 or earlier.
13
both these errors.
9
This regression was introduced by the VFP refactoring, and more
10
specifically by commits 1120827fa182f0e76 and 266bd25c485597c,
11
which accidentally disabled VFP short-vector support and
12
double-precision support on these CPUs.
13
14
14
Fixes: 1120827fa182f0e
15
Fixes: 84940ed82552d3c ("target/arm: Add support for FEAT_TLBIRANGE")
15
Fixes: 266bd25c485597c
16
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/734
16
Fixes: https://bugs.launchpad.net/qemu/+bug/1836192
17
Reported-by: Christophe Lyon <christophe.lyon@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
19
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
21
Tested-by: Christophe Lyon <christophe.lyon@linaro.org>
20
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
22
Message-id: 20190711131241.22231-1-peter.maydell@linaro.org
21
Message-id: 20211130173257.1274194-1-peter.maydell@linaro.org
23
---
22
---
24
target/arm/cpu.c | 12 ++++++++++++
23
target/arm/helper.c | 6 +++---
25
1 file changed, 12 insertions(+)
24
1 file changed, 3 insertions(+), 3 deletions(-)
26
25
27
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
26
diff --git a/target/arm/helper.c b/target/arm/helper.c
28
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/cpu.c
28
--- a/target/arm/helper.c
30
+++ b/target/arm/cpu.c
29
+++ b/target/arm/helper.c
31
@@ -XXX,XX +XXX,XX @@ static void arm926_initfn(Object *obj)
30
@@ -XXX,XX +XXX,XX @@ static uint64_t tlbi_aa64_range_get_length(CPUARMState *env,
32
* set the field to indicate Jazelle support within QEMU.
31
uint64_t exponent;
33
*/
32
uint64_t length;
34
cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
33
35
+ /*
34
- num = extract64(value, 39, 4);
36
+ * Similarly, we need to set MVFR0 fields to enable double precision
35
+ num = extract64(value, 39, 5);
37
+ * and short vector support even though ARMv5 doesn't have this register.
36
scale = extract64(value, 44, 2);
38
+ */
37
page_size_granule = extract64(value, 46, 2);
39
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
38
40
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
39
- page_shift = page_size_granule * 2 + 12;
41
}
40
-
42
41
if (page_size_granule == 0) {
43
static void arm946_initfn(Object *obj)
42
qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n",
44
@@ -XXX,XX +XXX,XX @@ static void arm1026_initfn(Object *obj)
43
page_size_granule);
45
* set the field to indicate Jazelle support within QEMU.
44
return 0;
46
*/
45
}
47
cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
46
48
+ /*
47
+ page_shift = (page_size_granule - 1) * 2 + 12;
49
+ * Similarly, we need to set MVFR0 fields to enable double precision
48
+
50
+ * and short vector support even though ARMv5 doesn't have this register.
49
exponent = (5 * scale) + 1;
51
+ */
50
length = (num + 1) << (exponent + page_shift);
52
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
51
53
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
54
55
{
56
/* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
57
--
52
--
58
2.20.1
53
2.25.1
59
54
60
55
diff view generated by jsdifflib
1
The PL031 RTC tracks the difference between the guest RTC
1
From: Patrick Venture <venture@google.com>
2
and the host RTC using a tick_offset field. For migration,
3
however, we currently always migrate the offset between
4
the guest and the vm_clock, even if the RTC clock is not
5
the same as the vm_clock; this was an attempt to retain
6
migration backwards compatibility.
7
2
8
Unfortunately this results in the RTC behaving oddly across
3
The rx_active boolean change to true should always trigger a try_read
9
a VM state save and restore -- since the VM clock stands still
4
call that flushes the queue.
10
across save-then-restore, regardless of how much real world
11
time has elapsed, the guest RTC ends up out of sync with the
12
host RTC in the restored VM.
13
5
14
Fix this by migrating the raw tick_offset. To retain migration
6
Signed-off-by: Patrick Venture <venture@google.com>
15
compatibility as far as possible, we have a new property
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
migrate-tick-offset; by default this is 'true' and we will
8
Message-id: 20211203221002.1719306-1-venture@google.com
17
migrate the true tick offset in a new subsection; if the
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
incoming data has no subsection we fall back to the old
10
---
19
vm_clock-based offset information, so old->new migration
11
hw/net/npcm7xx_emc.c | 18 ++++++++----------
20
compatibility is preserved. For complete new->old migration
12
1 file changed, 8 insertions(+), 10 deletions(-)
21
compatibility, the property is set to 'false' for 4.0 and
22
earlier machine types (this will only affect 'virt-4.0'
23
and below, as none of the other pl031-using machines are
24
versioned).
25
13
26
Reported-by: Russell King <rmk@armlinux.org.uk>
14
diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
29
Message-id: 20190709143912.28905-1-peter.maydell@linaro.org
30
---
31
include/hw/timer/pl031.h | 2 +
32
hw/core/machine.c | 1 +
33
hw/timer/pl031.c | 92 ++++++++++++++++++++++++++++++++++++++--
34
3 files changed, 91 insertions(+), 4 deletions(-)
35
36
diff --git a/include/hw/timer/pl031.h b/include/hw/timer/pl031.h
37
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/timer/pl031.h
16
--- a/hw/net/npcm7xx_emc.c
39
+++ b/include/hw/timer/pl031.h
17
+++ b/hw/net/npcm7xx_emc.c
40
@@ -XXX,XX +XXX,XX @@ typedef struct PL031State {
18
@@ -XXX,XX +XXX,XX @@ static void emc_halt_rx(NPCM7xxEMCState *emc, uint32_t mista_flag)
41
*/
19
emc_set_mista(emc, mista_flag);
42
uint32_t tick_offset_vmstate;
43
uint32_t tick_offset;
44
+ bool tick_offset_migrated;
45
+ bool migrate_tick_offset;
46
47
uint32_t mr;
48
uint32_t lr;
49
diff --git a/hw/core/machine.c b/hw/core/machine.c
50
index XXXXXXX..XXXXXXX 100644
51
--- a/hw/core/machine.c
52
+++ b/hw/core/machine.c
53
@@ -XXX,XX +XXX,XX @@ GlobalProperty hw_compat_4_0[] = {
54
{ "virtio-gpu-pci", "edid", "false" },
55
{ "virtio-device", "use-started", "false" },
56
{ "virtio-balloon-device", "qemu-4-0-config-size", "true" },
57
+ { "pl031", "migrate-tick-offset", "false" },
58
};
59
const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0);
60
61
diff --git a/hw/timer/pl031.c b/hw/timer/pl031.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/hw/timer/pl031.c
64
+++ b/hw/timer/pl031.c
65
@@ -XXX,XX +XXX,XX @@ static int pl031_pre_save(void *opaque)
66
{
67
PL031State *s = opaque;
68
69
- /* tick_offset is base_time - rtc_clock base time. Instead, we want to
70
- * store the base time relative to the QEMU_CLOCK_VIRTUAL for backwards-compatibility. */
71
+ /*
72
+ * The PL031 device model code uses the tick_offset field, which is
73
+ * the offset between what the guest RTC should read and what the
74
+ * QEMU rtc_clock reads:
75
+ * guest_rtc = rtc_clock + tick_offset
76
+ * and so
77
+ * tick_offset = guest_rtc - rtc_clock
78
+ *
79
+ * We want to migrate this offset, which sounds straightforward.
80
+ * Unfortunately older versions of QEMU migrated a conversion of this
81
+ * offset into an offset from the vm_clock. (This was in turn an
82
+ * attempt to be compatible with even older QEMU versions, but it
83
+ * has incorrect behaviour if the rtc_clock is not the same as the
84
+ * vm_clock.) So we put the actual tick_offset into a migration
85
+ * subsection, and the backwards-compatible time-relative-to-vm_clock
86
+ * in the main migration state.
87
+ *
88
+ * Calculate base time relative to QEMU_CLOCK_VIRTUAL:
89
+ */
90
int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
91
s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND;
92
93
return 0;
94
}
20
}
95
21
96
+static int pl031_pre_load(void *opaque)
22
+static void emc_enable_rx_and_flush(NPCM7xxEMCState *emc)
97
+{
23
+{
98
+ PL031State *s = opaque;
24
+ emc->rx_active = true;
99
+
25
+ qemu_flush_queued_packets(qemu_get_queue(emc->nic));
100
+ s->tick_offset_migrated = false;
101
+ return 0;
102
+}
26
+}
103
+
27
+
104
static int pl031_post_load(void *opaque, int version_id)
28
static void emc_set_next_tx_descriptor(NPCM7xxEMCState *emc,
29
const NPCM7xxEMCTxDesc *tx_desc,
30
uint32_t desc_addr)
31
@@ -XXX,XX +XXX,XX @@ static ssize_t emc_receive(NetClientState *nc, const uint8_t *buf, size_t len1)
32
return len;
33
}
34
35
-static void emc_try_receive_next_packet(NPCM7xxEMCState *emc)
36
-{
37
- if (emc_can_receive(qemu_get_queue(emc->nic))) {
38
- qemu_flush_queued_packets(qemu_get_queue(emc->nic));
39
- }
40
-}
41
-
42
static uint64_t npcm7xx_emc_read(void *opaque, hwaddr offset, unsigned size)
105
{
43
{
106
PL031State *s = opaque;
44
NPCM7xxEMCState *emc = opaque;
107
45
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset,
108
- int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
46
emc->regs[REG_MGSTA] |= REG_MGSTA_RXHA;
109
- s->tick_offset = s->tick_offset_vmstate - delta / NANOSECONDS_PER_SECOND;
47
}
110
+ /*
48
if (value & REG_MCMDR_RXON) {
111
+ * If we got the tick_offset subsection, then we can just use
49
- emc->rx_active = true;
112
+ * the value in that. Otherwise the source is an older QEMU and
50
+ emc_enable_rx_and_flush(emc);
113
+ * has given us the offset from the vm_clock; convert it back to
51
} else {
114
+ * an offset from the rtc_clock. This will cause time to incorrectly
52
emc_halt_rx(emc, 0);
115
+ * go backwards compared to the host RTC, but this is unavoidable.
53
}
116
+ */
54
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset,
117
+
55
break;
118
+ if (!s->tick_offset_migrated) {
56
case REG_RSDR:
119
+ int64_t delta = qemu_clock_get_ns(rtc_clock) -
57
if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) {
120
+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
58
- emc->rx_active = true;
121
+ s->tick_offset = s->tick_offset_vmstate -
59
- emc_try_receive_next_packet(emc);
122
+ delta / NANOSECONDS_PER_SECOND;
60
+ emc_enable_rx_and_flush(emc);
123
+ }
61
}
124
pl031_set_alarm(s);
62
break;
125
return 0;
63
case REG_MIIDA:
126
}
127
128
+static int pl031_tick_offset_post_load(void *opaque, int version_id)
129
+{
130
+ PL031State *s = opaque;
131
+
132
+ s->tick_offset_migrated = true;
133
+ return 0;
134
+}
135
+
136
+static bool pl031_tick_offset_needed(void *opaque)
137
+{
138
+ PL031State *s = opaque;
139
+
140
+ return s->migrate_tick_offset;
141
+}
142
+
143
+static const VMStateDescription vmstate_pl031_tick_offset = {
144
+ .name = "pl031/tick-offset",
145
+ .version_id = 1,
146
+ .minimum_version_id = 1,
147
+ .needed = pl031_tick_offset_needed,
148
+ .post_load = pl031_tick_offset_post_load,
149
+ .fields = (VMStateField[]) {
150
+ VMSTATE_UINT32(tick_offset, PL031State),
151
+ VMSTATE_END_OF_LIST()
152
+ }
153
+};
154
+
155
static const VMStateDescription vmstate_pl031 = {
156
.name = "pl031",
157
.version_id = 1,
158
.minimum_version_id = 1,
159
.pre_save = pl031_pre_save,
160
+ .pre_load = pl031_pre_load,
161
.post_load = pl031_post_load,
162
.fields = (VMStateField[]) {
163
VMSTATE_UINT32(tick_offset_vmstate, PL031State),
164
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl031 = {
165
VMSTATE_UINT32(im, PL031State),
166
VMSTATE_UINT32(is, PL031State),
167
VMSTATE_END_OF_LIST()
168
+ },
169
+ .subsections = (const VMStateDescription*[]) {
170
+ &vmstate_pl031_tick_offset,
171
+ NULL
172
}
173
};
174
175
+static Property pl031_properties[] = {
176
+ /*
177
+ * True to correctly migrate the tick offset of the RTC. False to
178
+ * obtain backward migration compatibility with older QEMU versions,
179
+ * at the expense of the guest RTC going backwards compared with the
180
+ * host RTC when the VM is saved/restored if using -rtc host.
181
+ * (Even if set to 'true' older QEMU can migrate forward to newer QEMU;
182
+ * 'false' also permits newer QEMU to migrate to older QEMU.)
183
+ */
184
+ DEFINE_PROP_BOOL("migrate-tick-offset",
185
+ PL031State, migrate_tick_offset, true),
186
+ DEFINE_PROP_END_OF_LIST()
187
+};
188
+
189
static void pl031_class_init(ObjectClass *klass, void *data)
190
{
191
DeviceClass *dc = DEVICE_CLASS(klass);
192
193
dc->vmsd = &vmstate_pl031;
194
+ dc->props = pl031_properties;
195
}
196
197
static const TypeInfo pl031_info = {
198
--
64
--
199
2.20.1
65
2.25.1
200
66
201
67
diff view generated by jsdifflib
New patch
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
2
3
When a virtio-iommu is instantiated, describe it using the ACPI VIOT
4
table.
5
6
Acked-by: Igor Mammedov <imammedo@redhat.com>
7
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
9
Message-id: 20211210170415.583179-2-jean-philippe@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/virt-acpi-build.c | 7 +++++++
13
hw/arm/Kconfig | 1 +
14
2 files changed, 8 insertions(+)
15
16
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/virt-acpi-build.c
19
+++ b/hw/arm/virt-acpi-build.c
20
@@ -XXX,XX +XXX,XX @@
21
#include "kvm_arm.h"
22
#include "migration/vmstate.h"
23
#include "hw/acpi/ghes.h"
24
+#include "hw/acpi/viot.h"
25
26
#define ARM_SPI_BASE 32
27
28
@@ -XXX,XX +XXX,XX @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
29
}
30
#endif
31
32
+ if (vms->iommu == VIRT_IOMMU_VIRTIO) {
33
+ acpi_add_table(table_offsets, tables_blob);
34
+ build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf,
35
+ vms->oem_id, vms->oem_table_id);
36
+ }
37
+
38
/* XSDT is pointed to by RSDP */
39
xsdt = tables_blob->len;
40
build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id,
41
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
42
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/arm/Kconfig
44
+++ b/hw/arm/Kconfig
45
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
46
select DIMM
47
select ACPI_HW_REDUCED
48
select ACPI_APEI
49
+ select ACPI_VIOT
50
51
config CHEETAH
52
bool
53
--
54
2.25.1
55
56
diff view generated by jsdifflib
New patch
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
2
3
virtio-iommu is now supported with ACPI VIOT as well as device tree.
4
Remove the restriction that prevents from instantiating a virtio-iommu
5
device under ACPI.
6
7
Acked-by: Igor Mammedov <imammedo@redhat.com>
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
10
Message-id: 20211210170415.583179-3-jean-philippe@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/virt.c | 10 ++--------
14
hw/virtio/virtio-iommu-pci.c | 12 ++----------
15
2 files changed, 4 insertions(+), 18 deletions(-)
16
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/virt.c
20
+++ b/hw/arm/virt.c
21
@@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
22
MachineClass *mc = MACHINE_GET_CLASS(machine);
23
24
if (device_is_dynamic_sysbus(mc, dev) ||
25
- (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) {
26
+ object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
27
+ object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
28
return HOTPLUG_HANDLER(machine);
29
}
30
- if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
31
- VirtMachineState *vms = VIRT_MACHINE(machine);
32
-
33
- if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) {
34
- return HOTPLUG_HANDLER(machine);
35
- }
36
- }
37
return NULL;
38
}
39
40
diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/virtio/virtio-iommu-pci.c
43
+++ b/hw/virtio/virtio-iommu-pci.c
44
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
45
VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
46
47
if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) {
48
- MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
49
-
50
- error_setg(errp,
51
- "%s machine fails to create iommu-map device tree bindings",
52
- mc->name);
53
- error_append_hint(errp,
54
- "Check your machine implements a hotplug handler "
55
- "for the virtio-iommu-pci device\n");
56
- error_append_hint(errp, "Check the guest is booted without FW or with "
57
- "-no-acpi\n");
58
+ error_setg(errp, "Check your machine implements a hotplug handler "
59
+ "for the virtio-iommu-pci device");
60
return;
61
}
62
for (int i = 0; i < s->nb_reserved_regions; i++) {
63
--
64
2.25.1
65
66
diff view generated by jsdifflib
1
From: David Engraf <david.engraf@sysgo.com>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
Using the whole 128 MiB flash in non-secure mode is not working because
3
We do not support instantiating multiple IOMMUs. Before adding a
4
virt_flash_fdt() expects the same address for secure_sysmem and sysmem.
4
virtio-iommu, check that no other IOMMU is present. This will detect
5
This is not correctly handled by caller because it forwards NULL for
5
both "iommu=smmuv3" machine parameter and another virtio-iommu instance.
6
secure_sysmem in non-secure flash mode.
7
6
8
Fixed by using sysmem when secure_sysmem is NULL.
7
Fixes: 70e89132c9 ("hw/arm/virt: Add the virtio-iommu device tree mappings")
9
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Signed-off-by: David Engraf <david.engraf@sysgo.com>
9
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
11
Message-id: 20190712075002.14326-1-david.engraf@sysgo.com
10
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20211210170415.583179-4-jean-philippe@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
13
---
15
hw/arm/virt.c | 2 +-
14
hw/arm/virt.c | 5 +++++
16
1 file changed, 1 insertion(+), 1 deletion(-)
15
1 file changed, 5 insertions(+)
17
16
18
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
19
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/virt.c
19
--- a/hw/arm/virt.c
21
+++ b/hw/arm/virt.c
20
+++ b/hw/arm/virt.c
22
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
21
@@ -XXX,XX +XXX,XX @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
23
&machine->device_memory->mr);
22
hwaddr db_start = 0, db_end = 0;
24
}
23
char *resv_prop_str;
25
24
26
- virt_flash_fdt(vms, sysmem, secure_sysmem);
25
+ if (vms->iommu != VIRT_IOMMU_NONE) {
27
+ virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
26
+ error_setg(errp, "virt machine does not support multiple IOMMUs");
28
27
+ return;
29
create_gic(vms, pic);
28
+ }
30
29
+
30
switch (vms->msi_controller) {
31
case VIRT_MSI_CTRL_NONE:
32
return;
31
--
33
--
32
2.20.1
34
2.25.1
33
35
34
36
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
In the next commit we will implement the write_with_attrs()
3
To propagate errors to the caller of the pre_plug callback, use the
4
handler. To avoid using different APIs, convert the read()
4
object_poperty_set*() functions directly instead of the qdev_prop_set*()
5
handler first.
5
helpers.
6
6
7
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
7
Suggested-by: Igor Mammedov <imammedo@redhat.com>
8
Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
10
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
11
Message-id: 20211210170415.583179-5-jean-philippe@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
hw/ssi/xilinx_spips.c | 23 +++++++++++------------
14
hw/arm/virt.c | 5 +++--
13
1 file changed, 11 insertions(+), 12 deletions(-)
15
1 file changed, 3 insertions(+), 2 deletions(-)
14
16
15
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/ssi/xilinx_spips.c
19
--- a/hw/arm/virt.c
18
+++ b/hw/ssi/xilinx_spips.c
20
+++ b/hw/arm/virt.c
19
@@ -XXX,XX +XXX,XX @@ static void lqspi_load_cache(void *opaque, hwaddr addr)
21
@@ -XXX,XX +XXX,XX @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
22
db_start, db_end,
23
VIRTIO_IOMMU_RESV_MEM_T_MSI);
24
25
- qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
26
- qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
27
+ object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
28
+ object_property_set_str(OBJECT(dev), "reserved-regions[0]",
29
+ resv_prop_str, errp);
30
g_free(resv_prop_str);
20
}
31
}
21
}
32
}
22
23
-static uint64_t
24
-lqspi_read(void *opaque, hwaddr addr, unsigned int size)
25
+static MemTxResult lqspi_read(void *opaque, hwaddr addr, uint64_t *value,
26
+ unsigned size, MemTxAttrs attrs)
27
{
28
- XilinxQSPIPS *q = opaque;
29
- uint32_t ret;
30
+ XilinxQSPIPS *q = XILINX_QSPIPS(opaque);
31
32
if (addr >= q->lqspi_cached_addr &&
33
addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
34
uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr];
35
- ret = cpu_to_le32(*(uint32_t *)retp);
36
- DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr,
37
- (unsigned)ret);
38
- return ret;
39
- } else {
40
- lqspi_load_cache(opaque, addr);
41
- return lqspi_read(opaque, addr, size);
42
+ *value = cpu_to_le32(*(uint32_t *)retp);
43
+ DB_PRINT_L(1, "addr: %08" HWADDR_PRIx ", data: %08" PRIx64 "\n",
44
+ addr, *value);
45
+ return MEMTX_OK;
46
}
47
+
48
+ lqspi_load_cache(opaque, addr);
49
+ return lqspi_read(opaque, addr, value, size, attrs);
50
}
51
52
static const MemoryRegionOps lqspi_ops = {
53
- .read = lqspi_read,
54
+ .read_with_attrs = lqspi_read,
55
.endianness = DEVICE_NATIVE_ENDIAN,
56
.valid = {
57
.min_access_size = 1,
58
--
33
--
59
2.20.1
34
2.25.1
60
35
61
36
diff view generated by jsdifflib
New patch
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
2
3
Create empty data files and allow updates for the upcoming VIOT tests.
4
5
Acked-by: Igor Mammedov <imammedo@redhat.com>
6
Reviewed-by: Eric Auger <eric.auger@redhat.com>
7
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
8
Message-id: 20211210170415.583179-6-jean-philippe@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
12
tests/data/acpi/q35/DSDT.viot | 0
13
tests/data/acpi/q35/VIOT.viot | 0
14
tests/data/acpi/virt/VIOT | 0
15
4 files changed, 3 insertions(+)
16
create mode 100644 tests/data/acpi/q35/DSDT.viot
17
create mode 100644 tests/data/acpi/q35/VIOT.viot
18
create mode 100644 tests/data/acpi/virt/VIOT
19
20
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/tests/qtest/bios-tables-test-allowed-diff.h
23
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
24
@@ -1 +1,4 @@
25
/* List of comma-separated changed AML files to ignore */
26
+"tests/data/acpi/virt/VIOT",
27
+"tests/data/acpi/q35/DSDT.viot",
28
+"tests/data/acpi/q35/VIOT.viot",
29
diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot
30
new file mode 100644
31
index XXXXXXX..XXXXXXX
32
diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot
33
new file mode 100644
34
index XXXXXXX..XXXXXXX
35
diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT
36
new file mode 100644
37
index XXXXXXX..XXXXXXX
38
--
39
2.25.1
40
41
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
Lei Sun found while auditing the code that a CPU write would
3
Add two test cases for VIOT, one on the q35 machine and the other on
4
trigger a NULL pointer dereference.
4
virt. To test complex topologies the q35 test has two PCIe buses that
5
bypass the IOMMU (and are therefore not described by VIOT), and two
6
buses that are translated by virtio-iommu.
5
7
6
>From UG1085 datasheet [*] AXI writes in this region are ignored
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
7
and generates an AXI Slave Error (SLVERR).
9
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
8
10
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
9
Fix by implementing the write_with_attrs() handler.
11
Message-id: 20211210170415.583179-7-jean-philippe@linaro.org
10
Return MEMTX_ERROR when the region is accessed (this error maps
11
to an AXI slave error).
12
13
[*] https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
14
15
Reported-by: Lei Sun <slei.casper@gmail.com>
16
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
17
Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
18
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
13
---
21
hw/ssi/xilinx_spips.c | 16 ++++++++++++++++
14
tests/qtest/bios-tables-test.c | 38 ++++++++++++++++++++++++++++++++++
22
1 file changed, 16 insertions(+)
15
1 file changed, 38 insertions(+)
23
16
24
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
17
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
25
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/ssi/xilinx_spips.c
19
--- a/tests/qtest/bios-tables-test.c
27
+++ b/hw/ssi/xilinx_spips.c
20
+++ b/tests/qtest/bios-tables-test.c
28
@@ -XXX,XX +XXX,XX @@ static MemTxResult lqspi_read(void *opaque, hwaddr addr, uint64_t *value,
21
@@ -XXX,XX +XXX,XX @@ static void test_acpi_virt_tcg(void)
29
return lqspi_read(opaque, addr, value, size, attrs);
22
free_test_data(&data);
30
}
23
}
31
24
32
+static MemTxResult lqspi_write(void *opaque, hwaddr offset, uint64_t value,
25
+static void test_acpi_q35_viot(void)
33
+ unsigned size, MemTxAttrs attrs)
34
+{
26
+{
27
+ test_data data = {
28
+ .machine = MACHINE_Q35,
29
+ .variant = ".viot",
30
+ };
31
+
35
+ /*
32
+ /*
36
+ * From UG1085, Chapter 24 (Quad-SPI controllers):
33
+ * To keep things interesting, two buses bypass the IOMMU.
37
+ * - Writes are ignored
34
+ * VIOT should only describes the other two buses.
38
+ * - AXI writes generate an external AXI slave error (SLVERR)
39
+ */
35
+ */
40
+ qemu_log_mask(LOG_GUEST_ERROR, "%s Unexpected %u-bit access to 0x%" PRIx64
36
+ test_acpi_one("-machine default_bus_bypass_iommu=on "
41
+ " (value: 0x%" PRIx64 "\n",
37
+ "-device virtio-iommu-pci "
42
+ __func__, size << 3, offset, value);
38
+ "-device pxb-pcie,bus_nr=0x10,id=pcie.100,bus=pcie.0 "
43
+
39
+ "-device pxb-pcie,bus_nr=0x20,id=pcie.200,bus=pcie.0,bypass_iommu=on "
44
+ return MEMTX_ERROR;
40
+ "-device pxb-pcie,bus_nr=0x30,id=pcie.300,bus=pcie.0",
41
+ &data);
42
+ free_test_data(&data);
45
+}
43
+}
46
+
44
+
47
static const MemoryRegionOps lqspi_ops = {
45
+static void test_acpi_virt_viot(void)
48
.read_with_attrs = lqspi_read,
46
+{
49
+ .write_with_attrs = lqspi_write,
47
+ test_data data = {
50
.endianness = DEVICE_NATIVE_ENDIAN,
48
+ .machine = "virt",
51
.valid = {
49
+ .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
52
.min_access_size = 1,
50
+ .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
51
+ .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2",
52
+ .ram_start = 0x40000000ULL,
53
+ .scan_len = 128ULL * 1024 * 1024,
54
+ };
55
+
56
+ test_acpi_one("-cpu cortex-a57 "
57
+ "-device virtio-iommu-pci", &data);
58
+ free_test_data(&data);
59
+}
60
+
61
static void test_oem_fields(test_data *data)
62
{
63
int i;
64
@@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[])
65
qtest_add_func("acpi/q35/kvm/xapic", test_acpi_q35_kvm_xapic);
66
qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar);
67
}
68
+ qtest_add_func("acpi/q35/viot", test_acpi_q35_viot);
69
} else if (strcmp(arch, "aarch64") == 0) {
70
if (has_tcg) {
71
qtest_add_func("acpi/virt", test_acpi_virt_tcg);
72
@@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[])
73
qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp);
74
qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb);
75
qtest_add_func("acpi/virt/oem-fields", test_acpi_oem_fields_virt);
76
+ qtest_add_func("acpi/virt/viot", test_acpi_virt_viot);
77
}
78
}
79
ret = g_test_run();
53
--
80
--
54
2.20.1
81
2.25.1
55
82
56
83
diff view generated by jsdifflib
New patch
1
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
3
Add expected blobs of the VIOT and DSDT table for the VIOT test on the
4
q35 machine.
5
6
Since the test instantiates a virtio device and two PCIe expander
7
bridges, DSDT.viot has more blocks than the base DSDT.
8
9
The VIOT table generated for the q35 test is:
10
11
[000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table]
12
[004h 0004 4] Table Length : 00000070
13
[008h 0008 1] Revision : 00
14
[009h 0009 1] Checksum : 3D
15
[00Ah 0010 6] Oem ID : "BOCHS "
16
[010h 0016 8] Oem Table ID : "BXPC "
17
[018h 0024 4] Oem Revision : 00000001
18
[01Ch 0028 4] Asl Compiler ID : "BXPC"
19
[020h 0032 4] Asl Compiler Revision : 00000001
20
21
[024h 0036 2] Node count : 0003
22
[026h 0038 2] Node offset : 0030
23
[028h 0040 8] Reserved : 0000000000000000
24
25
[030h 0048 1] Type : 03 [VirtIO-PCI IOMMU]
26
[031h 0049 1] Reserved : 00
27
[032h 0050 2] Length : 0010
28
29
[034h 0052 2] PCI Segment : 0000
30
[036h 0054 2] PCI BDF number : 0010
31
[038h 0056 8] Reserved : 0000000000000000
32
33
[040h 0064 1] Type : 01 [PCI Range]
34
[041h 0065 1] Reserved : 00
35
[042h 0066 2] Length : 0018
36
37
[044h 0068 4] Endpoint start : 00003000
38
[048h 0072 2] PCI Segment start : 0000
39
[04Ah 0074 2] PCI Segment end : 0000
40
[04Ch 0076 2] PCI BDF start : 3000
41
[04Eh 0078 2] PCI BDF end : 30FF
42
[050h 0080 2] Output node : 0030
43
[052h 0082 6] Reserved : 000000000000
44
45
[058h 0088 1] Type : 01 [PCI Range]
46
[059h 0089 1] Reserved : 00
47
[05Ah 0090 2] Length : 0018
48
49
[05Ch 0092 4] Endpoint start : 00001000
50
[060h 0096 2] PCI Segment start : 0000
51
[062h 0098 2] PCI Segment end : 0000
52
[064h 0100 2] PCI BDF start : 1000
53
[066h 0102 2] PCI BDF end : 10FF
54
[068h 0104 2] Output node : 0030
55
[06Ah 0106 6] Reserved : 000000000000
56
57
And the DSDT diff is:
58
59
@@ -XXX,XX +XXX,XX @@
60
*
61
* Disassembling to symbolic ASL+ operators
62
*
63
- * Disassembly of tests/data/acpi/q35/DSDT, Fri Dec 10 15:03:08 2021
64
+ * Disassembly of /tmp/aml-H9Y5D1, Fri Dec 10 15:02:27 2021
65
*
66
* Original Table Header:
67
* Signature "DSDT"
68
- * Length 0x00002061 (8289)
69
+ * Length 0x000024B6 (9398)
70
* Revision 0x01 **** 32-bit table (V1), no 64-bit math support
71
- * Checksum 0xFA
72
+ * Checksum 0xA7
73
* OEM ID "BOCHS "
74
* OEM Table ID "BXPC "
75
* OEM Revision 0x00000001 (1)
76
@@ -XXX,XX +XXX,XX @@
77
}
78
}
79
80
+ Scope (\_SB)
81
+ {
82
+ Device (PC30)
83
+ {
84
+ Name (_UID, 0x30) // _UID: Unique ID
85
+ Name (_BBN, 0x30) // _BBN: BIOS Bus Number
86
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
87
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
88
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
89
+ {
90
+ CreateDWordField (Arg3, Zero, CDW1)
91
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
92
+ {
93
+ CreateDWordField (Arg3, 0x04, CDW2)
94
+ CreateDWordField (Arg3, 0x08, CDW3)
95
+ Local0 = CDW3 /* \_SB_.PC30._OSC.CDW3 */
96
+ Local0 &= 0x1F
97
+ If ((Arg1 != One))
98
+ {
99
+ CDW1 |= 0x08
100
+ }
101
+
102
+ If ((CDW3 != Local0))
103
+ {
104
+ CDW1 |= 0x10
105
+ }
106
+
107
+ CDW3 = Local0
108
+ }
109
+ Else
110
+ {
111
+ CDW1 |= 0x04
112
+ }
113
+
114
+ Return (Arg3)
115
+ }
116
+
117
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
118
+ {
119
+ Local0 = Package (0x80){}
120
+ Local1 = Zero
121
+ While ((Local1 < 0x80))
122
+ {
123
+ Local2 = (Local1 >> 0x02)
124
+ Local3 = ((Local1 + Local2) & 0x03)
125
+ If ((Local3 == Zero))
126
+ {
127
+ Local4 = Package (0x04)
128
+ {
129
+ Zero,
130
+ Zero,
131
+ LNKD,
132
+ Zero
133
+ }
134
+ }
135
+
136
+ If ((Local3 == One))
137
+ {
138
+ Local4 = Package (0x04)
139
+ {
140
+ Zero,
141
+ Zero,
142
+ LNKA,
143
+ Zero
144
+ }
145
+ }
146
+
147
+ If ((Local3 == 0x02))
148
+ {
149
+ Local4 = Package (0x04)
150
+ {
151
+ Zero,
152
+ Zero,
153
+ LNKB,
154
+ Zero
155
+ }
156
+ }
157
+
158
+ If ((Local3 == 0x03))
159
+ {
160
+ Local4 = Package (0x04)
161
+ {
162
+ Zero,
163
+ Zero,
164
+ LNKC,
165
+ Zero
166
+ }
167
+ }
168
+
169
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
170
+ Local4 [One] = (Local1 & 0x03)
171
+ Local0 [Local1] = Local4
172
+ Local1++
173
+ }
174
+
175
+ Return (Local0)
176
+ }
177
+
178
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
179
+ {
180
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
181
+ 0x0000, // Granularity
182
+ 0x0030, // Range Minimum
183
+ 0x0030, // Range Maximum
184
+ 0x0000, // Translation Offset
185
+ 0x0001, // Length
186
+ ,, )
187
+ })
188
+ }
189
+ }
190
+
191
+ Scope (\_SB)
192
+ {
193
+ Device (PC20)
194
+ {
195
+ Name (_UID, 0x20) // _UID: Unique ID
196
+ Name (_BBN, 0x20) // _BBN: BIOS Bus Number
197
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
198
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
199
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
200
+ {
201
+ CreateDWordField (Arg3, Zero, CDW1)
202
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
203
+ {
204
+ CreateDWordField (Arg3, 0x04, CDW2)
205
+ CreateDWordField (Arg3, 0x08, CDW3)
206
+ Local0 = CDW3 /* \_SB_.PC20._OSC.CDW3 */
207
+ Local0 &= 0x1F
208
+ If ((Arg1 != One))
209
+ {
210
+ CDW1 |= 0x08
211
+ }
212
+
213
+ If ((CDW3 != Local0))
214
+ {
215
+ CDW1 |= 0x10
216
+ }
217
+
218
+ CDW3 = Local0
219
+ }
220
+ Else
221
+ {
222
+ CDW1 |= 0x04
223
+ }
224
+
225
+ Return (Arg3)
226
+ }
227
+
228
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
229
+ {
230
+ Local0 = Package (0x80){}
231
+ Local1 = Zero
232
+ While ((Local1 < 0x80))
233
+ {
234
+ Local2 = (Local1 >> 0x02)
235
+ Local3 = ((Local1 + Local2) & 0x03)
236
+ If ((Local3 == Zero))
237
+ {
238
+ Local4 = Package (0x04)
239
+ {
240
+ Zero,
241
+ Zero,
242
+ LNKD,
243
+ Zero
244
+ }
245
+ }
246
+
247
+ If ((Local3 == One))
248
+ {
249
+ Local4 = Package (0x04)
250
+ {
251
+ Zero,
252
+ Zero,
253
+ LNKA,
254
+ Zero
255
+ }
256
+ }
257
+
258
+ If ((Local3 == 0x02))
259
+ {
260
+ Local4 = Package (0x04)
261
+ {
262
+ Zero,
263
+ Zero,
264
+ LNKB,
265
+ Zero
266
+ }
267
+ }
268
+
269
+ If ((Local3 == 0x03))
270
+ {
271
+ Local4 = Package (0x04)
272
+ {
273
+ Zero,
274
+ Zero,
275
+ LNKC,
276
+ Zero
277
+ }
278
+ }
279
+
280
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
281
+ Local4 [One] = (Local1 & 0x03)
282
+ Local0 [Local1] = Local4
283
+ Local1++
284
+ }
285
+
286
+ Return (Local0)
287
+ }
288
+
289
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
290
+ {
291
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
292
+ 0x0000, // Granularity
293
+ 0x0020, // Range Minimum
294
+ 0x0020, // Range Maximum
295
+ 0x0000, // Translation Offset
296
+ 0x0001, // Length
297
+ ,, )
298
+ })
299
+ }
300
+ }
301
+
302
+ Scope (\_SB)
303
+ {
304
+ Device (PC10)
305
+ {
306
+ Name (_UID, 0x10) // _UID: Unique ID
307
+ Name (_BBN, 0x10) // _BBN: BIOS Bus Number
308
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
309
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
310
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
311
+ {
312
+ CreateDWordField (Arg3, Zero, CDW1)
313
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
314
+ {
315
+ CreateDWordField (Arg3, 0x04, CDW2)
316
+ CreateDWordField (Arg3, 0x08, CDW3)
317
+ Local0 = CDW3 /* \_SB_.PC10._OSC.CDW3 */
318
+ Local0 &= 0x1F
319
+ If ((Arg1 != One))
320
+ {
321
+ CDW1 |= 0x08
322
+ }
323
+
324
+ If ((CDW3 != Local0))
325
+ {
326
+ CDW1 |= 0x10
327
+ }
328
+
329
+ CDW3 = Local0
330
+ }
331
+ Else
332
+ {
333
+ CDW1 |= 0x04
334
+ }
335
+
336
+ Return (Arg3)
337
+ }
338
+
339
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
340
+ {
341
+ Local0 = Package (0x80){}
342
+ Local1 = Zero
343
+ While ((Local1 < 0x80))
344
+ {
345
+ Local2 = (Local1 >> 0x02)
346
+ Local3 = ((Local1 + Local2) & 0x03)
347
+ If ((Local3 == Zero))
348
+ {
349
+ Local4 = Package (0x04)
350
+ {
351
+ Zero,
352
+ Zero,
353
+ LNKD,
354
+ Zero
355
+ }
356
+ }
357
+
358
+ If ((Local3 == One))
359
+ {
360
+ Local4 = Package (0x04)
361
+ {
362
+ Zero,
363
+ Zero,
364
+ LNKA,
365
+ Zero
366
+ }
367
+ }
368
+
369
+ If ((Local3 == 0x02))
370
+ {
371
+ Local4 = Package (0x04)
372
+ {
373
+ Zero,
374
+ Zero,
375
+ LNKB,
376
+ Zero
377
+ }
378
+ }
379
+
380
+ If ((Local3 == 0x03))
381
+ {
382
+ Local4 = Package (0x04)
383
+ {
384
+ Zero,
385
+ Zero,
386
+ LNKC,
387
+ Zero
388
+ }
389
+ }
390
+
391
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
392
+ Local4 [One] = (Local1 & 0x03)
393
+ Local0 [Local1] = Local4
394
+ Local1++
395
+ }
396
+
397
+ Return (Local0)
398
+ }
399
+
400
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
401
+ {
402
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
403
+ 0x0000, // Granularity
404
+ 0x0010, // Range Minimum
405
+ 0x0010, // Range Maximum
406
+ 0x0000, // Translation Offset
407
+ 0x0001, // Length
408
+ ,, )
409
+ })
410
+ }
411
+ }
412
+
413
Scope (\_SB.PCI0)
414
{
415
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
416
@@ -XXX,XX +XXX,XX @@
417
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
418
0x0000, // Granularity
419
0x0000, // Range Minimum
420
- 0x00FF, // Range Maximum
421
+ 0x000F, // Range Maximum
422
0x0000, // Translation Offset
423
- 0x0100, // Length
424
+ 0x0010, // Length
425
,, )
426
IO (Decode16,
427
0x0CF8, // Range Minimum
428
@@ -XXX,XX +XXX,XX @@
429
}
430
}
431
432
+ Device (S10)
433
+ {
434
+ Name (_ADR, 0x00020000) // _ADR: Address
435
+ }
436
+
437
+ Device (S18)
438
+ {
439
+ Name (_ADR, 0x00030000) // _ADR: Address
440
+ }
441
+
442
+ Device (S20)
443
+ {
444
+ Name (_ADR, 0x00040000) // _ADR: Address
445
+ }
446
+
447
+ Device (S28)
448
+ {
449
+ Name (_ADR, 0x00050000) // _ADR: Address
450
+ }
451
+
452
Method (PCNT, 0, NotSerialized)
453
{
454
}
455
456
Reviewed-by: Eric Auger <eric.auger@redhat.com>
457
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
458
Message-id: 20211210170415.583179-8-jean-philippe@linaro.org
459
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
460
---
461
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
462
tests/data/acpi/q35/DSDT.viot | Bin 0 -> 9398 bytes
463
tests/data/acpi/q35/VIOT.viot | Bin 0 -> 112 bytes
464
3 files changed, 2 deletions(-)
465
466
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
467
index XXXXXXX..XXXXXXX 100644
468
--- a/tests/qtest/bios-tables-test-allowed-diff.h
469
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
470
@@ -XXX,XX +XXX,XX @@
471
/* List of comma-separated changed AML files to ignore */
472
"tests/data/acpi/virt/VIOT",
473
-"tests/data/acpi/q35/DSDT.viot",
474
-"tests/data/acpi/q35/VIOT.viot",
475
diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot
476
index XXXXXXX..XXXXXXX 100644
477
GIT binary patch
478
literal 9398
479
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480
z5(9Az1F`}niVsB-)<KW7p`g9Br(A2Gm-gmc1N78GFS!;)e2V(MnH_0{q<{#yMgn&C
481
zn|*J-d9yqFhO_H6z19~`FlPL*u<DkZ*}|)JH;X@mF-FI<cPg<fti9tEN*yB^i5czN
482
zNq&q?!OZ;BE3B7{KWzJ-`Tn~f`9?Qj8~2^N8{Oc8J%57{==w%rS#;nOCp*nTr@iZ1
483
zb+?i;JLQUJ=O0?8*>S~D)a>NF1~WVB6^~_B#yhJ`H+JU@=6aXs`?Yv)J2h=N?drcS
484
zeLZ*n<<Bm^n}6`jfBx#u8&(W}1?)}iF9o#mZ~E2+zwdn7yK3AbIzKnxpZ>JRPm3~#
485
z&ICS{+_OayRW-l=Mtk=~uaS3o8z<_udd|(wqg`&JnVPfCe>BUOO`Su3e>pff_^UW%
486
z&JE^NO`)=Amg~iqRB1pPscP?(>#ZuY8GHCmlEvD$9g3%4Db~Dfz2SATnddvrR-Oe^
487
z;s;dJec!hnzi)ri^I6YN9vtkm{^TdUF8h7gX8-<Qe4p)GQ=)AtYx2VcwdLVAEXEjG
488
z^Mj|UHPqkj-LsWuzQem1>F3atdZn=zv3$#RmZzSHN+6-yyU#8cJb=YDilX&sl}vNm
489
znkgAR^O<3kj4if>{ly5fwRfMWuC5=lrlvKPX~i#654Cp}R_d*JS$9laZ$ra6)<ns8
490
zFZy28G%xP(nit&F>LDi%G<tIc=TY=gl$jSD&Uv!Yat~XR46h%rI$!}a%!|xG7u8Zn
491
zeY8_|n=K>xz_v_W8VX$W-Fg-qFWcT}7MCyz{%%{ia7hZ>Law-k6NOr}VI&_48U=2l
492
zwqDKFE8eTwwozDdms#e?x?5a|v>&JF;2_v0L~z5n%BYU^52<*cWuD4|GYUm@1+?))
493
zte^45>Rz)t*<T5V#={r>@t@{%?^i#W{i=HAZ*Dc9y59Va-+#P!jrGs;u38a{fLr`N
494
zvT@rUu>DljxJ?^&Z?-?vyJn3C>3D=qux{Y*bs5|5n)Qmi$TD^Zdn4GU$ocJS2Hh-<
495
z`xPI^^+v0nUVdjMos8k`WGl7hA`{03ju%<lrgAHSpd^DRf-*}_#Ly0mB!LSfVgWcQ
496
z&T$@~G9)JI=hz5m0vkrel+Xy{Oh7pkAu-V!j*W7rY(bO}Q$nMH2`FbGB&N)QaV4<4
497
zo)~9JXiP9=;}NPl<C@MmXG&;XFlFNrsyfFsonxFSp<}vEgsRSQP3O3#b6nSnP}ON_
498
zI!#Tdsp~|j>ckUB>FI=~GokB5sOq#dotCE4(sd$KbtW~PNlj-`*NIToiD#j5J#9^=
499
zt?NXn>YUJYPG~wObe#xQos*i*NloXZt`niEb4t@WrRki~bs|)CI+{*L)9L6s5vn><
500
zn$DD_Go|Z9sOn5>I@6lYw5}7Os&iV?Ij!lO)^#FOb!If38BJ$K*NIToIiu;E(R9w}
501
zIuWWmPiZ<&X*y5oIuWWmF_XaEC!a&Jn$B5WCqh-{X-(&8P3LJ{Cqh-{8P3dyPr@^t
502
zSqL9?X9Uwd3W@23*s~h*tj0X6GZCuHa~kuU#yqDp5vt7d8uPryJg+kms?5hU=3^T3
503
zF`bD}WnSP+=`t5MQ$FJ_2&Q~+BP6E0f^%BVIW6a$o)e+SX~IDBih-7z6{O~7YTy`&
504
zLjy&Cv?7QikV#>n0>>@MV8oK`Gmun34-FKdlm-J8SZSaNlnhir4-FI{S|bfqV8e)V
505
zss<{chX#reE#g=hsKAC%sF6d-Km}BWs!kZFsFpKfpbC@>6rprQGEjt4Ck#|zITHq|
506
zK*>M_l;<P^MJRQ`Kn0dFVW0|>3{*fllMEE0)CmI>Sk8ojDo`>|0p(0GP=xY&!axO<
507
zGhv_#lnhirIg<<&q0|Wj6<E%MfhtfkPyyvkGEjt4Ck#|zITHq|K*>M_lrzad5lWpf
508
zP=V!47^ngz0~JutBm+e#b;3XemNQ|X3X}{~Ksl2P6rt1!0~J`#gn=qhGEf2KOfpb}
509
zQYQ>lU^x>8szAv=1(Y+%KoLrvFi?TzOc<yFB?A>u&LjgxD0RX>1(q{mpbC@>R6seC
510
z3>2Z%2?G^a&V+#~P%=;f<xDbAgi<FARA4z12C6{GKn0XD$v_cGoiI>=<xCi;0wn_#
511
zP|hR+MJRQ`Kn0dFVW0|>3{*fllMEE0)CmI>Sk8ojDo`>|0p(0GP=rz^3{+q_69%e4
512
z$v_2^Gs!>^N}VuJf#pmXr~)Me6;RG314Srx!axxz28u{EP=u<1B2)}iVZuNaCK;&0
513
zBm-5LFi?dF167!0pbC==RAItE6($T+VUmF=Ofpb~2?JG_Fi?d_2C6X0Kouqo6p_5T
514
zFi=FeV!SiSKoR0H$dH(_Z(*Q_WZ%L-5y`$K14StNmJAdjmWs}HV4<vU_xO+1efmLq
515
zZ;W>N_U)fP6Qy6Nw5mbt9Y(#emWSi66=>tq#xoh#Ue=0qyhxi8ZOUe5y0V7VfPUhp
516
zwX=;ymc+i5%sg9Ja~lZ&8oAV@mHc>&CHP9v4R(jhtT?un;O4e9#pno)Xkh7OWgK&a
517
zyj=3Iv0OuoK_;5rOr5f(Kb~ZXDBO+V`OWYo#_C08imwChQxnjdd?wZLDou8aj;$SD
518
zGDYiA3<$Tu<JnHL(KPOChi#zrR32t83}naR$+ym4P_h?z_5#|cW-nw$XD_sOtE62l
519
zrD3@*)NVyiklt0&yF9%+klsBey&I<Y2E<!f(E8TuJte)z(|ZHyy<^gQVfx}=`q&B5
520
z7nSryp1wGczIaUfVwiq$Fn#<4=@*ssi#+|}K>EdF(l3VTOM~ghPLRH&q%ZOGrGfON
521
zW73zx^yR_y<0nX8R??Sw`tm^f@-gYlNFSp|*<gA{q?Zp5Oe-+l#rmyYmKozi9y=P>
522
zVReJU*h=ZuVXiS$ohTbw-O#v9>(yZbGE|)?8(H1ZIKvV!jWa0>vy!3eMA^vdhQ>`s
523
zuMSg{q3T50$m)j1!HixV<}X9liL#N^4c*tL^y)CF8LCc{jjV3yKAqL8!%SzWI#H%q
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z=bSrQ&)%JCRttF5g4Zf`6l?y@>PzD7MA^D>wBlcH6r1ucwJ<p0O%rZ?JzIY3-QdmZ
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zBPa51y^_n#=cpOt#Zf$ya$Ae9Mfz56n|<i!a=ELS@)%a{^NIH3SDuN<R~sah1km#P
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zU@?*f%<rG=4W1wgfi;C?_n|W@%lm$&8YfvNOJodIg&IcIpIJQRHr<+ej11GQ6)&eF
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z2Lam*jIH}#y0>KnY%4JQfOYS$*uU%f#@$U6`N8I3N-lV?5ErFCdv~xDmu2(wexld4
530
z4v^;aVAT2k6GJ^m*FD(Wqc(Qg^)6a<?}h$zLoj}4;PP!+(O{@!a1y-hoAhF_7!z+6
531
zslpAmNtYbjHrw-~#SPVk_FUf>-Obg6yV`8o$8_`PyJe_;bY5_EMBfBfWU!Q=*9HsG
532
z%_Cda{@_Krr!oHVhv9+y+T5qR8zZ2aZ>5r!$*|f$^U%yBUYfR&B!+EYy_PwL!BeUi
533
zJH^}r3r9Q+B)X@Z)fk=P13w&7x#wBtXTZ)g>WITPg5r&pQc!nmyrmk#S(>>b9xnNr
534
zx_b#v9Xv-Y><Wb%?S^0Xe&<)bbKl_=Z|3C$tf|F<bYzE*mfHB;uC)`q-?buaBe?l?
535
zcLTpK*k<49Z32`K?|nSBMFqxTK^_IE-li2fEGdK~(ZdoKBl6ab4a;Hler#`xvEXJG
536
zb?<E%EZExfX>jcOVhS*0rS~RS1dA#xhkv@Nct@#q?LyeKS<$uFec!bw>{@uu$gZ6a
537
zyVen1i{1BKd%~`D7|m$;U0a<I*3I7%^N%N%lGYdU_GS!gaR8T$NA@GzFi~z`l7hdl
538
zarZy6590|88pi(1zq;V(>38zM0sT&<zX;R5$1w3;`_JMG`;&I&0Y23DMx1%@(w(R9
539
z4M$j;D5J+Gy%fijRQsctzFKf&cv|BAz#YLq3CZJWDdtL4u1u1|mkdcUp7|sxJC+?Y
540
z_@@s`v3j}Q7*z>6X~cwUxUL8G1KT)_XTp!KAbs;vCp{K3&~_X@+ew=-D}v`2MbFV0
541
zQsVsL=rXi-pI*G|iiz;VTCutgUs)hDzV1+4?8KcoP3xROf<M%qC6lgVdpFt4<-|uM
542
z=#rl_b1#YjSIl6Toj2z_hOZcKupkdE(LozC(fN=FY(x|sk)ym|;Rq2E1xJWD%Z!ol
543
Gu>S+TT-130
544
545
literal 0
546
HcmV?d00001
547
548
diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot
549
index XXXXXXX..XXXXXXX 100644
550
GIT binary patch
551
literal 112
552
zcmWIZ^baXu00LVle`k+i1*eDrX9XZ&1PX!JAex!M0Hgv8m>C3sGzdcgBZCA3T-xBj
553
Q0Zb)W9Hva*zW_`e0M!8s0RR91
554
555
literal 0
556
HcmV?d00001
557
558
--
559
2.25.1
560
561
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
Both lqspi_read() and lqspi_load_cache() expect a 32-bit
3
The VIOT blob contains the following:
4
aligned address.
5
4
6
>From UG1085 datasheet [*] chapter on 'Quad-SPI Controller':
5
[000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table]
6
[004h 0004 4] Table Length : 00000058
7
[008h 0008 1] Revision : 00
8
[009h 0009 1] Checksum : 66
9
[00Ah 0010 6] Oem ID : "BOCHS "
10
[010h 0016 8] Oem Table ID : "BXPC "
11
[018h 0024 4] Oem Revision : 00000001
12
[01Ch 0028 4] Asl Compiler ID : "BXPC"
13
[020h 0032 4] Asl Compiler Revision : 00000001
7
14
8
Transfer Size Limitations
15
[024h 0036 2] Node count : 0002
16
[026h 0038 2] Node offset : 0030
17
[028h 0040 8] Reserved : 0000000000000000
9
18
10
Because of the 32-bit wide TX, RX, and generic FIFO, all
19
[030h 0048 1] Type : 03 [VirtIO-PCI IOMMU]
11
APB/AXI transfers must be an integer multiple of 4-bytes.
20
[031h 0049 1] Reserved : 00
12
Shorter transfers are not possible.
21
[032h 0050 2] Length : 0010
13
22
14
Set MemoryRegionOps.impl values to force 32-bit accesses,
23
[034h 0052 2] PCI Segment : 0000
15
this way we are sure we do not access the lqspi_buf[] array
24
[036h 0054 2] PCI BDF number : 0008
16
out of bound.
25
[038h 0056 8] Reserved : 0000000000000000
17
26
18
[*] https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
27
[040h 0064 1] Type : 01 [PCI Range]
28
[041h 0065 1] Reserved : 00
29
[042h 0066 2] Length : 0018
19
30
20
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
31
[044h 0068 4] Endpoint start : 00000000
21
Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
32
[048h 0072 2] PCI Segment start : 0000
22
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
33
[04Ah 0074 2] PCI Segment end : 0000
34
[04Ch 0076 2] PCI BDF start : 0000
35
[04Eh 0078 2] PCI BDF end : 00FF
36
[050h 0080 2] Output node : 0030
37
[052h 0082 6] Reserved : 000000000000
38
39
Acked-by: Ani Sinha <ani@anisinha.ca>
40
Reviewed-by: Eric Auger <eric.auger@redhat.com>
41
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
42
Message-id: 20211210170415.583179-9-jean-philippe@linaro.org
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
43
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
---
44
---
25
hw/ssi/xilinx_spips.c | 4 ++++
45
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
26
1 file changed, 4 insertions(+)
46
tests/data/acpi/virt/VIOT | Bin 0 -> 88 bytes
47
2 files changed, 1 deletion(-)
27
48
28
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
49
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
29
index XXXXXXX..XXXXXXX 100644
50
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/ssi/xilinx_spips.c
51
--- a/tests/qtest/bios-tables-test-allowed-diff.h
31
+++ b/hw/ssi/xilinx_spips.c
52
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
32
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps lqspi_ops = {
53
@@ -1,2 +1 @@
33
.read_with_attrs = lqspi_read,
54
/* List of comma-separated changed AML files to ignore */
34
.write_with_attrs = lqspi_write,
55
-"tests/data/acpi/virt/VIOT",
35
.endianness = DEVICE_NATIVE_ENDIAN,
56
diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT
36
+ .impl = {
57
index XXXXXXX..XXXXXXX 100644
37
+ .min_access_size = 4,
58
GIT binary patch
38
+ .max_access_size = 4,
59
literal 88
39
+ },
60
zcmWIZ^bd((0D?3pe`k+i1*eDrX9XZ&1PX!JAexE60Hgv8m>C3sGzXN&z`)2L0cSHX
40
.valid = {
61
I{D-Rq0Q5fy0RR91
41
.min_access_size = 1,
62
42
.max_access_size = 4
63
literal 0
64
HcmV?d00001
65
43
--
66
--
44
2.20.1
67
2.25.1
45
68
46
69
diff view generated by jsdifflib