Series comparison

-[Qemu-devel] [PULL 00/10] target-arm queue
+[PULL 00/27] target-arm queue
-target-arm queue for rc1 -- these are all bug fixes.
+arm queue: big stuff here is my MVE codegen optimisation,
 and Alex's Apple Silicon hvf support.
-thanks
 -- PMM
-The following changes since commit b9404bf592e7ba74180e1a54ed7a266ec6ee67f2:
+The following changes since commit 7adb961995a3744f51396502b33ad04a56a317c3:
-  Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20190715' into staging (2019-07-15 12:22:07 +0100)
+  Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20210916' into staging (2021-09-19 18:53:29 +0100)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190715
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210920
-for you to fetch changes up to 51c9122e92b776a3f16af0b9282f1dc5012e2a19:
+for you to fetch changes up to 1dc5a60bfe406bc1122d68cbdefda38d23134b27:
-  target/arm: NS BusFault on vector table fetch escalates to NS HardFault (2019-07-15 14:17:04 +0100)
+  target/arm: Optimize MVE 1op-immediate insns (2021-09-20 14:18:01 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * report ARMv8-A FP support for AArch32 -cpu max
+ * Optimize codegen for MVE when predication not active
- * hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
+ * hvf: Add Apple Silicon support
- * hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
+ * hw/intc: Set GIC maintenance interrupt level to only 0 or 1
- * hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
+ * Fix mishandling of MVE FPSCR.LTPSIZE reset for usermode emulator
- * hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
+ * elf2dmp: Fix coverity nits
  * hw/arm/virt: Fix non-secure flash mode
  * pl031: Correctly migrate state when using -rtc clock=host
  * fix regression that meant arm926 and arm1026 lost VFP
    double-precision support
  * v8M: NS BusFault on vector table fetch escalates to NS HardFault
 ----------------------------------------------------------------
-Alex Bennée (1):
+Alexander Graf (7):
-      target/arm: report ARMv8-A FP support for AArch32 -cpu max
+      arm: Move PMC register definitions to internals.h
       hvf: Add execute to dirty log permission bitmap
       hvf: Introduce hvf_arch_init() callback
       hvf: Add Apple Silicon support
       hvf: arm: Implement PSCI handling
       arm: Add Hypervisor.framework build target
       hvf: arm: Add rudimentary PMC support
-David Engraf (1):
+Peter Collingbourne (1):
-      hw/arm/virt: Fix non-secure flash mode
+      arm/hvf: Add a WFI handler
-Peter Maydell (3):
+Peter Maydell (18):
-      pl031: Correctly migrate state when using -rtc clock=host
+      elf2dmp: Check curl_easy_setopt() return value
-      target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026
+      elf2dmp: Fail cleanly if PDB file specifies zero block_size
-      target/arm: NS BusFault on vector table fetch escalates to NS HardFault
+      target/arm: Don't skip M-profile reset entirely in user mode
       target/arm: Always clear exclusive monitor on reset
       target/arm: Consolidate ifdef blocks in reset
       hvf: arm: Implement -cpu host
       target/arm: Avoid goto_tb if we're trying to exit to the main loop
       target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration
       target/arm: Add TB flag for "MVE insns not predicated"
       target/arm: Optimize MVE logic ops
       target/arm: Optimize MVE arithmetic ops
       target/arm: Optimize MVE VNEG, VABS
       target/arm: Optimize MVE VDUP
       target/arm: Optimize MVE VMVN
       target/arm: Optimize MVE VSHL, VSHR immediate forms
       target/arm: Optimize MVE VSHLL and VMOVL
       target/arm: Optimize MVE VSLI and VSRI
       target/arm: Optimize MVE 1op-immediate insns
-Philippe Mathieu-Daudé (5):
+Shashi Mallela (1):
-      hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs
+      hw/intc: Set GIC maintenance interrupt level to only 0 or 1
       hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
       hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
       hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
       hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
- include/hw/timer/pl031.h |  2 ++
+ meson.build                   |    8 +
- hw/arm/virt.c            |  2 +-
+ include/sysemu/hvf_int.h      |   12 +-
- hw/core/machine.c        |  1 +
+ target/arm/cpu.h              |    6 +-
- hw/display/xlnx_dp.c     | 15 +++++---
+ target/arm/hvf_arm.h          |   18 +
- hw/ssi/mss-spi.c         |  8 ++++-
+ target/arm/internals.h        |   44 ++
- hw/ssi/xilinx_spips.c    | 43 +++++++++++++++-------
+ target/arm/kvm_arm.h          |    2 -
- hw/timer/pl031.c         | 92 +++++++++++++++++++++++++++++++++++++++++++++---
+ target/arm/translate.h        |    2 +
- target/arm/cpu.c         | 16 +++++++++
+ accel/hvf/hvf-accel-ops.c     |   21 +-
- target/arm/m_helper.c    | 21 ++++++++---
+ contrib/elf2dmp/download.c    |   22 +-
-files changed, 174 insertions(+), 26 deletions(-)
+ contrib/elf2dmp/pdb.c         |    4 +
  hw/intc/arm_gicv3_cpuif.c     |    5 +-
  target/arm/cpu.c              |   56 +-
  target/arm/helper.c           |   77 ++-
  target/arm/hvf/hvf.c          | 1278 +++++++++++++++++++++++++++++++++++++++++
  target/arm/machine.c          |   13 +
  target/arm/translate-m-nocp.c |    8 +-
  target/arm/translate-mve.c    |  310 +++++++---
  target/arm/translate-vfp.c    |   33 +-
  target/arm/translate.c        |   42 +-
  target/i386/hvf/hvf.c         |   10 +
  MAINTAINERS                   |    5 +
  target/arm/hvf/meson.build    |    3 +
  target/arm/hvf/trace-events   |   11 +
  target/arm/meson.build        |    2 +
 files changed, 1824 insertions(+), 168 deletions(-)
  create mode 100644 target/arm/hvf_arm.h
  create mode 100644 target/arm/hvf/hvf.c
  create mode 100644 target/arm/hvf/meson.build
  create mode 100644 target/arm/hvf/trace-events

-New patch
+[PULL 01/27] elf2dmp: Check curl_easy_setopt() return value
+Coverity points out that we aren't checking the return value
+from curl_easy_setopt().
+Fixes: Coverity CID 1458895
+Inspired-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Viktor Prutyanov <viktor.prutyanov@phystech.edu>
+Tested-by: Viktor Prutyanov <viktor.prutyanov@phystech.edu>
+Message-id: 20210910170656.366592-2-philmd@redhat.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ contrib/elf2dmp/download.c | 22 ++++++++++------------
+file changed, 10 insertions(+), 12 deletions(-)
+diff --git a/contrib/elf2dmp/download.c b/contrib/elf2dmp/download.c
+index XXXXXXX..XXXXXXX 100644
+--- a/contrib/elf2dmp/download.c
++++ b/contrib/elf2dmp/download.c
+@@ -XXX,XX +XXX,XX @@ int download_url(const char *name, const char *url)
+         goto out_curl;
+     }
+-    curl_easy_setopt(curl, CURLOPT_URL, url);
+-    curl_easy_setopt(curl, CURLOPT_WRITEFUNCTION, NULL);
+-    curl_easy_setopt(curl, CURLOPT_WRITEDATA, file);
+-    curl_easy_setopt(curl, CURLOPT_FOLLOWLOCATION, 1);
+-    curl_easy_setopt(curl, CURLOPT_NOPROGRESS, 0);
+-
+-    if (curl_easy_perform(curl) != CURLE_OK) {
+-        err = 1;
+-        fclose(file);
++    if (curl_easy_setopt(curl, CURLOPT_URL, url) != CURLE_OK
++            || curl_easy_setopt(curl, CURLOPT_WRITEFUNCTION, NULL) != CURLE_OK
++            || curl_easy_setopt(curl, CURLOPT_WRITEDATA, file) != CURLE_OK
++            || curl_easy_setopt(curl, CURLOPT_FOLLOWLOCATION, 1) != CURLE_OK
++            || curl_easy_setopt(curl, CURLOPT_NOPROGRESS, 0) != CURLE_OK
++            || curl_easy_perform(curl) != CURLE_OK) {
+         unlink(name);
+-        goto out_curl;
++        fclose(file);
++        err = 1;
++    } else {
++        err = fclose(file);
+     }
+-    err = fclose(file);
+-
+ out_curl:
+     curl_easy_cleanup(curl);
+--
+.20.1

-New patch
+[PULL 02/27] elf2dmp: Fail cleanly if PDB file specifies zero block_size
+Coverity points out that if the PDB file we're trying to read
+has a header specifying a block_size of zero then we will
+end up trying to divide by zero in pdb_ds_read_file().
+Check for this and fail cleanly instead.
+Fixes: Coverity CID 1458869
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Viktor Prutyanov <viktor.prutyanov@phystech.edu>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Tested-by: Viktor Prutyanov <viktor.prutyanov@phystech.edu>
+Message-id: 20210910170656.366592-3-philmd@redhat.com
+Message-Id: <20210901143910.17112-3-peter.maydell@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+---
+ contrib/elf2dmp/pdb.c | 4 ++++
+file changed, 4 insertions(+)
+diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c
+index XXXXXXX..XXXXXXX 100644
+--- a/contrib/elf2dmp/pdb.c
++++ b/contrib/elf2dmp/pdb.c
+@@ -XXX,XX +XXX,XX @@ out_symbols:
+ static int pdb_reader_ds_init(struct pdb_reader *r, PDB_DS_HEADER *hdr)
+ {
++    if (hdr->block_size == 0) {
++        return 1;
++    }
++
+     memset(r->file_used, 0, sizeof(r->file_used));
+     r->ds.header = hdr;
+     r->ds.toc = pdb_ds_read(hdr, (uint32_t *)((uint8_t *)hdr +
+--
+.20.1

-New patch
+[PULL 03/27] target/arm: Don't skip M-profile reset entirely in user mode
+Currently all of the M-profile specific code in arm_cpu_reset() is
+inside a !defined(CONFIG_USER_ONLY) ifdef block.  This is
+unintentional: it happened because originally the only
+M-profile-specific handling was the setup of the initial SP and PC
+from the vector table, which is system-emulation only.  But then we
+added a lot of other M-profile setup to the same "if (ARM_FEATURE_M)"
+code block without noticing that it was all inside a not-user-mode
+ifdef.  This has generally been harmless, but with the addition of
+v8.1M low-overhead-loop support we ran into a problem: the reset of
+FPSCR.LTPSIZE to 4 was only being done for system emulation mode, so
+if a user-mode guest tried to execute the LE instruction it would
+incorrectly take a UsageFault.
+Adjust the ifdefs so only the really system-emulation specific parts
+are covered.  Because this means we now run some reset code that sets
+up initial values in the FPCCR and similar FPU related registers,
+explicitly set up the registers controlling FPU context handling in
+user-emulation mode so that the FPU works by design and not by
+chance.
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/613
+Cc: qemu-stable@nongnu.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210914120725.24992-2-peter.maydell@linaro.org
+---
+ target/arm/cpu.c | 19 +++++++++++++++++++
+file changed, 19 insertions(+)
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.c
++++ b/target/arm/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
+         env->uncached_cpsr = ARM_CPU_MODE_SVC;
+     }
+     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
++#endif
+     if (arm_feature(env, ARM_FEATURE_M)) {
++#ifndef CONFIG_USER_ONLY
+         uint32_t initial_msp; /* Loaded from 0x0 */
+         uint32_t initial_pc; /* Loaded from 0x4 */
+         uint8_t *rom;
+         uint32_t vecbase;
++#endif
+         if (cpu_isar_feature(aa32_lob, cpu)) {
+             /*
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
+             env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
+                 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
+         }
++
++#ifndef CONFIG_USER_ONLY
+         /* Unlike A/R profile, M profile defines the reset LR value */
+         env->regs[14] = 0xffffffff;
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
+         env->regs[13] = initial_msp & 0xFFFFFFFC;
+         env->regs[15] = initial_pc & ~1;
+         env->thumb = initial_pc & 1;
++#else
++        /*
++         * For user mode we run non-secure and with access to the FPU.
++         * The FPU context is active (ie does not need further setup)
++         * and is owned by non-secure.
++         */
++        env->v7m.secure = false;
++        env->v7m.nsacr = 0xcff;
++        env->v7m.cpacr[M_REG_NS] = 0xf0ffff;
++        env->v7m.fpccr[M_REG_S] &=
++            ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK);
++        env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK;
++#endif
+     }
++#ifndef CONFIG_USER_ONLY
+     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
+      * executing as AArch32 then check if highvecs are enabled and
+      * adjust the PC accordingly.
+--
+.20.1

-New patch
+[PULL 04/27] target/arm: Always clear exclusive monitor on reset
+There's no particular reason why the exclusive monitor should
+be only cleared on reset in system emulation mode. It doesn't
+hurt if it isn't cleared in user mode, but we might as well
+reduce the amount of code we have that's inside an ifdef.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210914120725.24992-3-peter.maydell@linaro.org
+---
+ target/arm/cpu.c | 6 +++---
+file changed, 3 insertions(+), 3 deletions(-)
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.c
++++ b/target/arm/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
+         env->regs[15] = 0xFFFF0000;
+     }
++    env->vfp.xregs[ARM_VFP_FPEXC] = 0;
++#endif
++
+     /* M profile requires that reset clears the exclusive monitor;
+      * A profile does not, but clearing it makes more sense than having it
+      * set with an exclusive access on address zero.
+      */
+     arm_clear_exclusive(env);
+-    env->vfp.xregs[ARM_VFP_FPEXC] = 0;
+-#endif
+-
+     if (arm_feature(env, ARM_FEATURE_PMSA)) {
+         if (cpu->pmsav7_dregion > 0) {
+             if (arm_feature(env, ARM_FEATURE_V8)) {
+--
+.20.1

-[Qemu-devel] [PULL 09/10] target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026
+[PULL 05/27] target/arm: Consolidate ifdef blocks in reset
-The ARMv5 architecture didn't specify detailed per-feature ID
+Move an ifndef CONFIG_USER_ONLY code block up in arm_cpu_reset() so
-registers. Now that we're using the MVFR0 register fields to
+it can be merged with another earlier one.
 gate the existence of VFP instructions, we need to set up
 the correct values in the cpu->isar structure so that we still
 provide an FPU to the guest.
-This fixes a regression in the arm926 and arm1026 CPUs, which
-are the only ones that both have VFP and are ARMv5 or earlier.
-This regression was introduced by the VFP refactoring, and more
-specifically by commits 1120827fa182f0e76 and 266bd25c485597c,
-which accidentally disabled VFP short-vector support and
-double-precision support on these CPUs.
-Fixes: 1120827fa182f0e
-Fixes: 266bd25c485597c
-Fixes: https://bugs.launchpad.net/qemu/+bug/1836192
-Reported-by: Christophe Lyon <christophe.lyon@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Message-id: 20210914120725.24992-4-peter.maydell@linaro.org
 Tested-by: Christophe Lyon <christophe.lyon@linaro.org>
 Message-id: 20190711131241.22231-1-peter.maydell@linaro.org
 ---
- target/arm/cpu.c | 12 ++++++++++++
+ target/arm/cpu.c | 22 ++++++++++------------
-file changed, 12 insertions(+)
+file changed, 10 insertions(+), 12 deletions(-)
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm926_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
-      * set the field to indicate Jazelle support within QEMU.
+         env->uncached_cpsr = ARM_CPU_MODE_SVC;
-      */
+     }
-     cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
+     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
-+    /*
++
-+     * Similarly, we need to set MVFR0 fields to enable double precision
++    /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
-+     * and short vector support even though ARMv5 doesn't have this register.
++     * executing as AArch32 then check if highvecs are enabled and
 +     * adjust the PC accordingly.
 +     */
-+    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
++    if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
-+    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
++        env->regs[15] = 0xFFFF0000;
- }
++    }
++
- static void arm946_initfn(Object *obj)
++    env->vfp.xregs[ARM_VFP_FPEXC] = 0;
-@@ -XXX,XX +XXX,XX @@ static void arm1026_initfn(Object *obj)
+ #endif
-      * set the field to indicate Jazelle support within QEMU.
-      */
+     if (arm_feature(env, ARM_FEATURE_M)) {
-     cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
-+    /*
+ #endif
-+     * Similarly, we need to set MVFR0 fields to enable double precision
+     }
-+     * and short vector support even though ARMv5 doesn't have this register.
-+     */
+-#ifndef CONFIG_USER_ONLY
-+    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+-    /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
-+    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
+-     * executing as AArch32 then check if highvecs are enabled and
+-     * adjust the PC accordingly.
-     {
+-     */
-         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
+-    if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 -        env->regs[15] = 0xFFFF0000;
 -    }
 -
 -    env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 -#endif
 -
      /* M profile requires that reset clears the exclusive monitor;
       * A profile does not, but clearing it makes more sense than having it
       * set with an exclusive access on address zero.
 --
 .20.1

-[Qemu-devel] [PULL 07/10] hw/arm/virt: Fix non-secure flash mode
+[PULL 06/27] hw/intc: Set GIC maintenance interrupt level to only 0 or 1
-From: David Engraf <david.engraf@sysgo.com>
+From: Shashi Mallela <shashi.mallela@linaro.org>
-Using the whole 128 MiB flash in non-secure mode is not working because
+During sbsa acs level 3 testing, it is seen that the GIC maintenance
-virt_flash_fdt() expects the same address for secure_sysmem and sysmem.
+interrupts are not triggered and the related test cases fail.  This
-This is not correctly handled by caller because it forwards NULL for
+is because we were incorrectly passing the value of the MISR register
-secure_sysmem in non-secure flash mode.
+(from maintenance_interrupt_state()) to qemu_set_irq() as the level
 argument, whereas the device on the other end of this irq line
 expects a 0/1 value.
-Fixed by using sysmem when secure_sysmem is NULL.
+Fix the logic to pass a 0/1 level indication, rather than a
 /not-0 value.
-Signed-off-by: David Engraf <david.engraf@sysgo.com>
+Fixes: c5fc89b36c0 ("hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()")
-Message-id: 20190712075002.14326-1-david.engraf@sysgo.com
+Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20210915205809.59068-1-shashi.mallela@linaro.org
 [PMM: tweaked commit message; collapsed nested if()s into one]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 2 +-
+ hw/intc/arm_gicv3_cpuif.c | 5 +++--
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 3 insertions(+), 2 deletions(-)
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/hw/arm/virt.c
++++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
-                                     &machine->device_memory->mr);
+         }
      }
--    virt_flash_fdt(vms, sysmem, secure_sysmem);
+-    if (cs->ich_hcr_el2 & ICH_HCR_EL2_EN) {
-+    virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
+-        maintlevel = maintenance_interrupt_state(cs);
++    if ((cs->ich_hcr_el2 & ICH_HCR_EL2_EN) &&
-     create_gic(vms, pic);
++        maintenance_interrupt_state(cs) != 0) {
++        maintlevel = 1;
      }
      trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel,
 --
 .20.1

-New patch
+[PULL 07/27] arm: Move PMC register definitions to internals.h
+From: Alexander Graf <agraf@csgraf.de>
+We will need PMC register definitions in accel specific code later.
+Move all constant definitions to common arm headers so we can reuse
+them.
+Signed-off-by: Alexander Graf <agraf@csgraf.de>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20210916155404.86958-2-agraf@csgraf.de
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/internals.h | 44 ++++++++++++++++++++++++++++++++++++++++++
+ target/arm/helper.c    | 44 ------------------------------------------
+files changed, 44 insertions(+), 44 deletions(-)
+diff --git a/target/arm/internals.h b/target/arm/internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/internals.h
++++ b/target/arm/internals.h
+@@ -XXX,XX +XXX,XX @@ enum MVEECIState {
+     /* All other values reserved */
+ };
++/* Definitions for the PMU registers */
++#define PMCRN_MASK  0xf800
++#define PMCRN_SHIFT 11
++#define PMCRLC  0x40
++#define PMCRDP  0x20
++#define PMCRX   0x10
++#define PMCRD   0x8
++#define PMCRC   0x4
++#define PMCRP   0x2
++#define PMCRE   0x1
++/*
++ * Mask of PMCR bits writeable by guest (not including WO bits like C, P,
++ * which can be written as 1 to trigger behaviour but which stay RAZ).
++ */
++#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
++
++#define PMXEVTYPER_P          0x80000000
++#define PMXEVTYPER_U          0x40000000
++#define PMXEVTYPER_NSK        0x20000000
++#define PMXEVTYPER_NSU        0x10000000
++#define PMXEVTYPER_NSH        0x08000000
++#define PMXEVTYPER_M          0x04000000
++#define PMXEVTYPER_MT         0x02000000
++#define PMXEVTYPER_EVTCOUNT   0x0000ffff
++#define PMXEVTYPER_MASK       (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
++                               PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
++                               PMXEVTYPER_M | PMXEVTYPER_MT | \
++                               PMXEVTYPER_EVTCOUNT)
++
++#define PMCCFILTR             0xf8000000
++#define PMCCFILTR_M           PMXEVTYPER_M
++#define PMCCFILTR_EL0         (PMCCFILTR | PMCCFILTR_M)
++
++static inline uint32_t pmu_num_counters(CPUARMState *env)
++{
++  return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
++}
++
++/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
++static inline uint64_t pmu_counter_mask(CPUARMState *env)
++{
++  return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
++}
++
+ #endif
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
+     REGINFO_SENTINEL
+ };
+-/* Definitions for the PMU registers */
+-#define PMCRN_MASK  0xf800
+-#define PMCRN_SHIFT 11
+-#define PMCRLC  0x40
+-#define PMCRDP  0x20
+-#define PMCRX   0x10
+-#define PMCRD   0x8
+-#define PMCRC   0x4
+-#define PMCRP   0x2
+-#define PMCRE   0x1
+-/*
+- * Mask of PMCR bits writeable by guest (not including WO bits like C, P,
+- * which can be written as 1 to trigger behaviour but which stay RAZ).
+- */
+-#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
+-
+-#define PMXEVTYPER_P          0x80000000
+-#define PMXEVTYPER_U          0x40000000
+-#define PMXEVTYPER_NSK        0x20000000
+-#define PMXEVTYPER_NSU        0x10000000
+-#define PMXEVTYPER_NSH        0x08000000
+-#define PMXEVTYPER_M          0x04000000
+-#define PMXEVTYPER_MT         0x02000000
+-#define PMXEVTYPER_EVTCOUNT   0x0000ffff
+-#define PMXEVTYPER_MASK       (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
+-                               PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
+-                               PMXEVTYPER_M | PMXEVTYPER_MT | \
+-                               PMXEVTYPER_EVTCOUNT)
+-
+-#define PMCCFILTR             0xf8000000
+-#define PMCCFILTR_M           PMXEVTYPER_M
+-#define PMCCFILTR_EL0         (PMCCFILTR | PMCCFILTR_M)
+-
+-static inline uint32_t pmu_num_counters(CPUARMState *env)
+-{
+-  return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
+-}
+-
+-/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
+-static inline uint64_t pmu_counter_mask(CPUARMState *env)
+-{
+-  return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
+-}
+-
+ typedef struct pm_event {
+     uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */
+     /* If the event is supported on this CPU (used to generate PMCEID[01]) */
+--
+.20.1

-[Qemu-devel] [PULL 02/10] hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs
+[PULL 08/27] hvf: Add execute to dirty log permission bitmap
-From: Philippe Mathieu-Daudé <philmd@redhat.com>
+From: Alexander Graf <agraf@csgraf.de>
-In the next commit we will implement the write_with_attrs()
+Hvf's permission bitmap during and after dirty logging does not include
-handler. To avoid using different APIs, convert the read()
+the HV_MEMORY_EXEC permission. At least on Apple Silicon, this leads to
-handler first.
+instruction faults once dirty logging was enabled.
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Add the bit to make it work properly.
-Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
-Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Signed-off-by: Alexander Graf <agraf@csgraf.de>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20210916155404.86958-3-agraf@csgraf.de
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/ssi/xilinx_spips.c | 23 +++++++++++------------
+ accel/hvf/hvf-accel-ops.c | 4 ++--
-file changed, 11 insertions(+), 12 deletions(-)
+file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
+diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/ssi/xilinx_spips.c
+--- a/accel/hvf/hvf-accel-ops.c
-+++ b/hw/ssi/xilinx_spips.c
++++ b/accel/hvf/hvf-accel-ops.c
-@@ -XXX,XX +XXX,XX @@ static void lqspi_load_cache(void *opaque, hwaddr addr)
+@@ -XXX,XX +XXX,XX @@ static void hvf_set_dirty_tracking(MemoryRegionSection *section, bool on)
      if (on) {
          slot->flags |= HVF_SLOT_LOG;
          hv_vm_protect((uintptr_t)slot->start, (size_t)slot->size,
 -                      HV_MEMORY_READ);
 +                      HV_MEMORY_READ | HV_MEMORY_EXEC);
      /* stop tracking region*/
      } else {
          slot->flags &= ~HVF_SLOT_LOG;
          hv_vm_protect((uintptr_t)slot->start, (size_t)slot->size,
 -                      HV_MEMORY_READ | HV_MEMORY_WRITE);
 +                      HV_MEMORY_READ | HV_MEMORY_WRITE | HV_MEMORY_EXEC);
      }
  }
--static uint64_t
--lqspi_read(void *opaque, hwaddr addr, unsigned int size)
-+static MemTxResult lqspi_read(void *opaque, hwaddr addr, uint64_t *value,
-+                              unsigned size, MemTxAttrs attrs)
- {
--    XilinxQSPIPS *q = opaque;
--    uint32_t ret;
-+    XilinxQSPIPS *q = XILINX_QSPIPS(opaque);
-     if (addr >= q->lqspi_cached_addr &&
-             addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
-         uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr];
--        ret = cpu_to_le32(*(uint32_t *)retp);
--        DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr,
--                   (unsigned)ret);
--        return ret;
--    } else {
--        lqspi_load_cache(opaque, addr);
--        return lqspi_read(opaque, addr, size);
-+        *value = cpu_to_le32(*(uint32_t *)retp);
-+        DB_PRINT_L(1, "addr: %08" HWADDR_PRIx ", data: %08" PRIx64 "\n",
-+                   addr, *value);
-+        return MEMTX_OK;
-     }
-+
-+    lqspi_load_cache(opaque, addr);
-+    return lqspi_read(opaque, addr, value, size, attrs);
- }
- static const MemoryRegionOps lqspi_ops = {
--    .read = lqspi_read,
-+    .read_with_attrs = lqspi_read,
-     .endianness = DEVICE_NATIVE_ENDIAN,
-     .valid = {
-         .min_access_size = 1,
 --
 .20.1

-New patch
+[PULL 09/27] hvf: Introduce hvf_arch_init() callback
+From: Alexander Graf <agraf@csgraf.de>
+We will need to install a migration helper for the ARM hvf backend.
+Let's introduce an arch callback for the overall hvf init chain to
+do so.
+Signed-off-by: Alexander Graf <agraf@csgraf.de>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20210916155404.86958-4-agraf@csgraf.de
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/sysemu/hvf_int.h  | 1 +
+ accel/hvf/hvf-accel-ops.c | 3 ++-
+ target/i386/hvf/hvf.c     | 5 +++++
+files changed, 8 insertions(+), 1 deletion(-)
+diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/sysemu/hvf_int.h
++++ b/include/sysemu/hvf_int.h
+@@ -XXX,XX +XXX,XX @@ struct hvf_vcpu_state {
+ };
+ void assert_hvf_ok(hv_return_t ret);
++int hvf_arch_init(void);
+ int hvf_arch_init_vcpu(CPUState *cpu);
+ void hvf_arch_vcpu_destroy(CPUState *cpu);
+ int hvf_vcpu_exec(CPUState *);
+diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c
+index XXXXXXX..XXXXXXX 100644
+--- a/accel/hvf/hvf-accel-ops.c
++++ b/accel/hvf/hvf-accel-ops.c
+@@ -XXX,XX +XXX,XX @@ static int hvf_accel_init(MachineState *ms)
+     hvf_state = s;
+     memory_listener_register(&hvf_memory_listener, &address_space_memory);
+-    return 0;
++
++    return hvf_arch_init();
+ }
+ static void hvf_accel_class_init(ObjectClass *oc, void *data)
+diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/i386/hvf/hvf.c
++++ b/target/i386/hvf/hvf.c
+@@ -XXX,XX +XXX,XX @@ static inline bool apic_bus_freq_is_known(CPUX86State *env)
+     return env->apic_bus_freq != 0;
+ }
++int hvf_arch_init(void)
++{
++    return 0;
++}
++
+ int hvf_arch_init_vcpu(CPUState *cpu)
+ {
+     X86CPU *x86cpu = X86_CPU(cpu);
+--
+.20.1

-[Qemu-devel] [PULL 08/10] pl031: Correctly migrate state when using -rtc clock=host
+[PULL 10/27] hvf: Add Apple Silicon support
-The PL031 RTC tracks the difference between the guest RTC
+From: Alexander Graf <agraf@csgraf.de>
 and the host RTC using a tick_offset field. For migration,
 however, we currently always migrate the offset between
 the guest and the vm_clock, even if the RTC clock is not
 the same as the vm_clock; this was an attempt to retain
 migration backwards compatibility.
-Unfortunately this results in the RTC behaving oddly across
+With Apple Silicon available to the masses, it's a good time to add support
-a VM state save and restore -- since the VM clock stands still
+for driving its virtualization extensions from QEMU.
 across save-then-restore, regardless of how much real world
 time has elapsed, the guest RTC ends up out of sync with the
 host RTC in the restored VM.
-Fix this by migrating the raw tick_offset. To retain migration
+This patch adds all necessary architecture specific code to get basic VMs
-compatibility as far as possible, we have a new property
+working, including save/restore.
 migrate-tick-offset; by default this is 'true' and we will
 migrate the true tick offset in a new subsection; if the
 incoming data has no subsection we fall back to the old
 vm_clock-based offset information, so old->new migration
 compatibility is preserved. For complete new->old migration
 compatibility, the property is set to 'false' for 4.0 and
 earlier machine types (this will only affect 'virt-4.0'
 and below, as none of the other pl031-using machines are
 versioned).
-Reported-by: Russell King <rmk@armlinux.org.uk>
+Known limitations:
   - WFI handling is missing (follows in later patch)
   - No watchpoint/breakpoint support
 Signed-off-by: Alexander Graf <agraf@csgraf.de>
 Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
 Reviewed-by: Sergio Lopez <slp@redhat.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20210916155404.86958-5-agraf@csgraf.de
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
-Message-id: 20190709143912.28905-1-peter.maydell@linaro.org
 ---
- include/hw/timer/pl031.h |  2 +
+ meson.build                 |   1 +
- hw/core/machine.c        |  1 +
+ include/sysemu/hvf_int.h    |  10 +-
- hw/timer/pl031.c         | 92 ++++++++++++++++++++++++++++++++++++++--
+ accel/hvf/hvf-accel-ops.c   |   9 +
-files changed, 91 insertions(+), 4 deletions(-)
+ target/arm/hvf/hvf.c        | 794 ++++++++++++++++++++++++++++++++++++
  target/i386/hvf/hvf.c       |   5 +
  MAINTAINERS                 |   5 +
  target/arm/hvf/trace-events |  10 +
 files changed, 833 insertions(+), 1 deletion(-)
  create mode 100644 target/arm/hvf/hvf.c
  create mode 100644 target/arm/hvf/trace-events
-diff --git a/include/hw/timer/pl031.h b/include/hw/timer/pl031.h
+diff --git a/meson.build b/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/timer/pl031.h
+--- a/meson.build
-+++ b/include/hw/timer/pl031.h
++++ b/meson.build
-@@ -XXX,XX +XXX,XX @@ typedef struct PL031State {
+@@ -XXX,XX +XXX,XX @@ if have_system or have_user
-      */
+     'accel/tcg',
-     uint32_t tick_offset_vmstate;
+     'hw/core',
-     uint32_t tick_offset;
+     'target/arm',
-+    bool tick_offset_migrated;
++    'target/arm/hvf',
-+    bool migrate_tick_offset;
+     'target/hppa',
+     'target/i386',
-     uint32_t mr;
+     'target/i386/kvm',
-     uint32_t lr;
+diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h
 diff --git a/hw/core/machine.c b/hw/core/machine.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/core/machine.c
+--- a/include/sysemu/hvf_int.h
-+++ b/hw/core/machine.c
++++ b/include/sysemu/hvf_int.h
-@@ -XXX,XX +XXX,XX @@ GlobalProperty hw_compat_4_0[] = {
+@@ -XXX,XX +XXX,XX @@
-     { "virtio-gpu-pci", "edid", "false" },
+ #ifndef HVF_INT_H
-     { "virtio-device", "use-started", "false" },
+ #define HVF_INT_H
-     { "virtio-balloon-device", "qemu-4-0-config-size", "true" },
-+    { "pl031", "migrate-tick-offset", "false" },
++#ifdef __aarch64__
 +#include <Hypervisor/Hypervisor.h>
 +#else
  #include <Hypervisor/hv.h>
 +#endif
  /* hvf_slot flags */
  #define HVF_SLOT_LOG (1 << 0)
@@ -XXX,XX +XXX,XX @@ struct HVFState {
      int num_slots;
      hvf_vcpu_caps *hvf_caps;
 +    uint64_t vtimer_offset;
  };
- const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0);
+ extern HVFState *hvf_state;
-diff --git a/hw/timer/pl031.c b/hw/timer/pl031.c
+ struct hvf_vcpu_state {
 -    int fd;
 +    uint64_t fd;
 +    void *exit;
 +    bool vtimer_masked;
  };
  void assert_hvf_ok(hv_return_t ret);
@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *);
  hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t);
  int hvf_put_registers(CPUState *);
  int hvf_get_registers(CPUState *);
 +void hvf_kick_vcpu_thread(CPUState *cpu);
  #endif
 diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/pl031.c
+--- a/accel/hvf/hvf-accel-ops.c
-+++ b/hw/timer/pl031.c
++++ b/accel/hvf/hvf-accel-ops.c
-@@ -XXX,XX +XXX,XX @@ static int pl031_pre_save(void *opaque)
+@@ -XXX,XX +XXX,XX @@
- {
-     PL031State *s = opaque;
+ HVFState *hvf_state;
--    /* tick_offset is base_time - rtc_clock base time.  Instead, we want to
++#ifdef __aarch64__
--     * store the base time relative to the QEMU_CLOCK_VIRTUAL for backwards-compatibility.  */
++#define HV_VM_DEFAULT NULL
 +#endif
 +
  /* Memory slots */
  hvf_slot *hvf_find_overlap_slot(uint64_t start, uint64_t size)
@@ -XXX,XX +XXX,XX @@ static int hvf_init_vcpu(CPUState *cpu)
      pthread_sigmask(SIG_BLOCK, NULL, &set);
      sigdelset(&set, SIG_IPI);
 +#ifdef __aarch64__
 +    r = hv_vcpu_create(&cpu->hvf->fd, (hv_vcpu_exit_t **)&cpu->hvf->exit, NULL);
 +#else
      r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf->fd, HV_VCPU_DEFAULT);
 +#endif
      cpu->vcpu_dirty = 1;
      assert_hvf_ok(r);
@@ -XXX,XX +XXX,XX @@ static void hvf_accel_ops_class_init(ObjectClass *oc, void *data)
      AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
      ops->create_vcpu_thread = hvf_start_vcpu_thread;
 +    ops->kick_vcpu_thread = hvf_kick_vcpu_thread;
      ops->synchronize_post_reset = hvf_cpu_synchronize_post_reset;
      ops->synchronize_post_init = hvf_cpu_synchronize_post_init;
 diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/arm/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QEMU Hypervisor.framework support for Apple Silicon
 +
 + * Copyright 2020 Alexander Graf <agraf@csgraf.de>
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
 + *
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu-common.h"
 +#include "qemu/error-report.h"
 +
 +#include "sysemu/runstate.h"
 +#include "sysemu/hvf.h"
 +#include "sysemu/hvf_int.h"
 +#include "sysemu/hw_accel.h"
 +
 +#include <mach/mach_time.h>
 +
 +#include "exec/address-spaces.h"
 +#include "hw/irq.h"
 +#include "qemu/main-loop.h"
 +#include "sysemu/cpus.h"
 +#include "target/arm/cpu.h"
 +#include "target/arm/internals.h"
 +#include "trace/trace-target_arm_hvf.h"
 +#include "migration/vmstate.h"
 +
 +#define HVF_SYSREG(crn, crm, op0, op1, op2) \
 +        ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
 +#define PL1_WRITE_MASK 0x4
 +
 +#define SYSREG(op0, op1, crn, crm, op2) \
 +    ((op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (crm << 1))
 +#define SYSREG_MASK           SYSREG(0x3, 0x7, 0xf, 0xf, 0x7)
 +#define SYSREG_OSLAR_EL1      SYSREG(2, 0, 1, 0, 4)
 +#define SYSREG_OSLSR_EL1      SYSREG(2, 0, 1, 1, 4)
 +#define SYSREG_OSDLR_EL1      SYSREG(2, 0, 1, 3, 4)
 +#define SYSREG_CNTPCT_EL0     SYSREG(3, 3, 14, 0, 1)
 +
 +#define WFX_IS_WFE (1 << 0)
 +
 +#define TMR_CTL_ENABLE  (1 << 0)
 +#define TMR_CTL_IMASK   (1 << 1)
 +#define TMR_CTL_ISTATUS (1 << 2)
 +
 +typedef struct HVFVTimer {
 +    /* Vtimer value during migration and paused state */
 +    uint64_t vtimer_val;
 +} HVFVTimer;
 +
 +static HVFVTimer vtimer;
 +
 +struct hvf_reg_match {
 +    int reg;
 +    uint64_t offset;
 +};
 +
 +static const struct hvf_reg_match hvf_reg_match[] = {
 +    { HV_REG_X0,   offsetof(CPUARMState, xregs[0]) },
 +    { HV_REG_X1,   offsetof(CPUARMState, xregs[1]) },
 +    { HV_REG_X2,   offsetof(CPUARMState, xregs[2]) },
 +    { HV_REG_X3,   offsetof(CPUARMState, xregs[3]) },
 +    { HV_REG_X4,   offsetof(CPUARMState, xregs[4]) },
 +    { HV_REG_X5,   offsetof(CPUARMState, xregs[5]) },
 +    { HV_REG_X6,   offsetof(CPUARMState, xregs[6]) },
 +    { HV_REG_X7,   offsetof(CPUARMState, xregs[7]) },
 +    { HV_REG_X8,   offsetof(CPUARMState, xregs[8]) },
 +    { HV_REG_X9,   offsetof(CPUARMState, xregs[9]) },
 +    { HV_REG_X10,  offsetof(CPUARMState, xregs[10]) },
 +    { HV_REG_X11,  offsetof(CPUARMState, xregs[11]) },
 +    { HV_REG_X12,  offsetof(CPUARMState, xregs[12]) },
 +    { HV_REG_X13,  offsetof(CPUARMState, xregs[13]) },
 +    { HV_REG_X14,  offsetof(CPUARMState, xregs[14]) },
 +    { HV_REG_X15,  offsetof(CPUARMState, xregs[15]) },
 +    { HV_REG_X16,  offsetof(CPUARMState, xregs[16]) },
 +    { HV_REG_X17,  offsetof(CPUARMState, xregs[17]) },
 +    { HV_REG_X18,  offsetof(CPUARMState, xregs[18]) },
 +    { HV_REG_X19,  offsetof(CPUARMState, xregs[19]) },
 +    { HV_REG_X20,  offsetof(CPUARMState, xregs[20]) },
 +    { HV_REG_X21,  offsetof(CPUARMState, xregs[21]) },
 +    { HV_REG_X22,  offsetof(CPUARMState, xregs[22]) },
 +    { HV_REG_X23,  offsetof(CPUARMState, xregs[23]) },
 +    { HV_REG_X24,  offsetof(CPUARMState, xregs[24]) },
 +    { HV_REG_X25,  offsetof(CPUARMState, xregs[25]) },
 +    { HV_REG_X26,  offsetof(CPUARMState, xregs[26]) },
 +    { HV_REG_X27,  offsetof(CPUARMState, xregs[27]) },
 +    { HV_REG_X28,  offsetof(CPUARMState, xregs[28]) },
 +    { HV_REG_X29,  offsetof(CPUARMState, xregs[29]) },
 +    { HV_REG_X30,  offsetof(CPUARMState, xregs[30]) },
 +    { HV_REG_PC,   offsetof(CPUARMState, pc) },
 +};
 +
 +static const struct hvf_reg_match hvf_fpreg_match[] = {
 +    { HV_SIMD_FP_REG_Q0,  offsetof(CPUARMState, vfp.zregs[0]) },
 +    { HV_SIMD_FP_REG_Q1,  offsetof(CPUARMState, vfp.zregs[1]) },
 +    { HV_SIMD_FP_REG_Q2,  offsetof(CPUARMState, vfp.zregs[2]) },
 +    { HV_SIMD_FP_REG_Q3,  offsetof(CPUARMState, vfp.zregs[3]) },
 +    { HV_SIMD_FP_REG_Q4,  offsetof(CPUARMState, vfp.zregs[4]) },
 +    { HV_SIMD_FP_REG_Q5,  offsetof(CPUARMState, vfp.zregs[5]) },
 +    { HV_SIMD_FP_REG_Q6,  offsetof(CPUARMState, vfp.zregs[6]) },
 +    { HV_SIMD_FP_REG_Q7,  offsetof(CPUARMState, vfp.zregs[7]) },
 +    { HV_SIMD_FP_REG_Q8,  offsetof(CPUARMState, vfp.zregs[8]) },
 +    { HV_SIMD_FP_REG_Q9,  offsetof(CPUARMState, vfp.zregs[9]) },
 +    { HV_SIMD_FP_REG_Q10, offsetof(CPUARMState, vfp.zregs[10]) },
 +    { HV_SIMD_FP_REG_Q11, offsetof(CPUARMState, vfp.zregs[11]) },
 +    { HV_SIMD_FP_REG_Q12, offsetof(CPUARMState, vfp.zregs[12]) },
 +    { HV_SIMD_FP_REG_Q13, offsetof(CPUARMState, vfp.zregs[13]) },
 +    { HV_SIMD_FP_REG_Q14, offsetof(CPUARMState, vfp.zregs[14]) },
 +    { HV_SIMD_FP_REG_Q15, offsetof(CPUARMState, vfp.zregs[15]) },
 +    { HV_SIMD_FP_REG_Q16, offsetof(CPUARMState, vfp.zregs[16]) },
 +    { HV_SIMD_FP_REG_Q17, offsetof(CPUARMState, vfp.zregs[17]) },
 +    { HV_SIMD_FP_REG_Q18, offsetof(CPUARMState, vfp.zregs[18]) },
 +    { HV_SIMD_FP_REG_Q19, offsetof(CPUARMState, vfp.zregs[19]) },
 +    { HV_SIMD_FP_REG_Q20, offsetof(CPUARMState, vfp.zregs[20]) },
 +    { HV_SIMD_FP_REG_Q21, offsetof(CPUARMState, vfp.zregs[21]) },
 +    { HV_SIMD_FP_REG_Q22, offsetof(CPUARMState, vfp.zregs[22]) },
 +    { HV_SIMD_FP_REG_Q23, offsetof(CPUARMState, vfp.zregs[23]) },
 +    { HV_SIMD_FP_REG_Q24, offsetof(CPUARMState, vfp.zregs[24]) },
 +    { HV_SIMD_FP_REG_Q25, offsetof(CPUARMState, vfp.zregs[25]) },
 +    { HV_SIMD_FP_REG_Q26, offsetof(CPUARMState, vfp.zregs[26]) },
 +    { HV_SIMD_FP_REG_Q27, offsetof(CPUARMState, vfp.zregs[27]) },
 +    { HV_SIMD_FP_REG_Q28, offsetof(CPUARMState, vfp.zregs[28]) },
 +    { HV_SIMD_FP_REG_Q29, offsetof(CPUARMState, vfp.zregs[29]) },
 +    { HV_SIMD_FP_REG_Q30, offsetof(CPUARMState, vfp.zregs[30]) },
 +    { HV_SIMD_FP_REG_Q31, offsetof(CPUARMState, vfp.zregs[31]) },
 +};
 +
 +struct hvf_sreg_match {
 +    int reg;
 +    uint32_t key;
 +    uint32_t cp_idx;
 +};
 +
 +static struct hvf_sreg_match hvf_sreg_match[] = {
 +    { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 4) },
 +    { HV_SYS_REG_DBGBCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 5) },
 +    { HV_SYS_REG_DBGWVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 6) },
 +    { HV_SYS_REG_DBGWCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 7) },
 +
 +    { HV_SYS_REG_DBGBVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 4) },
 +    { HV_SYS_REG_DBGBCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 5) },
 +    { HV_SYS_REG_DBGWVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 6) },
 +    { HV_SYS_REG_DBGWCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 7) },
 +
 +    { HV_SYS_REG_DBGBVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 4) },
 +    { HV_SYS_REG_DBGBCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 5) },
 +    { HV_SYS_REG_DBGWVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 6) },
 +    { HV_SYS_REG_DBGWCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 7) },
 +
 +    { HV_SYS_REG_DBGBVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 4) },
 +    { HV_SYS_REG_DBGBCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 5) },
 +    { HV_SYS_REG_DBGWVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 6) },
 +    { HV_SYS_REG_DBGWCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 7) },
 +
 +    { HV_SYS_REG_DBGBVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 4) },
 +    { HV_SYS_REG_DBGBCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 5) },
 +    { HV_SYS_REG_DBGWVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 6) },
 +    { HV_SYS_REG_DBGWCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 7) },
 +
 +    { HV_SYS_REG_DBGBVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 4) },
 +    { HV_SYS_REG_DBGBCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 5) },
 +    { HV_SYS_REG_DBGWVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 6) },
 +    { HV_SYS_REG_DBGWCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 7) },
 +
 +    { HV_SYS_REG_DBGBVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 4) },
 +    { HV_SYS_REG_DBGBCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 5) },
 +    { HV_SYS_REG_DBGWVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 6) },
 +    { HV_SYS_REG_DBGWCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 7) },
 +
 +    { HV_SYS_REG_DBGBVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 4) },
 +    { HV_SYS_REG_DBGBCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 5) },
 +    { HV_SYS_REG_DBGWVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 6) },
 +    { HV_SYS_REG_DBGWCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 7) },
 +
 +    { HV_SYS_REG_DBGBVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 4) },
 +    { HV_SYS_REG_DBGBCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 5) },
 +    { HV_SYS_REG_DBGWVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 6) },
 +    { HV_SYS_REG_DBGWCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 7) },
 +
 +    { HV_SYS_REG_DBGBVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 4) },
 +    { HV_SYS_REG_DBGBCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 5) },
 +    { HV_SYS_REG_DBGWVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 6) },
 +    { HV_SYS_REG_DBGWCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 7) },
 +
 +    { HV_SYS_REG_DBGBVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 4) },
 +    { HV_SYS_REG_DBGBCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 5) },
 +    { HV_SYS_REG_DBGWVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 6) },
 +    { HV_SYS_REG_DBGWCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 7) },
 +
 +    { HV_SYS_REG_DBGBVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 4) },
 +    { HV_SYS_REG_DBGBCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 5) },
 +    { HV_SYS_REG_DBGWVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 6) },
 +    { HV_SYS_REG_DBGWCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 7) },
 +
 +    { HV_SYS_REG_DBGBVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 4) },
 +    { HV_SYS_REG_DBGBCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 5) },
 +    { HV_SYS_REG_DBGWVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 6) },
 +    { HV_SYS_REG_DBGWCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 7) },
 +
 +    { HV_SYS_REG_DBGBVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 4) },
 +    { HV_SYS_REG_DBGBCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 5) },
 +    { HV_SYS_REG_DBGWVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 6) },
 +    { HV_SYS_REG_DBGWCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 7) },
 +
 +    { HV_SYS_REG_DBGBVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 4) },
 +    { HV_SYS_REG_DBGBCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 5) },
 +    { HV_SYS_REG_DBGWVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 6) },
 +    { HV_SYS_REG_DBGWCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 7) },
 +
 +    { HV_SYS_REG_DBGBVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 4) },
 +    { HV_SYS_REG_DBGBCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 5) },
 +    { HV_SYS_REG_DBGWVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 6) },
 +    { HV_SYS_REG_DBGWCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 7) },
 +
 +#ifdef SYNC_NO_RAW_REGS
 +    /*
-+     * The PL031 device model code uses the tick_offset field, which is
++     * The registers below are manually synced on init because they are
-+     * the offset between what the guest RTC should read and what the
++     * marked as NO_RAW. We still list them to make number space sync easier.
 +     * QEMU rtc_clock reads:
 +     *  guest_rtc = rtc_clock + tick_offset
 +     * and so
 +     *  tick_offset = guest_rtc - rtc_clock
 +     *
 +     * We want to migrate this offset, which sounds straightforward.
 +     * Unfortunately older versions of QEMU migrated a conversion of this
 +     * offset into an offset from the vm_clock. (This was in turn an
 +     * attempt to be compatible with even older QEMU versions, but it
 +     * has incorrect behaviour if the rtc_clock is not the same as the
 +     * vm_clock.) So we put the actual tick_offset into a migration
 +     * subsection, and the backwards-compatible time-relative-to-vm_clock
 +     * in the main migration state.
 +     *
 +     * Calculate base time relative to QEMU_CLOCK_VIRTUAL:
 +     */
-     int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
++    { HV_SYS_REG_MDCCINT_EL1, HVF_SYSREG(0, 2, 2, 0, 0) },
-     s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND;
++    { HV_SYS_REG_MIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 0) },
++    { HV_SYS_REG_MPIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 5) },
-     return 0;
++    { HV_SYS_REG_ID_AA64PFR0_EL1, HVF_SYSREG(0, 4, 3, 0, 0) },
- }
++#endif
++    { HV_SYS_REG_ID_AA64PFR1_EL1, HVF_SYSREG(0, 4, 3, 0, 2) },
-+static int pl031_pre_load(void *opaque)
++    { HV_SYS_REG_ID_AA64DFR0_EL1, HVF_SYSREG(0, 5, 3, 0, 0) },
-+{
++    { HV_SYS_REG_ID_AA64DFR1_EL1, HVF_SYSREG(0, 5, 3, 0, 1) },
-+    PL031State *s = opaque;
++    { HV_SYS_REG_ID_AA64ISAR0_EL1, HVF_SYSREG(0, 6, 3, 0, 0) },
-+
++    { HV_SYS_REG_ID_AA64ISAR1_EL1, HVF_SYSREG(0, 6, 3, 0, 1) },
-+    s->tick_offset_migrated = false;
++#ifdef SYNC_NO_MMFR0
 +    /* We keep the hardware MMFR0 around. HW limits are there anyway */
 +    { HV_SYS_REG_ID_AA64MMFR0_EL1, HVF_SYSREG(0, 7, 3, 0, 0) },
 +#endif
 +    { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) },
 +    { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) },
 +
 +    { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) },
 +    { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) },
 +    { HV_SYS_REG_CPACR_EL1, HVF_SYSREG(1, 0, 3, 0, 2) },
 +    { HV_SYS_REG_TTBR0_EL1, HVF_SYSREG(2, 0, 3, 0, 0) },
 +    { HV_SYS_REG_TTBR1_EL1, HVF_SYSREG(2, 0, 3, 0, 1) },
 +    { HV_SYS_REG_TCR_EL1, HVF_SYSREG(2, 0, 3, 0, 2) },
 +
 +    { HV_SYS_REG_APIAKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 0) },
 +    { HV_SYS_REG_APIAKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 1) },
 +    { HV_SYS_REG_APIBKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 2) },
 +    { HV_SYS_REG_APIBKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 3) },
 +    { HV_SYS_REG_APDAKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 0) },
 +    { HV_SYS_REG_APDAKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 1) },
 +    { HV_SYS_REG_APDBKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 2) },
 +    { HV_SYS_REG_APDBKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 3) },
 +    { HV_SYS_REG_APGAKEYLO_EL1, HVF_SYSREG(2, 3, 3, 0, 0) },
 +    { HV_SYS_REG_APGAKEYHI_EL1, HVF_SYSREG(2, 3, 3, 0, 1) },
 +
 +    { HV_SYS_REG_SPSR_EL1, HVF_SYSREG(4, 0, 3, 0, 0) },
 +    { HV_SYS_REG_ELR_EL1, HVF_SYSREG(4, 0, 3, 0, 1) },
 +    { HV_SYS_REG_SP_EL0, HVF_SYSREG(4, 1, 3, 0, 0) },
 +    { HV_SYS_REG_AFSR0_EL1, HVF_SYSREG(5, 1, 3, 0, 0) },
 +    { HV_SYS_REG_AFSR1_EL1, HVF_SYSREG(5, 1, 3, 0, 1) },
 +    { HV_SYS_REG_ESR_EL1, HVF_SYSREG(5, 2, 3, 0, 0) },
 +    { HV_SYS_REG_FAR_EL1, HVF_SYSREG(6, 0, 3, 0, 0) },
 +    { HV_SYS_REG_PAR_EL1, HVF_SYSREG(7, 4, 3, 0, 0) },
 +    { HV_SYS_REG_MAIR_EL1, HVF_SYSREG(10, 2, 3, 0, 0) },
 +    { HV_SYS_REG_AMAIR_EL1, HVF_SYSREG(10, 3, 3, 0, 0) },
 +    { HV_SYS_REG_VBAR_EL1, HVF_SYSREG(12, 0, 3, 0, 0) },
 +    { HV_SYS_REG_CONTEXTIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 1) },
 +    { HV_SYS_REG_TPIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 4) },
 +    { HV_SYS_REG_CNTKCTL_EL1, HVF_SYSREG(14, 1, 3, 0, 0) },
 +    { HV_SYS_REG_CSSELR_EL1, HVF_SYSREG(0, 0, 3, 2, 0) },
 +    { HV_SYS_REG_TPIDR_EL0, HVF_SYSREG(13, 0, 3, 3, 2) },
 +    { HV_SYS_REG_TPIDRRO_EL0, HVF_SYSREG(13, 0, 3, 3, 3) },
 +    { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) },
 +    { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) },
 +    { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) },
 +};
 +
 +int hvf_get_registers(CPUState *cpu)
 +{
 +    ARMCPU *arm_cpu = ARM_CPU(cpu);
 +    CPUARMState *env = &arm_cpu->env;
 +    hv_return_t ret;
 +    uint64_t val;
 +    hv_simd_fp_uchar16_t fpval;
 +    int i;
 +
 +    for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) {
 +        ret = hv_vcpu_get_reg(cpu->hvf->fd, hvf_reg_match[i].reg, &val);
 +        *(uint64_t *)((void *)env + hvf_reg_match[i].offset) = val;
 +        assert_hvf_ok(ret);
 +    }
 +
 +    for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) {
 +        ret = hv_vcpu_get_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].reg,
 +                                      &fpval);
 +        memcpy((void *)env + hvf_fpreg_match[i].offset, &fpval, sizeof(fpval));
 +        assert_hvf_ok(ret);
 +    }
 +
 +    val = 0;
 +    ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPCR, &val);
 +    assert_hvf_ok(ret);
 +    vfp_set_fpcr(env, val);
 +
 +    val = 0;
 +    ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPSR, &val);
 +    assert_hvf_ok(ret);
 +    vfp_set_fpsr(env, val);
 +
 +    ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_CPSR, &val);
 +    assert_hvf_ok(ret);
 +    pstate_write(env, val);
 +
 +    for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) {
 +        if (hvf_sreg_match[i].cp_idx == -1) {
 +            continue;
 +        }
 +
 +        ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, &val);
 +        assert_hvf_ok(ret);
 +
 +        arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val;
 +    }
 +    assert(write_list_to_cpustate(arm_cpu));
 +
 +    aarch64_restore_sp(env, arm_current_el(env));
 +
 +    return 0;
 +}
 +
- static int pl031_post_load(void *opaque, int version_id)
++int hvf_put_registers(CPUState *cpu)
- {
++{
-     PL031State *s = opaque;
++    ARMCPU *arm_cpu = ARM_CPU(cpu);
++    CPUARMState *env = &arm_cpu->env;
--    int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
++    hv_return_t ret;
--    s->tick_offset = s->tick_offset_vmstate - delta / NANOSECONDS_PER_SECOND;
++    uint64_t val;
 +    hv_simd_fp_uchar16_t fpval;
 +    int i;
 +
 +    for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) {
 +        val = *(uint64_t *)((void *)env + hvf_reg_match[i].offset);
 +        ret = hv_vcpu_set_reg(cpu->hvf->fd, hvf_reg_match[i].reg, val);
 +        assert_hvf_ok(ret);
 +    }
 +
 +    for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) {
 +        memcpy(&fpval, (void *)env + hvf_fpreg_match[i].offset, sizeof(fpval));
 +        ret = hv_vcpu_set_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].reg,
 +                                      fpval);
 +        assert_hvf_ok(ret);
 +    }
 +
 +    ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPCR, vfp_get_fpcr(env));
 +    assert_hvf_ok(ret);
 +
 +    ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPSR, vfp_get_fpsr(env));
 +    assert_hvf_ok(ret);
 +
 +    ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_CPSR, pstate_read(env));
 +    assert_hvf_ok(ret);
 +
 +    aarch64_save_sp(env, arm_current_el(env));
 +
 +    assert(write_cpustate_to_list(arm_cpu, false));
 +    for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) {
 +        if (hvf_sreg_match[i].cp_idx == -1) {
 +            continue;
 +        }
 +
 +        val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx];
 +        ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, val);
 +        assert_hvf_ok(ret);
 +    }
 +
 +    ret = hv_vcpu_set_vtimer_offset(cpu->hvf->fd, hvf_state->vtimer_offset);
 +    assert_hvf_ok(ret);
 +
 +    return 0;
 +}
 +
 +static void flush_cpu_state(CPUState *cpu)
 +{
 +    if (cpu->vcpu_dirty) {
 +        hvf_put_registers(cpu);
 +        cpu->vcpu_dirty = false;
 +    }
 +}
 +
 +static void hvf_set_reg(CPUState *cpu, int rt, uint64_t val)
 +{
 +    hv_return_t r;
 +
 +    flush_cpu_state(cpu);
 +
 +    if (rt < 31) {
 +        r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_X0 + rt, val);
 +        assert_hvf_ok(r);
 +    }
 +}
 +
 +static uint64_t hvf_get_reg(CPUState *cpu, int rt)
 +{
 +    uint64_t val = 0;
 +    hv_return_t r;
 +
 +    flush_cpu_state(cpu);
 +
 +    if (rt < 31) {
 +        r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_X0 + rt, &val);
 +        assert_hvf_ok(r);
 +    }
 +
 +    return val;
 +}
 +
 +void hvf_arch_vcpu_destroy(CPUState *cpu)
 +{
 +}
 +
 +int hvf_arch_init_vcpu(CPUState *cpu)
 +{
 +    ARMCPU *arm_cpu = ARM_CPU(cpu);
 +    CPUARMState *env = &arm_cpu->env;
 +    uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_match);
 +    uint32_t sregs_cnt = 0;
 +    uint64_t pfr;
 +    hv_return_t ret;
 +    int i;
 +
 +    env->aarch64 = 1;
 +    asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz));
 +
 +    /* Allocate enough space for our sysreg sync */
 +    arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes,
 +                                     sregs_match_len);
 +    arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values,
 +                                    sregs_match_len);
 +    arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t,
 +                                             arm_cpu->cpreg_vmstate_indexes,
 +                                             sregs_match_len);
 +    arm_cpu->cpreg_vmstate_values = g_renew(uint64_t,
 +                                            arm_cpu->cpreg_vmstate_values,
 +                                            sregs_match_len);
 +
 +    memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t));
 +
 +    /* Populate cp list for all known sysregs */
 +    for (i = 0; i < sregs_match_len; i++) {
 +        const ARMCPRegInfo *ri;
 +        uint32_t key = hvf_sreg_match[i].key;
 +
 +        ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);
 +        if (ri) {
 +            assert(!(ri->type & ARM_CP_NO_RAW));
 +            hvf_sreg_match[i].cp_idx = sregs_cnt;
 +            arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key);
 +        } else {
 +            hvf_sreg_match[i].cp_idx = -1;
 +        }
 +    }
 +    arm_cpu->cpreg_array_len = sregs_cnt;
 +    arm_cpu->cpreg_vmstate_array_len = sregs_cnt;
 +
 +    assert(write_cpustate_to_list(arm_cpu, false));
 +
 +    /* Set CP_NO_RAW system registers on init */
 +    ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MIDR_EL1,
 +                              arm_cpu->midr);
 +    assert_hvf_ok(ret);
 +
 +    ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MPIDR_EL1,
 +                              arm_cpu->mp_affinity);
 +    assert_hvf_ok(ret);
 +
 +    ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr);
 +    assert_hvf_ok(ret);
 +    pfr |= env->gicv3state ? (1 << 24) : 0;
 +    ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr);
 +    assert_hvf_ok(ret);
 +
 +    /* We're limited to underlying hardware caps, override internal versions */
 +    ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64MMFR0_EL1,
 +                              &arm_cpu->isar.id_aa64mmfr0);
 +    assert_hvf_ok(ret);
 +
 +    return 0;
 +}
 +
 +void hvf_kick_vcpu_thread(CPUState *cpu)
 +{
 +    hv_vcpus_exit(&cpu->hvf->fd, 1);
 +}
 +
 +static void hvf_raise_exception(CPUState *cpu, uint32_t excp,
 +                                uint32_t syndrome)
 +{
 +    ARMCPU *arm_cpu = ARM_CPU(cpu);
 +    CPUARMState *env = &arm_cpu->env;
 +
 +    cpu->exception_index = excp;
 +    env->exception.target_el = 1;
 +    env->exception.syndrome = syndrome;
 +
 +    arm_cpu_do_interrupt(cpu);
 +}
 +
 +static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
 +{
 +    ARMCPU *arm_cpu = ARM_CPU(cpu);
 +    CPUARMState *env = &arm_cpu->env;
 +    uint64_t val = 0;
 +
 +    switch (reg) {
 +    case SYSREG_CNTPCT_EL0:
 +        val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /
 +              gt_cntfrq_period_ns(arm_cpu);
 +        break;
 +    case SYSREG_OSLSR_EL1:
 +        val = env->cp15.oslsr_el1;
 +        break;
 +    case SYSREG_OSDLR_EL1:
 +        /* Dummy register */
 +        break;
 +    default:
 +        cpu_synchronize_state(cpu);
 +        trace_hvf_unhandled_sysreg_read(env->pc, reg,
 +                                        (reg >> 20) & 0x3,
 +                                        (reg >> 14) & 0x7,
 +                                        (reg >> 10) & 0xf,
 +                                        (reg >> 1) & 0xf,
 +                                        (reg >> 17) & 0x7);
 +        hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
 +        return 1;
 +    }
 +
 +    trace_hvf_sysreg_read(reg,
 +                          (reg >> 20) & 0x3,
 +                          (reg >> 14) & 0x7,
 +                          (reg >> 10) & 0xf,
 +                          (reg >> 1) & 0xf,
 +                          (reg >> 17) & 0x7,
 +                          val);
 +    hvf_set_reg(cpu, rt, val);
 +
 +    return 0;
 +}
 +
 +static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
 +{
 +    ARMCPU *arm_cpu = ARM_CPU(cpu);
 +    CPUARMState *env = &arm_cpu->env;
 +
 +    trace_hvf_sysreg_write(reg,
 +                           (reg >> 20) & 0x3,
 +                           (reg >> 14) & 0x7,
 +                           (reg >> 10) & 0xf,
 +                           (reg >> 1) & 0xf,
 +                           (reg >> 17) & 0x7,
 +                           val);
 +
 +    switch (reg) {
 +    case SYSREG_OSLAR_EL1:
 +        env->cp15.oslsr_el1 = val & 1;
 +        break;
 +    case SYSREG_OSDLR_EL1:
 +        /* Dummy register */
 +        break;
 +    default:
 +        cpu_synchronize_state(cpu);
 +        trace_hvf_unhandled_sysreg_write(env->pc, reg,
 +                                         (reg >> 20) & 0x3,
 +                                         (reg >> 14) & 0x7,
 +                                         (reg >> 10) & 0xf,
 +                                         (reg >> 1) & 0xf,
 +                                         (reg >> 17) & 0x7);
 +        hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
 +        return 1;
 +    }
 +
 +    return 0;
 +}
 +
 +static int hvf_inject_interrupts(CPUState *cpu)
 +{
 +    if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) {
 +        trace_hvf_inject_fiq();
 +        hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_FIQ,
 +                                      true);
 +    }
 +
 +    if (cpu->interrupt_request & CPU_INTERRUPT_HARD) {
 +        trace_hvf_inject_irq();
 +        hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_IRQ,
 +                                      true);
 +    }
 +
 +    return 0;
 +}
 +
 +static uint64_t hvf_vtimer_val_raw(void)
 +{
 +    /*
-+     * If we got the tick_offset subsection, then we can just use
++     * mach_absolute_time() returns the vtimer value without the VM
-+     * the value in that. Otherwise the source is an older QEMU and
++     * offset that we define. Add our own offset on top.
 +     * has given us the offset from the vm_clock; convert it back to
 +     * an offset from the rtc_clock. This will cause time to incorrectly
 +     * go backwards compared to the host RTC, but this is unavoidable.
 +     */
-+
++    return mach_absolute_time() - hvf_state->vtimer_offset;
-+    if (!s->tick_offset_migrated) {
++}
-+        int64_t delta = qemu_clock_get_ns(rtc_clock) -
++
-+            qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
++static void hvf_sync_vtimer(CPUState *cpu)
-+        s->tick_offset = s->tick_offset_vmstate -
++{
-+            delta / NANOSECONDS_PER_SECOND;
++    ARMCPU *arm_cpu = ARM_CPU(cpu);
-+    }
++    hv_return_t r;
-     pl031_set_alarm(s);
++    uint64_t ctl;
-     return 0;
++    bool irq_state;
- }
++
++    if (!cpu->hvf->vtimer_masked) {
-+static int pl031_tick_offset_post_load(void *opaque, int version_id)
++        /* We will get notified on vtimer changes by hvf, nothing to do */
-+{
++        return;
-+    PL031State *s = opaque;
++    }
 +
-+    s->tick_offset_migrated = true;
++    r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl);
 +    assert_hvf_ok(r);
 +
 +    irq_state = (ctl & (TMR_CTL_ENABLE | TMR_CTL_IMASK | TMR_CTL_ISTATUS)) ==
 +                (TMR_CTL_ENABLE | TMR_CTL_ISTATUS);
 +    qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], irq_state);
 +
 +    if (!irq_state) {
 +        /* Timer no longer asserting, we can unmask it */
 +        hv_vcpu_set_vtimer_mask(cpu->hvf->fd, false);
 +        cpu->hvf->vtimer_masked = false;
 +    }
 +}
 +
 +int hvf_vcpu_exec(CPUState *cpu)
 +{
 +    ARMCPU *arm_cpu = ARM_CPU(cpu);
 +    CPUARMState *env = &arm_cpu->env;
 +    hv_vcpu_exit_t *hvf_exit = cpu->hvf->exit;
 +    hv_return_t r;
 +    bool advance_pc = false;
 +
 +    if (hvf_inject_interrupts(cpu)) {
 +        return EXCP_INTERRUPT;
 +    }
 +
 +    if (cpu->halted) {
 +        return EXCP_HLT;
 +    }
 +
 +    flush_cpu_state(cpu);
 +
 +    qemu_mutex_unlock_iothread();
 +    assert_hvf_ok(hv_vcpu_run(cpu->hvf->fd));
 +
 +    /* handle VMEXIT */
 +    uint64_t exit_reason = hvf_exit->reason;
 +    uint64_t syndrome = hvf_exit->exception.syndrome;
 +    uint32_t ec = syn_get_ec(syndrome);
 +
 +    qemu_mutex_lock_iothread();
 +    switch (exit_reason) {
 +    case HV_EXIT_REASON_EXCEPTION:
 +        /* This is the main one, handle below. */
 +        break;
 +    case HV_EXIT_REASON_VTIMER_ACTIVATED:
 +        qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1);
 +        cpu->hvf->vtimer_masked = true;
 +        return 0;
 +    case HV_EXIT_REASON_CANCELED:
 +        /* we got kicked, no exit to process */
 +        return 0;
 +    default:
 +        assert(0);
 +    }
 +
 +    hvf_sync_vtimer(cpu);
 +
 +    switch (ec) {
 +    case EC_DATAABORT: {
 +        bool isv = syndrome & ARM_EL_ISV;
 +        bool iswrite = (syndrome >> 6) & 1;
 +        bool s1ptw = (syndrome >> 7) & 1;
 +        uint32_t sas = (syndrome >> 22) & 3;
 +        uint32_t len = 1 << sas;
 +        uint32_t srt = (syndrome >> 16) & 0x1f;
 +        uint64_t val = 0;
 +
 +        trace_hvf_data_abort(env->pc, hvf_exit->exception.virtual_address,
 +                             hvf_exit->exception.physical_address, isv,
 +                             iswrite, s1ptw, len, srt);
 +
 +        assert(isv);
 +
 +        if (iswrite) {
 +            val = hvf_get_reg(cpu, srt);
 +            address_space_write(&address_space_memory,
 +                                hvf_exit->exception.physical_address,
 +                                MEMTXATTRS_UNSPECIFIED, &val, len);
 +        } else {
 +            address_space_read(&address_space_memory,
 +                               hvf_exit->exception.physical_address,
 +                               MEMTXATTRS_UNSPECIFIED, &val, len);
 +            hvf_set_reg(cpu, srt, val);
 +        }
 +
 +        advance_pc = true;
 +        break;
 +    }
 +    case EC_SYSTEMREGISTERTRAP: {
 +        bool isread = (syndrome >> 0) & 1;
 +        uint32_t rt = (syndrome >> 5) & 0x1f;
 +        uint32_t reg = syndrome & SYSREG_MASK;
 +        uint64_t val;
 +        int ret = 0;
 +
 +        if (isread) {
 +            ret = hvf_sysreg_read(cpu, reg, rt);
 +        } else {
 +            val = hvf_get_reg(cpu, rt);
 +            ret = hvf_sysreg_write(cpu, reg, val);
 +        }
 +
 +        advance_pc = !ret;
 +        break;
 +    }
 +    case EC_WFX_TRAP:
 +        advance_pc = true;
 +        break;
 +    case EC_AA64_HVC:
 +        cpu_synchronize_state(cpu);
 +        trace_hvf_unknown_hvc(env->xregs[0]);
 +        /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */
 +        env->xregs[0] = -1;
 +        break;
 +    case EC_AA64_SMC:
 +        cpu_synchronize_state(cpu);
 +        trace_hvf_unknown_smc(env->xregs[0]);
 +        hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
 +        break;
 +    default:
 +        cpu_synchronize_state(cpu);
 +        trace_hvf_exit(syndrome, ec, env->pc);
 +        error_report("0x%llx: unhandled exception ec=0x%x", env->pc, ec);
 +    }
 +
 +    if (advance_pc) {
 +        uint64_t pc;
 +
 +        flush_cpu_state(cpu);
 +
 +        r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_PC, &pc);
 +        assert_hvf_ok(r);
 +        pc += 4;
 +        r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_PC, pc);
 +        assert_hvf_ok(r);
 +    }
 +
 +    return 0;
 +}
 +
-+static bool pl031_tick_offset_needed(void *opaque)
++static const VMStateDescription vmstate_hvf_vtimer = {
-+{
++    .name = "hvf-vtimer",
 +    PL031State *s = opaque;
 +
 +    return s->migrate_tick_offset;
 +}
 +
 +static const VMStateDescription vmstate_pl031_tick_offset = {
 +    .name = "pl031/tick-offset",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
-+    .needed = pl031_tick_offset_needed,
-+    .post_load = pl031_tick_offset_post_load,
 +    .fields = (VMStateField[]) {
-+        VMSTATE_UINT32(tick_offset, PL031State),
++        VMSTATE_UINT64(vtimer_val, HVFVTimer),
 +        VMSTATE_END_OF_LIST()
-+    }
++    },
 +};
 +
- static const VMStateDescription vmstate_pl031 = {
++static void hvf_vm_state_change(void *opaque, bool running, RunState state)
-     .name = "pl031",
++{
-     .version_id = 1,
++    HVFVTimer *s = opaque;
-     .minimum_version_id = 1,
++
-     .pre_save = pl031_pre_save,
++    if (running) {
-+    .pre_load = pl031_pre_load,
++        /* Update vtimer offset on all CPUs */
-     .post_load = pl031_post_load,
++        hvf_state->vtimer_offset = mach_absolute_time() - s->vtimer_val;
-     .fields = (VMStateField[]) {
++        cpu_synchronize_all_states();
-         VMSTATE_UINT32(tick_offset_vmstate, PL031State),
++    } else {
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl031 = {
++        /* Remember vtimer value on every pause */
-         VMSTATE_UINT32(im, PL031State),
++        s->vtimer_val = hvf_vtimer_val_raw();
-         VMSTATE_UINT32(is, PL031State),
++    }
-         VMSTATE_END_OF_LIST()
++}
-+    },
++
-+    .subsections = (const VMStateDescription*[]) {
++int hvf_arch_init(void)
-+        &vmstate_pl031_tick_offset,
++{
-+        NULL
++    hvf_state->vtimer_offset = mach_absolute_time();
-     }
++    vmstate_register(NULL, 0, &vmstate_hvf_vtimer, &vtimer);
- };
++    qemu_add_vm_change_state_handler(hvf_vm_state_change, &vtimer);
++    return 0;
-+static Property pl031_properties[] = {
++}
-+    /*
+diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
-+     * True to correctly migrate the tick offset of the RTC. False to
+index XXXXXXX..XXXXXXX 100644
-+     * obtain backward migration compatibility with older QEMU versions,
+--- a/target/i386/hvf/hvf.c
-+     * at the expense of the guest RTC going backwards compared with the
++++ b/target/i386/hvf/hvf.c
-+     * host RTC when the VM is saved/restored if using -rtc host.
+@@ -XXX,XX +XXX,XX @@ static inline bool apic_bus_freq_is_known(CPUX86State *env)
-+     * (Even if set to 'true' older QEMU can migrate forward to newer QEMU;
+     return env->apic_bus_freq != 0;
-+     * 'false' also permits newer QEMU to migrate to older QEMU.)
+ }
-+     */
-+    DEFINE_PROP_BOOL("migrate-tick-offset",
++void hvf_kick_vcpu_thread(CPUState *cpu)
-+                     PL031State, migrate_tick_offset, true),
++{
-+    DEFINE_PROP_END_OF_LIST()
++    cpus_kick_thread(cpu);
-+};
++}
 +
- static void pl031_class_init(ObjectClass *klass, void *data)
+ int hvf_arch_init(void)
  {
-     DeviceClass *dc = DEVICE_CLASS(klass);
+     return 0;
+diff --git a/MAINTAINERS b/MAINTAINERS
-     dc->vmsd = &vmstate_pl031;
+index XXXXXXX..XXXXXXX 100644
-+    dc->props = pl031_properties;
+--- a/MAINTAINERS
- }
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ F: accel/accel-*.c
- static const TypeInfo pl031_info = {
+ F: accel/Makefile.objs
  F: accel/stubs/Makefile.objs
 +Apple Silicon HVF CPUs
 +M: Alexander Graf <agraf@csgraf.de>
 +S: Maintained
 +F: target/arm/hvf/
 +
  X86 HVF CPUs
  M: Cameron Esfahani <dirty@apple.com>
  M: Roman Bolshakov <r.bolshakov@yadro.com>
 diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/arm/hvf/trace-events
@@ -XXX,XX +XXX,XX @@
 +hvf_unhandled_sysreg_read(uint64_t pc, uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2) "unhandled sysreg read at pc=0x%"PRIx64": 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d)"
 +hvf_unhandled_sysreg_write(uint64_t pc, uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2) "unhandled sysreg write at pc=0x%"PRIx64": 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d)"
 +hvf_inject_fiq(void) "injecting FIQ"
 +hvf_inject_irq(void) "injecting IRQ"
 +hvf_data_abort(uint64_t pc, uint64_t va, uint64_t pa, bool isv, bool iswrite, bool s1ptw, uint32_t len, uint32_t srt) "data abort: [pc=0x%"PRIx64" va=0x%016"PRIx64" pa=0x%016"PRIx64" isv=%d iswrite=%d s1ptw=%d len=%d srt=%d]"
 +hvf_sysreg_read(uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg read 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d) = 0x%016"PRIx64
 +hvf_sysreg_write(uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg write 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d, val=0x%016"PRIx64")"
 +hvf_unknown_hvc(uint64_t x0) "unknown HVC! 0x%016"PRIx64
 +hvf_unknown_smc(uint64_t x0) "unknown SMC! 0x%016"PRIx64
 +hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [ec=0x%x pc=0x%"PRIx64"]"
 --
 .20.1

-[Qemu-devel] [PULL 03/10] hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
+[PULL 11/27] arm/hvf: Add a WFI handler
-From: Philippe Mathieu-Daudé <philmd@redhat.com>
+From: Peter Collingbourne <pcc@google.com>
-Lei Sun found while auditing the code that a CPU write would
+Sleep on WFI until the VTIMER is due but allow ourselves to be woken
-trigger a NULL pointer dereference.
+up on IPI.
->From UG1085 datasheet [*] AXI writes in this region are ignored
+In this implementation IPI is blocked on the CPU thread at startup and
-and generates an AXI Slave Error (SLVERR).
+pselect() is used to atomically unblock the signal and begin sleeping.
 The signal is sent unconditionally so there's no need to worry about
 races between actually sleeping and the "we think we're sleeping"
 state. It may lead to an extra wakeup but that's better than missing
 it entirely.
-Fix by implementing the write_with_attrs() handler.
+Signed-off-by: Peter Collingbourne <pcc@google.com>
-Return MEMTX_ERROR when the region is accessed (this error maps
+Signed-off-by: Alexander Graf <agraf@csgraf.de>
-to an AXI slave error).
+Acked-by: Roman Bolshakov <r.bolshakov@yadro.com>
+Reviewed-by: Sergio Lopez <slp@redhat.com>
-[*] https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
+Message-id: 20210916155404.86958-6-agraf@csgraf.de
+[agraf: Remove unused 'set' variable, always advance PC on WFX trap,
-Reported-by: Lei Sun <slei.casper@gmail.com>
+        support vm stop / continue operations and cntv offsets]
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Signed-off-by: Alexander Graf <agraf@csgraf.de>
-Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Acked-by: Roman Bolshakov <r.bolshakov@yadro.com>
-Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Sergio Lopez <slp@redhat.com>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/ssi/xilinx_spips.c | 16 ++++++++++++++++
+ include/sysemu/hvf_int.h  |  1 +
-file changed, 16 insertions(+)
+ accel/hvf/hvf-accel-ops.c |  5 +--
  target/arm/hvf/hvf.c      | 79 +++++++++++++++++++++++++++++++++++++++
 files changed, 82 insertions(+), 3 deletions(-)
-diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
+diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/ssi/xilinx_spips.c
+--- a/include/sysemu/hvf_int.h
-+++ b/hw/ssi/xilinx_spips.c
++++ b/include/sysemu/hvf_int.h
-@@ -XXX,XX +XXX,XX @@ static MemTxResult lqspi_read(void *opaque, hwaddr addr, uint64_t *value,
+@@ -XXX,XX +XXX,XX @@ struct hvf_vcpu_state {
-     return lqspi_read(opaque, addr, value, size, attrs);
+     uint64_t fd;
      void *exit;
      bool vtimer_masked;
 +    sigset_t unblock_ipi_mask;
  };
  void assert_hvf_ok(hv_return_t ret);
 diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c
 index XXXXXXX..XXXXXXX 100644
 --- a/accel/hvf/hvf-accel-ops.c
 +++ b/accel/hvf/hvf-accel-ops.c
@@ -XXX,XX +XXX,XX @@ static int hvf_init_vcpu(CPUState *cpu)
      cpu->hvf = g_malloc0(sizeof(*cpu->hvf));
      /* init cpu signals */
 -    sigset_t set;
      struct sigaction sigact;
      memset(&sigact, 0, sizeof(sigact));
      sigact.sa_handler = dummy_signal;
      sigaction(SIG_IPI, &sigact, NULL);
 -    pthread_sigmask(SIG_BLOCK, NULL, &set);
 -    sigdelset(&set, SIG_IPI);
 +    pthread_sigmask(SIG_BLOCK, NULL, &cpu->hvf->unblock_ipi_mask);
 +    sigdelset(&cpu->hvf->unblock_ipi_mask, SIG_IPI);
  #ifdef __aarch64__
      r = hv_vcpu_create(&cpu->hvf->fd, (hv_vcpu_exit_t **)&cpu->hvf->exit, NULL);
 diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/hvf/hvf.c
 +++ b/target/arm/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@
   * QEMU Hypervisor.framework support for Apple Silicon
   * Copyright 2020 Alexander Graf <agraf@csgraf.de>
 + * Copyright 2020 Google LLC
   *
   * This work is licensed under the terms of the GNU GPL, version 2 or later.
   * See the COPYING file in the top-level directory.
@@ -XXX,XX +XXX,XX @@ int hvf_arch_init_vcpu(CPUState *cpu)
  void hvf_kick_vcpu_thread(CPUState *cpu)
  {
 +    cpus_kick_thread(cpu);
      hv_vcpus_exit(&cpu->hvf->fd, 1);
  }
-+static MemTxResult lqspi_write(void *opaque, hwaddr offset, uint64_t value,
+@@ -XXX,XX +XXX,XX @@ static uint64_t hvf_vtimer_val_raw(void)
-+                               unsigned size, MemTxAttrs attrs)
+     return mach_absolute_time() - hvf_state->vtimer_offset;
  }
 +static uint64_t hvf_vtimer_val(void)
 +{
 +    if (!runstate_is_running()) {
 +        /* VM is paused, the vtimer value is in vtimer.vtimer_val */
 +        return vtimer.vtimer_val;
 +    }
 +
 +    return hvf_vtimer_val_raw();
 +}
 +
 +static void hvf_wait_for_ipi(CPUState *cpu, struct timespec *ts)
 +{
 +    /*
-+     * From UG1085, Chapter 24 (Quad-SPI controllers):
++     * Use pselect to sleep so that other threads can IPI us while we're
-+     * - Writes are ignored
++     * sleeping.
 +     * - AXI writes generate an external AXI slave error (SLVERR)
 +     */
-+    qemu_log_mask(LOG_GUEST_ERROR, "%s Unexpected %u-bit access to 0x%" PRIx64
++    qatomic_mb_set(&cpu->thread_kicked, false);
-+                                   " (value: 0x%" PRIx64 "\n",
++    qemu_mutex_unlock_iothread();
-+                  __func__, size << 3, offset, value);
++    pselect(0, 0, 0, 0, ts, &cpu->hvf->unblock_ipi_mask);
-+
++    qemu_mutex_lock_iothread();
 +    return MEMTX_ERROR;
 +}
 +
- static const MemoryRegionOps lqspi_ops = {
++static void hvf_wfi(CPUState *cpu)
-     .read_with_attrs = lqspi_read,
++{
-+    .write_with_attrs = lqspi_write,
++    ARMCPU *arm_cpu = ARM_CPU(cpu);
-     .endianness = DEVICE_NATIVE_ENDIAN,
++    struct timespec ts;
-     .valid = {
++    hv_return_t r;
-         .min_access_size = 1,
++    uint64_t ctl;
 +    uint64_t cval;
 +    int64_t ticks_to_sleep;
 +    uint64_t seconds;
 +    uint64_t nanos;
 +    uint32_t cntfrq;
 +
 +    if (cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ)) {
 +        /* Interrupt pending, no need to wait */
 +        return;
 +    }
 +
 +    r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl);
 +    assert_hvf_ok(r);
 +
 +    if (!(ctl & 1) || (ctl & 2)) {
 +        /* Timer disabled or masked, just wait for an IPI. */
 +        hvf_wait_for_ipi(cpu, NULL);
 +        return;
 +    }
 +
 +    r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CVAL_EL0, &cval);
 +    assert_hvf_ok(r);
 +
 +    ticks_to_sleep = cval - hvf_vtimer_val();
 +    if (ticks_to_sleep < 0) {
 +        return;
 +    }
 +
 +    cntfrq = gt_cntfrq_period_ns(arm_cpu);
 +    seconds = muldiv64(ticks_to_sleep, cntfrq, NANOSECONDS_PER_SECOND);
 +    ticks_to_sleep -= muldiv64(seconds, NANOSECONDS_PER_SECOND, cntfrq);
 +    nanos = ticks_to_sleep * cntfrq;
 +
 +    /*
 +     * Don't sleep for less than the time a context switch would take,
 +     * so that we can satisfy fast timer requests on the same CPU.
 +     * Measurements on M1 show the sweet spot to be ~2ms.
 +     */
 +    if (!seconds && nanos < (2 * SCALE_MS)) {
 +        return;
 +    }
 +
 +    ts = (struct timespec) { seconds, nanos };
 +    hvf_wait_for_ipi(cpu, &ts);
 +}
 +
  static void hvf_sync_vtimer(CPUState *cpu)
  {
      ARMCPU *arm_cpu = ARM_CPU(cpu);
@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu)
      }
      case EC_WFX_TRAP:
          advance_pc = true;
 +        if (!(syndrome & WFX_IS_WFE)) {
 +            hvf_wfi(cpu);
 +        }
          break;
      case EC_AA64_HVC:
          cpu_synchronize_state(cpu);
 --
 .20.1

-New patch
+[PULL 12/27] hvf: arm: Implement -cpu host
+Now that we have working system register sync, we push more target CPU
 properties into the virtual machine. That might be useful in some
 situations, but is not the typical case that users want.
 So let's add a -cpu host option that allows them to explicitly pass all
 CPU capabilities of their host CPU into the guest.
 Signed-off-by: Alexander Graf <agraf@csgraf.de>
 Acked-by: Roman Bolshakov <r.bolshakov@yadro.com>
 Reviewed-by: Sergio Lopez <slp@redhat.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20210916155404.86958-7-agraf@csgraf.de
 [PMM: drop unnecessary #include line from .h file]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpu.h     |  2 +
  target/arm/hvf_arm.h | 18 +++++++++
  target/arm/kvm_arm.h |  2 -
  target/arm/cpu.c     | 13 ++++--
  target/arm/hvf/hvf.c | 95 ++++++++++++++++++++++++++++++++++++++++++++
 files changed, 124 insertions(+), 6 deletions(-)
  create mode 100644 target/arm/hvf_arm.h
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
  #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
  #define CPU_RESOLVING_TYPE TYPE_ARM_CPU
 +#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
 +
  #define cpu_signal_handler cpu_arm_signal_handler
  #define cpu_list arm_cpu_list
 diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/arm/hvf_arm.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QEMU Hypervisor.framework (HVF) support -- ARM specifics
 + *
 + * Copyright (c) 2021 Alexander Graf
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
 + *
 + */
 +
 +#ifndef QEMU_HVF_ARM_H
 +#define QEMU_HVF_ARM_H
 +
 +#include "cpu.h"
 +
 +void hvf_arm_set_cpu_features_from_host(struct ARMCPU *cpu);
 +
 +#endif
 diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm_arm.h
 +++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
   */
  void kvm_arm_destroy_scratch_host_vcpu(int *fdarray);
 -#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
 -
  /**
   * ARMHostCPUFeatures: information about the host CPU (identified
   * by asking the host kernel)
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
  #include "sysemu/tcg.h"
  #include "sysemu/hw_accel.h"
  #include "kvm_arm.h"
 +#include "hvf_arm.h"
  #include "disas/capstone.h"
  #include "fpu/softfloat.h"
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
       * this is the first point where we can report it.
       */
      if (cpu->host_cpu_probe_failed) {
 -        if (!kvm_enabled()) {
 -            error_setg(errp, "The 'host' CPU type can only be used with KVM");
 +        if (!kvm_enabled() && !hvf_enabled()) {
 +            error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF");
          } else {
              error_setg(errp, "Failed to retrieve host CPU features");
          }
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
  #endif /* CONFIG_TCG */
  }
 -#ifdef CONFIG_KVM
 +#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
  static void arm_host_initfn(Object *obj)
  {
      ARMCPU *cpu = ARM_CPU(obj);
 +#ifdef CONFIG_KVM
      kvm_arm_set_cpu_features_from_host(cpu);
      if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
          aarch64_add_sve_properties(obj);
      }
 +#else
 +    hvf_arm_set_cpu_features_from_host(cpu);
 +#endif
      arm_cpu_post_init(obj);
  }
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void)
  {
      type_register_static(&arm_cpu_type_info);
 -#ifdef CONFIG_KVM
 +#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
      type_register_static(&host_arm_cpu_type_info);
  #endif
  }
 diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/hvf/hvf.c
 +++ b/target/arm/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@
  #include "sysemu/hvf.h"
  #include "sysemu/hvf_int.h"
  #include "sysemu/hw_accel.h"
 +#include "hvf_arm.h"
  #include <mach/mach_time.h>
@@ -XXX,XX +XXX,XX @@ typedef struct HVFVTimer {
  static HVFVTimer vtimer;
 +typedef struct ARMHostCPUFeatures {
 +    ARMISARegisters isar;
 +    uint64_t features;
 +    uint64_t midr;
 +    uint32_t reset_sctlr;
 +    const char *dtb_compatible;
 +} ARMHostCPUFeatures;
 +
 +static ARMHostCPUFeatures arm_host_cpu_features;
 +
  struct hvf_reg_match {
      int reg;
      uint64_t offset;
@@ -XXX,XX +XXX,XX @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt)
      return val;
  }
 +static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
 +{
 +    ARMISARegisters host_isar = {};
 +    const struct isar_regs {
 +        int reg;
 +        uint64_t *val;
 +    } regs[] = {
 +        { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 },
 +        { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 },
 +        { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 },
 +        { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 },
 +        { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 },
 +        { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 },
 +        { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 },
 +        { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 },
 +        { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 },
 +    };
 +    hv_vcpu_t fd;
 +    hv_return_t r = HV_SUCCESS;
 +    hv_vcpu_exit_t *exit;
 +    int i;
 +
 +    ahcf->dtb_compatible = "arm,arm-v8";
 +    ahcf->features = (1ULL << ARM_FEATURE_V8) |
 +                     (1ULL << ARM_FEATURE_NEON) |
 +                     (1ULL << ARM_FEATURE_AARCH64) |
 +                     (1ULL << ARM_FEATURE_PMU) |
 +                     (1ULL << ARM_FEATURE_GENERIC_TIMER);
 +
 +    /* We set up a small vcpu to extract host registers */
 +
 +    if (hv_vcpu_create(&fd, &exit, NULL) != HV_SUCCESS) {
 +        return false;
 +    }
 +
 +    for (i = 0; i < ARRAY_SIZE(regs); i++) {
 +        r |= hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val);
 +    }
 +    r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr);
 +    r |= hv_vcpu_destroy(fd);
 +
 +    ahcf->isar = host_isar;
 +
 +    /*
 +     * A scratch vCPU returns SCTLR 0, so let's fill our default with the M1
 +     * boot SCTLR from https://github.com/AsahiLinux/m1n1/issues/97
 +     */
 +    ahcf->reset_sctlr = 0x30100180;
 +    /*
 +     * SPAN is disabled by default when SCTLR.SPAN=1. To improve compatibility,
 +     * let's disable it on boot and then allow guest software to turn it on by
 +     * setting it to 0.
 +     */
 +    ahcf->reset_sctlr |= 0x00800000;
 +
 +    /* Make sure we don't advertise AArch32 support for EL0/EL1 */
 +    if ((host_isar.id_aa64pfr0 & 0xff) != 0x11) {
 +        return false;
 +    }
 +
 +    return r == HV_SUCCESS;
 +}
 +
 +void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu)
 +{
 +    if (!arm_host_cpu_features.dtb_compatible) {
 +        if (!hvf_enabled() ||
 +            !hvf_arm_get_host_cpu_features(&arm_host_cpu_features)) {
 +            /*
 +             * We can't report this error yet, so flag that we need to
 +             * in arm_cpu_realizefn().
 +             */
 +            cpu->host_cpu_probe_failed = true;
 +            return;
 +        }
 +    }
 +
 +    cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible;
 +    cpu->isar = arm_host_cpu_features.isar;
 +    cpu->env.features = arm_host_cpu_features.features;
 +    cpu->midr = arm_host_cpu_features.midr;
 +    cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr;
 +}
 +
  void hvf_arch_vcpu_destroy(CPUState *cpu)
  {
  }
 --
 .20.1

-[Qemu-devel] [PULL 01/10] target/arm: report ARMv8-A FP support for AArch32 -cpu max
+[PULL 13/27] hvf: arm: Implement PSCI handling
-From: Alex Bennée <alex.bennee@linaro.org>
+From: Alexander Graf <agraf@csgraf.de>
-When we converted to using feature bits in 602f6e42cfbf we missed out
+We need to handle PSCI calls. Most of the TCG code works for us,
-the fact (dp && arm_dc_feature(s, ARM_FEATURE_V8)) was supported for
+but we can simplify it to only handle aa64 mode and we need to
--cpu max configurations. This caused a regression in the GCC test
+handle SUSPEND differently.
-suite. Fix this by setting the appropriate bits in mvfr1.FPHP to
-report ARMv8-A with FP support (but not ARMv8.2-FP16).
+This patch takes the TCG code as template and duplicates it in HVF.
-Fixes: https://bugs.launchpad.net/qemu/+bug/1836078
+To tell the guest that we support PSCI 0.2 now, update the check in
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+arm_cpu_initfn() as well.
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190711103737.10017-1-alex.bennee@linaro.org
+Signed-off-by: Alexander Graf <agraf@csgraf.de>
 Reviewed-by: Sergio Lopez <slp@redhat.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20210916155404.86958-8-agraf@csgraf.de
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.c | 4 ++++
+ target/arm/cpu.c            |   4 +-
-file changed, 4 insertions(+)
+ target/arm/hvf/hvf.c        | 141 ++++++++++++++++++++++++++++++++++--
  target/arm/hvf/trace-events |   1 +
 files changed, 139 insertions(+), 7 deletions(-)
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
-             t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
+     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
-             cpu->isar.id_isar6 = t;
+     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
-+            t = cpu->isar.mvfr1;
+-    if (tcg_enabled()) {
-+            t = FIELD_DP32(t, MVFR1, FPHP, 2);     /* v8.0 FP support */
+-        cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
-+            cpu->isar.mvfr1 = t;
++    if (tcg_enabled() || hvf_enabled()) {
-+
++        cpu->psci_version = 2; /* TCG and HVF implement PSCI 0.2 */
-             t = cpu->isar.mvfr2;
+     }
-             t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
+ }
-             t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
 diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/hvf/hvf.c
 +++ b/target/arm/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/irq.h"
  #include "qemu/main-loop.h"
  #include "sysemu/cpus.h"
 +#include "arm-powerctl.h"
  #include "target/arm/cpu.h"
  #include "target/arm/internals.h"
  #include "trace/trace-target_arm_hvf.h"
@@ -XXX,XX +XXX,XX @@
  #define TMR_CTL_IMASK   (1 << 1)
  #define TMR_CTL_ISTATUS (1 << 2)
 +static void hvf_wfi(CPUState *cpu);
 +
  typedef struct HVFVTimer {
      /* Vtimer value during migration and paused state */
      uint64_t vtimer_val;
@@ -XXX,XX +XXX,XX @@ static void hvf_raise_exception(CPUState *cpu, uint32_t excp,
      arm_cpu_do_interrupt(cpu);
  }
 +static void hvf_psci_cpu_off(ARMCPU *arm_cpu)
 +{
 +    int32_t ret = arm_set_cpu_off(arm_cpu->mp_affinity);
 +    assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS);
 +}
 +
 +/*
 + * Handle a PSCI call.
 + *
 + * Returns 0 on success
 + *         -1 when the PSCI call is unknown,
 + */
 +static bool hvf_handle_psci_call(CPUState *cpu)
 +{
 +    ARMCPU *arm_cpu = ARM_CPU(cpu);
 +    CPUARMState *env = &arm_cpu->env;
 +    uint64_t param[4] = {
 +        env->xregs[0],
 +        env->xregs[1],
 +        env->xregs[2],
 +        env->xregs[3]
 +    };
 +    uint64_t context_id, mpidr;
 +    bool target_aarch64 = true;
 +    CPUState *target_cpu_state;
 +    ARMCPU *target_cpu;
 +    target_ulong entry;
 +    int target_el = 1;
 +    int32_t ret = 0;
 +
 +    trace_hvf_psci_call(param[0], param[1], param[2], param[3],
 +                        arm_cpu->mp_affinity);
 +
 +    switch (param[0]) {
 +    case QEMU_PSCI_0_2_FN_PSCI_VERSION:
 +        ret = QEMU_PSCI_0_2_RET_VERSION_0_2;
 +        break;
 +    case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
 +        ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */
 +        break;
 +    case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
 +    case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
 +        mpidr = param[1];
 +
 +        switch (param[2]) {
 +        case 0:
 +            target_cpu_state = arm_get_cpu_by_id(mpidr);
 +            if (!target_cpu_state) {
 +                ret = QEMU_PSCI_RET_INVALID_PARAMS;
 +                break;
 +            }
 +            target_cpu = ARM_CPU(target_cpu_state);
 +
 +            ret = target_cpu->power_state;
 +            break;
 +        default:
 +            /* Everything above affinity level 0 is always on. */
 +            ret = 0;
 +        }
 +        break;
 +    case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
 +        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 +        /*
 +         * QEMU reset and shutdown are async requests, but PSCI
 +         * mandates that we never return from the reset/shutdown
 +         * call, so power the CPU off now so it doesn't execute
 +         * anything further.
 +         */
 +        hvf_psci_cpu_off(arm_cpu);
 +        break;
 +    case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
 +        qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 +        hvf_psci_cpu_off(arm_cpu);
 +        break;
 +    case QEMU_PSCI_0_1_FN_CPU_ON:
 +    case QEMU_PSCI_0_2_FN_CPU_ON:
 +    case QEMU_PSCI_0_2_FN64_CPU_ON:
 +        mpidr = param[1];
 +        entry = param[2];
 +        context_id = param[3];
 +        ret = arm_set_cpu_on(mpidr, entry, context_id,
 +                             target_el, target_aarch64);
 +        break;
 +    case QEMU_PSCI_0_1_FN_CPU_OFF:
 +    case QEMU_PSCI_0_2_FN_CPU_OFF:
 +        hvf_psci_cpu_off(arm_cpu);
 +        break;
 +    case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
 +    case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
 +    case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
 +        /* Affinity levels are not supported in QEMU */
 +        if (param[1] & 0xfffe0000) {
 +            ret = QEMU_PSCI_RET_INVALID_PARAMS;
 +            break;
 +        }
 +        /* Powerdown is not supported, we always go into WFI */
 +        env->xregs[0] = 0;
 +        hvf_wfi(cpu);
 +        break;
 +    case QEMU_PSCI_0_1_FN_MIGRATE:
 +    case QEMU_PSCI_0_2_FN_MIGRATE:
 +        ret = QEMU_PSCI_RET_NOT_SUPPORTED;
 +        break;
 +    default:
 +        return false;
 +    }
 +
 +    env->xregs[0] = ret;
 +    return true;
 +}
 +
  static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
  {
      ARMCPU *arm_cpu = ARM_CPU(cpu);
@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu)
          break;
      case EC_AA64_HVC:
          cpu_synchronize_state(cpu);
 -        trace_hvf_unknown_hvc(env->xregs[0]);
 -        /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */
 -        env->xregs[0] = -1;
 +        if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_HVC) {
 +            if (!hvf_handle_psci_call(cpu)) {
 +                trace_hvf_unknown_hvc(env->xregs[0]);
 +                /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */
 +                env->xregs[0] = -1;
 +            }
 +        } else {
 +            trace_hvf_unknown_hvc(env->xregs[0]);
 +            hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
 +        }
          break;
      case EC_AA64_SMC:
          cpu_synchronize_state(cpu);
 -        trace_hvf_unknown_smc(env->xregs[0]);
 -        hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
 +        if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_SMC) {
 +            advance_pc = true;
 +
 +            if (!hvf_handle_psci_call(cpu)) {
 +                trace_hvf_unknown_smc(env->xregs[0]);
 +                /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */
 +                env->xregs[0] = -1;
 +            }
 +        } else {
 +            trace_hvf_unknown_smc(env->xregs[0]);
 +            hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
 +        }
          break;
      default:
          cpu_synchronize_state(cpu);
 diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/hvf/trace-events
 +++ b/target/arm/hvf/trace-events
@@ -XXX,XX +XXX,XX @@ hvf_sysreg_write(uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_
  hvf_unknown_hvc(uint64_t x0) "unknown HVC! 0x%016"PRIx64
  hvf_unknown_smc(uint64_t x0) "unknown SMC! 0x%016"PRIx64
  hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [ec=0x%x pc=0x%"PRIx64"]"
 +hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t cpuid) "PSCI Call x0=0x%016"PRIx64" x1=0x%016"PRIx64" x2=0x%016"PRIx64" x3=0x%016"PRIx64" cpu=0x%x"
 --
 .20.1

-[Qemu-devel] [PULL 05/10] hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
+[PULL 14/27] arm: Add Hypervisor.framework build target
-From: Philippe Mathieu-Daudé <philmd@redhat.com>
+From: Alexander Graf <agraf@csgraf.de>
-Reading the RX_DATA register when the RX_FIFO is empty triggers
+Now that we have all logic in place that we need to handle Hypervisor.framework
-an abort. This can be easily reproduced:
+on Apple Silicon systems, let's add CONFIG_HVF for aarch64 as well so that we
 can build it.
-  $ qemu-system-arm -M emcraft-sf2 -monitor stdio -S
+Signed-off-by: Alexander Graf <agraf@csgraf.de>
-  QEMU 4.0.50 monitor - type 'help' for more information
+Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
-  (qemu) x 0x40001010
+Tested-by: Roman Bolshakov <r.bolshakov@yadro.com> (x86 only)
-  Aborted (core dumped)
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Sergio Lopez <slp@redhat.com>
-  (gdb) bt
+Message-id: 20210916155404.86958-9-agraf@csgraf.de
   #1  0x00007f035874f895 in abort () at /lib64/libc.so.6
   #2  0x00005628686591ff in fifo8_pop (fifo=0x56286a9a4c68) at util/fifo8.c:66
   #3  0x00005628683e0b8e in fifo32_pop (fifo=0x56286a9a4c68) at include/qemu/fifo32.h:137
   #4  0x00005628683e0efb in spi_read (opaque=0x56286a9a4850, addr=4, size=4) at hw/ssi/mss-spi.c:168
   #5  0x0000562867f96801 in memory_region_read_accessor (mr=0x56286a9a4b60, addr=16, value=0x7ffeecb0c5c8, size=4, shift=0, mask=4294967295, attrs=...) at memory.c:439
   #6  0x0000562867f96cdb in access_with_adjusted_size (addr=16, value=0x7ffeecb0c5c8, size=4, access_size_min=1, access_size_max=4, access_fn=0x562867f967c3 <memory_region_read_accessor>, mr=0x56286a9a4b60, attrs=...) at memory.c:569
   #7  0x0000562867f99940 in memory_region_dispatch_read1 (mr=0x56286a9a4b60, addr=16, pval=0x7ffeecb0c5c8, size=4, attrs=...) at memory.c:1420
   #8  0x0000562867f99a08 in memory_region_dispatch_read (mr=0x56286a9a4b60, addr=16, pval=0x7ffeecb0c5c8, size=4, attrs=...) at memory.c:1447
   #9  0x0000562867f38721 in flatview_read_continue (fv=0x56286aec6360, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4, addr1=16, l=4, mr=0x56286a9a4b60) at exec.c:3385
   #10 0x0000562867f38874 in flatview_read (fv=0x56286aec6360, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4) at exec.c:3423
   #11 0x0000562867f388ea in address_space_read_full (as=0x56286aa3e890, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4) at exec.c:3436
   #12 0x0000562867f389c5 in address_space_rw (as=0x56286aa3e890, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4, is_write=false) at exec.c:3466
   #13 0x0000562867f3bdd7 in cpu_memory_rw_debug (cpu=0x56286aa19d00, addr=1073745936, buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4, is_write=0) at exec.c:3976
   #14 0x000056286811ed51 in memory_dump (mon=0x56286a8c32d0, count=1, format=120, wsize=4, addr=1073745936, is_physical=0) at monitor/misc.c:730
   #15 0x000056286811eff1 in hmp_memory_dump (mon=0x56286a8c32d0, qdict=0x56286b15c400) at monitor/misc.c:785
   #16 0x00005628684740ee in handle_hmp_command (mon=0x56286a8c32d0, cmdline=0x56286a8caeb2 "0x40001010") at monitor/hmp.c:1082
 From the datasheet "Actel SmartFusion Microcontroller Subsystem
 User's Guide" Rev.1, Table 13-3 "SPI Register Summary", this
 register has a reset value of 0.
 Check the FIFO is not empty before accessing it, else log an
 error message.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20190709113715.7761-3-philmd@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/ssi/mss-spi.c | 8 +++++++-
+ meson.build                | 7 +++++++
-file changed, 7 insertions(+), 1 deletion(-)
+ target/arm/hvf/meson.build | 3 +++
  target/arm/meson.build     | 2 ++
 files changed, 12 insertions(+)
  create mode 100644 target/arm/hvf/meson.build
-diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
+diff --git a/meson.build b/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/hw/ssi/mss-spi.c
+--- a/meson.build
-+++ b/hw/ssi/mss-spi.c
++++ b/meson.build
-@@ -XXX,XX +XXX,XX @@ spi_read(void *opaque, hwaddr addr, unsigned int size)
+@@ -XXX,XX +XXX,XX @@ else
-     case R_SPI_RX:
+ endif
-         s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
-         s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF;
+ accelerator_targets = { 'CONFIG_KVM': kvm_targets }
--        ret = fifo32_pop(&s->rx_fifo);
++
-+        if (fifo32_is_empty(&s->rx_fifo)) {
++if cpu in ['aarch64']
-+            qemu_log_mask(LOG_GUEST_ERROR,
++  accelerator_targets += {
-+                          "%s: Reading empty RX_FIFO\n",
++    'CONFIG_HVF': ['aarch64-softmmu']
-+                          __func__);
++  }
-+        } else {
++endif
-+            ret = fifo32_pop(&s->rx_fifo);
++
-+        }
+ if cpu in ['x86', 'x86_64', 'arm', 'aarch64']
-         if (fifo32_is_empty(&s->rx_fifo)) {
+   # i386 emulator provides xenpv machine type for multiple architectures
-             s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
+   accelerator_targets += {
-         }
+diff --git a/target/arm/hvf/meson.build b/target/arm/hvf/meson.build
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/arm/hvf/meson.build
@@ -XXX,XX +XXX,XX @@
 +arm_softmmu_ss.add(when: [hvf, 'CONFIG_HVF'], if_true: files(
 +  'hvf.c',
 +))
 diff --git a/target/arm/meson.build b/target/arm/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/meson.build
 +++ b/target/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_softmmu_ss.add(files(
    'psci.c',
  ))
 +subdir('hvf')
 +
  target_arch += {'arm': arm_ss}
  target_softmmu_arch += {'arm': arm_softmmu_ss}
 --
 .20.1

-[Qemu-devel] [PULL 04/10] hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
+[PULL 15/27] hvf: arm: Add rudimentary PMC support
-From: Philippe Mathieu-Daudé <philmd@redhat.com>
+From: Alexander Graf <agraf@csgraf.de>
-Both lqspi_read() and lqspi_load_cache() expect a 32-bit
+We can expose cycle counters on the PMU easily. To be as compatible as
-aligned address.
+possible, let's do so, but make sure we don't expose any other architectural
+counters that we can not model yet.
->From UG1085 datasheet [*] chapter on 'Quad-SPI Controller':
+This allows OSs to work that require PMU support.
-  Transfer Size Limitations
+Signed-off-by: Alexander Graf <agraf@csgraf.de>
-    Because of the 32-bit wide TX, RX, and generic FIFO, all
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-    APB/AXI transfers must be an integer multiple of 4-bytes.
+Message-id: 20210916155404.86958-10-agraf@csgraf.de
     Shorter transfers are not possible.
 Set MemoryRegionOps.impl values to force 32-bit accesses,
 this way we are sure we do not access the lqspi_buf[] array
 out of bound.
 [*] https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
 Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
 Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/ssi/xilinx_spips.c | 4 ++++
+ target/arm/hvf/hvf.c | 179 +++++++++++++++++++++++++++++++++++++++++++
-file changed, 4 insertions(+)
+file changed, 179 insertions(+)
-diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
+diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/ssi/xilinx_spips.c
+--- a/target/arm/hvf/hvf.c
-+++ b/hw/ssi/xilinx_spips.c
++++ b/target/arm/hvf/hvf.c
-@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps lqspi_ops = {
+@@ -XXX,XX +XXX,XX @@
-     .read_with_attrs = lqspi_read,
+ #define SYSREG_OSLSR_EL1      SYSREG(2, 0, 1, 1, 4)
-     .write_with_attrs = lqspi_write,
+ #define SYSREG_OSDLR_EL1      SYSREG(2, 0, 1, 3, 4)
-     .endianness = DEVICE_NATIVE_ENDIAN,
+ #define SYSREG_CNTPCT_EL0     SYSREG(3, 3, 14, 0, 1)
-+    .impl = {
++#define SYSREG_PMCR_EL0       SYSREG(3, 3, 9, 12, 0)
-+        .min_access_size = 4,
++#define SYSREG_PMUSERENR_EL0  SYSREG(3, 3, 9, 14, 0)
-+        .max_access_size = 4,
++#define SYSREG_PMCNTENSET_EL0 SYSREG(3, 3, 9, 12, 1)
-+    },
++#define SYSREG_PMCNTENCLR_EL0 SYSREG(3, 3, 9, 12, 2)
-     .valid = {
++#define SYSREG_PMINTENCLR_EL1 SYSREG(3, 0, 9, 14, 2)
-         .min_access_size = 1,
++#define SYSREG_PMOVSCLR_EL0   SYSREG(3, 3, 9, 12, 3)
-         .max_access_size = 4
++#define SYSREG_PMSWINC_EL0    SYSREG(3, 3, 9, 12, 4)
 +#define SYSREG_PMSELR_EL0     SYSREG(3, 3, 9, 12, 5)
 +#define SYSREG_PMCEID0_EL0    SYSREG(3, 3, 9, 12, 6)
 +#define SYSREG_PMCEID1_EL0    SYSREG(3, 3, 9, 12, 7)
 +#define SYSREG_PMCCNTR_EL0    SYSREG(3, 3, 9, 13, 0)
 +#define SYSREG_PMCCFILTR_EL0  SYSREG(3, 3, 14, 15, 7)
  #define WFX_IS_WFE (1 << 0)
@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
          val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /
                gt_cntfrq_period_ns(arm_cpu);
          break;
 +    case SYSREG_PMCR_EL0:
 +        val = env->cp15.c9_pmcr;
 +        break;
 +    case SYSREG_PMCCNTR_EL0:
 +        pmu_op_start(env);
 +        val = env->cp15.c15_ccnt;
 +        pmu_op_finish(env);
 +        break;
 +    case SYSREG_PMCNTENCLR_EL0:
 +        val = env->cp15.c9_pmcnten;
 +        break;
 +    case SYSREG_PMOVSCLR_EL0:
 +        val = env->cp15.c9_pmovsr;
 +        break;
 +    case SYSREG_PMSELR_EL0:
 +        val = env->cp15.c9_pmselr;
 +        break;
 +    case SYSREG_PMINTENCLR_EL1:
 +        val = env->cp15.c9_pminten;
 +        break;
 +    case SYSREG_PMCCFILTR_EL0:
 +        val = env->cp15.pmccfiltr_el0;
 +        break;
 +    case SYSREG_PMCNTENSET_EL0:
 +        val = env->cp15.c9_pmcnten;
 +        break;
 +    case SYSREG_PMUSERENR_EL0:
 +        val = env->cp15.c9_pmuserenr;
 +        break;
 +    case SYSREG_PMCEID0_EL0:
 +    case SYSREG_PMCEID1_EL0:
 +        /* We can't really count anything yet, declare all events invalid */
 +        val = 0;
 +        break;
      case SYSREG_OSLSR_EL1:
          val = env->cp15.oslsr_el1;
          break;
@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
      return 0;
  }
 +static void pmu_update_irq(CPUARMState *env)
 +{
 +    ARMCPU *cpu = env_archcpu(env);
 +    qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) &&
 +            (env->cp15.c9_pminten & env->cp15.c9_pmovsr));
 +}
 +
 +static bool pmu_event_supported(uint16_t number)
 +{
 +    return false;
 +}
 +
 +/* Returns true if the counter (pass 31 for PMCCNTR) should count events using
 + * the current EL, security state, and register configuration.
 + */
 +static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
 +{
 +    uint64_t filter;
 +    bool enabled, filtered = true;
 +    int el = arm_current_el(env);
 +
 +    enabled = (env->cp15.c9_pmcr & PMCRE) &&
 +              (env->cp15.c9_pmcnten & (1 << counter));
 +
 +    if (counter == 31) {
 +        filter = env->cp15.pmccfiltr_el0;
 +    } else {
 +        filter = env->cp15.c14_pmevtyper[counter];
 +    }
 +
 +    if (el == 0) {
 +        filtered = filter & PMXEVTYPER_U;
 +    } else if (el == 1) {
 +        filtered = filter & PMXEVTYPER_P;
 +    }
 +
 +    if (counter != 31) {
 +        /*
 +         * If not checking PMCCNTR, ensure the counter is setup to an event we
 +         * support
 +         */
 +        uint16_t event = filter & PMXEVTYPER_EVTCOUNT;
 +        if (!pmu_event_supported(event)) {
 +            return false;
 +        }
 +    }
 +
 +    return enabled && !filtered;
 +}
 +
 +static void pmswinc_write(CPUARMState *env, uint64_t value)
 +{
 +    unsigned int i;
 +    for (i = 0; i < pmu_num_counters(env); i++) {
 +        /* Increment a counter's count iff: */
 +        if ((value & (1 << i)) && /* counter's bit is set */
 +                /* counter is enabled and not filtered */
 +                pmu_counter_enabled(env, i) &&
 +                /* counter is SW_INCR */
 +                (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) {
 +            /*
 +             * Detect if this write causes an overflow since we can't predict
 +             * PMSWINC overflows like we can for other events
 +             */
 +            uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1;
 +
 +            if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) {
 +                env->cp15.c9_pmovsr |= (1 << i);
 +                pmu_update_irq(env);
 +            }
 +
 +            env->cp15.c14_pmevcntr[i] = new_pmswinc;
 +        }
 +    }
 +}
 +
  static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
  {
      ARMCPU *arm_cpu = ARM_CPU(cpu);
@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
                             val);
      switch (reg) {
 +    case SYSREG_PMCCNTR_EL0:
 +        pmu_op_start(env);
 +        env->cp15.c15_ccnt = val;
 +        pmu_op_finish(env);
 +        break;
 +    case SYSREG_PMCR_EL0:
 +        pmu_op_start(env);
 +
 +        if (val & PMCRC) {
 +            /* The counter has been reset */
 +            env->cp15.c15_ccnt = 0;
 +        }
 +
 +        if (val & PMCRP) {
 +            unsigned int i;
 +            for (i = 0; i < pmu_num_counters(env); i++) {
 +                env->cp15.c14_pmevcntr[i] = 0;
 +            }
 +        }
 +
 +        env->cp15.c9_pmcr &= ~PMCR_WRITEABLE_MASK;
 +        env->cp15.c9_pmcr |= (val & PMCR_WRITEABLE_MASK);
 +
 +        pmu_op_finish(env);
 +        break;
 +    case SYSREG_PMUSERENR_EL0:
 +        env->cp15.c9_pmuserenr = val & 0xf;
 +        break;
 +    case SYSREG_PMCNTENSET_EL0:
 +        env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env));
 +        break;
 +    case SYSREG_PMCNTENCLR_EL0:
 +        env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env));
 +        break;
 +    case SYSREG_PMINTENCLR_EL1:
 +        pmu_op_start(env);
 +        env->cp15.c9_pminten |= val;
 +        pmu_op_finish(env);
 +        break;
 +    case SYSREG_PMOVSCLR_EL0:
 +        pmu_op_start(env);
 +        env->cp15.c9_pmovsr &= ~val;
 +        pmu_op_finish(env);
 +        break;
 +    case SYSREG_PMSWINC_EL0:
 +        pmu_op_start(env);
 +        pmswinc_write(env, val);
 +        pmu_op_finish(env);
 +        break;
 +    case SYSREG_PMSELR_EL0:
 +        env->cp15.c9_pmselr = val & 0x1f;
 +        break;
 +    case SYSREG_PMCCFILTR_EL0:
 +        pmu_op_start(env);
 +        env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0;
 +        pmu_op_finish(env);
 +        break;
      case SYSREG_OSLAR_EL1:
          env->cp15.oslsr_el1 = val & 1;
          break;
 --
 .20.1

-New patch
+[PULL 16/27] target/arm: Avoid goto_tb if we're trying to exit to the main loop
+Currently gen_jmp_tb() assumes that if it is called then the jump it
+is handling is the only reason that we might be trying to end the TB,
+so it will use goto_tb if it can.  This is usually the case: mostly
+"we did something that means we must end the TB" happens on a
+non-branch instruction.  However, there are cases where we decide
+early in handling an instruction that we need to end the TB and
+return to the main loop, and then the insn is a complex one that
+involves gen_jmp_tb().  For instance, for M-profile FP instructions,
+in gen_preserve_fp_state() which is called from vfp_access_check() we
+want to force an exit to the main loop if lazy state preservation is
+active and we are in icount mode.
+Make gen_jmp_tb() look at the current value of is_jmp, and only use
+goto_tb if the previous is_jmp was DISAS_NEXT or DISAS_TOO_MANY.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210913095440.13462-2-peter.maydell@linaro.org
+---
+ target/arm/translate.c | 34 +++++++++++++++++++++++++++++++++-
+file changed, 33 insertions(+), 1 deletion(-)
+diff --git a/target/arm/translate.c b/target/arm/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.c
++++ b/target/arm/translate.c
+@@ -XXX,XX +XXX,XX @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
+         /* An indirect jump so that we still trigger the debug exception.  */
+         gen_set_pc_im(s, dest);
+         s->base.is_jmp = DISAS_JUMP;
+-    } else {
++        return;
++    }
++    switch (s->base.is_jmp) {
++    case DISAS_NEXT:
++    case DISAS_TOO_MANY:
++    case DISAS_NORETURN:
++        /*
++         * The normal case: just go to the destination TB.
++         * NB: NORETURN happens if we generate code like
++         *    gen_brcondi(l);
++         *    gen_jmp();
++         *    gen_set_label(l);
++         *    gen_jmp();
++         * on the second call to gen_jmp().
++         */
+         gen_goto_tb(s, tbno, dest);
++        break;
++    case DISAS_UPDATE_NOCHAIN:
++    case DISAS_UPDATE_EXIT:
++        /*
++         * We already decided we're leaving the TB for some other reason.
++         * Avoid using goto_tb so we really do exit back to the main loop
++         * and don't chain to another TB.
++         */
++        gen_set_pc_im(s, dest);
++        gen_goto_ptr();
++        s->base.is_jmp = DISAS_NORETURN;
++        break;
++    default:
++        /*
++         * We shouldn't be emitting code for a jump and also have
++         * is_jmp set to one of the special cases like DISAS_SWI.
++         */
++        g_assert_not_reached();
+     }
+ }
+--
+.20.1

-New patch
+[PULL 17/27] target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration
+Architecturally, for an M-profile CPU with the LOB feature the
+LTPSIZE field in FPDSCR is always constant 4.  QEMU's implementation
+enforces this everywhere, except that we don't check that it is true
+in incoming migration data.
+We're going to add come in gen_update_fp_context() which relies on
+the "always 4" property.  Since this is TCG-only, we don't actually
+need to be robust to bogus incoming migration data, and the effect of
+it being wrong would be wrong code generation rather than a QEMU
+crash; but if it did ever happen somehow it would be very difficult
+to track down the cause.  Add a check so that we fail the inbound
+migration if the FPDSCR.LTPSIZE value is incorrect.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210913095440.13462-3-peter.maydell@linaro.org
+---
+ target/arm/machine.c | 13 +++++++++++++
+file changed, 13 insertions(+)
+diff --git a/target/arm/machine.c b/target/arm/machine.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/machine.c
++++ b/target/arm/machine.c
+@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
+     hw_breakpoint_update_all(cpu);
+     hw_watchpoint_update_all(cpu);
++    /*
++     * TCG gen_update_fp_context() relies on the invariant that
++     * FPDSCR.LTPSIZE is constant 4 for M-profile with the LOB extension;
++     * forbid bogus incoming data with some other value.
++     */
++    if (arm_feature(env, ARM_FEATURE_M) && cpu_isar_feature(aa32_lob, cpu)) {
++        if (extract32(env->v7m.fpdscr[M_REG_NS],
++                      FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4 ||
++            extract32(env->v7m.fpdscr[M_REG_S],
++                      FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4) {
++            return -1;
++        }
++    }
+     if (!kvm_enabled()) {
+         pmu_op_finish(&cpu->env);
+     }
+--
+.20.1

-New patch
+[PULL 18/27] target/arm: Add TB flag for "MVE insns not predicated"
+Our current codegen for MVE always calls out to helper functions,
 because some byte lanes might be predicated.  The common case is that
 in fact there is no predication active and all lanes should be
 updated together, so we can produce better code by detecting that and
 using the TCG generic vector infrastructure.
 Add a TB flag that is set when we can guarantee that there is no
 active MVE predication, and a bool in the DisasContext.  Subsequent
 patches will use this flag to generate improved code for some
 instructions.
 In most cases when the predication state changes we simply end the TB
 after that instruction.  For the code called from vfp_access_check()
 that handles lazy state preservation and creating a new FP context,
 we can usually avoid having to try to end the TB because luckily the
 new value of the flag following the register changes in those
 sequences doesn't depend on any runtime decisions.  We do have to end
 the TB if the guest has enabled lazy FP state preservation but not
 automatic state preservation, but this is an odd corner case that is
 not going to be common in real-world code.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20210913095440.13462-4-peter.maydell@linaro.org
 ---
  target/arm/cpu.h              |  4 +++-
  target/arm/translate.h        |  2 ++
  target/arm/helper.c           | 33 +++++++++++++++++++++++++++++++++
  target/arm/translate-m-nocp.c |  8 +++++++-
  target/arm/translate-mve.c    | 13 ++++++++++++-
  target/arm/translate-vfp.c    | 33 +++++++++++++++++++++++++++------
  target/arm/translate.c        |  8 ++++++++
 files changed, 92 insertions(+), 9 deletions(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef ARMCPU ArchCPU;
   * | TBFLAG_AM32 |          +-----+----------+
   * |             |                |TBFLAG_M32|
   * +-------------+----------------+----------+
 - *  31         23                5 4        0
 + *  31         23                6 5        0
   *
   * Unless otherwise noted, these bits are cached in env->hflags.
   */
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_M32, LSPACT, 2, 1)                 /* Not cached. */
  FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1)     /* Not cached. */
  /* Set if FPCCR.S does not match current security state */
  FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1)          /* Not cached. */
 +/* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */
 +FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1)            /* Not cached. */
  /*
   * Bit usage when in AArch64 state
 diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.h
 +++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
      bool align_mem;
      /* True if PSTATE.IL is set */
      bool pstate_il;
 +    /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */
 +    bool mve_no_pred;
      /*
       * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
       *  < 0, set by the current instruction.
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static inline void assert_hflags_rebuild_correctly(CPUARMState *env)
  #endif
  }
 +static bool mve_no_pred(CPUARMState *env)
 +{
 +    /*
 +     * Return true if there is definitely no predication of MVE
 +     * instructions by VPR or LTPSIZE. (Returning false even if there
 +     * isn't any predication is OK; generated code will just be
 +     * a little worse.)
 +     * If the CPU does not implement MVE then this TB flag is always 0.
 +     *
 +     * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
 +     * logic in gen_update_fp_context() needs to be updated to match.
 +     *
 +     * We do not include the effect of the ECI bits here -- they are
 +     * tracked in other TB flags. This simplifies the logic for
 +     * "when did we emit code that changes the MVE_NO_PRED TB flag
 +     * and thus need to end the TB?".
 +     */
 +    if (cpu_isar_feature(aa32_mve, env_archcpu(env))) {
 +        return false;
 +    }
 +    if (env->v7m.vpr) {
 +        return false;
 +    }
 +    if (env->v7m.ltpsize < 4) {
 +        return false;
 +    }
 +    return true;
 +}
 +
  void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
                            target_ulong *cs_base, uint32_t *pflags)
  {
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
              if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) {
                  DP_TBFLAG_M32(flags, LSPACT, 1);
              }
 +
 +            if (mve_no_pred(env)) {
 +                DP_TBFLAG_M32(flags, MVE_NO_PRED, 1);
 +            }
          } else {
              /*
               * Note that XSCALE_CPAR shares bits with VECSTRIDE.
 diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-m-nocp.c
 +++ b/target/arm/translate-m-nocp.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
      clear_eci_state(s);
 -    /* End the TB, because we have updated FP control bits */
 +    /*
 +     * End the TB, because we have updated FP control bits,
 +     * and possibly VPR or LTPSIZE.
 +     */
      s->base.is_jmp = DISAS_UPDATE_EXIT;
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
          store_cpu_field(control, v7m.control[M_REG_S]);
          tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
          gen_helper_vfp_set_fpscr(cpu_env, tmp);
 +        s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
          tcg_temp_free_i32(tmp);
          tcg_temp_free_i32(sfpa);
          break;
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
          }
          tmp = loadfn(s, opaque, true);
          store_cpu_field(tmp, v7m.vpr);
 +        s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
          break;
      case ARM_VFP_P0:
      {
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
          tcg_gen_deposit_i32(vpr, vpr, tmp,
                              R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH);
          store_cpu_field(vpr, v7m.vpr);
 +        s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
          tcg_temp_free_i32(tmp);
          break;
      }
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_LOGIC(VORR, gen_helper_mve_vorr)
  DO_LOGIC(VORN, gen_helper_mve_vorn)
  DO_LOGIC(VEOR, gen_helper_mve_veor)
 -DO_LOGIC(VPSEL, gen_helper_mve_vpsel)
 +static bool trans_VPSEL(DisasContext *s, arg_2op *a)
 +{
 +    /* This insn updates predication bits */
 +    s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
 +    return do_2op(s, a, gen_helper_mve_vpsel);
 +}
  #define DO_2OP(INSN, FN) \
      static bool trans_##INSN(DisasContext *s, arg_2op *a)       \
@@ -XXX,XX +XXX,XX @@ static bool trans_VPNOT(DisasContext *s, arg_VPNOT *a)
      }
      gen_helper_mve_vpnot(cpu_env);
 +    /* This insn updates predication bits */
 +    s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
      mve_update_eci(s);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool do_vcmp(DisasContext *s, arg_vcmp *a, MVEGenCmpFn *fn)
          /* VPT */
          gen_vpst(s, a->mask);
      }
 +    /* This insn updates predication bits */
 +    s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
      mve_update_eci(s);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool do_vcmp_scalar(DisasContext *s, arg_vcmp_scalar *a,
          /* VPT */
          gen_vpst(s, a->mask);
      }
 +    /* This insn updates predication bits */
 +    s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
      mve_update_eci(s);
      return true;
  }
 diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-vfp.c
 +++ b/target/arm/translate-vfp.c
@@ -XXX,XX +XXX,XX @@ static inline long vfp_f16_offset(unsigned reg, bool top)
   * Generate code for M-profile lazy FP state preservation if needed;
   * this corresponds to the pseudocode PreserveFPState() function.
   */
 -static void gen_preserve_fp_state(DisasContext *s)
 +static void gen_preserve_fp_state(DisasContext *s, bool skip_context_update)
  {
      if (s->v7m_lspact) {
          /*
@@ -XXX,XX +XXX,XX @@ static void gen_preserve_fp_state(DisasContext *s)
           * any further FP insns in this TB.
           */
          s->v7m_lspact = false;
 +        /*
 +         * The helper might have zeroed VPR, so we do not know the
 +         * correct value for the MVE_NO_PRED TB flag any more.
 +         * If we're about to create a new fp context then that
 +         * will precisely determine the MVE_NO_PRED value (see
 +         * gen_update_fp_context()). Otherwise, we must:
 +         *  - set s->mve_no_pred to false, so this instruction
 +         *    is generated to use helper functions
 +         *  - end the TB now, without chaining to the next TB
 +         */
 +        if (skip_context_update || !s->v7m_new_fp_ctxt_needed) {
 +            s->mve_no_pred = false;
 +            s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
 +        }
      }
  }
@@ -XXX,XX +XXX,XX @@ static void gen_update_fp_context(DisasContext *s)
              TCGv_i32 z32 = tcg_const_i32(0);
              store_cpu_field(z32, v7m.vpr);
          }
 -
          /*
 -         * We don't need to arrange to end the TB, because the only
 -         * parts of FPSCR which we cache in the TB flags are the VECLEN
 -         * and VECSTRIDE, and those don't exist for M-profile.
 +         * We just updated the FPSCR and VPR. Some of this state is cached
 +         * in the MVE_NO_PRED TB flag. We want to avoid having to end the
 +         * TB here, which means we need the new value of the MVE_NO_PRED
 +         * flag to be exactly known here and the same for all executions.
 +         * Luckily FPDSCR.LTPSIZE is always constant 4 and the VPR is
 +         * always set to 0, so the new MVE_NO_PRED flag is always 1
 +         * if and only if we have MVE.
 +         *
 +         * (The other FPSCR state cached in TB flags is VECLEN and VECSTRIDE,
 +         * but those do not exist for M-profile, so are not relevant here.)
           */
 +        s->mve_no_pred = dc_isar_feature(aa32_mve, s);
          if (s->v8m_secure) {
              bits |= R_V7M_CONTROL_SFPA_MASK;
@@ -XXX,XX +XXX,XX @@ bool vfp_access_check_m(DisasContext *s, bool skip_context_update)
      /* Handle M-profile lazy FP state mechanics */
      /* Trigger lazy-state preservation if necessary */
 -    gen_preserve_fp_state(s);
 +    gen_preserve_fp_state(s, skip_context_update);
      if (!skip_context_update) {
          /* Update ownership of FP context and create new FP context if needed */
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_DLS(DisasContext *s, arg_DLS *a)
          /* DLSTP: set FPSCR.LTPSIZE */
          tmp = tcg_const_i32(a->size);
          store_cpu_field(tmp, v7m.ltpsize);
 +        s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
      }
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
          assert(ok);
          tmp = tcg_const_i32(a->size);
          store_cpu_field(tmp, v7m.ltpsize);
 +        /*
 +         * LTPSIZE updated, but MVE_NO_PRED will always be the same thing (0)
 +         * when we take this upcoming exit from this TB, so gen_jmp_tb() is OK.
 +         */
      }
      gen_jmp_tb(s, s->base.pc_next, 1);
@@ -XXX,XX +XXX,XX @@ static bool trans_VCTP(DisasContext *s, arg_VCTP *a)
      gen_helper_mve_vctp(cpu_env, masklen);
      tcg_temp_free_i32(masklen);
      tcg_temp_free_i32(rn_shifted);
 +    /* This insn updates predication bits */
 +    s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
      mve_update_eci(s);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
          dc->v7m_new_fp_ctxt_needed =
              EX_TBFLAG_M32(tb_flags, NEW_FP_CTXT_NEEDED);
          dc->v7m_lspact = EX_TBFLAG_M32(tb_flags, LSPACT);
 +        dc->mve_no_pred = EX_TBFLAG_M32(tb_flags, MVE_NO_PRED);
      } else {
          dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL);
          dc->sctlr_b = EX_TBFLAG_A32(tb_flags, SCTLR__B);
 --
 .20.1

-[Qemu-devel] [PULL 06/10] hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
+[PULL 19/27] target/arm: Optimize MVE logic ops
-From: Philippe Mathieu-Daudé <philmd@redhat.com>
+When not predicating, implement the MVE bitwise logical insns
 directly using TCG vector operations.
-In the previous commit we fixed a crash when the guest read a
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-register that pop from an empty FIFO.
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-By auditing the repository, we found another similar use with
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-an easy way to reproduce:
+Message-id: 20210913095440.13462-5-peter.maydell@linaro.org
 ---
  target/arm/translate-mve.c | 51 +++++++++++++++++++++++++++-----------
 file changed, 36 insertions(+), 15 deletions(-)
-  $ qemu-system-aarch64 -M xlnx-zcu102 -monitor stdio -S
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
   QEMU 4.0.50 monitor - type 'help' for more information
   (qemu) xp/b 0xfd4a0134
   Aborted (core dumped)
   (gdb) bt
   #0  0x00007f6936dea57f in raise () at /lib64/libc.so.6
   #1  0x00007f6936dd4895 in abort () at /lib64/libc.so.6
   #2  0x0000561ad32975ec in xlnx_dp_aux_pop_rx_fifo (s=0x7f692babee70) at hw/display/xlnx_dp.c:431
   #3  0x0000561ad3297dc0 in xlnx_dp_read (opaque=0x7f692babee70, offset=77, size=4) at hw/display/xlnx_dp.c:667
   #4  0x0000561ad321b896 in memory_region_read_accessor (mr=0x7f692babf620, addr=308, value=0x7ffe05c1db88, size=4, shift=0, mask=4294967295, attrs=...) at memory.c:439
   #5  0x0000561ad321bd70 in access_with_adjusted_size (addr=308, value=0x7ffe05c1db88, size=1, access_size_min=4, access_size_max=4, access_fn=0x561ad321b858 <memory_region_read_accessor>, mr=0x7f692babf620, attrs=...) at memory.c:569
   #6  0x0000561ad321e9d5 in memory_region_dispatch_read1 (mr=0x7f692babf620, addr=308, pval=0x7ffe05c1db88, size=1, attrs=...) at memory.c:1420
   #7  0x0000561ad321ea9d in memory_region_dispatch_read (mr=0x7f692babf620, addr=308, pval=0x7ffe05c1db88, size=1, attrs=...) at memory.c:1447
   #8  0x0000561ad31bd742 in flatview_read_continue (fv=0x561ad69c04f0, addr=4249485620, attrs=..., buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", len=1, addr1=308, l=1, mr=0x7f692babf620) at exec.c:3385
   #9  0x0000561ad31bd895 in flatview_read (fv=0x561ad69c04f0, addr=4249485620, attrs=..., buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", len=1) at exec.c:3423
   #10 0x0000561ad31bd90b in address_space_read_full (as=0x561ad5bb3020, addr=4249485620, attrs=..., buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", len=1) at exec.c:3436
   #11 0x0000561ad33b1c42 in address_space_read (len=1, buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", attrs=..., addr=4249485620, as=0x561ad5bb3020) at include/exec/memory.h:2131
   #12 0x0000561ad33b1c42 in memory_dump (mon=0x561ad59c4530, count=1, format=120, wsize=1, addr=4249485620, is_physical=1) at monitor/misc.c:723
   #13 0x0000561ad33b1fc1 in hmp_physical_memory_dump (mon=0x561ad59c4530, qdict=0x561ad6c6fd00) at monitor/misc.c:795
   #14 0x0000561ad37b4a9f in handle_hmp_command (mon=0x561ad59c4530, cmdline=0x561ad59d0f22 "/b 0x00000000fd4a0134") at monitor/hmp.c:1082
 Fix by checking the FIFO is not empty before popping from it.
 The datasheet is not clear about the reset value of this register,
 we choose to return '0'.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20190709113715.7761-4-philmd@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  hw/display/xlnx_dp.c | 15 +++++++++++----
 file changed, 11 insertions(+), 4 deletions(-)
 diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/display/xlnx_dp.c
+--- a/target/arm/translate-mve.c
-+++ b/hw/display/xlnx_dp.c
++++ b/target/arm/translate-mve.c
-@@ -XXX,XX +XXX,XX @@ static uint8_t xlnx_dp_aux_pop_rx_fifo(XlnxDPState *s)
+@@ -XXX,XX +XXX,XX @@ static TCGv_ptr mve_qreg_ptr(unsigned reg)
      uint8_t ret;
      if (fifo8_is_empty(&s->rx_fifo)) {
 -        DPRINTF("rx_fifo underflow..\n");
 -        abort();
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Reading empty RX_FIFO\n",
 +                      __func__);
 +        /*
 +         * The datasheet is not clear about the reset value, it seems
 +         * to be unspecified. We choose to return '0'.
 +         */
 +        ret = 0;
 +    } else {
 +        ret = fifo8_pop(&s->rx_fifo);
 +        DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret);
      }
 -    ret = fifo8_pop(&s->rx_fifo);
 -    DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret);
      return ret;
  }
++static bool mve_no_predication(DisasContext *s)
++{
++    /*
++     * Return true if we are executing the entire MVE instruction
++     * with no predication or partial-execution, and so we can safely
++     * use an inline TCG vector implementation.
++     */
++    return s->eci == 0 && s->mve_no_pred;
++}
++
+ static bool mve_check_qreg_bank(DisasContext *s, int qmask)
+ {
+     /*
+@@ -XXX,XX +XXX,XX @@ static bool trans_VNEG_fp(DisasContext *s, arg_1op *a)
+     return do_1op(s, a, fns[a->size]);
+ }
+-static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn)
++static bool do_2op_vec(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn,
++                       GVecGen3Fn *vecfn)
+ {
+     TCGv_ptr qd, qn, qm;
+@@ -XXX,XX +XXX,XX @@ static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn)
+         return true;
+     }
+-    qd = mve_qreg_ptr(a->qd);
+-    qn = mve_qreg_ptr(a->qn);
+-    qm = mve_qreg_ptr(a->qm);
+-    fn(cpu_env, qd, qn, qm);
+-    tcg_temp_free_ptr(qd);
+-    tcg_temp_free_ptr(qn);
+-    tcg_temp_free_ptr(qm);
++    if (vecfn && mve_no_predication(s)) {
++        vecfn(a->size, mve_qreg_offset(a->qd), mve_qreg_offset(a->qn),
++              mve_qreg_offset(a->qm), 16, 16);
++    } else {
++        qd = mve_qreg_ptr(a->qd);
++        qn = mve_qreg_ptr(a->qn);
++        qm = mve_qreg_ptr(a->qm);
++        fn(cpu_env, qd, qn, qm);
++        tcg_temp_free_ptr(qd);
++        tcg_temp_free_ptr(qn);
++        tcg_temp_free_ptr(qm);
++    }
+     mve_update_eci(s);
+     return true;
+ }
+-#define DO_LOGIC(INSN, HELPER)                                  \
++static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn *fn)
++{
++    return do_2op_vec(s, a, fn, NULL);
++}
++
++#define DO_LOGIC(INSN, HELPER, VECFN)                           \
+     static bool trans_##INSN(DisasContext *s, arg_2op *a)       \
+     {                                                           \
+-        return do_2op(s, a, HELPER);                            \
++        return do_2op_vec(s, a, HELPER, VECFN);                 \
+     }
+-DO_LOGIC(VAND, gen_helper_mve_vand)
+-DO_LOGIC(VBIC, gen_helper_mve_vbic)
+-DO_LOGIC(VORR, gen_helper_mve_vorr)
+-DO_LOGIC(VORN, gen_helper_mve_vorn)
+-DO_LOGIC(VEOR, gen_helper_mve_veor)
++DO_LOGIC(VAND, gen_helper_mve_vand, tcg_gen_gvec_and)
++DO_LOGIC(VBIC, gen_helper_mve_vbic, tcg_gen_gvec_andc)
++DO_LOGIC(VORR, gen_helper_mve_vorr, tcg_gen_gvec_or)
++DO_LOGIC(VORN, gen_helper_mve_vorn, tcg_gen_gvec_orc)
++DO_LOGIC(VEOR, gen_helper_mve_veor, tcg_gen_gvec_xor)
+ static bool trans_VPSEL(DisasContext *s, arg_2op *a)
+ {
 --
 .20.1

-New patch
+[PULL 20/27] target/arm: Optimize MVE arithmetic ops
+Optimize MVE arithmetic ops when we have a TCG
+vector operation we can use.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210913095440.13462-6-peter.maydell@linaro.org
+---
+ target/arm/translate-mve.c | 20 +++++++++++---------
+file changed, 11 insertions(+), 9 deletions(-)
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-mve.c
++++ b/target/arm/translate-mve.c
+@@ -XXX,XX +XXX,XX @@ static bool trans_VPSEL(DisasContext *s, arg_2op *a)
+     return do_2op(s, a, gen_helper_mve_vpsel);
+ }
+-#define DO_2OP(INSN, FN) \
++#define DO_2OP_VEC(INSN, FN, VECFN)                             \
+     static bool trans_##INSN(DisasContext *s, arg_2op *a)       \
+     {                                                           \
+         static MVEGenTwoOpFn * const fns[] = {                  \
+@@ -XXX,XX +XXX,XX @@ static bool trans_VPSEL(DisasContext *s, arg_2op *a)
+             gen_helper_mve_##FN##w,                             \
+             NULL,                                               \
+         };                                                      \
+-        return do_2op(s, a, fns[a->size]);                      \
++        return do_2op_vec(s, a, fns[a->size], VECFN);           \
+     }
+-DO_2OP(VADD, vadd)
+-DO_2OP(VSUB, vsub)
+-DO_2OP(VMUL, vmul)
++#define DO_2OP(INSN, FN) DO_2OP_VEC(INSN, FN, NULL)
++
++DO_2OP_VEC(VADD, vadd, tcg_gen_gvec_add)
++DO_2OP_VEC(VSUB, vsub, tcg_gen_gvec_sub)
++DO_2OP_VEC(VMUL, vmul, tcg_gen_gvec_mul)
+ DO_2OP(VMULH_S, vmulhs)
+ DO_2OP(VMULH_U, vmulhu)
+ DO_2OP(VRMULH_S, vrmulhs)
+ DO_2OP(VRMULH_U, vrmulhu)
+-DO_2OP(VMAX_S, vmaxs)
+-DO_2OP(VMAX_U, vmaxu)
+-DO_2OP(VMIN_S, vmins)
+-DO_2OP(VMIN_U, vminu)
++DO_2OP_VEC(VMAX_S, vmaxs, tcg_gen_gvec_smax)
++DO_2OP_VEC(VMAX_U, vmaxu, tcg_gen_gvec_umax)
++DO_2OP_VEC(VMIN_S, vmins, tcg_gen_gvec_smin)
++DO_2OP_VEC(VMIN_U, vminu, tcg_gen_gvec_umin)
+ DO_2OP(VABD_S, vabds)
+ DO_2OP(VABD_U, vabdu)
+ DO_2OP(VHADD_S, vhadds)
+--
+.20.1

-New patch
+[PULL 21/27] target/arm: Optimize MVE VNEG, VABS
+Optimize the MVE VNEG and VABS insns by using TCG
+vector ops when possible.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210913095440.13462-7-peter.maydell@linaro.org
+---
+ target/arm/translate-mve.c | 32 ++++++++++++++++++++++----------
+file changed, 22 insertions(+), 10 deletions(-)
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-mve.c
++++ b/target/arm/translate-mve.c
+@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
+     return true;
+ }
+-static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn)
++static bool do_1op_vec(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn,
++                       GVecGen2Fn vecfn)
+ {
+     TCGv_ptr qd, qm;
+@@ -XXX,XX +XXX,XX @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn)
+         return true;
+     }
+-    qd = mve_qreg_ptr(a->qd);
+-    qm = mve_qreg_ptr(a->qm);
+-    fn(cpu_env, qd, qm);
+-    tcg_temp_free_ptr(qd);
+-    tcg_temp_free_ptr(qm);
++    if (vecfn && mve_no_predication(s)) {
++        vecfn(a->size, mve_qreg_offset(a->qd), mve_qreg_offset(a->qm), 16, 16);
++    } else {
++        qd = mve_qreg_ptr(a->qd);
++        qm = mve_qreg_ptr(a->qm);
++        fn(cpu_env, qd, qm);
++        tcg_temp_free_ptr(qd);
++        tcg_temp_free_ptr(qm);
++    }
+     mve_update_eci(s);
+     return true;
+ }
+-#define DO_1OP(INSN, FN)                                        \
++static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn)
++{
++    return do_1op_vec(s, a, fn, NULL);
++}
++
++#define DO_1OP_VEC(INSN, FN, VECFN)                             \
+     static bool trans_##INSN(DisasContext *s, arg_1op *a)       \
+     {                                                           \
+         static MVEGenOneOpFn * const fns[] = {                  \
+@@ -XXX,XX +XXX,XX @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn)
+             gen_helper_mve_##FN##w,                             \
+             NULL,                                               \
+         };                                                      \
+-        return do_1op(s, a, fns[a->size]);                      \
++        return do_1op_vec(s, a, fns[a->size], VECFN);           \
+     }
++#define DO_1OP(INSN, FN) DO_1OP_VEC(INSN, FN, NULL)
++
+ DO_1OP(VCLZ, vclz)
+ DO_1OP(VCLS, vcls)
+-DO_1OP(VABS, vabs)
+-DO_1OP(VNEG, vneg)
++DO_1OP_VEC(VABS, vabs, tcg_gen_gvec_abs)
++DO_1OP_VEC(VNEG, vneg, tcg_gen_gvec_neg)
+ DO_1OP(VQABS, vqabs)
+ DO_1OP(VQNEG, vqneg)
+ DO_1OP(VMAXA, vmaxa)
+--
+.20.1

-New patch
+[PULL 22/27] target/arm: Optimize MVE VDUP
+Optimize the MVE VDUP insns by using TCG vector ops when possible.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210913095440.13462-8-peter.maydell@linaro.org
+---
+ target/arm/translate-mve.c | 12 ++++++++----
+file changed, 8 insertions(+), 4 deletions(-)
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-mve.c
++++ b/target/arm/translate-mve.c
+@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
+         return true;
+     }
+-    qd = mve_qreg_ptr(a->qd);
+     rt = load_reg(s, a->rt);
+-    tcg_gen_dup_i32(a->size, rt, rt);
+-    gen_helper_mve_vdup(cpu_env, qd, rt);
+-    tcg_temp_free_ptr(qd);
++    if (mve_no_predication(s)) {
++        tcg_gen_gvec_dup_i32(a->size, mve_qreg_offset(a->qd), 16, 16, rt);
++    } else {
++        qd = mve_qreg_ptr(a->qd);
++        tcg_gen_dup_i32(a->size, rt, rt);
++        gen_helper_mve_vdup(cpu_env, qd, rt);
++        tcg_temp_free_ptr(qd);
++    }
+     tcg_temp_free_i32(rt);
+     mve_update_eci(s);
+     return true;
+--
+.20.1

-New patch
+[PULL 23/27] target/arm: Optimize MVE VMVN
+Optimize the MVE VMVN insn by using TCG vector ops when possible.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210913095440.13462-9-peter.maydell@linaro.org
+---
+ target/arm/translate-mve.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-mve.c
++++ b/target/arm/translate-mve.c
+@@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_1op *a)
+ static bool trans_VMVN(DisasContext *s, arg_1op *a)
+ {
+-    return do_1op(s, a, gen_helper_mve_vmvn);
++    return do_1op_vec(s, a, gen_helper_mve_vmvn, tcg_gen_gvec_not);
+ }
+ static bool trans_VABS_fp(DisasContext *s, arg_1op *a)
+--
+.20.1

-New patch
+[PULL 24/27] target/arm: Optimize MVE VSHL, VSHR immediate forms
+Optimize the MVE VSHL and VSHR immediate forms by using TCG vector
+ops when possible.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210913095440.13462-10-peter.maydell@linaro.org
+---
+ target/arm/translate-mve.c | 83 +++++++++++++++++++++++++++++---------
+file changed, 63 insertions(+), 20 deletions(-)
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-mve.c
++++ b/target/arm/translate-mve.c
+@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
+     return do_1imm(s, a, fn);
+ }
+-static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
+-                      bool negateshift)
++static bool do_2shift_vec(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
++                          bool negateshift, GVecGen2iFn vecfn)
+ {
+     TCGv_ptr qd, qm;
+     int shift = a->shift;
+@@ -XXX,XX +XXX,XX @@ static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
+         shift = -shift;
+     }
+-    qd = mve_qreg_ptr(a->qd);
+-    qm = mve_qreg_ptr(a->qm);
+-    fn(cpu_env, qd, qm, tcg_constant_i32(shift));
+-    tcg_temp_free_ptr(qd);
+-    tcg_temp_free_ptr(qm);
++    if (vecfn && mve_no_predication(s)) {
++        vecfn(a->size, mve_qreg_offset(a->qd), mve_qreg_offset(a->qm),
++              shift, 16, 16);
++    } else {
++        qd = mve_qreg_ptr(a->qd);
++        qm = mve_qreg_ptr(a->qm);
++        fn(cpu_env, qd, qm, tcg_constant_i32(shift));
++        tcg_temp_free_ptr(qd);
++        tcg_temp_free_ptr(qm);
++    }
+     mve_update_eci(s);
+     return true;
+ }
+-#define DO_2SHIFT(INSN, FN, NEGATESHIFT)                         \
+-    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
+-    {                                                           \
+-        static MVEGenTwoOpShiftFn * const fns[] = {             \
+-            gen_helper_mve_##FN##b,                             \
+-            gen_helper_mve_##FN##h,                             \
+-            gen_helper_mve_##FN##w,                             \
+-            NULL,                                               \
+-        };                                                      \
+-        return do_2shift(s, a, fns[a->size], NEGATESHIFT);      \
++static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
++                      bool negateshift)
++{
++    return do_2shift_vec(s, a, fn, negateshift, NULL);
++}
++
++#define DO_2SHIFT_VEC(INSN, FN, NEGATESHIFT, VECFN)                     \
++    static bool trans_##INSN(DisasContext *s, arg_2shift *a)            \
++    {                                                                   \
++        static MVEGenTwoOpShiftFn * const fns[] = {                     \
++            gen_helper_mve_##FN##b,                                     \
++            gen_helper_mve_##FN##h,                                     \
++            gen_helper_mve_##FN##w,                                     \
++            NULL,                                                       \
++        };                                                              \
++        return do_2shift_vec(s, a, fns[a->size], NEGATESHIFT, VECFN);   \
+     }
+-DO_2SHIFT(VSHLI, vshli_u, false)
++#define DO_2SHIFT(INSN, FN, NEGATESHIFT)        \
++    DO_2SHIFT_VEC(INSN, FN, NEGATESHIFT, NULL)
++
++static void do_gvec_shri_s(unsigned vece, uint32_t dofs, uint32_t aofs,
++                           int64_t shift, uint32_t oprsz, uint32_t maxsz)
++{
++    /*
++     * We get here with a negated shift count, and we must handle
++     * shifts by the element size, which tcg_gen_gvec_sari() does not do.
++     */
++    shift = -shift;
++    if (shift == (8 << vece)) {
++        shift--;
++    }
++    tcg_gen_gvec_sari(vece, dofs, aofs, shift, oprsz, maxsz);
++}
++
++static void do_gvec_shri_u(unsigned vece, uint32_t dofs, uint32_t aofs,
++                           int64_t shift, uint32_t oprsz, uint32_t maxsz)
++{
++    /*
++     * We get here with a negated shift count, and we must handle
++     * shifts by the element size, which tcg_gen_gvec_shri() does not do.
++     */
++    shift = -shift;
++    if (shift == (8 << vece)) {
++        tcg_gen_gvec_dup_imm(vece, dofs, oprsz, maxsz, 0);
++    } else {
++        tcg_gen_gvec_shri(vece, dofs, aofs, shift, oprsz, maxsz);
++    }
++}
++
++DO_2SHIFT_VEC(VSHLI, vshli_u, false, tcg_gen_gvec_shli)
+ DO_2SHIFT(VQSHLI_S, vqshli_s, false)
+ DO_2SHIFT(VQSHLI_U, vqshli_u, false)
+ DO_2SHIFT(VQSHLUI, vqshlui_s, false)
+ /* These right shifts use a left-shift helper with negated shift count */
+-DO_2SHIFT(VSHRI_S, vshli_s, true)
+-DO_2SHIFT(VSHRI_U, vshli_u, true)
++DO_2SHIFT_VEC(VSHRI_S, vshli_s, true, do_gvec_shri_s)
++DO_2SHIFT_VEC(VSHRI_U, vshli_u, true, do_gvec_shri_u)
+ DO_2SHIFT(VRSHRI_S, vrshli_s, true)
+ DO_2SHIFT(VRSHRI_U, vrshli_u, true)
+--
+.20.1

-New patch
+[PULL 25/27] target/arm: Optimize MVE VSHLL and VMOVL
+Optimize the MVE VSHLL insns by using TCG vector ops when possible.
+This includes the VMOVL insn, which we handle in mve.decode as "VSHLL
+with zero shift count".
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210913095440.13462-11-peter.maydell@linaro.org
+---
+ target/arm/translate-mve.c | 67 +++++++++++++++++++++++++++++++++-----
+file changed, 59 insertions(+), 8 deletions(-)
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-mve.c
++++ b/target/arm/translate-mve.c
+@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SCALAR(VQSHL_U_scalar, vqshli_u)
+ DO_2SHIFT_SCALAR(VQRSHL_S_scalar, vqrshli_s)
+ DO_2SHIFT_SCALAR(VQRSHL_U_scalar, vqrshli_u)
+-#define DO_VSHLL(INSN, FN)                                      \
+-    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
+-    {                                                           \
+-        static MVEGenTwoOpShiftFn * const fns[] = {             \
+-            gen_helper_mve_##FN##b,                             \
+-            gen_helper_mve_##FN##h,                             \
+-        };                                                      \
+-        return do_2shift(s, a, fns[a->size], false);            \
++#define DO_VSHLL(INSN, FN)                                              \
++    static bool trans_##INSN(DisasContext *s, arg_2shift *a)            \
++    {                                                                   \
++        static MVEGenTwoOpShiftFn * const fns[] = {                     \
++            gen_helper_mve_##FN##b,                                     \
++            gen_helper_mve_##FN##h,                                     \
++        };                                                              \
++        return do_2shift_vec(s, a, fns[a->size], false, do_gvec_##FN);  \
+     }
++/*
++ * For the VSHLL vector helpers, the vece is the size of the input
++ * (ie MO_8 or MO_16); the helpers want to work in the output size.
++ * The shift count can be 0..<input size>, inclusive. (0 is VMOVL.)
++ */
++static void do_gvec_vshllbs(unsigned vece, uint32_t dofs, uint32_t aofs,
++                            int64_t shift, uint32_t oprsz, uint32_t maxsz)
++{
++    unsigned ovece = vece + 1;
++    unsigned ibits = vece == MO_8 ? 8 : 16;
++    tcg_gen_gvec_shli(ovece, dofs, aofs, ibits, oprsz, maxsz);
++    tcg_gen_gvec_sari(ovece, dofs, dofs, ibits - shift, oprsz, maxsz);
++}
++
++static void do_gvec_vshllbu(unsigned vece, uint32_t dofs, uint32_t aofs,
++                            int64_t shift, uint32_t oprsz, uint32_t maxsz)
++{
++    unsigned ovece = vece + 1;
++    tcg_gen_gvec_andi(ovece, dofs, aofs,
++                      ovece == MO_16 ? 0xff : 0xffff, oprsz, maxsz);
++    tcg_gen_gvec_shli(ovece, dofs, dofs, shift, oprsz, maxsz);
++}
++
++static void do_gvec_vshllts(unsigned vece, uint32_t dofs, uint32_t aofs,
++                            int64_t shift, uint32_t oprsz, uint32_t maxsz)
++{
++    unsigned ovece = vece + 1;
++    unsigned ibits = vece == MO_8 ? 8 : 16;
++    if (shift == 0) {
++        tcg_gen_gvec_sari(ovece, dofs, aofs, ibits, oprsz, maxsz);
++    } else {
++        tcg_gen_gvec_andi(ovece, dofs, aofs,
++                          ovece == MO_16 ? 0xff00 : 0xffff0000, oprsz, maxsz);
++        tcg_gen_gvec_sari(ovece, dofs, dofs, ibits - shift, oprsz, maxsz);
++    }
++}
++
++static void do_gvec_vshlltu(unsigned vece, uint32_t dofs, uint32_t aofs,
++                            int64_t shift, uint32_t oprsz, uint32_t maxsz)
++{
++    unsigned ovece = vece + 1;
++    unsigned ibits = vece == MO_8 ? 8 : 16;
++    if (shift == 0) {
++        tcg_gen_gvec_shri(ovece, dofs, aofs, ibits, oprsz, maxsz);
++    } else {
++        tcg_gen_gvec_andi(ovece, dofs, aofs,
++                          ovece == MO_16 ? 0xff00 : 0xffff0000, oprsz, maxsz);
++        tcg_gen_gvec_shri(ovece, dofs, dofs, ibits - shift, oprsz, maxsz);
++    }
++}
++
+ DO_VSHLL(VSHLL_BS, vshllbs)
+ DO_VSHLL(VSHLL_BU, vshllbu)
+ DO_VSHLL(VSHLL_TS, vshllts)
+--
+.20.1

-New patch
+[PULL 26/27] target/arm: Optimize MVE VSLI and VSRI
+Optimize the MVE shift-and-insert insns by using TCG
+vector ops when possible.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210913095440.13462-12-peter.maydell@linaro.org
+---
+ target/arm/translate-mve.c | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-mve.c
++++ b/target/arm/translate-mve.c
+@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_VEC(VSHRI_U, vshli_u, true, do_gvec_shri_u)
+ DO_2SHIFT(VRSHRI_S, vrshli_s, true)
+ DO_2SHIFT(VRSHRI_U, vrshli_u, true)
+-DO_2SHIFT(VSRI, vsri, false)
+-DO_2SHIFT(VSLI, vsli, false)
++DO_2SHIFT_VEC(VSRI, vsri, false, gen_gvec_sri)
++DO_2SHIFT_VEC(VSLI, vsli, false, gen_gvec_sli)
+ #define DO_2SHIFT_FP(INSN, FN)                                  \
+     static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
+--
+.20.1

-[Qemu-devel] [PULL 10/10] target/arm: NS BusFault on vector table fetch escalates to NS HardFault
+[PULL 27/27] target/arm: Optimize MVE 1op-immediate insns
-In the M-profile architecture, when we do a vector table fetch and it
+Optimize the MVE 1op-immediate insns (VORR, VBIC, VMOV) to
-fails, we need to report a HardFault.  Whether this is a Secure HF or
+use TCG vector ops when possible.
 a NonSecure HF depends on several things.  If AIRCR.BFHFNMINS is 0
 then HF is always Secure, because there is no NonSecure HardFault.
 Otherwise, the answer depends on whether the 'underlying exception'
 (MemManage, BusFault, SecureFault) targets Secure or NonSecure.  (In
 the pseudocode, this is handled in the Vector() function: the final
 exc.isSecure is calculated by looking at the exc.isSecure from the
 exception returned from the memory access, not the isSecure input
 argument.)
 We weren't doing this correctly, because we were looking at
 the target security domain of the exception we were trying to
 load the vector table entry for. This produces errors of two kinds:
  * a load from the NS vector table which hits the "NS access
    to S memory" SecureFault should end up as a Secure HardFault,
    but we were raising an NS HardFault
  * a load from the S vector table which causes a BusFault
    should raise an NS HardFault if BFHFNMINS == 1 (because
    in that case all BusFaults are NonSecure), but we were raising
    a Secure HardFault
 Correct the logic.
 We also fix a comment error where we claimed that we might
 be escalating MemManage to HardFault, and forgot about SecureFault.
 (Vector loads can never hit MPU access faults, because they're
 always aligned and always use the default address map.)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20190705094823.28905-1-peter.maydell@linaro.org
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20210913095440.13462-13-peter.maydell@linaro.org
 ---
- target/arm/m_helper.c | 21 +++++++++++++++++----
+ target/arm/translate-mve.c | 26 +++++++++++++++++++++-----
-file changed, 17 insertions(+), 4 deletions(-)
+file changed, 21 insertions(+), 5 deletions(-)
-diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/m_helper.c
+--- a/target/arm/translate-mve.c
-+++ b/target/arm/m_helper.c
++++ b/target/arm/translate-mve.c
-@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
+@@ -XXX,XX +XXX,XX @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
-         if (sattrs.ns) {
+     return true;
-             attrs.secure = false;
+ }
-         } else if (!targets_secure) {
--            /* NS access to S memory */
+-static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
-+            /*
++static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn,
-+             * NS access to S memory: the underlying exception which we escalate
++                    GVecGen2iFn *vecfn)
-+             * to HardFault is SecureFault, which always targets Secure.
+ {
-+             */
+     TCGv_ptr qd;
-+            exc_secure = true;
+     uint64_t imm;
-             goto load_fail;
+@@ -XXX,XX +XXX,XX @@ static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
      imm = asimd_imm_const(a->imm, a->cmode, a->op);
 -    qd = mve_qreg_ptr(a->qd);
 -    fn(cpu_env, qd, tcg_constant_i64(imm));
 -    tcg_temp_free_ptr(qd);
 +    if (vecfn && mve_no_predication(s)) {
 +        vecfn(MO_64, mve_qreg_offset(a->qd), mve_qreg_offset(a->qd),
 +              imm, 16, 16);
 +    } else {
 +        qd = mve_qreg_ptr(a->qd);
 +        fn(cpu_env, qd, tcg_constant_i64(imm));
 +        tcg_temp_free_ptr(qd);
 +    }
      mve_update_eci(s);
      return true;
  }
 +static void gen_gvec_vmovi(unsigned vece, uint32_t dofs, uint32_t aofs,
 +                           int64_t c, uint32_t oprsz, uint32_t maxsz)
 +{
 +    tcg_gen_gvec_dup_imm(vece, dofs, oprsz, maxsz, c);
 +}
 +
  static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
  {
      /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
      MVEGenOneOpImmFn *fn;
 +    GVecGen2iFn *vecfn;
      if ((a->cmode & 1) && a->cmode < 12) {
          if (a->op) {
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
               * so the VBIC becomes a logical AND operation.
               */
              fn = gen_helper_mve_vandi;
 +            vecfn = tcg_gen_gvec_andi;
          } else {
              fn = gen_helper_mve_vorri;
 +            vecfn = tcg_gen_gvec_ori;
          }
+     } else {
+         /* There is one unallocated cmode/op combination in this space */
+@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
+         }
+         /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
+         fn = gen_helper_mve_vmovi;
++        vecfn = gen_gvec_vmovi;
      }
-@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
+-    return do_1imm(s, a, fn);
-     vector_entry = address_space_ldl(arm_addressspace(cs, attrs), addr,
++    return do_1imm(s, a, fn, vecfn);
-                                      attrs, &result);
+ }
-     if (result != MEMTX_OK) {
-+        /*
+ static bool do_2shift_vec(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
 +         * Underlying exception is BusFault: its target security state
 +         * depends on BFHFNMINS.
 +         */
 +        exc_secure = !(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
          goto load_fail;
      }
      *pvec = vector_entry;
@@ -XXX,XX +XXX,XX @@ load_fail:
      /*
       * All vector table fetch fails are reported as HardFault, with
       * HFSR.VECTTBL and .FORCED set. (FORCED is set because
 -     * technically the underlying exception is a MemManage or BusFault
 +     * technically the underlying exception is a SecureFault or BusFault
       * that is escalated to HardFault.) This is a terminal exception,
       * so we will either take the HardFault immediately or else enter
       * lockup (the latter case is handled in armv7m_nvic_set_pending_derived()).
 +     * The HardFault is Secure if BFHFNMINS is 0 (meaning that all HFs are
 +     * secure); otherwise it targets the same security state as the
 +     * underlying exception.
       */
 -    exc_secure = targets_secure ||
 -        !(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
 +    if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
 +        exc_secure = true;
 +    }
      env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK | R_V7M_HFSR_FORCED_MASK;
      armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secure);
      return false;
 --
 .20.1

target-arm queue for rc1 -- these are all bug fixes.

thanks
-- PMM

The following changes since commit b9404bf592e7ba74180e1a54ed7a266ec6ee67f2:

Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20190715' into staging (2019-07-15 12:22:07 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190715

for you to fetch changes up to 51c9122e92b776a3f16af0b9282f1dc5012e2a19:

target/arm: NS BusFault on vector table fetch escalates to NS HardFault (2019-07-15 14:17:04 +0100)

----------------------------------------------------------------
target-arm queue:
 * report ARMv8-A FP support for AArch32 -cpu max
 * hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
 * hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
 * hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
 * hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
 * hw/arm/virt: Fix non-secure flash mode
 * pl031: Correctly migrate state when using -rtc clock=host
 * fix regression that meant arm926 and arm1026 lost VFP
   double-precision support
 * v8M: NS BusFault on vector table fetch escalates to NS HardFault

----------------------------------------------------------------
Alex Bennée (1):
      target/arm: report ARMv8-A FP support for AArch32 -cpu max

David Engraf (1):
      hw/arm/virt: Fix non-secure flash mode

Peter Maydell (3):
      pl031: Correctly migrate state when using -rtc clock=host
      target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026
      target/arm: NS BusFault on vector table fetch escalates to NS HardFault

Philippe Mathieu-Daudé (5):
      hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs
      hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
      hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
      hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
      hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO

From: Alex Bennée <alex.bennee@linaro.org>

When we converted to using feature bits in 602f6e42cfbf we missed out
the fact (dp && arm_dc_feature(s, ARM_FEATURE_V8)) was supported for
-cpu max configurations. This caused a regression in the GCC test
suite. Fix this by setting the appropriate bits in mvfr1.FPHP to
report ARMv8-A with FP support (but not ARMv8.2-FP16).

Fixes: https://bugs.launchpad.net/qemu/+bug/1836078
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190711103737.10017-1-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
             t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
             cpu->isar.id_isar6 = t;
 
+            t = cpu->isar.mvfr1;
+            t = FIELD_DP32(t, MVFR1, FPHP, 2);     /* v8.0 FP support */
+            cpu->isar.mvfr1 = t;
+
             t = cpu->isar.mvfr2;
             t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
             t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

In the next commit we will implement the write_with_attrs()
handler. To avoid using different APIs, convert the read()
handler first.

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/ssi/xilinx_spips.c | 23 +++++++++++------------
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -XXX,XX +XXX,XX @@ static void lqspi_load_cache(void *opaque, hwaddr addr)
     }
 }
 
-static uint64_t
-lqspi_read(void *opaque, hwaddr addr, unsigned int size)
+static MemTxResult lqspi_read(void *opaque, hwaddr addr, uint64_t *value,
+                              unsigned size, MemTxAttrs attrs)
 {
-    XilinxQSPIPS *q = opaque;
-    uint32_t ret;
+    XilinxQSPIPS *q = XILINX_QSPIPS(opaque);
 
     if (addr >= q->lqspi_cached_addr &&
             addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
         uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr];
-        ret = cpu_to_le32(*(uint32_t *)retp);
-        DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr,
-                   (unsigned)ret);
-        return ret;
-    } else {
-        lqspi_load_cache(opaque, addr);
-        return lqspi_read(opaque, addr, size);
+        *value = cpu_to_le32(*(uint32_t *)retp);
+        DB_PRINT_L(1, "addr: %08" HWADDR_PRIx ", data: %08" PRIx64 "\n",
+                   addr, *value);
+        return MEMTX_OK;
     }
+
+    lqspi_load_cache(opaque, addr);
+    return lqspi_read(opaque, addr, value, size, attrs);
 }
 
 static const MemoryRegionOps lqspi_ops = {
-    .read = lqspi_read,
+    .read_with_attrs = lqspi_read,
     .endianness = DEVICE_NATIVE_ENDIAN,
     .valid = {
         .min_access_size = 1,
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

Lei Sun found while auditing the code that a CPU write would
trigger a NULL pointer dereference.

>From UG1085 datasheet [*] AXI writes in this region are ignored
and generates an AXI Slave Error (SLVERR).

Fix by implementing the write_with_attrs() handler.
Return MEMTX_ERROR when the region is accessed (this error maps
to an AXI slave error).

[*] https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

Reported-by: Lei Sun <slei.casper@gmail.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/ssi/xilinx_spips.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -XXX,XX +XXX,XX @@ static MemTxResult lqspi_read(void *opaque, hwaddr addr, uint64_t *value,
     return lqspi_read(opaque, addr, value, size, attrs);
 }
 
+static MemTxResult lqspi_write(void *opaque, hwaddr offset, uint64_t value,
+                               unsigned size, MemTxAttrs attrs)
+{
+    /*
+     * From UG1085, Chapter 24 (Quad-SPI controllers):
+     * - Writes are ignored
+     * - AXI writes generate an external AXI slave error (SLVERR)
+     */
+    qemu_log_mask(LOG_GUEST_ERROR, "%s Unexpected %u-bit access to 0x%" PRIx64
+                                   " (value: 0x%" PRIx64 "\n",
+                  __func__, size << 3, offset, value);
+
+    return MEMTX_ERROR;
+}
+
 static const MemoryRegionOps lqspi_ops = {
     .read_with_attrs = lqspi_read,
+    .write_with_attrs = lqspi_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
     .valid = {
         .min_access_size = 1,
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

Both lqspi_read() and lqspi_load_cache() expect a 32-bit
aligned address.

>From UG1085 datasheet [*] chapter on 'Quad-SPI Controller':

Transfer Size Limitations

Because of the 32-bit wide TX, RX, and generic FIFO, all
    APB/AXI transfers must be an integer multiple of 4-bytes.
    Shorter transfers are not possible.

Set MemoryRegionOps.impl values to force 32-bit accesses,
this way we are sure we do not access the lqspi_buf[] array
out of bound.

[*] https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps lqspi_ops = {
     .read_with_attrs = lqspi_read,
     .write_with_attrs = lqspi_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
     .valid = {
         .min_access_size = 1,
         .max_access_size = 4
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

Reading the RX_DATA register when the RX_FIFO is empty triggers
an abort. This can be easily reproduced:

$ qemu-system-arm -M emcraft-sf2 -monitor stdio -S
  QEMU 4.0.50 monitor - type 'help' for more information
  (qemu) x 0x40001010
  Aborted (core dumped)

(gdb) bt
  #1  0x00007f035874f895 in abort () at /lib64/libc.so.6
  #2  0x00005628686591ff in fifo8_pop (fifo=0x56286a9a4c68) at util/fifo8.c:66
  #3  0x00005628683e0b8e in fifo32_pop (fifo=0x56286a9a4c68) at include/qemu/fifo32.h:137
  #4  0x00005628683e0efb in spi_read (opaque=0x56286a9a4850, addr=4, size=4) at hw/ssi/mss-spi.c:168
  #5  0x0000562867f96801 in memory_region_read_accessor (mr=0x56286a9a4b60, addr=16, value=0x7ffeecb0c5c8, size=4, shift=0, mask=4294967295, attrs=...) at memory.c:439
  #6  0x0000562867f96cdb in access_with_adjusted_size (addr=16, value=0x7ffeecb0c5c8, size=4, access_size_min=1, access_size_max=4, access_fn=0x562867f967c3 <memory_region_read_accessor>, mr=0x56286a9a4b60, attrs=...) at memory.c:569
  #7  0x0000562867f99940 in memory_region_dispatch_read1 (mr=0x56286a9a4b60, addr=16, pval=0x7ffeecb0c5c8, size=4, attrs=...) at memory.c:1420
  #8  0x0000562867f99a08 in memory_region_dispatch_read (mr=0x56286a9a4b60, addr=16, pval=0x7ffeecb0c5c8, size=4, attrs=...) at memory.c:1447
  #9  0x0000562867f38721 in flatview_read_continue (fv=0x56286aec6360, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4, addr1=16, l=4, mr=0x56286a9a4b60) at exec.c:3385
  #10 0x0000562867f38874 in flatview_read (fv=0x56286aec6360, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4) at exec.c:3423
  #11 0x0000562867f388ea in address_space_read_full (as=0x56286aa3e890, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4) at exec.c:3436
  #12 0x0000562867f389c5 in address_space_rw (as=0x56286aa3e890, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4, is_write=false) at exec.c:3466
  #13 0x0000562867f3bdd7 in cpu_memory_rw_debug (cpu=0x56286aa19d00, addr=1073745936, buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4, is_write=0) at exec.c:3976
  #14 0x000056286811ed51 in memory_dump (mon=0x56286a8c32d0, count=1, format=120, wsize=4, addr=1073745936, is_physical=0) at monitor/misc.c:730
  #15 0x000056286811eff1 in hmp_memory_dump (mon=0x56286a8c32d0, qdict=0x56286b15c400) at monitor/misc.c:785
  #16 0x00005628684740ee in handle_hmp_command (mon=0x56286a8c32d0, cmdline=0x56286a8caeb2 "0x40001010") at monitor/hmp.c:1082

From the datasheet "Actel SmartFusion Microcontroller Subsystem
User's Guide" Rev.1, Table 13-3 "SPI Register Summary", this
register has a reset value of 0.

Check the FIFO is not empty before accessing it, else log an
error message.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20190709113715.7761-3-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/ssi/mss-spi.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/mss-spi.c
+++ b/hw/ssi/mss-spi.c
@@ -XXX,XX +XXX,XX @@ spi_read(void *opaque, hwaddr addr, unsigned int size)
     case R_SPI_RX:
         s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
         s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF;
-        ret = fifo32_pop(&s->rx_fifo);
+        if (fifo32_is_empty(&s->rx_fifo)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: Reading empty RX_FIFO\n",
+                          __func__);
+        } else {
+            ret = fifo32_pop(&s->rx_fifo);
+        }
         if (fifo32_is_empty(&s->rx_fifo)) {
             s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
         }
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

In the previous commit we fixed a crash when the guest read a
register that pop from an empty FIFO.
By auditing the repository, we found another similar use with
an easy way to reproduce:

$ qemu-system-aarch64 -M xlnx-zcu102 -monitor stdio -S
  QEMU 4.0.50 monitor - type 'help' for more information
  (qemu) xp/b 0xfd4a0134
  Aborted (core dumped)

(gdb) bt
  #0  0x00007f6936dea57f in raise () at /lib64/libc.so.6
  #1  0x00007f6936dd4895 in abort () at /lib64/libc.so.6
  #2  0x0000561ad32975ec in xlnx_dp_aux_pop_rx_fifo (s=0x7f692babee70) at hw/display/xlnx_dp.c:431
  #3  0x0000561ad3297dc0 in xlnx_dp_read (opaque=0x7f692babee70, offset=77, size=4) at hw/display/xlnx_dp.c:667
  #4  0x0000561ad321b896 in memory_region_read_accessor (mr=0x7f692babf620, addr=308, value=0x7ffe05c1db88, size=4, shift=0, mask=4294967295, attrs=...) at memory.c:439
  #5  0x0000561ad321bd70 in access_with_adjusted_size (addr=308, value=0x7ffe05c1db88, size=1, access_size_min=4, access_size_max=4, access_fn=0x561ad321b858 <memory_region_read_accessor>, mr=0x7f692babf620, attrs=...) at memory.c:569
  #6  0x0000561ad321e9d5 in memory_region_dispatch_read1 (mr=0x7f692babf620, addr=308, pval=0x7ffe05c1db88, size=1, attrs=...) at memory.c:1420
  #7  0x0000561ad321ea9d in memory_region_dispatch_read (mr=0x7f692babf620, addr=308, pval=0x7ffe05c1db88, size=1, attrs=...) at memory.c:1447
  #8  0x0000561ad31bd742 in flatview_read_continue (fv=0x561ad69c04f0, addr=4249485620, attrs=..., buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", len=1, addr1=308, l=1, mr=0x7f692babf620) at exec.c:3385
  #9  0x0000561ad31bd895 in flatview_read (fv=0x561ad69c04f0, addr=4249485620, attrs=..., buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", len=1) at exec.c:3423
  #10 0x0000561ad31bd90b in address_space_read_full (as=0x561ad5bb3020, addr=4249485620, attrs=..., buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", len=1) at exec.c:3436
  #11 0x0000561ad33b1c42 in address_space_read (len=1, buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", attrs=..., addr=4249485620, as=0x561ad5bb3020) at include/exec/memory.h:2131
  #12 0x0000561ad33b1c42 in memory_dump (mon=0x561ad59c4530, count=1, format=120, wsize=1, addr=4249485620, is_physical=1) at monitor/misc.c:723
  #13 0x0000561ad33b1fc1 in hmp_physical_memory_dump (mon=0x561ad59c4530, qdict=0x561ad6c6fd00) at monitor/misc.c:795
  #14 0x0000561ad37b4a9f in handle_hmp_command (mon=0x561ad59c4530, cmdline=0x561ad59d0f22 "/b 0x00000000fd4a0134") at monitor/hmp.c:1082

Fix by checking the FIFO is not empty before popping from it.

The datasheet is not clear about the reset value of this register,
we choose to return '0'.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20190709113715.7761-4-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/display/xlnx_dp.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/xlnx_dp.c
+++ b/hw/display/xlnx_dp.c
@@ -XXX,XX +XXX,XX @@ static uint8_t xlnx_dp_aux_pop_rx_fifo(XlnxDPState *s)
     uint8_t ret;
 
     if (fifo8_is_empty(&s->rx_fifo)) {
-        DPRINTF("rx_fifo underflow..\n");
-        abort();
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Reading empty RX_FIFO\n",
+                      __func__);
+        /*
+         * The datasheet is not clear about the reset value, it seems
+         * to be unspecified. We choose to return '0'.
+         */
+        ret = 0;
+    } else {
+        ret = fifo8_pop(&s->rx_fifo);
+        DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret);
     }
-    ret = fifo8_pop(&s->rx_fifo);
-    DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret);
     return ret;
 }
 
-- 
2.20.1

From: David Engraf <david.engraf@sysgo.com>

Using the whole 128 MiB flash in non-secure mode is not working because
virt_flash_fdt() expects the same address for secure_sysmem and sysmem.
This is not correctly handled by caller because it forwards NULL for
secure_sysmem in non-secure flash mode.

Fixed by using sysmem when secure_sysmem is NULL.

Signed-off-by: David Engraf <david.engraf@sysgo.com>
Message-id: 20190712075002.14326-1-david.engraf@sysgo.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
                                     &machine->device_memory->mr);
     }
 
-    virt_flash_fdt(vms, sysmem, secure_sysmem);
+    virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
 
     create_gic(vms, pic);
 
-- 
2.20.1

The PL031 RTC tracks the difference between the guest RTC
and the host RTC using a tick_offset field. For migration,
however, we currently always migrate the offset between
the guest and the vm_clock, even if the RTC clock is not
the same as the vm_clock; this was an attempt to retain
migration backwards compatibility.

Unfortunately this results in the RTC behaving oddly across
a VM state save and restore -- since the VM clock stands still
across save-then-restore, regardless of how much real world
time has elapsed, the guest RTC ends up out of sync with the
host RTC in the restored VM.

Fix this by migrating the raw tick_offset. To retain migration
compatibility as far as possible, we have a new property
migrate-tick-offset; by default this is 'true' and we will
migrate the true tick offset in a new subsection; if the
incoming data has no subsection we fall back to the old
vm_clock-based offset information, so old->new migration
compatibility is preserved. For complete new->old migration
compatibility, the property is set to 'false' for 4.0 and
earlier machine types (this will only affect 'virt-4.0'
and below, as none of the other pl031-using machines are
versioned).

Reported-by: Russell King <rmk@armlinux.org.uk>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-id: 20190709143912.28905-1-peter.maydell@linaro.org
---
 include/hw/timer/pl031.h |  2 +
 hw/core/machine.c        |  1 +
 hw/timer/pl031.c         | 92 ++++++++++++++++++++++++++++++++++++++--
 3 files changed, 91 insertions(+), 4 deletions(-)

diff --git a/include/hw/timer/pl031.h b/include/hw/timer/pl031.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/timer/pl031.h
+++ b/include/hw/timer/pl031.h
@@ -XXX,XX +XXX,XX @@ typedef struct PL031State {
      */
     uint32_t tick_offset_vmstate;
     uint32_t tick_offset;
+    bool tick_offset_migrated;
+    bool migrate_tick_offset;
 
     uint32_t mr;
     uint32_t lr;
diff --git a/hw/core/machine.c b/hw/core/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -XXX,XX +XXX,XX @@ GlobalProperty hw_compat_4_0[] = {
     { "virtio-gpu-pci", "edid", "false" },
     { "virtio-device", "use-started", "false" },
     { "virtio-balloon-device", "qemu-4-0-config-size", "true" },
+    { "pl031", "migrate-tick-offset", "false" },
 };
 const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0);
 
diff --git a/hw/timer/pl031.c b/hw/timer/pl031.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/pl031.c
+++ b/hw/timer/pl031.c
@@ -XXX,XX +XXX,XX @@ static int pl031_pre_save(void *opaque)
 {
     PL031State *s = opaque;
 
-    /* tick_offset is base_time - rtc_clock base time.  Instead, we want to
-     * store the base time relative to the QEMU_CLOCK_VIRTUAL for backwards-compatibility.  */
+    /*
+     * The PL031 device model code uses the tick_offset field, which is
+     * the offset between what the guest RTC should read and what the
+     * QEMU rtc_clock reads:
+     *  guest_rtc = rtc_clock + tick_offset
+     * and so
+     *  tick_offset = guest_rtc - rtc_clock
+     *
+     * We want to migrate this offset, which sounds straightforward.
+     * Unfortunately older versions of QEMU migrated a conversion of this
+     * offset into an offset from the vm_clock. (This was in turn an
+     * attempt to be compatible with even older QEMU versions, but it
+     * has incorrect behaviour if the rtc_clock is not the same as the
+     * vm_clock.) So we put the actual tick_offset into a migration
+     * subsection, and the backwards-compatible time-relative-to-vm_clock
+     * in the main migration state.
+     *
+     * Calculate base time relative to QEMU_CLOCK_VIRTUAL:
+     */
     int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
     s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND;
 
     return 0;
 }
 
+static int pl031_pre_load(void *opaque)
+{
+    PL031State *s = opaque;
+
+    s->tick_offset_migrated = false;
+    return 0;
+}
+
 static int pl031_post_load(void *opaque, int version_id)
 {
     PL031State *s = opaque;
 
-    int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
-    s->tick_offset = s->tick_offset_vmstate - delta / NANOSECONDS_PER_SECOND;
+    /*
+     * If we got the tick_offset subsection, then we can just use
+     * the value in that. Otherwise the source is an older QEMU and
+     * has given us the offset from the vm_clock; convert it back to
+     * an offset from the rtc_clock. This will cause time to incorrectly
+     * go backwards compared to the host RTC, but this is unavoidable.
+     */
+
+    if (!s->tick_offset_migrated) {
+        int64_t delta = qemu_clock_get_ns(rtc_clock) -
+            qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+        s->tick_offset = s->tick_offset_vmstate -
+            delta / NANOSECONDS_PER_SECOND;
+    }
     pl031_set_alarm(s);
     return 0;
 }
 
+static int pl031_tick_offset_post_load(void *opaque, int version_id)
+{
+    PL031State *s = opaque;
+
+    s->tick_offset_migrated = true;
+    return 0;
+}
+
+static bool pl031_tick_offset_needed(void *opaque)
+{
+    PL031State *s = opaque;
+
+    return s->migrate_tick_offset;
+}
+
+static const VMStateDescription vmstate_pl031_tick_offset = {
+    .name = "pl031/tick-offset",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = pl031_tick_offset_needed,
+    .post_load = pl031_tick_offset_post_load,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(tick_offset, PL031State),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static const VMStateDescription vmstate_pl031 = {
     .name = "pl031",
     .version_id = 1,
     .minimum_version_id = 1,
     .pre_save = pl031_pre_save,
+    .pre_load = pl031_pre_load,
     .post_load = pl031_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(tick_offset_vmstate, PL031State),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl031 = {
         VMSTATE_UINT32(im, PL031State),
         VMSTATE_UINT32(is, PL031State),
         VMSTATE_END_OF_LIST()
+    },
+    .subsections = (const VMStateDescription*[]) {
+        &vmstate_pl031_tick_offset,
+        NULL
     }
 };
 
+static Property pl031_properties[] = {
+    /*
+     * True to correctly migrate the tick offset of the RTC. False to
+     * obtain backward migration compatibility with older QEMU versions,
+     * at the expense of the guest RTC going backwards compared with the
+     * host RTC when the VM is saved/restored if using -rtc host.
+     * (Even if set to 'true' older QEMU can migrate forward to newer QEMU;
+     * 'false' also permits newer QEMU to migrate to older QEMU.)
+     */
+    DEFINE_PROP_BOOL("migrate-tick-offset",
+                     PL031State, migrate_tick_offset, true),
+    DEFINE_PROP_END_OF_LIST()
+};
+
 static void pl031_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
 
     dc->vmsd = &vmstate_pl031;
+    dc->props = pl031_properties;
 }
 
 static const TypeInfo pl031_info = {
-- 
2.20.1

The ARMv5 architecture didn't specify detailed per-feature ID
registers. Now that we're using the MVFR0 register fields to
gate the existence of VFP instructions, we need to set up
the correct values in the cpu->isar structure so that we still
provide an FPU to the guest.

This fixes a regression in the arm926 and arm1026 CPUs, which
are the only ones that both have VFP and are ARMv5 or earlier.
This regression was introduced by the VFP refactoring, and more
specifically by commits 1120827fa182f0e76 and 266bd25c485597c,
which accidentally disabled VFP short-vector support and
double-precision support on these CPUs.

Fixes: 1120827fa182f0e
Fixes: 266bd25c485597c
Fixes: https://bugs.launchpad.net/qemu/+bug/1836192
Reported-by: Christophe Lyon <christophe.lyon@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Christophe Lyon <christophe.lyon@linaro.org>
Message-id: 20190711131241.22231-1-peter.maydell@linaro.org
---
 target/arm/cpu.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm926_initfn(Object *obj)
      * set the field to indicate Jazelle support within QEMU.
      */
     cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
+    /*
+     * Similarly, we need to set MVFR0 fields to enable double precision
+     * and short vector support even though ARMv5 doesn't have this register.
+     */
+    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
 }
 
 static void arm946_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void arm1026_initfn(Object *obj)
      * set the field to indicate Jazelle support within QEMU.
      */
     cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
+    /*
+     * Similarly, we need to set MVFR0 fields to enable double precision
+     * and short vector support even though ARMv5 doesn't have this register.
+     */
+    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
 
     {
         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
-- 
2.20.1

In the M-profile architecture, when we do a vector table fetch and it
fails, we need to report a HardFault.  Whether this is a Secure HF or
a NonSecure HF depends on several things.  If AIRCR.BFHFNMINS is 0
then HF is always Secure, because there is no NonSecure HardFault.
Otherwise, the answer depends on whether the 'underlying exception'
(MemManage, BusFault, SecureFault) targets Secure or NonSecure.  (In
the pseudocode, this is handled in the Vector() function: the final
exc.isSecure is calculated by looking at the exc.isSecure from the
exception returned from the memory access, not the isSecure input
argument.)

We weren't doing this correctly, because we were looking at
the target security domain of the exception we were trying to
load the vector table entry for. This produces errors of two kinds:
 * a load from the NS vector table which hits the "NS access
   to S memory" SecureFault should end up as a Secure HardFault,
   but we were raising an NS HardFault
 * a load from the S vector table which causes a BusFault
   should raise an NS HardFault if BFHFNMINS == 1 (because
   in that case all BusFaults are NonSecure), but we were raising
   a Secure HardFault

Correct the logic.

We also fix a comment error where we claimed that we might
be escalating MemManage to HardFault, and forgot about SecureFault.
(Vector loads can never hit MPU access faults, because they're
always aligned and always use the default address map.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20190705094823.28905-1-peter.maydell@linaro.org
---
 target/arm/m_helper.c | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
         if (sattrs.ns) {
             attrs.secure = false;
         } else if (!targets_secure) {
-            /* NS access to S memory */
+            /*
+             * NS access to S memory: the underlying exception which we escalate
+             * to HardFault is SecureFault, which always targets Secure.
+             */
+            exc_secure = true;
             goto load_fail;
         }
     }
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
     vector_entry = address_space_ldl(arm_addressspace(cs, attrs), addr,
                                      attrs, &result);
     if (result != MEMTX_OK) {
+        /*
+         * Underlying exception is BusFault: its target security state
+         * depends on BFHFNMINS.
+         */
+        exc_secure = !(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
         goto load_fail;
     }
     *pvec = vector_entry;
@@ -XXX,XX +XXX,XX @@ load_fail:
     /*
      * All vector table fetch fails are reported as HardFault, with
      * HFSR.VECTTBL and .FORCED set. (FORCED is set because
-     * technically the underlying exception is a MemManage or BusFault
+     * technically the underlying exception is a SecureFault or BusFault
      * that is escalated to HardFault.) This is a terminal exception,
      * so we will either take the HardFault immediately or else enter
      * lockup (the latter case is handled in armv7m_nvic_set_pending_derived()).
+     * The HardFault is Secure if BFHFNMINS is 0 (meaning that all HFs are
+     * secure); otherwise it targets the same security state as the
+     * underlying exception.
      */
-    exc_secure = targets_secure ||
-        !(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
+    if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
+        exc_secure = true;
+    }
     env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK | R_V7M_HFSR_FORCED_MASK;
     armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secure);
     return false;
-- 
2.20.1

arm queue: big stuff here is my MVE codegen optimisation,
and Alex's Apple Silicon hvf support.

-- PMM

The following changes since commit 7adb961995a3744f51396502b33ad04a56a317c3:

Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20210916' into staging (2021-09-19 18:53:29 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210920

for you to fetch changes up to 1dc5a60bfe406bc1122d68cbdefda38d23134b27:

target/arm: Optimize MVE 1op-immediate insns (2021-09-20 14:18:01 +0100)

----------------------------------------------------------------
target-arm queue:
 * Optimize codegen for MVE when predication not active
 * hvf: Add Apple Silicon support
 * hw/intc: Set GIC maintenance interrupt level to only 0 or 1
 * Fix mishandling of MVE FPSCR.LTPSIZE reset for usermode emulator
 * elf2dmp: Fix coverity nits

----------------------------------------------------------------
Alexander Graf (7):
      arm: Move PMC register definitions to internals.h
      hvf: Add execute to dirty log permission bitmap
      hvf: Introduce hvf_arch_init() callback
      hvf: Add Apple Silicon support
      hvf: arm: Implement PSCI handling
      arm: Add Hypervisor.framework build target
      hvf: arm: Add rudimentary PMC support

Peter Collingbourne (1):
      arm/hvf: Add a WFI handler

Peter Maydell (18):
      elf2dmp: Check curl_easy_setopt() return value
      elf2dmp: Fail cleanly if PDB file specifies zero block_size
      target/arm: Don't skip M-profile reset entirely in user mode
      target/arm: Always clear exclusive monitor on reset
      target/arm: Consolidate ifdef blocks in reset
      hvf: arm: Implement -cpu host
      target/arm: Avoid goto_tb if we're trying to exit to the main loop
      target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration
      target/arm: Add TB flag for "MVE insns not predicated"
      target/arm: Optimize MVE logic ops
      target/arm: Optimize MVE arithmetic ops
      target/arm: Optimize MVE VNEG, VABS
      target/arm: Optimize MVE VDUP
      target/arm: Optimize MVE VMVN
      target/arm: Optimize MVE VSHL, VSHR immediate forms
      target/arm: Optimize MVE VSHLL and VMOVL
      target/arm: Optimize MVE VSLI and VSRI
      target/arm: Optimize MVE 1op-immediate insns

Shashi Mallela (1):
      hw/intc: Set GIC maintenance interrupt level to only 0 or 1

Coverity points out that we aren't checking the return value
from curl_easy_setopt().

Fixes: Coverity CID 1458895
Inspired-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Viktor Prutyanov <viktor.prutyanov@phystech.edu>
Tested-by: Viktor Prutyanov <viktor.prutyanov@phystech.edu>
Message-id: 20210910170656.366592-2-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 contrib/elf2dmp/download.c | 22 ++++++++++------------
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/contrib/elf2dmp/download.c b/contrib/elf2dmp/download.c
index XXXXXXX..XXXXXXX 100644
--- a/contrib/elf2dmp/download.c
+++ b/contrib/elf2dmp/download.c
@@ -XXX,XX +XXX,XX @@ int download_url(const char *name, const char *url)
         goto out_curl;
     }
 
-    curl_easy_setopt(curl, CURLOPT_URL, url);
-    curl_easy_setopt(curl, CURLOPT_WRITEFUNCTION, NULL);
-    curl_easy_setopt(curl, CURLOPT_WRITEDATA, file);
-    curl_easy_setopt(curl, CURLOPT_FOLLOWLOCATION, 1);
-    curl_easy_setopt(curl, CURLOPT_NOPROGRESS, 0);
-
-    if (curl_easy_perform(curl) != CURLE_OK) {
-        err = 1;
-        fclose(file);
+    if (curl_easy_setopt(curl, CURLOPT_URL, url) != CURLE_OK
+            || curl_easy_setopt(curl, CURLOPT_WRITEFUNCTION, NULL) != CURLE_OK
+            || curl_easy_setopt(curl, CURLOPT_WRITEDATA, file) != CURLE_OK
+            || curl_easy_setopt(curl, CURLOPT_FOLLOWLOCATION, 1) != CURLE_OK
+            || curl_easy_setopt(curl, CURLOPT_NOPROGRESS, 0) != CURLE_OK
+            || curl_easy_perform(curl) != CURLE_OK) {
         unlink(name);
-        goto out_curl;
+        fclose(file);
+        err = 1;
+    } else {
+        err = fclose(file);
     }
 
-    err = fclose(file);
-
 out_curl:
     curl_easy_cleanup(curl);
 
-- 
2.20.1

Coverity points out that if the PDB file we're trying to read
has a header specifying a block_size of zero then we will
end up trying to divide by zero in pdb_ds_read_file().
Check for this and fail cleanly instead.

Fixes: Coverity CID 1458869
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Viktor Prutyanov <viktor.prutyanov@phystech.edu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Viktor Prutyanov <viktor.prutyanov@phystech.edu>
Message-id: 20210910170656.366592-3-philmd@redhat.com
Message-Id: <20210901143910.17112-3-peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 contrib/elf2dmp/pdb.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c
index XXXXXXX..XXXXXXX 100644
--- a/contrib/elf2dmp/pdb.c
+++ b/contrib/elf2dmp/pdb.c
@@ -XXX,XX +XXX,XX @@ out_symbols:
 
 static int pdb_reader_ds_init(struct pdb_reader *r, PDB_DS_HEADER *hdr)
 {
+    if (hdr->block_size == 0) {
+        return 1;
+    }
+
     memset(r->file_used, 0, sizeof(r->file_used));
     r->ds.header = hdr;
     r->ds.toc = pdb_ds_read(hdr, (uint32_t *)((uint8_t *)hdr +
-- 
2.20.1

Currently all of the M-profile specific code in arm_cpu_reset() is
inside a !defined(CONFIG_USER_ONLY) ifdef block.  This is
unintentional: it happened because originally the only
M-profile-specific handling was the setup of the initial SP and PC
from the vector table, which is system-emulation only.  But then we
added a lot of other M-profile setup to the same "if (ARM_FEATURE_M)"
code block without noticing that it was all inside a not-user-mode
ifdef.  This has generally been harmless, but with the addition of
v8.1M low-overhead-loop support we ran into a problem: the reset of
FPSCR.LTPSIZE to 4 was only being done for system emulation mode, so
if a user-mode guest tried to execute the LE instruction it would
incorrectly take a UsageFault.

Adjust the ifdefs so only the really system-emulation specific parts
are covered.  Because this means we now run some reset code that sets
up initial values in the FPCCR and similar FPU related registers,
explicitly set up the registers controlling FPU context handling in
user-emulation mode so that the FPU works by design and not by
chance.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/613
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210914120725.24992-2-peter.maydell@linaro.org
---
 target/arm/cpu.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
         env->uncached_cpsr = ARM_CPU_MODE_SVC;
     }
     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
+#endif
 
     if (arm_feature(env, ARM_FEATURE_M)) {
+#ifndef CONFIG_USER_ONLY
         uint32_t initial_msp; /* Loaded from 0x0 */
         uint32_t initial_pc; /* Loaded from 0x4 */
         uint8_t *rom;
         uint32_t vecbase;
+#endif
 
         if (cpu_isar_feature(aa32_lob, cpu)) {
             /*
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
             env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
                 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
         }
+
+#ifndef CONFIG_USER_ONLY
         /* Unlike A/R profile, M profile defines the reset LR value */
         env->regs[14] = 0xffffffff;
 
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
         env->regs[13] = initial_msp & 0xFFFFFFFC;
         env->regs[15] = initial_pc & ~1;
         env->thumb = initial_pc & 1;
+#else
+        /*
+         * For user mode we run non-secure and with access to the FPU.
+         * The FPU context is active (ie does not need further setup)
+         * and is owned by non-secure.
+         */
+        env->v7m.secure = false;
+        env->v7m.nsacr = 0xcff;
+        env->v7m.cpacr[M_REG_NS] = 0xf0ffff;
+        env->v7m.fpccr[M_REG_S] &=
+            ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK);
+        env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK;
+#endif
     }
 
+#ifndef CONFIG_USER_ONLY
     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
      * executing as AArch32 then check if highvecs are enabled and
      * adjust the PC accordingly.
-- 
2.20.1

There's no particular reason why the exclusive monitor should
be only cleared on reset in system emulation mode. It doesn't
hurt if it isn't cleared in user mode, but we might as well
reduce the amount of code we have that's inside an ifdef.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210914120725.24992-3-peter.maydell@linaro.org
---
 target/arm/cpu.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
         env->regs[15] = 0xFFFF0000;
     }
 
+    env->vfp.xregs[ARM_VFP_FPEXC] = 0;
+#endif
+
     /* M profile requires that reset clears the exclusive monitor;
      * A profile does not, but clearing it makes more sense than having it
      * set with an exclusive access on address zero.
      */
     arm_clear_exclusive(env);
 
-    env->vfp.xregs[ARM_VFP_FPEXC] = 0;
-#endif
-
     if (arm_feature(env, ARM_FEATURE_PMSA)) {
         if (cpu->pmsav7_dregion > 0) {
             if (arm_feature(env, ARM_FEATURE_V8)) {
-- 
2.20.1

Move an ifndef CONFIG_USER_ONLY code block up in arm_cpu_reset() so
it can be merged with another earlier one.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210914120725.24992-4-peter.maydell@linaro.org
---
 target/arm/cpu.c | 22 ++++++++++------------
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
         env->uncached_cpsr = ARM_CPU_MODE_SVC;
     }
     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
+
+    /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
+     * executing as AArch32 then check if highvecs are enabled and
+     * adjust the PC accordingly.
+     */
+    if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
+        env->regs[15] = 0xFFFF0000;
+    }
+
+    env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 #endif
 
     if (arm_feature(env, ARM_FEATURE_M)) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
 #endif
     }
 
-#ifndef CONFIG_USER_ONLY
-    /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
-     * executing as AArch32 then check if highvecs are enabled and
-     * adjust the PC accordingly.
-     */
-    if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
-        env->regs[15] = 0xFFFF0000;
-    }
-
-    env->vfp.xregs[ARM_VFP_FPEXC] = 0;
-#endif
-
     /* M profile requires that reset clears the exclusive monitor;
      * A profile does not, but clearing it makes more sense than having it
      * set with an exclusive access on address zero.
-- 
2.20.1

From: Shashi Mallela <shashi.mallela@linaro.org>

During sbsa acs level 3 testing, it is seen that the GIC maintenance
interrupts are not triggered and the related test cases fail.  This
is because we were incorrectly passing the value of the MISR register
(from maintenance_interrupt_state()) to qemu_set_irq() as the level
argument, whereas the device on the other end of this irq line
expects a 0/1 value.

Fix the logic to pass a 0/1 level indication, rather than a
0/not-0 value.

Fixes: c5fc89b36c0 ("hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()")
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210915205809.59068-1-shashi.mallela@linaro.org
[PMM: tweaked commit message; collapsed nested if()s into one]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_cpuif.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
         }
     }
 
-    if (cs->ich_hcr_el2 & ICH_HCR_EL2_EN) {
-        maintlevel = maintenance_interrupt_state(cs);
+    if ((cs->ich_hcr_el2 & ICH_HCR_EL2_EN) &&
+        maintenance_interrupt_state(cs) != 0) {
+        maintlevel = 1;
     }
 
     trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel,
-- 
2.20.1

From: Alexander Graf <agraf@csgraf.de>

We will need PMC register definitions in accel specific code later.
Move all constant definitions to common arm headers so we can reuse
them.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210916155404.86958-2-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h | 44 ++++++++++++++++++++++++++++++++++++++++++
 target/arm/helper.c    | 44 ------------------------------------------
 2 files changed, 44 insertions(+), 44 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ enum MVEECIState {
     /* All other values reserved */
 };
 
+/* Definitions for the PMU registers */
+#define PMCRN_MASK  0xf800
+#define PMCRN_SHIFT 11
+#define PMCRLC  0x40
+#define PMCRDP  0x20
+#define PMCRX   0x10
+#define PMCRD   0x8
+#define PMCRC   0x4
+#define PMCRP   0x2
+#define PMCRE   0x1
+/*
+ * Mask of PMCR bits writeable by guest (not including WO bits like C, P,
+ * which can be written as 1 to trigger behaviour but which stay RAZ).
+ */
+#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
+
+#define PMXEVTYPER_P          0x80000000
+#define PMXEVTYPER_U          0x40000000
+#define PMXEVTYPER_NSK        0x20000000
+#define PMXEVTYPER_NSU        0x10000000
+#define PMXEVTYPER_NSH        0x08000000
+#define PMXEVTYPER_M          0x04000000
+#define PMXEVTYPER_MT         0x02000000
+#define PMXEVTYPER_EVTCOUNT   0x0000ffff
+#define PMXEVTYPER_MASK       (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
+                               PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
+                               PMXEVTYPER_M | PMXEVTYPER_MT | \
+                               PMXEVTYPER_EVTCOUNT)
+
+#define PMCCFILTR             0xf8000000
+#define PMCCFILTR_M           PMXEVTYPER_M
+#define PMCCFILTR_EL0         (PMCCFILTR | PMCCFILTR_M)
+
+static inline uint32_t pmu_num_counters(CPUARMState *env)
+{
+  return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
+}
+
+/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
+static inline uint64_t pmu_counter_mask(CPUARMState *env)
+{
+  return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
+}
+
 #endif
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
     REGINFO_SENTINEL
 };
 
-/* Definitions for the PMU registers */
-#define PMCRN_MASK  0xf800
-#define PMCRN_SHIFT 11
-#define PMCRLC  0x40
-#define PMCRDP  0x20
-#define PMCRX   0x10
-#define PMCRD   0x8
-#define PMCRC   0x4
-#define PMCRP   0x2
-#define PMCRE   0x1
-/*
- * Mask of PMCR bits writeable by guest (not including WO bits like C, P,
- * which can be written as 1 to trigger behaviour but which stay RAZ).
- */
-#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
-
-#define PMXEVTYPER_P          0x80000000
-#define PMXEVTYPER_U          0x40000000
-#define PMXEVTYPER_NSK        0x20000000
-#define PMXEVTYPER_NSU        0x10000000
-#define PMXEVTYPER_NSH        0x08000000
-#define PMXEVTYPER_M          0x04000000
-#define PMXEVTYPER_MT         0x02000000
-#define PMXEVTYPER_EVTCOUNT   0x0000ffff
-#define PMXEVTYPER_MASK       (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
-                               PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
-                               PMXEVTYPER_M | PMXEVTYPER_MT | \
-                               PMXEVTYPER_EVTCOUNT)
-
-#define PMCCFILTR             0xf8000000
-#define PMCCFILTR_M           PMXEVTYPER_M
-#define PMCCFILTR_EL0         (PMCCFILTR | PMCCFILTR_M)
-
-static inline uint32_t pmu_num_counters(CPUARMState *env)
-{
-  return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
-}
-
-/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
-static inline uint64_t pmu_counter_mask(CPUARMState *env)
-{
-  return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
-}
-
 typedef struct pm_event {
     uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */
     /* If the event is supported on this CPU (used to generate PMCEID[01]) */
-- 
2.20.1

From: Alexander Graf <agraf@csgraf.de>

Hvf's permission bitmap during and after dirty logging does not include
the HV_MEMORY_EXEC permission. At least on Apple Silicon, this leads to
instruction faults once dirty logging was enabled.

Add the bit to make it work properly.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210916155404.86958-3-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 accel/hvf/hvf-accel-ops.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/hvf/hvf-accel-ops.c
+++ b/accel/hvf/hvf-accel-ops.c
@@ -XXX,XX +XXX,XX @@ static void hvf_set_dirty_tracking(MemoryRegionSection *section, bool on)
     if (on) {
         slot->flags |= HVF_SLOT_LOG;
         hv_vm_protect((uintptr_t)slot->start, (size_t)slot->size,
-                      HV_MEMORY_READ);
+                      HV_MEMORY_READ | HV_MEMORY_EXEC);
     /* stop tracking region*/
     } else {
         slot->flags &= ~HVF_SLOT_LOG;
         hv_vm_protect((uintptr_t)slot->start, (size_t)slot->size,
-                      HV_MEMORY_READ | HV_MEMORY_WRITE);
+                      HV_MEMORY_READ | HV_MEMORY_WRITE | HV_MEMORY_EXEC);
     }
 }
 
-- 
2.20.1

From: Alexander Graf <agraf@csgraf.de>

We will need to install a migration helper for the ARM hvf backend.
Let's introduce an arch callback for the overall hvf init chain to
do so.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210916155404.86958-4-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/sysemu/hvf_int.h  | 1 +
 accel/hvf/hvf-accel-ops.c | 3 ++-
 target/i386/hvf/hvf.c     | 5 +++++
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/hvf_int.h
+++ b/include/sysemu/hvf_int.h
@@ -XXX,XX +XXX,XX @@ struct hvf_vcpu_state {
 };
 
 void assert_hvf_ok(hv_return_t ret);
+int hvf_arch_init(void);
 int hvf_arch_init_vcpu(CPUState *cpu);
 void hvf_arch_vcpu_destroy(CPUState *cpu);
 int hvf_vcpu_exec(CPUState *);
diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/hvf/hvf-accel-ops.c
+++ b/accel/hvf/hvf-accel-ops.c
@@ -XXX,XX +XXX,XX @@ static int hvf_accel_init(MachineState *ms)
 
     hvf_state = s;
     memory_listener_register(&hvf_memory_listener, &address_space_memory);
-    return 0;
+
+    return hvf_arch_init();
 }
 
 static void hvf_accel_class_init(ObjectClass *oc, void *data)
diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
index XXXXXXX..XXXXXXX 100644
--- a/target/i386/hvf/hvf.c
+++ b/target/i386/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@ static inline bool apic_bus_freq_is_known(CPUX86State *env)
     return env->apic_bus_freq != 0;
 }
 
+int hvf_arch_init(void)
+{
+    return 0;
+}
+
 int hvf_arch_init_vcpu(CPUState *cpu)
 {
     X86CPU *x86cpu = X86_CPU(cpu);
-- 
2.20.1

From: Alexander Graf <agraf@csgraf.de>

With Apple Silicon available to the masses, it's a good time to add support
for driving its virtualization extensions from QEMU.

This patch adds all necessary architecture specific code to get basic VMs
working, including save/restore.

Known limitations:

- WFI handling is missing (follows in later patch)
  - No watchpoint/breakpoint support

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210916155404.86958-5-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 meson.build                 |   1 +
 include/sysemu/hvf_int.h    |  10 +-
 accel/hvf/hvf-accel-ops.c   |   9 +
 target/arm/hvf/hvf.c        | 794 ++++++++++++++++++++++++++++++++++++
 target/i386/hvf/hvf.c       |   5 +
 MAINTAINERS                 |   5 +
 target/arm/hvf/trace-events |  10 +
 7 files changed, 833 insertions(+), 1 deletion(-)
 create mode 100644 target/arm/hvf/hvf.c
 create mode 100644 target/arm/hvf/trace-events

diff --git a/meson.build b/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/meson.build
+++ b/meson.build
@@ -XXX,XX +XXX,XX @@ if have_system or have_user
     'accel/tcg',
     'hw/core',
     'target/arm',
+    'target/arm/hvf',
     'target/hppa',
     'target/i386',
     'target/i386/kvm',
diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/hvf_int.h
+++ b/include/sysemu/hvf_int.h
@@ -XXX,XX +XXX,XX @@
 #ifndef HVF_INT_H
 #define HVF_INT_H
 
+#ifdef __aarch64__
+#include <Hypervisor/Hypervisor.h>
+#else
 #include <Hypervisor/hv.h>
+#endif
 
 /* hvf_slot flags */
 #define HVF_SLOT_LOG (1 << 0)
@@ -XXX,XX +XXX,XX @@ struct HVFState {
     int num_slots;
 
     hvf_vcpu_caps *hvf_caps;
+    uint64_t vtimer_offset;
 };
 extern HVFState *hvf_state;
 
 struct hvf_vcpu_state {
-    int fd;
+    uint64_t fd;
+    void *exit;
+    bool vtimer_masked;
 };
 
 void assert_hvf_ok(hv_return_t ret);
@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *);
 hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t);
 int hvf_put_registers(CPUState *);
 int hvf_get_registers(CPUState *);
+void hvf_kick_vcpu_thread(CPUState *cpu);
 
 #endif
diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/hvf/hvf-accel-ops.c
+++ b/accel/hvf/hvf-accel-ops.c
@@ -XXX,XX +XXX,XX @@
 
 HVFState *hvf_state;
 
+#ifdef __aarch64__
+#define HV_VM_DEFAULT NULL
+#endif
+
 /* Memory slots */
 
 hvf_slot *hvf_find_overlap_slot(uint64_t start, uint64_t size)
@@ -XXX,XX +XXX,XX @@ static int hvf_init_vcpu(CPUState *cpu)
     pthread_sigmask(SIG_BLOCK, NULL, &set);
     sigdelset(&set, SIG_IPI);
 
+#ifdef __aarch64__
+    r = hv_vcpu_create(&cpu->hvf->fd, (hv_vcpu_exit_t **)&cpu->hvf->exit, NULL);
+#else
     r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf->fd, HV_VCPU_DEFAULT);
+#endif
     cpu->vcpu_dirty = 1;
     assert_hvf_ok(r);
 
@@ -XXX,XX +XXX,XX @@ static void hvf_accel_ops_class_init(ObjectClass *oc, void *data)
     AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
 
     ops->create_vcpu_thread = hvf_start_vcpu_thread;
+    ops->kick_vcpu_thread = hvf_kick_vcpu_thread;
 
     ops->synchronize_post_reset = hvf_cpu_synchronize_post_reset;
     ops->synchronize_post_init = hvf_cpu_synchronize_post_init;
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU Hypervisor.framework support for Apple Silicon
+
+ * Copyright 2020 Alexander Graf <agraf@csgraf.de>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "qemu/error-report.h"
+
+#include "sysemu/runstate.h"
+#include "sysemu/hvf.h"
+#include "sysemu/hvf_int.h"
+#include "sysemu/hw_accel.h"
+
+#include <mach/mach_time.h>
+
+#include "exec/address-spaces.h"
+#include "hw/irq.h"
+#include "qemu/main-loop.h"
+#include "sysemu/cpus.h"
+#include "target/arm/cpu.h"
+#include "target/arm/internals.h"
+#include "trace/trace-target_arm_hvf.h"
+#include "migration/vmstate.h"
+
+#define HVF_SYSREG(crn, crm, op0, op1, op2) \
+        ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
+#define PL1_WRITE_MASK 0x4
+
+#define SYSREG(op0, op1, crn, crm, op2) \
+    ((op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (crm << 1))
+#define SYSREG_MASK           SYSREG(0x3, 0x7, 0xf, 0xf, 0x7)
+#define SYSREG_OSLAR_EL1      SYSREG(2, 0, 1, 0, 4)
+#define SYSREG_OSLSR_EL1      SYSREG(2, 0, 1, 1, 4)
+#define SYSREG_OSDLR_EL1      SYSREG(2, 0, 1, 3, 4)
+#define SYSREG_CNTPCT_EL0     SYSREG(3, 3, 14, 0, 1)
+
+#define WFX_IS_WFE (1 << 0)
+
+#define TMR_CTL_ENABLE  (1 << 0)
+#define TMR_CTL_IMASK   (1 << 1)
+#define TMR_CTL_ISTATUS (1 << 2)
+
+typedef struct HVFVTimer {
+    /* Vtimer value during migration and paused state */
+    uint64_t vtimer_val;
+} HVFVTimer;
+
+static HVFVTimer vtimer;
+
+struct hvf_reg_match {
+    int reg;
+    uint64_t offset;
+};
+
+static const struct hvf_reg_match hvf_reg_match[] = {
+    { HV_REG_X0,   offsetof(CPUARMState, xregs[0]) },
+    { HV_REG_X1,   offsetof(CPUARMState, xregs[1]) },
+    { HV_REG_X2,   offsetof(CPUARMState, xregs[2]) },
+    { HV_REG_X3,   offsetof(CPUARMState, xregs[3]) },
+    { HV_REG_X4,   offsetof(CPUARMState, xregs[4]) },
+    { HV_REG_X5,   offsetof(CPUARMState, xregs[5]) },
+    { HV_REG_X6,   offsetof(CPUARMState, xregs[6]) },
+    { HV_REG_X7,   offsetof(CPUARMState, xregs[7]) },
+    { HV_REG_X8,   offsetof(CPUARMState, xregs[8]) },
+    { HV_REG_X9,   offsetof(CPUARMState, xregs[9]) },
+    { HV_REG_X10,  offsetof(CPUARMState, xregs[10]) },
+    { HV_REG_X11,  offsetof(CPUARMState, xregs[11]) },
+    { HV_REG_X12,  offsetof(CPUARMState, xregs[12]) },
+    { HV_REG_X13,  offsetof(CPUARMState, xregs[13]) },
+    { HV_REG_X14,  offsetof(CPUARMState, xregs[14]) },
+    { HV_REG_X15,  offsetof(CPUARMState, xregs[15]) },
+    { HV_REG_X16,  offsetof(CPUARMState, xregs[16]) },
+    { HV_REG_X17,  offsetof(CPUARMState, xregs[17]) },
+    { HV_REG_X18,  offsetof(CPUARMState, xregs[18]) },
+    { HV_REG_X19,  offsetof(CPUARMState, xregs[19]) },
+    { HV_REG_X20,  offsetof(CPUARMState, xregs[20]) },
+    { HV_REG_X21,  offsetof(CPUARMState, xregs[21]) },
+    { HV_REG_X22,  offsetof(CPUARMState, xregs[22]) },
+    { HV_REG_X23,  offsetof(CPUARMState, xregs[23]) },
+    { HV_REG_X24,  offsetof(CPUARMState, xregs[24]) },
+    { HV_REG_X25,  offsetof(CPUARMState, xregs[25]) },
+    { HV_REG_X26,  offsetof(CPUARMState, xregs[26]) },
+    { HV_REG_X27,  offsetof(CPUARMState, xregs[27]) },
+    { HV_REG_X28,  offsetof(CPUARMState, xregs[28]) },
+    { HV_REG_X29,  offsetof(CPUARMState, xregs[29]) },
+    { HV_REG_X30,  offsetof(CPUARMState, xregs[30]) },
+    { HV_REG_PC,   offsetof(CPUARMState, pc) },
+};
+
+static const struct hvf_reg_match hvf_fpreg_match[] = {
+    { HV_SIMD_FP_REG_Q0,  offsetof(CPUARMState, vfp.zregs[0]) },
+    { HV_SIMD_FP_REG_Q1,  offsetof(CPUARMState, vfp.zregs[1]) },
+    { HV_SIMD_FP_REG_Q2,  offsetof(CPUARMState, vfp.zregs[2]) },
+    { HV_SIMD_FP_REG_Q3,  offsetof(CPUARMState, vfp.zregs[3]) },
+    { HV_SIMD_FP_REG_Q4,  offsetof(CPUARMState, vfp.zregs[4]) },
+    { HV_SIMD_FP_REG_Q5,  offsetof(CPUARMState, vfp.zregs[5]) },
+    { HV_SIMD_FP_REG_Q6,  offsetof(CPUARMState, vfp.zregs[6]) },
+    { HV_SIMD_FP_REG_Q7,  offsetof(CPUARMState, vfp.zregs[7]) },
+    { HV_SIMD_FP_REG_Q8,  offsetof(CPUARMState, vfp.zregs[8]) },
+    { HV_SIMD_FP_REG_Q9,  offsetof(CPUARMState, vfp.zregs[9]) },
+    { HV_SIMD_FP_REG_Q10, offsetof(CPUARMState, vfp.zregs[10]) },
+    { HV_SIMD_FP_REG_Q11, offsetof(CPUARMState, vfp.zregs[11]) },
+    { HV_SIMD_FP_REG_Q12, offsetof(CPUARMState, vfp.zregs[12]) },
+    { HV_SIMD_FP_REG_Q13, offsetof(CPUARMState, vfp.zregs[13]) },
+    { HV_SIMD_FP_REG_Q14, offsetof(CPUARMState, vfp.zregs[14]) },
+    { HV_SIMD_FP_REG_Q15, offsetof(CPUARMState, vfp.zregs[15]) },
+    { HV_SIMD_FP_REG_Q16, offsetof(CPUARMState, vfp.zregs[16]) },
+    { HV_SIMD_FP_REG_Q17, offsetof(CPUARMState, vfp.zregs[17]) },
+    { HV_SIMD_FP_REG_Q18, offsetof(CPUARMState, vfp.zregs[18]) },
+    { HV_SIMD_FP_REG_Q19, offsetof(CPUARMState, vfp.zregs[19]) },
+    { HV_SIMD_FP_REG_Q20, offsetof(CPUARMState, vfp.zregs[20]) },
+    { HV_SIMD_FP_REG_Q21, offsetof(CPUARMState, vfp.zregs[21]) },
+    { HV_SIMD_FP_REG_Q22, offsetof(CPUARMState, vfp.zregs[22]) },
+    { HV_SIMD_FP_REG_Q23, offsetof(CPUARMState, vfp.zregs[23]) },
+    { HV_SIMD_FP_REG_Q24, offsetof(CPUARMState, vfp.zregs[24]) },
+    { HV_SIMD_FP_REG_Q25, offsetof(CPUARMState, vfp.zregs[25]) },
+    { HV_SIMD_FP_REG_Q26, offsetof(CPUARMState, vfp.zregs[26]) },
+    { HV_SIMD_FP_REG_Q27, offsetof(CPUARMState, vfp.zregs[27]) },
+    { HV_SIMD_FP_REG_Q28, offsetof(CPUARMState, vfp.zregs[28]) },
+    { HV_SIMD_FP_REG_Q29, offsetof(CPUARMState, vfp.zregs[29]) },
+    { HV_SIMD_FP_REG_Q30, offsetof(CPUARMState, vfp.zregs[30]) },
+    { HV_SIMD_FP_REG_Q31, offsetof(CPUARMState, vfp.zregs[31]) },
+};
+
+struct hvf_sreg_match {
+    int reg;
+    uint32_t key;
+    uint32_t cp_idx;
+};
+
+static struct hvf_sreg_match hvf_sreg_match[] = {
+    { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 4) },
+    { HV_SYS_REG_DBGBCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 5) },
+    { HV_SYS_REG_DBGWVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 6) },
+    { HV_SYS_REG_DBGWCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 7) },
+
+    { HV_SYS_REG_DBGBVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 4) },
+    { HV_SYS_REG_DBGBCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 5) },
+    { HV_SYS_REG_DBGWVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 6) },
+    { HV_SYS_REG_DBGWCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 7) },
+
+    { HV_SYS_REG_DBGBVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 4) },
+    { HV_SYS_REG_DBGBCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 5) },
+    { HV_SYS_REG_DBGWVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 6) },
+    { HV_SYS_REG_DBGWCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 7) },
+
+    { HV_SYS_REG_DBGBVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 4) },
+    { HV_SYS_REG_DBGBCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 5) },
+    { HV_SYS_REG_DBGWVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 6) },
+    { HV_SYS_REG_DBGWCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 7) },
+
+    { HV_SYS_REG_DBGBVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 4) },
+    { HV_SYS_REG_DBGBCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 5) },
+    { HV_SYS_REG_DBGWVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 6) },
+    { HV_SYS_REG_DBGWCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 7) },
+
+    { HV_SYS_REG_DBGBVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 4) },
+    { HV_SYS_REG_DBGBCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 5) },
+    { HV_SYS_REG_DBGWVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 6) },
+    { HV_SYS_REG_DBGWCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 7) },
+
+    { HV_SYS_REG_DBGBVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 4) },
+    { HV_SYS_REG_DBGBCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 5) },
+    { HV_SYS_REG_DBGWVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 6) },
+    { HV_SYS_REG_DBGWCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 7) },
+
+    { HV_SYS_REG_DBGBVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 4) },
+    { HV_SYS_REG_DBGBCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 5) },
+    { HV_SYS_REG_DBGWVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 6) },
+    { HV_SYS_REG_DBGWCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 7) },
+
+    { HV_SYS_REG_DBGBVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 4) },
+    { HV_SYS_REG_DBGBCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 5) },
+    { HV_SYS_REG_DBGWVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 6) },
+    { HV_SYS_REG_DBGWCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 7) },
+
+    { HV_SYS_REG_DBGBVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 4) },
+    { HV_SYS_REG_DBGBCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 5) },
+    { HV_SYS_REG_DBGWVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 6) },
+    { HV_SYS_REG_DBGWCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 7) },
+
+    { HV_SYS_REG_DBGBVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 4) },
+    { HV_SYS_REG_DBGBCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 5) },
+    { HV_SYS_REG_DBGWVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 6) },
+    { HV_SYS_REG_DBGWCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 7) },
+
+    { HV_SYS_REG_DBGBVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 4) },
+    { HV_SYS_REG_DBGBCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 5) },
+    { HV_SYS_REG_DBGWVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 6) },
+    { HV_SYS_REG_DBGWCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 7) },
+
+    { HV_SYS_REG_DBGBVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 4) },
+    { HV_SYS_REG_DBGBCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 5) },
+    { HV_SYS_REG_DBGWVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 6) },
+    { HV_SYS_REG_DBGWCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 7) },
+
+    { HV_SYS_REG_DBGBVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 4) },
+    { HV_SYS_REG_DBGBCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 5) },
+    { HV_SYS_REG_DBGWVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 6) },
+    { HV_SYS_REG_DBGWCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 7) },
+
+    { HV_SYS_REG_DBGBVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 4) },
+    { HV_SYS_REG_DBGBCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 5) },
+    { HV_SYS_REG_DBGWVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 6) },
+    { HV_SYS_REG_DBGWCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 7) },
+
+    { HV_SYS_REG_DBGBVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 4) },
+    { HV_SYS_REG_DBGBCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 5) },
+    { HV_SYS_REG_DBGWVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 6) },
+    { HV_SYS_REG_DBGWCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 7) },
+
+#ifdef SYNC_NO_RAW_REGS
+    /*
+     * The registers below are manually synced on init because they are
+     * marked as NO_RAW. We still list them to make number space sync easier.
+     */
+    { HV_SYS_REG_MDCCINT_EL1, HVF_SYSREG(0, 2, 2, 0, 0) },
+    { HV_SYS_REG_MIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 0) },
+    { HV_SYS_REG_MPIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 5) },
+    { HV_SYS_REG_ID_AA64PFR0_EL1, HVF_SYSREG(0, 4, 3, 0, 0) },
+#endif
+    { HV_SYS_REG_ID_AA64PFR1_EL1, HVF_SYSREG(0, 4, 3, 0, 2) },
+    { HV_SYS_REG_ID_AA64DFR0_EL1, HVF_SYSREG(0, 5, 3, 0, 0) },
+    { HV_SYS_REG_ID_AA64DFR1_EL1, HVF_SYSREG(0, 5, 3, 0, 1) },
+    { HV_SYS_REG_ID_AA64ISAR0_EL1, HVF_SYSREG(0, 6, 3, 0, 0) },
+    { HV_SYS_REG_ID_AA64ISAR1_EL1, HVF_SYSREG(0, 6, 3, 0, 1) },
+#ifdef SYNC_NO_MMFR0
+    /* We keep the hardware MMFR0 around. HW limits are there anyway */
+    { HV_SYS_REG_ID_AA64MMFR0_EL1, HVF_SYSREG(0, 7, 3, 0, 0) },
+#endif
+    { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) },
+    { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) },
+
+    { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) },
+    { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) },
+    { HV_SYS_REG_CPACR_EL1, HVF_SYSREG(1, 0, 3, 0, 2) },
+    { HV_SYS_REG_TTBR0_EL1, HVF_SYSREG(2, 0, 3, 0, 0) },
+    { HV_SYS_REG_TTBR1_EL1, HVF_SYSREG(2, 0, 3, 0, 1) },
+    { HV_SYS_REG_TCR_EL1, HVF_SYSREG(2, 0, 3, 0, 2) },
+
+    { HV_SYS_REG_APIAKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 0) },
+    { HV_SYS_REG_APIAKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 1) },
+    { HV_SYS_REG_APIBKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 2) },
+    { HV_SYS_REG_APIBKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 3) },
+    { HV_SYS_REG_APDAKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 0) },
+    { HV_SYS_REG_APDAKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 1) },
+    { HV_SYS_REG_APDBKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 2) },
+    { HV_SYS_REG_APDBKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 3) },
+    { HV_SYS_REG_APGAKEYLO_EL1, HVF_SYSREG(2, 3, 3, 0, 0) },
+    { HV_SYS_REG_APGAKEYHI_EL1, HVF_SYSREG(2, 3, 3, 0, 1) },
+
+    { HV_SYS_REG_SPSR_EL1, HVF_SYSREG(4, 0, 3, 0, 0) },
+    { HV_SYS_REG_ELR_EL1, HVF_SYSREG(4, 0, 3, 0, 1) },
+    { HV_SYS_REG_SP_EL0, HVF_SYSREG(4, 1, 3, 0, 0) },
+    { HV_SYS_REG_AFSR0_EL1, HVF_SYSREG(5, 1, 3, 0, 0) },
+    { HV_SYS_REG_AFSR1_EL1, HVF_SYSREG(5, 1, 3, 0, 1) },
+    { HV_SYS_REG_ESR_EL1, HVF_SYSREG(5, 2, 3, 0, 0) },
+    { HV_SYS_REG_FAR_EL1, HVF_SYSREG(6, 0, 3, 0, 0) },
+    { HV_SYS_REG_PAR_EL1, HVF_SYSREG(7, 4, 3, 0, 0) },
+    { HV_SYS_REG_MAIR_EL1, HVF_SYSREG(10, 2, 3, 0, 0) },
+    { HV_SYS_REG_AMAIR_EL1, HVF_SYSREG(10, 3, 3, 0, 0) },
+    { HV_SYS_REG_VBAR_EL1, HVF_SYSREG(12, 0, 3, 0, 0) },
+    { HV_SYS_REG_CONTEXTIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 1) },
+    { HV_SYS_REG_TPIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 4) },
+    { HV_SYS_REG_CNTKCTL_EL1, HVF_SYSREG(14, 1, 3, 0, 0) },
+    { HV_SYS_REG_CSSELR_EL1, HVF_SYSREG(0, 0, 3, 2, 0) },
+    { HV_SYS_REG_TPIDR_EL0, HVF_SYSREG(13, 0, 3, 3, 2) },
+    { HV_SYS_REG_TPIDRRO_EL0, HVF_SYSREG(13, 0, 3, 3, 3) },
+    { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) },
+    { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) },
+    { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) },
+};
+
+int hvf_get_registers(CPUState *cpu)
+{
+    ARMCPU *arm_cpu = ARM_CPU(cpu);
+    CPUARMState *env = &arm_cpu->env;
+    hv_return_t ret;
+    uint64_t val;
+    hv_simd_fp_uchar16_t fpval;
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) {
+        ret = hv_vcpu_get_reg(cpu->hvf->fd, hvf_reg_match[i].reg, &val);
+        *(uint64_t *)((void *)env + hvf_reg_match[i].offset) = val;
+        assert_hvf_ok(ret);
+    }
+
+    for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) {
+        ret = hv_vcpu_get_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].reg,
+                                      &fpval);
+        memcpy((void *)env + hvf_fpreg_match[i].offset, &fpval, sizeof(fpval));
+        assert_hvf_ok(ret);
+    }
+
+    val = 0;
+    ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPCR, &val);
+    assert_hvf_ok(ret);
+    vfp_set_fpcr(env, val);
+
+    val = 0;
+    ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPSR, &val);
+    assert_hvf_ok(ret);
+    vfp_set_fpsr(env, val);
+
+    ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_CPSR, &val);
+    assert_hvf_ok(ret);
+    pstate_write(env, val);
+
+    for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) {
+        if (hvf_sreg_match[i].cp_idx == -1) {
+            continue;
+        }
+
+        ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, &val);
+        assert_hvf_ok(ret);
+
+        arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val;
+    }
+    assert(write_list_to_cpustate(arm_cpu));
+
+    aarch64_restore_sp(env, arm_current_el(env));
+
+    return 0;
+}
+
+int hvf_put_registers(CPUState *cpu)
+{
+    ARMCPU *arm_cpu = ARM_CPU(cpu);
+    CPUARMState *env = &arm_cpu->env;
+    hv_return_t ret;
+    uint64_t val;
+    hv_simd_fp_uchar16_t fpval;
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) {
+        val = *(uint64_t *)((void *)env + hvf_reg_match[i].offset);
+        ret = hv_vcpu_set_reg(cpu->hvf->fd, hvf_reg_match[i].reg, val);
+        assert_hvf_ok(ret);
+    }
+
+    for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) {
+        memcpy(&fpval, (void *)env + hvf_fpreg_match[i].offset, sizeof(fpval));
+        ret = hv_vcpu_set_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].reg,
+                                      fpval);
+        assert_hvf_ok(ret);
+    }
+
+    ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPCR, vfp_get_fpcr(env));
+    assert_hvf_ok(ret);
+
+    ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPSR, vfp_get_fpsr(env));
+    assert_hvf_ok(ret);
+
+    ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_CPSR, pstate_read(env));
+    assert_hvf_ok(ret);
+
+    aarch64_save_sp(env, arm_current_el(env));
+
+    assert(write_cpustate_to_list(arm_cpu, false));
+    for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) {
+        if (hvf_sreg_match[i].cp_idx == -1) {
+            continue;
+        }
+
+        val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx];
+        ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, val);
+        assert_hvf_ok(ret);
+    }
+
+    ret = hv_vcpu_set_vtimer_offset(cpu->hvf->fd, hvf_state->vtimer_offset);
+    assert_hvf_ok(ret);
+
+    return 0;
+}
+
+static void flush_cpu_state(CPUState *cpu)
+{
+    if (cpu->vcpu_dirty) {
+        hvf_put_registers(cpu);
+        cpu->vcpu_dirty = false;
+    }
+}
+
+static void hvf_set_reg(CPUState *cpu, int rt, uint64_t val)
+{
+    hv_return_t r;
+
+    flush_cpu_state(cpu);
+
+    if (rt < 31) {
+        r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_X0 + rt, val);
+        assert_hvf_ok(r);
+    }
+}
+
+static uint64_t hvf_get_reg(CPUState *cpu, int rt)
+{
+    uint64_t val = 0;
+    hv_return_t r;
+
+    flush_cpu_state(cpu);
+
+    if (rt < 31) {
+        r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_X0 + rt, &val);
+        assert_hvf_ok(r);
+    }
+
+    return val;
+}
+
+void hvf_arch_vcpu_destroy(CPUState *cpu)
+{
+}
+
+int hvf_arch_init_vcpu(CPUState *cpu)
+{
+    ARMCPU *arm_cpu = ARM_CPU(cpu);
+    CPUARMState *env = &arm_cpu->env;
+    uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_match);
+    uint32_t sregs_cnt = 0;
+    uint64_t pfr;
+    hv_return_t ret;
+    int i;
+
+    env->aarch64 = 1;
+    asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz));
+
+    /* Allocate enough space for our sysreg sync */
+    arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes,
+                                     sregs_match_len);
+    arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values,
+                                    sregs_match_len);
+    arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t,
+                                             arm_cpu->cpreg_vmstate_indexes,
+                                             sregs_match_len);
+    arm_cpu->cpreg_vmstate_values = g_renew(uint64_t,
+                                            arm_cpu->cpreg_vmstate_values,
+                                            sregs_match_len);
+
+    memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t));
+
+    /* Populate cp list for all known sysregs */
+    for (i = 0; i < sregs_match_len; i++) {
+        const ARMCPRegInfo *ri;
+        uint32_t key = hvf_sreg_match[i].key;
+
+        ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);
+        if (ri) {
+            assert(!(ri->type & ARM_CP_NO_RAW));
+            hvf_sreg_match[i].cp_idx = sregs_cnt;
+            arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key);
+        } else {
+            hvf_sreg_match[i].cp_idx = -1;
+        }
+    }
+    arm_cpu->cpreg_array_len = sregs_cnt;
+    arm_cpu->cpreg_vmstate_array_len = sregs_cnt;
+
+    assert(write_cpustate_to_list(arm_cpu, false));
+
+    /* Set CP_NO_RAW system registers on init */
+    ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MIDR_EL1,
+                              arm_cpu->midr);
+    assert_hvf_ok(ret);
+
+    ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MPIDR_EL1,
+                              arm_cpu->mp_affinity);
+    assert_hvf_ok(ret);
+
+    ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr);
+    assert_hvf_ok(ret);
+    pfr |= env->gicv3state ? (1 << 24) : 0;
+    ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr);
+    assert_hvf_ok(ret);
+
+    /* We're limited to underlying hardware caps, override internal versions */
+    ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64MMFR0_EL1,
+                              &arm_cpu->isar.id_aa64mmfr0);
+    assert_hvf_ok(ret);
+
+    return 0;
+}
+
+void hvf_kick_vcpu_thread(CPUState *cpu)
+{
+    hv_vcpus_exit(&cpu->hvf->fd, 1);
+}
+
+static void hvf_raise_exception(CPUState *cpu, uint32_t excp,
+                                uint32_t syndrome)
+{
+    ARMCPU *arm_cpu = ARM_CPU(cpu);
+    CPUARMState *env = &arm_cpu->env;
+
+    cpu->exception_index = excp;
+    env->exception.target_el = 1;
+    env->exception.syndrome = syndrome;
+
+    arm_cpu_do_interrupt(cpu);
+}
+
+static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
+{
+    ARMCPU *arm_cpu = ARM_CPU(cpu);
+    CPUARMState *env = &arm_cpu->env;
+    uint64_t val = 0;
+
+    switch (reg) {
+    case SYSREG_CNTPCT_EL0:
+        val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /
+              gt_cntfrq_period_ns(arm_cpu);
+        break;
+    case SYSREG_OSLSR_EL1:
+        val = env->cp15.oslsr_el1;
+        break;
+    case SYSREG_OSDLR_EL1:
+        /* Dummy register */
+        break;
+    default:
+        cpu_synchronize_state(cpu);
+        trace_hvf_unhandled_sysreg_read(env->pc, reg,
+                                        (reg >> 20) & 0x3,
+                                        (reg >> 14) & 0x7,
+                                        (reg >> 10) & 0xf,
+                                        (reg >> 1) & 0xf,
+                                        (reg >> 17) & 0x7);
+        hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
+        return 1;
+    }
+
+    trace_hvf_sysreg_read(reg,
+                          (reg >> 20) & 0x3,
+                          (reg >> 14) & 0x7,
+                          (reg >> 10) & 0xf,
+                          (reg >> 1) & 0xf,
+                          (reg >> 17) & 0x7,
+                          val);
+    hvf_set_reg(cpu, rt, val);
+
+    return 0;
+}
+
+static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
+{
+    ARMCPU *arm_cpu = ARM_CPU(cpu);
+    CPUARMState *env = &arm_cpu->env;
+
+    trace_hvf_sysreg_write(reg,
+                           (reg >> 20) & 0x3,
+                           (reg >> 14) & 0x7,
+                           (reg >> 10) & 0xf,
+                           (reg >> 1) & 0xf,
+                           (reg >> 17) & 0x7,
+                           val);
+
+    switch (reg) {
+    case SYSREG_OSLAR_EL1:
+        env->cp15.oslsr_el1 = val & 1;
+        break;
+    case SYSREG_OSDLR_EL1:
+        /* Dummy register */
+        break;
+    default:
+        cpu_synchronize_state(cpu);
+        trace_hvf_unhandled_sysreg_write(env->pc, reg,
+                                         (reg >> 20) & 0x3,
+                                         (reg >> 14) & 0x7,
+                                         (reg >> 10) & 0xf,
+                                         (reg >> 1) & 0xf,
+                                         (reg >> 17) & 0x7);
+        hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
+        return 1;
+    }
+
+    return 0;
+}
+
+static int hvf_inject_interrupts(CPUState *cpu)
+{
+    if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) {
+        trace_hvf_inject_fiq();
+        hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_FIQ,
+                                      true);
+    }
+
+    if (cpu->interrupt_request & CPU_INTERRUPT_HARD) {
+        trace_hvf_inject_irq();
+        hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_IRQ,
+                                      true);
+    }
+
+    return 0;
+}
+
+static uint64_t hvf_vtimer_val_raw(void)
+{
+    /*
+     * mach_absolute_time() returns the vtimer value without the VM
+     * offset that we define. Add our own offset on top.
+     */
+    return mach_absolute_time() - hvf_state->vtimer_offset;
+}
+
+static void hvf_sync_vtimer(CPUState *cpu)
+{
+    ARMCPU *arm_cpu = ARM_CPU(cpu);
+    hv_return_t r;
+    uint64_t ctl;
+    bool irq_state;
+
+    if (!cpu->hvf->vtimer_masked) {
+        /* We will get notified on vtimer changes by hvf, nothing to do */
+        return;
+    }
+
+    r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl);
+    assert_hvf_ok(r);
+
+    irq_state = (ctl & (TMR_CTL_ENABLE | TMR_CTL_IMASK | TMR_CTL_ISTATUS)) ==
+                (TMR_CTL_ENABLE | TMR_CTL_ISTATUS);
+    qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], irq_state);
+
+    if (!irq_state) {
+        /* Timer no longer asserting, we can unmask it */
+        hv_vcpu_set_vtimer_mask(cpu->hvf->fd, false);
+        cpu->hvf->vtimer_masked = false;
+    }
+}
+
+int hvf_vcpu_exec(CPUState *cpu)
+{
+    ARMCPU *arm_cpu = ARM_CPU(cpu);
+    CPUARMState *env = &arm_cpu->env;
+    hv_vcpu_exit_t *hvf_exit = cpu->hvf->exit;
+    hv_return_t r;
+    bool advance_pc = false;
+
+    if (hvf_inject_interrupts(cpu)) {
+        return EXCP_INTERRUPT;
+    }
+
+    if (cpu->halted) {
+        return EXCP_HLT;
+    }
+
+    flush_cpu_state(cpu);
+
+    qemu_mutex_unlock_iothread();
+    assert_hvf_ok(hv_vcpu_run(cpu->hvf->fd));
+
+    /* handle VMEXIT */
+    uint64_t exit_reason = hvf_exit->reason;
+    uint64_t syndrome = hvf_exit->exception.syndrome;
+    uint32_t ec = syn_get_ec(syndrome);
+
+    qemu_mutex_lock_iothread();
+    switch (exit_reason) {
+    case HV_EXIT_REASON_EXCEPTION:
+        /* This is the main one, handle below. */
+        break;
+    case HV_EXIT_REASON_VTIMER_ACTIVATED:
+        qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1);
+        cpu->hvf->vtimer_masked = true;
+        return 0;
+    case HV_EXIT_REASON_CANCELED:
+        /* we got kicked, no exit to process */
+        return 0;
+    default:
+        assert(0);
+    }
+
+    hvf_sync_vtimer(cpu);
+
+    switch (ec) {
+    case EC_DATAABORT: {
+        bool isv = syndrome & ARM_EL_ISV;
+        bool iswrite = (syndrome >> 6) & 1;
+        bool s1ptw = (syndrome >> 7) & 1;
+        uint32_t sas = (syndrome >> 22) & 3;
+        uint32_t len = 1 << sas;
+        uint32_t srt = (syndrome >> 16) & 0x1f;
+        uint64_t val = 0;
+
+        trace_hvf_data_abort(env->pc, hvf_exit->exception.virtual_address,
+                             hvf_exit->exception.physical_address, isv,
+                             iswrite, s1ptw, len, srt);
+
+        assert(isv);
+
+        if (iswrite) {
+            val = hvf_get_reg(cpu, srt);
+            address_space_write(&address_space_memory,
+                                hvf_exit->exception.physical_address,
+                                MEMTXATTRS_UNSPECIFIED, &val, len);
+        } else {
+            address_space_read(&address_space_memory,
+                               hvf_exit->exception.physical_address,
+                               MEMTXATTRS_UNSPECIFIED, &val, len);
+            hvf_set_reg(cpu, srt, val);
+        }
+
+        advance_pc = true;
+        break;
+    }
+    case EC_SYSTEMREGISTERTRAP: {
+        bool isread = (syndrome >> 0) & 1;
+        uint32_t rt = (syndrome >> 5) & 0x1f;
+        uint32_t reg = syndrome & SYSREG_MASK;
+        uint64_t val;
+        int ret = 0;
+
+        if (isread) {
+            ret = hvf_sysreg_read(cpu, reg, rt);
+        } else {
+            val = hvf_get_reg(cpu, rt);
+            ret = hvf_sysreg_write(cpu, reg, val);
+        }
+
+        advance_pc = !ret;
+        break;
+    }
+    case EC_WFX_TRAP:
+        advance_pc = true;
+        break;
+    case EC_AA64_HVC:
+        cpu_synchronize_state(cpu);
+        trace_hvf_unknown_hvc(env->xregs[0]);
+        /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */
+        env->xregs[0] = -1;
+        break;
+    case EC_AA64_SMC:
+        cpu_synchronize_state(cpu);
+        trace_hvf_unknown_smc(env->xregs[0]);
+        hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
+        break;
+    default:
+        cpu_synchronize_state(cpu);
+        trace_hvf_exit(syndrome, ec, env->pc);
+        error_report("0x%llx: unhandled exception ec=0x%x", env->pc, ec);
+    }
+
+    if (advance_pc) {
+        uint64_t pc;
+
+        flush_cpu_state(cpu);
+
+        r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_PC, &pc);
+        assert_hvf_ok(r);
+        pc += 4;
+        r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_PC, pc);
+        assert_hvf_ok(r);
+    }
+
+    return 0;
+}
+
+static const VMStateDescription vmstate_hvf_vtimer = {
+    .name = "hvf-vtimer",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64(vtimer_val, HVFVTimer),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+static void hvf_vm_state_change(void *opaque, bool running, RunState state)
+{
+    HVFVTimer *s = opaque;
+
+    if (running) {
+        /* Update vtimer offset on all CPUs */
+        hvf_state->vtimer_offset = mach_absolute_time() - s->vtimer_val;
+        cpu_synchronize_all_states();
+    } else {
+        /* Remember vtimer value on every pause */
+        s->vtimer_val = hvf_vtimer_val_raw();
+    }
+}
+
+int hvf_arch_init(void)
+{
+    hvf_state->vtimer_offset = mach_absolute_time();
+    vmstate_register(NULL, 0, &vmstate_hvf_vtimer, &vtimer);
+    qemu_add_vm_change_state_handler(hvf_vm_state_change, &vtimer);
+    return 0;
+}
diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
index XXXXXXX..XXXXXXX 100644
--- a/target/i386/hvf/hvf.c
+++ b/target/i386/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@ static inline bool apic_bus_freq_is_known(CPUX86State *env)
     return env->apic_bus_freq != 0;
 }
 
+void hvf_kick_vcpu_thread(CPUState *cpu)
+{
+    cpus_kick_thread(cpu);
+}
+
 int hvf_arch_init(void)
 {
     return 0;
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: accel/accel-*.c
 F: accel/Makefile.objs
 F: accel/stubs/Makefile.objs
 
+Apple Silicon HVF CPUs
+M: Alexander Graf <agraf@csgraf.de>
+S: Maintained
+F: target/arm/hvf/
+
 X86 HVF CPUs
 M: Cameron Esfahani <dirty@apple.com>
 M: Roman Bolshakov <r.bolshakov@yadro.com>
diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/hvf/trace-events
@@ -XXX,XX +XXX,XX @@
+hvf_unhandled_sysreg_read(uint64_t pc, uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2) "unhandled sysreg read at pc=0x%"PRIx64": 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d)"
+hvf_unhandled_sysreg_write(uint64_t pc, uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2) "unhandled sysreg write at pc=0x%"PRIx64": 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d)"
+hvf_inject_fiq(void) "injecting FIQ"
+hvf_inject_irq(void) "injecting IRQ"
+hvf_data_abort(uint64_t pc, uint64_t va, uint64_t pa, bool isv, bool iswrite, bool s1ptw, uint32_t len, uint32_t srt) "data abort: [pc=0x%"PRIx64" va=0x%016"PRIx64" pa=0x%016"PRIx64" isv=%d iswrite=%d s1ptw=%d len=%d srt=%d]"
+hvf_sysreg_read(uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg read 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d) = 0x%016"PRIx64
+hvf_sysreg_write(uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg write 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d, val=0x%016"PRIx64")"
+hvf_unknown_hvc(uint64_t x0) "unknown HVC! 0x%016"PRIx64
+hvf_unknown_smc(uint64_t x0) "unknown SMC! 0x%016"PRIx64
+hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [ec=0x%x pc=0x%"PRIx64"]"
-- 
2.20.1

From: Peter Collingbourne <pcc@google.com>

Sleep on WFI until the VTIMER is due but allow ourselves to be woken
up on IPI.

In this implementation IPI is blocked on the CPU thread at startup and
pselect() is used to atomically unblock the signal and begin sleeping.
The signal is sent unconditionally so there's no need to worry about
races between actually sleeping and the "we think we're sleeping"
state. It may lead to an extra wakeup but that's better than missing
it entirely.

Signed-off-by: Peter Collingbourne <pcc@google.com>
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Acked-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id: 20210916155404.86958-6-agraf@csgraf.de
[agraf: Remove unused 'set' variable, always advance PC on WFX trap,
        support vm stop / continue operations and cntv offsets]
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Acked-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/sysemu/hvf_int.h  |  1 +
 accel/hvf/hvf-accel-ops.c |  5 +--
 target/arm/hvf/hvf.c      | 79 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 82 insertions(+), 3 deletions(-)

diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/hvf_int.h
+++ b/include/sysemu/hvf_int.h
@@ -XXX,XX +XXX,XX @@ struct hvf_vcpu_state {
     uint64_t fd;
     void *exit;
     bool vtimer_masked;
+    sigset_t unblock_ipi_mask;
 };
 
 void assert_hvf_ok(hv_return_t ret);
diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/hvf/hvf-accel-ops.c
+++ b/accel/hvf/hvf-accel-ops.c
@@ -XXX,XX +XXX,XX @@ static int hvf_init_vcpu(CPUState *cpu)
     cpu->hvf = g_malloc0(sizeof(*cpu->hvf));
 
     /* init cpu signals */
-    sigset_t set;
     struct sigaction sigact;
 
     memset(&sigact, 0, sizeof(sigact));
     sigact.sa_handler = dummy_signal;
     sigaction(SIG_IPI, &sigact, NULL);
 
-    pthread_sigmask(SIG_BLOCK, NULL, &set);
-    sigdelset(&set, SIG_IPI);
+    pthread_sigmask(SIG_BLOCK, NULL, &cpu->hvf->unblock_ipi_mask);
+    sigdelset(&cpu->hvf->unblock_ipi_mask, SIG_IPI);
 
 #ifdef __aarch64__
     r = hv_vcpu_create(&cpu->hvf->fd, (hv_vcpu_exit_t **)&cpu->hvf->exit, NULL);
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@
  * QEMU Hypervisor.framework support for Apple Silicon
 
  * Copyright 2020 Alexander Graf <agraf@csgraf.de>
+ * Copyright 2020 Google LLC
  *
  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  * See the COPYING file in the top-level directory.
@@ -XXX,XX +XXX,XX @@ int hvf_arch_init_vcpu(CPUState *cpu)
 
 void hvf_kick_vcpu_thread(CPUState *cpu)
 {
+    cpus_kick_thread(cpu);
     hv_vcpus_exit(&cpu->hvf->fd, 1);
 }
 
@@ -XXX,XX +XXX,XX @@ static uint64_t hvf_vtimer_val_raw(void)
     return mach_absolute_time() - hvf_state->vtimer_offset;
 }
 
+static uint64_t hvf_vtimer_val(void)
+{
+    if (!runstate_is_running()) {
+        /* VM is paused, the vtimer value is in vtimer.vtimer_val */
+        return vtimer.vtimer_val;
+    }
+
+    return hvf_vtimer_val_raw();
+}
+
+static void hvf_wait_for_ipi(CPUState *cpu, struct timespec *ts)
+{
+    /*
+     * Use pselect to sleep so that other threads can IPI us while we're
+     * sleeping.
+     */
+    qatomic_mb_set(&cpu->thread_kicked, false);
+    qemu_mutex_unlock_iothread();
+    pselect(0, 0, 0, 0, ts, &cpu->hvf->unblock_ipi_mask);
+    qemu_mutex_lock_iothread();
+}
+
+static void hvf_wfi(CPUState *cpu)
+{
+    ARMCPU *arm_cpu = ARM_CPU(cpu);
+    struct timespec ts;
+    hv_return_t r;
+    uint64_t ctl;
+    uint64_t cval;
+    int64_t ticks_to_sleep;
+    uint64_t seconds;
+    uint64_t nanos;
+    uint32_t cntfrq;
+
+    if (cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ)) {
+        /* Interrupt pending, no need to wait */
+        return;
+    }
+
+    r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl);
+    assert_hvf_ok(r);
+
+    if (!(ctl & 1) || (ctl & 2)) {
+        /* Timer disabled or masked, just wait for an IPI. */
+        hvf_wait_for_ipi(cpu, NULL);
+        return;
+    }
+
+    r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CVAL_EL0, &cval);
+    assert_hvf_ok(r);
+
+    ticks_to_sleep = cval - hvf_vtimer_val();
+    if (ticks_to_sleep < 0) {
+        return;
+    }
+
+    cntfrq = gt_cntfrq_period_ns(arm_cpu);
+    seconds = muldiv64(ticks_to_sleep, cntfrq, NANOSECONDS_PER_SECOND);
+    ticks_to_sleep -= muldiv64(seconds, NANOSECONDS_PER_SECOND, cntfrq);
+    nanos = ticks_to_sleep * cntfrq;
+
+    /*
+     * Don't sleep for less than the time a context switch would take,
+     * so that we can satisfy fast timer requests on the same CPU.
+     * Measurements on M1 show the sweet spot to be ~2ms.
+     */
+    if (!seconds && nanos < (2 * SCALE_MS)) {
+        return;
+    }
+
+    ts = (struct timespec) { seconds, nanos };
+    hvf_wait_for_ipi(cpu, &ts);
+}
+
 static void hvf_sync_vtimer(CPUState *cpu)
 {
     ARMCPU *arm_cpu = ARM_CPU(cpu);
@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu)
     }
     case EC_WFX_TRAP:
         advance_pc = true;
+        if (!(syndrome & WFX_IS_WFE)) {
+            hvf_wfi(cpu);
+        }
         break;
     case EC_AA64_HVC:
         cpu_synchronize_state(cpu);
-- 
2.20.1

Now that we have working system register sync, we push more target CPU
properties into the virtual machine. That might be useful in some
situations, but is not the typical case that users want.

So let's add a -cpu host option that allows them to explicitly pass all
CPU capabilities of their host CPU into the guest.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Acked-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210916155404.86958-7-agraf@csgraf.de
[PMM: drop unnecessary #include line from .h file]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h     |  2 +
 target/arm/hvf_arm.h | 18 +++++++++
 target/arm/kvm_arm.h |  2 -
 target/arm/cpu.c     | 13 ++++--
 target/arm/hvf/hvf.c | 95 ++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 124 insertions(+), 6 deletions(-)
 create mode 100644 target/arm/hvf_arm.h

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU
 
+#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
+
 #define cpu_signal_handler cpu_arm_signal_handler
 #define cpu_list arm_cpu_list
 
diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/hvf_arm.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU Hypervisor.framework (HVF) support -- ARM specifics
+ *
+ * Copyright (c) 2021 Alexander Graf
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef QEMU_HVF_ARM_H
+#define QEMU_HVF_ARM_H
+
+#include "cpu.h"
+
+void hvf_arm_set_cpu_features_from_host(struct ARMCPU *cpu);
+
+#endif
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
  */
 void kvm_arm_destroy_scratch_host_vcpu(int *fdarray);
 
-#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
-
 /**
  * ARMHostCPUFeatures: information about the host CPU (identified
  * by asking the host kernel)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/tcg.h"
 #include "sysemu/hw_accel.h"
 #include "kvm_arm.h"
+#include "hvf_arm.h"
 #include "disas/capstone.h"
 #include "fpu/softfloat.h"
 
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
      * this is the first point where we can report it.
      */
     if (cpu->host_cpu_probe_failed) {
-        if (!kvm_enabled()) {
-            error_setg(errp, "The 'host' CPU type can only be used with KVM");
+        if (!kvm_enabled() && !hvf_enabled()) {
+            error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF");
         } else {
             error_setg(errp, "Failed to retrieve host CPU features");
         }
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
 #endif /* CONFIG_TCG */
 }
 
-#ifdef CONFIG_KVM
+#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
 static void arm_host_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
 
+#ifdef CONFIG_KVM
     kvm_arm_set_cpu_features_from_host(cpu);
     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
         aarch64_add_sve_properties(obj);
     }
+#else
+    hvf_arm_set_cpu_features_from_host(cpu);
+#endif
     arm_cpu_post_init(obj);
 }
 
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void)
 {
     type_register_static(&arm_cpu_type_info);
 
-#ifdef CONFIG_KVM
+#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
     type_register_static(&host_arm_cpu_type_info);
 #endif
 }
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/hvf.h"
 #include "sysemu/hvf_int.h"
 #include "sysemu/hw_accel.h"
+#include "hvf_arm.h"
 
 #include <mach/mach_time.h>
 
@@ -XXX,XX +XXX,XX @@ typedef struct HVFVTimer {
 
 static HVFVTimer vtimer;
 
+typedef struct ARMHostCPUFeatures {
+    ARMISARegisters isar;
+    uint64_t features;
+    uint64_t midr;
+    uint32_t reset_sctlr;
+    const char *dtb_compatible;
+} ARMHostCPUFeatures;
+
+static ARMHostCPUFeatures arm_host_cpu_features;
+
 struct hvf_reg_match {
     int reg;
     uint64_t offset;
@@ -XXX,XX +XXX,XX @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt)
     return val;
 }
 
+static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
+{
+    ARMISARegisters host_isar = {};
+    const struct isar_regs {
+        int reg;
+        uint64_t *val;
+    } regs[] = {
+        { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 },
+        { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 },
+        { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 },
+        { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 },
+        { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 },
+        { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 },
+        { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 },
+        { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 },
+        { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 },
+    };
+    hv_vcpu_t fd;
+    hv_return_t r = HV_SUCCESS;
+    hv_vcpu_exit_t *exit;
+    int i;
+
+    ahcf->dtb_compatible = "arm,arm-v8";
+    ahcf->features = (1ULL << ARM_FEATURE_V8) |
+                     (1ULL << ARM_FEATURE_NEON) |
+                     (1ULL << ARM_FEATURE_AARCH64) |
+                     (1ULL << ARM_FEATURE_PMU) |
+                     (1ULL << ARM_FEATURE_GENERIC_TIMER);
+
+    /* We set up a small vcpu to extract host registers */
+
+    if (hv_vcpu_create(&fd, &exit, NULL) != HV_SUCCESS) {
+        return false;
+    }
+
+    for (i = 0; i < ARRAY_SIZE(regs); i++) {
+        r |= hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val);
+    }
+    r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr);
+    r |= hv_vcpu_destroy(fd);
+
+    ahcf->isar = host_isar;
+
+    /*
+     * A scratch vCPU returns SCTLR 0, so let's fill our default with the M1
+     * boot SCTLR from https://github.com/AsahiLinux/m1n1/issues/97
+     */
+    ahcf->reset_sctlr = 0x30100180;
+    /*
+     * SPAN is disabled by default when SCTLR.SPAN=1. To improve compatibility,
+     * let's disable it on boot and then allow guest software to turn it on by
+     * setting it to 0.
+     */
+    ahcf->reset_sctlr |= 0x00800000;
+
+    /* Make sure we don't advertise AArch32 support for EL0/EL1 */
+    if ((host_isar.id_aa64pfr0 & 0xff) != 0x11) {
+        return false;
+    }
+
+    return r == HV_SUCCESS;
+}
+
+void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu)
+{
+    if (!arm_host_cpu_features.dtb_compatible) {
+        if (!hvf_enabled() ||
+            !hvf_arm_get_host_cpu_features(&arm_host_cpu_features)) {
+            /*
+             * We can't report this error yet, so flag that we need to
+             * in arm_cpu_realizefn().
+             */
+            cpu->host_cpu_probe_failed = true;
+            return;
+        }
+    }
+
+    cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible;
+    cpu->isar = arm_host_cpu_features.isar;
+    cpu->env.features = arm_host_cpu_features.features;
+    cpu->midr = arm_host_cpu_features.midr;
+    cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr;
+}
+
 void hvf_arch_vcpu_destroy(CPUState *cpu)
 {
 }
-- 
2.20.1

From: Alexander Graf <agraf@csgraf.de>

We need to handle PSCI calls. Most of the TCG code works for us,
but we can simplify it to only handle aa64 mode and we need to
handle SUSPEND differently.

This patch takes the TCG code as template and duplicates it in HVF.

To tell the guest that we support PSCI 0.2 now, update the check in
arm_cpu_initfn() as well.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210916155404.86958-8-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c            |   4 +-
 target/arm/hvf/hvf.c        | 141 ++++++++++++++++++++++++++++++++++--
 target/arm/hvf/trace-events |   1 +
 3 files changed, 139 insertions(+), 7 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 
-    if (tcg_enabled()) {
-        cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
+    if (tcg_enabled() || hvf_enabled()) {
+        cpu->psci_version = 2; /* TCG and HVF implement PSCI 0.2 */
     }
 }
 
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/irq.h"
 #include "qemu/main-loop.h"
 #include "sysemu/cpus.h"
+#include "arm-powerctl.h"
 #include "target/arm/cpu.h"
 #include "target/arm/internals.h"
 #include "trace/trace-target_arm_hvf.h"
@@ -XXX,XX +XXX,XX @@
 #define TMR_CTL_IMASK   (1 << 1)
 #define TMR_CTL_ISTATUS (1 << 2)
 
+static void hvf_wfi(CPUState *cpu);
+
 typedef struct HVFVTimer {
     /* Vtimer value during migration and paused state */
     uint64_t vtimer_val;
@@ -XXX,XX +XXX,XX @@ static void hvf_raise_exception(CPUState *cpu, uint32_t excp,
     arm_cpu_do_interrupt(cpu);
 }
 
+static void hvf_psci_cpu_off(ARMCPU *arm_cpu)
+{
+    int32_t ret = arm_set_cpu_off(arm_cpu->mp_affinity);
+    assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS);
+}
+
+/*
+ * Handle a PSCI call.
+ *
+ * Returns 0 on success
+ *         -1 when the PSCI call is unknown,
+ */
+static bool hvf_handle_psci_call(CPUState *cpu)
+{
+    ARMCPU *arm_cpu = ARM_CPU(cpu);
+    CPUARMState *env = &arm_cpu->env;
+    uint64_t param[4] = {
+        env->xregs[0],
+        env->xregs[1],
+        env->xregs[2],
+        env->xregs[3]
+    };
+    uint64_t context_id, mpidr;
+    bool target_aarch64 = true;
+    CPUState *target_cpu_state;
+    ARMCPU *target_cpu;
+    target_ulong entry;
+    int target_el = 1;
+    int32_t ret = 0;
+
+    trace_hvf_psci_call(param[0], param[1], param[2], param[3],
+                        arm_cpu->mp_affinity);
+
+    switch (param[0]) {
+    case QEMU_PSCI_0_2_FN_PSCI_VERSION:
+        ret = QEMU_PSCI_0_2_RET_VERSION_0_2;
+        break;
+    case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
+        ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */
+        break;
+    case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
+    case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
+        mpidr = param[1];
+
+        switch (param[2]) {
+        case 0:
+            target_cpu_state = arm_get_cpu_by_id(mpidr);
+            if (!target_cpu_state) {
+                ret = QEMU_PSCI_RET_INVALID_PARAMS;
+                break;
+            }
+            target_cpu = ARM_CPU(target_cpu_state);
+
+            ret = target_cpu->power_state;
+            break;
+        default:
+            /* Everything above affinity level 0 is always on. */
+            ret = 0;
+        }
+        break;
+    case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
+        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+        /*
+         * QEMU reset and shutdown are async requests, but PSCI
+         * mandates that we never return from the reset/shutdown
+         * call, so power the CPU off now so it doesn't execute
+         * anything further.
+         */
+        hvf_psci_cpu_off(arm_cpu);
+        break;
+    case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
+        qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+        hvf_psci_cpu_off(arm_cpu);
+        break;
+    case QEMU_PSCI_0_1_FN_CPU_ON:
+    case QEMU_PSCI_0_2_FN_CPU_ON:
+    case QEMU_PSCI_0_2_FN64_CPU_ON:
+        mpidr = param[1];
+        entry = param[2];
+        context_id = param[3];
+        ret = arm_set_cpu_on(mpidr, entry, context_id,
+                             target_el, target_aarch64);
+        break;
+    case QEMU_PSCI_0_1_FN_CPU_OFF:
+    case QEMU_PSCI_0_2_FN_CPU_OFF:
+        hvf_psci_cpu_off(arm_cpu);
+        break;
+    case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
+    case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
+    case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
+        /* Affinity levels are not supported in QEMU */
+        if (param[1] & 0xfffe0000) {
+            ret = QEMU_PSCI_RET_INVALID_PARAMS;
+            break;
+        }
+        /* Powerdown is not supported, we always go into WFI */
+        env->xregs[0] = 0;
+        hvf_wfi(cpu);
+        break;
+    case QEMU_PSCI_0_1_FN_MIGRATE:
+    case QEMU_PSCI_0_2_FN_MIGRATE:
+        ret = QEMU_PSCI_RET_NOT_SUPPORTED;
+        break;
+    default:
+        return false;
+    }
+
+    env->xregs[0] = ret;
+    return true;
+}
+
 static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
 {
     ARMCPU *arm_cpu = ARM_CPU(cpu);
@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu)
         break;
     case EC_AA64_HVC:
         cpu_synchronize_state(cpu);
-        trace_hvf_unknown_hvc(env->xregs[0]);
-        /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */
-        env->xregs[0] = -1;
+        if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_HVC) {
+            if (!hvf_handle_psci_call(cpu)) {
+                trace_hvf_unknown_hvc(env->xregs[0]);
+                /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */
+                env->xregs[0] = -1;
+            }
+        } else {
+            trace_hvf_unknown_hvc(env->xregs[0]);
+            hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
+        }
         break;
     case EC_AA64_SMC:
         cpu_synchronize_state(cpu);
-        trace_hvf_unknown_smc(env->xregs[0]);
-        hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
+        if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_SMC) {
+            advance_pc = true;
+
+            if (!hvf_handle_psci_call(cpu)) {
+                trace_hvf_unknown_smc(env->xregs[0]);
+                /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */
+                env->xregs[0] = -1;
+            }
+        } else {
+            trace_hvf_unknown_smc(env->xregs[0]);
+            hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
+        }
         break;
     default:
         cpu_synchronize_state(cpu);
diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/hvf/trace-events
+++ b/target/arm/hvf/trace-events
@@ -XXX,XX +XXX,XX @@ hvf_sysreg_write(uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_
 hvf_unknown_hvc(uint64_t x0) "unknown HVC! 0x%016"PRIx64
 hvf_unknown_smc(uint64_t x0) "unknown SMC! 0x%016"PRIx64
 hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [ec=0x%x pc=0x%"PRIx64"]"
+hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t cpuid) "PSCI Call x0=0x%016"PRIx64" x1=0x%016"PRIx64" x2=0x%016"PRIx64" x3=0x%016"PRIx64" cpu=0x%x"
-- 
2.20.1

From: Alexander Graf <agraf@csgraf.de>

Now that we have all logic in place that we need to handle Hypervisor.framework
on Apple Silicon systems, let's add CONFIG_HVF for aarch64 as well so that we
can build it.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
Tested-by: Roman Bolshakov <r.bolshakov@yadro.com> (x86 only)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id: 20210916155404.86958-9-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 meson.build                | 7 +++++++
 target/arm/hvf/meson.build | 3 +++
 target/arm/meson.build     | 2 ++
 3 files changed, 12 insertions(+)
 create mode 100644 target/arm/hvf/meson.build

diff --git a/meson.build b/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/meson.build
+++ b/meson.build
@@ -XXX,XX +XXX,XX @@ else
 endif
 
 accelerator_targets = { 'CONFIG_KVM': kvm_targets }
+
+if cpu in ['aarch64']
+  accelerator_targets += {
+    'CONFIG_HVF': ['aarch64-softmmu']
+  }
+endif
+
 if cpu in ['x86', 'x86_64', 'arm', 'aarch64']
   # i386 emulator provides xenpv machine type for multiple architectures
   accelerator_targets += {
diff --git a/target/arm/hvf/meson.build b/target/arm/hvf/meson.build
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/hvf/meson.build
@@ -XXX,XX +XXX,XX @@
+arm_softmmu_ss.add(when: [hvf, 'CONFIG_HVF'], if_true: files(
+  'hvf.c',
+))
diff --git a/target/arm/meson.build b/target/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_softmmu_ss.add(files(
   'psci.c',
 ))
 
+subdir('hvf')
+
 target_arch += {'arm': arm_ss}
 target_softmmu_arch += {'arm': arm_softmmu_ss}
-- 
2.20.1

From: Alexander Graf <agraf@csgraf.de>

We can expose cycle counters on the PMU easily. To be as compatible as
possible, let's do so, but make sure we don't expose any other architectural
counters that we can not model yet.

This allows OSs to work that require PMU support.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210916155404.86958-10-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/hvf/hvf.c | 179 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 179 insertions(+)

diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@
 #define SYSREG_OSLSR_EL1      SYSREG(2, 0, 1, 1, 4)
 #define SYSREG_OSDLR_EL1      SYSREG(2, 0, 1, 3, 4)
 #define SYSREG_CNTPCT_EL0     SYSREG(3, 3, 14, 0, 1)
+#define SYSREG_PMCR_EL0       SYSREG(3, 3, 9, 12, 0)
+#define SYSREG_PMUSERENR_EL0  SYSREG(3, 3, 9, 14, 0)
+#define SYSREG_PMCNTENSET_EL0 SYSREG(3, 3, 9, 12, 1)
+#define SYSREG_PMCNTENCLR_EL0 SYSREG(3, 3, 9, 12, 2)
+#define SYSREG_PMINTENCLR_EL1 SYSREG(3, 0, 9, 14, 2)
+#define SYSREG_PMOVSCLR_EL0   SYSREG(3, 3, 9, 12, 3)
+#define SYSREG_PMSWINC_EL0    SYSREG(3, 3, 9, 12, 4)
+#define SYSREG_PMSELR_EL0     SYSREG(3, 3, 9, 12, 5)
+#define SYSREG_PMCEID0_EL0    SYSREG(3, 3, 9, 12, 6)
+#define SYSREG_PMCEID1_EL0    SYSREG(3, 3, 9, 12, 7)
+#define SYSREG_PMCCNTR_EL0    SYSREG(3, 3, 9, 13, 0)
+#define SYSREG_PMCCFILTR_EL0  SYSREG(3, 3, 14, 15, 7)
 
 #define WFX_IS_WFE (1 << 0)
 
@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
         val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /
               gt_cntfrq_period_ns(arm_cpu);
         break;
+    case SYSREG_PMCR_EL0:
+        val = env->cp15.c9_pmcr;
+        break;
+    case SYSREG_PMCCNTR_EL0:
+        pmu_op_start(env);
+        val = env->cp15.c15_ccnt;
+        pmu_op_finish(env);
+        break;
+    case SYSREG_PMCNTENCLR_EL0:
+        val = env->cp15.c9_pmcnten;
+        break;
+    case SYSREG_PMOVSCLR_EL0:
+        val = env->cp15.c9_pmovsr;
+        break;
+    case SYSREG_PMSELR_EL0:
+        val = env->cp15.c9_pmselr;
+        break;
+    case SYSREG_PMINTENCLR_EL1:
+        val = env->cp15.c9_pminten;
+        break;
+    case SYSREG_PMCCFILTR_EL0:
+        val = env->cp15.pmccfiltr_el0;
+        break;
+    case SYSREG_PMCNTENSET_EL0:
+        val = env->cp15.c9_pmcnten;
+        break;
+    case SYSREG_PMUSERENR_EL0:
+        val = env->cp15.c9_pmuserenr;
+        break;
+    case SYSREG_PMCEID0_EL0:
+    case SYSREG_PMCEID1_EL0:
+        /* We can't really count anything yet, declare all events invalid */
+        val = 0;
+        break;
     case SYSREG_OSLSR_EL1:
         val = env->cp15.oslsr_el1;
         break;
@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
     return 0;
 }
 
+static void pmu_update_irq(CPUARMState *env)
+{
+    ARMCPU *cpu = env_archcpu(env);
+    qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) &&
+            (env->cp15.c9_pminten & env->cp15.c9_pmovsr));
+}
+
+static bool pmu_event_supported(uint16_t number)
+{
+    return false;
+}
+
+/* Returns true if the counter (pass 31 for PMCCNTR) should count events using
+ * the current EL, security state, and register configuration.
+ */
+static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
+{
+    uint64_t filter;
+    bool enabled, filtered = true;
+    int el = arm_current_el(env);
+
+    enabled = (env->cp15.c9_pmcr & PMCRE) &&
+              (env->cp15.c9_pmcnten & (1 << counter));
+
+    if (counter == 31) {
+        filter = env->cp15.pmccfiltr_el0;
+    } else {
+        filter = env->cp15.c14_pmevtyper[counter];
+    }
+
+    if (el == 0) {
+        filtered = filter & PMXEVTYPER_U;
+    } else if (el == 1) {
+        filtered = filter & PMXEVTYPER_P;
+    }
+
+    if (counter != 31) {
+        /*
+         * If not checking PMCCNTR, ensure the counter is setup to an event we
+         * support
+         */
+        uint16_t event = filter & PMXEVTYPER_EVTCOUNT;
+        if (!pmu_event_supported(event)) {
+            return false;
+        }
+    }
+
+    return enabled && !filtered;
+}
+
+static void pmswinc_write(CPUARMState *env, uint64_t value)
+{
+    unsigned int i;
+    for (i = 0; i < pmu_num_counters(env); i++) {
+        /* Increment a counter's count iff: */
+        if ((value & (1 << i)) && /* counter's bit is set */
+                /* counter is enabled and not filtered */
+                pmu_counter_enabled(env, i) &&
+                /* counter is SW_INCR */
+                (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) {
+            /*
+             * Detect if this write causes an overflow since we can't predict
+             * PMSWINC overflows like we can for other events
+             */
+            uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1;
+
+            if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) {
+                env->cp15.c9_pmovsr |= (1 << i);
+                pmu_update_irq(env);
+            }
+
+            env->cp15.c14_pmevcntr[i] = new_pmswinc;
+        }
+    }
+}
+
 static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
 {
     ARMCPU *arm_cpu = ARM_CPU(cpu);
@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
                            val);
 
     switch (reg) {
+    case SYSREG_PMCCNTR_EL0:
+        pmu_op_start(env);
+        env->cp15.c15_ccnt = val;
+        pmu_op_finish(env);
+        break;
+    case SYSREG_PMCR_EL0:
+        pmu_op_start(env);
+
+        if (val & PMCRC) {
+            /* The counter has been reset */
+            env->cp15.c15_ccnt = 0;
+        }
+
+        if (val & PMCRP) {
+            unsigned int i;
+            for (i = 0; i < pmu_num_counters(env); i++) {
+                env->cp15.c14_pmevcntr[i] = 0;
+            }
+        }
+
+        env->cp15.c9_pmcr &= ~PMCR_WRITEABLE_MASK;
+        env->cp15.c9_pmcr |= (val & PMCR_WRITEABLE_MASK);
+
+        pmu_op_finish(env);
+        break;
+    case SYSREG_PMUSERENR_EL0:
+        env->cp15.c9_pmuserenr = val & 0xf;
+        break;
+    case SYSREG_PMCNTENSET_EL0:
+        env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env));
+        break;
+    case SYSREG_PMCNTENCLR_EL0:
+        env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env));
+        break;
+    case SYSREG_PMINTENCLR_EL1:
+        pmu_op_start(env);
+        env->cp15.c9_pminten |= val;
+        pmu_op_finish(env);
+        break;
+    case SYSREG_PMOVSCLR_EL0:
+        pmu_op_start(env);
+        env->cp15.c9_pmovsr &= ~val;
+        pmu_op_finish(env);
+        break;
+    case SYSREG_PMSWINC_EL0:
+        pmu_op_start(env);
+        pmswinc_write(env, val);
+        pmu_op_finish(env);
+        break;
+    case SYSREG_PMSELR_EL0:
+        env->cp15.c9_pmselr = val & 0x1f;
+        break;
+    case SYSREG_PMCCFILTR_EL0:
+        pmu_op_start(env);
+        env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0;
+        pmu_op_finish(env);
+        break;
     case SYSREG_OSLAR_EL1:
         env->cp15.oslsr_el1 = val & 1;
         break;
-- 
2.20.1

Currently gen_jmp_tb() assumes that if it is called then the jump it
is handling is the only reason that we might be trying to end the TB,
so it will use goto_tb if it can.  This is usually the case: mostly
"we did something that means we must end the TB" happens on a
non-branch instruction.  However, there are cases where we decide
early in handling an instruction that we need to end the TB and
return to the main loop, and then the insn is a complex one that
involves gen_jmp_tb().  For instance, for M-profile FP instructions,
in gen_preserve_fp_state() which is called from vfp_access_check() we
want to force an exit to the main loop if lazy state preservation is
active and we are in icount mode.

Make gen_jmp_tb() look at the current value of is_jmp, and only use
goto_tb if the previous is_jmp was DISAS_NEXT or DISAS_TOO_MANY.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-2-peter.maydell@linaro.org
---
 target/arm/translate.c | 34 +++++++++++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
         /* An indirect jump so that we still trigger the debug exception.  */
         gen_set_pc_im(s, dest);
         s->base.is_jmp = DISAS_JUMP;
-    } else {
+        return;
+    }
+    switch (s->base.is_jmp) {
+    case DISAS_NEXT:
+    case DISAS_TOO_MANY:
+    case DISAS_NORETURN:
+        /*
+         * The normal case: just go to the destination TB.
+         * NB: NORETURN happens if we generate code like
+         *    gen_brcondi(l);
+         *    gen_jmp();
+         *    gen_set_label(l);
+         *    gen_jmp();
+         * on the second call to gen_jmp().
+         */
         gen_goto_tb(s, tbno, dest);
+        break;
+    case DISAS_UPDATE_NOCHAIN:
+    case DISAS_UPDATE_EXIT:
+        /*
+         * We already decided we're leaving the TB for some other reason.
+         * Avoid using goto_tb so we really do exit back to the main loop
+         * and don't chain to another TB.
+         */
+        gen_set_pc_im(s, dest);
+        gen_goto_ptr();
+        s->base.is_jmp = DISAS_NORETURN;
+        break;
+    default:
+        /*
+         * We shouldn't be emitting code for a jump and also have
+         * is_jmp set to one of the special cases like DISAS_SWI.
+         */
+        g_assert_not_reached();
     }
 }
 
-- 
2.20.1

Architecturally, for an M-profile CPU with the LOB feature the
LTPSIZE field in FPDSCR is always constant 4.  QEMU's implementation
enforces this everywhere, except that we don't check that it is true
in incoming migration data.

We're going to add come in gen_update_fp_context() which relies on
the "always 4" property.  Since this is TCG-only, we don't actually
need to be robust to bogus incoming migration data, and the effect of
it being wrong would be wrong code generation rather than a QEMU
crash; but if it did ever happen somehow it would be very difficult
to track down the cause.  Add a check so that we fail the inbound
migration if the FPDSCR.LTPSIZE value is incorrect.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-3-peter.maydell@linaro.org
---
 target/arm/machine.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/target/arm/machine.c b/target/arm/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
     hw_breakpoint_update_all(cpu);
     hw_watchpoint_update_all(cpu);
 
+    /*
+     * TCG gen_update_fp_context() relies on the invariant that
+     * FPDSCR.LTPSIZE is constant 4 for M-profile with the LOB extension;
+     * forbid bogus incoming data with some other value.
+     */
+    if (arm_feature(env, ARM_FEATURE_M) && cpu_isar_feature(aa32_lob, cpu)) {
+        if (extract32(env->v7m.fpdscr[M_REG_NS],
+                      FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4 ||
+            extract32(env->v7m.fpdscr[M_REG_S],
+                      FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4) {
+            return -1;
+        }
+    }
     if (!kvm_enabled()) {
         pmu_op_finish(&cpu->env);
     }
-- 
2.20.1

Our current codegen for MVE always calls out to helper functions,
because some byte lanes might be predicated.  The common case is that
in fact there is no predication active and all lanes should be
updated together, so we can produce better code by detecting that and
using the TCG generic vector infrastructure.

Add a TB flag that is set when we can guarantee that there is no
active MVE predication, and a bool in the DisasContext.  Subsequent
patches will use this flag to generate improved code for some
instructions.

In most cases when the predication state changes we simply end the TB
after that instruction.  For the code called from vfp_access_check()
that handles lazy state preservation and creating a new FP context,
we can usually avoid having to try to end the TB because luckily the
new value of the flag following the register changes in those
sequences doesn't depend on any runtime decisions.  We do have to end
the TB if the guest has enabled lazy FP state preservation but not
automatic state preservation, but this is an odd corner case that is
not going to be common in real-world code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-4-peter.maydell@linaro.org
---
 target/arm/cpu.h              |  4 +++-
 target/arm/translate.h        |  2 ++
 target/arm/helper.c           | 33 +++++++++++++++++++++++++++++++++
 target/arm/translate-m-nocp.c |  8 +++++++-
 target/arm/translate-mve.c    | 13 ++++++++++++-
 target/arm/translate-vfp.c    | 33 +++++++++++++++++++++++++++------
 target/arm/translate.c        |  8 ++++++++
 7 files changed, 92 insertions(+), 9 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef ARMCPU ArchCPU;
  * | TBFLAG_AM32 |          +-----+----------+
  * |             |                |TBFLAG_M32|
  * +-------------+----------------+----------+
- *  31         23                5 4        0
+ *  31         23                6 5        0
  *
  * Unless otherwise noted, these bits are cached in env->hflags.
  */
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_M32, LSPACT, 2, 1)                 /* Not cached. */
 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1)     /* Not cached. */
 /* Set if FPCCR.S does not match current security state */
 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1)          /* Not cached. */
+/* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */
+FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1)            /* Not cached. */
 
 /*
  * Bit usage when in AArch64 state
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     bool align_mem;
     /* True if PSTATE.IL is set */
     bool pstate_il;
+    /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */
+    bool mve_no_pred;
     /*
      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
      *  < 0, set by the current instruction.
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static inline void assert_hflags_rebuild_correctly(CPUARMState *env)
 #endif
 }
 
+static bool mve_no_pred(CPUARMState *env)
+{
+    /*
+     * Return true if there is definitely no predication of MVE
+     * instructions by VPR or LTPSIZE. (Returning false even if there
+     * isn't any predication is OK; generated code will just be
+     * a little worse.)
+     * If the CPU does not implement MVE then this TB flag is always 0.
+     *
+     * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
+     * logic in gen_update_fp_context() needs to be updated to match.
+     *
+     * We do not include the effect of the ECI bits here -- they are
+     * tracked in other TB flags. This simplifies the logic for
+     * "when did we emit code that changes the MVE_NO_PRED TB flag
+     * and thus need to end the TB?".
+     */
+    if (cpu_isar_feature(aa32_mve, env_archcpu(env))) {
+        return false;
+    }
+    if (env->v7m.vpr) {
+        return false;
+    }
+    if (env->v7m.ltpsize < 4) {
+        return false;
+    }
+    return true;
+}
+
 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
                           target_ulong *cs_base, uint32_t *pflags)
 {
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
             if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) {
                 DP_TBFLAG_M32(flags, LSPACT, 1);
             }
+
+            if (mve_no_pred(env)) {
+                DP_TBFLAG_M32(flags, MVE_NO_PRED, 1);
+            }
         } else {
             /*
              * Note that XSCALE_CPAR shares bits with VECSTRIDE.
diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-m-nocp.c
+++ b/target/arm/translate-m-nocp.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
 
     clear_eci_state(s);
 
-    /* End the TB, because we have updated FP control bits */
+    /*
+     * End the TB, because we have updated FP control bits,
+     * and possibly VPR or LTPSIZE.
+     */
     s->base.is_jmp = DISAS_UPDATE_EXIT;
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
         store_cpu_field(control, v7m.control[M_REG_S]);
         tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
         gen_helper_vfp_set_fpscr(cpu_env, tmp);
+        s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
         tcg_temp_free_i32(tmp);
         tcg_temp_free_i32(sfpa);
         break;
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
         }
         tmp = loadfn(s, opaque, true);
         store_cpu_field(tmp, v7m.vpr);
+        s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
         break;
     case ARM_VFP_P0:
     {
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
         tcg_gen_deposit_i32(vpr, vpr, tmp,
                             R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH);
         store_cpu_field(vpr, v7m.vpr);
+        s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
         tcg_temp_free_i32(tmp);
         break;
     }
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_LOGIC(VORR, gen_helper_mve_vorr)
 DO_LOGIC(VORN, gen_helper_mve_vorn)
 DO_LOGIC(VEOR, gen_helper_mve_veor)
 
-DO_LOGIC(VPSEL, gen_helper_mve_vpsel)
+static bool trans_VPSEL(DisasContext *s, arg_2op *a)
+{
+    /* This insn updates predication bits */
+    s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
+    return do_2op(s, a, gen_helper_mve_vpsel);
+}
 
 #define DO_2OP(INSN, FN) \
     static bool trans_##INSN(DisasContext *s, arg_2op *a)       \
@@ -XXX,XX +XXX,XX @@ static bool trans_VPNOT(DisasContext *s, arg_VPNOT *a)
     }
 
     gen_helper_mve_vpnot(cpu_env);
+    /* This insn updates predication bits */
+    s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
     mve_update_eci(s);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool do_vcmp(DisasContext *s, arg_vcmp *a, MVEGenCmpFn *fn)
         /* VPT */
         gen_vpst(s, a->mask);
     }
+    /* This insn updates predication bits */
+    s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
     mve_update_eci(s);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool do_vcmp_scalar(DisasContext *s, arg_vcmp_scalar *a,
         /* VPT */
         gen_vpst(s, a->mask);
     }
+    /* This insn updates predication bits */
+    s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
     mve_update_eci(s);
     return true;
 }
diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.c
+++ b/target/arm/translate-vfp.c
@@ -XXX,XX +XXX,XX @@ static inline long vfp_f16_offset(unsigned reg, bool top)
  * Generate code for M-profile lazy FP state preservation if needed;
  * this corresponds to the pseudocode PreserveFPState() function.
  */
-static void gen_preserve_fp_state(DisasContext *s)
+static void gen_preserve_fp_state(DisasContext *s, bool skip_context_update)
 {
     if (s->v7m_lspact) {
         /*
@@ -XXX,XX +XXX,XX @@ static void gen_preserve_fp_state(DisasContext *s)
          * any further FP insns in this TB.
          */
         s->v7m_lspact = false;
+        /*
+         * The helper might have zeroed VPR, so we do not know the
+         * correct value for the MVE_NO_PRED TB flag any more.
+         * If we're about to create a new fp context then that
+         * will precisely determine the MVE_NO_PRED value (see
+         * gen_update_fp_context()). Otherwise, we must:
+         *  - set s->mve_no_pred to false, so this instruction
+         *    is generated to use helper functions
+         *  - end the TB now, without chaining to the next TB
+         */
+        if (skip_context_update || !s->v7m_new_fp_ctxt_needed) {
+            s->mve_no_pred = false;
+            s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
+        }
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_update_fp_context(DisasContext *s)
             TCGv_i32 z32 = tcg_const_i32(0);
             store_cpu_field(z32, v7m.vpr);
         }
-
         /*
-         * We don't need to arrange to end the TB, because the only
-         * parts of FPSCR which we cache in the TB flags are the VECLEN
-         * and VECSTRIDE, and those don't exist for M-profile.
+         * We just updated the FPSCR and VPR. Some of this state is cached
+         * in the MVE_NO_PRED TB flag. We want to avoid having to end the
+         * TB here, which means we need the new value of the MVE_NO_PRED
+         * flag to be exactly known here and the same for all executions.
+         * Luckily FPDSCR.LTPSIZE is always constant 4 and the VPR is
+         * always set to 0, so the new MVE_NO_PRED flag is always 1
+         * if and only if we have MVE.
+         *
+         * (The other FPSCR state cached in TB flags is VECLEN and VECSTRIDE,
+         * but those do not exist for M-profile, so are not relevant here.)
          */
+        s->mve_no_pred = dc_isar_feature(aa32_mve, s);
 
         if (s->v8m_secure) {
             bits |= R_V7M_CONTROL_SFPA_MASK;
@@ -XXX,XX +XXX,XX @@ bool vfp_access_check_m(DisasContext *s, bool skip_context_update)
     /* Handle M-profile lazy FP state mechanics */
 
     /* Trigger lazy-state preservation if necessary */
-    gen_preserve_fp_state(s);
+    gen_preserve_fp_state(s, skip_context_update);
 
     if (!skip_context_update) {
         /* Update ownership of FP context and create new FP context if needed */
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_DLS(DisasContext *s, arg_DLS *a)
         /* DLSTP: set FPSCR.LTPSIZE */
         tmp = tcg_const_i32(a->size);
         store_cpu_field(tmp, v7m.ltpsize);
+        s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
     }
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
         assert(ok);
         tmp = tcg_const_i32(a->size);
         store_cpu_field(tmp, v7m.ltpsize);
+        /*
+         * LTPSIZE updated, but MVE_NO_PRED will always be the same thing (0)
+         * when we take this upcoming exit from this TB, so gen_jmp_tb() is OK.
+         */
     }
     gen_jmp_tb(s, s->base.pc_next, 1);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_VCTP(DisasContext *s, arg_VCTP *a)
     gen_helper_mve_vctp(cpu_env, masklen);
     tcg_temp_free_i32(masklen);
     tcg_temp_free_i32(rn_shifted);
+    /* This insn updates predication bits */
+    s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
     mve_update_eci(s);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
         dc->v7m_new_fp_ctxt_needed =
             EX_TBFLAG_M32(tb_flags, NEW_FP_CTXT_NEEDED);
         dc->v7m_lspact = EX_TBFLAG_M32(tb_flags, LSPACT);
+        dc->mve_no_pred = EX_TBFLAG_M32(tb_flags, MVE_NO_PRED);
     } else {
         dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL);
         dc->sctlr_b = EX_TBFLAG_A32(tb_flags, SCTLR__B);
-- 
2.20.1

When not predicating, implement the MVE bitwise logical insns
directly using TCG vector operations.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-5-peter.maydell@linaro.org
---
 target/arm/translate-mve.c | 51 +++++++++++++++++++++++++++-----------
 1 file changed, 36 insertions(+), 15 deletions(-)

diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ static TCGv_ptr mve_qreg_ptr(unsigned reg)
     return ret;
 }
 
+static bool mve_no_predication(DisasContext *s)
+{
+    /*
+     * Return true if we are executing the entire MVE instruction
+     * with no predication or partial-execution, and so we can safely
+     * use an inline TCG vector implementation.
+     */
+    return s->eci == 0 && s->mve_no_pred;
+}
+
 static bool mve_check_qreg_bank(DisasContext *s, int qmask)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static bool trans_VNEG_fp(DisasContext *s, arg_1op *a)
     return do_1op(s, a, fns[a->size]);
 }
 
-static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn)
+static bool do_2op_vec(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn,
+                       GVecGen3Fn *vecfn)
 {
     TCGv_ptr qd, qn, qm;
 
@@ -XXX,XX +XXX,XX @@ static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn)
         return true;
     }
 
-    qd = mve_qreg_ptr(a->qd);
-    qn = mve_qreg_ptr(a->qn);
-    qm = mve_qreg_ptr(a->qm);
-    fn(cpu_env, qd, qn, qm);
-    tcg_temp_free_ptr(qd);
-    tcg_temp_free_ptr(qn);
-    tcg_temp_free_ptr(qm);
+    if (vecfn && mve_no_predication(s)) {
+        vecfn(a->size, mve_qreg_offset(a->qd), mve_qreg_offset(a->qn),
+              mve_qreg_offset(a->qm), 16, 16);
+    } else {
+        qd = mve_qreg_ptr(a->qd);
+        qn = mve_qreg_ptr(a->qn);
+        qm = mve_qreg_ptr(a->qm);
+        fn(cpu_env, qd, qn, qm);
+        tcg_temp_free_ptr(qd);
+        tcg_temp_free_ptr(qn);
+        tcg_temp_free_ptr(qm);
+    }
     mve_update_eci(s);
     return true;
 }
 
-#define DO_LOGIC(INSN, HELPER)                                  \
+static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn *fn)
+{
+    return do_2op_vec(s, a, fn, NULL);
+}
+
+#define DO_LOGIC(INSN, HELPER, VECFN)                           \
     static bool trans_##INSN(DisasContext *s, arg_2op *a)       \
     {                                                           \
-        return do_2op(s, a, HELPER);                            \
+        return do_2op_vec(s, a, HELPER, VECFN);                 \
     }
 
-DO_LOGIC(VAND, gen_helper_mve_vand)
-DO_LOGIC(VBIC, gen_helper_mve_vbic)
-DO_LOGIC(VORR, gen_helper_mve_vorr)
-DO_LOGIC(VORN, gen_helper_mve_vorn)
-DO_LOGIC(VEOR, gen_helper_mve_veor)
+DO_LOGIC(VAND, gen_helper_mve_vand, tcg_gen_gvec_and)
+DO_LOGIC(VBIC, gen_helper_mve_vbic, tcg_gen_gvec_andc)
+DO_LOGIC(VORR, gen_helper_mve_vorr, tcg_gen_gvec_or)
+DO_LOGIC(VORN, gen_helper_mve_vorn, tcg_gen_gvec_orc)
+DO_LOGIC(VEOR, gen_helper_mve_veor, tcg_gen_gvec_xor)
 
 static bool trans_VPSEL(DisasContext *s, arg_2op *a)
 {
-- 
2.20.1

Optimize MVE arithmetic ops when we have a TCG
vector operation we can use.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-6-peter.maydell@linaro.org
---
 target/arm/translate-mve.c | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

Optimize the MVE VNEG and VABS insns by using TCG
vector ops when possible.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-7-peter.maydell@linaro.org
---
 target/arm/translate-mve.c | 32 ++++++++++++++++++++++----------
 1 file changed, 22 insertions(+), 10 deletions(-)

Optimize the MVE VDUP insns by using TCG vector ops when possible.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-8-peter.maydell@linaro.org
---
 target/arm/translate-mve.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
         return true;
     }
 
-    qd = mve_qreg_ptr(a->qd);
     rt = load_reg(s, a->rt);
-    tcg_gen_dup_i32(a->size, rt, rt);
-    gen_helper_mve_vdup(cpu_env, qd, rt);
-    tcg_temp_free_ptr(qd);
+    if (mve_no_predication(s)) {
+        tcg_gen_gvec_dup_i32(a->size, mve_qreg_offset(a->qd), 16, 16, rt);
+    } else {
+        qd = mve_qreg_ptr(a->qd);
+        tcg_gen_dup_i32(a->size, rt, rt);
+        gen_helper_mve_vdup(cpu_env, qd, rt);
+        tcg_temp_free_ptr(qd);
+    }
     tcg_temp_free_i32(rt);
     mve_update_eci(s);
     return true;
-- 
2.20.1

Optimize the MVE VSHL and VSHR immediate forms by using TCG vector
ops when possible.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-10-peter.maydell@linaro.org
---
 target/arm/translate-mve.c | 83 +++++++++++++++++++++++++++++---------
 1 file changed, 63 insertions(+), 20 deletions(-)

diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
     return do_1imm(s, a, fn);
 }
 
-static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
-                      bool negateshift)
+static bool do_2shift_vec(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
+                          bool negateshift, GVecGen2iFn vecfn)
 {
     TCGv_ptr qd, qm;
     int shift = a->shift;
@@ -XXX,XX +XXX,XX @@ static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
         shift = -shift;
     }
 
-    qd = mve_qreg_ptr(a->qd);
-    qm = mve_qreg_ptr(a->qm);
-    fn(cpu_env, qd, qm, tcg_constant_i32(shift));
-    tcg_temp_free_ptr(qd);
-    tcg_temp_free_ptr(qm);
+    if (vecfn && mve_no_predication(s)) {
+        vecfn(a->size, mve_qreg_offset(a->qd), mve_qreg_offset(a->qm),
+              shift, 16, 16);
+    } else {
+        qd = mve_qreg_ptr(a->qd);
+        qm = mve_qreg_ptr(a->qm);
+        fn(cpu_env, qd, qm, tcg_constant_i32(shift));
+        tcg_temp_free_ptr(qd);
+        tcg_temp_free_ptr(qm);
+    }
     mve_update_eci(s);
     return true;
 }
 
-#define DO_2SHIFT(INSN, FN, NEGATESHIFT)                         \
-    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
-    {                                                           \
-        static MVEGenTwoOpShiftFn * const fns[] = {             \
-            gen_helper_mve_##FN##b,                             \
-            gen_helper_mve_##FN##h,                             \
-            gen_helper_mve_##FN##w,                             \
-            NULL,                                               \
-        };                                                      \
-        return do_2shift(s, a, fns[a->size], NEGATESHIFT);      \
+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
+                      bool negateshift)
+{
+    return do_2shift_vec(s, a, fn, negateshift, NULL);
+}
+
+#define DO_2SHIFT_VEC(INSN, FN, NEGATESHIFT, VECFN)                     \
+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)            \
+    {                                                                   \
+        static MVEGenTwoOpShiftFn * const fns[] = {                     \
+            gen_helper_mve_##FN##b,                                     \
+            gen_helper_mve_##FN##h,                                     \
+            gen_helper_mve_##FN##w,                                     \
+            NULL,                                                       \
+        };                                                              \
+        return do_2shift_vec(s, a, fns[a->size], NEGATESHIFT, VECFN);   \
     }
 
-DO_2SHIFT(VSHLI, vshli_u, false)
+#define DO_2SHIFT(INSN, FN, NEGATESHIFT)        \
+    DO_2SHIFT_VEC(INSN, FN, NEGATESHIFT, NULL)
+
+static void do_gvec_shri_s(unsigned vece, uint32_t dofs, uint32_t aofs,
+                           int64_t shift, uint32_t oprsz, uint32_t maxsz)
+{
+    /*
+     * We get here with a negated shift count, and we must handle
+     * shifts by the element size, which tcg_gen_gvec_sari() does not do.
+     */
+    shift = -shift;
+    if (shift == (8 << vece)) {
+        shift--;
+    }
+    tcg_gen_gvec_sari(vece, dofs, aofs, shift, oprsz, maxsz);
+}
+
+static void do_gvec_shri_u(unsigned vece, uint32_t dofs, uint32_t aofs,
+                           int64_t shift, uint32_t oprsz, uint32_t maxsz)
+{
+    /*
+     * We get here with a negated shift count, and we must handle
+     * shifts by the element size, which tcg_gen_gvec_shri() does not do.
+     */
+    shift = -shift;
+    if (shift == (8 << vece)) {
+        tcg_gen_gvec_dup_imm(vece, dofs, oprsz, maxsz, 0);
+    } else {
+        tcg_gen_gvec_shri(vece, dofs, aofs, shift, oprsz, maxsz);
+    }
+}
+
+DO_2SHIFT_VEC(VSHLI, vshli_u, false, tcg_gen_gvec_shli)
 DO_2SHIFT(VQSHLI_S, vqshli_s, false)
 DO_2SHIFT(VQSHLI_U, vqshli_u, false)
 DO_2SHIFT(VQSHLUI, vqshlui_s, false)
 /* These right shifts use a left-shift helper with negated shift count */
-DO_2SHIFT(VSHRI_S, vshli_s, true)
-DO_2SHIFT(VSHRI_U, vshli_u, true)
+DO_2SHIFT_VEC(VSHRI_S, vshli_s, true, do_gvec_shri_s)
+DO_2SHIFT_VEC(VSHRI_U, vshli_u, true, do_gvec_shri_u)
 DO_2SHIFT(VRSHRI_S, vrshli_s, true)
 DO_2SHIFT(VRSHRI_U, vrshli_u, true)
 
-- 
2.20.1

Optimize the MVE VSHLL insns by using TCG vector ops when possible.
This includes the VMOVL insn, which we handle in mve.decode as "VSHLL
with zero shift count".

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-11-peter.maydell@linaro.org
---
 target/arm/translate-mve.c | 67 +++++++++++++++++++++++++++++++++-----
 1 file changed, 59 insertions(+), 8 deletions(-)

diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SCALAR(VQSHL_U_scalar, vqshli_u)
 DO_2SHIFT_SCALAR(VQRSHL_S_scalar, vqrshli_s)
 DO_2SHIFT_SCALAR(VQRSHL_U_scalar, vqrshli_u)
 
-#define DO_VSHLL(INSN, FN)                                      \
-    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
-    {                                                           \
-        static MVEGenTwoOpShiftFn * const fns[] = {             \
-            gen_helper_mve_##FN##b,                             \
-            gen_helper_mve_##FN##h,                             \
-        };                                                      \
-        return do_2shift(s, a, fns[a->size], false);            \
+#define DO_VSHLL(INSN, FN)                                              \
+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)            \
+    {                                                                   \
+        static MVEGenTwoOpShiftFn * const fns[] = {                     \
+            gen_helper_mve_##FN##b,                                     \
+            gen_helper_mve_##FN##h,                                     \
+        };                                                              \
+        return do_2shift_vec(s, a, fns[a->size], false, do_gvec_##FN);  \
     }
 
+/*
+ * For the VSHLL vector helpers, the vece is the size of the input
+ * (ie MO_8 or MO_16); the helpers want to work in the output size.
+ * The shift count can be 0..<input size>, inclusive. (0 is VMOVL.)
+ */
+static void do_gvec_vshllbs(unsigned vece, uint32_t dofs, uint32_t aofs,
+                            int64_t shift, uint32_t oprsz, uint32_t maxsz)
+{
+    unsigned ovece = vece + 1;
+    unsigned ibits = vece == MO_8 ? 8 : 16;
+    tcg_gen_gvec_shli(ovece, dofs, aofs, ibits, oprsz, maxsz);
+    tcg_gen_gvec_sari(ovece, dofs, dofs, ibits - shift, oprsz, maxsz);
+}
+
+static void do_gvec_vshllbu(unsigned vece, uint32_t dofs, uint32_t aofs,
+                            int64_t shift, uint32_t oprsz, uint32_t maxsz)
+{
+    unsigned ovece = vece + 1;
+    tcg_gen_gvec_andi(ovece, dofs, aofs,
+                      ovece == MO_16 ? 0xff : 0xffff, oprsz, maxsz);
+    tcg_gen_gvec_shli(ovece, dofs, dofs, shift, oprsz, maxsz);
+}
+
+static void do_gvec_vshllts(unsigned vece, uint32_t dofs, uint32_t aofs,
+                            int64_t shift, uint32_t oprsz, uint32_t maxsz)
+{
+    unsigned ovece = vece + 1;
+    unsigned ibits = vece == MO_8 ? 8 : 16;
+    if (shift == 0) {
+        tcg_gen_gvec_sari(ovece, dofs, aofs, ibits, oprsz, maxsz);
+    } else {
+        tcg_gen_gvec_andi(ovece, dofs, aofs,
+                          ovece == MO_16 ? 0xff00 : 0xffff0000, oprsz, maxsz);
+        tcg_gen_gvec_sari(ovece, dofs, dofs, ibits - shift, oprsz, maxsz);
+    }
+}
+
+static void do_gvec_vshlltu(unsigned vece, uint32_t dofs, uint32_t aofs,
+                            int64_t shift, uint32_t oprsz, uint32_t maxsz)
+{
+    unsigned ovece = vece + 1;
+    unsigned ibits = vece == MO_8 ? 8 : 16;
+    if (shift == 0) {
+        tcg_gen_gvec_shri(ovece, dofs, aofs, ibits, oprsz, maxsz);
+    } else {
+        tcg_gen_gvec_andi(ovece, dofs, aofs,
+                          ovece == MO_16 ? 0xff00 : 0xffff0000, oprsz, maxsz);
+        tcg_gen_gvec_shri(ovece, dofs, dofs, ibits - shift, oprsz, maxsz);
+    }
+}
+
 DO_VSHLL(VSHLL_BS, vshllbs)
 DO_VSHLL(VSHLL_BU, vshllbu)
 DO_VSHLL(VSHLL_TS, vshllts)
-- 
2.20.1

Optimize the MVE 1op-immediate insns (VORR, VBIC, VMOV) to
use TCG vector ops when possible.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-13-peter.maydell@linaro.org
---
 target/arm/translate-mve.c | 26 +++++++++++++++++++++-----
 1 file changed, 21 insertions(+), 5 deletions(-)