The following changes since commit 6eeea6725a70e6fcb5abba0764496bdab07ddfb3:

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-10-06' into staging (2020-10-06 21:13:34 +0100)

https://github.com/rth7680/qemu.git tags/pull-tcg-20201008

for you to fetch changes up to 62475e9d007d83db4d0a6ccebcda8914f392e9c9:

accel/tcg: Fix computing of is_write for MIPS (2020-10-08 05:57:32 -0500)

Extend maximum gvec vector size

Fix i386 avx2 dupi

Fix mips host user-only write detection

Misc cleanups.

Kele Huang (1):

accel/tcg: Fix computing of is_write for MIPS

Richard Henderson (10):

tcg: Adjust simd_desc size encoding

tcg: Drop union from TCGArgConstraint

tcg: Move sorted_args into TCGArgConstraint.sort_index

tcg: Remove TCG_CT_REG

tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields

tcg: Remove TCGOpDef.used

tcg/i386: Fix dupi for avx2 32-bit hosts

tcg: Fix generation of dupi_vec for 32-bit host

tcg/optimize: Fold dup2_vec

tcg: Remove TCG_TARGET_HAS_cmp_vec

With larger vector sizes, it turns out oprsz == maxsz, and we only

need to represent mismatch for oprsz <= 32. We do, however, need

to represent larger oprsz and do so without reducing SIMD_DATA_BITS.

Reduce the size of the oprsz field and increase the maxsz field.

Steal the oprsz value of 24 to indicate equality with maxsz.

Tested-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

include/tcg/tcg-gvec-desc.h | 38 ++++++++++++++++++++++++-------------

tcg/tcg-op-gvec.c | 35 ++++++++++++++++++++++++++--------

2 files changed, 52 insertions(+), 21 deletions(-)

diff --git a/include/tcg/tcg-gvec-desc.h b/include/tcg/tcg-gvec-desc.h

--- a/include/tcg/tcg-gvec-desc.h

+++ b/include/tcg/tcg-gvec-desc.h

@@ -XXX,XX +XXX,XX @@

#ifndef TCG_TCG_GVEC_DESC_H

#define TCG_TCG_GVEC_DESC_H

-/* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vectors. */

-#define SIMD_OPRSZ_SHIFT 0

-#define SIMD_OPRSZ_BITS 5

+/*

+ * This configuration allows MAXSZ to represent 2048 bytes, and

+ * OPRSZ to match MAXSZ, or represent the smaller values 8, 16, or 32.

+ *

+ * Encode this with:

+ * 0, 1, 3 -> 8, 16, 32

+ * 2 -> maxsz

+ *

+ * This steals the input that would otherwise map to 24 to match maxsz.

+ */

+#define SIMD_MAXSZ_SHIFT 0

+#define SIMD_MAXSZ_BITS 8

-#define SIMD_MAXSZ_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)

-#define SIMD_MAXSZ_BITS 5

+#define SIMD_OPRSZ_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)

+#define SIMD_OPRSZ_BITS 2

-#define SIMD_DATA_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)

+#define SIMD_DATA_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)

#define SIMD_DATA_BITS (32 - SIMD_DATA_SHIFT)

/* Create a descriptor from components. */

uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data);

-/* Extract the operation size from a descriptor. */

-static inline intptr_t simd_oprsz(uint32_t desc)

-{

- return (extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS) + 1) * 8;

-}

-

/* Extract the max vector size from a descriptor. */

static inline intptr_t simd_maxsz(uint32_t desc)

- return (extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) + 1) * 8;

+ return extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) * 8 + 8;

+}

+

+/* Extract the operation size from a descriptor. */

+static inline intptr_t simd_oprsz(uint32_t desc)

+{

+ uint32_t f = extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS);

+ intptr_t o = f * 8 + 8;

+ intptr_t m = simd_maxsz(desc);

+ return f == 2 ? m : o;

2.25.1

These are easier to set and test when they have their own fields.

Reduce the size of alias_index and sort_index to 4 bits, which is

sufficient for TCG_MAX_OP_ARGS. This leaves only the bits indicating

constants within the ct field.

Move all initialization to allocation time, rather than init

individual fields in process_op_defs.

include/tcg/tcg.h | 14 +++++++-------

tcg/tcg.c | 28 ++++++++++++----------------

2 files changed, 19 insertions(+), 23 deletions(-)

diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h

--- a/include/tcg/tcg.h

+++ b/include/tcg/tcg.h

@@ -XXX,XX +XXX,XX @@ int64_t tcg_cpu_exec_time(void);

void tcg_dump_info(void);

void tcg_dump_op_count(void);

-#define TCG_CT_ALIAS 0x80

-#define TCG_CT_IALIAS 0x40

-#define TCG_CT_NEWREG 0x20 /* output requires a new register */

-#define TCG_CT_CONST 0x02 /* any constant of register size */

+#define TCG_CT_CONST 1 /* any constant of register size */

typedef struct TCGArgConstraint {

- uint16_t ct;

- uint8_t alias_index;

- uint8_t sort_index;

+ unsigned ct : 16;

+ unsigned alias_index : 4;

+ unsigned sort_index : 4;

+ bool oalias : 1;

+ bool ialias : 1;

+ bool newreg : 1;

TCGRegSet regs;

} TCGArgConstraint;

diff --git a/tcg/tcg.c b/tcg/tcg.c

--- a/tcg/tcg.c

+++ b/tcg/tcg.c

@@ -XXX,XX +XXX,XX @@ void tcg_context_init(TCGContext *s)

total_args += n;

- args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);

+ args_ct = g_new0(TCGArgConstraint, total_args);

for(op = 0; op < NB_OPS; op++) {

def = &tcg_op_defs[op];

@@ -XXX,XX +XXX,XX @@ static int get_constraint_priority(const TCGOpDef *def, int k)

const TCGArgConstraint *arg_ct = &def->args_ct[k];

int n;

- if (arg_ct->ct & TCG_CT_ALIAS) {

+ if (arg_ct->oalias) {