1
A last handful of patches before the rc0. These are all bugfixes
1
Mostly just bug fixes. The important one here is
2
so they could equally well go into rc1, but since my pullreq
2
hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
3
queue is otherwise empty I might as well push them out. The
3
which fixes a buffer overrun that's a security issue if you're running
4
FPSCR bugfix is definitely one I'd like in rc0; the rest are
4
KVM on Arm with kernel-irqchip=off (which hopefully nobody is doing in
5
not really user-visible I think.
5
a security context, because kernel-irqchip=on is the default and the
6
sensible choice for performance).
6
7
7
thanks
8
-- PMM
8
-- PMM
9
9
10
The following changes since commit c4107e8208d0222f9b328691b519aaee4101db87:
10
The following changes since commit cf7ca7d5b9faca13f1f8e3ea92cfb2f741eb0c0e:
11
11
12
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2019-07-08 10:26:18 +0100)
12
Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/tracing-pull-request' into staging (2021-02-01 16:28:00 +0000)
13
13
14
are available in the Git repository at:
14
are available in the Git repository at:
15
15
16
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190708
16
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210202-1
17
17
18
for you to fetch changes up to 85795187f416326f87177cabc39fae1911f04c50:
18
for you to fetch changes up to 14657850c9cc10948551fbb884c30eb5a3a7370a:
19
19
20
target/arm/vfp_helper: Call set_fpscr_to_host before updating to FPSCR (2019-07-08 14:11:31 +0100)
20
hw/arm: Display CPU type in machine description (2021-02-02 17:53:44 +0000)
21
21
22
----------------------------------------------------------------
22
----------------------------------------------------------------
23
target-arm queue:
23
target-arm queue:
24
* tests/migration-test: Fix read off end of aarch64_kernel array
24
* hw/intc/arm_gic: Allow to use QTest without crashing
25
* Fix sve_zcr_len_for_el off-by-one error
25
* hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled
26
* hw/arm/sbsa-ref: Silence Coverity nit
26
* hw/char/exynos4210_uart: Fix missing call to report ready for input
27
* vfp_helper: Call set_fpscr_to_host before updating to FPSCR
27
* hw/arm/smmuv3: Fix addr_mask for range-based invalidation
28
* hw/ssi/imx_spi: Fix various minor bugs
29
* hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
30
* hw/arm: Add missing Kconfig dependencies
31
* hw/arm: Display CPU type in machine description
28
32
29
----------------------------------------------------------------
33
----------------------------------------------------------------
30
Peter Maydell (2):
34
Bin Meng (5):
31
tests/migration-test: Fix read off end of aarch64_kernel array
35
hw/ssi: imx_spi: Use a macro for number of chip selects supported
32
hw/arm/sbsa-ref: Remove unnecessary check for secure_sysmem == NULL
36
hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset()
37
hw/ssi: imx_spi: Round up the burst length to be multiple of 8
38
hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic
39
hw/ssi: imx_spi: Correct tx and rx fifo endianness
33
40
34
Philippe Mathieu-Daudé (1):
41
Iris Johnson (2):
35
target/arm/vfp_helper: Call set_fpscr_to_host before updating to FPSCR
42
hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled
43
hw/char/exynos4210_uart: Fix missing call to report ready for input
36
44
37
Richard Henderson (1):
45
Philippe Mathieu-Daudé (12):
38
target/arm: Fix sve_zcr_len_for_el
46
hw/intc/arm_gic: Allow to use QTest without crashing
47
hw/ssi: imx_spi: Remove pointless variable initialization
48
hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value
49
hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled
50
hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled
51
hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
52
hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ
53
hw/arm/exynos4210: Add missing dependency on OR_IRQ
54
hw/arm/xlnx-versal: Versal SoC requires ZDMA
55
hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals
56
hw/net/can: ZynqMP CAN device requires PTIMER
57
hw/arm: Display CPU type in machine description
39
58
40
hw/arm/sbsa-ref.c | 8 ++------
59
Xuzhou Cheng (1):
41
target/arm/helper.c | 4 ++--
60
hw/ssi: imx_spi: Disable chip selects when controller is disabled
42
target/arm/vfp_helper.c | 4 ++--
43
tests/migration-test.c | 22 +++++++---------------
44
4 files changed, 13 insertions(+), 25 deletions(-)
45
61
62
Zenghui Yu (1):
63
hw/arm/smmuv3: Fix addr_mask for range-based invalidation
64
65
include/hw/ssi/imx_spi.h | 5 +-
66
hw/arm/digic_boards.c | 2 +-
67
hw/arm/microbit.c | 2 +-
68
hw/arm/netduino2.c | 2 +-
69
hw/arm/netduinoplus2.c | 2 +-
70
hw/arm/orangepi.c | 2 +-
71
hw/arm/smmuv3.c | 4 +-
72
hw/arm/stellaris.c | 4 +-
73
hw/char/exynos4210_uart.c | 7 ++-
74
hw/intc/arm_gic.c | 5 +-
75
hw/ssi/imx_spi.c | 153 +++++++++++++++++++++++++++++-----------------
76
hw/Kconfig | 1 +
77
hw/arm/Kconfig | 5 ++
78
hw/dma/Kconfig | 3 +
79
hw/dma/meson.build | 2 +-
80
15 files changed, 130 insertions(+), 69 deletions(-)
81
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
Alexander reported an issue in gic_get_current_cpu() using the
4
fuzzer. Yet another "deref current_cpu with QTest" bug, reproducible
5
doing:
6
7
$ echo readb 0xf03ff000 | qemu-system-arm -M npcm750-evb,accel=qtest -qtest stdio
8
[I 1611849440.651452] OPENED
9
[R +0.242498] readb 0xf03ff000
10
hw/intc/arm_gic.c:63:29: runtime error: member access within null pointer of type 'CPUState' (aka 'struct CPUState')
11
SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior hw/intc/arm_gic.c:63:29 in
12
AddressSanitizer:DEADLYSIGNAL
13
=================================================================
14
==3719691==ERROR: AddressSanitizer: SEGV on unknown address 0x0000000082a0 (pc 0x5618790ac882 bp 0x7ffca946f4f0 sp 0x7ffca946f4a0 T0)
15
==3719691==The signal is caused by a READ memory access.
16
#0 0x5618790ac882 in gic_get_current_cpu hw/intc/arm_gic.c:63:29
17
#1 0x5618790a8901 in gic_dist_readb hw/intc/arm_gic.c:955:11
18
#2 0x5618790a7489 in gic_dist_read hw/intc/arm_gic.c:1158:17
19
#3 0x56187adc573b in memory_region_read_with_attrs_accessor softmmu/memory.c:464:9
20
#4 0x56187ad7903a in access_with_adjusted_size softmmu/memory.c:552:18
21
#5 0x56187ad766d6 in memory_region_dispatch_read1 softmmu/memory.c:1426:16
22
#6 0x56187ad758a8 in memory_region_dispatch_read softmmu/memory.c:1449:9
23
#7 0x56187b09e84c in flatview_read_continue softmmu/physmem.c:2822:23
24
#8 0x56187b0a0115 in flatview_read softmmu/physmem.c:2862:12
25
#9 0x56187b09fc9e in address_space_read_full softmmu/physmem.c:2875:18
26
#10 0x56187aa88633 in address_space_read include/exec/memory.h:2489:18
27
#11 0x56187aa88633 in qtest_process_command softmmu/qtest.c:558:13
28
#12 0x56187aa81881 in qtest_process_inbuf softmmu/qtest.c:797:9
29
#13 0x56187aa80e02 in qtest_read softmmu/qtest.c:809:5
30
31
current_cpu is NULL because QTest accelerator does not use CPU.
32
33
Fix by skipping the check and returning the first CPU index when
34
QTest accelerator is used, similarly to commit c781a2cc423
35
("hw/i386/vmport: Allow QTest use without crashing").
36
37
Reported-by: Alexander Bulekov <alxndr@bu.edu>
38
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
39
Reviewed-by: Darren Kenny <darren.kenny@oracle.com>
40
Reviewed-by: Alexander Bulekov <alxndr@bu.edu>
41
Message-id: 20210128161417.3726358-1-philmd@redhat.com
42
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
43
---
44
hw/intc/arm_gic.c | 3 ++-
45
1 file changed, 2 insertions(+), 1 deletion(-)
46
47
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/hw/intc/arm_gic.c
50
+++ b/hw/intc/arm_gic.c
51
@@ -XXX,XX +XXX,XX @@
52
#include "qemu/module.h"
53
#include "trace.h"
54
#include "sysemu/kvm.h"
55
+#include "sysemu/qtest.h"
56
57
/* #define DEBUG_GIC */
58
59
@@ -XXX,XX +XXX,XX @@ static const uint8_t gic_id_gicv2[] = {
60
61
static inline int gic_get_current_cpu(GICState *s)
62
{
63
- if (s->num_cpu > 1) {
64
+ if (!qtest_enabled() && s->num_cpu > 1) {
65
return current_cpu->cpu_index;
66
}
67
return 0;
68
--
69
2.20.1
70
71
diff view generated by jsdifflib
New patch
1
From: Iris Johnson <iris@modwiz.com>
1
2
3
Currently the Exynos 4210 UART code always reports available FIFO space
4
when the backend checks for buffer space. When the FIFO is disabled this
5
is behavior causes the backend chardev code to replace the data before the
6
guest can read it.
7
8
This patch changes adds the logic to report the capacity properly when the
9
FIFO is not being used.
10
11
Buglink: https://bugs.launchpad.net/qemu/+bug/1913344
12
Signed-off-by: Iris Johnson <iris@modwiz.com>
13
Message-id: 20210128033655.1029577-1-iris@modwiz.com
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/char/exynos4210_uart.c | 6 +++++-
18
1 file changed, 5 insertions(+), 1 deletion(-)
19
20
diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/char/exynos4210_uart.c
23
+++ b/hw/char/exynos4210_uart.c
24
@@ -XXX,XX +XXX,XX @@ static int exynos4210_uart_can_receive(void *opaque)
25
{
26
Exynos4210UartState *s = (Exynos4210UartState *)opaque;
27
28
- return fifo_empty_elements_number(&s->rx);
29
+ if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
30
+ return fifo_empty_elements_number(&s->rx);
31
+ } else {
32
+ return !(s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY);
33
+ }
34
}
35
36
static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size)
37
--
38
2.20.1
39
40
diff view generated by jsdifflib
New patch
1
From: Iris Johnson <iris@modwiz.com>
1
2
3
When the frontend device has no space for a read the fd is removed
4
from polling to allow time for the guest to read and clear the buffer.
5
Without the call to qemu_chr_fe_accept_input(), the poll will not be
6
broken out of when the guest has cleared the buffer causing significant
7
IO delays that get worse with smaller buffers.
8
9
Buglink: https://bugs.launchpad.net/qemu/+bug/1913341
10
Signed-off-by: Iris Johnson <iris@modwiz.com>
11
Message-id: 20210130184016.1787097-1-iris@modwiz.com
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/char/exynos4210_uart.c | 1 +
16
1 file changed, 1 insertion(+)
17
18
diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/char/exynos4210_uart.c
21
+++ b/hw/char/exynos4210_uart.c
22
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,
23
s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
24
res = s->reg[I_(URXH)];
25
}
26
+ qemu_chr_fe_accept_input(&s->chr);
27
exynos4210_uart_update_dmabusy(s);
28
trace_exynos_uart_read(s->channel, offset,
29
exynos4210_uart_regname(offset), res);
30
--
31
2.20.1
32
33
diff view generated by jsdifflib
New patch
1
From: Zenghui Yu <yuzenghui@huawei.com>
1
2
3
When handling guest range-based IOTLB invalidation, we should decode the TG
4
field into the corresponding translation granule size so that we can pass
5
the correct invalidation range to backend. Set @granule to (tg * 2 + 10) to
6
properly emulate the architecture.
7
8
Fixes: d52915616c05 ("hw/arm/smmuv3: Get prepared for range invalidation")
9
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
10
Acked-by: Eric Auger <eric.auger@redhat.com>
11
Message-id: 20210130043220.1345-1-yuzenghui@huawei.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/smmuv3.c | 4 +++-
15
1 file changed, 3 insertions(+), 1 deletion(-)
16
17
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/smmuv3.c
20
+++ b/hw/arm/smmuv3.c
21
@@ -XXX,XX +XXX,XX @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
22
{
23
SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
24
IOMMUTLBEvent event;
25
- uint8_t granule = tg;
26
+ uint8_t granule;
27
28
if (!tg) {
29
SMMUEventInfo event = {.inval_ste_allowed = true};
30
@@ -XXX,XX +XXX,XX @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
31
return;
32
}
33
granule = tt->granule_sz;
34
+ } else {
35
+ granule = tg * 2 + 10;
36
}
37
38
event.type = IOMMU_NOTIFIER_UNMAP;
39
--
40
2.20.1
41
42
diff view generated by jsdifflib
New patch
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
Avoid using a magic number (4) everywhere for the number of chip
4
selects supported.
5
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Juan Quintela <quintela@redhat.com>
10
Message-id: 20210129132323.30946-2-bmeng.cn@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/hw/ssi/imx_spi.h | 5 ++++-
14
hw/ssi/imx_spi.c | 4 ++--
15
2 files changed, 6 insertions(+), 3 deletions(-)
16
17
diff --git a/include/hw/ssi/imx_spi.h b/include/hw/ssi/imx_spi.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/ssi/imx_spi.h
20
+++ b/include/hw/ssi/imx_spi.h
21
@@ -XXX,XX +XXX,XX @@
22
23
#define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH)
24
25
+/* number of chip selects supported */
26
+#define ECSPI_NUM_CS 4
27
+
28
#define TYPE_IMX_SPI "imx.spi"
29
OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI)
30
31
@@ -XXX,XX +XXX,XX @@ struct IMXSPIState {
32
33
qemu_irq irq;
34
35
- qemu_irq cs_lines[4];
36
+ qemu_irq cs_lines[ECSPI_NUM_CS];
37
38
SSIBus *bus;
39
40
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/ssi/imx_spi.c
43
+++ b/hw/ssi/imx_spi.c
44
@@ -XXX,XX +XXX,XX @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
45
46
/* We are in master mode */
47
48
- for (i = 0; i < 4; i++) {
49
+ for (i = 0; i < ECSPI_NUM_CS; i++) {
50
qemu_set_irq(s->cs_lines[i],
51
i == imx_spi_selected_channel(s) ? 0 : 1);
52
}
53
@@ -XXX,XX +XXX,XX @@ static void imx_spi_realize(DeviceState *dev, Error **errp)
54
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
55
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
56
57
- for (i = 0; i < 4; ++i) {
58
+ for (i = 0; i < ECSPI_NUM_CS; ++i) {
59
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]);
60
}
61
62
--
63
2.20.1
64
65
diff view generated by jsdifflib
New patch
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
Usually the approach is that the device on the other end of the line
4
is going to reset its state anyway, so there's no need to actively
5
signal an irq line change during the reset hook.
6
7
Move imx_spi_update_irq() out of imx_spi_reset(), to a new function
8
imx_spi_soft_reset() that is called when the controller is disabled.
9
10
Signed-off-by: Bin Meng <bin.meng@windriver.com>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20210129132323.30946-3-bmeng.cn@gmail.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/ssi/imx_spi.c | 14 ++++++++++----
16
1 file changed, 10 insertions(+), 4 deletions(-)
17
18
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/ssi/imx_spi.c
21
+++ b/hw/ssi/imx_spi.c
22
@@ -XXX,XX +XXX,XX @@ static void imx_spi_reset(DeviceState *dev)
23
imx_spi_rxfifo_reset(s);
24
imx_spi_txfifo_reset(s);
25
26
- imx_spi_update_irq(s);
27
-
28
s->burst_length = 0;
29
}
30
31
+static void imx_spi_soft_reset(IMXSPIState *s)
32
+{
33
+ imx_spi_reset(DEVICE(s));
34
+
35
+ imx_spi_update_irq(s);
36
+}
37
+
38
static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
39
{
40
uint32_t value = 0;
41
@@ -XXX,XX +XXX,XX @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
42
s->regs[ECSPI_CONREG] = value;
43
44
if (!imx_spi_is_enabled(s)) {
45
- /* device is disabled, so this is a reset */
46
- imx_spi_reset(DEVICE(s));
47
+ /* device is disabled, so this is a soft reset */
48
+ imx_spi_soft_reset(s);
49
+
50
return;
51
}
52
53
--
54
2.20.1
55
56
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
'burst_length' is cleared in imx_spi_reset(), which is called
4
after imx_spi_realize(). Remove the initialization to simplify.
5
6
Reviewed-by: Juan Quintela <quintela@redhat.com>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Bin Meng <bin.meng@windriver.com>
9
Signed-off-by: Bin Meng <bin.meng@windriver.com>
10
Message-id: 20210129132323.30946-4-bmeng.cn@gmail.com
11
Message-Id: <20210115153049.3353008-3-f4bug@amsat.org>
12
Reviewed-by: Bin Meng <bin.meng@windriver.com>
13
Signed-off-by: Bin Meng <bin.meng@windriver.com>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/ssi/imx_spi.c | 2 --
17
1 file changed, 2 deletions(-)
18
19
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/ssi/imx_spi.c
22
+++ b/hw/ssi/imx_spi.c
23
@@ -XXX,XX +XXX,XX @@ static void imx_spi_realize(DeviceState *dev, Error **errp)
24
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]);
25
}
26
27
- s->burst_length = 0;
28
-
29
fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE);
30
fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE);
31
}
32
--
33
2.20.1
34
35
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
When the block is disabled, all registers are reset with the
4
exception of the ECSPI_CONREG. It is initialized to zero
5
when the instance is created.
6
7
Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM),
8
chapter 21.7.3: Control Register (ECSPIx_CONREG)
9
10
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Signed-off-by: Bin Meng <bin.meng@windriver.com>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20210129132323.30946-5-bmeng.cn@gmail.com
14
[bmeng: add a 'common_reset' function that does most of reset operation]
15
Signed-off-by: Bin Meng <bin.meng@windriver.com>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
hw/ssi/imx_spi.c | 32 ++++++++++++++++++++++++--------
19
1 file changed, 24 insertions(+), 8 deletions(-)
20
21
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/ssi/imx_spi.c
24
+++ b/hw/ssi/imx_spi.c
25
@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
26
fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
27
}
28
29
-static void imx_spi_reset(DeviceState *dev)
30
+static void imx_spi_common_reset(IMXSPIState *s)
31
{
32
- IMXSPIState *s = IMX_SPI(dev);
33
+ int i;
34
35
- DPRINTF("\n");
36
-
37
- memset(s->regs, 0, sizeof(s->regs));
38
-
39
- s->regs[ECSPI_STATREG] = 0x00000003;
40
+ for (i = 0; i < ARRAY_SIZE(s->regs); i++) {
41
+ switch (i) {
42
+ case ECSPI_CONREG:
43
+ /* CONREG is not updated on soft reset */
44
+ break;
45
+ case ECSPI_STATREG:
46
+ s->regs[i] = 0x00000003;
47
+ break;
48
+ default:
49
+ s->regs[i] = 0;
50
+ break;
51
+ }
52
+ }
53
54
imx_spi_rxfifo_reset(s);
55
imx_spi_txfifo_reset(s);
56
@@ -XXX,XX +XXX,XX @@ static void imx_spi_reset(DeviceState *dev)
57
58
static void imx_spi_soft_reset(IMXSPIState *s)
59
{
60
- imx_spi_reset(DEVICE(s));
61
+ imx_spi_common_reset(s);
62
63
imx_spi_update_irq(s);
64
}
65
66
+static void imx_spi_reset(DeviceState *dev)
67
+{
68
+ IMXSPIState *s = IMX_SPI(dev);
69
+
70
+ imx_spi_common_reset(s);
71
+ s->regs[ECSPI_CONREG] = 0;
72
+}
73
+
74
static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
75
{
76
uint32_t value = 0;
77
--
78
2.20.1
79
80
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
In commit e9d652824b0 we extracted the vfp_set_fpscr_to_host()
3
When the block is disabled, it stay it is 'internal reset logic'
4
function but failed at calling it in the correct place, we call
4
(internal clocks are gated off). Reading any register returns
5
it after xregs[ARM_VFP_FPSCR] is modified.
5
its reset value. Only update this value if the device is enabled.
6
6
7
Fix by calling this function before we update FPSCR.
7
Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM),
8
chapter 21.7.3: Control Register (ECSPIx_CONREG)
8
9
9
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
Reviewed-by: Juan Quintela <quintela@redhat.com>
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
12
Reviewed-by: Bin Meng <bin.meng@windriver.com>
12
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
13
Signed-off-by: Bin Meng <bin.meng@windriver.com>
13
Message-id: 20190705124318.1075-1-philmd@redhat.com
14
Message-id: 20210129132323.30946-6-bmeng.cn@gmail.com
15
Message-Id: <20210115153049.3353008-5-f4bug@amsat.org>
16
Reviewed-by: Bin Meng <bin.meng@windriver.com>
17
Signed-off-by: Bin Meng <bin.meng@windriver.com>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
19
---
16
target/arm/vfp_helper.c | 4 ++--
20
hw/ssi/imx_spi.c | 60 +++++++++++++++++++++++-------------------------
17
1 file changed, 2 insertions(+), 2 deletions(-)
21
1 file changed, 29 insertions(+), 31 deletions(-)
18
22
19
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
23
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
20
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/vfp_helper.c
25
--- a/hw/ssi/imx_spi.c
22
+++ b/target/arm/vfp_helper.c
26
+++ b/hw/ssi/imx_spi.c
23
@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
27
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
24
val &= 0xf7c0009f;
28
return 0;
25
}
29
}
26
30
27
+ vfp_set_fpscr_to_host(env, val);
31
- switch (index) {
32
- case ECSPI_RXDATA:
33
- if (!imx_spi_is_enabled(s)) {
34
- value = 0;
35
- } else if (fifo32_is_empty(&s->rx_fifo)) {
36
- /* value is undefined */
37
- value = 0xdeadbeef;
38
- } else {
39
- /* read from the RX FIFO */
40
- value = fifo32_pop(&s->rx_fifo);
41
+ value = s->regs[index];
28
+
42
+
29
/*
43
+ if (imx_spi_is_enabled(s)) {
30
* We don't implement trapped exception handling, so the
44
+ switch (index) {
31
* trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
45
+ case ECSPI_RXDATA:
32
@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
46
+ if (fifo32_is_empty(&s->rx_fifo)) {
33
env->vfp.qc[1] = 0;
47
+ /* value is undefined */
34
env->vfp.qc[2] = 0;
48
+ value = 0xdeadbeef;
35
env->vfp.qc[3] = 0;
49
+ } else {
50
+ /* read from the RX FIFO */
51
+ value = fifo32_pop(&s->rx_fifo);
52
+ }
53
+ break;
54
+ case ECSPI_TXDATA:
55
+ qemu_log_mask(LOG_GUEST_ERROR,
56
+ "[%s]%s: Trying to read from TX FIFO\n",
57
+ TYPE_IMX_SPI, __func__);
58
+
59
+ /* Reading from TXDATA gives 0 */
60
+ break;
61
+ case ECSPI_MSGDATA:
62
+ qemu_log_mask(LOG_GUEST_ERROR,
63
+ "[%s]%s: Trying to read from MSG FIFO\n",
64
+ TYPE_IMX_SPI, __func__);
65
+ /* Reading from MSGDATA gives 0 */
66
+ break;
67
+ default:
68
+ break;
69
}
70
71
- break;
72
- case ECSPI_TXDATA:
73
- qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX FIFO\n",
74
- TYPE_IMX_SPI, __func__);
36
-
75
-
37
- vfp_set_fpscr_to_host(env, val);
76
- /* Reading from TXDATA gives 0 */
77
-
78
- break;
79
- case ECSPI_MSGDATA:
80
- qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG FIFO\n",
81
- TYPE_IMX_SPI, __func__);
82
-
83
- /* Reading from MSGDATA gives 0 */
84
-
85
- break;
86
- default:
87
- value = s->regs[index];
88
- break;
89
+ imx_spi_update_irq(s);
90
}
91
-
92
DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value);
93
94
- imx_spi_update_irq(s);
95
-
96
return (uint64_t)value;
38
}
97
}
39
98
40
void vfp_set_fpscr(CPUARMState *env, uint32_t val)
41
--
99
--
42
2.20.1
100
2.20.1
43
101
44
102
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
When the block is disabled, only the ECSPI_CONREG register can
4
be modified. Setting the EN bit enabled the device, clearing it
5
"disables the block and resets the internal logic with the
6
exception of the ECSPI_CONREG" register.
7
8
Ignore all other registers write except ECSPI_CONREG when the
9
block is disabled.
10
11
Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM),
12
chapter 21.7.3: Control Register (ECSPIx_CONREG)
13
14
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Signed-off-by: Bin Meng <bin.meng@windriver.com>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 20210129132323.30946-7-bmeng.cn@gmail.com
18
Message-Id: <20210115153049.3353008-6-f4bug@amsat.org>
19
Signed-off-by: Bin Meng <bin.meng@windriver.com>
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
hw/ssi/imx_spi.c | 13 +++++++++----
24
1 file changed, 9 insertions(+), 4 deletions(-)
25
26
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/ssi/imx_spi.c
29
+++ b/hw/ssi/imx_spi.c
30
@@ -XXX,XX +XXX,XX @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
31
DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index),
32
(uint32_t)value);
33
34
+ if (!imx_spi_is_enabled(s)) {
35
+ /* Block is disabled */
36
+ if (index != ECSPI_CONREG) {
37
+ /* Ignore access */
38
+ return;
39
+ }
40
+ }
41
+
42
change_mask = s->regs[index] ^ value;
43
44
switch (index) {
45
@@ -XXX,XX +XXX,XX @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
46
TYPE_IMX_SPI, __func__);
47
break;
48
case ECSPI_TXDATA:
49
- if (!imx_spi_is_enabled(s)) {
50
- /* Ignore writes if device is disabled */
51
- break;
52
- } else if (fifo32_is_full(&s->tx_fifo)) {
53
+ if (fifo32_is_full(&s->tx_fifo)) {
54
/* Ignore writes if queue is full */
55
break;
56
}
57
--
58
2.20.1
59
60
diff view generated by jsdifflib
New patch
1
From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
1
2
3
When a write to ECSPI_CONREG register to disable the SPI controller,
4
imx_spi_soft_reset() is called to reset the controller, but chip
5
select lines should have been disabled, otherwise the state machine
6
of any devices (e.g.: SPI flashes) connected to the SPI master is
7
stuck to its last state and responds incorrectly to any follow-up
8
commands.
9
10
Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller")
11
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
12
Signed-off-by: Bin Meng <bin.meng@windriver.com>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20210129132323.30946-8-bmeng.cn@gmail.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/ssi/imx_spi.c | 6 ++++++
18
1 file changed, 6 insertions(+)
19
20
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/ssi/imx_spi.c
23
+++ b/hw/ssi/imx_spi.c
24
@@ -XXX,XX +XXX,XX @@ static void imx_spi_common_reset(IMXSPIState *s)
25
26
static void imx_spi_soft_reset(IMXSPIState *s)
27
{
28
+ int i;
29
+
30
imx_spi_common_reset(s);
31
32
imx_spi_update_irq(s);
33
+
34
+ for (i = 0; i < ECSPI_NUM_CS; i++) {
35
+ qemu_set_irq(s->cs_lines[i], 1);
36
+ }
37
}
38
39
static void imx_spi_reset(DeviceState *dev)
40
--
41
2.20.1
42
43
diff view generated by jsdifflib
1
The test aarch64 kernel is in an array defined with
1
From: Bin Meng <bin.meng@windriver.com>
2
unsigned char aarch64_kernel[] = { [...] }
3
2
4
which means it could be any size; currently it's quite small.
3
Current implementation of the imx spi controller expects the burst
5
However we write it to a file using init_bootfile(), which
4
length to be multiple of 8, which is the most common use case.
6
writes exactly 512 bytes to the file. This will break if
7
we ever end up with a kernel larger than that, and will
8
read garbage off the end of the array in the current setup
9
where the kernel is smaller.
10
5
11
Make init_bootfile() take an argument giving the length of
6
In case the burst length is not what we expect, log it to give user
12
the data to write. This allows us to use it for all architectures
7
a chance to notice it, and round it up to be multiple of 8.
13
(previously s390 had a special-purpose init_bootfile_s390x
14
which hardcoded the file to write so it could write the
15
correct length). We assert that the x86 bootfile really is
16
exactly 512 bytes as it should be (and as we were previously
17
just assuming it was).
18
8
19
This was detected by the clang-7 asan:
9
Signed-off-by: Bin Meng <bin.meng@windriver.com>
20
==15607==ERROR: AddressSanitizer: global-buffer-overflow on address 0x55a796f51d20 at pc 0x55a796b89c2f bp 0x7ffc58e89160 sp 0x7ffc58e88908
10
Message-id: 20210129132323.30946-9-bmeng.cn@gmail.com
21
READ of size 512 at 0x55a796f51d20 thread T0
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
22
#0 0x55a796b89c2e in fwrite (/home/petmay01/linaro/qemu-from-laptop/qemu/build/sanitizers/tests/migration-test+0xb0c2e)
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
#1 0x55a796c46492 in init_bootfile /home/petmay01/linaro/qemu-from-laptop/qemu/tests/migration-test.c:99:5
13
---
24
#2 0x55a796c46492 in test_migrate_start /home/petmay01/linaro/qemu-from-laptop/qemu/tests/migration-test.c:593
14
hw/ssi/imx_spi.c | 17 ++++++++++++++++-
25
#3 0x55a796c44101 in test_baddest /home/petmay01/linaro/qemu-from-laptop/qemu/tests/migration-test.c:854:9
15
1 file changed, 16 insertions(+), 1 deletion(-)
26
#4 0x7f906ffd3cc9 (/usr/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x72cc9)
27
#5 0x7f906ffd3bfa (/usr/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x72bfa)
28
#6 0x7f906ffd3bfa (/usr/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x72bfa)
29
#7 0x7f906ffd3ea1 in g_test_run_suite (/usr/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x72ea1)
30
#8 0x7f906ffd3ec0 in g_test_run (/usr/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x72ec0)
31
#9 0x55a796c43707 in main /home/petmay01/linaro/qemu-from-laptop/qemu/tests/migration-test.c:1187:11
32
#10 0x7f906e9abb96 in __libc_start_main /build/glibc-OTsEL5/glibc-2.27/csu/../csu/libc-start.c:310
33
#11 0x55a796b6c2d9 in _start (/home/petmay01/linaro/qemu-from-laptop/qemu/build/sanitizers/tests/migration-test+0x932d9)
34
16
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
36
Reviewed-by: Laurent Vivier <lvivier@redhat.com>
37
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
38
Message-id: 20190702150311.20467-1-peter.maydell@linaro.org
39
---
40
tests/migration-test.c | 22 +++++++---------------
41
1 file changed, 7 insertions(+), 15 deletions(-)
42
43
diff --git a/tests/migration-test.c b/tests/migration-test.c
44
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
45
--- a/tests/migration-test.c
19
--- a/hw/ssi/imx_spi.c
46
+++ b/tests/migration-test.c
20
+++ b/hw/ssi/imx_spi.c
47
@@ -XXX,XX +XXX,XX @@ static const char *tmpfs;
21
@@ -XXX,XX +XXX,XX @@ static uint8_t imx_spi_selected_channel(IMXSPIState *s)
48
*/
22
49
#include "tests/migration/i386/a-b-bootblock.h"
23
static uint32_t imx_spi_burst_length(IMXSPIState *s)
50
#include "tests/migration/aarch64/a-b-kernel.h"
51
-
52
-static void init_bootfile(const char *bootpath, void *content)
53
-{
54
- FILE *bootfile = fopen(bootpath, "wb");
55
-
56
- g_assert_cmpint(fwrite(content, 512, 1, bootfile), ==, 1);
57
- fclose(bootfile);
58
-}
59
-
60
#include "tests/migration/s390x/a-b-bios.h"
61
62
-static void init_bootfile_s390x(const char *bootpath)
63
+static void init_bootfile(const char *bootpath, void *content, size_t len)
64
{
24
{
65
FILE *bootfile = fopen(bootpath, "wb");
25
- return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
66
- size_t len = sizeof(s390x_elf);
26
+ uint32_t burst;
67
27
+
68
- g_assert_cmpint(fwrite(s390x_elf, len, 1, bootfile), ==, 1);
28
+ burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
69
+ g_assert_cmpint(fwrite(content, len, 1, bootfile), ==, 1);
29
+ if (burst % 8) {
70
fclose(bootfile);
30
+ burst = ROUND_UP(burst, 8);
31
+ }
32
+
33
+ return burst;
71
}
34
}
72
35
73
@@ -XXX,XX +XXX,XX @@ static int test_migrate_start(QTestState **from, QTestState **to,
36
static bool imx_spi_is_enabled(IMXSPIState *s)
74
got_stop = false;
37
@@ -XXX,XX +XXX,XX @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
75
bootpath = g_strdup_printf("%s/bootsect", tmpfs);
38
IMXSPIState *s = opaque;
76
if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
39
uint32_t index = offset >> 2;
77
- init_bootfile(bootpath, x86_bootsect);
40
uint32_t change_mask;
78
+ /* the assembled x86 boot sector should be exactly one sector large */
41
+ uint32_t burst;
79
+ assert(sizeof(x86_bootsect) == 512);
42
80
+ init_bootfile(bootpath, x86_bootsect, sizeof(x86_bootsect));
43
if (index >= ECSPI_MAX) {
81
extra_opts = use_shmem ? get_shmem_opts("150M", shmem_path) : NULL;
44
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
82
cmd_src = g_strdup_printf("-machine accel=%s -m 150M"
45
@@ -XXX,XX +XXX,XX @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
83
" -name source,debug-threads=on"
46
case ECSPI_CONREG:
84
@@ -XXX,XX +XXX,XX @@ static int test_migrate_start(QTestState **from, QTestState **to,
47
s->regs[ECSPI_CONREG] = value;
85
start_address = X86_TEST_MEM_START;
48
86
end_address = X86_TEST_MEM_END;
49
+ burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
87
} else if (g_str_equal(arch, "s390x")) {
50
+ if (burst % 8) {
88
- init_bootfile_s390x(bootpath);
51
+ qemu_log_mask(LOG_UNIMP,
89
+ init_bootfile(bootpath, s390x_elf, sizeof(s390x_elf));
52
+ "[%s]%s: burst length %d not supported: rounding up to next multiple of 8\n",
90
extra_opts = use_shmem ? get_shmem_opts("128M", shmem_path) : NULL;
53
+ TYPE_IMX_SPI, __func__, burst);
91
cmd_src = g_strdup_printf("-machine accel=%s -m 128M"
54
+ }
92
" -name source,debug-threads=on"
55
+
93
@@ -XXX,XX +XXX,XX @@ static int test_migrate_start(QTestState **from, QTestState **to,
56
if (!imx_spi_is_enabled(s)) {
94
start_address = PPC_TEST_MEM_START;
57
/* device is disabled, so this is a soft reset */
95
end_address = PPC_TEST_MEM_END;
58
imx_spi_soft_reset(s);
96
} else if (strcmp(arch, "aarch64") == 0) {
97
- init_bootfile(bootpath, aarch64_kernel);
98
+ init_bootfile(bootpath, aarch64_kernel, sizeof(aarch64_kernel));
99
extra_opts = use_shmem ? get_shmem_opts("150M", shmem_path) : NULL;
100
cmd_src = g_strdup_printf("-machine virt,accel=%s,gic-version=max "
101
"-name vmsource,debug-threads=on -cpu max "
102
--
59
--
103
2.20.1
60
2.20.1
104
61
105
62
diff view generated by jsdifflib
New patch
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
For the ECSPIx_CONREG register BURST_LENGTH field, the manual says:
4
5
0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second word.
6
0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second word.
7
8
Current logic uses either s->burst_length or 32, whichever smaller,
9
to determine how many bits it should read from the tx fifo each time.
10
For example, for a 48 bit burst length, current logic transfers the
11
first 32 bit from the first word in the tx fifo, followed by a 16
12
bit from the second word in the tx fifo, which is wrong. The correct
13
logic should be: transfer the first 16 bit from the first word in
14
the tx fifo, followed by a 32 bit from the second word in the tx fifo.
15
16
With this change, SPI flash can be successfully probed by U-Boot on
17
imx6 sabrelite board.
18
19
=> sf probe
20
SF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, total 2 MiB
21
22
Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller")
23
Signed-off-by: Bin Meng <bin.meng@windriver.com>
24
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
25
Message-id: 20210129132323.30946-10-bmeng.cn@gmail.com
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
---
28
hw/ssi/imx_spi.c | 2 +-
29
1 file changed, 1 insertion(+), 1 deletion(-)
30
31
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/ssi/imx_spi.c
34
+++ b/hw/ssi/imx_spi.c
35
@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
36
37
DPRINTF("data tx:0x%08x\n", tx);
38
39
- tx_burst = MIN(s->burst_length, 32);
40
+ tx_burst = (s->burst_length % 32) ? : 32;
41
42
rx = 0;
43
44
--
45
2.20.1
46
47
diff view generated by jsdifflib
New patch
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
The endianness of data exchange between tx and rx fifo is incorrect.
4
Earlier bytes are supposed to show up on MSB and later bytes on LSB,
5
ie: in big endian. The manual does not explicitly say this, but the
6
U-Boot and Linux driver codes have a swap on the data transferred
7
to tx fifo and from rx fifo.
8
9
With this change, U-Boot read from / write to SPI flash tests pass.
10
11
=> sf test 1ff000 1000
12
SPI flash test:
13
0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps
14
1 check: 3 ticks, 1333 KiB/s 10.664 Mbps
15
2 write: 235 ticks, 17 KiB/s 0.136 Mbps
16
3 read: 2 ticks, 2000 KiB/s 16.000 Mbps
17
Test passed
18
0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps
19
1 check: 3 ticks, 1333 KiB/s 10.664 Mbps
20
2 write: 235 ticks, 17 KiB/s 0.136 Mbps
21
3 read: 2 ticks, 2000 KiB/s 16.000 Mbps
22
23
Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller")
24
Signed-off-by: Bin Meng <bin.meng@windriver.com>
25
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
26
Message-id: 20210129132323.30946-11-bmeng.cn@gmail.com
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
---
29
hw/ssi/imx_spi.c | 7 ++-----
30
1 file changed, 2 insertions(+), 5 deletions(-)
31
32
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/ssi/imx_spi.c
35
+++ b/hw/ssi/imx_spi.c
36
@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
37
38
while (!fifo32_is_empty(&s->tx_fifo)) {
39
int tx_burst = 0;
40
- int index = 0;
41
42
if (s->burst_length <= 0) {
43
s->burst_length = imx_spi_burst_length(s);
44
@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
45
rx = 0;
46
47
while (tx_burst > 0) {
48
- uint8_t byte = tx & 0xff;
49
+ uint8_t byte = tx >> (tx_burst - 8);
50
51
DPRINTF("writing 0x%02x\n", (uint32_t)byte);
52
53
@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
54
55
DPRINTF("0x%02x read\n", (uint32_t)byte);
56
57
- tx = tx >> 8;
58
- rx |= (byte << (index * 8));
59
+ rx = (rx << 8) | byte;
60
61
/* Remove 8 bits from the actual burst */
62
tx_burst -= 8;
63
s->burst_length -= 8;
64
- index++;
65
}
66
67
DPRINTF("data rx:0x%08x\n", rx);
68
--
69
2.20.1
70
71
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Per the ARM Generic Interrupt Controller Architecture specification
4
(document "ARM IHI 0048B.b (ID072613)"), the SGIINTID field is 4 bit,
5
not 10:
6
7
- 4.3 Distributor register descriptions
8
- 4.3.15 Software Generated Interrupt Register, GICD_SG
9
10
- Table 4-21 GICD_SGIR bit assignments
11
12
The Interrupt ID of the SGI to forward to the specified CPU
13
interfaces. The value of this field is the Interrupt ID, in
14
the range 0-15, for example a value of 0b0011 specifies
15
Interrupt ID 3.
16
17
Correct the irq mask to fix an undefined behavior (which eventually
18
lead to a heap-buffer-overflow, see [Buglink]):
19
20
$ echo 'writel 0x8000f00 0xff4affb0' | qemu-system-aarch64 -M virt,accel=qtest -qtest stdio
21
[I 1612088147.116987] OPENED
22
[R +0.278293] writel 0x8000f00 0xff4affb0
23
../hw/intc/arm_gic.c:1498:13: runtime error: index 944 out of bounds for type 'uint8_t [16][8]'
24
SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior ../hw/intc/arm_gic.c:1498:13
25
26
This fixes a security issue when running with KVM on Arm with
27
kernel-irqchip=off. (The default is kernel-irqchip=on, which is
28
unaffected, and which is also the correct choice for performance.)
29
30
Cc: qemu-stable@nongnu.org
31
Fixes: 9ee6e8bb853 ("ARMv7 support.")
32
Buglink: https://bugs.launchpad.net/qemu/+bug/1913916
33
Buglink: https://bugs.launchpad.net/qemu/+bug/1913917
34
Reported-by: Alexander Bulekov <alxndr@bu.edu>
35
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
36
Message-id: 20210131103401.217160-1-f4bug@amsat.org
37
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
38
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
39
---
40
hw/intc/arm_gic.c | 2 +-
41
1 file changed, 1 insertion(+), 1 deletion(-)
42
43
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/intc/arm_gic.c
46
+++ b/hw/intc/arm_gic.c
47
@@ -XXX,XX +XXX,XX @@ static void gic_dist_writel(void *opaque, hwaddr offset,
48
int target_cpu;
49
50
cpu = gic_get_current_cpu(s);
51
- irq = value & 0x3ff;
52
+ irq = value & 0xf;
53
switch ((value >> 24) & 3) {
54
case 0:
55
mask = (value >> 16) & ALL_CPU_MASK;
56
--
57
2.20.1
58
59
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
The STM32F405 SoC uses an OR gate on its ADC IRQs.
4
5
Fixes: 529fc5fd3e1 ("hw/arm: Add the STM32F4xx SoC")
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20210131184449.382425-2-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/Kconfig | 1 +
12
1 file changed, 1 insertion(+)
13
14
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/Kconfig
17
+++ b/hw/arm/Kconfig
18
@@ -XXX,XX +XXX,XX @@ config STM32F205_SOC
19
config STM32F405_SOC
20
bool
21
select ARM_V7M
22
+ select OR_IRQ
23
select STM32F4XX_SYSCFG
24
select STM32F4XX_EXTI
25
26
--
27
2.20.1
28
29
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
The Exynos4210 SoC uses an OR gate on the PL330 IRQ lines.
4
5
Fixes: dab15fbe2ab ("hw/arm/exynos4210: Fix DMA initialization")
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20210131184449.382425-3-f4bug@amsat.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/Kconfig | 1 +
12
1 file changed, 1 insertion(+)
13
14
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/Kconfig
17
+++ b/hw/arm/Kconfig
18
@@ -XXX,XX +XXX,XX @@ config EXYNOS4
19
select PTIMER
20
select SDHCI
21
select USB_EHCI_SYSBUS
22
+ select OR_IRQ
23
24
config HIGHBANK
25
bool
26
--
27
2.20.1
28
29
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
The Versal SoC instantiates the TYPE_XLNX_ZDMA object in
4
versal_create_admas(). Introduce the XLNX_ZDMA configuration
5
and select it to fix:
6
7
$ qemu-system-aarch64 -M xlnx-versal-virt ...
8
qemu-system-aarch64: missing object type 'xlnx.zdma'
9
10
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-id: 20210131184449.382425-4-f4bug@amsat.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/arm/Kconfig | 2 ++
16
hw/dma/Kconfig | 3 +++
17
hw/dma/meson.build | 2 +-
18
3 files changed, 6 insertions(+), 1 deletion(-)
19
20
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/Kconfig
23
+++ b/hw/arm/Kconfig
24
@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP_ARM
25
select XILINX_AXI
26
select XILINX_SPIPS
27
select XLNX_ZYNQMP
28
+ select XLNX_ZDMA
29
30
config XLNX_VERSAL
31
bool
32
@@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL
33
select CADENCE
34
select VIRTIO_MMIO
35
select UNIMP
36
+ select XLNX_ZDMA
37
38
config NPCM7XX
39
bool
40
diff --git a/hw/dma/Kconfig b/hw/dma/Kconfig
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/dma/Kconfig
43
+++ b/hw/dma/Kconfig
44
@@ -XXX,XX +XXX,XX @@ config ZYNQ_DEVCFG
45
bool
46
select REGISTER
47
48
+config XLNX_ZDMA
49
+ bool
50
+
51
config STP2000
52
bool
53
54
diff --git a/hw/dma/meson.build b/hw/dma/meson.build
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/dma/meson.build
57
+++ b/hw/dma/meson.build
58
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ZYNQ_DEVCFG', if_true: files('xlnx-zynq-devcfg.c'))
59
softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_dma.c'))
60
softmmu_ss.add(when: 'CONFIG_STP2000', if_true: files('sparc32_dma.c'))
61
softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx_dpdma.c'))
62
-softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zdma.c'))
63
+softmmu_ss.add(when: 'CONFIG_XLNX_ZDMA', if_true: files('xlnx-zdma.c'))
64
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_dma.c', 'soc_dma.c'))
65
softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_dma.c'))
66
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_dma.c'))
67
--
68
2.20.1
69
70
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
The Versal SoC instantiates the TYPE_XLNX_ZYNQMP_RTC object in
4
versal_create_rtc()(). Select CONFIG_XLNX_ZYNQMP to fix:
5
6
$ make check-qtest-aarch64
7
...
8
Running test qtest-aarch64/qom-test
9
qemu-system-aarch64: missing object type 'xlnx-zynmp.rtc'
10
Broken pipe
11
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Message-id: 20210131184449.382425-5-f4bug@amsat.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/arm/Kconfig | 1 +
18
1 file changed, 1 insertion(+)
19
20
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/Kconfig
23
+++ b/hw/arm/Kconfig
24
@@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL
25
select VIRTIO_MMIO
26
select UNIMP
27
select XLNX_ZDMA
28
+ select XLNX_ZYNQMP
29
30
config NPCM7XX
31
bool
32
--
33
2.20.1
34
35
diff view generated by jsdifflib
1
In the virt machine, we support TrustZone being either present or
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
absent, and so the code must deal with the secure_sysmem pointer
3
possibly being NULL. In the sbsa-ref machine, TrustZone is always
4
present, but some code and comments copied from virt still treat
5
it as possibly not being present.
6
2
7
This causes Coverity to complain (CID 1407287) that we check
3
Add a dependency XLNX_ZYNQMP -> PTIMER to fix:
8
secure_sysmem for being NULL after an unconditional dereference.
9
Simplify the code so that instead of initializing the variable
10
to NULL, unconditionally assigning it, and then testing it for NULL,
11
we just initialize it correctly in the variable declaration and
12
then assume it to be non-NULL. We also delete a comment which
13
only applied to the non-TrustZone config.
14
4
5
/usr/bin/ld:
6
libcommon.fa.p/hw_net_can_xlnx-zynqmp-can.c.o: in function `xlnx_zynqmp_can_realize':
7
hw/net/can/xlnx-zynqmp-can.c:1082: undefined reference to `ptimer_init'
8
hw/net/can/xlnx-zynqmp-can.c:1085: undefined reference to `ptimer_transaction_begin'
9
hw/net/can/xlnx-zynqmp-can.c:1087: undefined reference to `ptimer_set_freq'
10
hw/net/can/xlnx-zynqmp-can.c:1088: undefined reference to `ptimer_set_limit'
11
hw/net/can/xlnx-zynqmp-can.c:1089: undefined reference to `ptimer_run'
12
hw/net/can/xlnx-zynqmp-can.c:1090: undefined reference to `ptimer_transaction_commit'
13
libcommon.fa.p/hw_net_can_xlnx-zynqmp-can.c.o:(.data.rel+0x2c8): undefined reference to `vmstate_ptimer'
14
15
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Message-id: 20210131184449.382425-6-f4bug@amsat.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
17
Message-id: 20190704142004.7150-1-peter.maydell@linaro.org
18
Tested-by: Radosław Biernacki <radoslaw.biernacki@linaro.org>
19
Reviewed-by: Radosław Biernacki <radoslaw.biernacki@linaro.org>
20
---
19
---
21
hw/arm/sbsa-ref.c | 8 ++------
20
hw/Kconfig | 1 +
22
1 file changed, 2 insertions(+), 6 deletions(-)
21
1 file changed, 1 insertion(+)
23
22
24
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
23
diff --git a/hw/Kconfig b/hw/Kconfig
25
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/sbsa-ref.c
25
--- a/hw/Kconfig
27
+++ b/hw/arm/sbsa-ref.c
26
+++ b/hw/Kconfig
28
@@ -XXX,XX +XXX,XX @@ static void sbsa_flash_map(SBSAMachineState *sms,
27
@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP
29
* sysmem is the system memory space. secure_sysmem is the secure view
28
bool
30
* of the system, and the first flash device should be made visible only
29
select REGISTER
31
* there. The second flash device is visible to both secure and nonsecure.
30
select CAN_BUS
32
- * If sysmem == secure_sysmem this means there is no separate Secure
31
+ select PTIMER
33
- * address space and both flash devices are generally visible.
34
*/
35
hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2;
36
hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base;
37
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
38
SBSAMachineState *sms = SBSA_MACHINE(machine);
39
MachineClass *mc = MACHINE_GET_CLASS(machine);
40
MemoryRegion *sysmem = get_system_memory();
41
- MemoryRegion *secure_sysmem = NULL;
42
+ MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1);
43
MemoryRegion *ram = g_new(MemoryRegion, 1);
44
bool firmware_loaded;
45
const CPUArchIdList *possible_cpus;
46
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
47
* containing the system memory at low priority; any secure-only
48
* devices go in at higher priority and take precedence.
49
*/
50
- secure_sysmem = g_new(MemoryRegion, 1);
51
memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
52
UINT64_MAX);
53
memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
54
55
- firmware_loaded = sbsa_firmware_init(sms, sysmem,
56
- secure_sysmem ?: sysmem);
57
+ firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem);
58
59
if (machine->kernel_filename && firmware_loaded) {
60
error_report("sbsa-ref: No fw_cfg device on this machine, "
61
--
32
--
62
2.20.1
33
2.20.1
63
34
64
35
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Off by one error in the EL2 and EL3 tests. Remove the test
3
Most of ARM machines display their CPU when QEMU list the available
4
against EL3 entirely, since it must always be true.
4
machines (-M help). Some machines do not. Fix to unify the help
5
output.
5
6
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20210131184449.382425-7-f4bug@amsat.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20190702104732.31154-1-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
13
---
11
target/arm/helper.c | 4 ++--
14
hw/arm/digic_boards.c | 2 +-
12
1 file changed, 2 insertions(+), 2 deletions(-)
15
hw/arm/microbit.c | 2 +-
16
hw/arm/netduino2.c | 2 +-
17
hw/arm/netduinoplus2.c | 2 +-
18
hw/arm/orangepi.c | 2 +-
19
hw/arm/stellaris.c | 4 ++--
20
6 files changed, 7 insertions(+), 7 deletions(-)
13
21
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
22
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
15
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
24
--- a/hw/arm/digic_boards.c
17
+++ b/target/arm/helper.c
25
+++ b/hw/arm/digic_boards.c
18
@@ -XXX,XX +XXX,XX @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
26
@@ -XXX,XX +XXX,XX @@ static void canon_a1100_init(MachineState *machine)
19
if (el <= 1) {
27
20
zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
28
static void canon_a1100_machine_init(MachineClass *mc)
21
}
29
{
22
- if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
30
- mc->desc = "Canon PowerShot A1100 IS";
23
+ if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) {
31
+ mc->desc = "Canon PowerShot A1100 IS (ARM946)";
24
zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]);
32
mc->init = &canon_a1100_init;
25
}
33
mc->ignore_memory_transaction_failures = true;
26
- if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
34
mc->default_ram_size = 64 * MiB;
27
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
35
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
28
zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
36
index XXXXXXX..XXXXXXX 100644
29
}
37
--- a/hw/arm/microbit.c
30
return zcr_len;
38
+++ b/hw/arm/microbit.c
39
@@ -XXX,XX +XXX,XX @@ static void microbit_machine_class_init(ObjectClass *oc, void *data)
40
{
41
MachineClass *mc = MACHINE_CLASS(oc);
42
43
- mc->desc = "BBC micro:bit";
44
+ mc->desc = "BBC micro:bit (Cortex-M0)";
45
mc->init = microbit_init;
46
mc->max_cpus = 1;
47
}
48
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/arm/netduino2.c
51
+++ b/hw/arm/netduino2.c
52
@@ -XXX,XX +XXX,XX @@ static void netduino2_init(MachineState *machine)
53
54
static void netduino2_machine_init(MachineClass *mc)
55
{
56
- mc->desc = "Netduino 2 Machine";
57
+ mc->desc = "Netduino 2 Machine (Cortex-M3)";
58
mc->init = netduino2_init;
59
mc->ignore_memory_transaction_failures = true;
60
}
61
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/hw/arm/netduinoplus2.c
64
+++ b/hw/arm/netduinoplus2.c
65
@@ -XXX,XX +XXX,XX @@ static void netduinoplus2_init(MachineState *machine)
66
67
static void netduinoplus2_machine_init(MachineClass *mc)
68
{
69
- mc->desc = "Netduino Plus 2 Machine";
70
+ mc->desc = "Netduino Plus 2 Machine (Cortex-M4)";
71
mc->init = netduinoplus2_init;
72
}
73
74
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/hw/arm/orangepi.c
77
+++ b/hw/arm/orangepi.c
78
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
79
80
static void orangepi_machine_init(MachineClass *mc)
81
{
82
- mc->desc = "Orange Pi PC";
83
+ mc->desc = "Orange Pi PC (Cortex-A7)";
84
mc->init = orangepi_init;
85
mc->block_default_type = IF_SD;
86
mc->units_per_default_bus = 1;
87
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
88
index XXXXXXX..XXXXXXX 100644
89
--- a/hw/arm/stellaris.c
90
+++ b/hw/arm/stellaris.c
91
@@ -XXX,XX +XXX,XX @@ static void lm3s811evb_class_init(ObjectClass *oc, void *data)
92
{
93
MachineClass *mc = MACHINE_CLASS(oc);
94
95
- mc->desc = "Stellaris LM3S811EVB";
96
+ mc->desc = "Stellaris LM3S811EVB (Cortex-M3)";
97
mc->init = lm3s811evb_init;
98
mc->ignore_memory_transaction_failures = true;
99
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
100
@@ -XXX,XX +XXX,XX @@ static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
101
{
102
MachineClass *mc = MACHINE_CLASS(oc);
103
104
- mc->desc = "Stellaris LM3S6965EVB";
105
+ mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)";
106
mc->init = lm3s6965evb_init;
107
mc->ignore_memory_transaction_failures = true;
108
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
31
--
109
--
32
2.20.1
110
2.20.1
33
111
34
112
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