The following changes since commit 8f6330a807f2642dc2a3cdf33347aa28a4c00a87:

Merge tag 'pull-maintainer-updates-060324-1' of https://gitlab.com/stsquad/qemu into staging (2024-03-06 16:56:20 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240308

for you to fetch changes up to bbf6c6dbead82292a20951eb1204442a6b838de9:

target/arm: Move v7m-related code from cpu32.c into a separate file (2024-03-08 14:45:03 +0000)

* Implement FEAT_ECV

* STM32L4x5: Implement GPIO device

* Fix 32-bit SMOPA

* Refactor v7m related code from cpu32.c into its own file

* hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later

Inès Varhol (3):

hw/gpio: Implement STM32L4x5 GPIO

hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC

tests/qtest: Add STM32L4x5 GPIO QTest testcase

Peter Maydell (9):

target/arm: Move some register related defines to internals.h

target/arm: Timer _EL02 registers UNDEF for E2H == 0

target/arm: use FIELD macro for CNTHCTL bit definitions

target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written

target/arm: Implement new FEAT_ECV trap bits

target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0

target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling

target/arm: Enable FEAT_ECV for 'max' CPU

hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later

Richard Henderson (1):

target/arm: Fix 32-bit SMOPA

We prefer the FIELD macro over ad-hoc #defines for register bits;

switch CNTHCTL to that style before we add any more bits.

Message-id: 20240301183219.2424889-4-peter.maydell@linaro.org

target/arm/internals.h | 27 +++++++++++++++++++++++++--

target/arm/helper.c | 9 ++++-----

2 files changed, 29 insertions(+), 7 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h

--- a/target/arm/internals.h

+++ b/target/arm/internals.h

@@ -XXX,XX +XXX,XX @@ FIELD(VTCR, SL2, 33, 1)

#define HSTR_TTEE (1 << 16)

#define HSTR_TJDBX (1 << 17)

-#define CNTHCTL_CNTVMASK (1 << 18)

-#define CNTHCTL_CNTPMASK (1 << 19)

+/*

+ * Depending on the value of HCR_EL2.E2H, bits 0 and 1

+ * have different bit definitions, and EL1PCTEN might be

+ * bit 0 or bit 10. We use _E2H1 and _E2H0 suffixes to

+ * disambiguate if necessary.

+ */

+FIELD(CNTHCTL, EL0PCTEN_E2H1, 0, 1)

+FIELD(CNTHCTL, EL0VCTEN_E2H1, 1, 1)

+FIELD(CNTHCTL, EL1PCTEN_E2H0, 0, 1)

+FIELD(CNTHCTL, EL1PCEN_E2H0, 1, 1)

+FIELD(CNTHCTL, EVNTEN, 2, 1)

+FIELD(CNTHCTL, EVNTDIR, 3, 1)

+FIELD(CNTHCTL, EVNTI, 4, 4)

+FIELD(CNTHCTL, EL0VTEN, 8, 1)

+FIELD(CNTHCTL, EL0PTEN, 9, 1)

+FIELD(CNTHCTL, EL1PCTEN_E2H1, 10, 1)

+FIELD(CNTHCTL, EL1PTEN, 11, 1)

+FIELD(CNTHCTL, ECV, 12, 1)

+FIELD(CNTHCTL, EL1TVT, 13, 1)

+FIELD(CNTHCTL, EL1TVCT, 14, 1)

+FIELD(CNTHCTL, EL1NVPCT, 15, 1)

+FIELD(CNTHCTL, EL1NVVCT, 16, 1)

+FIELD(CNTHCTL, EVNTIS, 17, 1)

+FIELD(CNTHCTL, CNTVMASK, 18, 1)

+FIELD(CNTHCTL, CNTPMASK, 19, 1)

/* We use a few fake FSR values for internal purposes in M profile.

* M profile cores don't have A/R format FSRs, but currently our

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ static void gt_update_irq(ARMCPU *cpu, int timeridx)

* It is RES0 in Secure and NonSecure state.

*/

if ((ss == ARMSS_Root || ss == ARMSS_Realm) &&

- ((timeridx == GTIMER_VIRT && (cnthctl & CNTHCTL_CNTVMASK)) ||

- (timeridx == GTIMER_PHYS && (cnthctl & CNTHCTL_CNTPMASK)))) {

+ ((timeridx == GTIMER_VIRT && (cnthctl & R_CNTHCTL_CNTVMASK_MASK)) ||

+ (timeridx == GTIMER_PHYS && (cnthctl & R_CNTHCTL_CNTPMASK_MASK)))) {

irqstate = 0;

@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,

{

ARMCPU *cpu = env_archcpu(env);

uint32_t oldval = env->cp15.cnthctl_el2;

-

raw_write(env, ri, value);

- if ((oldval ^ value) & CNTHCTL_CNTVMASK) {

+ if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) {

gt_update_irq(cpu, GTIMER_VIRT);

- } else if ((oldval ^ value) & CNTHCTL_CNTPMASK) {

+ } else if ((oldval ^ value) & R_CNTHCTL_CNTPMASK_MASK) {

gt_update_irq(cpu, GTIMER_PHYS);

}

}

2.34.1

The functionality defined by ID_AA64MMFR0_EL1.ECV == 1 is:

* four new trap bits for various counter and timer registers

* the CNTHCTL_EL2.EVNTIS and CNTKCTL_EL1.EVNTIS bits which control

scaling of the event stream. This is a no-op for us, because we don't

implement the event stream (our WFE is a NOP): all we need to do is

allow CNTHCTL_EL2.ENVTIS to be read and written.

* extensions to PMSCR_EL1.PCT, PMSCR_EL2.PCT, TRFCR_EL1.TS and

TRFCR_EL2.TS: these are all no-ops for us, because we don't implement

FEAT_SPE or FEAT_TRF.

* new registers CNTPCTSS_EL0 and NCTVCTSS_EL0 which are

"self-sychronizing" views of the CNTPCT_EL0 and CNTVCT_EL0, meaning

that no barriers are needed around their accesses. For us these

are just the same as the normal views, because all our sysregs are

inherently self-sychronizing.

In this commit we implement the trap handling and permit the new

CNTHCTL_EL2 bits to be written.

Message-id: 20240301183219.2424889-6-peter.maydell@linaro.org

target/arm/cpu-features.h | 5 ++++

target/arm/helper.c | 51 +++++++++++++++++++++++++++++++++++----

2 files changed, 51 insertions(+), 5 deletions(-)

diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h

--- a/target/arm/cpu-features.h

+++ b/target/arm/cpu-features.h

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)

return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;

}

+static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id)

+{

+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0;

+}

+

static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)

return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,

: !extract32(env->cp15.cnthctl_el2, 0, 1))) {

return CP_ACCESS_TRAP_EL2;

}

+ if (has_el2 && timeridx == GTIMER_VIRT) {

+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVCT)) {

+ return CP_ACCESS_TRAP_EL2;

+ }

break;

}

return CP_ACCESS_OK;

@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,

}

}

}

+ if (has_el2 && timeridx == GTIMER_VIRT) {

+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVT)) {

+ return CP_ACCESS_TRAP_EL2;

+ }

+ }

break;

}

return CP_ACCESS_OK;

@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,

if (cpu_isar_feature(aa64_rme, cpu)) {

valid_mask |= R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK;

}

+ if (cpu_isar_feature(aa64_ecv_traps, cpu)) {

+ valid_mask |=

+ R_CNTHCTL_EL1TVT_MASK |

+ R_CNTHCTL_EL1TVCT_MASK |

+ R_CNTHCTL_EL1NVPCT_MASK |

+ R_CNTHCTL_EL1NVVCT_MASK |

+ R_CNTHCTL_EVNTIS_MASK;

+ }

/* Clear RES0 bits */

value &= valid_mask;

@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,

{

if (arm_current_el(env) == 1) {

/* This must be a FEAT_NV access */

- /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */

return CP_ACCESS_OK;

}

if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {

@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,

return CP_ACCESS_OK;

}

+static CPAccessResult access_el1nvpct(CPUARMState *env, const ARMCPRegInfo *ri,

+ bool isread)

+{

+ if (arm_current_el(env) == 1) {

+ /* This must be a FEAT_NV access with NVx == 101 */

+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVPCT)) {

+ return CP_ACCESS_TRAP_EL2;

+static CPAccessResult access_el1nvvct(CPUARMState *env, const ARMCPRegInfo *ri,

+ bool isread)

+{

+ if (arm_current_el(env) == 1) {

+ /* This must be a FEAT_NV access with NVx == 101 */

+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVVCT)) {

+ return CP_ACCESS_TRAP_EL2;

+ }

+ return e2h_access(env, ri, isread);

+}

+

/* Test if system register redirection is to occur in the current state. */

static bool redirect_for_e2h(CPUARMState *env)

{

@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {

{ .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64,

.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1,

.type = ARM_CP_IO | ARM_CP_ALIAS,

- .access = PL2_RW, .accessfn = e2h_access,

+ .access = PL2_RW, .accessfn = access_el1nvpct,

.nv2_redirect_offset = 0x180 | NV2_REDIR_NO_NV1,

.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),

.writefn = gt_phys_ctl_write, .raw_writefn = raw_write },

{ .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64,

.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1,

.type = ARM_CP_IO | ARM_CP_ALIAS,

- .access = PL2_RW, .accessfn = e2h_access,

+ .access = PL2_RW, .accessfn = access_el1nvvct,

.nv2_redirect_offset = 0x170 | NV2_REDIR_NO_NV1,

.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),

.writefn = gt_virt_ctl_write, .raw_writefn = raw_write },

@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {

.type = ARM_CP_IO | ARM_CP_ALIAS,

.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),

.nv2_redirect_offset = 0x178 | NV2_REDIR_NO_NV1,

- .access = PL2_RW, .accessfn = e2h_access,

+ .access = PL2_RW, .accessfn = access_el1nvpct,

.writefn = gt_phys_cval_write, .raw_writefn = raw_write },

{ .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64,

.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2,

.type = ARM_CP_IO | ARM_CP_ALIAS,

.nv2_redirect_offset = 0x168 | NV2_REDIR_NO_NV1,

.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),

- .access = PL2_RW, .accessfn = e2h_access,

+ .access = PL2_RW, .accessfn = access_el1nvvct,

.writefn = gt_virt_cval_write, .raw_writefn = raw_write },

#endif

};

2.34.1

When ID_AA64MMFR0_EL1.ECV is 0b0010, a new register CNTPOFF_EL2 is

implemented. This is similar to the existing CNTVOFF_EL2, except

that it controls a hypervisor-adjustable offset made to the physical

counter and timer.

Implement the handling for this register, which includes control/trap

bits in SCR_EL3 and CNTHCTL_EL2.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20240301183219.2424889-8-peter.maydell@linaro.org

---

target/arm/cpu-features.h | 5 +++

target/arm/cpu.h | 1 +

target/arm/helper.c | 68 +++++++++++++++++++++++++++++++++++++--

target/arm/trace-events | 1 +

4 files changed, 73 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h

--- a/target/arm/cpu-features.h

+++ b/target/arm/cpu-features.h

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id)

return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0;

}

+static inline bool isar_feature_aa64_ecv(const ARMISARegisters *id)

+{

+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 1;

+}

+

static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)

{

return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;

@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {

uint64_t c14_cntkctl; /* Timer Control register */

uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */

uint64_t cntvoff_el2; /* Counter Virtual Offset register */

+ uint64_t cntpoff_el2; /* Counter Physical Offset register */

ARMGenericTimer c14_timer[NUM_GTIMERS];

uint32_t c15_cpar; /* XScale Coprocessor Access Register */

uint32_t c15_ticonfig; /* TI925T configuration byte. */

@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)

if (cpu_isar_feature(aa64_rme, cpu)) {

valid_mask |= SCR_NSE | SCR_GPF;

}

+ if (cpu_isar_feature(aa64_ecv, cpu)) {

+ valid_mask |= SCR_ECVEN;

+ }

} else {

valid_mask &= ~(SCR_RW | SCR_ST);

if (cpu_isar_feature(aa32_ras, cpu)) {

@@ -XXX,XX +XXX,XX @@ void gt_rme_post_el_change(ARMCPU *cpu, void *ignored)

gt_update_irq(cpu, GTIMER_PHYS);

}

+static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env)

+{

+ if ((env->cp15.scr_el3 & SCR_ECVEN) &&

+ FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) &&

+ arm_is_el2_enabled(env) &&

+ (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {

+ return env->cp15.cntpoff_el2;

+ }

+ return 0;

+}

+

+static uint64_t gt_phys_cnt_offset(CPUARMState *env)

+{

+ if (arm_current_el(env) >= 2) {

+ return 0;

+ }

+ return gt_phys_raw_cnt_offset(env);

+}

+

static void gt_recalc_timer(ARMCPU *cpu, int timeridx)

{

ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];

@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)

* reset timer to when ISTATUS next has to change

*/

uint64_t offset = timeridx == GTIMER_VIRT ?

- cpu->env.cp15.cntvoff_el2 : 0;

+ cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env);

uint64_t count = gt_get_countervalue(&cpu->env);

/* Note that this must be unsigned 64 bit arithmetic: */

int istatus = count - offset >= gt->cval;

@@ -XXX,XX +XXX,XX @@ static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,

static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)

{

- return gt_get_countervalue(env);

+ return gt_get_countervalue(env) - gt_phys_cnt_offset(env);

}

static uint64_t gt_virt_cnt_offset(CPUARMState *env)

@@ -XXX,XX +XXX,XX @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,

case GTIMER_HYPVIRT:

offset = gt_virt_cnt_offset(env);

break;

+ case GTIMER_PHYS:

+ offset = gt_phys_cnt_offset(env);

+ break;

}

return (uint32_t)(env->cp15.c14_timer[timeridx].cval -

@@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,

case GTIMER_HYPVIRT:

offset = gt_virt_cnt_offset(env);

break;

+ case GTIMER_PHYS:

+ offset = gt_phys_cnt_offset(env);

+ break;

}

trace_arm_gt_tval_write(timeridx, value);

@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,

R_CNTHCTL_EL1NVVCT_MASK |

R_CNTHCTL_EVNTIS_MASK;

}

+ if (cpu_isar_feature(aa64_ecv, cpu)) {

+ valid_mask |= R_CNTHCTL_ECV_MASK;

+ }

/* Clear RES0 bits */

value &= valid_mask;

@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = {

},

};

+static CPAccessResult gt_cntpoff_access(CPUARMState *env,

+ const ARMCPRegInfo *ri,

+ bool isread)

+{

+ if (arm_current_el(env) == 2 && !(env->cp15.scr_el3 & SCR_ECVEN)) {

+ return CP_ACCESS_TRAP_EL3;

+ }

+ return CP_ACCESS_OK;

+}

+

+static void gt_cntpoff_write(CPUARMState *env, const ARMCPRegInfo *ri,

+ uint64_t value)

+{

+ ARMCPU *cpu = env_archcpu(env);

+

+ trace_arm_gt_cntpoff_write(value);

+ raw_write(env, ri, value);

+ gt_recalc_timer(cpu, GTIMER_PHYS);

+}

+

+static const ARMCPRegInfo gen_timer_cntpoff_reginfo = {

+ .name = "CNTPOFF_EL2", .state = ARM_CP_STATE_AA64,

+ .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 6,

+ .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,

+ .accessfn = gt_cntpoff_access, .writefn = gt_cntpoff_write,

+ .nv2_redirect_offset = 0x1a8,

+ .fieldoffset = offsetof(CPUARMState, cp15.cntpoff_el2),

+};

#else

/*

@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)

if (cpu_isar_feature(aa64_ecv_traps, cpu)) {

define_arm_cp_regs(cpu, gen_timer_ecv_cp_reginfo);

}

+#ifndef CONFIG_USER_ONLY

+ if (cpu_isar_feature(aa64_ecv, cpu)) {

+ define_one_arm_cp_reg(cpu, &gen_timer_cntpoff_reginfo);

+ }

if (arm_feature(env, ARM_FEATURE_VAPA)) {

ARMCPRegInfo vapa_cp_reginfo[] = {

{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,

diff --git a/target/arm/trace-events b/target/arm/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/trace-events

+++ b/target/arm/trace-events

@@ -XXX,XX +XXX,XX @@ arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write: timer %d value 0x%"

arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value 0x%" PRIx64

arm_gt_imask_toggle(int timer) "gt_ctl_write: timer %d IMASK toggle"

arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value 0x%" PRIx64

+arm_gt_cntpoff_write(uint64_t value) "gt_cntpoff_write: value 0x%" PRIx64

arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d"

# kvm.c

2.34.1

Enable all FEAT_ECV features on the 'max' CPU.

Message-id: 20240301183219.2424889-9-peter.maydell@linaro.org

docs/system/arm/emulation.rst | 1 +

target/arm/tcg/cpu64.c | 1 +

2 files changed, 2 insertions(+)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst

--- a/docs/system/arm/emulation.rst

+++ b/docs/system/arm/emulation.rst

@@ -XXX,XX +XXX,XX @@ the following architecture extensions:

- FEAT_DotProd (Advanced SIMD dot product instructions)

- FEAT_DoubleFault (Double Fault Extension)

- FEAT_E0PD (Preventing EL0 access to halves of address maps)

+- FEAT_ECV (Enhanced Counter Virtualization)

- FEAT_EPAC (Enhanced pointer authentication)

- FEAT_ETS (Enhanced Translation Synchronization)

- FEAT_EVT (Enhanced Virtualization Traps)

diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/tcg/cpu64.c

+++ b/target/arm/tcg/cpu64.c

@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)

t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */

t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */

t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */

+ t = FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */

cpu->isar.id_aa64mmfr0 = t;

t = cpu->isar.id_aa64mmfr1;

2.34.1

From: Inès Varhol <ines.varhol@telecom-paris.fr>

Features supported :

- the 8 STM32L4x5 GPIOs are initialized with their reset values

(except IDR, see below)

- input mode : setting a pin in input mode "externally" (using input

irqs) results in an out irq (transmitted to SYSCFG)

- output mode : setting a bit in ODR sets the corresponding out irq

(if this line is configured in output mode)

- pull-up, pull-down

- push-pull, open-drain

Difference with the real GPIOs :

- Alternate Function and Analog mode aren't implemented :

pins in AF/Analog behave like pins in input mode

- floating pins stay at their last value

- register IDR reset values differ from the real one :

values are coherent with the other registers reset values

and the fact that AF/Analog modes aren't implemented

- setting I/O output speed isn't supported

- locking port bits isn't supported

- ADC function isn't supported

- GPIOH has 16 pins instead of 2 pins

- writing to registers LCKR, AFRL, AFRH and ASCR is ineffective

Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>

Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Message-id: 20240305210444.310665-2-ines.varhol@telecom-paris.fr

MAINTAINERS | 1 +

docs/system/arm/b-l475e-iot01a.rst | 2 +-

include/hw/gpio/stm32l4x5_gpio.h | 70 +++++

hw/gpio/stm32l4x5_gpio.c | 477 +++++++++++++++++++++++++++++

hw/gpio/Kconfig | 3 +

hw/gpio/meson.build | 1 +

hw/gpio/trace-events | 6 +

7 files changed, 559 insertions(+), 1 deletion(-)

create mode 100644 include/hw/gpio/stm32l4x5_gpio.h

create mode 100644 hw/gpio/stm32l4x5_gpio.c

diff --git a/MAINTAINERS b/MAINTAINERS

--- a/MAINTAINERS

+++ b/MAINTAINERS

@@ -XXX,XX +XXX,XX @@ F: hw/arm/stm32l4x5_soc.c

F: hw/misc/stm32l4x5_exti.c

F: hw/misc/stm32l4x5_syscfg.c

F: hw/misc/stm32l4x5_rcc.c

+F: hw/gpio/stm32l4x5_gpio.c

F: include/hw/*/stm32l4x5_*.h

B-L475E-IOT01A IoT Node

diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst

--- a/docs/system/arm/b-l475e-iot01a.rst

+++ b/docs/system/arm/b-l475e-iot01a.rst

@@ -XXX,XX +XXX,XX @@ Currently B-L475E-IOT01A machine's only supports the following devices:

- STM32L4x5 EXTI (Extended interrupts and events controller)

- STM32L4x5 SYSCFG (System configuration controller)

- STM32L4x5 RCC (Reset and clock control)

+- STM32L4x5 GPIOs (General-purpose I/Os)

Missing devices

"""""""""""""""

@@ -XXX,XX +XXX,XX @@ Missing devices

The B-L475E-IOT01A does *not* support the following devices:

- Serial ports (UART)

-- General-purpose I/Os (GPIO)

- Analog to Digital Converter (ADC)

- SPI controller

- Timer controller (TIMER)

diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_gpio.h