[Qemu-devel] [PULL 0/3] tcg patch queue
[PATCH v3 00/28] tcg patch queue
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The following changes since commit c4e42a9c2b714de5cddabffe46c7789fcff49c30:
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v3: One more try to fix macos issues.
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190701' into staging (2019-07-02 12:58:32 +0100)
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r~
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The following changes since commit e0209297cddd5e10a07e15fac5cca7aa1a8e0e59:
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Merge tag 'pull-ufs-20250217' of https://gitlab.com/jeuk20.kim/qemu into staging (2025-02-18 10:58:48 +0800)
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are available in the Git repository at:
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are available in the Git repository at:
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https://github.com/rth7680/qemu.git tags/pull-tcg-20190702
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215-3
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for you to fetch changes up to 0c3c385c62759e1427f88c5fc5b0d9741a456807:
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for you to fetch changes up to e726f65867087d86436de05e9f372a86ec1381a6:
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tcg: Fix expansion of INDEX_op_not_vec (2019-07-02 15:59:42 +0200)
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tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 (2025-02-18 08:29:03 -0800)
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----------------------------------------------------------------
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----------------------------------------------------------------
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Queued tcg bug fixes
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tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
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tcg: Cleanups after disallowing 64-on-32
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tcg: Introduce constraint for zero register
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tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
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tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
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linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
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linux-user: Fix alignment when unmapping excess reservation
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target/sparc: Fix register selection for all F*TOx and FxTO* instructions
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target/sparc: Fix gdbstub incorrectly handling registers f32-f62
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target/sparc: fake UltraSPARC T1 PCR and PIC registers
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----------------------------------------------------------------
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----------------------------------------------------------------
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Alistair Francis (1):
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Andreas Schwab (1):
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tcg/riscv: Fix RISC-VH host build failure
34
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
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35
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Richard Henderson (2):
36
Artyom Tarasenko (1):
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tcg: Fix mmap lock assert on translation failure
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target/sparc: fake UltraSPARC T1 PCR and PIC registers
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tcg: Fix expansion of INDEX_op_not_vec
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include/exec/cpu-all.h | 1 +
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Fabiano Rosas (1):
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include/exec/cpu_ldst_useronly_template.h | 8 ++++++--
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elfload: Fix alignment when unmapping excess reservation
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accel/tcg/translate-all.c | 29 +++++++++++++++++++++++++++++
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tcg/riscv/tcg-target.inc.c | 4 ++--
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tcg/tcg-op-vec.c | 6 ++++++
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5 files changed, 44 insertions(+), 4 deletions(-)
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Mikael Szreder (2):
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target/sparc: Fix register selection for all F*TOx and FxTO* instructions
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target/sparc: Fix gdbstub incorrectly handling registers f32-f62
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Richard Henderson (23):
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tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
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tcg: Remove TCG_OVERSIZED_GUEST
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tcg: Drop support for two address registers in gen_ldst
50
tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
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tcg/arm: Drop addrhi from prepare_host_addr
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tcg/i386: Drop addrhi from prepare_host_addr
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tcg/mips: Drop addrhi from prepare_host_addr
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tcg/ppc: Drop addrhi from prepare_host_addr
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tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
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plugins: Fix qemu_plugin_read_memory_vaddr parameters
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accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
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target/loongarch: Use VADDR_PRIx for logging pc_next
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target/mips: Use VADDR_PRIx for logging pc_next
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include/exec: Change vaddr to uintptr_t
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include/exec: Use uintptr_t in CPUTLBEntry
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tcg: Introduce the 'z' constraint for a hardware zero register
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tcg/aarch64: Use 'z' constraint
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tcg/loongarch64: Use 'z' constraint
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tcg/mips: Use 'z' constraint
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tcg/riscv: Use 'z' constraint
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tcg/sparc64: Use 'z' constraint
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tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
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tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
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include/exec/tlb-common.h | 10 +-
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include/exec/vaddr.h | 16 +-
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include/qemu/atomic.h | 18 +-
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include/tcg/oversized-guest.h | 23 ---
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include/tcg/tcg-opc.h | 28 +--
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include/tcg/tcg.h | 3 +-
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linux-user/aarch64/target_signal.h | 2 +
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linux-user/arm/target_signal.h | 2 +
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linux-user/generic/signal.h | 1 -
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linux-user/i386/target_signal.h | 2 +
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linux-user/m68k/target_signal.h | 1 +
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linux-user/microblaze/target_signal.h | 2 +
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linux-user/ppc/target_signal.h | 2 +
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linux-user/s390x/target_signal.h | 2 +
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linux-user/sh4/target_signal.h | 2 +
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linux-user/x86_64/target_signal.h | 2 +
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linux-user/xtensa/target_signal.h | 2 +
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tcg/aarch64/tcg-target-con-set.h | 12 +-
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tcg/aarch64/tcg-target.h | 2 +
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tcg/loongarch64/tcg-target-con-set.h | 15 +-
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tcg/loongarch64/tcg-target-con-str.h | 1 -
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tcg/loongarch64/tcg-target-has.h | 2 -
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tcg/loongarch64/tcg-target.h | 2 +
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tcg/mips/tcg-target-con-set.h | 26 +--
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tcg/mips/tcg-target-con-str.h | 1 -
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tcg/mips/tcg-target.h | 2 +
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tcg/riscv/tcg-target-con-set.h | 10 +-
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tcg/riscv/tcg-target-con-str.h | 1 -
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tcg/riscv/tcg-target-has.h | 2 -
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tcg/riscv/tcg-target.h | 2 +
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tcg/sparc64/tcg-target-con-set.h | 12 +-
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tcg/sparc64/tcg-target-con-str.h | 1 -
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tcg/sparc64/tcg-target.h | 3 +-
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tcg/tci/tcg-target.h | 1 -
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accel/tcg/cputlb.c | 32 +---
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accel/tcg/tcg-all.c | 9 +-
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linux-user/elfload.c | 4 +-
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plugins/api.c | 2 +-
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target/arm/ptw.c | 34 ----
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target/loongarch/tcg/translate.c | 2 +-
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target/mips/tcg/octeon_translate.c | 4 +-
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target/riscv/cpu_helper.c | 13 +-
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target/sparc/gdbstub.c | 18 +-
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target/sparc/translate.c | 19 +++
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tcg/optimize.c | 21 +--
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tcg/tcg-op-ldst.c | 103 +++--------
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tcg/tcg.c | 97 +++++------
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tcg/tci.c | 119 +++----------
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docs/devel/multi-thread-tcg.rst | 1 -
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docs/devel/tcg-ops.rst | 4 +-
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target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
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target/sparc/insns.decode | 19 ++-
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tcg/aarch64/tcg-target.c.inc | 86 ++++------
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tcg/arm/tcg-target.c.inc | 114 ++++---------
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tcg/i386/tcg-target.c.inc | 190 +++++----------------
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tcg/loongarch64/tcg-target.c.inc | 72 +++-----
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tcg/mips/tcg-target.c.inc | 169 ++++++------------
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tcg/ppc/tcg-target.c.inc | 164 +++++-------------
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tcg/riscv/tcg-target.c.inc | 56 +++---
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tcg/s390x/tcg-target.c.inc | 40 ++---
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tcg/sparc64/tcg-target.c.inc | 45 ++---
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tcg/tci/tcg-target.c.inc | 60 ++-----
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62 files changed, 550 insertions(+), 1162 deletions(-)
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delete mode 100644 include/tcg/oversized-guest.h
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/3] tcg: Fix mmap lock assert on translation failure
Deleted patch
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Check page flags before letting an invalid pc cause a SIGSEGV.
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1
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Prepare for eventially validating PROT_EXEC. The current wrinkle being
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that we have a problem with our implementation of signals. We should
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be using a vdso like the kernel, but we instead put the trampoline on
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the stack. In the meantime, let PROT_READ match PROT_EXEC.
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Fixes: https://bugs.launchpad.net/qemu/+bug/1832353
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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---
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include/exec/cpu-all.h | 1 +
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include/exec/cpu_ldst_useronly_template.h | 8 +++++--
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accel/tcg/translate-all.c | 29 +++++++++++++++++++++++
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3 files changed, 36 insertions(+), 2 deletions(-)
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diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
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index XXXXXXX..XXXXXXX 100644
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--- a/include/exec/cpu-all.h
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+++ b/include/exec/cpu-all.h
20
@@ -XXX,XX +XXX,XX @@ int walk_memory_regions(void *, walk_memory_regions_fn);
21
int page_get_flags(target_ulong address);
22
void page_set_flags(target_ulong start, target_ulong end, int flags);
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int page_check_range(target_ulong start, target_ulong len, int flags);
24
+void validate_exec_access(CPUArchState *env, target_ulong s, target_ulong l);
25
#endif
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CPUArchState *cpu_copy(CPUArchState *env);
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diff --git a/include/exec/cpu_ldst_useronly_template.h b/include/exec/cpu_ldst_useronly_template.h
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index XXXXXXX..XXXXXXX 100644
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--- a/include/exec/cpu_ldst_useronly_template.h
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+++ b/include/exec/cpu_ldst_useronly_template.h
32
@@ -XXX,XX +XXX,XX @@
33
static inline RES_TYPE
34
glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr)
35
{
36
-#if !defined(CODE_ACCESS)
37
+#ifdef CODE_ACCESS
38
+ validate_exec_access(env, ptr, DATA_SIZE);
39
+#else
40
trace_guest_mem_before_exec(
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env_cpu(env), ptr,
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trace_mem_build_info(SHIFT, false, MO_TE, false));
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@@ -XXX,XX +XXX,XX @@ glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
44
static inline int
45
glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr)
46
{
47
-#if !defined(CODE_ACCESS)
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+#ifdef CODE_ACCESS
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+ validate_exec_access(env, ptr, DATA_SIZE);
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+#else
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trace_guest_mem_before_exec(
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env_cpu(env), ptr,
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trace_mem_build_info(SHIFT, true, MO_TE, false));
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diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
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index XXXXXXX..XXXXXXX 100644
56
--- a/accel/tcg/translate-all.c
57
+++ b/accel/tcg/translate-all.c
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@@ -XXX,XX +XXX,XX @@ int page_check_range(target_ulong start, target_ulong len, int flags)
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}
60
}
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}
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+ /*
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+ * FIXME: We place the signal trampoline on the stack,
64
+ * even when the guest expects that to be in the vdso.
65
+ * Until we fix that, allow execute on any readable page.
66
+ */
67
+ if ((flags & PAGE_EXEC) && !(p->flags & (PAGE_EXEC | PAGE_READ))) {
68
+ return -1;
69
+ }
70
}
71
return 0;
72
}
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74
+/*
75
+ * Called for each code read, longjmp out to issue SIGSEGV if the page(s)
76
+ * do not have execute access.
77
+ */
78
+void validate_exec_access(CPUArchState *env,
79
+ target_ulong ptr, target_ulong len)
80
+{
81
+ if (page_check_range(ptr, len, PAGE_EXEC) < 0) {
82
+ CPUState *cs = env_cpu(env);
83
+ CPUClass *cc = CPU_GET_CLASS(cs);
84
+
85
+ /* Like tb_gen_code, release the memory lock before cpu_loop_exit. */
86
+ assert_memory_lock();
87
+ mmap_unlock();
88
+
89
+ /* This is user-only. The target must raise an exception. */
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+ cc->tlb_fill(cs, ptr, 0, MMU_INST_FETCH, MMU_USER_IDX, false, 0);
91
+ g_assert_not_reached();
92
+ }
93
+}
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+
95
/* called from signal handler: invalidate the code and unprotect the
96
* page. Return 0 if the fault was not handled, 1 if it was handled,
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* and 2 if it was handled but the caller must cause the TB to be
98
--
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2.17.1
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101
diff view generated by jsdifflib
[Qemu-devel] [PULL 2/3] tcg/riscv: Fix RISC-VH host build failure
[PATCH v3 13/28] target/mips: Use VADDR_PRIx for logging pc_next
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From: Alistair Francis <alistair.francis@wdc.com>
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DisasContextBase.pc_next has type vaddr; use the correct log format.
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2
3
Commit 269bd5d8 "cpu: Move the softmmu tlb to CPUNegativeOffsetState'
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Fixes: 85c19af63e7 ("include/exec: Use vaddr in DisasContextBase for virtual addresses")
4
broke the RISC-V host build as there are two variables that are used but
5
not defined.
6
7
This patch renames the undefined variables mask_off and table_off to the
8
existing (but unused) mask_ofs and table_ofs variables.
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10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Message-Id: <79729cc88ca509e08b5c4aa0aa8a52847af70c0f.1561039316.git.alistair.francis@wdc.com>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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---
5
---
14
tcg/riscv/tcg-target.inc.c | 4 ++--
6
target/mips/tcg/octeon_translate.c | 4 ++--
15
1 file changed, 2 insertions(+), 2 deletions(-)
7
1 file changed, 2 insertions(+), 2 deletions(-)
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8
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diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
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diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
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index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
19
--- a/tcg/riscv/tcg-target.inc.c
11
--- a/target/mips/tcg/octeon_translate.c
20
+++ b/tcg/riscv/tcg-target.inc.c
12
+++ b/target/mips/tcg/octeon_translate.c
21
@@ -XXX,XX +XXX,XX @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
13
@@ -XXX,XX +XXX,XX @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
22
int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
14
TCGv p;
23
TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
15
24
16
if (ctx->hflags & MIPS_HFLAG_BMASK) {
25
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_off);
17
- LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
26
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_off);
18
- TARGET_FMT_lx "\n", ctx->base.pc_next);
27
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs);
19
+ LOG_DISAS("Branch in delay / forbidden slot at PC 0x%" VADDR_PRIx "\n",
28
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs);
20
+ ctx->base.pc_next);
29
21
generate_exception_end(ctx, EXCP_RI);
30
tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addrl,
22
return true;
31
TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
23
}
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--
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--
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2.17.1
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2.43.0
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diff view generated by jsdifflib
[Qemu-devel] [PULL 3/3] tcg: Fix expansion of INDEX_op_not_vec
Deleted patch
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This operation can always be emitted, even if we need to
2
fall back to xor. Adjust the assertions to match.
3
1
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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---
6
tcg/tcg-op-vec.c | 6 ++++++
7
1 file changed, 6 insertions(+)
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9
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tcg-op-vec.c
12
+++ b/tcg/tcg-op-vec.c
13
@@ -XXX,XX +XXX,XX @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list,
14
case INDEX_op_bitsel_vec:
15
/* These opcodes are mandatory and should not be listed. */
16
g_assert_not_reached();
17
+ case INDEX_op_not_vec:
18
+ /* These opcodes have generic expansions using the above. */
19
+ g_assert_not_reached();
20
default:
21
break;
22
}
23
@@ -XXX,XX +XXX,XX @@ static bool do_op2(unsigned vece, TCGv_vec r, TCGv_vec a, TCGOpcode opc)
24
25
void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
26
{
27
+ const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
28
+
29
if (!TCG_TARGET_HAS_not_vec || !do_op2(vece, r, a, INDEX_op_not_vec)) {
30
TCGv_vec t = tcg_const_ones_vec_matching(r);
31
tcg_gen_xor_vec(0, r, a, t);
32
tcg_temp_free_vec(t);
33
}
34
+ tcg_swap_vecop_list(hold_list);
35
}
36
37
void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
38
--
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2.17.1
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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