[Qemu-devel] [PULL 00/46] target-arm queue
[PULL 00/72] target-arm queue
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target-arm queue for softfreeze: this is quite big as I
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First arm pullreq of the cycle; this is mostly my softfloat NaN
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was on holiday last week, so this is all just sneaking in
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handling series. (Lots more in my to-review queue, but I don't
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under the wire. I particularly wanted to get Philippe's
3
like pullreqs growing too close to a hundred patches at a time :-))
4
patches in before freeze as that sort of code-movement
5
patchset is painful to have to rebase.
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4
7
thanks
5
thanks
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-- PMM
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-- PMM
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The following changes since commit ae9108f8f0746ce64d02afb1a216153a50926132:
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The following changes since commit 97f2796a3736ed37a1b85dc1c76a6c45b829dd17:
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Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-4.1-pull-request' into staging (2019-07-01 15:55:40 +0100)
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Open 10.0 development tree (2024-12-10 17:41:17 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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13
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190701
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241211
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15
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for you to fetch changes up to 787a7e76c2e93a48c47b324fea592c9910a70483:
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for you to fetch changes up to 1abe28d519239eea5cf9620bb13149423e5665f8:
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target/arm: Declare some M-profile functions publicly (2019-07-01 17:29:01 +0100)
18
MAINTAINERS: Add correct email address for Vikram Garhwal (2024-12-11 15:31:09 +0000)
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19
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----------------------------------------------------------------
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----------------------------------------------------------------
23
target-arm queue:
21
target-arm queue:
24
* hw/arm/boot: fix direct kernel boot with initrd
22
* hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs
25
* hw/arm/msf2-som: Exit when the cpu is not the expected one
23
* fpu: Make muladd NaN handling runtime-selected, not compile-time
26
* i.mx7: fix bugs in PCI controller needed to boot recent kernels
24
* fpu: Make default NaN pattern runtime-selected, not compile-time
27
* aspeed: add RTC device
25
* fpu: Minor NaN-related cleanups
28
* aspeed: fix some timer device bugs
26
* MAINTAINERS: email address updates
29
* aspeed: add swift-bmc board
30
* aspeed: vic: Add support for legacy register interface
31
* aspeed: add aspeed-xdma device
32
* Add new sbsa-ref board for aarch64
33
* target/arm: code refactoring in preparation for support of
34
compilation with TCG disabled
35
27
36
----------------------------------------------------------------
28
----------------------------------------------------------------
37
Adriana Kobylak (1):
29
Bernhard Beschow (5):
38
aspeed: Add support for the swift-bmc board
30
hw/net/lan9118: Extract lan9118_phy
31
hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
32
hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
33
hw/net/lan9118_phy: Reuse MII constants
34
hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
39
35
40
Andrew Jeffery (3):
36
Leif Lindholm (1):
41
aspeed/timer: Status register contains reload for stopped timer
37
MAINTAINERS: update email address for Leif Lindholm
42
aspeed/timer: Fix match calculations
43
aspeed: vic: Add support for legacy register interface
44
38
45
Andrew Jones (1):
39
Peter Maydell (54):
46
hw/arm/boot: fix direct kernel boot with initrd
40
fpu: handle raising Invalid for infzero in pick_nan_muladd
41
fpu: Check for default_nan_mode before calling pickNaNMulAdd
42
softfloat: Allow runtime choice of inf * 0 + NaN result
43
tests/fp: Explicitly set inf-zero-nan rule
44
target/arm: Set FloatInfZeroNaNRule explicitly
45
target/s390: Set FloatInfZeroNaNRule explicitly
46
target/ppc: Set FloatInfZeroNaNRule explicitly
47
target/mips: Set FloatInfZeroNaNRule explicitly
48
target/sparc: Set FloatInfZeroNaNRule explicitly
49
target/xtensa: Set FloatInfZeroNaNRule explicitly
50
target/x86: Set FloatInfZeroNaNRule explicitly
51
target/loongarch: Set FloatInfZeroNaNRule explicitly
52
target/hppa: Set FloatInfZeroNaNRule explicitly
53
softfloat: Pass have_snan to pickNaNMulAdd
54
softfloat: Allow runtime choice of NaN propagation for muladd
55
tests/fp: Explicitly set 3-NaN propagation rule
56
target/arm: Set Float3NaNPropRule explicitly
57
target/loongarch: Set Float3NaNPropRule explicitly
58
target/ppc: Set Float3NaNPropRule explicitly
59
target/s390x: Set Float3NaNPropRule explicitly
60
target/sparc: Set Float3NaNPropRule explicitly
61
target/mips: Set Float3NaNPropRule explicitly
62
target/xtensa: Set Float3NaNPropRule explicitly
63
target/i386: Set Float3NaNPropRule explicitly
64
target/hppa: Set Float3NaNPropRule explicitly
65
fpu: Remove use_first_nan field from float_status
66
target/m68k: Don't pass NULL float_status to floatx80_default_nan()
67
softfloat: Create floatx80 default NaN from parts64_default_nan
68
target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
69
target/m68k: In frem helper, initialize local float_status from env->fp_status
70
target/m68k: Init local float_status from env fp_status in gdb get/set reg
71
target/sparc: Initialize local scratch float_status from env->fp_status
72
target/ppc: Use env->fp_status in helper_compute_fprf functions
73
fpu: Allow runtime choice of default NaN value
74
tests/fp: Set default NaN pattern explicitly
75
target/microblaze: Set default NaN pattern explicitly
76
target/i386: Set default NaN pattern explicitly
77
target/hppa: Set default NaN pattern explicitly
78
target/alpha: Set default NaN pattern explicitly
79
target/arm: Set default NaN pattern explicitly
80
target/loongarch: Set default NaN pattern explicitly
81
target/m68k: Set default NaN pattern explicitly
82
target/mips: Set default NaN pattern explicitly
83
target/openrisc: Set default NaN pattern explicitly
84
target/ppc: Set default NaN pattern explicitly
85
target/sh4: Set default NaN pattern explicitly
86
target/rx: Set default NaN pattern explicitly
87
target/s390x: Set default NaN pattern explicitly
88
target/sparc: Set default NaN pattern explicitly
89
target/xtensa: Set default NaN pattern explicitly
90
target/hexagon: Set default NaN pattern explicitly
91
target/riscv: Set default NaN pattern explicitly
92
target/tricore: Set default NaN pattern explicitly
93
fpu: Remove default handling for dnan_pattern
47
94
48
Andrey Smirnov (5):
95
Richard Henderson (11):
49
i.mx7d: Add no-op/unimplemented APBH DMA module
96
target/arm: Copy entire float_status in is_ebf
50
i.mx7d: Add no-op/unimplemented PCIE PHY IP block
97
softfloat: Inline pickNaNMulAdd
51
pci: designware: Update MSI mapping unconditionally
98
softfloat: Use goto for default nan case in pick_nan_muladd
52
pci: designware: Update MSI mapping when MSI address changes
99
softfloat: Remove which from parts_pick_nan_muladd
53
i.mx7d: pci: Update PCI IRQ mapping to match HW
100
softfloat: Pad array size in pick_nan_muladd
101
softfloat: Move propagateFloatx80NaN to softfloat.c
102
softfloat: Use parts_pick_nan in propagateFloatx80NaN
103
softfloat: Inline pickNaN
104
softfloat: Share code between parts_pick_nan cases
105
softfloat: Sink frac_cmp in parts_pick_nan until needed
106
softfloat: Replace WHICH with RET in parts_pick_nan
54
107
55
Christian Svensson (1):
108
Vikram Garhwal (1):
56
aspeed/timer: Ensure positive muldiv delta
109
MAINTAINERS: Add correct email address for Vikram Garhwal
57
110
58
Cédric Le Goater (7):
111
MAINTAINERS | 4 +-
59
aspeed: add a per SoC mapping for the interrupt space
112
include/fpu/softfloat-helpers.h | 38 +++-
60
aspeed: add a per SoC mapping for the memory space
113
include/fpu/softfloat-types.h | 89 +++++++-
61
aspeed: introduce a configurable number of CPU per machine
114
include/hw/net/imx_fec.h | 9 +-
62
aspeed: add support for multiple NICs
115
include/hw/net/lan9118_phy.h | 37 ++++
63
aspeed: remove the "ram" link
116
include/hw/net/mii.h | 6 +
64
aspeed: add a RAM memory region container
117
target/mips/fpu_helper.h | 20 ++
65
aspeed/smc: add a 'sdram_base' property
118
target/sparc/helper.h | 4 +-
66
119
fpu/softfloat.c | 19 ++
67
Eddie James (1):
120
hw/net/imx_fec.c | 146 ++------------
68
hw/misc/aspeed_xdma: New device
121
hw/net/lan9118.c | 137 ++-----------
69
122
hw/net/lan9118_phy.c | 222 ++++++++++++++++++++
70
Hongbo Zhang (2):
123
linux-user/arm/nwfpe/fpa11.c | 5 +
71
hw/arm: Add arm SBSA reference machine, skeleton part
124
target/alpha/cpu.c | 2 +
72
hw/arm: Add arm SBSA reference machine, devices part
125
target/arm/cpu.c | 10 +
73
126
target/arm/tcg/vec_helper.c | 20 +-
74
Jan Kiszka (1):
127
target/hexagon/cpu.c | 2 +
75
hw/arm/virt: Add support for Cortex-A7
128
target/hppa/fpu_helper.c | 12 ++
76
129
target/i386/tcg/fpu_helper.c | 12 ++
77
Joel Stanley (4):
130
target/loongarch/tcg/fpu_helper.c | 14 +-
78
hw: timer: Add ASPEED RTC device
131
target/m68k/cpu.c | 14 +-
79
hw/arm/aspeed: Add RTC to SoC
132
target/m68k/fpu_helper.c | 6 +-
80
aspeed/timer: Fix behaviour running Linux
133
target/m68k/helper.c | 6 +-
81
aspeed: Link SCU to the watchdog
134
target/microblaze/cpu.c | 2 +
82
135
target/mips/msa.c | 10 +
83
Philippe Mathieu-Daudé (19):
136
target/openrisc/cpu.c | 2 +
84
hw/arm/msf2-som: Exit when the cpu is not the expected one
137
target/ppc/cpu_init.c | 19 ++
85
target/arm: Makefile cleanup (Aarch64)
138
target/ppc/fpu_helper.c | 3 +-
86
target/arm: Makefile cleanup (ARM)
139
target/riscv/cpu.c | 2 +
87
target/arm: Makefile cleanup (KVM)
140
target/rx/cpu.c | 2 +
88
target/arm: Makefile cleanup (softmmu)
141
target/s390x/cpu.c | 5 +
89
target/arm: Add copyright boilerplate
142
target/sh4/cpu.c | 2 +
90
target/arm/helper: Remove unused include
143
target/sparc/cpu.c | 6 +
91
target/arm: Fix multiline comment syntax
144
target/sparc/fop_helper.c | 8 +-
92
target/arm: Fix coding style issues
145
target/sparc/translate.c | 4 +-
93
target/arm: Move CPU state dumping routines to cpu.c
146
target/tricore/helper.c | 2 +
94
target/arm: Declare get_phys_addr() function publicly
147
target/xtensa/cpu.c | 4 +
95
target/arm: Move TLB related routines to tlb_helper.c
148
target/xtensa/fpu_helper.c | 3 +-
96
target/arm/vfp_helper: Move code around
149
tests/fp/fp-bench.c | 7 +
97
target/arm/vfp_helper: Extract vfp_set_fpscr_to_host()
150
tests/fp/fp-test-log2.c | 1 +
98
target/arm/vfp_helper: Extract vfp_set_fpscr_from_host()
151
tests/fp/fp-test.c | 7 +
99
target/arm/vfp_helper: Restrict the SoftFloat use to TCG
152
fpu/softfloat-parts.c.inc | 152 +++++++++++---
100
target/arm: Restrict PSCI to TCG
153
fpu/softfloat-specialize.c.inc | 412 ++------------------------------------
101
target/arm: Declare arm_log_exception() function publicly
154
.mailmap | 5 +-
102
target/arm: Declare some M-profile functions publicly
155
hw/net/Kconfig | 5 +
103
156
hw/net/meson.build | 1 +
104
Samuel Ortiz (1):
157
hw/net/trace-events | 10 +-
105
target/arm: Move the DC ZVA helper into op_helper
158
47 files changed, 778 insertions(+), 730 deletions(-)
106
159
create mode 100644 include/hw/net/lan9118_phy.h
107
hw/arm/Makefile.objs | 1 +
160
create mode 100644 hw/net/lan9118_phy.c
108
hw/misc/Makefile.objs | 1 +
109
hw/timer/Makefile.objs | 2 +-
110
target/arm/Makefile.objs | 24 +-
111
include/hw/arm/aspeed_soc.h | 53 ++-
112
include/hw/arm/fsl-imx7.h | 14 +-
113
include/hw/misc/aspeed_xdma.h | 30 ++
114
include/hw/ssi/aspeed_smc.h | 3 +
115
include/hw/timer/aspeed_rtc.h | 31 ++
116
include/hw/watchdog/wdt_aspeed.h | 1 +
117
target/arm/cpu.h | 2 -
118
target/arm/internals.h | 69 ++-
119
target/arm/translate.h | 5 -
120
hw/arm/aspeed.c | 76 +++-
121
hw/arm/aspeed_soc.c | 262 +++++++++---
122
hw/arm/boot.c | 3 +-
123
hw/arm/fsl-imx7.c | 11 +
124
hw/arm/msf2-som.c | 1 +
125
hw/arm/sbsa-ref.c | 806 ++++++++++++++++++++++++++++++++++++
126
hw/arm/virt.c | 1 +
127
hw/intc/aspeed_vic.c | 105 +++--
128
hw/misc/aspeed_xdma.c | 165 ++++++++
129
hw/pci-host/designware.c | 18 +-
130
hw/ssi/aspeed_smc.c | 1 +
131
hw/timer/aspeed_rtc.c | 180 ++++++++
132
hw/timer/aspeed_timer.c | 76 ++--
133
hw/watchdog/wdt_aspeed.c | 20 +
134
target/arm/cpu.c | 232 ++++++++++-
135
target/arm/helper.c | 498 +++++++++-------------
136
target/arm/op_helper.c | 262 ++++++------
137
target/arm/tlb_helper.c | 200 +++++++++
138
target/arm/translate-a64.c | 128 ------
139
target/arm/translate.c | 91 +---
140
target/arm/vfp_helper.c | 199 +++++----
141
MAINTAINERS | 8 +
142
default-configs/aarch64-softmmu.mak | 1 +
143
hw/arm/Kconfig | 14 +
144
hw/misc/trace-events | 3 +
145
hw/timer/trace-events | 4 +
146
39 files changed, 2675 insertions(+), 926 deletions(-)
147
create mode 100644 include/hw/misc/aspeed_xdma.h
148
create mode 100644 include/hw/timer/aspeed_rtc.h
149
create mode 100644 hw/arm/sbsa-ref.c
150
create mode 100644 hw/misc/aspeed_xdma.c
151
create mode 100644 hw/timer/aspeed_rtc.c
152
create mode 100644 target/arm/tlb_helper.c
153
diff view generated by jsdifflib
[Qemu-devel] [PULL 23/46] hw/misc/aspeed_xdma: New device
[PULL 01/72] hw/net/lan9118: Extract lan9118_phy
1
From: Eddie James <eajames@linux.ibm.com>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
The XDMA engine embedded in the Aspeed SOCs performs PCI DMA operations
3
A very similar implementation of the same device exists in imx_fec. Prepare for
4
between the SOC (acting as a BMC) and a host processor in a server.
4
a common implementation by extracting a device model into its own files.
5
5
6
The XDMA engine exists on the AST2400, AST2500, and AST2600 SOCs, so
6
Some migration state has been moved into the new device model which breaks
7
enable it for all of those. Add trace events on the important register
7
migration compatibility for the following machines:
8
writes in the XDMA engine.
8
* smdkc210
9
* realview-*
10
* vexpress-*
11
* kzm
12
* mps2-*
9
13
10
Signed-off-by: Eddie James <eajames@linux.ibm.com>
14
While breaking migration ABI, fix the size of the MII registers to be 16 bit,
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
as defined by IEEE 802.3u.
12
Signed-off-by: Cédric Le Goater <clg@kaod.org>
16
13
Message-id: 20190618165311.27066-21-clg@kaod.org
17
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
14
[clg: - changed title ]
18
Tested-by: Guenter Roeck <linux@roeck-us.net>
15
Signed-off-by: Cédric Le Goater <clg@kaod.org>
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
Message-id: 20241102125724.532843-2-shentey@gmail.com
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
22
---
18
hw/misc/Makefile.objs | 1 +
23
include/hw/net/lan9118_phy.h | 37 ++++++++
19
include/hw/arm/aspeed_soc.h | 3 +
24
hw/net/lan9118.c | 137 +++++-----------------------
20
include/hw/misc/aspeed_xdma.h | 30 +++++++
25
hw/net/lan9118_phy.c | 169 +++++++++++++++++++++++++++++++++++
21
hw/arm/aspeed_soc.c | 17 ++++
26
hw/net/Kconfig | 4 +
22
hw/misc/aspeed_xdma.c | 165 ++++++++++++++++++++++++++++++++++
27
hw/net/meson.build | 1 +
23
hw/misc/trace-events | 3 +
28
5 files changed, 233 insertions(+), 115 deletions(-)
24
6 files changed, 219 insertions(+)
29
create mode 100644 include/hw/net/lan9118_phy.h
25
create mode 100644 include/hw/misc/aspeed_xdma.h
30
create mode 100644 hw/net/lan9118_phy.c
26
create mode 100644 hw/misc/aspeed_xdma.c
27
31
28
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
32
diff --git a/include/hw/net/lan9118_phy.h b/include/hw/net/lan9118_phy.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/misc/Makefile.objs
31
+++ b/hw/misc/Makefile.objs
32
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_ARMSSE_MHU) += armsse-mhu.o
33
34
obj-$(CONFIG_PVPANIC) += pvpanic.o
35
obj-$(CONFIG_AUX) += auxbus.o
36
+obj-$(CONFIG_ASPEED_SOC) += aspeed_xdma.o
37
obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
38
obj-$(CONFIG_MSF2) += msf2-sysreg.o
39
obj-$(CONFIG_NRF51_SOC) += nrf51_rng.o
40
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
41
index XXXXXXX..XXXXXXX 100644
42
--- a/include/hw/arm/aspeed_soc.h
43
+++ b/include/hw/arm/aspeed_soc.h
44
@@ -XXX,XX +XXX,XX @@
45
#include "hw/intc/aspeed_vic.h"
46
#include "hw/misc/aspeed_scu.h"
47
#include "hw/misc/aspeed_sdmc.h"
48
+#include "hw/misc/aspeed_xdma.h"
49
#include "hw/timer/aspeed_timer.h"
50
#include "hw/timer/aspeed_rtc.h"
51
#include "hw/i2c/aspeed_i2c.h"
52
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
53
AspeedTimerCtrlState timerctrl;
54
AspeedI2CState i2c;
55
AspeedSCUState scu;
56
+ AspeedXDMAState xdma;
57
AspeedSMCState fmc;
58
AspeedSMCState spi[ASPEED_SPIS_NUM];
59
AspeedSDMCState sdmc;
60
@@ -XXX,XX +XXX,XX @@ enum {
61
ASPEED_ETH1,
62
ASPEED_ETH2,
63
ASPEED_SDRAM,
64
+ ASPEED_XDMA,
65
};
66
67
#endif /* ASPEED_SOC_H */
68
diff --git a/include/hw/misc/aspeed_xdma.h b/include/hw/misc/aspeed_xdma.h
69
new file mode 100644
33
new file mode 100644
70
index XXXXXXX..XXXXXXX
34
index XXXXXXX..XXXXXXX
71
--- /dev/null
35
--- /dev/null
72
+++ b/include/hw/misc/aspeed_xdma.h
36
+++ b/include/hw/net/lan9118_phy.h
73
@@ -XXX,XX +XXX,XX @@
37
@@ -XXX,XX +XXX,XX @@
74
+/*
38
+/*
75
+ * ASPEED XDMA Controller
39
+ * SMSC LAN9118 PHY emulation
76
+ * Eddie James <eajames@linux.ibm.com>
77
+ *
40
+ *
78
+ * Copyright (C) 2019 IBM Corp.
41
+ * Copyright (c) 2009 CodeSourcery, LLC.
79
+ * SPDX-License-Identifer: GPL-2.0-or-later
42
+ * Written by Paul Brook
43
+ *
44
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
45
+ * See the COPYING file in the top-level directory.
80
+ */
46
+ */
81
+
47
+
82
+#ifndef ASPEED_XDMA_H
48
+#ifndef HW_NET_LAN9118_PHY_H
83
+#define ASPEED_XDMA_H
49
+#define HW_NET_LAN9118_PHY_H
84
+
50
+
51
+#include "qom/object.h"
85
+#include "hw/sysbus.h"
52
+#include "hw/sysbus.h"
86
+
53
+
87
+#define TYPE_ASPEED_XDMA "aspeed.xdma"
54
+#define TYPE_LAN9118_PHY "lan9118-phy"
88
+#define ASPEED_XDMA(obj) OBJECT_CHECK(AspeedXDMAState, (obj), TYPE_ASPEED_XDMA)
55
+OBJECT_DECLARE_SIMPLE_TYPE(Lan9118PhyState, LAN9118_PHY)
89
+
56
+
90
+#define ASPEED_XDMA_NUM_REGS (ASPEED_XDMA_REG_SIZE / sizeof(uint32_t))
57
+typedef struct Lan9118PhyState {
91
+#define ASPEED_XDMA_REG_SIZE 0x7C
58
+ SysBusDevice parent_obj;
92
+
59
+
93
+typedef struct AspeedXDMAState {
60
+ uint16_t status;
94
+ SysBusDevice parent;
61
+ uint16_t control;
95
+
62
+ uint16_t advertise;
96
+ MemoryRegion iomem;
63
+ uint16_t ints;
64
+ uint16_t int_mask;
97
+ qemu_irq irq;
65
+ qemu_irq irq;
98
+
66
+ bool link_down;
99
+ char bmc_cmdq_readp_set;
67
+} Lan9118PhyState;
100
+ uint32_t regs[ASPEED_XDMA_NUM_REGS];
68
+
101
+} AspeedXDMAState;
69
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down);
102
+
70
+void lan9118_phy_reset(Lan9118PhyState *s);
103
+#endif /* ASPEED_XDMA_H */
71
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg);
104
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
72
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val);
73
+
74
+#endif
75
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
105
index XXXXXXX..XXXXXXX 100644
76
index XXXXXXX..XXXXXXX 100644
106
--- a/hw/arm/aspeed_soc.c
77
--- a/hw/net/lan9118.c
107
+++ b/hw/arm/aspeed_soc.c
78
+++ b/hw/net/lan9118.c
108
@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2400_memmap[] = {
79
@@ -XXX,XX +XXX,XX @@
109
[ASPEED_VIC] = 0x1E6C0000,
80
#include "net/net.h"
110
[ASPEED_SDMC] = 0x1E6E0000,
81
#include "net/eth.h"
111
[ASPEED_SCU] = 0x1E6E2000,
82
#include "hw/irq.h"
112
+ [ASPEED_XDMA] = 0x1E6E7000,
83
+#include "hw/net/lan9118_phy.h"
113
[ASPEED_ADC] = 0x1E6E9000,
84
#include "hw/net/lan9118.h"
114
[ASPEED_SRAM] = 0x1E720000,
85
#include "hw/ptimer.h"
115
[ASPEED_GPIO] = 0x1E780000,
86
#include "hw/qdev-properties.h"
116
@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2500_memmap[] = {
87
@@ -XXX,XX +XXX,XX @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
117
[ASPEED_VIC] = 0x1E6C0000,
88
#define MAC_CR_RXEN 0x00000004
118
[ASPEED_SDMC] = 0x1E6E0000,
89
#define MAC_CR_RESERVED 0x7f404213
119
[ASPEED_SCU] = 0x1E6E2000,
90
120
+ [ASPEED_XDMA] = 0x1E6E7000,
91
-#define PHY_INT_ENERGYON 0x80
121
[ASPEED_ADC] = 0x1E6E9000,
92
-#define PHY_INT_AUTONEG_COMPLETE 0x40
122
[ASPEED_SRAM] = 0x1E720000,
93
-#define PHY_INT_FAULT 0x20
123
[ASPEED_GPIO] = 0x1E780000,
94
-#define PHY_INT_DOWN 0x10
124
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2400_irqmap[] = {
95
-#define PHY_INT_AUTONEG_LP 0x08
125
[ASPEED_I2C] = 12,
96
-#define PHY_INT_PARFAULT 0x04
126
[ASPEED_ETH1] = 2,
97
-#define PHY_INT_AUTONEG_PAGE 0x02
127
[ASPEED_ETH2] = 3,
98
-
128
+ [ASPEED_XDMA] = 6,
99
#define GPT_TIMER_EN 0x20000000
129
};
100
130
101
/*
131
#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
102
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
132
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
103
uint32_t mac_mii_data;
133
sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
104
uint32_t mac_flow;
134
sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
105
106
- uint32_t phy_status;
107
- uint32_t phy_control;
108
- uint32_t phy_advertise;
109
- uint32_t phy_int;
110
- uint32_t phy_int_mask;
111
+ Lan9118PhyState mii;
112
+ IRQState mii_irq;
113
114
int32_t eeprom_writable;
115
uint8_t eeprom[128];
116
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
117
118
static const VMStateDescription vmstate_lan9118 = {
119
.name = "lan9118",
120
- .version_id = 2,
121
- .minimum_version_id = 1,
122
+ .version_id = 3,
123
+ .minimum_version_id = 3,
124
.fields = (const VMStateField[]) {
125
VMSTATE_PTIMER(timer, lan9118_state),
126
VMSTATE_UINT32(irq_cfg, lan9118_state),
127
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118 = {
128
VMSTATE_UINT32(mac_mii_acc, lan9118_state),
129
VMSTATE_UINT32(mac_mii_data, lan9118_state),
130
VMSTATE_UINT32(mac_flow, lan9118_state),
131
- VMSTATE_UINT32(phy_status, lan9118_state),
132
- VMSTATE_UINT32(phy_control, lan9118_state),
133
- VMSTATE_UINT32(phy_advertise, lan9118_state),
134
- VMSTATE_UINT32(phy_int, lan9118_state),
135
- VMSTATE_UINT32(phy_int_mask, lan9118_state),
136
VMSTATE_INT32(eeprom_writable, lan9118_state),
137
VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128),
138
VMSTATE_INT32(tx_fifo_size, lan9118_state),
139
@@ -XXX,XX +XXX,XX @@ static void lan9118_reload_eeprom(lan9118_state *s)
140
lan9118_mac_changed(s);
141
}
142
143
-static void phy_update_irq(lan9118_state *s)
144
+static void lan9118_update_irq(void *opaque, int n, int level)
145
{
146
- if (s->phy_int & s->phy_int_mask) {
147
+ lan9118_state *s = opaque;
148
+
149
+ if (level) {
150
s->int_sts |= PHY_INT;
151
} else {
152
s->int_sts &= ~PHY_INT;
153
@@ -XXX,XX +XXX,XX @@ static void phy_update_irq(lan9118_state *s)
154
lan9118_update(s);
155
}
156
157
-static void phy_update_link(lan9118_state *s)
158
-{
159
- /* Autonegotiation status mirrors link status. */
160
- if (qemu_get_queue(s->nic)->link_down) {
161
- s->phy_status &= ~0x0024;
162
- s->phy_int |= PHY_INT_DOWN;
163
- } else {
164
- s->phy_status |= 0x0024;
165
- s->phy_int |= PHY_INT_ENERGYON;
166
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
167
- }
168
- phy_update_irq(s);
169
-}
170
-
171
static void lan9118_set_link(NetClientState *nc)
172
{
173
- phy_update_link(qemu_get_nic_opaque(nc));
174
-}
175
-
176
-static void phy_reset(lan9118_state *s)
177
-{
178
- s->phy_status = 0x7809;
179
- s->phy_control = 0x3000;
180
- s->phy_advertise = 0x01e1;
181
- s->phy_int_mask = 0;
182
- s->phy_int = 0;
183
- phy_update_link(s);
184
+ lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii,
185
+ nc->link_down);
186
}
187
188
static void lan9118_reset(DeviceState *d)
189
@@ -XXX,XX +XXX,XX @@ static void lan9118_reset(DeviceState *d)
190
s->read_word_n = 0;
191
s->write_word_n = 0;
192
193
- phy_reset(s);
194
-
195
s->eeprom_writable = 0;
196
lan9118_reload_eeprom(s);
197
}
198
@@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s)
199
uint32_t status;
200
201
/* FIXME: Honor TX disable, and allow queueing of packets. */
202
- if (s->phy_control & 0x4000) {
203
+ if (s->mii.control & 0x4000) {
204
/* This assumes the receive routine doesn't touch the VLANClient. */
205
qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
206
} else {
207
@@ -XXX,XX +XXX,XX @@ static void tx_fifo_push(lan9118_state *s, uint32_t val)
135
}
208
}
136
+
137
+ sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
138
+ TYPE_ASPEED_XDMA);
139
}
209
}
140
210
141
static void aspeed_soc_realize(DeviceState *dev, Error **errp)
211
-static uint32_t do_phy_read(lan9118_state *s, int reg)
142
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
212
-{
143
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
213
- uint32_t val;
144
aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
214
-
145
}
215
- switch (reg) {
146
+
216
- case 0: /* Basic Control */
147
+ /* XDMA */
217
- return s->phy_control;
148
+ object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
218
- case 1: /* Basic Status */
149
+ if (err) {
219
- return s->phy_status;
150
+ error_propagate(errp, err);
220
- case 2: /* ID1 */
221
- return 0x0007;
222
- case 3: /* ID2 */
223
- return 0xc0d1;
224
- case 4: /* Auto-neg advertisement */
225
- return s->phy_advertise;
226
- case 5: /* Auto-neg Link Partner Ability */
227
- return 0x0f71;
228
- case 6: /* Auto-neg Expansion */
229
- return 1;
230
- /* TODO 17, 18, 27, 29, 30, 31 */
231
- case 29: /* Interrupt source. */
232
- val = s->phy_int;
233
- s->phy_int = 0;
234
- phy_update_irq(s);
235
- return val;
236
- case 30: /* Interrupt mask */
237
- return s->phy_int_mask;
238
- default:
239
- qemu_log_mask(LOG_GUEST_ERROR,
240
- "do_phy_read: PHY read reg %d\n", reg);
241
- return 0;
242
- }
243
-}
244
-
245
-static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
246
-{
247
- switch (reg) {
248
- case 0: /* Basic Control */
249
- if (val & 0x8000) {
250
- phy_reset(s);
251
- break;
252
- }
253
- s->phy_control = val & 0x7980;
254
- /* Complete autonegotiation immediately. */
255
- if (val & 0x1000) {
256
- s->phy_status |= 0x0020;
257
- }
258
- break;
259
- case 4: /* Auto-neg advertisement */
260
- s->phy_advertise = (val & 0x2d7f) | 0x80;
261
- break;
262
- /* TODO 17, 18, 27, 31 */
263
- case 30: /* Interrupt mask */
264
- s->phy_int_mask = val & 0xff;
265
- phy_update_irq(s);
266
- break;
267
- default:
268
- qemu_log_mask(LOG_GUEST_ERROR,
269
- "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
270
- }
271
-}
272
-
273
static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
274
{
275
switch (reg) {
276
@@ -XXX,XX +XXX,XX @@ static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
277
if (val & 2) {
278
DPRINTF("PHY write %d = 0x%04x\n",
279
(val >> 6) & 0x1f, s->mac_mii_data);
280
- do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
281
+ lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data);
282
} else {
283
- s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
284
+ s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f);
285
DPRINTF("PHY read %d = 0x%04x\n",
286
(val >> 6) & 0x1f, s->mac_mii_data);
287
}
288
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
289
break;
290
case CSR_PMT_CTRL:
291
if (val & 0x400) {
292
- phy_reset(s);
293
+ lan9118_phy_reset(&s->mii);
294
}
295
s->pmt_ctrl &= ~0x34e;
296
s->pmt_ctrl |= (val & 0x34e);
297
@@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp)
298
const MemoryRegionOps *mem_ops =
299
s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops;
300
301
+ qemu_init_irq(&s->mii_irq, lan9118_update_irq, s, 0);
302
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
303
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
151
+ return;
304
+ return;
152
+ }
305
+ }
153
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
306
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
154
+ sc->info->memmap[ASPEED_XDMA]);
307
+
155
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
308
memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s,
156
+ aspeed_soc_get_irq(s, ASPEED_XDMA));
309
"lan9118-mmio", 0x100);
157
}
310
sysbus_init_mmio(sbd, &s->mmio);
158
static Property aspeed_soc_properties[] = {
311
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
159
DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
160
diff --git a/hw/misc/aspeed_xdma.c b/hw/misc/aspeed_xdma.c
161
new file mode 100644
312
new file mode 100644
162
index XXXXXXX..XXXXXXX
313
index XXXXXXX..XXXXXXX
163
--- /dev/null
314
--- /dev/null
164
+++ b/hw/misc/aspeed_xdma.c
315
+++ b/hw/net/lan9118_phy.c
165
@@ -XXX,XX +XXX,XX @@
316
@@ -XXX,XX +XXX,XX @@
166
+/*
317
+/*
167
+ * ASPEED XDMA Controller
318
+ * SMSC LAN9118 PHY emulation
168
+ * Eddie James <eajames@linux.ibm.com>
169
+ *
319
+ *
170
+ * Copyright (C) 2019 IBM Corp
320
+ * Copyright (c) 2009 CodeSourcery, LLC.
171
+ * SPDX-License-Identifer: GPL-2.0-or-later
321
+ * Written by Paul Brook
322
+ *
323
+ * This code is licensed under the GNU GPL v2
324
+ *
325
+ * Contributions after 2012-01-13 are licensed under the terms of the
326
+ * GNU GPL, version 2 or (at your option) any later version.
172
+ */
327
+ */
173
+
328
+
174
+#include "qemu/osdep.h"
329
+#include "qemu/osdep.h"
330
+#include "hw/net/lan9118_phy.h"
331
+#include "hw/irq.h"
332
+#include "hw/resettable.h"
333
+#include "migration/vmstate.h"
175
+#include "qemu/log.h"
334
+#include "qemu/log.h"
176
+#include "qemu/error-report.h"
335
+
177
+#include "hw/misc/aspeed_xdma.h"
336
+#define PHY_INT_ENERGYON (1 << 7)
178
+#include "qapi/error.h"
337
+#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
179
+
338
+#define PHY_INT_FAULT (1 << 5)
180
+#include "trace.h"
339
+#define PHY_INT_DOWN (1 << 4)
181
+
340
+#define PHY_INT_AUTONEG_LP (1 << 3)
182
+#define XDMA_BMC_CMDQ_ADDR 0x10
341
+#define PHY_INT_PARFAULT (1 << 2)
183
+#define XDMA_BMC_CMDQ_ENDP 0x14
342
+#define PHY_INT_AUTONEG_PAGE (1 << 1)
184
+#define XDMA_BMC_CMDQ_WRP 0x18
343
+
185
+#define XDMA_BMC_CMDQ_W_MASK 0x0003FFFF
344
+static void lan9118_phy_update_irq(Lan9118PhyState *s)
186
+#define XDMA_BMC_CMDQ_RDP 0x1C
345
+{
187
+#define XDMA_BMC_CMDQ_RDP_MAGIC 0xEE882266
346
+ qemu_set_irq(s->irq, !!(s->ints & s->int_mask));
188
+#define XDMA_IRQ_ENG_CTRL 0x20
347
+}
189
+#define XDMA_IRQ_ENG_CTRL_US_COMP BIT(4)
348
+
190
+#define XDMA_IRQ_ENG_CTRL_DS_COMP BIT(5)
349
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
191
+#define XDMA_IRQ_ENG_CTRL_W_MASK 0xBFEFF07F
350
+{
192
+#define XDMA_IRQ_ENG_STAT 0x24
351
+ uint16_t val;
193
+#define XDMA_IRQ_ENG_STAT_US_COMP BIT(4)
352
+
194
+#define XDMA_IRQ_ENG_STAT_DS_COMP BIT(5)
353
+ switch (reg) {
195
+#define XDMA_IRQ_ENG_STAT_RESET 0xF8000000
354
+ case 0: /* Basic Control */
196
+#define XDMA_MEM_SIZE 0x1000
355
+ return s->control;
197
+
356
+ case 1: /* Basic Status */
198
+#define TO_REG(addr) ((addr) / sizeof(uint32_t))
357
+ return s->status;
199
+
358
+ case 2: /* ID1 */
200
+static uint64_t aspeed_xdma_read(void *opaque, hwaddr addr, unsigned int size)
359
+ return 0x0007;
201
+{
360
+ case 3: /* ID2 */
202
+ uint32_t val = 0;
361
+ return 0xc0d1;
203
+ AspeedXDMAState *xdma = opaque;
362
+ case 4: /* Auto-neg advertisement */
204
+
363
+ return s->advertise;
205
+ if (addr < ASPEED_XDMA_REG_SIZE) {
364
+ case 5: /* Auto-neg Link Partner Ability */
206
+ val = xdma->regs[TO_REG(addr)];
365
+ return 0x0f71;
366
+ case 6: /* Auto-neg Expansion */
367
+ return 1;
368
+ /* TODO 17, 18, 27, 29, 30, 31 */
369
+ case 29: /* Interrupt source. */
370
+ val = s->ints;
371
+ s->ints = 0;
372
+ lan9118_phy_update_irq(s);
373
+ return val;
374
+ case 30: /* Interrupt mask */
375
+ return s->int_mask;
376
+ default:
377
+ qemu_log_mask(LOG_GUEST_ERROR,
378
+ "lan9118_phy_read: PHY read reg %d\n", reg);
379
+ return 0;
207
+ }
380
+ }
208
+
381
+}
209
+ return (uint64_t)val;
382
+
210
+}
383
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
211
+
384
+{
212
+static void aspeed_xdma_write(void *opaque, hwaddr addr, uint64_t val,
385
+ switch (reg) {
213
+ unsigned int size)
386
+ case 0: /* Basic Control */
214
+{
387
+ if (val & 0x8000) {
215
+ unsigned int idx;
388
+ lan9118_phy_reset(s);
216
+ uint32_t val32 = (uint32_t)val;
389
+ break;
217
+ AspeedXDMAState *xdma = opaque;
390
+ }
218
+
391
+ s->control = val & 0x7980;
219
+ if (addr >= ASPEED_XDMA_REG_SIZE) {
392
+ /* Complete autonegotiation immediately. */
220
+ return;
393
+ if (val & 0x1000) {
221
+ }
394
+ s->status |= 0x0020;
222
+
223
+ switch (addr) {
224
+ case XDMA_BMC_CMDQ_ENDP:
225
+ xdma->regs[TO_REG(addr)] = val32 & XDMA_BMC_CMDQ_W_MASK;
226
+ break;
227
+ case XDMA_BMC_CMDQ_WRP:
228
+ idx = TO_REG(addr);
229
+ xdma->regs[idx] = val32 & XDMA_BMC_CMDQ_W_MASK;
230
+ xdma->regs[TO_REG(XDMA_BMC_CMDQ_RDP)] = xdma->regs[idx];
231
+
232
+ trace_aspeed_xdma_write(addr, val);
233
+
234
+ if (xdma->bmc_cmdq_readp_set) {
235
+ xdma->bmc_cmdq_readp_set = 0;
236
+ } else {
237
+ xdma->regs[TO_REG(XDMA_IRQ_ENG_STAT)] |=
238
+ XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP;
239
+
240
+ if (xdma->regs[TO_REG(XDMA_IRQ_ENG_CTRL)] &
241
+ (XDMA_IRQ_ENG_CTRL_US_COMP | XDMA_IRQ_ENG_CTRL_DS_COMP))
242
+ qemu_irq_raise(xdma->irq);
243
+ }
395
+ }
244
+ break;
396
+ break;
245
+ case XDMA_BMC_CMDQ_RDP:
397
+ case 4: /* Auto-neg advertisement */
246
+ trace_aspeed_xdma_write(addr, val);
398
+ s->advertise = (val & 0x2d7f) | 0x80;
247
+
248
+ if (val32 == XDMA_BMC_CMDQ_RDP_MAGIC) {
249
+ xdma->bmc_cmdq_readp_set = 1;
250
+ }
251
+ break;
399
+ break;
252
+ case XDMA_IRQ_ENG_CTRL:
400
+ /* TODO 17, 18, 27, 31 */
253
+ xdma->regs[TO_REG(addr)] = val32 & XDMA_IRQ_ENG_CTRL_W_MASK;
401
+ case 30: /* Interrupt mask */
254
+ break;
402
+ s->int_mask = val & 0xff;
255
+ case XDMA_IRQ_ENG_STAT:
403
+ lan9118_phy_update_irq(s);
256
+ trace_aspeed_xdma_write(addr, val);
257
+
258
+ idx = TO_REG(addr);
259
+ if (val32 & (XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP)) {
260
+ xdma->regs[idx] &=
261
+ ~(XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP);
262
+ qemu_irq_lower(xdma->irq);
263
+ }
264
+ break;
404
+ break;
265
+ default:
405
+ default:
266
+ xdma->regs[TO_REG(addr)] = val32;
406
+ qemu_log_mask(LOG_GUEST_ERROR,
267
+ break;
407
+ "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
268
+ }
408
+ }
269
+}
409
+}
270
+
410
+
271
+static const MemoryRegionOps aspeed_xdma_ops = {
411
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
272
+ .read = aspeed_xdma_read,
412
+{
273
+ .write = aspeed_xdma_write,
413
+ s->link_down = link_down;
274
+ .endianness = DEVICE_NATIVE_ENDIAN,
414
+
275
+ .valid.min_access_size = 4,
415
+ /* Autonegotiation status mirrors link status. */
276
+ .valid.max_access_size = 4,
416
+ if (link_down) {
417
+ s->status &= ~0x0024;
418
+ s->ints |= PHY_INT_DOWN;
419
+ } else {
420
+ s->status |= 0x0024;
421
+ s->ints |= PHY_INT_ENERGYON;
422
+ s->ints |= PHY_INT_AUTONEG_COMPLETE;
423
+ }
424
+ lan9118_phy_update_irq(s);
425
+}
426
+
427
+void lan9118_phy_reset(Lan9118PhyState *s)
428
+{
429
+ s->control = 0x3000;
430
+ s->status = 0x7809;
431
+ s->advertise = 0x01e1;
432
+ s->int_mask = 0;
433
+ s->ints = 0;
434
+ lan9118_phy_update_link(s, s->link_down);
435
+}
436
+
437
+static void lan9118_phy_reset_hold(Object *obj, ResetType type)
438
+{
439
+ Lan9118PhyState *s = LAN9118_PHY(obj);
440
+
441
+ lan9118_phy_reset(s);
442
+}
443
+
444
+static void lan9118_phy_init(Object *obj)
445
+{
446
+ Lan9118PhyState *s = LAN9118_PHY(obj);
447
+
448
+ qdev_init_gpio_out(DEVICE(s), &s->irq, 1);
449
+}
450
+
451
+static const VMStateDescription vmstate_lan9118_phy = {
452
+ .name = "lan9118-phy",
453
+ .version_id = 1,
454
+ .minimum_version_id = 1,
455
+ .fields = (const VMStateField[]) {
456
+ VMSTATE_UINT16(control, Lan9118PhyState),
457
+ VMSTATE_UINT16(status, Lan9118PhyState),
458
+ VMSTATE_UINT16(advertise, Lan9118PhyState),
459
+ VMSTATE_UINT16(ints, Lan9118PhyState),
460
+ VMSTATE_UINT16(int_mask, Lan9118PhyState),
461
+ VMSTATE_BOOL(link_down, Lan9118PhyState),
462
+ VMSTATE_END_OF_LIST()
463
+ }
277
+};
464
+};
278
+
465
+
279
+static void aspeed_xdma_realize(DeviceState *dev, Error **errp)
466
+static void lan9118_phy_class_init(ObjectClass *klass, void *data)
280
+{
467
+{
281
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
468
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
282
+ AspeedXDMAState *xdma = ASPEED_XDMA(dev);
469
+ DeviceClass *dc = DEVICE_CLASS(klass);
283
+
470
+
284
+ sysbus_init_irq(sbd, &xdma->irq);
471
+ rc->phases.hold = lan9118_phy_reset_hold;
285
+ memory_region_init_io(&xdma->iomem, OBJECT(xdma), &aspeed_xdma_ops, xdma,
472
+ dc->vmsd = &vmstate_lan9118_phy;
286
+ TYPE_ASPEED_XDMA, XDMA_MEM_SIZE);
473
+}
287
+ sysbus_init_mmio(sbd, &xdma->iomem);
474
+
288
+}
475
+static const TypeInfo types[] = {
289
+
476
+ {
290
+static void aspeed_xdma_reset(DeviceState *dev)
477
+ .name = TYPE_LAN9118_PHY,
291
+{
478
+ .parent = TYPE_SYS_BUS_DEVICE,
292
+ AspeedXDMAState *xdma = ASPEED_XDMA(dev);
479
+ .instance_size = sizeof(Lan9118PhyState),
293
+
480
+ .instance_init = lan9118_phy_init,
294
+ xdma->bmc_cmdq_readp_set = 0;
481
+ .class_init = lan9118_phy_class_init,
295
+ memset(xdma->regs, 0, ASPEED_XDMA_REG_SIZE);
482
+ }
296
+ xdma->regs[TO_REG(XDMA_IRQ_ENG_STAT)] = XDMA_IRQ_ENG_STAT_RESET;
297
+
298
+ qemu_irq_lower(xdma->irq);
299
+}
300
+
301
+static const VMStateDescription aspeed_xdma_vmstate = {
302
+ .name = TYPE_ASPEED_XDMA,
303
+ .version_id = 1,
304
+ .fields = (VMStateField[]) {
305
+ VMSTATE_UINT32_ARRAY(regs, AspeedXDMAState, ASPEED_XDMA_NUM_REGS),
306
+ VMSTATE_END_OF_LIST(),
307
+ },
308
+};
483
+};
309
+
484
+
310
+static void aspeed_xdma_class_init(ObjectClass *classp, void *data)
485
+DEFINE_TYPES(types)
311
+{
486
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
312
+ DeviceClass *dc = DEVICE_CLASS(classp);
313
+
314
+ dc->realize = aspeed_xdma_realize;
315
+ dc->reset = aspeed_xdma_reset;
316
+ dc->vmsd = &aspeed_xdma_vmstate;
317
+}
318
+
319
+static const TypeInfo aspeed_xdma_info = {
320
+ .name = TYPE_ASPEED_XDMA,
321
+ .parent = TYPE_SYS_BUS_DEVICE,
322
+ .instance_size = sizeof(AspeedXDMAState),
323
+ .class_init = aspeed_xdma_class_init,
324
+};
325
+
326
+static void aspeed_xdma_register_type(void)
327
+{
328
+ type_register_static(&aspeed_xdma_info);
329
+}
330
+type_init(aspeed_xdma_register_type);
331
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
332
index XXXXXXX..XXXXXXX 100644
487
index XXXXXXX..XXXXXXX 100644
333
--- a/hw/misc/trace-events
488
--- a/hw/net/Kconfig
334
+++ b/hw/misc/trace-events
489
+++ b/hw/net/Kconfig
335
@@ -XXX,XX +XXX,XX @@ armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_I
490
@@ -XXX,XX +XXX,XX @@ config VMXNET3_PCI
336
# armsse-mhu.c
491
config SMC91C111
337
armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
492
bool
338
armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
493
339
+
494
+config LAN9118_PHY
340
+# aspeed_xdma.c
495
+ bool
341
+aspeed_xdma_write(uint64_t offset, uint64_t data) "XDMA write: offset 0x%" PRIx64 " data 0x%" PRIx64
496
+
497
config LAN9118
498
bool
499
+ select LAN9118_PHY
500
select PTIMER
501
502
config NE2000_ISA
503
diff --git a/hw/net/meson.build b/hw/net/meson.build
504
index XXXXXXX..XXXXXXX 100644
505
--- a/hw/net/meson.build
506
+++ b/hw/net/meson.build
507
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c'))
508
509
system_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c'))
510
system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c'))
511
+system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c'))
512
system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c'))
513
system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c'))
514
system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c'))
342
--
515
--
343
2.20.1
516
2.34.1
344
345
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/46] aspeed: introduce a configurable number of CPU per machine
[PULL 02/72] hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
1
From: Cédric Le Goater <clg@kaod.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
The current models of the Aspeed SoCs only have one CPU but future
3
imx_fec models the same PHY as lan9118_phy. The code is almost the same with
4
ones will support SMP. Introduce a new num_cpus field at the SoC class
4
imx_fec having more logging and tracing. Merge these improvements into
5
level to define the number of available CPUs per SoC and also
5
lan9118_phy and reuse in imx_fec to fix the code duplication.
6
introduce a 'num-cpus' property to activate the CPUs configured for
7
the machine.
8
6
9
The max_cpus limit of the machine should depend on the SoC definition
7
Some migration state how resides in the new device model which breaks migration
10
but, unfortunately, these values are not available when the machine
8
compatibility for the following machines:
11
class is initialized. This is the reason why we add a check on
9
* imx25-pdk
12
num_cpus in the AspeedSoC realize handler.
10
* sabrelite
11
* mcimx7d-sabre
12
* mcimx6ul-evk
13
13
14
SMP support will be activated when models for such SoCs are implemented.
14
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
15
15
Tested-by: Guenter Roeck <linux@roeck-us.net>
16
Signed-off-by: Cédric Le Goater <clg@kaod.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Joel Stanley <joel@jms.id.au>
17
Message-id: 20241102125724.532843-3-shentey@gmail.com
18
Message-id: 20190618165311.27066-6-clg@kaod.org
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
19
---
21
include/hw/arm/aspeed_soc.h | 5 ++++-
20
include/hw/net/imx_fec.h | 9 ++-
22
hw/arm/aspeed.c | 7 +++++--
21
hw/net/imx_fec.c | 146 ++++-----------------------------------
23
hw/arm/aspeed_soc.c | 33 +++++++++++++++++++++++++++------
22
hw/net/lan9118_phy.c | 82 ++++++++++++++++------
24
3 files changed, 36 insertions(+), 9 deletions(-)
23
hw/net/Kconfig | 1 +
24
hw/net/trace-events | 10 +--
25
5 files changed, 85 insertions(+), 163 deletions(-)
25
26
26
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
27
diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
27
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/arm/aspeed_soc.h
29
--- a/include/hw/net/imx_fec.h
29
+++ b/include/hw/arm/aspeed_soc.h
30
+++ b/include/hw/net/imx_fec.h
30
@@ -XXX,XX +XXX,XX @@
31
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC)
31
32
#define TYPE_IMX_ENET "imx.enet"
32
#define ASPEED_SPIS_NUM 2
33
33
#define ASPEED_WDTS_NUM 3
34
#include "hw/sysbus.h"
34
+#define ASPEED_CPUS_NUM 2
35
+#include "hw/net/lan9118_phy.h"
35
36
+#include "hw/irq.h"
36
typedef struct AspeedSoCState {
37
#include "net/net.h"
37
/*< private >*/
38
38
DeviceState parent;
39
#define ENET_EIR 1
39
40
@@ -XXX,XX +XXX,XX @@ struct IMXFECState {
40
/*< public >*/
41
uint32_t tx_descriptor[ENET_TX_RING_NUM];
41
- ARMCPU cpu;
42
uint32_t tx_ring_num;
42
+ ARMCPU cpu[ASPEED_CPUS_NUM];
43
43
+ uint32_t num_cpus;
44
- uint32_t phy_status;
44
MemoryRegion sram;
45
- uint32_t phy_control;
45
AspeedVICState vic;
46
- uint32_t phy_advertise;
46
AspeedRtcState rtc;
47
- uint32_t phy_int;
47
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCInfo {
48
- uint32_t phy_int_mask;
48
int wdts_num;
49
+ Lan9118PhyState mii;
49
const int *irqmap;
50
+ IRQState mii_irq;
50
const hwaddr *memmap;
51
uint32_t phy_num;
51
+ uint32_t num_cpus;
52
bool phy_connected;
52
} AspeedSoCInfo;
53
struct IMXFECState *phy_consumer;
53
54
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
54
typedef struct AspeedSoCClass {
55
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
56
index XXXXXXX..XXXXXXX 100644
55
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/arm/aspeed.c
56
--- a/hw/net/imx_fec.c
58
+++ b/hw/arm/aspeed.c
57
+++ b/hw/net/imx_fec.c
59
@@ -XXX,XX +XXX,XX @@
58
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth_txdescs = {
60
#include "hw/misc/tmp105.h"
59
61
#include "qemu/log.h"
60
static const VMStateDescription vmstate_imx_eth = {
62
#include "sysemu/block-backend.h"
61
.name = TYPE_IMX_FEC,
63
+#include "sysemu/sysemu.h"
62
- .version_id = 2,
64
#include "hw/loader.h"
63
- .minimum_version_id = 2,
65
#include "qemu/error-report.h"
64
+ .version_id = 3,
66
#include "qemu/units.h"
65
+ .minimum_version_id = 3,
67
66
.fields = (const VMStateField[]) {
68
static struct arm_boot_info aspeed_board_binfo = {
67
VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX),
69
.board_id = -1, /* device-tree-only board */
68
VMSTATE_UINT32(rx_descriptor, IMXFECState),
70
- .nb_cpus = 1,
69
VMSTATE_UINT32(tx_descriptor[0], IMXFECState),
71
};
70
- VMSTATE_UINT32(phy_status, IMXFECState),
72
71
- VMSTATE_UINT32(phy_control, IMXFECState),
73
struct AspeedBoardState {
72
- VMSTATE_UINT32(phy_advertise, IMXFECState),
74
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
73
- VMSTATE_UINT32(phy_int, IMXFECState),
75
&error_abort);
74
- VMSTATE_UINT32(phy_int_mask, IMXFECState),
76
object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs",
75
VMSTATE_END_OF_LIST()
77
&error_abort);
76
},
78
+ object_property_set_int(OBJECT(&bmc->soc), smp_cpus, "num-cpus",
77
.subsections = (const VMStateDescription * const []) {
79
+ &error_abort);
78
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth = {
80
if (machine->kernel_filename) {
81
/*
82
* When booting with a -kernel command line there is no u-boot
83
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
84
aspeed_board_binfo.kernel_cmdline = machine->kernel_cmdline;
85
aspeed_board_binfo.ram_size = ram_size;
86
aspeed_board_binfo.loader_start = sc->info->memmap[ASPEED_SDRAM];
87
+ aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus;
88
89
if (cfg->i2c_init) {
90
cfg->i2c_init(bmc);
91
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data)
92
93
mc->desc = board->desc;
94
mc->init = aspeed_machine_init;
95
- mc->max_cpus = 1;
96
+ mc->max_cpus = ASPEED_CPUS_NUM;
97
mc->no_sdcard = 1;
98
mc->no_floppy = 1;
99
mc->no_cdrom = 1;
100
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/hw/arm/aspeed_soc.c
103
+++ b/hw/arm/aspeed_soc.c
104
@@ -XXX,XX +XXX,XX @@
105
#include "hw/char/serial.h"
106
#include "qemu/log.h"
107
#include "qemu/module.h"
108
+#include "qemu/error-report.h"
109
#include "hw/i2c/aspeed_i2c.h"
110
#include "net/net.h"
111
112
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
113
.wdts_num = 2,
114
.irqmap = aspeed_soc_ast2400_irqmap,
115
.memmap = aspeed_soc_ast2400_memmap,
116
+ .num_cpus = 1,
117
}, {
118
.name = "ast2400-a1",
119
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
120
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
121
.wdts_num = 2,
122
.irqmap = aspeed_soc_ast2400_irqmap,
123
.memmap = aspeed_soc_ast2400_memmap,
124
+ .num_cpus = 1,
125
}, {
126
.name = "ast2400",
127
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
128
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
129
.wdts_num = 2,
130
.irqmap = aspeed_soc_ast2400_irqmap,
131
.memmap = aspeed_soc_ast2400_memmap,
132
+ .num_cpus = 1,
133
}, {
134
.name = "ast2500-a1",
135
.cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
136
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
137
.wdts_num = 3,
138
.irqmap = aspeed_soc_ast2500_irqmap,
139
.memmap = aspeed_soc_ast2500_memmap,
140
+ .num_cpus = 1,
141
},
79
},
142
};
80
};
143
81
144
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
82
-#define PHY_INT_ENERGYON (1 << 7)
145
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
83
-#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
146
int i;
84
-#define PHY_INT_FAULT (1 << 5)
147
85
-#define PHY_INT_DOWN (1 << 4)
148
- object_initialize_child(obj, "cpu", OBJECT(&s->cpu), sizeof(s->cpu),
86
-#define PHY_INT_AUTONEG_LP (1 << 3)
149
- sc->info->cpu_type, &error_abort, NULL);
87
-#define PHY_INT_PARFAULT (1 << 2)
150
+ for (i = 0; i < sc->info->num_cpus; i++) {
88
-#define PHY_INT_AUTONEG_PAGE (1 << 1)
151
+ object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
89
-
152
+ sizeof(s->cpu[i]), sc->info->cpu_type,
90
static void imx_eth_update(IMXFECState *s);
153
+ &error_abort, NULL);
91
92
/*
93
@@ -XXX,XX +XXX,XX @@ static void imx_eth_update(IMXFECState *s);
94
* For now we don't handle any GPIO/interrupt line, so the OS will
95
* have to poll for the PHY status.
96
*/
97
-static void imx_phy_update_irq(IMXFECState *s)
98
+static void imx_phy_update_irq(void *opaque, int n, int level)
99
{
100
- imx_eth_update(s);
101
-}
102
-
103
-static void imx_phy_update_link(IMXFECState *s)
104
-{
105
- /* Autonegotiation status mirrors link status. */
106
- if (qemu_get_queue(s->nic)->link_down) {
107
- trace_imx_phy_update_link("down");
108
- s->phy_status &= ~0x0024;
109
- s->phy_int |= PHY_INT_DOWN;
110
- } else {
111
- trace_imx_phy_update_link("up");
112
- s->phy_status |= 0x0024;
113
- s->phy_int |= PHY_INT_ENERGYON;
114
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
115
- }
116
- imx_phy_update_irq(s);
117
+ imx_eth_update(opaque);
118
}
119
120
static void imx_eth_set_link(NetClientState *nc)
121
{
122
- imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc)));
123
-}
124
-
125
-static void imx_phy_reset(IMXFECState *s)
126
-{
127
- trace_imx_phy_reset();
128
-
129
- s->phy_status = 0x7809;
130
- s->phy_control = 0x3000;
131
- s->phy_advertise = 0x01e1;
132
- s->phy_int_mask = 0;
133
- s->phy_int = 0;
134
- imx_phy_update_link(s);
135
+ lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii,
136
+ nc->link_down);
137
}
138
139
static uint32_t imx_phy_read(IMXFECState *s, int reg)
140
{
141
- uint32_t val;
142
uint32_t phy = reg / 32;
143
144
if (!s->phy_connected) {
145
@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
146
147
reg %= 32;
148
149
- switch (reg) {
150
- case 0: /* Basic Control */
151
- val = s->phy_control;
152
- break;
153
- case 1: /* Basic Status */
154
- val = s->phy_status;
155
- break;
156
- case 2: /* ID1 */
157
- val = 0x0007;
158
- break;
159
- case 3: /* ID2 */
160
- val = 0xc0d1;
161
- break;
162
- case 4: /* Auto-neg advertisement */
163
- val = s->phy_advertise;
164
- break;
165
- case 5: /* Auto-neg Link Partner Ability */
166
- val = 0x0f71;
167
- break;
168
- case 6: /* Auto-neg Expansion */
169
- val = 1;
170
- break;
171
- case 29: /* Interrupt source. */
172
- val = s->phy_int;
173
- s->phy_int = 0;
174
- imx_phy_update_irq(s);
175
- break;
176
- case 30: /* Interrupt mask */
177
- val = s->phy_int_mask;
178
- break;
179
- case 17:
180
- case 18:
181
- case 27:
182
- case 31:
183
- qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n",
184
- TYPE_IMX_FEC, __func__, reg);
185
- val = 0;
186
- break;
187
- default:
188
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
189
- TYPE_IMX_FEC, __func__, reg);
190
- val = 0;
191
- break;
192
- }
193
-
194
- trace_imx_phy_read(val, phy, reg);
195
-
196
- return val;
197
+ return lan9118_phy_read(&s->mii, reg);
198
}
199
200
static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
201
@@ -XXX,XX +XXX,XX @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
202
203
reg %= 32;
204
205
- trace_imx_phy_write(val, phy, reg);
206
-
207
- switch (reg) {
208
- case 0: /* Basic Control */
209
- if (val & 0x8000) {
210
- imx_phy_reset(s);
211
- } else {
212
- s->phy_control = val & 0x7980;
213
- /* Complete autonegotiation immediately. */
214
- if (val & 0x1000) {
215
- s->phy_status |= 0x0020;
216
- }
217
- }
218
- break;
219
- case 4: /* Auto-neg advertisement */
220
- s->phy_advertise = (val & 0x2d7f) | 0x80;
221
- break;
222
- case 30: /* Interrupt mask */
223
- s->phy_int_mask = val & 0xff;
224
- imx_phy_update_irq(s);
225
- break;
226
- case 17:
227
- case 18:
228
- case 27:
229
- case 31:
230
- qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n",
231
- TYPE_IMX_FEC, __func__, reg);
232
- break;
233
- default:
234
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
235
- TYPE_IMX_FEC, __func__, reg);
236
- break;
237
- }
238
+ lan9118_phy_write(&s->mii, reg, val);
239
}
240
241
static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr)
242
@@ -XXX,XX +XXX,XX @@ static void imx_eth_reset(DeviceState *d)
243
244
s->rx_descriptor = 0;
245
memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor));
246
-
247
- /* We also reset the PHY */
248
- imx_phy_reset(s);
249
}
250
251
static uint32_t imx_default_read(IMXFECState *s, uint32_t index)
252
@@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
253
sysbus_init_irq(sbd, &s->irq[0]);
254
sysbus_init_irq(sbd, &s->irq[1]);
255
256
+ qemu_init_irq(&s->mii_irq, imx_phy_update_irq, s, 0);
257
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
258
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
259
+ return;
154
+ }
260
+ }
155
261
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
156
sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
262
+
157
TYPE_ASPEED_SCU);
263
qemu_macaddr_default_if_unset(&s->conf.macaddr);
158
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
264
159
create_unimplemented_device("aspeed_soc.io", sc->info->memmap[ASPEED_IOMEM],
265
s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf,
160
ASPEED_SOC_IOMEM_SIZE);
266
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
161
267
index XXXXXXX..XXXXXXX 100644
162
+ if (s->num_cpus > sc->info->num_cpus) {
268
--- a/hw/net/lan9118_phy.c
163
+ warn_report("%s: invalid number of CPUs %d, using default %d",
269
+++ b/hw/net/lan9118_phy.c
164
+ sc->info->name, s->num_cpus, sc->info->num_cpus);
270
@@ -XXX,XX +XXX,XX @@
165
+ s->num_cpus = sc->info->num_cpus;
271
* Copyright (c) 2009 CodeSourcery, LLC.
166
+ }
272
* Written by Paul Brook
167
+
273
*
168
/* CPU */
274
+ * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
169
- object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
275
+ *
170
- if (err) {
276
* This code is licensed under the GNU GPL v2
171
- error_propagate(errp, err);
277
*
172
- return;
278
* Contributions after 2012-01-13 are licensed under the terms of the
173
+ for (i = 0; i < s->num_cpus; i++) {
279
@@ -XXX,XX +XXX,XX @@
174
+ object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
280
#include "hw/resettable.h"
175
+ if (err) {
281
#include "migration/vmstate.h"
176
+ error_propagate(errp, err);
282
#include "qemu/log.h"
177
+ return;
283
+#include "trace.h"
178
+ }
284
285
#define PHY_INT_ENERGYON (1 << 7)
286
#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
287
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
288
289
switch (reg) {
290
case 0: /* Basic Control */
291
- return s->control;
292
+ val = s->control;
293
+ break;
294
case 1: /* Basic Status */
295
- return s->status;
296
+ val = s->status;
297
+ break;
298
case 2: /* ID1 */
299
- return 0x0007;
300
+ val = 0x0007;
301
+ break;
302
case 3: /* ID2 */
303
- return 0xc0d1;
304
+ val = 0xc0d1;
305
+ break;
306
case 4: /* Auto-neg advertisement */
307
- return s->advertise;
308
+ val = s->advertise;
309
+ break;
310
case 5: /* Auto-neg Link Partner Ability */
311
- return 0x0f71;
312
+ val = 0x0f71;
313
+ break;
314
case 6: /* Auto-neg Expansion */
315
- return 1;
316
- /* TODO 17, 18, 27, 29, 30, 31 */
317
+ val = 1;
318
+ break;
319
case 29: /* Interrupt source. */
320
val = s->ints;
321
s->ints = 0;
322
lan9118_phy_update_irq(s);
323
- return val;
324
+ break;
325
case 30: /* Interrupt mask */
326
- return s->int_mask;
327
+ val = s->int_mask;
328
+ break;
329
+ case 17:
330
+ case 18:
331
+ case 27:
332
+ case 31:
333
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
334
+ __func__, reg);
335
+ val = 0;
336
+ break;
337
default:
338
- qemu_log_mask(LOG_GUEST_ERROR,
339
- "lan9118_phy_read: PHY read reg %d\n", reg);
340
- return 0;
341
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
342
+ __func__, reg);
343
+ val = 0;
344
+ break;
179
}
345
}
180
346
+
181
/* SRAM */
347
+ trace_lan9118_phy_read(val, reg);
182
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
348
+
183
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
349
+ return val;
184
aspeed_soc_get_irq(s, ASPEED_ETH1));
350
}
185
}
351
186
+static Property aspeed_soc_properties[] = {
352
void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
187
+ DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
188
+ DEFINE_PROP_END_OF_LIST(),
189
+};
190
191
static void aspeed_soc_class_init(ObjectClass *oc, void *data)
192
{
353
{
193
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
354
+ trace_lan9118_phy_write(val, reg);
194
dc->realize = aspeed_soc_realize;
355
+
195
/* Reason: Uses serial_hds and nd_table in realize() directly */
356
switch (reg) {
196
dc->user_creatable = false;
357
case 0: /* Basic Control */
197
+ dc->props = aspeed_soc_properties;
358
if (val & 0x8000) {
198
}
359
lan9118_phy_reset(s);
199
360
- break;
200
static const TypeInfo aspeed_soc_type_info = {
361
- }
362
- s->control = val & 0x7980;
363
- /* Complete autonegotiation immediately. */
364
- if (val & 0x1000) {
365
- s->status |= 0x0020;
366
+ } else {
367
+ s->control = val & 0x7980;
368
+ /* Complete autonegotiation immediately. */
369
+ if (val & 0x1000) {
370
+ s->status |= 0x0020;
371
+ }
372
}
373
break;
374
case 4: /* Auto-neg advertisement */
375
s->advertise = (val & 0x2d7f) | 0x80;
376
break;
377
- /* TODO 17, 18, 27, 31 */
378
case 30: /* Interrupt mask */
379
s->int_mask = val & 0xff;
380
lan9118_phy_update_irq(s);
381
break;
382
+ case 17:
383
+ case 18:
384
+ case 27:
385
+ case 31:
386
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
387
+ __func__, reg);
388
+ break;
389
default:
390
- qemu_log_mask(LOG_GUEST_ERROR,
391
- "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
392
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
393
+ __func__, reg);
394
+ break;
395
}
396
}
397
398
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
399
400
/* Autonegotiation status mirrors link status. */
401
if (link_down) {
402
+ trace_lan9118_phy_update_link("down");
403
s->status &= ~0x0024;
404
s->ints |= PHY_INT_DOWN;
405
} else {
406
+ trace_lan9118_phy_update_link("up");
407
s->status |= 0x0024;
408
s->ints |= PHY_INT_ENERGYON;
409
s->ints |= PHY_INT_AUTONEG_COMPLETE;
410
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
411
412
void lan9118_phy_reset(Lan9118PhyState *s)
413
{
414
+ trace_lan9118_phy_reset();
415
+
416
s->control = 0x3000;
417
s->status = 0x7809;
418
s->advertise = 0x01e1;
419
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118_phy = {
420
.version_id = 1,
421
.minimum_version_id = 1,
422
.fields = (const VMStateField[]) {
423
- VMSTATE_UINT16(control, Lan9118PhyState),
424
VMSTATE_UINT16(status, Lan9118PhyState),
425
+ VMSTATE_UINT16(control, Lan9118PhyState),
426
VMSTATE_UINT16(advertise, Lan9118PhyState),
427
VMSTATE_UINT16(ints, Lan9118PhyState),
428
VMSTATE_UINT16(int_mask, Lan9118PhyState),
429
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
430
index XXXXXXX..XXXXXXX 100644
431
--- a/hw/net/Kconfig
432
+++ b/hw/net/Kconfig
433
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_SUN8I_EMAC
434
435
config IMX_FEC
436
bool
437
+ select LAN9118_PHY
438
439
config CADENCE
440
bool
441
diff --git a/hw/net/trace-events b/hw/net/trace-events
442
index XXXXXXX..XXXXXXX 100644
443
--- a/hw/net/trace-events
444
+++ b/hw/net/trace-events
445
@@ -XXX,XX +XXX,XX @@ allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u"
446
allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64
447
allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
448
449
+# lan9118_phy.c
450
+lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16
451
+lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16
452
+lan9118_phy_update_link(const char *s) "%s"
453
+lan9118_phy_reset(void) ""
454
+
455
# lance.c
456
lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x"
457
lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x"
458
@@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
459
i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
460
461
# imx_fec.c
462
-imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
463
imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)"
464
-imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
465
imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)"
466
-imx_phy_update_link(const char *s) "%s"
467
-imx_phy_reset(void) ""
468
imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
469
imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x"
470
imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit"
201
--
471
--
202
2.20.1
472
2.34.1
203
204
diff view generated by jsdifflib
[Qemu-devel] [PULL 44/46] target/arm: Restrict PSCI to TCG
[PULL 03/72] hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Under KVM, the kernel gets the HVC call and handle the PSCI requests.
3
Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and
4
fixes the MSB of selector field to be zero, as specified in the datasheet.
4
5
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Fixes: 2a424990170b "LAN9118 emulation"
6
Message-id: 20190701132516.26392-20-philmd@redhat.com
7
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
8
Tested-by: Guenter Roeck <linux@roeck-us.net>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20241102125724.532843-4-shentey@gmail.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
target/arm/internals.h | 6 +++++-
13
hw/net/lan9118_phy.c | 2 +-
11
1 file changed, 5 insertions(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
12
15
13
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/internals.h
18
--- a/hw/net/lan9118_phy.c
16
+++ b/target/arm/internals.h
19
+++ b/hw/net/lan9118_phy.c
17
@@ -XXX,XX +XXX,XX @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
20
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
18
/* Callback function for when a watchpoint or breakpoint triggers. */
21
val = s->advertise;
19
void arm_debug_excp_handler(CPUState *cs);
22
break;
20
23
case 5: /* Auto-neg Link Partner Ability */
21
-#ifdef CONFIG_USER_ONLY
24
- val = 0x0f71;
22
+#if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG)
25
+ val = 0x0fe1;
23
static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
26
break;
24
{
27
case 6: /* Auto-neg Expansion */
25
return false;
28
val = 1;
26
}
27
+static inline void arm_handle_psci_call(ARMCPU *cpu)
28
+{
29
+ g_assert_not_reached();
30
+}
31
#else
32
/* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
33
bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
34
--
29
--
35
2.20.1
30
2.34.1
36
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/46] aspeed/timer: Ensure positive muldiv delta
[PULL 04/72] hw/net/lan9118_phy: Reuse MII constants
1
From: Christian Svensson <bluecmd@google.com>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
If the host decrements the counter register that results in a negative
3
Prefer named constants over magic values for better readability.
4
delta. This is then passed to muldiv64 which only handles unsigned
5
numbers resulting in bogus results.
6
4
7
This fix ensures the delta being operated on is positive.
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
6
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
9
Test case: kexec a kernel using aspeed_timer and it will freeze on the
7
Tested-by: Guenter Roeck <linux@roeck-us.net>
10
second bootup when the kernel initializes the timer. With this patch
8
Message-id: 20241102125724.532843-5-shentey@gmail.com
11
that no longer happens and the timer appears to run OK.
12
13
Signed-off-by: Christian Svensson <bluecmd@google.com>
14
Signed-off-by: Cédric Le Goater <clg@kaod.org>
15
Reviewed-by: Joel Stanley <joel@jms.id.au>
16
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
17
Message-id: 20190618165311.27066-12-clg@kaod.org
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
10
---
20
hw/timer/aspeed_timer.c | 6 +++++-
11
include/hw/net/mii.h | 6 +++++
21
1 file changed, 5 insertions(+), 1 deletion(-)
12
hw/net/lan9118_phy.c | 63 ++++++++++++++++++++++++++++----------------
13
2 files changed, 46 insertions(+), 23 deletions(-)
22
14
23
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
15
diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h
24
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/timer/aspeed_timer.c
17
--- a/include/hw/net/mii.h
26
+++ b/hw/timer/aspeed_timer.c
18
+++ b/include/hw/net/mii.h
27
@@ -XXX,XX +XXX,XX @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
19
@@ -XXX,XX +XXX,XX @@
28
int64_t delta = (int64_t) value - (int64_t) calculate_ticks(t, now);
20
#define MII_BMSR_JABBER (1 << 1) /* Jabber detected */
29
uint32_t rate = calculate_rate(t);
21
#define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */
30
22
31
- t->start += muldiv64(delta, NANOSECONDS_PER_SECOND, rate);
23
+#define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */
32
+ if (delta >= 0) {
24
#define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymmetric pause */
33
+ t->start += muldiv64(delta, NANOSECONDS_PER_SECOND, rate);
25
#define MII_ANAR_PAUSE (1 << 10) /* Try for pause */
34
+ } else {
26
#define MII_ANAR_TXFD (1 << 8)
35
+ t->start -= muldiv64(-delta, NANOSECONDS_PER_SECOND, rate);
27
@@ -XXX,XX +XXX,XX @@
36
+ }
28
#define MII_ANAR_10FD (1 << 6)
37
aspeed_timer_mod(t);
29
#define MII_ANAR_10 (1 << 5)
30
#define MII_ANAR_CSMACD (1 << 0)
31
+#define MII_ANAR_SELECT (0x001f) /* Selector bits */
32
33
#define MII_ANLPAR_ACK (1 << 14)
34
#define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */
35
@@ -XXX,XX +XXX,XX @@
36
#define RTL8201CP_PHYID1 0x0000
37
#define RTL8201CP_PHYID2 0x8201
38
39
+/* SMSC LAN9118 */
40
+#define SMSCLAN9118_PHYID1 0x0007
41
+#define SMSCLAN9118_PHYID2 0xc0d1
42
+
43
/* RealTek 8211E */
44
#define RTL8211E_PHYID1 0x001c
45
#define RTL8211E_PHYID2 0xc915
46
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/net/lan9118_phy.c
49
+++ b/hw/net/lan9118_phy.c
50
@@ -XXX,XX +XXX,XX @@
51
52
#include "qemu/osdep.h"
53
#include "hw/net/lan9118_phy.h"
54
+#include "hw/net/mii.h"
55
#include "hw/irq.h"
56
#include "hw/resettable.h"
57
#include "migration/vmstate.h"
58
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
59
uint16_t val;
60
61
switch (reg) {
62
- case 0: /* Basic Control */
63
+ case MII_BMCR:
64
val = s->control;
65
break;
66
- case 1: /* Basic Status */
67
+ case MII_BMSR:
68
val = s->status;
69
break;
70
- case 2: /* ID1 */
71
- val = 0x0007;
72
+ case MII_PHYID1:
73
+ val = SMSCLAN9118_PHYID1;
74
break;
75
- case 3: /* ID2 */
76
- val = 0xc0d1;
77
+ case MII_PHYID2:
78
+ val = SMSCLAN9118_PHYID2;
79
break;
80
- case 4: /* Auto-neg advertisement */
81
+ case MII_ANAR:
82
val = s->advertise;
83
break;
84
- case 5: /* Auto-neg Link Partner Ability */
85
- val = 0x0fe1;
86
+ case MII_ANLPAR:
87
+ val = MII_ANLPAR_PAUSEASY | MII_ANLPAR_PAUSE | MII_ANLPAR_T4 |
88
+ MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD |
89
+ MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
90
break;
91
- case 6: /* Auto-neg Expansion */
92
- val = 1;
93
+ case MII_ANER:
94
+ val = MII_ANER_NWAY;
95
break;
96
case 29: /* Interrupt source. */
97
val = s->ints;
98
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
99
trace_lan9118_phy_write(val, reg);
100
101
switch (reg) {
102
- case 0: /* Basic Control */
103
- if (val & 0x8000) {
104
+ case MII_BMCR:
105
+ if (val & MII_BMCR_RESET) {
106
lan9118_phy_reset(s);
107
} else {
108
- s->control = val & 0x7980;
109
+ s->control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 |
110
+ MII_BMCR_AUTOEN | MII_BMCR_PDOWN | MII_BMCR_FD |
111
+ MII_BMCR_CTST);
112
/* Complete autonegotiation immediately. */
113
- if (val & 0x1000) {
114
- s->status |= 0x0020;
115
+ if (val & MII_BMCR_AUTOEN) {
116
+ s->status |= MII_BMSR_AN_COMP;
117
}
38
}
118
}
39
break;
119
break;
120
- case 4: /* Auto-neg advertisement */
121
- s->advertise = (val & 0x2d7f) | 0x80;
122
+ case MII_ANAR:
123
+ s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
124
+ MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
125
+ MII_ANAR_SELECT))
126
+ | MII_ANAR_TX;
127
break;
128
case 30: /* Interrupt mask */
129
s->int_mask = val & 0xff;
130
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
131
/* Autonegotiation status mirrors link status. */
132
if (link_down) {
133
trace_lan9118_phy_update_link("down");
134
- s->status &= ~0x0024;
135
+ s->status &= ~(MII_BMSR_AN_COMP | MII_BMSR_LINK_ST);
136
s->ints |= PHY_INT_DOWN;
137
} else {
138
trace_lan9118_phy_update_link("up");
139
- s->status |= 0x0024;
140
+ s->status |= MII_BMSR_AN_COMP | MII_BMSR_LINK_ST;
141
s->ints |= PHY_INT_ENERGYON;
142
s->ints |= PHY_INT_AUTONEG_COMPLETE;
143
}
144
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_reset(Lan9118PhyState *s)
145
{
146
trace_lan9118_phy_reset();
147
148
- s->control = 0x3000;
149
- s->status = 0x7809;
150
- s->advertise = 0x01e1;
151
+ s->control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100;
152
+ s->status = MII_BMSR_100TX_FD
153
+ | MII_BMSR_100TX_HD
154
+ | MII_BMSR_10T_FD
155
+ | MII_BMSR_10T_HD
156
+ | MII_BMSR_AUTONEG
157
+ | MII_BMSR_EXTCAP;
158
+ s->advertise = MII_ANAR_TXFD
159
+ | MII_ANAR_TX
160
+ | MII_ANAR_10FD
161
+ | MII_ANAR_10
162
+ | MII_ANAR_CSMACD;
163
s->int_mask = 0;
164
s->ints = 0;
165
lan9118_phy_update_link(s, s->link_down);
40
--
166
--
41
2.20.1
167
2.34.1
42
43
diff view generated by jsdifflib
[Qemu-devel] [PULL 33/46] target/arm/helper: Remove unused include
[PULL 05/72] hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
3
The real device advertises this mode and the device model already advertises
4
Message-id: 20190701132516.26392-7-philmd@redhat.com
4
100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to
5
make the model more realistic.
6
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
9
Tested-by: Guenter Roeck <linux@roeck-us.net>
10
Message-id: 20241102125724.532843-6-shentey@gmail.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
12
---
8
target/arm/helper.c | 2 --
13
hw/net/lan9118_phy.c | 4 ++--
9
1 file changed, 2 deletions(-)
14
1 file changed, 2 insertions(+), 2 deletions(-)
10
15
11
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
12
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/helper.c
18
--- a/hw/net/lan9118_phy.c
14
+++ b/target/arm/helper.c
19
+++ b/hw/net/lan9118_phy.c
15
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
16
#include "exec/gdbstub.h"
21
break;
17
#include "exec/helper-proto.h"
22
case MII_ANAR:
18
#include "qemu/host-utils.h"
23
s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
19
-#include "sysemu/arch_init.h"
24
- MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
20
#include "sysemu/sysemu.h"
25
- MII_ANAR_SELECT))
21
#include "qemu/bitops.h"
26
+ MII_ANAR_PAUSE | MII_ANAR_TXFD | MII_ANAR_10FD |
22
#include "qemu/crc32c.h"
27
+ MII_ANAR_10 | MII_ANAR_SELECT))
23
@@ -XXX,XX +XXX,XX @@
28
| MII_ANAR_TX;
24
#include "hw/semihosting/semihost.h"
29
break;
25
#include "sysemu/cpus.h"
30
case 30: /* Interrupt mask */
26
#include "sysemu/kvm.h"
27
-#include "fpu/softfloat.h"
28
#include "qemu/range.h"
29
#include "qapi/qapi-commands-target.h"
30
#include "qapi/error.h"
31
--
31
--
32
2.20.1
32
2.34.1
33
34
diff view generated by jsdifflib
[Qemu-devel] [PULL 24/46] aspeed: vic: Add support for legacy register interface
[PULL 06/72] fpu: handle raising Invalid for infzero in pick_nan_muladd
1
From: Andrew Jeffery <andrew@aj.id.au>
1
For IEEE fused multiply-add, the (0 * inf) + NaN case should raise
2
Invalid for the multiplication of 0 by infinity. Currently we handle
3
this in the per-architecture ifdef ladder in pickNaNMulAdd().
4
However, since this isn't really architecture specific we can hoist
5
it up to the generic code.
2
6
3
The legacy interface only supported up to 32 IRQs, which became
7
For the cases where the infzero test in pickNaNMulAdd was
4
restrictive around the AST2400 generation. QEMU support for the SoCs
8
returning 2, we can delete the check entirely and allow the
5
started with the AST2400 along with an effort to reimplement and
9
code to fall into the normal pick-a-NaN handling, because this
6
upstream drivers for Linux, so up until this point the consumers of the
10
will return 2 anyway (input 'c' being the only NaN in this case).
7
QEMU ASPEED support only required the 64 IRQ register interface.
11
For the cases where infzero was returning 3 to indicate "return
12
the default NaN", we must retain that "return 3".
8
13
9
In an effort to support older BMC firmware, add support for the 32 IRQ
14
For Arm, this looks like it might be a behaviour change because we
10
interface.
15
used to set float_flag_invalid | float_flag_invalid_imz only if C is
16
a quiet NaN. However, it is not, because Arm target code never looks
17
at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we
18
already raised float_flag_invalid via the "abc_mask &
19
float_cmask_snan" check in pick_nan_muladd.
11
20
12
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
21
For any target architecture using the "default implementation" at the
13
Signed-off-by: Cédric Le Goater <clg@kaod.org>
22
bottom of the ifdef, this is a behaviour change but will be fixing a
14
Reviewed-by: Joel Stanley <joel@jms.id.au>
23
bug (where we failed to raise the Invalid exception for (0 * inf +
15
Message-id: 20190618165311.27066-22-clg@kaod.org
24
QNaN). The architectures using the default case are:
25
* hppa
26
* i386
27
* sh4
28
* tricore
29
30
The x86, Tricore and SH4 CPU architecture manuals are clear that this
31
should have raised Invalid; HPPA is a bit vaguer but still seems
32
clear enough.
33
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
36
Message-id: 20241202131347.498124-2-peter.maydell@linaro.org
17
---
37
---
18
hw/intc/aspeed_vic.c | 105 ++++++++++++++++++++++++++-----------------
38
fpu/softfloat-parts.c.inc | 13 +++++++------
19
1 file changed, 63 insertions(+), 42 deletions(-)
39
fpu/softfloat-specialize.c.inc | 29 +----------------------------
40
2 files changed, 8 insertions(+), 34 deletions(-)
20
41
21
diff --git a/hw/intc/aspeed_vic.c b/hw/intc/aspeed_vic.c
42
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
22
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/intc/aspeed_vic.c
44
--- a/fpu/softfloat-parts.c.inc
24
+++ b/hw/intc/aspeed_vic.c
45
+++ b/fpu/softfloat-parts.c.inc
25
@@ -XXX,XX +XXX,XX @@ static void aspeed_vic_set_irq(void *opaque, int irq, int level)
46
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
26
47
int ab_mask, int abc_mask)
27
static uint64_t aspeed_vic_read(void *opaque, hwaddr offset, unsigned size)
28
{
48
{
29
- uint64_t val;
49
int which;
30
- const bool high = !!(offset & 0x4);
50
+ bool infzero = (ab_mask == float_cmask_infzero);
31
- hwaddr n_offset = (offset & ~0x4);
51
32
AspeedVICState *s = (AspeedVICState *)opaque;
52
if (unlikely(abc_mask & float_cmask_snan)) {
33
+ hwaddr n_offset;
53
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
34
+ uint64_t val;
35
+ bool high;
36
37
if (offset < AVIC_NEW_BASE_OFFSET) {
38
- qemu_log_mask(LOG_UNIMP, "%s: Ignoring read from legacy registers "
39
- "at 0x%" HWADDR_PRIx "[%u]\n", __func__, offset, size);
40
- return 0;
41
+ high = false;
42
+ n_offset = offset;
43
+ } else {
44
+ high = !!(offset & 0x4);
45
+ n_offset = (offset & ~0x4);
46
}
54
}
47
55
48
- n_offset -= AVIC_NEW_BASE_OFFSET;
56
- which = pickNaNMulAdd(a->cls, b->cls, c->cls,
49
-
57
- ab_mask == float_cmask_infzero, s);
50
switch (n_offset) {
58
+ if (infzero) {
51
- case 0x0: /* IRQ Status */
59
+ /* This is (0 * inf) + NaN or (inf * 0) + NaN */
52
+ case 0x80: /* IRQ Status */
60
+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
53
+ case 0x00:
61
+ }
54
val = s->raw & ~s->select & s->enable;
62
+
55
break;
63
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
56
- case 0x08: /* FIQ Status */
64
57
+ case 0x88: /* FIQ Status */
65
if (s->default_nan_mode || which == 3) {
58
+ case 0x04:
66
- /*
59
val = s->raw & s->select & s->enable;
67
- * Note that this check is after pickNaNMulAdd so that function
60
break;
68
- * has an opportunity to set the Invalid flag for infzero.
61
- case 0x10: /* Raw Interrupt Status */
69
- */
62
+ case 0x90: /* Raw Interrupt Status */
70
parts_default_nan(a, s);
63
+ case 0x08:
71
return a;
64
val = s->raw;
65
break;
66
- case 0x18: /* Interrupt Selection */
67
+ case 0x98: /* Interrupt Selection */
68
+ case 0x0c:
69
val = s->select;
70
break;
71
- case 0x20: /* Interrupt Enable */
72
+ case 0xa0: /* Interrupt Enable */
73
+ case 0x10:
74
val = s->enable;
75
break;
76
- case 0x30: /* Software Interrupt */
77
+ case 0xb0: /* Software Interrupt */
78
+ case 0x18:
79
val = s->trigger;
80
break;
81
- case 0x40: /* Interrupt Sensitivity */
82
+ case 0xc0: /* Interrupt Sensitivity */
83
+ case 0x24:
84
val = s->sense;
85
break;
86
- case 0x48: /* Interrupt Both Edge Trigger Control */
87
+ case 0xc8: /* Interrupt Both Edge Trigger Control */
88
+ case 0x28:
89
val = s->dual_edge;
90
break;
91
- case 0x50: /* Interrupt Event */
92
+ case 0xd0: /* Interrupt Event */
93
+ case 0x2c:
94
val = s->event;
95
break;
96
- case 0x60: /* Edge Triggered Interrupt Status */
97
+ case 0xe0: /* Edge Triggered Interrupt Status */
98
val = s->raw & ~s->sense;
99
break;
100
/* Illegal */
101
- case 0x28: /* Interrupt Enable Clear */
102
- case 0x38: /* Software Interrupt Clear */
103
- case 0x58: /* Edge Triggered Interrupt Clear */
104
+ case 0xa8: /* Interrupt Enable Clear */
105
+ case 0xb8: /* Software Interrupt Clear */
106
+ case 0xd8: /* Edge Triggered Interrupt Clear */
107
qemu_log_mask(LOG_GUEST_ERROR,
108
"%s: Read of write-only register with offset 0x%"
109
HWADDR_PRIx "\n", __func__, offset);
110
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_vic_read(void *opaque, hwaddr offset, unsigned size)
111
}
72
}
112
if (high) {
73
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
113
val = extract64(val, 32, 19);
74
index XXXXXXX..XXXXXXX 100644
114
+ } else {
75
--- a/fpu/softfloat-specialize.c.inc
115
+ val = extract64(val, 0, 32);
76
+++ b/fpu/softfloat-specialize.c.inc
77
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
78
* the default NaN
79
*/
80
if (infzero && is_qnan(c_cls)) {
81
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
82
return 3;
116
}
83
}
117
trace_aspeed_vic_read(offset, size, val);
84
118
return val;
85
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
119
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_vic_read(void *opaque, hwaddr offset, unsigned size)
86
* case sets InvalidOp and returns the default NaN
120
static void aspeed_vic_write(void *opaque, hwaddr offset, uint64_t data,
87
*/
121
unsigned size)
88
if (infzero) {
122
{
89
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
123
- const bool high = !!(offset & 0x4);
90
return 3;
124
- hwaddr n_offset = (offset & ~0x4);
91
}
125
AspeedVICState *s = (AspeedVICState *)opaque;
92
/* Prefer sNaN over qNaN, in the a, b, c order. */
126
+ hwaddr n_offset;
93
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
127
+ bool high;
94
* For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
128
95
* case sets InvalidOp and returns the input value 'c'
129
if (offset < AVIC_NEW_BASE_OFFSET) {
96
*/
130
- qemu_log_mask(LOG_UNIMP,
97
- if (infzero) {
131
- "%s: Ignoring write to legacy registers at 0x%"
98
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
132
- HWADDR_PRIx "[%u] <- 0x%" PRIx64 "\n", __func__, offset,
99
- return 2;
133
- size, data);
100
- }
134
- return;
101
/* Prefer sNaN over qNaN, in the c, a, b order. */
135
+ high = false;
102
if (is_snan(c_cls)) {
136
+ n_offset = offset;
103
return 2;
137
+ } else {
104
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
138
+ high = !!(offset & 0x4);
105
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
139
+ n_offset = (offset & ~0x4);
106
* case sets InvalidOp and returns the input value 'c'
107
*/
108
- if (infzero) {
109
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
110
- return 2;
111
- }
112
+
113
/* Prefer sNaN over qNaN, in the c, a, b order. */
114
if (is_snan(c_cls)) {
115
return 2;
116
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
117
* to return an input NaN if we have one (ie c) rather than generating
118
* a default NaN
119
*/
120
- if (infzero) {
121
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
122
- return 2;
123
- }
124
125
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
126
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
127
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
128
return 1;
140
}
129
}
141
130
#elif defined(TARGET_RISCV)
142
- n_offset -= AVIC_NEW_BASE_OFFSET;
131
- /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
143
trace_aspeed_vic_write(offset, size, data);
132
- if (infzero) {
144
133
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
145
/* Given we have members using separate enable/clear registers, deposit64()
134
- }
146
@@ -XXX,XX +XXX,XX @@ static void aspeed_vic_write(void *opaque, hwaddr offset, uint64_t data,
135
return 3; /* default NaN */
136
#elif defined(TARGET_S390X)
137
if (infzero) {
138
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
139
return 3;
147
}
140
}
148
141
149
switch (n_offset) {
142
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
150
- case 0x18: /* Interrupt Selection */
143
return 2;
151
+ case 0x98: /* Interrupt Selection */
144
}
152
+ case 0x0c:
145
#elif defined(TARGET_SPARC)
153
/* Register has deposit64() semantics - overwrite requested 32 bits */
146
- /* For (inf,0,nan) return c. */
154
if (high) {
147
- if (infzero) {
155
s->select &= AVIC_L_MASK;
148
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
156
@@ -XXX,XX +XXX,XX @@ static void aspeed_vic_write(void *opaque, hwaddr offset, uint64_t data,
149
- return 2;
157
}
150
- }
158
s->select |= data;
151
/* Prefer SNaN over QNaN, order C, B, A. */
159
break;
152
if (is_snan(c_cls)) {
160
- case 0x20: /* Interrupt Enable */
153
return 2;
161
+ case 0xa0: /* Interrupt Enable */
154
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
162
+ case 0x10:
155
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
163
s->enable |= data;
156
* an input NaN if we have one (ie c).
164
break;
157
*/
165
- case 0x28: /* Interrupt Enable Clear */
158
- if (infzero) {
166
+ case 0xa8: /* Interrupt Enable Clear */
159
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
167
+ case 0x14:
160
- return 2;
168
s->enable &= ~data;
161
- }
169
break;
162
if (status->use_first_nan) {
170
- case 0x30: /* Software Interrupt */
163
if (is_nan(a_cls)) {
171
+ case 0xb0: /* Software Interrupt */
164
return 0;
172
+ case 0x18:
173
qemu_log_mask(LOG_UNIMP, "%s: Software interrupts unavailable. "
174
"IRQs requested: 0x%016" PRIx64 "\n", __func__, data);
175
break;
176
- case 0x38: /* Software Interrupt Clear */
177
+ case 0xb8: /* Software Interrupt Clear */
178
+ case 0x1c:
179
qemu_log_mask(LOG_UNIMP, "%s: Software interrupts unavailable. "
180
"IRQs to be cleared: 0x%016" PRIx64 "\n", __func__, data);
181
break;
182
- case 0x50: /* Interrupt Event */
183
+ case 0xd0: /* Interrupt Event */
184
/* Register has deposit64() semantics - overwrite the top four valid
185
* IRQ bits, as only the top four IRQs (GPIOs) can change their event
186
* type */
187
@@ -XXX,XX +XXX,XX @@ static void aspeed_vic_write(void *opaque, hwaddr offset, uint64_t data,
188
"Ignoring invalid write to interrupt event register");
189
}
190
break;
191
- case 0x58: /* Edge Triggered Interrupt Clear */
192
+ case 0xd8: /* Edge Triggered Interrupt Clear */
193
+ case 0x38:
194
s->raw &= ~(data & ~s->sense);
195
break;
196
- case 0x00: /* IRQ Status */
197
- case 0x08: /* FIQ Status */
198
- case 0x10: /* Raw Interrupt Status */
199
- case 0x40: /* Interrupt Sensitivity */
200
- case 0x48: /* Interrupt Both Edge Trigger Control */
201
- case 0x60: /* Edge Triggered Interrupt Status */
202
+ case 0x80: /* IRQ Status */
203
+ case 0x00:
204
+ case 0x88: /* FIQ Status */
205
+ case 0x04:
206
+ case 0x90: /* Raw Interrupt Status */
207
+ case 0x08:
208
+ case 0xc0: /* Interrupt Sensitivity */
209
+ case 0x24:
210
+ case 0xc8: /* Interrupt Both Edge Trigger Control */
211
+ case 0x28:
212
+ case 0xe0: /* Edge Triggered Interrupt Status */
213
qemu_log_mask(LOG_GUEST_ERROR,
214
"%s: Write of read-only register with offset 0x%"
215
HWADDR_PRIx "\n", __func__, offset);
216
--
165
--
217
2.20.1
166
2.34.1
218
219
diff view generated by jsdifflib
New patch
[PULL 07/72] fpu: Check for default_nan_mode before calling pickNaNMulAdd
1
If the target sets default_nan_mode then we're always going to return
2
the default NaN, and pickNaNMulAdd() no longer has any side effects.
3
For consistency with pickNaN(), check for default_nan_mode before
4
calling pickNaNMulAdd().
1
5
6
When we convert pickNaNMulAdd() to allow runtime selection of the NaN
7
propagation rule, this means we won't have to make the targets which
8
use default_nan_mode also set a propagation rule.
9
10
Since RiscV always uses default_nan_mode, this allows us to remove
11
its ifdef case from pickNaNMulAdd().
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-3-peter.maydell@linaro.org
16
---
17
fpu/softfloat-parts.c.inc | 8 ++++++--
18
fpu/softfloat-specialize.c.inc | 9 +++++++--
19
2 files changed, 13 insertions(+), 4 deletions(-)
20
21
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
22
index XXXXXXX..XXXXXXX 100644
23
--- a/fpu/softfloat-parts.c.inc
24
+++ b/fpu/softfloat-parts.c.inc
25
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
26
float_raise(float_flag_invalid | float_flag_invalid_imz, s);
27
}
28
29
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
30
+ if (s->default_nan_mode) {
31
+ which = 3;
32
+ } else {
33
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ }
35
36
- if (s->default_nan_mode || which == 3) {
37
+ if (which == 3) {
38
parts_default_nan(a, s);
39
return a;
40
}
41
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
42
index XXXXXXX..XXXXXXX 100644
43
--- a/fpu/softfloat-specialize.c.inc
44
+++ b/fpu/softfloat-specialize.c.inc
45
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
46
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
47
bool infzero, float_status *status)
48
{
49
+ /*
50
+ * We guarantee not to require the target to tell us how to
51
+ * pick a NaN if we're always returning the default NaN.
52
+ * But if we're not in default-NaN mode then the target must
53
+ * specify.
54
+ */
55
+ assert(!status->default_nan_mode);
56
#if defined(TARGET_ARM)
57
/* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
58
* the default NaN
59
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
60
} else {
61
return 1;
62
}
63
-#elif defined(TARGET_RISCV)
64
- return 3; /* default NaN */
65
#elif defined(TARGET_S390X)
66
if (infzero) {
67
return 3;
68
--
69
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 42/46] target/arm/vfp_helper: Extract vfp_set_fpscr_from_host()
[PULL 08/72] softfloat: Allow runtime choice of inf * 0 + NaN result
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
IEEE 758 does not define a fixed rule for what NaN to return in
2
2
the case of a fused multiply-add of inf * 0 + NaN. Different
3
The vfp_set_fpscr() helper contains code specific to the host
3
architectures thus do different things:
4
floating point implementation (here the SoftFloat library).
4
* some return the default NaN
5
Extract this code to vfp_set_fpscr_from_host().
5
* some return the input NaN
6
6
* Arm returns the default NaN if the input NaN is quiet,
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
and the input NaN if it is signalling
8
Message-id: 20190701132516.26392-17-philmd@redhat.com
8
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
We want to make this logic be runtime selected rather than
10
hardcoded into the binary, because:
11
* this will let us have multiple targets in one QEMU binary
12
* the Arm FEAT_AFP architectural feature includes letting
13
the guest select a NaN propagation rule at runtime
14
15
In this commit we add an enum for the propagation rule, the field in
16
float_status, and the corresponding getters and setters. We change
17
pickNaNMulAdd to honour this, but because all targets still leave
18
this field at its default 0 value, the fallback logic will pick the
19
rule type with the old ifdef ladder.
20
21
Note that four architectures both use the muladd softfloat functions
22
and did not have a branch of the ifdef ladder to specify their
23
behaviour (and so were ending up with the "default" case, probably
24
wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set
25
default_nan_mode, and so will never get into pickNaNMulAdd(). For
26
HPPA and i386 we retain the same behaviour as the old default-case,
27
which is to not ever return the default NaN. This might not be
28
correct but it is not a behaviour change.
29
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
32
Message-id: 20241202131347.498124-4-peter.maydell@linaro.org
11
---
33
---
12
target/arm/vfp_helper.c | 19 +++++++++++++------
34
include/fpu/softfloat-helpers.h | 11 ++++
13
1 file changed, 13 insertions(+), 6 deletions(-)
35
include/fpu/softfloat-types.h | 23 +++++++++
14
36
fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++-----------
15
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
37
3 files changed, 95 insertions(+), 30 deletions(-)
38
39
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
16
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/vfp_helper.c
41
--- a/include/fpu/softfloat-helpers.h
18
+++ b/target/arm/vfp_helper.c
42
+++ b/include/fpu/softfloat-helpers.h
19
@@ -XXX,XX +XXX,XX @@ static inline int vfp_exceptbits_to_host(int target_bits)
43
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
20
return host_bits;
44
status->float_2nan_prop_rule = rule;
21
}
45
}
22
46
23
+static uint32_t vfp_get_fpscr_from_host(CPUARMState *env)
47
+static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
48
+ float_status *status)
24
+{
49
+{
25
+ uint32_t i;
50
+ status->float_infzeronan_rule = rule;
26
+
27
+ i = get_float_exception_flags(&env->vfp.fp_status);
28
+ i |= get_float_exception_flags(&env->vfp.standard_fp_status);
29
+ /* FZ16 does not generate an input denormal exception. */
30
+ i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
31
+ & ~float_flag_input_denormal);
32
+ return vfp_exceptbits_from_host(i);
33
+}
51
+}
34
+
52
+
35
static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
53
static inline void set_flush_to_zero(bool val, float_status *status)
36
{
54
{
37
int i;
55
status->flush_to_zero = val;
38
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
56
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
39
| (env->vfp.vec_len << 16)
57
return status->float_2nan_prop_rule;
40
| (env->vfp.vec_stride << 20);
58
}
41
59
42
- i = get_float_exception_flags(&env->vfp.fp_status);
60
+static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
43
- i |= get_float_exception_flags(&env->vfp.standard_fp_status);
61
+{
44
- /* FZ16 does not generate an input denormal exception. */
62
+ return status->float_infzeronan_rule;
45
- i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
63
+}
46
- & ~float_flag_input_denormal);
64
+
47
- fpscr |= vfp_exceptbits_from_host(i);
65
static inline bool get_flush_to_zero(float_status *status)
48
+ fpscr |= vfp_get_fpscr_from_host(env);
66
{
49
67
return status->flush_to_zero;
50
i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
68
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
51
fpscr |= i ? FPCR_QC : 0;
69
index XXXXXXX..XXXXXXX 100644
70
--- a/include/fpu/softfloat-types.h
71
+++ b/include/fpu/softfloat-types.h
72
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
73
float_2nan_prop_x87,
74
} Float2NaNPropRule;
75
76
+/*
77
+ * Rule for result of fused multiply-add 0 * Inf + NaN.
78
+ * This must be a NaN, but implementations differ on whether this
79
+ * is the input NaN or the default NaN.
80
+ *
81
+ * You don't need to set this if default_nan_mode is enabled.
82
+ * When not in default-NaN mode, it is an error for the target
83
+ * not to set the rule in float_status if it uses muladd, and we
84
+ * will assert if we need to handle an input NaN and no rule was
85
+ * selected.
86
+ */
87
+typedef enum __attribute__((__packed__)) {
88
+ /* No propagation rule specified */
89
+ float_infzeronan_none = 0,
90
+ /* Result is never the default NaN (so always the input NaN) */
91
+ float_infzeronan_dnan_never,
92
+ /* Result is always the default NaN */
93
+ float_infzeronan_dnan_always,
94
+ /* Result is the default NaN if the input NaN is quiet */
95
+ float_infzeronan_dnan_if_qnan,
96
+} FloatInfZeroNaNRule;
97
+
98
/*
99
* Floating Point Status. Individual architectures may maintain
100
* several versions of float_status for different functions. The
101
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
102
FloatRoundMode float_rounding_mode;
103
FloatX80RoundPrec floatx80_rounding_precision;
104
Float2NaNPropRule float_2nan_prop_rule;
105
+ FloatInfZeroNaNRule float_infzeronan_rule;
106
bool tininess_before_rounding;
107
/* should denormalised results go to zero and set the inexact flag? */
108
bool flush_to_zero;
109
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
110
index XXXXXXX..XXXXXXX 100644
111
--- a/fpu/softfloat-specialize.c.inc
112
+++ b/fpu/softfloat-specialize.c.inc
113
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
114
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
115
bool infzero, float_status *status)
116
{
117
+ FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
118
+
119
/*
120
* We guarantee not to require the target to tell us how to
121
* pick a NaN if we're always returning the default NaN.
122
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
123
* specify.
124
*/
125
assert(!status->default_nan_mode);
126
+
127
+ if (rule == float_infzeronan_none) {
128
+ /*
129
+ * Temporarily fall back to ifdef ladder
130
+ */
131
#if defined(TARGET_ARM)
132
- /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
133
- * the default NaN
134
- */
135
- if (infzero && is_qnan(c_cls)) {
136
- return 3;
137
+ /*
138
+ * For ARM, the (inf,zero,qnan) case returns the default NaN,
139
+ * but (inf,zero,snan) returns the input NaN.
140
+ */
141
+ rule = float_infzeronan_dnan_if_qnan;
142
+#elif defined(TARGET_MIPS)
143
+ if (snan_bit_is_one(status)) {
144
+ /*
145
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
146
+ * case sets InvalidOp and returns the default NaN
147
+ */
148
+ rule = float_infzeronan_dnan_always;
149
+ } else {
150
+ /*
151
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
152
+ * case sets InvalidOp and returns the input value 'c'
153
+ */
154
+ rule = float_infzeronan_dnan_never;
155
+ }
156
+#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
157
+ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
158
+ defined(TARGET_I386) || defined(TARGET_LOONGARCH)
159
+ /*
160
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
161
+ * case sets InvalidOp and returns the input value 'c'
162
+ */
163
+ /*
164
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
165
+ * to return an input NaN if we have one (ie c) rather than generating
166
+ * a default NaN
167
+ */
168
+ rule = float_infzeronan_dnan_never;
169
+#elif defined(TARGET_S390X)
170
+ rule = float_infzeronan_dnan_always;
171
+#endif
172
}
173
174
+ if (infzero) {
175
+ /*
176
+ * Inf * 0 + NaN -- some implementations return the default NaN here,
177
+ * and some return the input NaN.
178
+ */
179
+ switch (rule) {
180
+ case float_infzeronan_dnan_never:
181
+ return 2;
182
+ case float_infzeronan_dnan_always:
183
+ return 3;
184
+ case float_infzeronan_dnan_if_qnan:
185
+ return is_qnan(c_cls) ? 3 : 2;
186
+ default:
187
+ g_assert_not_reached();
188
+ }
189
+ }
190
+
191
+#if defined(TARGET_ARM)
192
+
193
/* This looks different from the ARM ARM pseudocode, because the ARM ARM
194
* puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
195
*/
196
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
197
}
198
#elif defined(TARGET_MIPS)
199
if (snan_bit_is_one(status)) {
200
- /*
201
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
202
- * case sets InvalidOp and returns the default NaN
203
- */
204
- if (infzero) {
205
- return 3;
206
- }
207
/* Prefer sNaN over qNaN, in the a, b, c order. */
208
if (is_snan(a_cls)) {
209
return 0;
210
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
211
return 2;
212
}
213
} else {
214
- /*
215
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
216
- * case sets InvalidOp and returns the input value 'c'
217
- */
218
/* Prefer sNaN over qNaN, in the c, a, b order. */
219
if (is_snan(c_cls)) {
220
return 2;
221
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
222
}
223
}
224
#elif defined(TARGET_LOONGARCH64)
225
- /*
226
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
227
- * case sets InvalidOp and returns the input value 'c'
228
- */
229
-
230
/* Prefer sNaN over qNaN, in the c, a, b order. */
231
if (is_snan(c_cls)) {
232
return 2;
233
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
234
return 1;
235
}
236
#elif defined(TARGET_PPC)
237
- /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
238
- * to return an input NaN if we have one (ie c) rather than generating
239
- * a default NaN
240
- */
241
-
242
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
243
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
244
*/
245
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
246
return 1;
247
}
248
#elif defined(TARGET_S390X)
249
- if (infzero) {
250
- return 3;
251
- }
252
-
253
if (is_snan(a_cls)) {
254
return 0;
255
} else if (is_snan(b_cls)) {
52
--
256
--
53
2.20.1
257
2.34.1
54
55
diff view generated by jsdifflib
New patch
[PULL 09/72] tests/fp: Explicitly set inf-zero-nan rule
1
Explicitly set a rule in the softfloat tests for the inf-zero-nan
2
muladd special case. In meson.build we put -DTARGET_ARM in fpcflags,
3
and so we should select here the Arm rule of
4
float_infzeronan_dnan_if_qnan.
1
5
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241202131347.498124-5-peter.maydell@linaro.org
9
---
10
tests/fp/fp-bench.c | 5 +++++
11
tests/fp/fp-test.c | 5 +++++
12
2 files changed, 10 insertions(+)
13
14
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tests/fp/fp-bench.c
17
+++ b/tests/fp/fp-bench.c
18
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
19
{
20
bench_func_t f;
21
22
+ /*
23
+ * These implementation-defined choices for various things IEEE
24
+ * doesn't specify match those used by the Arm architecture.
25
+ */
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
28
29
f = bench_funcs[operation][precision];
30
g_assert(f);
31
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/tests/fp/fp-test.c
34
+++ b/tests/fp/fp-test.c
35
@@ -XXX,XX +XXX,XX @@ void run_test(void)
36
{
37
unsigned int i;
38
39
+ /*
40
+ * These implementation-defined choices for various things IEEE
41
+ * doesn't specify match those used by the Arm architecture.
42
+ */
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
44
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
45
46
genCases_setLevel(test_level);
47
verCases_maxErrorCount = n_max_errors;
48
--
49
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 39/46] target/arm: Move TLB related routines to tlb_helper.c
[PULL 10/72] target/arm: Set FloatInfZeroNaNRule explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the FloatInfZeroNaNRule explicitly for the Arm target,
2
so we can remove the ifdef from pickNaNMulAdd().
2
3
3
These routines are TCG specific.
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
The arm_deliver_fault() function is only used within the new
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
helper. Make it static.
6
Message-id: 20241202131347.498124-6-peter.maydell@linaro.org
7
---
8
target/arm/cpu.c | 3 +++
9
fpu/softfloat-specialize.c.inc | 8 +-------
10
2 files changed, 4 insertions(+), 7 deletions(-)
6
11
7
Suggested-by: Alex Bennée <alex.bennee@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190701132516.26392-13-philmd@redhat.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/Makefile.objs | 1 +
14
target/arm/internals.h | 3 -
15
target/arm/cpu.c | 6 +-
16
target/arm/helper.c | 53 -----------
17
target/arm/op_helper.c | 135 --------------------------
18
target/arm/tlb_helper.c | 200 +++++++++++++++++++++++++++++++++++++++
19
6 files changed, 205 insertions(+), 193 deletions(-)
20
create mode 100644 target/arm/tlb_helper.c
21
22
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/Makefile.objs
25
+++ b/target/arm/Makefile.objs
26
@@ -XXX,XX +XXX,XX @@ target/arm/translate-sve.o: target/arm/decode-sve.inc.c
27
target/arm/translate.o: target/arm/decode-vfp.inc.c
28
target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
29
30
+obj-y += tlb_helper.o
31
obj-y += translate.o op_helper.o
32
obj-y += crypto_helper.o
33
obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
34
diff --git a/target/arm/internals.h b/target/arm/internals.h
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/internals.h
37
+++ b/target/arm/internals.h
38
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
39
MMUAccessType access_type, int mmu_idx,
40
bool probe, uintptr_t retaddr);
41
42
-void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type,
43
- int mmu_idx, ARMMMUFaultInfo *fi) QEMU_NORETURN;
44
-
45
/* Return true if the stage 1 translation regime is using LPAE format page
46
* tables */
47
bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
48
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
49
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/cpu.c
14
--- a/target/arm/cpu.c
51
+++ b/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
52
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
53
cc->gdb_write_register = arm_cpu_gdb_write_register;
17
* * tininess-before-rounding
54
#ifndef CONFIG_USER_ONLY
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
55
cc->do_interrupt = arm_cpu_do_interrupt;
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
56
- cc->do_unaligned_access = arm_cpu_do_unaligned_access;
20
+ * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
57
- cc->do_transaction_failed = arm_cpu_do_transaction_failed;
21
+ * and the input NaN if it is signalling
58
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
22
*/
59
cc->asidx_from_attrs = arm_asidx_from_attrs;
23
static void arm_set_default_fp_behaviours(float_status *s)
60
cc->vmsd = &vmstate_arm_cpu;
24
{
61
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
25
set_float_detect_tininess(float_tininess_before_rounding, s);
62
#ifdef CONFIG_TCG
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
63
cc->tcg_initialize = arm_translate_init;
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
64
cc->tlb_fill = arm_cpu_tlb_fill;
65
+#if !defined(CONFIG_USER_ONLY)
66
+ cc->do_unaligned_access = arm_cpu_do_unaligned_access;
67
+ cc->do_transaction_failed = arm_cpu_do_transaction_failed;
68
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
69
#endif
70
}
28
}
71
29
72
diff --git a/target/arm/helper.c b/target/arm/helper.c
30
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
73
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
74
--- a/target/arm/helper.c
33
--- a/fpu/softfloat-specialize.c.inc
75
+++ b/target/arm/helper.c
34
+++ b/fpu/softfloat-specialize.c.inc
76
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
77
36
/*
78
#endif
37
* Temporarily fall back to ifdef ladder
79
38
*/
80
-bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
39
-#if defined(TARGET_ARM)
81
- MMUAccessType access_type, int mmu_idx,
82
- bool probe, uintptr_t retaddr)
83
-{
84
- ARMCPU *cpu = ARM_CPU(cs);
85
-
86
-#ifdef CONFIG_USER_ONLY
87
- cpu->env.exception.vaddress = address;
88
- if (access_type == MMU_INST_FETCH) {
89
- cs->exception_index = EXCP_PREFETCH_ABORT;
90
- } else {
91
- cs->exception_index = EXCP_DATA_ABORT;
92
- }
93
- cpu_loop_exit_restore(cs, retaddr);
94
-#else
95
- hwaddr phys_addr;
96
- target_ulong page_size;
97
- int prot, ret;
98
- MemTxAttrs attrs = {};
99
- ARMMMUFaultInfo fi = {};
100
-
101
- /*
102
- * Walk the page table and (if the mapping exists) add the page
103
- * to the TLB. On success, return true. Otherwise, if probing,
104
- * return false. Otherwise populate fsr with ARM DFSR/IFSR fault
105
- * register format, and signal the fault.
106
- */
107
- ret = get_phys_addr(&cpu->env, address, access_type,
108
- core_to_arm_mmu_idx(&cpu->env, mmu_idx),
109
- &phys_addr, &attrs, &prot, &page_size, &fi, NULL);
110
- if (likely(!ret)) {
111
- /*
40
- /*
112
- * Map a single [sub]page. Regions smaller than our declared
41
- * For ARM, the (inf,zero,qnan) case returns the default NaN,
113
- * target page size are handled specially, so for those we
42
- * but (inf,zero,snan) returns the input NaN.
114
- * pass in the exact addresses.
115
- */
43
- */
116
- if (page_size >= TARGET_PAGE_SIZE) {
44
- rule = float_infzeronan_dnan_if_qnan;
117
- phys_addr &= TARGET_PAGE_MASK;
45
-#elif defined(TARGET_MIPS)
118
- address &= TARGET_PAGE_MASK;
46
+#if defined(TARGET_MIPS)
119
- }
47
if (snan_bit_is_one(status)) {
120
- tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
48
/*
121
- prot, mmu_idx, page_size);
49
* For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
122
- return true;
123
- } else if (probe) {
124
- return false;
125
- } else {
126
- /* now we have a real cpu fault */
127
- cpu_restore_state(cs, retaddr, true);
128
- arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
129
- }
130
-#endif
131
-}
132
-
133
/* Note that signed overflow is undefined in C. The following routines are
134
careful to use unsigned types where modulo arithmetic is required.
135
Failure to do so _will_ break on newer gcc. */
136
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
137
index XXXXXXX..XXXXXXX 100644
138
--- a/target/arm/op_helper.c
139
+++ b/target/arm/op_helper.c
140
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn,
141
return val;
142
}
143
144
-#if !defined(CONFIG_USER_ONLY)
145
-
146
-static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
147
- unsigned int target_el,
148
- bool same_el, bool ea,
149
- bool s1ptw, bool is_write,
150
- int fsc)
151
-{
152
- uint32_t syn;
153
-
154
- /*
155
- * ISV is only set for data aborts routed to EL2 and
156
- * never for stage-1 page table walks faulting on stage 2.
157
- *
158
- * Furthermore, ISV is only set for certain kinds of load/stores.
159
- * If the template syndrome does not have ISV set, we should leave
160
- * it cleared.
161
- *
162
- * See ARMv8 specs, D7-1974:
163
- * ISS encoding for an exception from a Data Abort, the
164
- * ISV field.
165
- */
166
- if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) {
167
- syn = syn_data_abort_no_iss(same_el,
168
- ea, 0, s1ptw, is_write, fsc);
169
- } else {
170
- /*
171
- * Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
172
- * syndrome created at translation time.
173
- * Now we create the runtime syndrome with the remaining fields.
174
- */
175
- syn = syn_data_abort_with_iss(same_el,
176
- 0, 0, 0, 0, 0,
177
- ea, 0, s1ptw, is_write, fsc,
178
- false);
179
- /* Merge the runtime syndrome with the template syndrome. */
180
- syn |= template_syn;
181
- }
182
- return syn;
183
-}
184
-
185
-void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type,
186
- int mmu_idx, ARMMMUFaultInfo *fi)
187
-{
188
- CPUARMState *env = &cpu->env;
189
- int target_el;
190
- bool same_el;
191
- uint32_t syn, exc, fsr, fsc;
192
- ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
193
-
194
- target_el = exception_target_el(env);
195
- if (fi->stage2) {
196
- target_el = 2;
197
- env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
198
- }
199
- same_el = (arm_current_el(env) == target_el);
200
-
201
- if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
202
- arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
203
- /*
204
- * LPAE format fault status register : bottom 6 bits are
205
- * status code in the same form as needed for syndrome
206
- */
207
- fsr = arm_fi_to_lfsc(fi);
208
- fsc = extract32(fsr, 0, 6);
209
- } else {
210
- fsr = arm_fi_to_sfsc(fi);
211
- /*
212
- * Short format FSR : this fault will never actually be reported
213
- * to an EL that uses a syndrome register. Use a (currently)
214
- * reserved FSR code in case the constructed syndrome does leak
215
- * into the guest somehow.
216
- */
217
- fsc = 0x3f;
218
- }
219
-
220
- if (access_type == MMU_INST_FETCH) {
221
- syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc);
222
- exc = EXCP_PREFETCH_ABORT;
223
- } else {
224
- syn = merge_syn_data_abort(env->exception.syndrome, target_el,
225
- same_el, fi->ea, fi->s1ptw,
226
- access_type == MMU_DATA_STORE,
227
- fsc);
228
- if (access_type == MMU_DATA_STORE
229
- && arm_feature(env, ARM_FEATURE_V6)) {
230
- fsr |= (1 << 11);
231
- }
232
- exc = EXCP_DATA_ABORT;
233
- }
234
-
235
- env->exception.vaddress = addr;
236
- env->exception.fsr = fsr;
237
- raise_exception(env, exc, syn, target_el);
238
-}
239
-
240
-/* Raise a data fault alignment exception for the specified virtual address */
241
-void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
242
- MMUAccessType access_type,
243
- int mmu_idx, uintptr_t retaddr)
244
-{
245
- ARMCPU *cpu = ARM_CPU(cs);
246
- ARMMMUFaultInfo fi = {};
247
-
248
- /* now we have a real cpu fault */
249
- cpu_restore_state(cs, retaddr, true);
250
-
251
- fi.type = ARMFault_Alignment;
252
- arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
253
-}
254
-
255
-/*
256
- * arm_cpu_do_transaction_failed: handle a memory system error response
257
- * (eg "no device/memory present at address") by raising an external abort
258
- * exception
259
- */
260
-void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
261
- vaddr addr, unsigned size,
262
- MMUAccessType access_type,
263
- int mmu_idx, MemTxAttrs attrs,
264
- MemTxResult response, uintptr_t retaddr)
265
-{
266
- ARMCPU *cpu = ARM_CPU(cs);
267
- ARMMMUFaultInfo fi = {};
268
-
269
- /* now we have a real cpu fault */
270
- cpu_restore_state(cs, retaddr, true);
271
-
272
- fi.ea = arm_extabort_type(response);
273
- fi.type = ARMFault_SyncExternal;
274
- arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi);
275
-}
276
-
277
-#endif /* !defined(CONFIG_USER_ONLY) */
278
-
279
void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t newvalue)
280
{
281
/*
282
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
283
new file mode 100644
284
index XXXXXXX..XXXXXXX
285
--- /dev/null
286
+++ b/target/arm/tlb_helper.c
287
@@ -XXX,XX +XXX,XX @@
288
+/*
289
+ * ARM TLB (Translation lookaside buffer) helpers.
290
+ *
291
+ * This code is licensed under the GNU GPL v2 or later.
292
+ *
293
+ * SPDX-License-Identifier: GPL-2.0-or-later
294
+ */
295
+#include "qemu/osdep.h"
296
+#include "cpu.h"
297
+#include "internals.h"
298
+#include "exec/exec-all.h"
299
+
300
+#if !defined(CONFIG_USER_ONLY)
301
+
302
+static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
303
+ unsigned int target_el,
304
+ bool same_el, bool ea,
305
+ bool s1ptw, bool is_write,
306
+ int fsc)
307
+{
308
+ uint32_t syn;
309
+
310
+ /*
311
+ * ISV is only set for data aborts routed to EL2 and
312
+ * never for stage-1 page table walks faulting on stage 2.
313
+ *
314
+ * Furthermore, ISV is only set for certain kinds of load/stores.
315
+ * If the template syndrome does not have ISV set, we should leave
316
+ * it cleared.
317
+ *
318
+ * See ARMv8 specs, D7-1974:
319
+ * ISS encoding for an exception from a Data Abort, the
320
+ * ISV field.
321
+ */
322
+ if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) {
323
+ syn = syn_data_abort_no_iss(same_el,
324
+ ea, 0, s1ptw, is_write, fsc);
325
+ } else {
326
+ /*
327
+ * Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
328
+ * syndrome created at translation time.
329
+ * Now we create the runtime syndrome with the remaining fields.
330
+ */
331
+ syn = syn_data_abort_with_iss(same_el,
332
+ 0, 0, 0, 0, 0,
333
+ ea, 0, s1ptw, is_write, fsc,
334
+ false);
335
+ /* Merge the runtime syndrome with the template syndrome. */
336
+ syn |= template_syn;
337
+ }
338
+ return syn;
339
+}
340
+
341
+static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
342
+ MMUAccessType access_type,
343
+ int mmu_idx, ARMMMUFaultInfo *fi)
344
+{
345
+ CPUARMState *env = &cpu->env;
346
+ int target_el;
347
+ bool same_el;
348
+ uint32_t syn, exc, fsr, fsc;
349
+ ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
350
+
351
+ target_el = exception_target_el(env);
352
+ if (fi->stage2) {
353
+ target_el = 2;
354
+ env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
355
+ }
356
+ same_el = (arm_current_el(env) == target_el);
357
+
358
+ if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
359
+ arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
360
+ /*
361
+ * LPAE format fault status register : bottom 6 bits are
362
+ * status code in the same form as needed for syndrome
363
+ */
364
+ fsr = arm_fi_to_lfsc(fi);
365
+ fsc = extract32(fsr, 0, 6);
366
+ } else {
367
+ fsr = arm_fi_to_sfsc(fi);
368
+ /*
369
+ * Short format FSR : this fault will never actually be reported
370
+ * to an EL that uses a syndrome register. Use a (currently)
371
+ * reserved FSR code in case the constructed syndrome does leak
372
+ * into the guest somehow.
373
+ */
374
+ fsc = 0x3f;
375
+ }
376
+
377
+ if (access_type == MMU_INST_FETCH) {
378
+ syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc);
379
+ exc = EXCP_PREFETCH_ABORT;
380
+ } else {
381
+ syn = merge_syn_data_abort(env->exception.syndrome, target_el,
382
+ same_el, fi->ea, fi->s1ptw,
383
+ access_type == MMU_DATA_STORE,
384
+ fsc);
385
+ if (access_type == MMU_DATA_STORE
386
+ && arm_feature(env, ARM_FEATURE_V6)) {
387
+ fsr |= (1 << 11);
388
+ }
389
+ exc = EXCP_DATA_ABORT;
390
+ }
391
+
392
+ env->exception.vaddress = addr;
393
+ env->exception.fsr = fsr;
394
+ raise_exception(env, exc, syn, target_el);
395
+}
396
+
397
+/* Raise a data fault alignment exception for the specified virtual address */
398
+void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
399
+ MMUAccessType access_type,
400
+ int mmu_idx, uintptr_t retaddr)
401
+{
402
+ ARMCPU *cpu = ARM_CPU(cs);
403
+ ARMMMUFaultInfo fi = {};
404
+
405
+ /* now we have a real cpu fault */
406
+ cpu_restore_state(cs, retaddr, true);
407
+
408
+ fi.type = ARMFault_Alignment;
409
+ arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
410
+}
411
+
412
+/*
413
+ * arm_cpu_do_transaction_failed: handle a memory system error response
414
+ * (eg "no device/memory present at address") by raising an external abort
415
+ * exception
416
+ */
417
+void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
418
+ vaddr addr, unsigned size,
419
+ MMUAccessType access_type,
420
+ int mmu_idx, MemTxAttrs attrs,
421
+ MemTxResult response, uintptr_t retaddr)
422
+{
423
+ ARMCPU *cpu = ARM_CPU(cs);
424
+ ARMMMUFaultInfo fi = {};
425
+
426
+ /* now we have a real cpu fault */
427
+ cpu_restore_state(cs, retaddr, true);
428
+
429
+ fi.ea = arm_extabort_type(response);
430
+ fi.type = ARMFault_SyncExternal;
431
+ arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi);
432
+}
433
+
434
+#endif /* !defined(CONFIG_USER_ONLY) */
435
+
436
+bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
437
+ MMUAccessType access_type, int mmu_idx,
438
+ bool probe, uintptr_t retaddr)
439
+{
440
+ ARMCPU *cpu = ARM_CPU(cs);
441
+
442
+#ifdef CONFIG_USER_ONLY
443
+ cpu->env.exception.vaddress = address;
444
+ if (access_type == MMU_INST_FETCH) {
445
+ cs->exception_index = EXCP_PREFETCH_ABORT;
446
+ } else {
447
+ cs->exception_index = EXCP_DATA_ABORT;
448
+ }
449
+ cpu_loop_exit_restore(cs, retaddr);
450
+#else
451
+ hwaddr phys_addr;
452
+ target_ulong page_size;
453
+ int prot, ret;
454
+ MemTxAttrs attrs = {};
455
+ ARMMMUFaultInfo fi = {};
456
+
457
+ /*
458
+ * Walk the page table and (if the mapping exists) add the page
459
+ * to the TLB. On success, return true. Otherwise, if probing,
460
+ * return false. Otherwise populate fsr with ARM DFSR/IFSR fault
461
+ * register format, and signal the fault.
462
+ */
463
+ ret = get_phys_addr(&cpu->env, address, access_type,
464
+ core_to_arm_mmu_idx(&cpu->env, mmu_idx),
465
+ &phys_addr, &attrs, &prot, &page_size, &fi, NULL);
466
+ if (likely(!ret)) {
467
+ /*
468
+ * Map a single [sub]page. Regions smaller than our declared
469
+ * target page size are handled specially, so for those we
470
+ * pass in the exact addresses.
471
+ */
472
+ if (page_size >= TARGET_PAGE_SIZE) {
473
+ phys_addr &= TARGET_PAGE_MASK;
474
+ address &= TARGET_PAGE_MASK;
475
+ }
476
+ tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
477
+ prot, mmu_idx, page_size);
478
+ return true;
479
+ } else if (probe) {
480
+ return false;
481
+ } else {
482
+ /* now we have a real cpu fault */
483
+ cpu_restore_state(cs, retaddr, true);
484
+ arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
485
+ }
486
+#endif
487
+}
488
--
50
--
489
2.20.1
51
2.34.1
490
491
diff view generated by jsdifflib
New patch
[PULL 11/72] target/s390: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for s390, so we
2
can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-7-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_infzeronan_rule(float_infzeronan_dnan_always,
21
+ &env->fpu_status);
22
/* fall through */
23
case RESET_TYPE_S390_CPU_NORMAL:
24
env->psw.mask &= ~PSW_MASK_RI;
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
* a default NaN
31
*/
32
rule = float_infzeronan_dnan_never;
33
-#elif defined(TARGET_S390X)
34
- rule = float_infzeronan_dnan_always;
35
#endif
36
}
37
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 12/72] target/ppc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the PPC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-8-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 7 +++++++
9
fpu/softfloat-specialize.c.inc | 7 +------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
22
+ * to return an input NaN if we have one (ie c) rather than generating
23
+ * a default NaN
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
27
28
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
29
ppc_spr_t *spr = &env->spr_cb[i];
30
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
31
index XXXXXXX..XXXXXXX 100644
32
--- a/fpu/softfloat-specialize.c.inc
33
+++ b/fpu/softfloat-specialize.c.inc
34
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
*/
36
rule = float_infzeronan_dnan_never;
37
}
38
-#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
39
+#elif defined(TARGET_SPARC) || \
40
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
41
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
42
/*
43
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
44
* case sets InvalidOp and returns the input value 'c'
45
*/
46
- /*
47
- * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
48
- * to return an input NaN if we have one (ie c) rather than generating
49
- * a default NaN
50
- */
51
rule = float_infzeronan_dnan_never;
52
#endif
53
}
54
--
55
2.34.1
diff view generated by jsdifflib
New patch
[PULL 13/72] target/mips: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the MIPS target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-9-peter.maydell@linaro.org
7
---
8
target/mips/fpu_helper.h | 9 +++++++++
9
target/mips/msa.c | 4 ++++
10
fpu/softfloat-specialize.c.inc | 16 +---------------
11
3 files changed, 14 insertions(+), 15 deletions(-)
12
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/mips/fpu_helper.h
16
+++ b/target/mips/fpu_helper.h
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_flush_mode(CPUMIPSState *env)
18
static inline void restore_snan_bit_mode(CPUMIPSState *env)
19
{
20
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
21
+ FloatInfZeroNaNRule izn_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status);
28
set_default_nan_mode(!nan2008, &env->active_fpu.fp_status);
29
+ /*
30
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
31
+ * case sets InvalidOp and returns the default NaN.
32
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
33
+ * case sets InvalidOp and returns the input value 'c'.
34
+ */
35
+ izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
36
+ set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
37
}
38
39
static inline void restore_fp_status(CPUMIPSState *env)
40
diff --git a/target/mips/msa.c b/target/mips/msa.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/mips/msa.c
43
+++ b/target/mips/msa.c
44
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
45
46
/* set proper signanling bit meaning ("1" means "quiet") */
47
set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
48
+
49
+ /* Inf * 0 + NaN returns the input NaN */
50
+ set_float_infzeronan_rule(float_infzeronan_dnan_never,
51
+ &env->active_tc.msa_fp_status);
52
}
53
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
54
index XXXXXXX..XXXXXXX 100644
55
--- a/fpu/softfloat-specialize.c.inc
56
+++ b/fpu/softfloat-specialize.c.inc
57
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
58
/*
59
* Temporarily fall back to ifdef ladder
60
*/
61
-#if defined(TARGET_MIPS)
62
- if (snan_bit_is_one(status)) {
63
- /*
64
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
65
- * case sets InvalidOp and returns the default NaN
66
- */
67
- rule = float_infzeronan_dnan_always;
68
- } else {
69
- /*
70
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
71
- * case sets InvalidOp and returns the input value 'c'
72
- */
73
- rule = float_infzeronan_dnan_never;
74
- }
75
-#elif defined(TARGET_SPARC) || \
76
+#if defined(TARGET_SPARC) || \
77
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
78
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
79
/*
80
--
81
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/72] target/sparc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the SPARC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-10-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
23
cpu_exec_realizefn(cs, &local_err);
24
if (local_err != NULL) {
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_SPARC) || \
34
- defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
35
+#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
36
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
37
/*
38
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 15/72] target/xtensa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the xtensa target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-11-peter.maydell@linaro.org
7
---
8
target/xtensa/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 +-
10
2 files changed, 3 insertions(+), 1 deletion(-)
11
12
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/xtensa/cpu.c
15
+++ b/target/xtensa/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
17
reset_mmu(env);
18
cs->halted = env->runstall;
19
#endif
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
set_no_signaling_nans(!dfpu, &env->fp_status);
23
xtensa_use_first_nan(env, !dfpu);
24
}
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
34
+#if defined(TARGET_HPPA) || \
35
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
36
/*
37
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 16/72] target/x86: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the x86 target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-12-peter.maydell@linaro.org
6
---
7
target/i386/tcg/fpu_helper.c | 7 +++++++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 8 insertions(+), 1 deletion(-)
10
11
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/i386/tcg/fpu_helper.c
14
+++ b/target/i386/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status);
18
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status);
19
+ /*
20
+ * Only SSE has multiply-add instructions. In the SDM Section 14.5.2
21
+ * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is
22
+ * specified -- for 0 * inf + NaN the input NaN is selected, and if
23
+ * there are multiple input NaNs they are selected in the order a, b, c.
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
26
}
27
28
static inline uint8_t save_exception_flags(CPUX86State *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
34
* Temporarily fall back to ifdef ladder
35
*/
36
#if defined(TARGET_HPPA) || \
37
- defined(TARGET_I386) || defined(TARGET_LOONGARCH)
38
+ defined(TARGET_LOONGARCH)
39
/*
40
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
41
* case sets InvalidOp and returns the input value 'c'
42
--
43
2.34.1
diff view generated by jsdifflib
New patch
[PULL 17/72] target/loongarch: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the loongarch target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-13-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 5 +++++
8
fpu/softfloat-specialize.c.inc | 7 +------
9
2 files changed, 6 insertions(+), 6 deletions(-)
10
11
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/loongarch/tcg/fpu_helper.c
14
+++ b/target/loongarch/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
16
&env->fp_status);
17
set_flush_to_zero(0, &env->fp_status);
18
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
19
+ /*
20
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
21
+ * case sets InvalidOp and returns the input value 'c'
22
+ */
23
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
}
25
26
int ieee_ex_to_loongarch(int xcpt)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
32
/*
33
* Temporarily fall back to ifdef ladder
34
*/
35
-#if defined(TARGET_HPPA) || \
36
- defined(TARGET_LOONGARCH)
37
- /*
38
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
- * case sets InvalidOp and returns the input value 'c'
40
- */
41
+#if defined(TARGET_HPPA)
42
rule = float_infzeronan_dnan_never;
43
#endif
44
}
45
--
46
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 41/46] target/arm/vfp_helper: Extract vfp_set_fpscr_to_host()
[PULL 18/72] target/hppa: Set FloatInfZeroNaNRule explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the FloatInfZeroNaNRule explicitly for the HPPA target,
2
so we can remove the ifdef from pickNaNMulAdd().
2
3
3
The vfp_set_fpscr() helper contains code specific to the host
4
As this is the last target to be converted to explicitly setting
4
floating point implementation (here the SoftFloat library).
5
the rule, we can remove the fallback code in pickNaNMulAdd()
5
Extract this code to vfp_set_fpscr_to_host().
6
entirely.
6
7
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20190701132516.26392-16-philmd@redhat.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20241202131347.498124-14-peter.maydell@linaro.org
11
---
11
---
12
target/arm/vfp_helper.c | 127 +++++++++++++++++++++-------------------
12
target/hppa/fpu_helper.c | 2 ++
13
1 file changed, 66 insertions(+), 61 deletions(-)
13
fpu/softfloat-specialize.c.inc | 13 +------------
14
2 files changed, 3 insertions(+), 12 deletions(-)
14
15
15
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
16
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/vfp_helper.c
18
--- a/target/hppa/fpu_helper.c
18
+++ b/target/arm/vfp_helper.c
19
+++ b/target/hppa/fpu_helper.c
19
@@ -XXX,XX +XXX,XX @@ static inline int vfp_exceptbits_to_host(int target_bits)
20
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
20
return host_bits;
21
* HPPA does note implement a CPU reset method at all...
22
*/
23
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
24
+ /* For inf * 0 + NaN, return the input NaN */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
21
}
26
}
22
27
23
-uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
28
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
24
-{
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
- uint32_t i, fpscr;
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
34
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
bool infzero, float_status *status)
36
{
37
- FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
26
-
38
-
27
- fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
39
/*
28
- | (env->vfp.vec_len << 16)
40
* We guarantee not to require the target to tell us how to
29
- | (env->vfp.vec_stride << 20);
41
* pick a NaN if we're always returning the default NaN.
30
-
42
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
31
- i = get_float_exception_flags(&env->vfp.fp_status);
43
*/
32
- i |= get_float_exception_flags(&env->vfp.standard_fp_status);
44
assert(!status->default_nan_mode);
33
- /* FZ16 does not generate an input denormal exception. */
45
34
- i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
46
- if (rule == float_infzeronan_none) {
35
- & ~float_flag_input_denormal);
47
- /*
36
- fpscr |= vfp_exceptbits_from_host(i);
48
- * Temporarily fall back to ifdef ladder
37
-
49
- */
38
- i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
50
-#if defined(TARGET_HPPA)
39
- fpscr |= i ? FPCR_QC : 0;
51
- rule = float_infzeronan_dnan_never;
40
-
52
-#endif
41
- return fpscr;
42
-}
43
-
44
-uint32_t vfp_get_fpscr(CPUARMState *env)
45
-{
46
- return HELPER(vfp_get_fpscr)(env);
47
-}
48
-
49
-void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
50
+static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
51
{
52
int i;
53
uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];
54
55
- /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
56
- if (!cpu_isar_feature(aa64_fp16, env_archcpu(env))) {
57
- val &= ~FPCR_FZ16;
58
- }
53
- }
59
-
54
-
60
- if (arm_feature(env, ARM_FEATURE_M)) {
55
if (infzero) {
61
- /*
56
/*
62
- * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
57
* Inf * 0 + NaN -- some implementations return the default NaN here,
63
- * and also for the trapped-exception-handling bits IxE.
58
* and some return the input NaN.
64
- */
59
*/
65
- val &= 0xf7c0009f;
60
- switch (rule) {
66
- }
61
+ switch (status->float_infzeronan_rule) {
67
-
62
case float_infzeronan_dnan_never:
68
- /*
63
return 2;
69
- * We don't implement trapped exception handling, so the
64
case float_infzeronan_dnan_always:
70
- * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
71
- *
72
- * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC
73
- * (which are stored in fp_status), and the other RES0 bits
74
- * in between, then we clear all of the low 16 bits.
75
- */
76
- env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
77
- env->vfp.vec_len = (val >> 16) & 7;
78
- env->vfp.vec_stride = (val >> 20) & 3;
79
-
80
- /*
81
- * The bit we set within fpscr_q is arbitrary; the register as a
82
- * whole being zero/non-zero is what counts.
83
- */
84
- env->vfp.qc[0] = val & FPCR_QC;
85
- env->vfp.qc[1] = 0;
86
- env->vfp.qc[2] = 0;
87
- env->vfp.qc[3] = 0;
88
-
89
changed ^= val;
90
if (changed & (3 << 22)) {
91
i = (val >> 22) & 3;
92
@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
93
set_float_exception_flags(0, &env->vfp.standard_fp_status);
94
}
95
96
+uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
97
+{
98
+ uint32_t i, fpscr;
99
+
100
+ fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
101
+ | (env->vfp.vec_len << 16)
102
+ | (env->vfp.vec_stride << 20);
103
+
104
+ i = get_float_exception_flags(&env->vfp.fp_status);
105
+ i |= get_float_exception_flags(&env->vfp.standard_fp_status);
106
+ /* FZ16 does not generate an input denormal exception. */
107
+ i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
108
+ & ~float_flag_input_denormal);
109
+ fpscr |= vfp_exceptbits_from_host(i);
110
+
111
+ i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
112
+ fpscr |= i ? FPCR_QC : 0;
113
+
114
+ return fpscr;
115
+}
116
+
117
+uint32_t vfp_get_fpscr(CPUARMState *env)
118
+{
119
+ return HELPER(vfp_get_fpscr)(env);
120
+}
121
+
122
+void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
123
+{
124
+ /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
125
+ if (!cpu_isar_feature(aa64_fp16, env_archcpu(env))) {
126
+ val &= ~FPCR_FZ16;
127
+ }
128
+
129
+ if (arm_feature(env, ARM_FEATURE_M)) {
130
+ /*
131
+ * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
132
+ * and also for the trapped-exception-handling bits IxE.
133
+ */
134
+ val &= 0xf7c0009f;
135
+ }
136
+
137
+ /*
138
+ * We don't implement trapped exception handling, so the
139
+ * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
140
+ *
141
+ * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC
142
+ * (which are stored in fp_status), and the other RES0 bits
143
+ * in between, then we clear all of the low 16 bits.
144
+ */
145
+ env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
146
+ env->vfp.vec_len = (val >> 16) & 7;
147
+ env->vfp.vec_stride = (val >> 20) & 3;
148
+
149
+ /*
150
+ * The bit we set within fpscr_q is arbitrary; the register as a
151
+ * whole being zero/non-zero is what counts.
152
+ */
153
+ env->vfp.qc[0] = val & FPCR_QC;
154
+ env->vfp.qc[1] = 0;
155
+ env->vfp.qc[2] = 0;
156
+ env->vfp.qc[3] = 0;
157
+
158
+ vfp_set_fpscr_to_host(env, val);
159
+}
160
+
161
void vfp_set_fpscr(CPUARMState *env, uint32_t val)
162
{
163
HELPER(vfp_set_fpscr)(env, val);
164
--
65
--
165
2.20.1
66
2.34.1
166
167
diff view generated by jsdifflib
New patch
[PULL 19/72] softfloat: Pass have_snan to pickNaNMulAdd
1
The new implementation of pickNaNMulAdd() will find it convenient
2
to know whether at least one of the three arguments to the muladd
3
was a signaling NaN. We already calculate that in the caller,
4
so pass it in as a new bool have_snan.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-15-peter.maydell@linaro.org
9
---
10
fpu/softfloat-parts.c.inc | 5 +++--
11
fpu/softfloat-specialize.c.inc | 2 +-
12
2 files changed, 4 insertions(+), 3 deletions(-)
13
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
16
--- a/fpu/softfloat-parts.c.inc
17
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
{
20
int which;
21
bool infzero = (ab_mask == float_cmask_infzero);
22
+ bool have_snan = (abc_mask & float_cmask_snan);
23
24
- if (unlikely(abc_mask & float_cmask_snan)) {
25
+ if (unlikely(have_snan)) {
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
27
}
28
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
30
if (s->default_nan_mode) {
31
which = 3;
32
} else {
33
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
35
}
36
37
if (which == 3) {
38
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
39
index XXXXXXX..XXXXXXX 100644
40
--- a/fpu/softfloat-specialize.c.inc
41
+++ b/fpu/softfloat-specialize.c.inc
42
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
43
| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
44
*----------------------------------------------------------------------------*/
45
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
46
- bool infzero, float_status *status)
47
+ bool infzero, bool have_snan, float_status *status)
48
{
49
/*
50
* We guarantee not to require the target to tell us how to
51
--
52
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/46] aspeed/timer: Fix match calculations
[PULL 20/72] softfloat: Allow runtime choice of NaN propagation for muladd
1
From: Andrew Jeffery <andrew@aj.id.au>
1
IEEE 758 does not define a fixed rule for which NaN to pick as the
2
2
result if both operands of a 3-operand fused multiply-add operation
3
If the match value exceeds reload then we don't want to include it in
3
are NaNs. As a result different architectures have ended up with
4
calculations for the next event.
4
different rules for propagating NaNs.
5
5
6
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
6
QEMU currently hardcodes the NaN propagation logic into the binary
7
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7
because pickNaNMulAdd() has an ifdef ladder for different targets.
8
Message-id: 20190618165311.27066-10-clg@kaod.org
8
We want to make the propagation rule instead be selectable at
9
runtime, because:
10
* this will let us have multiple targets in one QEMU binary
11
* the Arm FEAT_AFP architectural feature includes letting
12
the guest select a NaN propagation rule at runtime
13
14
In this commit we add an enum for the propagation rule, the field in
15
float_status, and the corresponding getters and setters. We change
16
pickNaNMulAdd to honour this, but because all targets still leave
17
this field at its default 0 value, the fallback logic will pick the
18
rule type with the old ifdef ladder.
19
20
It's valid not to set a propagation rule if default_nan_mode is
21
enabled, because in that case there's no need to pick a NaN; all the
22
callers of pickNaNMulAdd() catch this case and skip calling it.
23
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20241202131347.498124-16-peter.maydell@linaro.org
10
---
27
---
11
hw/timer/aspeed_timer.c | 13 ++++++++++---
28
include/fpu/softfloat-helpers.h | 11 +++
12
1 file changed, 10 insertions(+), 3 deletions(-)
29
include/fpu/softfloat-types.h | 55 +++++++++++
13
30
fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------
14
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
31
3 files changed, 107 insertions(+), 126 deletions(-)
32
33
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
15
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/timer/aspeed_timer.c
35
--- a/include/fpu/softfloat-helpers.h
17
+++ b/hw/timer/aspeed_timer.c
36
+++ b/include/fpu/softfloat-helpers.h
18
@@ -XXX,XX +XXX,XX @@ static inline uint64_t calculate_time(struct AspeedTimer *t, uint32_t ticks)
37
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
19
return t->start + delta_ns;
38
status->float_2nan_prop_rule = rule;
20
}
39
}
21
40
22
+static inline uint32_t calculate_match(struct AspeedTimer *t, int i)
41
+static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule,
42
+ float_status *status)
23
+{
43
+{
24
+ return t->match[i] < t->reload ? t->match[i] : 0;
44
+ status->float_3nan_prop_rule = rule;
25
+}
45
+}
26
+
46
+
27
static uint64_t calculate_next(struct AspeedTimer *t)
47
static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
48
float_status *status)
28
{
49
{
29
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
50
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
30
@@ -XXX,XX +XXX,XX @@ static uint64_t calculate_next(struct AspeedTimer *t)
51
return status->float_2nan_prop_rule;
31
* the timer counts down to zero.
52
}
32
*/
53
33
54
+static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status)
34
- next = calculate_time(t, MAX(t->match[0], t->match[1]));
55
+{
35
+ next = calculate_time(t, MAX(calculate_match(t, 0), calculate_match(t, 1)));
56
+ return status->float_3nan_prop_rule;
36
if (now < next) {
57
+}
37
return next;
58
+
59
static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
60
{
61
return status->float_infzeronan_rule;
62
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/include/fpu/softfloat-types.h
65
+++ b/include/fpu/softfloat-types.h
66
@@ -XXX,XX +XXX,XX @@ this code that are retained.
67
#ifndef SOFTFLOAT_TYPES_H
68
#define SOFTFLOAT_TYPES_H
69
70
+#include "hw/registerfields.h"
71
+
72
/*
73
* Software IEC/IEEE floating-point types.
74
*/
75
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
76
float_2nan_prop_x87,
77
} Float2NaNPropRule;
78
79
+/*
80
+ * 3-input NaN propagation rule, for fused multiply-add. Individual
81
+ * architectures have different rules for which input NaN is
82
+ * propagated to the output when there is more than one NaN on the
83
+ * input.
84
+ *
85
+ * If default_nan_mode is enabled then it is valid not to set a NaN
86
+ * propagation rule, because the softfloat code guarantees not to try
87
+ * to pick a NaN to propagate in default NaN mode. When not in
88
+ * default-NaN mode, it is an error for the target not to set the rule
89
+ * in float_status if it uses a muladd, and we will assert if we need
90
+ * to handle an input NaN and no rule was selected.
91
+ *
92
+ * The naming scheme for Float3NaNPropRule values is:
93
+ * float_3nan_prop_s_abc:
94
+ * = "Prefer SNaN over QNaN, then operand A over B over C"
95
+ * float_3nan_prop_abc:
96
+ * = "Prefer A over B over C regardless of SNaN vs QNAN"
97
+ *
98
+ * For QEMU, the multiply-add operation is A * B + C.
99
+ */
100
+
101
+/*
102
+ * We set the Float3NaNPropRule enum values up so we can select the
103
+ * right value in pickNaNMulAdd in a data driven way.
104
+ */
105
+FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */
106
+FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */
107
+FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */
108
+FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */
109
+
110
+#define PROPRULE(X, Y, Z) \
111
+ ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT))
112
+
113
+typedef enum __attribute__((__packed__)) {
114
+ float_3nan_prop_none = 0, /* No propagation rule specified */
115
+ float_3nan_prop_abc = PROPRULE(0, 1, 2),
116
+ float_3nan_prop_acb = PROPRULE(0, 2, 1),
117
+ float_3nan_prop_bac = PROPRULE(1, 0, 2),
118
+ float_3nan_prop_bca = PROPRULE(1, 2, 0),
119
+ float_3nan_prop_cab = PROPRULE(2, 0, 1),
120
+ float_3nan_prop_cba = PROPRULE(2, 1, 0),
121
+ float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK,
122
+ float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK,
123
+ float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK,
124
+ float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK,
125
+ float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK,
126
+ float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK,
127
+} Float3NaNPropRule;
128
+
129
+#undef PROPRULE
130
+
131
/*
132
* Rule for result of fused multiply-add 0 * Inf + NaN.
133
* This must be a NaN, but implementations differ on whether this
134
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
135
FloatRoundMode float_rounding_mode;
136
FloatX80RoundPrec floatx80_rounding_precision;
137
Float2NaNPropRule float_2nan_prop_rule;
138
+ Float3NaNPropRule float_3nan_prop_rule;
139
FloatInfZeroNaNRule float_infzeronan_rule;
140
bool tininess_before_rounding;
141
/* should denormalised results go to zero and set the inexact flag? */
142
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
143
index XXXXXXX..XXXXXXX 100644
144
--- a/fpu/softfloat-specialize.c.inc
145
+++ b/fpu/softfloat-specialize.c.inc
146
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
147
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
148
bool infzero, bool have_snan, float_status *status)
149
{
150
+ FloatClass cls[3] = { a_cls, b_cls, c_cls };
151
+ Float3NaNPropRule rule = status->float_3nan_prop_rule;
152
+ int which;
153
+
154
/*
155
* We guarantee not to require the target to tell us how to
156
* pick a NaN if we're always returning the default NaN.
157
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
158
}
38
}
159
}
39
160
40
- next = calculate_time(t, MIN(t->match[0], t->match[1]));
161
+ if (rule == float_3nan_prop_none) {
41
+ next = calculate_time(t, MIN(calculate_match(t, 0), calculate_match(t, 1)));
162
#if defined(TARGET_ARM)
42
if (now < next) {
163
-
43
return next;
164
- /* This looks different from the ARM ARM pseudocode, because the ARM ARM
44
}
165
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
45
@@ -XXX,XX +XXX,XX @@ static uint64_t calculate_next(struct AspeedTimer *t)
166
- */
46
qemu_set_irq(t->irq, t->level);
167
- if (is_snan(c_cls)) {
47
}
168
- return 2;
48
169
- } else if (is_snan(a_cls)) {
49
+ next = MAX(MAX(calculate_match(t, 0), calculate_match(t, 1)), 0);
170
- return 0;
50
t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
171
- } else if (is_snan(b_cls)) {
51
- return calculate_time(t, MAX(MAX(t->match[0], t->match[1]), 0));
172
- return 1;
52
+
173
- } else if (is_qnan(c_cls)) {
53
+ return calculate_time(t, next);
174
- return 2;
175
- } else if (is_qnan(a_cls)) {
176
- return 0;
177
- } else {
178
- return 1;
179
- }
180
+ /*
181
+ * This looks different from the ARM ARM pseudocode, because the ARM ARM
182
+ * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
183
+ */
184
+ rule = float_3nan_prop_s_cab;
185
#elif defined(TARGET_MIPS)
186
- if (snan_bit_is_one(status)) {
187
- /* Prefer sNaN over qNaN, in the a, b, c order. */
188
- if (is_snan(a_cls)) {
189
- return 0;
190
- } else if (is_snan(b_cls)) {
191
- return 1;
192
- } else if (is_snan(c_cls)) {
193
- return 2;
194
- } else if (is_qnan(a_cls)) {
195
- return 0;
196
- } else if (is_qnan(b_cls)) {
197
- return 1;
198
+ if (snan_bit_is_one(status)) {
199
+ rule = float_3nan_prop_s_abc;
200
} else {
201
- return 2;
202
+ rule = float_3nan_prop_s_cab;
203
}
204
- } else {
205
- /* Prefer sNaN over qNaN, in the c, a, b order. */
206
- if (is_snan(c_cls)) {
207
- return 2;
208
- } else if (is_snan(a_cls)) {
209
- return 0;
210
- } else if (is_snan(b_cls)) {
211
- return 1;
212
- } else if (is_qnan(c_cls)) {
213
- return 2;
214
- } else if (is_qnan(a_cls)) {
215
- return 0;
216
- } else {
217
- return 1;
218
- }
219
- }
220
#elif defined(TARGET_LOONGARCH64)
221
- /* Prefer sNaN over qNaN, in the c, a, b order. */
222
- if (is_snan(c_cls)) {
223
- return 2;
224
- } else if (is_snan(a_cls)) {
225
- return 0;
226
- } else if (is_snan(b_cls)) {
227
- return 1;
228
- } else if (is_qnan(c_cls)) {
229
- return 2;
230
- } else if (is_qnan(a_cls)) {
231
- return 0;
232
- } else {
233
- return 1;
234
- }
235
+ rule = float_3nan_prop_s_cab;
236
#elif defined(TARGET_PPC)
237
- /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
238
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
239
- */
240
- if (is_nan(a_cls)) {
241
- return 0;
242
- } else if (is_nan(c_cls)) {
243
- return 2;
244
- } else {
245
- return 1;
246
- }
247
+ /*
248
+ * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
249
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
250
+ */
251
+ rule = float_3nan_prop_acb;
252
#elif defined(TARGET_S390X)
253
- if (is_snan(a_cls)) {
254
- return 0;
255
- } else if (is_snan(b_cls)) {
256
- return 1;
257
- } else if (is_snan(c_cls)) {
258
- return 2;
259
- } else if (is_qnan(a_cls)) {
260
- return 0;
261
- } else if (is_qnan(b_cls)) {
262
- return 1;
263
- } else {
264
- return 2;
265
- }
266
+ rule = float_3nan_prop_s_abc;
267
#elif defined(TARGET_SPARC)
268
- /* Prefer SNaN over QNaN, order C, B, A. */
269
- if (is_snan(c_cls)) {
270
- return 2;
271
- } else if (is_snan(b_cls)) {
272
- return 1;
273
- } else if (is_snan(a_cls)) {
274
- return 0;
275
- } else if (is_qnan(c_cls)) {
276
- return 2;
277
- } else if (is_qnan(b_cls)) {
278
- return 1;
279
- } else {
280
- return 0;
281
- }
282
+ rule = float_3nan_prop_s_cba;
283
#elif defined(TARGET_XTENSA)
284
- /*
285
- * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
286
- * an input NaN if we have one (ie c).
287
- */
288
- if (status->use_first_nan) {
289
- if (is_nan(a_cls)) {
290
- return 0;
291
- } else if (is_nan(b_cls)) {
292
- return 1;
293
+ if (status->use_first_nan) {
294
+ rule = float_3nan_prop_abc;
295
} else {
296
- return 2;
297
+ rule = float_3nan_prop_cba;
298
}
299
- } else {
300
- if (is_nan(c_cls)) {
301
- return 2;
302
- } else if (is_nan(b_cls)) {
303
- return 1;
304
- } else {
305
- return 0;
306
- }
307
- }
308
#else
309
- /* A default implementation: prefer a to b to c.
310
- * This is unlikely to actually match any real implementation.
311
- */
312
- if (is_nan(a_cls)) {
313
- return 0;
314
- } else if (is_nan(b_cls)) {
315
- return 1;
316
- } else {
317
- return 2;
318
- }
319
+ rule = float_3nan_prop_abc;
320
#endif
321
+ }
322
+
323
+ assert(rule != float_3nan_prop_none);
324
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
325
+ /* We have at least one SNaN input and should prefer it */
326
+ do {
327
+ which = rule & R_3NAN_1ST_MASK;
328
+ rule >>= R_3NAN_1ST_LENGTH;
329
+ } while (!is_snan(cls[which]));
330
+ } else {
331
+ do {
332
+ which = rule & R_3NAN_1ST_MASK;
333
+ rule >>= R_3NAN_1ST_LENGTH;
334
+ } while (!is_nan(cls[which]));
335
+ }
336
+ return which;
54
}
337
}
55
338
56
static void aspeed_timer_mod(AspeedTimer *t)
339
/*----------------------------------------------------------------------------
57
--
340
--
58
2.20.1
341
2.34.1
59
60
diff view generated by jsdifflib
New patch
[PULL 21/72] tests/fp: Explicitly set 3-NaN propagation rule
1
Explicitly set a rule in the softfloat tests for propagating NaNs in
2
the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and
3
so we should select here the Arm rule of float_3nan_prop_s_cab.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-17-peter.maydell@linaro.org
8
---
9
tests/fp/fp-bench.c | 1 +
10
tests/fp/fp-test.c | 1 +
11
2 files changed, 2 insertions(+)
12
13
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/tests/fp/fp-bench.c
16
+++ b/tests/fp/fp-bench.c
17
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
18
* doesn't specify match those used by the Arm architecture.
19
*/
20
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
22
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
23
24
f = bench_funcs[operation][precision];
25
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/tests/fp/fp-test.c
28
+++ b/tests/fp/fp-test.c
29
@@ -XXX,XX +XXX,XX @@ void run_test(void)
30
* doesn't specify match those used by the Arm architecture.
31
*/
32
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
33
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
34
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
35
36
genCases_setLevel(test_level);
37
--
38
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 37/46] target/arm: Move CPU state dumping routines to cpu.c
[PULL 22/72] target/arm: Set Float3NaNPropRule explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Suggested-by: Samuel Ortiz <sameo@linux.intel.com>
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Message-id: 20190701132516.26392-11-philmd@redhat.com
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-18-peter.maydell@linaro.org
8
---
7
---
9
target/arm/cpu.h | 2 -
8
target/arm/cpu.c | 5 +++++
10
target/arm/translate.h | 5 -
9
fpu/softfloat-specialize.c.inc | 8 +-------
11
target/arm/cpu.c | 226 +++++++++++++++++++++++++++++++++++++
10
2 files changed, 6 insertions(+), 7 deletions(-)
12
target/arm/translate-a64.c | 128 ---------------------
13
target/arm/translate.c | 88 ---------------
14
5 files changed, 226 insertions(+), 223 deletions(-)
15
11
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cpu);
21
void arm_v7m_cpu_do_interrupt(CPUState *cpu);
22
bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
23
24
-void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags);
25
-
26
hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
27
MemTxAttrs *attrs);
28
29
diff --git a/target/arm/translate.h b/target/arm/translate.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/translate.h
32
+++ b/target/arm/translate.h
33
@@ -XXX,XX +XXX,XX @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
34
#ifdef TARGET_AARCH64
35
void a64_translate_init(void);
36
void gen_a64_set_pc_im(uint64_t val);
37
-void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags);
38
extern const TranslatorOps aarch64_translator_ops;
39
#else
40
static inline void a64_translate_init(void)
41
@@ -XXX,XX +XXX,XX @@ static inline void a64_translate_init(void)
42
static inline void gen_a64_set_pc_im(uint64_t val)
43
{
44
}
45
-
46
-static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
47
-{
48
-}
49
#endif
50
51
void arm_test_cc(DisasCompare *cmp, int cc);
52
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
53
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/cpu.c
14
--- a/target/arm/cpu.c
55
+++ b/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
56
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
17
* * tininess-before-rounding
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
20
+ * * 3-input NaN propagation prefers SNaN over QNaN, and then
21
+ * operand C over A over B (see FPProcessNaNs3() pseudocode,
22
+ * but note that for QEMU muladd is a * b + c, whereas for
23
+ * the pseudocode function the arguments are in the order c, a, b.
24
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
25
* and the input NaN if it is signalling
57
*/
26
*/
58
27
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
59
#include "qemu/osdep.h"
28
{
60
+#include "qemu/qemu-print.h"
29
set_float_detect_tininess(float_tininess_before_rounding, s);
61
#include "qemu-common.h"
30
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
62
#include "target/arm/idau.h"
31
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
63
#include "qemu/module.h"
32
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
64
@@ -XXX,XX +XXX,XX @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
65
#endif
66
}
33
}
67
34
68
+#ifdef TARGET_AARCH64
35
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
69
+
70
+static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
71
+{
72
+ ARMCPU *cpu = ARM_CPU(cs);
73
+ CPUARMState *env = &cpu->env;
74
+ uint32_t psr = pstate_read(env);
75
+ int i;
76
+ int el = arm_current_el(env);
77
+ const char *ns_status;
78
+
79
+ qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
80
+ for (i = 0; i < 32; i++) {
81
+ if (i == 31) {
82
+ qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
83
+ } else {
84
+ qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
85
+ (i + 2) % 3 ? " " : "\n");
86
+ }
87
+ }
88
+
89
+ if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
90
+ ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
91
+ } else {
92
+ ns_status = "";
93
+ }
94
+ qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
95
+ psr,
96
+ psr & PSTATE_N ? 'N' : '-',
97
+ psr & PSTATE_Z ? 'Z' : '-',
98
+ psr & PSTATE_C ? 'C' : '-',
99
+ psr & PSTATE_V ? 'V' : '-',
100
+ ns_status,
101
+ el,
102
+ psr & PSTATE_SP ? 'h' : 't');
103
+
104
+ if (cpu_isar_feature(aa64_bti, cpu)) {
105
+ qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
106
+ }
107
+ if (!(flags & CPU_DUMP_FPU)) {
108
+ qemu_fprintf(f, "\n");
109
+ return;
110
+ }
111
+ if (fp_exception_el(env, el) != 0) {
112
+ qemu_fprintf(f, " FPU disabled\n");
113
+ return;
114
+ }
115
+ qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
116
+ vfp_get_fpcr(env), vfp_get_fpsr(env));
117
+
118
+ if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
119
+ int j, zcr_len = sve_zcr_len_for_el(env, el);
120
+
121
+ for (i = 0; i <= FFR_PRED_NUM; i++) {
122
+ bool eol;
123
+ if (i == FFR_PRED_NUM) {
124
+ qemu_fprintf(f, "FFR=");
125
+ /* It's last, so end the line. */
126
+ eol = true;
127
+ } else {
128
+ qemu_fprintf(f, "P%02d=", i);
129
+ switch (zcr_len) {
130
+ case 0:
131
+ eol = i % 8 == 7;
132
+ break;
133
+ case 1:
134
+ eol = i % 6 == 5;
135
+ break;
136
+ case 2:
137
+ case 3:
138
+ eol = i % 3 == 2;
139
+ break;
140
+ default:
141
+ /* More than one quadword per predicate. */
142
+ eol = true;
143
+ break;
144
+ }
145
+ }
146
+ for (j = zcr_len / 4; j >= 0; j--) {
147
+ int digits;
148
+ if (j * 4 + 4 <= zcr_len + 1) {
149
+ digits = 16;
150
+ } else {
151
+ digits = (zcr_len % 4 + 1) * 4;
152
+ }
153
+ qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
154
+ env->vfp.pregs[i].p[j],
155
+ j ? ":" : eol ? "\n" : " ");
156
+ }
157
+ }
158
+
159
+ for (i = 0; i < 32; i++) {
160
+ if (zcr_len == 0) {
161
+ qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
162
+ i, env->vfp.zregs[i].d[1],
163
+ env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
164
+ } else if (zcr_len == 1) {
165
+ qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
166
+ ":%016" PRIx64 ":%016" PRIx64 "\n",
167
+ i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
168
+ env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
169
+ } else {
170
+ for (j = zcr_len; j >= 0; j--) {
171
+ bool odd = (zcr_len - j) % 2 != 0;
172
+ if (j == zcr_len) {
173
+ qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
174
+ } else if (!odd) {
175
+ if (j > 0) {
176
+ qemu_fprintf(f, " [%x-%x]=", j, j - 1);
177
+ } else {
178
+ qemu_fprintf(f, " [%x]=", j);
179
+ }
180
+ }
181
+ qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
182
+ env->vfp.zregs[i].d[j * 2 + 1],
183
+ env->vfp.zregs[i].d[j * 2],
184
+ odd || j == 0 ? "\n" : ":");
185
+ }
186
+ }
187
+ }
188
+ } else {
189
+ for (i = 0; i < 32; i++) {
190
+ uint64_t *q = aa64_vfp_qreg(env, i);
191
+ qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
192
+ i, q[1], q[0], (i & 1 ? "\n" : " "));
193
+ }
194
+ }
195
+}
196
+
197
+#else
198
+
199
+static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
200
+{
201
+ g_assert_not_reached();
202
+}
203
+
204
+#endif
205
+
206
+static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
207
+{
208
+ ARMCPU *cpu = ARM_CPU(cs);
209
+ CPUARMState *env = &cpu->env;
210
+ int i;
211
+
212
+ if (is_a64(env)) {
213
+ aarch64_cpu_dump_state(cs, f, flags);
214
+ return;
215
+ }
216
+
217
+ for (i = 0; i < 16; i++) {
218
+ qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
219
+ if ((i % 4) == 3) {
220
+ qemu_fprintf(f, "\n");
221
+ } else {
222
+ qemu_fprintf(f, " ");
223
+ }
224
+ }
225
+
226
+ if (arm_feature(env, ARM_FEATURE_M)) {
227
+ uint32_t xpsr = xpsr_read(env);
228
+ const char *mode;
229
+ const char *ns_status = "";
230
+
231
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
232
+ ns_status = env->v7m.secure ? "S " : "NS ";
233
+ }
234
+
235
+ if (xpsr & XPSR_EXCP) {
236
+ mode = "handler";
237
+ } else {
238
+ if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
239
+ mode = "unpriv-thread";
240
+ } else {
241
+ mode = "priv-thread";
242
+ }
243
+ }
244
+
245
+ qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
246
+ xpsr,
247
+ xpsr & XPSR_N ? 'N' : '-',
248
+ xpsr & XPSR_Z ? 'Z' : '-',
249
+ xpsr & XPSR_C ? 'C' : '-',
250
+ xpsr & XPSR_V ? 'V' : '-',
251
+ xpsr & XPSR_T ? 'T' : 'A',
252
+ ns_status,
253
+ mode);
254
+ } else {
255
+ uint32_t psr = cpsr_read(env);
256
+ const char *ns_status = "";
257
+
258
+ if (arm_feature(env, ARM_FEATURE_EL3) &&
259
+ (psr & CPSR_M) != ARM_CPU_MODE_MON) {
260
+ ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
261
+ }
262
+
263
+ qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
264
+ psr,
265
+ psr & CPSR_N ? 'N' : '-',
266
+ psr & CPSR_Z ? 'Z' : '-',
267
+ psr & CPSR_C ? 'C' : '-',
268
+ psr & CPSR_V ? 'V' : '-',
269
+ psr & CPSR_T ? 'T' : 'A',
270
+ ns_status,
271
+ aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
272
+ }
273
+
274
+ if (flags & CPU_DUMP_FPU) {
275
+ int numvfpregs = 0;
276
+ if (arm_feature(env, ARM_FEATURE_VFP)) {
277
+ numvfpregs += 16;
278
+ }
279
+ if (arm_feature(env, ARM_FEATURE_VFP3)) {
280
+ numvfpregs += 16;
281
+ }
282
+ for (i = 0; i < numvfpregs; i++) {
283
+ uint64_t v = *aa32_vfp_dreg(env, i);
284
+ qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
285
+ i * 2, (uint32_t)v,
286
+ i * 2 + 1, (uint32_t)(v >> 32),
287
+ i, v);
288
+ }
289
+ qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
290
+ }
291
+}
292
+
293
uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
294
{
295
uint32_t Aff1 = idx / clustersz;
296
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
297
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
298
--- a/target/arm/translate-a64.c
37
--- a/fpu/softfloat-specialize.c.inc
299
+++ b/target/arm/translate-a64.c
38
+++ b/fpu/softfloat-specialize.c.inc
300
@@ -XXX,XX +XXX,XX @@
39
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
301
#include "translate.h"
40
}
302
#include "internals.h"
41
303
#include "qemu/host-utils.h"
42
if (rule == float_3nan_prop_none) {
304
-#include "qemu/qemu-print.h"
43
-#if defined(TARGET_ARM)
305
44
- /*
306
#include "hw/semihosting/semihost.h"
45
- * This looks different from the ARM ARM pseudocode, because the ARM ARM
307
#include "exec/gen-icount.h"
46
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
308
@@ -XXX,XX +XXX,XX @@ static void set_btype(DisasContext *s, int val)
47
- */
309
s->btype = -1;
48
- rule = float_3nan_prop_s_cab;
310
}
49
-#elif defined(TARGET_MIPS)
311
50
+#if defined(TARGET_MIPS)
312
-void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
51
if (snan_bit_is_one(status)) {
313
-{
52
rule = float_3nan_prop_s_abc;
314
- ARMCPU *cpu = ARM_CPU(cs);
53
} else {
315
- CPUARMState *env = &cpu->env;
316
- uint32_t psr = pstate_read(env);
317
- int i;
318
- int el = arm_current_el(env);
319
- const char *ns_status;
320
-
321
- qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
322
- for (i = 0; i < 32; i++) {
323
- if (i == 31) {
324
- qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
325
- } else {
326
- qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
327
- (i + 2) % 3 ? " " : "\n");
328
- }
329
- }
330
-
331
- if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
332
- ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
333
- } else {
334
- ns_status = "";
335
- }
336
- qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
337
- psr,
338
- psr & PSTATE_N ? 'N' : '-',
339
- psr & PSTATE_Z ? 'Z' : '-',
340
- psr & PSTATE_C ? 'C' : '-',
341
- psr & PSTATE_V ? 'V' : '-',
342
- ns_status,
343
- el,
344
- psr & PSTATE_SP ? 'h' : 't');
345
-
346
- if (cpu_isar_feature(aa64_bti, cpu)) {
347
- qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
348
- }
349
- if (!(flags & CPU_DUMP_FPU)) {
350
- qemu_fprintf(f, "\n");
351
- return;
352
- }
353
- if (fp_exception_el(env, el) != 0) {
354
- qemu_fprintf(f, " FPU disabled\n");
355
- return;
356
- }
357
- qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
358
- vfp_get_fpcr(env), vfp_get_fpsr(env));
359
-
360
- if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
361
- int j, zcr_len = sve_zcr_len_for_el(env, el);
362
-
363
- for (i = 0; i <= FFR_PRED_NUM; i++) {
364
- bool eol;
365
- if (i == FFR_PRED_NUM) {
366
- qemu_fprintf(f, "FFR=");
367
- /* It's last, so end the line. */
368
- eol = true;
369
- } else {
370
- qemu_fprintf(f, "P%02d=", i);
371
- switch (zcr_len) {
372
- case 0:
373
- eol = i % 8 == 7;
374
- break;
375
- case 1:
376
- eol = i % 6 == 5;
377
- break;
378
- case 2:
379
- case 3:
380
- eol = i % 3 == 2;
381
- break;
382
- default:
383
- /* More than one quadword per predicate. */
384
- eol = true;
385
- break;
386
- }
387
- }
388
- for (j = zcr_len / 4; j >= 0; j--) {
389
- int digits;
390
- if (j * 4 + 4 <= zcr_len + 1) {
391
- digits = 16;
392
- } else {
393
- digits = (zcr_len % 4 + 1) * 4;
394
- }
395
- qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
396
- env->vfp.pregs[i].p[j],
397
- j ? ":" : eol ? "\n" : " ");
398
- }
399
- }
400
-
401
- for (i = 0; i < 32; i++) {
402
- if (zcr_len == 0) {
403
- qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
404
- i, env->vfp.zregs[i].d[1],
405
- env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
406
- } else if (zcr_len == 1) {
407
- qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
408
- ":%016" PRIx64 ":%016" PRIx64 "\n",
409
- i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
410
- env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
411
- } else {
412
- for (j = zcr_len; j >= 0; j--) {
413
- bool odd = (zcr_len - j) % 2 != 0;
414
- if (j == zcr_len) {
415
- qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
416
- } else if (!odd) {
417
- if (j > 0) {
418
- qemu_fprintf(f, " [%x-%x]=", j, j - 1);
419
- } else {
420
- qemu_fprintf(f, " [%x]=", j);
421
- }
422
- }
423
- qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
424
- env->vfp.zregs[i].d[j * 2 + 1],
425
- env->vfp.zregs[i].d[j * 2],
426
- odd || j == 0 ? "\n" : ":");
427
- }
428
- }
429
- }
430
- } else {
431
- for (i = 0; i < 32; i++) {
432
- uint64_t *q = aa64_vfp_qreg(env, i);
433
- qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
434
- i, q[1], q[0], (i & 1 ? "\n" : " "));
435
- }
436
- }
437
-}
438
-
439
void gen_a64_set_pc_im(uint64_t val)
440
{
441
tcg_gen_movi_i64(cpu_pc, val);
442
diff --git a/target/arm/translate.c b/target/arm/translate.c
443
index XXXXXXX..XXXXXXX 100644
444
--- a/target/arm/translate.c
445
+++ b/target/arm/translate.c
446
@@ -XXX,XX +XXX,XX @@
447
#include "tcg-op-gvec.h"
448
#include "qemu/log.h"
449
#include "qemu/bitops.h"
450
-#include "qemu/qemu-print.h"
451
#include "arm_ldst.h"
452
#include "hw/semihosting/semihost.h"
453
454
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
455
translator_loop(ops, &dc.base, cpu, tb, max_insns);
456
}
457
458
-void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
459
-{
460
- ARMCPU *cpu = ARM_CPU(cs);
461
- CPUARMState *env = &cpu->env;
462
- int i;
463
-
464
- if (is_a64(env)) {
465
- aarch64_cpu_dump_state(cs, f, flags);
466
- return;
467
- }
468
-
469
- for (i = 0; i < 16; i++) {
470
- qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
471
- if ((i % 4) == 3) {
472
- qemu_fprintf(f, "\n");
473
- } else {
474
- qemu_fprintf(f, " ");
475
- }
476
- }
477
-
478
- if (arm_feature(env, ARM_FEATURE_M)) {
479
- uint32_t xpsr = xpsr_read(env);
480
- const char *mode;
481
- const char *ns_status = "";
482
-
483
- if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
484
- ns_status = env->v7m.secure ? "S " : "NS ";
485
- }
486
-
487
- if (xpsr & XPSR_EXCP) {
488
- mode = "handler";
489
- } else {
490
- if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
491
- mode = "unpriv-thread";
492
- } else {
493
- mode = "priv-thread";
494
- }
495
- }
496
-
497
- qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
498
- xpsr,
499
- xpsr & XPSR_N ? 'N' : '-',
500
- xpsr & XPSR_Z ? 'Z' : '-',
501
- xpsr & XPSR_C ? 'C' : '-',
502
- xpsr & XPSR_V ? 'V' : '-',
503
- xpsr & XPSR_T ? 'T' : 'A',
504
- ns_status,
505
- mode);
506
- } else {
507
- uint32_t psr = cpsr_read(env);
508
- const char *ns_status = "";
509
-
510
- if (arm_feature(env, ARM_FEATURE_EL3) &&
511
- (psr & CPSR_M) != ARM_CPU_MODE_MON) {
512
- ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
513
- }
514
-
515
- qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
516
- psr,
517
- psr & CPSR_N ? 'N' : '-',
518
- psr & CPSR_Z ? 'Z' : '-',
519
- psr & CPSR_C ? 'C' : '-',
520
- psr & CPSR_V ? 'V' : '-',
521
- psr & CPSR_T ? 'T' : 'A',
522
- ns_status,
523
- aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
524
- }
525
-
526
- if (flags & CPU_DUMP_FPU) {
527
- int numvfpregs = 0;
528
- if (arm_feature(env, ARM_FEATURE_VFP)) {
529
- numvfpregs += 16;
530
- }
531
- if (arm_feature(env, ARM_FEATURE_VFP3)) {
532
- numvfpregs += 16;
533
- }
534
- for (i = 0; i < numvfpregs; i++) {
535
- uint64_t v = *aa32_vfp_dreg(env, i);
536
- qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
537
- i * 2, (uint32_t)v,
538
- i * 2 + 1, (uint32_t)(v >> 32),
539
- i, v);
540
- }
541
- qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
542
- }
543
-}
544
-
545
void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb,
546
target_ulong *data)
547
{
548
--
54
--
549
2.20.1
55
2.34.1
550
551
diff view generated by jsdifflib
New patch
[PULL 23/72] target/loongarch: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for loongarch, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-19-peter.maydell@linaro.org
7
---
8
target/loongarch/tcg/fpu_helper.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/loongarch/tcg/fpu_helper.c
15
+++ b/target/loongarch/tcg/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
17
* case sets InvalidOp and returns the input value 'c'
18
*/
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
21
}
22
23
int ieee_ex_to_loongarch(int xcpt)
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_LOONGARCH64)
33
- rule = float_3nan_prop_s_cab;
34
#elif defined(TARGET_PPC)
35
/*
36
* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 24/72] target/ppc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for PPC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-20-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 8 ++++++++
9
fpu/softfloat-specialize.c.inc | 6 ------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * NaN propagation for fused multiply-add:
22
+ * if fRA is a NaN return it; otherwise if fRB is a NaN return it;
23
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
24
+ * whereas QEMU labels the operands as (a * b) + c.
25
+ */
26
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status);
27
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status);
28
/*
29
* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
30
* to return an input NaN if we have one (ie c) rather than generating
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
32
index XXXXXXX..XXXXXXX 100644
33
--- a/fpu/softfloat-specialize.c.inc
34
+++ b/fpu/softfloat-specialize.c.inc
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
36
} else {
37
rule = float_3nan_prop_s_cab;
38
}
39
-#elif defined(TARGET_PPC)
40
- /*
41
- * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
42
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
43
- */
44
- rule = float_3nan_prop_acb;
45
#elif defined(TARGET_S390X)
46
rule = float_3nan_prop_s_abc;
47
#elif defined(TARGET_SPARC)
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 25/72] target/s390x: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for s390x, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-21-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
21
set_float_infzeronan_rule(float_infzeronan_dnan_always,
22
&env->fpu_status);
23
/* fall through */
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_S390X)
33
- rule = float_3nan_prop_s_abc;
34
#elif defined(TARGET_SPARC)
35
rule = float_3nan_prop_s_cba;
36
#elif defined(TARGET_XTENSA)
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 26/72] target/sparc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for SPARC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-22-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
22
/* For inf * 0 + NaN, return the input NaN */
23
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
} else {
31
rule = float_3nan_prop_s_cab;
32
}
33
-#elif defined(TARGET_SPARC)
34
- rule = float_3nan_prop_s_cba;
35
#elif defined(TARGET_XTENSA)
36
if (status->use_first_nan) {
37
rule = float_3nan_prop_abc;
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 27/72] target/mips: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-23-peter.maydell@linaro.org
7
---
8
target/mips/fpu_helper.h | 4 ++++
9
target/mips/msa.c | 3 +++
10
fpu/softfloat-specialize.c.inc | 8 +-------
11
3 files changed, 8 insertions(+), 7 deletions(-)
12
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/mips/fpu_helper.h
16
+++ b/target/mips/fpu_helper.h
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
18
{
19
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
20
FloatInfZeroNaNRule izn_rule;
21
+ Float3NaNPropRule nan3_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
28
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
29
+ nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
30
+ set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
31
+
32
}
33
34
static inline void restore_fp_status(CPUMIPSState *env)
35
diff --git a/target/mips/msa.c b/target/mips/msa.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/mips/msa.c
38
+++ b/target/mips/msa.c
39
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
40
set_float_2nan_prop_rule(float_2nan_prop_s_ab,
41
&env->active_tc.msa_fp_status);
42
43
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab,
44
+ &env->active_tc.msa_fp_status);
45
+
46
/* clear float_status exception flags */
47
set_float_exception_flags(0, &env->active_tc.msa_fp_status);
48
49
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
50
index XXXXXXX..XXXXXXX 100644
51
--- a/fpu/softfloat-specialize.c.inc
52
+++ b/fpu/softfloat-specialize.c.inc
53
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
54
}
55
56
if (rule == float_3nan_prop_none) {
57
-#if defined(TARGET_MIPS)
58
- if (snan_bit_is_one(status)) {
59
- rule = float_3nan_prop_s_abc;
60
- } else {
61
- rule = float_3nan_prop_s_cab;
62
- }
63
-#elif defined(TARGET_XTENSA)
64
+#if defined(TARGET_XTENSA)
65
if (status->use_first_nan) {
66
rule = float_3nan_prop_abc;
67
} else {
68
--
69
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/46] aspeed: add support for multiple NICs
[PULL 28/72] target/xtensa: Set Float3NaNPropRule explicitly
1
From: Cédric Le Goater <clg@kaod.org>
1
Set the Float3NaNPropRule explicitly for xtensa, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
The Aspeed SoCs have two MACs. Extend the Aspeed model to support a
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
second NIC.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-24-peter.maydell@linaro.org
7
---
8
target/xtensa/fpu_helper.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 8 --------
10
2 files changed, 2 insertions(+), 8 deletions(-)
5
11
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
12
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
7
Reviewed-by: Joel Stanley <joel@jms.id.au>
8
Message-id: 20190618165311.27066-7-clg@kaod.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/aspeed_soc.h | 3 ++-
12
hw/arm/aspeed_soc.c | 33 +++++++++++++++++++--------------
13
2 files changed, 21 insertions(+), 15 deletions(-)
14
15
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/aspeed_soc.h
14
--- a/target/xtensa/fpu_helper.c
18
+++ b/include/hw/arm/aspeed_soc.h
15
+++ b/target/xtensa/fpu_helper.c
19
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
20
#define ASPEED_SPIS_NUM 2
17
set_use_first_nan(use_first, &env->fp_status);
21
#define ASPEED_WDTS_NUM 3
18
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
22
#define ASPEED_CPUS_NUM 2
19
&env->fp_status);
23
+#define ASPEED_MACS_NUM 2
20
+ set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
24
21
+ &env->fp_status);
25
typedef struct AspeedSoCState {
22
}
26
/*< private >*/
23
27
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
24
void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v)
28
AspeedSMCState spi[ASPEED_SPIS_NUM];
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
29
AspeedSDMCState sdmc;
30
AspeedWDTState wdt[ASPEED_WDTS_NUM];
31
- FTGMAC100State ftgmac100;
32
+ FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
33
} AspeedSoCState;
34
35
#define TYPE_ASPEED_SOC "aspeed-soc"
36
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
37
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/arm/aspeed_soc.c
27
--- a/fpu/softfloat-specialize.c.inc
39
+++ b/hw/arm/aspeed_soc.c
28
+++ b/fpu/softfloat-specialize.c.inc
40
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
41
sc->info->silicon_rev);
42
}
30
}
43
31
44
- sysbus_init_child_obj(obj, "ftgmac100", OBJECT(&s->ftgmac100),
32
if (rule == float_3nan_prop_none) {
45
- sizeof(s->ftgmac100), TYPE_FTGMAC100);
33
-#if defined(TARGET_XTENSA)
46
+ for (i = 0; i < ASPEED_MACS_NUM; i++) {
34
- if (status->use_first_nan) {
47
+ sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
35
- rule = float_3nan_prop_abc;
48
+ sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
36
- } else {
49
+ }
37
- rule = float_3nan_prop_cba;
50
}
38
- }
51
39
-#else
52
static void aspeed_soc_realize(DeviceState *dev, Error **errp)
40
rule = float_3nan_prop_abc;
53
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
41
-#endif
54
}
42
}
55
43
56
/* Net */
44
assert(rule != float_3nan_prop_none);
57
- qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]);
58
- object_property_set_bool(OBJECT(&s->ftgmac100), true, "aspeed", &err);
59
- object_property_set_bool(OBJECT(&s->ftgmac100), true, "realized",
60
- &local_err);
61
- error_propagate(&err, local_err);
62
- if (err) {
63
- error_propagate(errp, err);
64
- return;
65
+ for (i = 0; i < nb_nics; i++) {
66
+ qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
67
+ object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
68
+ &err);
69
+ object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
70
+ &local_err);
71
+ error_propagate(&err, local_err);
72
+ if (err) {
73
+ error_propagate(errp, err);
74
+ return;
75
+ }
76
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
77
+ sc->info->memmap[ASPEED_ETH1 + i]);
78
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
79
+ aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
80
}
81
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0,
82
- sc->info->memmap[ASPEED_ETH1]);
83
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
84
- aspeed_soc_get_irq(s, ASPEED_ETH1));
85
}
86
static Property aspeed_soc_properties[] = {
87
DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
88
--
45
--
89
2.20.1
46
2.34.1
90
91
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/46] hw/arm/virt: Add support for Cortex-A7
[PULL 29/72] target/i386: Set Float3NaNPropRule explicitly
1
From: Jan Kiszka <jan.kiszka@siemens.com>
1
Set the Float3NaNPropRule explicitly for i386. We had no
2
i386-specific behaviour in the old ifdef ladder, so we were using the
3
default "prefer a then b then c" fallback; this is actually the
4
correct per-the-spec handling for i386.
2
5
3
Allow cortex-a7 to be used with the virt board; it supports
4
the v7VE features and there is no reason to deny this type.
5
6
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: fc5404f7-4d1d-c28f-6e48-d8799c82acc0@web.de
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-25-peter.maydell@linaro.org
11
---
9
---
12
hw/arm/virt.c | 1 +
10
target/i386/tcg/fpu_helper.c | 1 +
13
1 file changed, 1 insertion(+)
11
1 file changed, 1 insertion(+)
14
12
15
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
13
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
16
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/virt.c
15
--- a/target/i386/tcg/fpu_helper.c
18
+++ b/hw/arm/virt.c
16
+++ b/target/i386/tcg/fpu_helper.c
19
@@ -XXX,XX +XXX,XX @@ static const int a15irqmap[] = {
17
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
20
};
18
* there are multiple input NaNs they are selected in the order a, b, c.
21
19
*/
22
static const char *valid_cpus[] = {
20
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
23
+ ARM_CPU_TYPE_NAME("cortex-a7"),
21
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
24
ARM_CPU_TYPE_NAME("cortex-a15"),
22
}
25
ARM_CPU_TYPE_NAME("cortex-a53"),
23
26
ARM_CPU_TYPE_NAME("cortex-a57"),
24
static inline uint8_t save_exception_flags(CPUX86State *env)
27
--
25
--
28
2.20.1
26
2.34.1
29
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 25/46] aspeed: Link SCU to the watchdog
[PULL 30/72] target/hppa: Set Float3NaNPropRule explicitly
1
From: Joel Stanley <joel@jms.id.au>
1
Set the Float3NaNPropRule explicitly for HPPA, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
The ast2500 uses the watchdog to reset the SDRAM controller. This
4
HPPA is the only target that was using the default branch of the
4
operation is usually performed by u-boot's memory training procedure,
5
ifdef ladder (other targets either do not use muladd or set
5
and it is enabled by setting a bit in the SCU and then causing the
6
default_nan_mode), so we can remove the ifdef fallback entirely now
6
watchdog to expire. Therefore, we need the watchdog to be able to
7
(allowing the "rule not set" case to fall into the default of the
7
access the SCU's register space.
8
switch statement and assert).
8
9
9
This causes the watchdog to not perform a system reset when the bit is
10
We add a TODO note that the HPPA rule is probably wrong; this is
10
set. In the future it could perform a reset of the SDMC model.
11
not a behavioural change for this refactoring.
11
12
12
Signed-off-by: Joel Stanley <joel@jms.id.au>
13
Signed-off-by: Cédric Le Goater <clg@kaod.org>
14
Reviewed-by: Cédric Le Goater <clg@kaod.org>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
16
Message-id: 20190621065242.32535-1-joel@jms.id.au
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-26-peter.maydell@linaro.org
18
---
16
---
19
include/hw/watchdog/wdt_aspeed.h | 1 +
17
target/hppa/fpu_helper.c | 8 ++++++++
20
hw/arm/aspeed_soc.c | 2 ++
18
fpu/softfloat-specialize.c.inc | 4 ----
21
hw/watchdog/wdt_aspeed.c | 20 ++++++++++++++++++++
19
2 files changed, 8 insertions(+), 4 deletions(-)
22
3 files changed, 23 insertions(+)
23
20
24
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
21
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
25
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/watchdog/wdt_aspeed.h
23
--- a/target/hppa/fpu_helper.c
27
+++ b/include/hw/watchdog/wdt_aspeed.h
24
+++ b/target/hppa/fpu_helper.c
28
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedWDTState {
25
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
29
MemoryRegion iomem;
26
* HPPA does note implement a CPU reset method at all...
30
uint32_t regs[ASPEED_WDT_REGS_MAX];
27
*/
31
28
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
32
+ AspeedSCUState *scu;
29
+ /*
33
uint32_t pclk_freq;
30
+ * TODO: The HPPA architecture reference only documents its NaN
34
uint32_t silicon_rev;
31
+ * propagation rule for 2-operand operations. Testing on real hardware
35
uint32_t ext_pulse_width_mask;
32
+ * might be necessary to confirm whether this order for muladd is correct.
36
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
33
+ * Not preferring the SNaN is almost certainly incorrect as it diverges
34
+ * from the documented rules for 2-operand operations.
35
+ */
36
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
37
/* For inf * 0 + NaN, return the input NaN */
38
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
39
}
40
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
37
index XXXXXXX..XXXXXXX 100644
41
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/arm/aspeed_soc.c
42
--- a/fpu/softfloat-specialize.c.inc
39
+++ b/hw/arm/aspeed_soc.c
43
+++ b/fpu/softfloat-specialize.c.inc
40
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
44
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
41
sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
45
}
42
qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev",
43
sc->info->silicon_rev);
44
+ object_property_add_const_link(OBJECT(&s->wdt[i]), "scu",
45
+ OBJECT(&s->scu), &error_abort);
46
}
46
}
47
47
48
for (i = 0; i < ASPEED_MACS_NUM; i++) {
48
- if (rule == float_3nan_prop_none) {
49
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
49
- rule = float_3nan_prop_abc;
50
index XXXXXXX..XXXXXXX 100644
50
- }
51
--- a/hw/watchdog/wdt_aspeed.c
51
-
52
+++ b/hw/watchdog/wdt_aspeed.c
52
assert(rule != float_3nan_prop_none);
53
@@ -XXX,XX +XXX,XX @@
53
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
54
54
/* We have at least one SNaN input and should prefer it */
55
#define WDT_RESTART_MAGIC 0x4755
56
57
+#define SCU_RESET_CONTROL1 (0x04 / 4)
58
+#define SCU_RESET_SDRAM BIT(0)
59
+
60
static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)
61
{
62
return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE;
63
@@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_timer_expired(void *dev)
64
{
65
AspeedWDTState *s = ASPEED_WDT(dev);
66
67
+ /* Do not reset on SDRAM controller reset */
68
+ if (s->scu->regs[SCU_RESET_CONTROL1] & SCU_RESET_SDRAM) {
69
+ timer_del(s->timer);
70
+ s->regs[WDT_CTRL] = 0;
71
+ return;
72
+ }
73
+
74
qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n");
75
watchdog_perform_action();
76
timer_del(s->timer);
77
@@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
78
{
79
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
80
AspeedWDTState *s = ASPEED_WDT(dev);
81
+ Error *err = NULL;
82
+ Object *obj;
83
+
84
+ obj = object_property_get_link(OBJECT(dev), "scu", &err);
85
+ if (!obj) {
86
+ error_propagate(errp, err);
87
+ error_prepend(errp, "required link 'scu' not found: ");
88
+ return;
89
+ }
90
+ s->scu = ASPEED_SCU(obj);
91
92
if (!is_supported_silicon_rev(s->silicon_rev)) {
93
error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
94
--
55
--
95
2.20.1
56
2.34.1
96
97
diff view generated by jsdifflib
[Qemu-devel] [PULL 45/46] target/arm: Declare arm_log_exception() function publicly
[PULL 31/72] fpu: Remove use_first_nan field from float_status
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
The use_first_nan field in float_status was an xtensa-specific way to
2
select at runtime from two different NaN propagation rules. Now that
3
xtensa is using the target-agnostic NaN propagation rule selection
4
that we've just added, we can remove use_first_nan, because there is
5
no longer any code that reads it.
2
6
3
In few commits we will split the M-profile functions from this
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
file, and this function will also be called in the new file.
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Declare it in the "internals.h" header.
9
Message-id: 20241202131347.498124-27-peter.maydell@linaro.org
6
Since it is in the middle of a block of M profile functions,
10
---
7
move it previous to this block to ease the later refactor.
11
include/fpu/softfloat-helpers.h | 5 -----
12
include/fpu/softfloat-types.h | 1 -
13
target/xtensa/fpu_helper.c | 1 -
14
3 files changed, 7 deletions(-)
8
15
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
16
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
10
Message-id: 20190701132516.26392-21-philmd@redhat.com
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/internals.h | 2 ++
15
target/arm/helper.c | 76 +++++++++++++++++++++---------------------
16
2 files changed, 40 insertions(+), 38 deletions(-)
17
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
19
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/internals.h
18
--- a/include/fpu/softfloat-helpers.h
21
+++ b/target/arm/internals.h
19
+++ b/include/fpu/softfloat-helpers.h
22
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
20
@@ -XXX,XX +XXX,XX @@ static inline void set_snan_bit_is_one(bool val, float_status *status)
23
target_ulong *page_size,
21
status->snan_bit_is_one = val;
24
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
25
26
+void arm_log_exception(int idx);
27
+
28
#endif /* !CONFIG_USER_ONLY */
29
30
#endif
31
diff --git a/target/arm/helper.c b/target/arm/helper.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/helper.c
34
+++ b/target/arm/helper.c
35
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
36
return target_el;
37
}
22
}
38
23
39
+void arm_log_exception(int idx)
24
-static inline void set_use_first_nan(bool val, float_status *status)
40
+{
41
+ if (qemu_loglevel_mask(CPU_LOG_INT)) {
42
+ const char *exc = NULL;
43
+ static const char * const excnames[] = {
44
+ [EXCP_UDEF] = "Undefined Instruction",
45
+ [EXCP_SWI] = "SVC",
46
+ [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
47
+ [EXCP_DATA_ABORT] = "Data Abort",
48
+ [EXCP_IRQ] = "IRQ",
49
+ [EXCP_FIQ] = "FIQ",
50
+ [EXCP_BKPT] = "Breakpoint",
51
+ [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
52
+ [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
53
+ [EXCP_HVC] = "Hypervisor Call",
54
+ [EXCP_HYP_TRAP] = "Hypervisor Trap",
55
+ [EXCP_SMC] = "Secure Monitor Call",
56
+ [EXCP_VIRQ] = "Virtual IRQ",
57
+ [EXCP_VFIQ] = "Virtual FIQ",
58
+ [EXCP_SEMIHOST] = "Semihosting call",
59
+ [EXCP_NOCP] = "v7M NOCP UsageFault",
60
+ [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
61
+ [EXCP_STKOF] = "v8M STKOF UsageFault",
62
+ [EXCP_LAZYFP] = "v7M exception during lazy FP stacking",
63
+ [EXCP_LSERR] = "v8M LSERR UsageFault",
64
+ [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
65
+ };
66
+
67
+ if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
68
+ exc = excnames[idx];
69
+ }
70
+ if (!exc) {
71
+ exc = "unknown";
72
+ }
73
+ qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
74
+ }
75
+}
76
+
77
/*
78
* Return true if the v7M CPACR permits access to the FPU for the specified
79
* security state and privilege level.
80
@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
81
return true;
82
}
83
84
-static void arm_log_exception(int idx)
85
-{
25
-{
86
- if (qemu_loglevel_mask(CPU_LOG_INT)) {
26
- status->use_first_nan = val;
87
- const char *exc = NULL;
88
- static const char * const excnames[] = {
89
- [EXCP_UDEF] = "Undefined Instruction",
90
- [EXCP_SWI] = "SVC",
91
- [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
92
- [EXCP_DATA_ABORT] = "Data Abort",
93
- [EXCP_IRQ] = "IRQ",
94
- [EXCP_FIQ] = "FIQ",
95
- [EXCP_BKPT] = "Breakpoint",
96
- [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
97
- [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
98
- [EXCP_HVC] = "Hypervisor Call",
99
- [EXCP_HYP_TRAP] = "Hypervisor Trap",
100
- [EXCP_SMC] = "Secure Monitor Call",
101
- [EXCP_VIRQ] = "Virtual IRQ",
102
- [EXCP_VFIQ] = "Virtual FIQ",
103
- [EXCP_SEMIHOST] = "Semihosting call",
104
- [EXCP_NOCP] = "v7M NOCP UsageFault",
105
- [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
106
- [EXCP_STKOF] = "v8M STKOF UsageFault",
107
- [EXCP_LAZYFP] = "v7M exception during lazy FP stacking",
108
- [EXCP_LSERR] = "v8M LSERR UsageFault",
109
- [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
110
- };
111
-
112
- if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
113
- exc = excnames[idx];
114
- }
115
- if (!exc) {
116
- exc = "unknown";
117
- }
118
- qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
119
- }
120
-}
27
-}
121
-
28
-
122
static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
29
static inline void set_no_signaling_nans(bool val, float_status *status)
123
uint32_t addr, uint16_t *insn)
124
{
30
{
31
status->no_signaling_nans = val;
32
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/include/fpu/softfloat-types.h
35
+++ b/include/fpu/softfloat-types.h
36
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
37
* softfloat-specialize.inc.c)
38
*/
39
bool snan_bit_is_one;
40
- bool use_first_nan;
41
bool no_signaling_nans;
42
/* should overflowed results subtract re_bias to its exponent? */
43
bool rebias_overflow;
44
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/xtensa/fpu_helper.c
47
+++ b/target/xtensa/fpu_helper.c
48
@@ -XXX,XX +XXX,XX @@ static const struct {
49
50
void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
51
{
52
- set_use_first_nan(use_first, &env->fp_status);
53
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
54
&env->fp_status);
55
set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
125
--
56
--
126
2.20.1
57
2.34.1
127
128
diff view generated by jsdifflib
New patch
[PULL 32/72] target/m68k: Don't pass NULL float_status to floatx80_default_nan()
1
Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL)
2
to get the NaN bit pattern to reset the FPU registers. This
3
works because it happens that our implementation of
4
floatx80_default_nan() doesn't actually look at the float_status
5
pointer except for TARGET_MIPS. However, this isn't guaranteed,
6
and to be able to remove the ifdef in floatx80_default_nan()
7
we're going to need a real float_status here.
1
8
9
Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status
10
earlier, and thus can pass it to floatx80_default_nan().
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20241202131347.498124-28-peter.maydell@linaro.org
15
---
16
target/m68k/cpu.c | 12 +++++++-----
17
1 file changed, 7 insertions(+), 5 deletions(-)
18
19
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/m68k/cpu.c
22
+++ b/target/m68k/cpu.c
23
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
24
CPUState *cs = CPU(obj);
25
M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj);
26
CPUM68KState *env = cpu_env(cs);
27
- floatx80 nan = floatx80_default_nan(NULL);
28
+ floatx80 nan;
29
int i;
30
31
if (mcc->parent_phases.hold) {
32
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
33
#else
34
cpu_m68k_set_sr(env, SR_S | SR_I);
35
#endif
36
- for (i = 0; i < 8; i++) {
37
- env->fregs[i].d = nan;
38
- }
39
- cpu_m68k_set_fpcr(env, 0);
40
/*
41
* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
42
* 3.4 FLOATING-POINT INSTRUCTION DETAILS
43
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
44
* preceding paragraph for nonsignaling NaNs.
45
*/
46
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
47
+
48
+ nan = floatx80_default_nan(&env->fp_status);
49
+ for (i = 0; i < 8; i++) {
50
+ env->fregs[i].d = nan;
51
+ }
52
+ cpu_m68k_set_fpcr(env, 0);
53
env->fpsr = 0;
54
55
/* TODO: We should set PC from the interrupt vector. */
56
--
57
2.34.1
diff view generated by jsdifflib
New patch
[PULL 33/72] softfloat: Create floatx80 default NaN from parts64_default_nan
1
We create our 128-bit default NaN by calling parts64_default_nan()
2
and then adjusting the result. We can do the same trick for creating
3
the floatx80 default NaN, which lets us drop a target ifdef.
1
4
5
floatx80 is used only by:
6
i386
7
m68k
8
arm nwfpe old floating-point emulation emulation support
9
(which is essentially dead, especially the parts involving floatx80)
10
PPC (only in the xsrqpxp instruction, which just rounds an input
11
value by converting to floatx80 and back, so will never generate
12
the default NaN)
13
14
The floatx80 default NaN as currently implemented is:
15
m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1
16
i386: sign = 1, exp = 1...1, int = 1, frac = 10...0
17
18
These are the same as the parts64_default_nan for these architectures.
19
20
This is technically a possible behaviour change for arm linux-user
21
nwfpe emulation emulation, because the default NaN will now have the
22
sign bit clear. But we were already generating a different floatx80
23
default NaN from the real kernel emulation we are supposedly
24
following, which appears to use an all-bits-1 value:
25
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267
26
27
This won't affect the only "real" use of the nwfpe emulation, which
28
is ancient binaries that used it as part of the old floating point
29
calling convention; that only uses loads and stores of 32 and 64 bit
30
floats, not any of the floatx80 behaviour the original hardware had.
31
We also get the nwfpe float64 default NaN value wrong:
32
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166
33
so if we ever cared about this obscure corner the right fix would be
34
to correct that so nwfpe used its own default-NaN setting rather
35
than the Arm VFP one.
36
37
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
38
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
39
Message-id: 20241202131347.498124-29-peter.maydell@linaro.org
40
---
41
fpu/softfloat-specialize.c.inc | 20 ++++++++++----------
42
1 file changed, 10 insertions(+), 10 deletions(-)
43
44
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
45
index XXXXXXX..XXXXXXX 100644
46
--- a/fpu/softfloat-specialize.c.inc
47
+++ b/fpu/softfloat-specialize.c.inc
48
@@ -XXX,XX +XXX,XX @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status)
49
floatx80 floatx80_default_nan(float_status *status)
50
{
51
floatx80 r;
52
+ /*
53
+ * Extrapolate from the choices made by parts64_default_nan to fill
54
+ * in the floatx80 format. We assume that floatx80's explicit
55
+ * integer bit is always set (this is true for i386 and m68k,
56
+ * which are the only real users of this format).
57
+ */
58
+ FloatParts64 p64;
59
+ parts64_default_nan(&p64, status);
60
61
- /* None of the targets that have snan_bit_is_one use floatx80. */
62
- assert(!snan_bit_is_one(status));
63
-#if defined(TARGET_M68K)
64
- r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
65
- r.high = 0x7FFF;
66
-#else
67
- /* X86 */
68
- r.low = UINT64_C(0xC000000000000000);
69
- r.high = 0xFFFF;
70
-#endif
71
+ r.high = 0x7FFF | (p64.sign << 15);
72
+ r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac;
73
return r;
74
}
75
76
--
77
2.34.1
diff view generated by jsdifflib
New patch
[PULL 34/72] target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
1
In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass
2
a zero-initialized float_status struct to float32_is_quiet_nan() and
3
float64_is_quiet_nan(), with the cryptic comment "for
4
snan_bit_is_one".
1
5
6
This pattern appears to have been copied from target/riscv, where it
7
is used because the functions there do not have ready access to the
8
CPU state struct. The comment presumably refers to the fact that the
9
main reason the is_quiet_nan() functions want the float_state is
10
because they want to know about the snan_bit_is_one config.
11
12
In the loongarch helpers, though, we have the CPU state struct
13
to hand. Use the usual env->fp_status here. This avoids our needing
14
to track that we need to update the initializer of the local
15
float_status structs when the core softfloat code adds new
16
options for targets to configure their behaviour.
17
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20241202131347.498124-30-peter.maydell@linaro.org
21
---
22
target/loongarch/tcg/fpu_helper.c | 6 ++----
23
1 file changed, 2 insertions(+), 4 deletions(-)
24
25
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/loongarch/tcg/fpu_helper.c
28
+++ b/target/loongarch/tcg/fpu_helper.c
29
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj)
30
} else if (float32_is_zero_or_denormal(f)) {
31
return sign ? 1 << 4 : 1 << 8;
32
} else if (float32_is_any_nan(f)) {
33
- float_status s = { }; /* for snan_bit_is_one */
34
- return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
35
+ return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
36
} else {
37
return sign ? 1 << 3 : 1 << 7;
38
}
39
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj)
40
} else if (float64_is_zero_or_denormal(f)) {
41
return sign ? 1 << 4 : 1 << 8;
42
} else if (float64_is_any_nan(f)) {
43
- float_status s = { }; /* for snan_bit_is_one */
44
- return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
45
+ return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
46
} else {
47
return sign ? 1 << 3 : 1 << 7;
48
}
49
--
50
2.34.1
diff view generated by jsdifflib
New patch
[PULL 35/72] target/m68k: In frem helper, initialize local float_status from env->fp_status
1
In the frem helper, we have a local float_status because we want to
2
execute the floatx80_div() with a custom rounding mode. Instead of
3
zero-initializing the local float_status and then having to set it up
4
with the m68k standard behaviour (including the NaN propagation rule
5
and copying the rounding precision from env->fp_status), initialize
6
it as a complete copy of env->fp_status. This will avoid our having
7
to add new code in this function for every new config knob we add
8
to fp_status.
1
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-31-peter.maydell@linaro.org
13
---
14
target/m68k/fpu_helper.c | 6 ++----
15
1 file changed, 2 insertions(+), 4 deletions(-)
16
17
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/m68k/fpu_helper.c
20
+++ b/target/m68k/fpu_helper.c
21
@@ -XXX,XX +XXX,XX @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1)
22
23
fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status);
24
if (!floatx80_is_any_nan(fp_rem)) {
25
- float_status fp_status = { };
26
+ /* Use local temporary fp_status to set different rounding mode */
27
+ float_status fp_status = env->fp_status;
28
uint32_t quotient;
29
int sign;
30
31
/* Calculate quotient directly using round to nearest mode */
32
- set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status);
33
set_float_rounding_mode(float_round_nearest_even, &fp_status);
34
- set_floatx80_rounding_precision(
35
- get_floatx80_rounding_precision(&env->fp_status), &fp_status);
36
fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status);
37
38
sign = extractFloatx80Sign(fp_quot.d);
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 36/72] target/m68k: Init local float_status from env fp_status in gdb get/set reg
1
In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion
2
from float64 to floatx80 using a scratch float_status, because we
3
don't want the conversion to affect the CPU's floating point exception
4
status. Currently we use a zero-initialized float_status. This will
5
get steadily more awkward as we add config knobs to float_status
6
that the target must initialize. Avoid having to add any of that
7
configuration here by instead initializing our local float_status
8
from the env->fp_status.
1
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-32-peter.maydell@linaro.org
13
---
14
target/m68k/helper.c | 6 ++++--
15
1 file changed, 4 insertions(+), 2 deletions(-)
16
17
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/m68k/helper.c
20
+++ b/target/m68k/helper.c
21
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n)
22
CPUM68KState *env = &cpu->env;
23
24
if (n < 8) {
25
- float_status s = {};
26
+ /* Use scratch float_status so any exceptions don't change CPU state */
27
+ float_status s = env->fp_status;
28
return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s));
29
}
30
switch (n) {
31
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n)
32
CPUM68KState *env = &cpu->env;
33
34
if (n < 8) {
35
- float_status s = {};
36
+ /* Use scratch float_status so any exceptions don't change CPU state */
37
+ float_status s = env->fp_status;
38
env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s);
39
return 8;
40
}
41
--
42
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/46] i.mx7d: pci: Update PCI IRQ mapping to match HW
[PULL 37/72] target/sparc: Initialize local scratch float_status from env->fp_status
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
In the helper functions flcmps and flcmpd we use a scratch float_status
2
so that we don't change the CPU state if the comparison raises any
3
floating point exception flags. Instead of zero-initializing this
4
scratch float_status, initialize it as a copy of env->fp_status. This
5
avoids the need to explicitly initialize settings like the NaN
6
propagation rule or others we might add to softfloat in future.
2
7
3
Datasheet for i.MX7 is incorrect and i.MX7's PCI IRQ mapping matches
8
To do this we need to pass the CPU env pointer in to the helper.
4
that of i.MX6:
5
9
6
* INTD/MSI 122
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
* INTC 123
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
* INTB 124
12
Message-id: 20241202131347.498124-33-peter.maydell@linaro.org
9
* INTA 125
13
---
14
target/sparc/helper.h | 4 ++--
15
target/sparc/fop_helper.c | 8 ++++----
16
target/sparc/translate.c | 4 ++--
17
3 files changed, 8 insertions(+), 8 deletions(-)
10
18
11
Fix all of the relevant code to reflect that fact. Needed by latest
19
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
12
Linux kernels.
13
14
(Reference: Linux kernel commit 538d6e9d597584e80 from an
15
NXP employee confirming that the datasheet is incorrect and
16
with a report of a test against hardware.)
17
18
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
19
Cc: Peter Maydell <peter.maydell@linaro.org>
20
Cc: Michael S. Tsirkin <mst@redhat.com>
21
Cc: qemu-devel@nongnu.org
22
Cc: qemu-arm@nongnu.org
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
[PMM: added ref to kernel commit confirming the datasheet error]
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
---
27
include/hw/arm/fsl-imx7.h | 8 ++++----
28
hw/pci-host/designware.c | 6 ++++--
29
2 files changed, 8 insertions(+), 6 deletions(-)
30
31
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
32
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
33
--- a/include/hw/arm/fsl-imx7.h
21
--- a/target/sparc/helper.h
34
+++ b/include/hw/arm/fsl-imx7.h
22
+++ b/target/sparc/helper.h
35
@@ -XXX,XX +XXX,XX @@ enum FslIMX7IRQs {
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64)
36
FSL_IMX7_USB2_IRQ = 42,
24
DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64)
37
FSL_IMX7_USB3_IRQ = 40,
25
DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128)
38
26
DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128)
39
- FSL_IMX7_PCI_INTA_IRQ = 122,
27
-DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32)
40
- FSL_IMX7_PCI_INTB_IRQ = 123,
28
-DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64)
41
- FSL_IMX7_PCI_INTC_IRQ = 124,
29
+DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32)
42
- FSL_IMX7_PCI_INTD_IRQ = 125,
30
+DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64)
43
+ FSL_IMX7_PCI_INTA_IRQ = 125,
31
DEF_HELPER_2(raise_exception, noreturn, env, int)
44
+ FSL_IMX7_PCI_INTB_IRQ = 124,
32
45
+ FSL_IMX7_PCI_INTC_IRQ = 123,
33
DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64)
46
+ FSL_IMX7_PCI_INTD_IRQ = 122,
34
diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c
47
48
FSL_IMX7_UART7_IRQ = 126,
49
50
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
51
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
52
--- a/hw/pci-host/designware.c
36
--- a/target/sparc/fop_helper.c
53
+++ b/hw/pci-host/designware.c
37
+++ b/target/sparc/fop_helper.c
54
@@ -XXX,XX +XXX,XX @@
38
@@ -XXX,XX +XXX,XX @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2)
55
#define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff)
39
return finish_fcmp(env, r, GETPC());
56
#define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C
40
}
57
41
58
+#define DESIGNWARE_PCIE_IRQ_MSI 3
42
-uint32_t helper_flcmps(float32 src1, float32 src2)
59
+
43
+uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2)
60
static DesignwarePCIEHost *
61
designware_pcie_root_to_host(DesignwarePCIERoot *root)
62
{
44
{
63
@@ -XXX,XX +XXX,XX @@ static void designware_pcie_root_msi_write(void *opaque, hwaddr addr,
45
/*
64
root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable;
46
* FLCMP never raises an exception nor modifies any FSR fields.
65
47
* Perform the comparison with a dummy fp environment.
66
if (root->msi.intr[0].status & ~root->msi.intr[0].mask) {
48
*/
67
- qemu_set_irq(host->pci.irqs[0], 1);
49
- float_status discard = { };
68
+ qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 1);
50
+ float_status discard = env->fp_status;
69
}
51
FloatRelation r;
52
53
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
54
@@ -XXX,XX +XXX,XX @@ uint32_t helper_flcmps(float32 src1, float32 src2)
55
g_assert_not_reached();
70
}
56
}
71
57
72
@@ -XXX,XX +XXX,XX @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
58
-uint32_t helper_flcmpd(float64 src1, float64 src2)
73
case DESIGNWARE_PCIE_MSI_INTR0_STATUS:
59
+uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2)
74
root->msi.intr[0].status ^= val;
60
{
75
if (!root->msi.intr[0].status) {
61
- float_status discard = { };
76
- qemu_set_irq(host->pci.irqs[0], 0);
62
+ float_status discard = env->fp_status;
77
+ qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 0);
63
FloatRelation r;
78
}
64
79
break;
65
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
66
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/sparc/translate.c
69
+++ b/target/sparc/translate.c
70
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a)
71
72
src1 = gen_load_fpr_F(dc, a->rs1);
73
src2 = gen_load_fpr_F(dc, a->rs2);
74
- gen_helper_flcmps(cpu_fcc[a->cc], src1, src2);
75
+ gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2);
76
return advance_pc(dc);
77
}
78
79
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a)
80
81
src1 = gen_load_fpr_D(dc, a->rs1);
82
src2 = gen_load_fpr_D(dc, a->rs2);
83
- gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2);
84
+ gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2);
85
return advance_pc(dc);
86
}
80
87
81
--
88
--
82
2.20.1
89
2.34.1
83
84
diff view generated by jsdifflib
New patch
[PULL 38/72] target/ppc: Use env->fp_status in helper_compute_fprf functions
1
In the helper_compute_fprf functions, we pass a dummy float_status
2
in to the is_signaling_nan() function. This is unnecessary, because
3
we have convenient access to the CPU env pointer here and that
4
is already set up with the correct values for the snan_bit_is_one
5
and no_signaling_nans config settings. is_signaling_nan() doesn't
6
ever update the fp_status with any exception flags, so there is
7
no reason not to use env->fp_status here.
1
8
9
Use env->fp_status instead of the dummy fp_status.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20241202131347.498124-34-peter.maydell@linaro.org
14
---
15
target/ppc/fpu_helper.c | 3 +--
16
1 file changed, 1 insertion(+), 2 deletions(-)
17
18
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/ppc/fpu_helper.c
21
+++ b/target/ppc/fpu_helper.c
22
@@ -XXX,XX +XXX,XX @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
23
} else if (tp##_is_infinity(arg)) { \
24
fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \
25
} else { \
26
- float_status dummy = { }; /* snan_bit_is_one = 0 */ \
27
- if (tp##_is_signaling_nan(arg, &dummy)) { \
28
+ if (tp##_is_signaling_nan(arg, &env->fp_status)) { \
29
fprf = 0x00 << FPSCR_FPRF; \
30
} else { \
31
fprf = 0x11 << FPSCR_FPRF; \
32
--
33
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 32/46] target/arm: Add copyright boilerplate
[PULL 39/72] target/arm: Copy entire float_status in is_ebf
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Reviewed-by: Robert Bradford <robert.bradford@intel.com>
3
Now that float_status has a bunch of fp parameters,
4
Reviewed-by: Samuel Ortiz <sameo@linux.intel.com>
4
it is easier to copy an existing structure than create
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
one from scratch. Begin by copying the structure that
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
corresponds to the FPSR and make only the adjustments
7
Message-id: 20190701132516.26392-6-philmd@redhat.com
7
required for BFloat16 semantics.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20241203203949.483774-2-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
14
---
10
target/arm/helper.c | 7 +++++++
15
target/arm/tcg/vec_helper.c | 20 +++++++-------------
11
1 file changed, 7 insertions(+)
16
1 file changed, 7 insertions(+), 13 deletions(-)
12
17
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
18
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
14
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
20
--- a/target/arm/tcg/vec_helper.c
16
+++ b/target/arm/helper.c
21
+++ b/target/arm/tcg/vec_helper.c
17
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp)
18
+/*
23
* no effect on AArch32 instructions.
19
+ * ARM generic helpers.
24
*/
20
+ *
25
bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF;
21
+ * This code is licensed under the GNU GPL v2 or later.
26
- *statusp = (float_status){
22
+ *
27
- .tininess_before_rounding = float_tininess_before_rounding,
23
+ * SPDX-License-Identifier: GPL-2.0-or-later
28
- .float_rounding_mode = float_round_to_odd_inf,
24
+ */
29
- .flush_to_zero = true,
25
#include "qemu/osdep.h"
30
- .flush_inputs_to_zero = true,
26
#include "qemu/units.h"
31
- .default_nan_mode = true,
27
#include "target/arm/idau.h"
32
- };
33
+
34
+ *statusp = env->vfp.fp_status;
35
+ set_default_nan_mode(true, statusp);
36
37
if (ebf) {
38
- float_status *fpst = &env->vfp.fp_status;
39
- set_flush_to_zero(get_flush_to_zero(fpst), statusp);
40
- set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp);
41
- set_float_rounding_mode(get_float_rounding_mode(fpst), statusp);
42
-
43
/* EBF=1 needs to do a step with round-to-odd semantics */
44
*oddstatusp = *statusp;
45
set_float_rounding_mode(float_round_to_odd, oddstatusp);
46
+ } else {
47
+ set_flush_to_zero(true, statusp);
48
+ set_flush_inputs_to_zero(true, statusp);
49
+ set_float_rounding_mode(float_round_to_odd_inf, statusp);
50
}
51
-
52
return ebf;
53
}
54
28
--
55
--
29
2.20.1
56
2.34.1
30
57
31
58
diff view generated by jsdifflib
[Qemu-devel] [PULL 43/46] target/arm/vfp_helper: Restrict the SoftFloat use to TCG
[PULL 40/72] fpu: Allow runtime choice of default NaN value
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Currently we hardcode the default NaN value in parts64_default_nan()
2
using a compile-time ifdef ladder. This is awkward for two cases:
3
* for single-QEMU-binary we can't hard-code target-specifics like this
4
* for Arm FEAT_AFP the default NaN value depends on FPCR.AH
5
(specifically the sign bit is different)
2
6
3
This code is specific to the SoftFloat floating-point
7
Add a field to float_status to specify the default NaN value; fall
4
implementation, which is only used by TCG.
8
back to the old ifdef behaviour if these are not set.
5
9
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
The default NaN value is specified by setting a uint8_t to a
7
Message-id: 20190701132516.26392-18-philmd@redhat.com
11
pattern corresponding to the sign and upper fraction parts of
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
the NaN; the lower bits of the fraction are set from bit 0 of
13
the pattern.
14
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20241202131347.498124-35-peter.maydell@linaro.org
10
---
18
---
11
target/arm/vfp_helper.c | 26 +++++++++++++++++++++++---
19
include/fpu/softfloat-helpers.h | 11 +++++++
12
1 file changed, 23 insertions(+), 3 deletions(-)
20
include/fpu/softfloat-types.h | 10 ++++++
21
fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++-------------
22
3 files changed, 54 insertions(+), 22 deletions(-)
13
23
14
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
24
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
15
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/vfp_helper.c
26
--- a/include/fpu/softfloat-helpers.h
17
+++ b/target/arm/vfp_helper.c
27
+++ b/include/fpu/softfloat-helpers.h
18
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
19
*/
29
status->float_infzeronan_rule = rule;
20
21
#include "qemu/osdep.h"
22
-#include "qemu/log.h"
23
#include "cpu.h"
24
#include "exec/helper-proto.h"
25
-#include "fpu/softfloat.h"
26
#include "internals.h"
27
-
28
+#ifdef CONFIG_TCG
29
+#include "qemu/log.h"
30
+#include "fpu/softfloat.h"
31
+#endif
32
33
/* VFP support. We follow the convention used for VFP instructions:
34
Single precision routines have a "s" suffix, double precision a
35
"d" suffix. */
36
37
+#ifdef CONFIG_TCG
38
+
39
/* Convert host exception flags to vfp form. */
40
static inline int vfp_exceptbits_from_host(int host_bits)
41
{
42
@@ -XXX,XX +XXX,XX @@ static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
43
set_float_exception_flags(0, &env->vfp.standard_fp_status);
44
}
30
}
45
31
46
+#else
32
+static inline void set_float_default_nan_pattern(uint8_t dnan_pattern,
47
+
33
+ float_status *status)
48
+static uint32_t vfp_get_fpscr_from_host(CPUARMState *env)
49
+{
34
+{
50
+ return 0;
35
+ status->default_nan_pattern = dnan_pattern;
51
+}
36
+}
52
+
37
+
53
+static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
38
static inline void set_flush_to_zero(bool val, float_status *status)
39
{
40
status->flush_to_zero = val;
41
@@ -XXX,XX +XXX,XX @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status
42
return status->float_infzeronan_rule;
43
}
44
45
+static inline uint8_t get_float_default_nan_pattern(float_status *status)
54
+{
46
+{
47
+ return status->default_nan_pattern;
55
+}
48
+}
56
+
49
+
57
+#endif
50
static inline bool get_flush_to_zero(float_status *status)
51
{
52
return status->flush_to_zero;
53
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
54
index XXXXXXX..XXXXXXX 100644
55
--- a/include/fpu/softfloat-types.h
56
+++ b/include/fpu/softfloat-types.h
57
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
58
/* should denormalised inputs go to zero and set the input_denormal flag? */
59
bool flush_inputs_to_zero;
60
bool default_nan_mode;
61
+ /*
62
+ * The pattern to use for the default NaN. Here the high bit specifies
63
+ * the default NaN's sign bit, and bits 6..0 specify the high bits of the
64
+ * fractional part. The low bits of the fractional part are copies of bit 0.
65
+ * The exponent of the default NaN is (as for any NaN) always all 1s.
66
+ * Note that a value of 0 here is not a valid NaN. The target must set
67
+ * this to the correct non-zero value, or we will assert when trying to
68
+ * create a default NaN.
69
+ */
70
+ uint8_t default_nan_pattern;
71
/*
72
* The flags below are not used on all specializations and may
73
* constant fold away (see snan_bit_is_one()/no_signalling_nans() in
74
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
75
index XXXXXXX..XXXXXXX 100644
76
--- a/fpu/softfloat-specialize.c.inc
77
+++ b/fpu/softfloat-specialize.c.inc
78
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
79
{
80
bool sign = 0;
81
uint64_t frac;
82
+ uint8_t dnan_pattern = status->default_nan_pattern;
83
84
+ if (dnan_pattern == 0) {
85
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
86
- /* !snan_bit_is_one, set all bits */
87
- frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
88
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
89
+ /* Sign bit clear, all frac bits set */
90
+ dnan_pattern = 0b01111111;
91
+#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
92
|| defined(TARGET_MICROBLAZE)
93
- /* !snan_bit_is_one, set sign and msb */
94
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
95
- sign = 1;
96
+ /* Sign bit set, most significant frac bit set */
97
+ dnan_pattern = 0b11000000;
98
#elif defined(TARGET_HPPA)
99
- /* snan_bit_is_one, set msb-1. */
100
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
101
+ /* Sign bit clear, msb-1 frac bit set */
102
+ dnan_pattern = 0b00100000;
103
#elif defined(TARGET_HEXAGON)
104
- sign = 1;
105
- frac = ~0ULL;
106
+ /* Sign bit set, all frac bits set. */
107
+ dnan_pattern = 0b11111111;
108
#else
109
- /*
110
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
111
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
112
- * do not have floating-point.
113
- */
114
- if (snan_bit_is_one(status)) {
115
- /* set all bits other than msb */
116
- frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
117
- } else {
118
- /* set msb */
119
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
120
- }
121
+ /*
122
+ * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
123
+ * S390, SH4, TriCore, and Xtensa. Our other supported targets
124
+ * do not have floating-point.
125
+ */
126
+ if (snan_bit_is_one(status)) {
127
+ /* sign bit clear, set all frac bits other than msb */
128
+ dnan_pattern = 0b00111111;
129
+ } else {
130
+ /* sign bit clear, set frac msb */
131
+ dnan_pattern = 0b01000000;
132
+ }
133
#endif
134
+ }
135
+ assert(dnan_pattern != 0);
58
+
136
+
59
uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
137
+ sign = dnan_pattern >> 7;
60
{
138
+ /*
61
uint32_t i, fpscr;
139
+ * Place default_nan_pattern [6:0] into bits [62:56],
62
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val)
140
+ * and replecate bit [0] down into [55:0]
63
HELPER(vfp_set_fpscr)(env, val);
141
+ */
64
}
142
+ frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern);
65
143
+ frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1));
66
+#ifdef CONFIG_TCG
144
67
+
145
*p = (FloatParts64) {
68
#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
146
.cls = float_class_qnan,
69
70
#define VFP_BINOP(name) \
71
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frint64_d)(float64 f, void *fpst)
72
{
73
return frint_d(f, fpst, 64);
74
}
75
+
76
+#endif
77
--
147
--
78
2.20.1
148
2.34.1
79
80
diff view generated by jsdifflib
New patch
[PULL 41/72] tests/fp: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the tests/fp code.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-36-peter.maydell@linaro.org
6
---
7
tests/fp/fp-bench.c | 1 +
8
tests/fp/fp-test-log2.c | 1 +
9
tests/fp/fp-test.c | 1 +
10
3 files changed, 3 insertions(+)
11
12
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tests/fp/fp-bench.c
15
+++ b/tests/fp/fp-bench.c
16
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
17
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
18
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
19
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
20
+ set_float_default_nan_pattern(0b01000000, &soft_status);
21
22
f = bench_funcs[operation][precision];
23
g_assert(f);
24
diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/tests/fp/fp-test-log2.c
27
+++ b/tests/fp/fp-test-log2.c
28
@@ -XXX,XX +XXX,XX @@ int main(int ac, char **av)
29
int i;
30
31
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
32
+ set_float_default_nan_pattern(0b01000000, &qsf);
33
set_float_rounding_mode(float_round_nearest_even, &qsf);
34
35
test.d = 0.0;
36
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/tests/fp/fp-test.c
39
+++ b/tests/fp/fp-test.c
40
@@ -XXX,XX +XXX,XX @@ void run_test(void)
41
*/
42
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
43
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
44
+ set_float_default_nan_pattern(0b01000000, &qsf);
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
46
47
genCases_setLevel(test_level);
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 42/72] target/microblaze: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-37-peter.maydell@linaro.org
7
---
8
target/microblaze/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/microblaze/cpu.c
15
+++ b/target/microblaze/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_reset_hold(Object *obj, ResetType type)
17
* this architecture.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
22
23
#if defined(CONFIG_USER_ONLY)
24
/* start in user mode with interrupts enabled. */
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
34
- || defined(TARGET_MICROBLAZE)
35
+#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
/* Sign bit set, most significant frac bit set */
37
dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 43/72] target/i386: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-38-peter.maydell@linaro.org
7
---
8
target/i386/tcg/fpu_helper.c | 4 ++++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 4 insertions(+), 3 deletions(-)
11
12
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/i386/tcg/fpu_helper.c
15
+++ b/target/i386/tcg/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
17
*/
18
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
19
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
22
+ set_float_default_nan_pattern(0b11000000, &env->mmx_status);
23
+ set_float_default_nan_pattern(0b11000000, &env->sse_status);
24
}
25
26
static inline uint8_t save_exception_flags(CPUX86State *env)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
32
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
/* Sign bit clear, all frac bits set */
34
dnan_pattern = 0b01111111;
35
-#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
- /* Sign bit set, most significant frac bit set */
37
- dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
/* Sign bit clear, msb-1 frac bit set */
40
dnan_pattern = 0b00100000;
41
--
42
2.34.1
diff view generated by jsdifflib
New patch
[PULL 44/72] target/hppa: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-39-peter.maydell@linaro.org
7
---
8
target/hppa/fpu_helper.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 2 insertions(+), 3 deletions(-)
11
12
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/hppa/fpu_helper.c
15
+++ b/target/hppa/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
17
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
18
/* For inf * 0 + NaN, return the input NaN */
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ /* Default NaN: sign bit clear, msb-1 frac bit set */
21
+ set_float_default_nan_pattern(0b00100000, &env->fp_status);
22
}
23
24
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_HPPA)
34
- /* Sign bit clear, msb-1 frac bit set */
35
- dnan_pattern = 0b00100000;
36
#elif defined(TARGET_HEXAGON)
37
/* Sign bit set, all frac bits set. */
38
dnan_pattern = 0b11111111;
39
--
40
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 31/46] target/arm: Makefile cleanup (softmmu)
[PULL 45/72] target/alpha: Set default NaN pattern explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the default NaN pattern explicitly for the alpha target.
2
2
3
Group SOFTMMU objects together.
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Since PSCI is TCG specific, keep it separate.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-40-peter.maydell@linaro.org
6
---
7
target/alpha/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
5
9
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20190701132516.26392-5-philmd@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/Makefile.objs | 5 ++++-
12
1 file changed, 4 insertions(+), 1 deletion(-)
13
14
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
15
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/Makefile.objs
12
--- a/target/alpha/cpu.c
17
+++ b/target/arm/Makefile.objs
13
+++ b/target/alpha/cpu.c
18
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_initfn(Object *obj)
19
obj-y += arm-semi.o
15
* operand in Fa. That is float_2nan_prop_ba.
20
-obj-$(CONFIG_SOFTMMU) += machine.o psci.o arch_dump.o monitor.o
16
*/
21
obj-y += helper.o vfp_helper.o
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
22
obj-y += cpu.o gdbstub.o
18
+ /* Default NaN: sign bit clear, msb frac bit set */
23
obj-$(TARGET_AARCH64) += cpu64.o gdbstub64.o
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
24
+
20
#if defined(CONFIG_USER_ONLY)
25
+obj-$(CONFIG_SOFTMMU) += machine.o arch_dump.o monitor.o
21
env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
26
obj-$(CONFIG_SOFTMMU) += arm-powerctl.o
22
cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD
27
28
obj-$(CONFIG_KVM) += kvm.o
29
@@ -XXX,XX +XXX,XX @@ obj-y += translate.o op_helper.o
30
obj-y += crypto_helper.o
31
obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
32
33
+obj-$(CONFIG_SOFTMMU) += psci.o
34
+
35
obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o
36
obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o
37
obj-$(TARGET_AARCH64) += pauth_helper.o
38
--
23
--
39
2.20.1
24
2.34.1
40
41
diff view generated by jsdifflib
[Qemu-devel] [PULL 40/46] target/arm/vfp_helper: Move code around
[PULL 46/72] target/arm: Set default NaN pattern explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the default NaN pattern explicitly for the arm target.
2
This includes setting it for the old linux-user nwfpe emulation.
3
For nwfpe, our default doesn't match the real kernel, but we
4
avoid making a behaviour change in this commit.
2
5
3
To ease the review of the next commit,
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
move the vfp_exceptbits_to_host() function directly after
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
vfp_exceptbits_from_host(). Amusingly the diff shows we
8
Message-id: 20241202131347.498124-41-peter.maydell@linaro.org
6
are moving vfp_get_fpscr().
9
---
10
linux-user/arm/nwfpe/fpa11.c | 5 +++++
11
target/arm/cpu.c | 2 ++
12
2 files changed, 7 insertions(+)
7
13
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c
9
Message-id: 20190701132516.26392-15-philmd@redhat.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/vfp_helper.c | 52 ++++++++++++++++++++---------------------
14
1 file changed, 26 insertions(+), 26 deletions(-)
15
16
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/vfp_helper.c
16
--- a/linux-user/arm/nwfpe/fpa11.c
19
+++ b/target/arm/vfp_helper.c
17
+++ b/linux-user/arm/nwfpe/fpa11.c
20
@@ -XXX,XX +XXX,XX @@ static inline int vfp_exceptbits_from_host(int host_bits)
18
@@ -XXX,XX +XXX,XX @@ void resetFPA11(void)
21
return target_bits;
19
* this late date.
20
*/
21
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status);
22
+ /*
23
+ * Use the same default NaN value as Arm VFP. This doesn't match
24
+ * the Linux kernel's nwfpe emulation, which uses an all-1s value.
25
+ */
26
+ set_float_default_nan_pattern(0b01000000, &fpa11->fp_status);
22
}
27
}
23
28
24
-uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
29
void SetRoundingMode(const unsigned int opcode)
25
-{
30
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
26
- uint32_t i, fpscr;
31
index XXXXXXX..XXXXXXX 100644
27
-
32
--- a/target/arm/cpu.c
28
- fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
33
+++ b/target/arm/cpu.c
29
- | (env->vfp.vec_len << 16)
34
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
30
- | (env->vfp.vec_stride << 20);
35
* the pseudocode function the arguments are in the order c, a, b.
31
-
36
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
32
- i = get_float_exception_flags(&env->vfp.fp_status);
37
* and the input NaN if it is signalling
33
- i |= get_float_exception_flags(&env->vfp.standard_fp_status);
38
+ * * Default NaN has sign bit clear, msb frac bit set
34
- /* FZ16 does not generate an input denormal exception. */
39
*/
35
- i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
40
static void arm_set_default_fp_behaviours(float_status *s)
36
- & ~float_flag_input_denormal);
37
- fpscr |= vfp_exceptbits_from_host(i);
38
-
39
- i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
40
- fpscr |= i ? FPCR_QC : 0;
41
-
42
- return fpscr;
43
-}
44
-
45
-uint32_t vfp_get_fpscr(CPUARMState *env)
46
-{
47
- return HELPER(vfp_get_fpscr)(env);
48
-}
49
-
50
/* Convert vfp exception flags to target form. */
51
static inline int vfp_exceptbits_to_host(int target_bits)
52
{
41
{
53
@@ -XXX,XX +XXX,XX @@ static inline int vfp_exceptbits_to_host(int target_bits)
42
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
54
return host_bits;
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
44
set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
46
+ set_float_default_nan_pattern(0b01000000, s);
55
}
47
}
56
48
57
+uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
49
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
58
+{
59
+ uint32_t i, fpscr;
60
+
61
+ fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
62
+ | (env->vfp.vec_len << 16)
63
+ | (env->vfp.vec_stride << 20);
64
+
65
+ i = get_float_exception_flags(&env->vfp.fp_status);
66
+ i |= get_float_exception_flags(&env->vfp.standard_fp_status);
67
+ /* FZ16 does not generate an input denormal exception. */
68
+ i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
69
+ & ~float_flag_input_denormal);
70
+ fpscr |= vfp_exceptbits_from_host(i);
71
+
72
+ i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
73
+ fpscr |= i ? FPCR_QC : 0;
74
+
75
+ return fpscr;
76
+}
77
+
78
+uint32_t vfp_get_fpscr(CPUARMState *env)
79
+{
80
+ return HELPER(vfp_get_fpscr)(env);
81
+}
82
+
83
void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
84
{
85
int i;
86
--
50
--
87
2.20.1
51
2.34.1
88
89
diff view generated by jsdifflib
[Qemu-devel] [PULL 30/46] target/arm: Makefile cleanup (KVM)
[PULL 47/72] target/loongarch: Set default NaN pattern explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the default NaN pattern explicitly for loongarch.
2
2
3
Group KVM rules together.
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-42-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 2 ++
8
1 file changed, 2 insertions(+)
4
9
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-id: 20190701132516.26392-4-philmd@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/Makefile.objs | 9 +++++----
11
1 file changed, 5 insertions(+), 4 deletions(-)
12
13
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
14
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/Makefile.objs
12
--- a/target/loongarch/tcg/fpu_helper.c
16
+++ b/target/arm/Makefile.objs
13
+++ b/target/loongarch/tcg/fpu_helper.c
17
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
18
obj-y += arm-semi.o
15
*/
19
obj-$(CONFIG_SOFTMMU) += machine.o psci.o arch_dump.o monitor.o
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
-obj-$(CONFIG_KVM) += kvm.o
17
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
21
-obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o
18
+ /* Default NaN: sign bit clear, msb frac bit set */
22
-obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
23
-obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
20
}
24
obj-y += helper.o vfp_helper.o
21
25
obj-y += cpu.o gdbstub.o
22
int ieee_ex_to_loongarch(int xcpt)
26
obj-$(TARGET_AARCH64) += cpu64.o gdbstub64.o
27
obj-$(CONFIG_SOFTMMU) += arm-powerctl.o
28
29
+obj-$(CONFIG_KVM) += kvm.o
30
+obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o
31
+obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o
32
+obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
33
+
34
DECODETREE = $(SRC_PATH)/scripts/decodetree.py
35
36
target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE)
37
--
23
--
38
2.20.1
24
2.34.1
39
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 29/46] target/arm: Makefile cleanup (ARM)
[PULL 48/72] target/m68k: Set default NaN pattern explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the default NaN pattern explicitly for m68k.
2
2
3
Group ARM objects together, TCG related ones at the bottom.
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
This will help when restricting TCG-only objects.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-43-peter.maydell@linaro.org
6
---
7
target/m68k/cpu.c | 2 ++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 3 insertions(+), 1 deletion(-)
5
10
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20190701132516.26392-3-philmd@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/Makefile.objs | 10 ++++++----
12
1 file changed, 6 insertions(+), 4 deletions(-)
13
14
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
15
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/Makefile.objs
13
--- a/target/m68k/cpu.c
17
+++ b/target/arm/Makefile.objs
14
+++ b/target/m68k/cpu.c
18
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_KVM) += kvm.o
15
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
19
obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o
16
* preceding paragraph for nonsignaling NaNs.
20
obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o
17
*/
21
obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
22
-obj-y += translate.o op_helper.o helper.o cpu.o
19
+ /* Default NaN: sign bit clear, all frac bits set */
23
-obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o vfp_helper.o
20
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
24
-obj-y += gdbstub.o
21
25
+obj-y += helper.o vfp_helper.o
22
nan = floatx80_default_nan(&env->fp_status);
26
+obj-y += cpu.o gdbstub.o
23
for (i = 0; i < 8; i++) {
27
obj-$(TARGET_AARCH64) += cpu64.o gdbstub64.o
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
-obj-y += crypto_helper.o
25
index XXXXXXX..XXXXXXX 100644
29
obj-$(CONFIG_SOFTMMU) += arm-powerctl.o
26
--- a/fpu/softfloat-specialize.c.inc
30
27
+++ b/fpu/softfloat-specialize.c.inc
31
DECODETREE = $(SRC_PATH)/scripts/decodetree.py
28
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
32
@@ -XXX,XX +XXX,XX @@ target/arm/translate-sve.o: target/arm/decode-sve.inc.c
29
uint8_t dnan_pattern = status->default_nan_pattern;
33
target/arm/translate.o: target/arm/decode-vfp.inc.c
30
34
target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
31
if (dnan_pattern == 0) {
35
32
-#if defined(TARGET_SPARC) || defined(TARGET_M68K)
36
+obj-y += translate.o op_helper.o
33
+#if defined(TARGET_SPARC)
37
+obj-y += crypto_helper.o
34
/* Sign bit clear, all frac bits set */
38
+obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
35
dnan_pattern = 0b01111111;
39
+
36
#elif defined(TARGET_HEXAGON)
40
obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o
41
obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o
42
obj-$(TARGET_AARCH64) += pauth_helper.o
43
--
37
--
44
2.20.1
38
2.34.1
45
46
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/46] aspeed: add a per SoC mapping for the memory space
[PULL 49/72] target/mips: Set default NaN pattern explicitly
1
From: Cédric Le Goater <clg@kaod.org>
1
Set the default NaN pattern explicitly for MIPS. Note that this
2
is our only target which currently changes the default NaN
3
at runtime (which it was previously doing indirectly when it
4
changed the snan_bit_is_one setting).
2
5
3
This will simplify the definition of new SoCs, like the AST2600 which
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
should use a slightly different address space and have a different set
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
of controllers.
8
Message-id: 20241202131347.498124-44-peter.maydell@linaro.org
9
---
10
target/mips/fpu_helper.h | 7 +++++++
11
target/mips/msa.c | 3 +++
12
2 files changed, 10 insertions(+)
6
13
7
Signed-off-by: Cédric Le Goater <clg@kaod.org>
14
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Joel Stanley <joel@jms.id.au>
10
Message-id: 20190618165311.27066-3-clg@kaod.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/hw/arm/aspeed_soc.h | 4 +-
14
hw/arm/aspeed.c | 8 +--
15
hw/arm/aspeed_soc.c | 117 ++++++++++++++++++++++--------------
16
3 files changed, 78 insertions(+), 51 deletions(-)
17
18
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/aspeed_soc.h
16
--- a/target/mips/fpu_helper.h
21
+++ b/include/hw/arm/aspeed_soc.h
17
+++ b/target/mips/fpu_helper.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCInfo {
18
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
23
const char *name;
19
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
24
const char *cpu_type;
20
nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
25
uint32_t silicon_rev;
21
set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
26
- hwaddr sdram_base;
22
+ /*
27
uint64_t sram_size;
23
+ * With nan2008, the default NaN value has the sign bit clear and the
28
int spis_num;
24
+ * frac msb set; with the older mode, the sign bit is clear, and all
29
- const hwaddr *spi_bases;
25
+ * frac bits except the msb are set.
30
const char *fmc_typename;
26
+ */
31
const char **spi_typename;
27
+ set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111,
32
int wdts_num;
28
+ &env->active_fpu.fp_status);
33
const int *irqmap;
29
34
+ const hwaddr *memmap;
30
}
35
} AspeedSoCInfo;
31
36
32
diff --git a/target/mips/msa.c b/target/mips/msa.c
37
typedef struct AspeedSoCClass {
38
@@ -XXX,XX +XXX,XX @@ enum {
39
ASPEED_I2C,
40
ASPEED_ETH1,
41
ASPEED_ETH2,
42
+ ASPEED_SDRAM,
43
};
44
45
#endif /* ASPEED_SOC_H */
46
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
47
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/aspeed.c
34
--- a/target/mips/msa.c
49
+++ b/hw/arm/aspeed.c
35
+++ b/target/mips/msa.c
50
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
36
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
51
&error_abort);
37
/* Inf * 0 + NaN returns the input NaN */
52
38
set_float_infzeronan_rule(float_infzeronan_dnan_never,
53
memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
39
&env->active_tc.msa_fp_status);
54
- memory_region_add_subregion(get_system_memory(), sc->info->sdram_base,
40
+ /* Default NaN: sign bit clear, frac msb set */
55
- &bmc->ram);
41
+ set_float_default_nan_pattern(0b01000000,
56
+ memory_region_add_subregion(get_system_memory(),
42
+ &env->active_tc.msa_fp_status);
57
+ sc->info->memmap[ASPEED_SDRAM], &bmc->ram);
58
object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
59
&error_abort);
60
61
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
62
memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
63
"max_ram", max_ram_size - ram_size);
64
memory_region_add_subregion(get_system_memory(),
65
- sc->info->sdram_base + ram_size,
66
+ sc->info->memmap[ASPEED_SDRAM] + ram_size,
67
&bmc->max_ram);
68
69
aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);
70
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
71
aspeed_board_binfo.initrd_filename = machine->initrd_filename;
72
aspeed_board_binfo.kernel_cmdline = machine->kernel_cmdline;
73
aspeed_board_binfo.ram_size = ram_size;
74
- aspeed_board_binfo.loader_start = sc->info->sdram_base;
75
+ aspeed_board_binfo.loader_start = sc->info->memmap[ASPEED_SDRAM];
76
77
if (cfg->i2c_init) {
78
cfg->i2c_init(bmc);
79
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/arm/aspeed_soc.c
82
+++ b/hw/arm/aspeed_soc.c
83
@@ -XXX,XX +XXX,XX @@
84
#include "hw/i2c/aspeed_i2c.h"
85
#include "net/net.h"
86
87
-#define ASPEED_SOC_UART_5_BASE 0x00184000
88
#define ASPEED_SOC_IOMEM_SIZE 0x00200000
89
-#define ASPEED_SOC_IOMEM_BASE 0x1E600000
90
-#define ASPEED_SOC_FMC_BASE 0x1E620000
91
-#define ASPEED_SOC_SPI_BASE 0x1E630000
92
-#define ASPEED_SOC_SPI2_BASE 0x1E631000
93
-#define ASPEED_SOC_VIC_BASE 0x1E6C0000
94
-#define ASPEED_SOC_SDMC_BASE 0x1E6E0000
95
-#define ASPEED_SOC_SCU_BASE 0x1E6E2000
96
-#define ASPEED_SOC_SRAM_BASE 0x1E720000
97
-#define ASPEED_SOC_TIMER_BASE 0x1E782000
98
-#define ASPEED_SOC_WDT_BASE 0x1E785000
99
-#define ASPEED_SOC_I2C_BASE 0x1E78A000
100
-#define ASPEED_SOC_ETH1_BASE 0x1E660000
101
-#define ASPEED_SOC_ETH2_BASE 0x1E680000
102
+
103
+static const hwaddr aspeed_soc_ast2400_memmap[] = {
104
+ [ASPEED_IOMEM] = 0x1E600000,
105
+ [ASPEED_FMC] = 0x1E620000,
106
+ [ASPEED_SPI1] = 0x1E630000,
107
+ [ASPEED_VIC] = 0x1E6C0000,
108
+ [ASPEED_SDMC] = 0x1E6E0000,
109
+ [ASPEED_SCU] = 0x1E6E2000,
110
+ [ASPEED_ADC] = 0x1E6E9000,
111
+ [ASPEED_SRAM] = 0x1E720000,
112
+ [ASPEED_GPIO] = 0x1E780000,
113
+ [ASPEED_RTC] = 0x1E781000,
114
+ [ASPEED_TIMER1] = 0x1E782000,
115
+ [ASPEED_WDT] = 0x1E785000,
116
+ [ASPEED_PWM] = 0x1E786000,
117
+ [ASPEED_LPC] = 0x1E789000,
118
+ [ASPEED_IBT] = 0x1E789140,
119
+ [ASPEED_I2C] = 0x1E78A000,
120
+ [ASPEED_ETH1] = 0x1E660000,
121
+ [ASPEED_ETH2] = 0x1E680000,
122
+ [ASPEED_UART1] = 0x1E783000,
123
+ [ASPEED_UART5] = 0x1E784000,
124
+ [ASPEED_VUART] = 0x1E787000,
125
+ [ASPEED_SDRAM] = 0x40000000,
126
+};
127
+
128
+static const hwaddr aspeed_soc_ast2500_memmap[] = {
129
+ [ASPEED_IOMEM] = 0x1E600000,
130
+ [ASPEED_FMC] = 0x1E620000,
131
+ [ASPEED_SPI1] = 0x1E630000,
132
+ [ASPEED_SPI2] = 0x1E631000,
133
+ [ASPEED_VIC] = 0x1E6C0000,
134
+ [ASPEED_SDMC] = 0x1E6E0000,
135
+ [ASPEED_SCU] = 0x1E6E2000,
136
+ [ASPEED_ADC] = 0x1E6E9000,
137
+ [ASPEED_SRAM] = 0x1E720000,
138
+ [ASPEED_GPIO] = 0x1E780000,
139
+ [ASPEED_RTC] = 0x1E781000,
140
+ [ASPEED_TIMER1] = 0x1E782000,
141
+ [ASPEED_WDT] = 0x1E785000,
142
+ [ASPEED_PWM] = 0x1E786000,
143
+ [ASPEED_LPC] = 0x1E789000,
144
+ [ASPEED_IBT] = 0x1E789140,
145
+ [ASPEED_I2C] = 0x1E78A000,
146
+ [ASPEED_ETH1] = 0x1E660000,
147
+ [ASPEED_ETH2] = 0x1E680000,
148
+ [ASPEED_UART1] = 0x1E783000,
149
+ [ASPEED_UART5] = 0x1E784000,
150
+ [ASPEED_VUART] = 0x1E787000,
151
+ [ASPEED_SDRAM] = 0x80000000,
152
+};
153
154
static const int aspeed_soc_ast2400_irqmap[] = {
155
[ASPEED_UART1] = 9,
156
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2400_irqmap[] = {
157
[ASPEED_ETH2] = 3,
158
};
159
160
-#define AST2400_SDRAM_BASE 0x40000000
161
-#define AST2500_SDRAM_BASE 0x80000000
162
-
163
-/* AST2500 uses the same IRQs as the AST2400 */
164
#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
165
166
-static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE };
167
static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
168
-
169
-static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE,
170
- ASPEED_SOC_SPI2_BASE};
171
static const char *aspeed_soc_ast2500_typenames[] = {
172
"aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
173
174
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
175
.name = "ast2400-a0",
176
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
177
.silicon_rev = AST2400_A0_SILICON_REV,
178
- .sdram_base = AST2400_SDRAM_BASE,
179
.sram_size = 0x8000,
180
.spis_num = 1,
181
- .spi_bases = aspeed_soc_ast2400_spi_bases,
182
.fmc_typename = "aspeed.smc.fmc",
183
.spi_typename = aspeed_soc_ast2400_typenames,
184
.wdts_num = 2,
185
.irqmap = aspeed_soc_ast2400_irqmap,
186
+ .memmap = aspeed_soc_ast2400_memmap,
187
}, {
188
.name = "ast2400-a1",
189
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
190
.silicon_rev = AST2400_A1_SILICON_REV,
191
- .sdram_base = AST2400_SDRAM_BASE,
192
.sram_size = 0x8000,
193
.spis_num = 1,
194
- .spi_bases = aspeed_soc_ast2400_spi_bases,
195
.fmc_typename = "aspeed.smc.fmc",
196
.spi_typename = aspeed_soc_ast2400_typenames,
197
.wdts_num = 2,
198
.irqmap = aspeed_soc_ast2400_irqmap,
199
+ .memmap = aspeed_soc_ast2400_memmap,
200
}, {
201
.name = "ast2400",
202
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
203
.silicon_rev = AST2400_A0_SILICON_REV,
204
- .sdram_base = AST2400_SDRAM_BASE,
205
.sram_size = 0x8000,
206
.spis_num = 1,
207
- .spi_bases = aspeed_soc_ast2400_spi_bases,
208
.fmc_typename = "aspeed.smc.fmc",
209
.spi_typename = aspeed_soc_ast2400_typenames,
210
.wdts_num = 2,
211
.irqmap = aspeed_soc_ast2400_irqmap,
212
+ .memmap = aspeed_soc_ast2400_memmap,
213
}, {
214
.name = "ast2500-a1",
215
.cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
216
.silicon_rev = AST2500_A1_SILICON_REV,
217
- .sdram_base = AST2500_SDRAM_BASE,
218
.sram_size = 0x9000,
219
.spis_num = 2,
220
- .spi_bases = aspeed_soc_ast2500_spi_bases,
221
.fmc_typename = "aspeed.smc.ast2500-fmc",
222
.spi_typename = aspeed_soc_ast2500_typenames,
223
.wdts_num = 3,
224
.irqmap = aspeed_soc_ast2500_irqmap,
225
+ .memmap = aspeed_soc_ast2500_memmap,
226
},
227
};
228
229
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
230
Error *err = NULL, *local_err = NULL;
231
232
/* IO space */
233
- create_unimplemented_device("aspeed_soc.io",
234
- ASPEED_SOC_IOMEM_BASE, ASPEED_SOC_IOMEM_SIZE);
235
+ create_unimplemented_device("aspeed_soc.io", sc->info->memmap[ASPEED_IOMEM],
236
+ ASPEED_SOC_IOMEM_SIZE);
237
238
/* CPU */
239
object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
240
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
241
error_propagate(errp, err);
242
return;
243
}
244
- memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE,
245
- &s->sram);
246
+ memory_region_add_subregion(get_system_memory(),
247
+ sc->info->memmap[ASPEED_SRAM], &s->sram);
248
249
/* SCU */
250
object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
251
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
252
error_propagate(errp, err);
253
return;
254
}
255
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);
256
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->info->memmap[ASPEED_SCU]);
257
258
/* VIC */
259
object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
260
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
261
error_propagate(errp, err);
262
return;
263
}
264
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE);
265
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->info->memmap[ASPEED_VIC]);
266
sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
267
qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
268
sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
269
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
270
error_propagate(errp, err);
271
return;
272
}
273
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
274
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
275
+ sc->info->memmap[ASPEED_TIMER1]);
276
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
277
qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
278
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
279
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
280
/* UART - attach an 8250 to the IO space as our UART5 */
281
if (serial_hd(0)) {
282
qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
283
- serial_mm_init(get_system_memory(),
284
- ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2,
285
+ serial_mm_init(get_system_memory(), sc->info->memmap[ASPEED_UART5], 2,
286
uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
287
}
288
289
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
290
error_propagate(errp, err);
291
return;
292
}
293
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
294
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->info->memmap[ASPEED_I2C]);
295
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
296
aspeed_soc_get_irq(s, ASPEED_I2C));
297
298
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
299
error_propagate(errp, err);
300
return;
301
}
302
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE);
303
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->info->memmap[ASPEED_FMC]);
304
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
305
s->fmc.ctrl->flash_window_base);
306
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
307
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
308
error_propagate(errp, err);
309
return;
310
}
311
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, sc->info->spi_bases[i]);
312
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
313
+ sc->info->memmap[ASPEED_SPI1 + i]);
314
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
315
s->spi[i].ctrl->flash_window_base);
316
}
317
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
318
error_propagate(errp, err);
319
return;
320
}
321
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
322
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->info->memmap[ASPEED_SDMC]);
323
324
/* Watch dog */
325
for (i = 0; i < sc->info->wdts_num; i++) {
326
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
327
return;
328
}
329
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
330
- ASPEED_SOC_WDT_BASE + i * 0x20);
331
+ sc->info->memmap[ASPEED_WDT] + i * 0x20);
332
}
333
334
/* Net */
335
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
336
error_propagate(errp, err);
337
return;
338
}
339
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, ASPEED_SOC_ETH1_BASE);
340
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0,
341
+ sc->info->memmap[ASPEED_ETH1]);
342
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
343
aspeed_soc_get_irq(s, ASPEED_ETH1));
344
}
43
}
345
--
44
--
346
2.20.1
45
2.34.1
347
348
diff view generated by jsdifflib
[Qemu-devel] [PULL 28/46] target/arm: Makefile cleanup (Aarch64)
[PULL 50/72] target/openrisc: Set default NaN pattern explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the default NaN pattern explicitly for openrisc.
2
2
3
Group Aarch64 rules together, TCG related ones at the bottom.
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
This will help when restricting TCG-only objects.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-45-peter.maydell@linaro.org
6
---
7
target/openrisc/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
5
9
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20190701132516.26392-2-philmd@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/Makefile.objs | 5 +++--
12
1 file changed, 3 insertions(+), 2 deletions(-)
13
14
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
15
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/Makefile.objs
12
--- a/target/openrisc/cpu.c
17
+++ b/target/arm/Makefile.objs
13
+++ b/target/openrisc/cpu.c
18
@@ -XXX,XX +XXX,XX @@ obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
14
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type)
19
obj-y += translate.o op_helper.o helper.o cpu.o
15
*/
20
obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o vfp_helper.o
16
set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status);
21
obj-y += gdbstub.o
17
22
-obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o
18
+ /* Default NaN: sign bit clear, frac msb set */
23
-obj-$(TARGET_AARCH64) += pauth_helper.o
19
+ set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status);
24
+obj-$(TARGET_AARCH64) += cpu64.o gdbstub64.o
20
25
obj-y += crypto_helper.o
21
#ifndef CONFIG_USER_ONLY
26
obj-$(CONFIG_SOFTMMU) += arm-powerctl.o
22
cpu->env.picmr = 0x00000000;
27
28
@@ -XXX,XX +XXX,XX @@ target/arm/translate-sve.o: target/arm/decode-sve.inc.c
29
target/arm/translate.o: target/arm/decode-vfp.inc.c
30
target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
31
32
+obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o
33
obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o
34
+obj-$(TARGET_AARCH64) += pauth_helper.o
35
--
23
--
36
2.20.1
24
2.34.1
37
38
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/46] aspeed/smc: add a 'sdram_base' property
[PULL 51/72] target/ppc: Set default NaN pattern explicitly
1
From: Cédric Le Goater <clg@kaod.org>
1
Set the default NaN pattern explicitly for ppc.
2
2
3
The DRAM address of a DMA transaction depends on the DRAM base address
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
of the SoC. Inform the SMC controller model with this value.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-46-peter.maydell@linaro.org
6
---
7
target/ppc/cpu_init.c | 4 ++++
8
1 file changed, 4 insertions(+)
5
9
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
10
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
7
Reviewed-by: Joel Stanley <joel@jms.id.au>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190618165311.27066-15-clg@kaod.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/ssi/aspeed_smc.h | 3 +++
13
hw/arm/aspeed_soc.c | 6 ++++++
14
hw/ssi/aspeed_smc.c | 1 +
15
3 files changed, 10 insertions(+)
16
17
diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
18
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/ssi/aspeed_smc.h
12
--- a/target/ppc/cpu_init.c
20
+++ b/include/hw/ssi/aspeed_smc.h
13
+++ b/target/ppc/cpu_init.c
21
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSMCState {
14
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
22
uint8_t r_timings;
15
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
23
uint8_t conf_enable_w0;
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
24
17
25
+ /* for DMA support */
18
+ /* Default NaN: sign bit clear, set frac msb */
26
+ uint64_t sdram_base;
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
+ set_float_default_nan_pattern(0b01000000, &env->vec_status);
27
+
21
+
28
AspeedSMCFlash *flashes;
22
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
29
23
ppc_spr_t *spr = &env->spr_cb[i];
30
uint8_t snoop_index;
31
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/aspeed_soc.c
34
+++ b/hw/arm/aspeed_soc.c
35
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
36
aspeed_soc_get_irq(s, ASPEED_I2C));
37
38
/* FMC, The number of CS is set at the board level */
39
+ object_property_set_int(OBJECT(&s->fmc), sc->info->memmap[ASPEED_SDRAM],
40
+ "sdram-base", &err);
41
+ if (err) {
42
+ error_propagate(errp, err);
43
+ return;
44
+ }
45
object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
46
if (err) {
47
error_propagate(errp, err);
48
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/ssi/aspeed_smc.c
51
+++ b/hw/ssi/aspeed_smc.c
52
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_smc = {
53
54
static Property aspeed_smc_properties[] = {
55
DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1),
56
+ DEFINE_PROP_UINT64("sdram-base", AspeedSMCState, sdram_base, 0),
57
DEFINE_PROP_END_OF_LIST(),
58
};
59
24
60
--
25
--
61
2.20.1
26
2.34.1
62
63
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/46] aspeed: add a RAM memory region container
[PULL 52/72] target/sh4: Set default NaN pattern explicitly
1
From: Cédric Le Goater <clg@kaod.org>
1
Set the default NaN pattern explicitly for sh4. Note that sh4
2
is one of the only three targets (the others being HPPA and
3
sometimes MIPS) that has snan_bit_is_one set.
2
4
3
The RAM memory region is defined after the SoC is realized when the
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
SDMC controller has checked that the defined RAM size for the machine
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
is correct. This is problematic for controller models requiring a link
7
Message-id: 20241202131347.498124-47-peter.maydell@linaro.org
6
on the RAM region, for DMA support in the SMC controller for instance.
8
---
9
target/sh4/cpu.c | 2 ++
10
1 file changed, 2 insertions(+)
7
11
8
Introduce a container memory region for the RAM that we can link into
12
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
9
the controllers early, before the SoC is realized. It will be
10
populated with the RAM region after the checks have be done.
11
12
Signed-off-by: Cédric Le Goater <clg@kaod.org>
13
Reviewed-by: Joel Stanley <joel@jms.id.au>
14
Message-id: 20190618165311.27066-14-clg@kaod.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/arm/aspeed.c | 13 +++++++++----
18
1 file changed, 9 insertions(+), 4 deletions(-)
19
20
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
21
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/aspeed.c
14
--- a/target/sh4/cpu.c
23
+++ b/hw/arm/aspeed.c
15
+++ b/target/sh4/cpu.c
24
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info aspeed_board_binfo = {
16
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)
25
17
set_flush_to_zero(1, &env->fp_status);
26
struct AspeedBoardState {
18
#endif
27
AspeedSoCState soc;
19
set_default_nan_mode(1, &env->fp_status);
28
+ MemoryRegion ram_container;
20
+ /* sign bit clear, set all frac bits other than msb */
29
MemoryRegion ram;
21
+ set_float_default_nan_pattern(0b00111111, &env->fp_status);
30
MemoryRegion max_ram;
22
}
31
};
23
32
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
24
static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
33
ram_addr_t max_ram_size;
34
35
bmc = g_new0(AspeedBoardState, 1);
36
+
37
+ memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container",
38
+ UINT32_MAX);
39
+
40
object_initialize_child(OBJECT(machine), "soc", &bmc->soc,
41
(sizeof(bmc->soc)), cfg->soc_name, &error_abort,
42
NULL);
43
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
44
&error_abort);
45
46
memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
47
+ memory_region_add_subregion(&bmc->ram_container, 0, &bmc->ram);
48
memory_region_add_subregion(get_system_memory(),
49
- sc->info->memmap[ASPEED_SDRAM], &bmc->ram);
50
+ sc->info->memmap[ASPEED_SDRAM],
51
+ &bmc->ram_container);
52
53
max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
54
&error_abort);
55
memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
56
"max_ram", max_ram_size - ram_size);
57
- memory_region_add_subregion(get_system_memory(),
58
- sc->info->memmap[ASPEED_SDRAM] + ram_size,
59
- &bmc->max_ram);
60
+ memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_ram);
61
62
aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);
63
aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort);
64
--
25
--
65
2.20.1
26
2.34.1
66
67
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/46] aspeed: remove the "ram" link
[PULL 53/72] target/rx: Set default NaN pattern explicitly
1
From: Cédric Le Goater <clg@kaod.org>
1
Set the default NaN pattern explicitly for rx.
2
2
3
It has never been used as far as I can tell from the git history.
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-48-peter.maydell@linaro.org
6
---
7
target/rx/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
4
9
5
Signed-off-by: Cédric Le Goater <clg@kaod.org>
10
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
6
Reviewed-by: Joel Stanley <joel@jms.id.au>
7
Message-id: 20190618165311.27066-13-clg@kaod.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/arm/aspeed.c | 2 --
11
1 file changed, 2 deletions(-)
12
13
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
14
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/aspeed.c
12
--- a/target/rx/cpu.c
16
+++ b/hw/arm/aspeed.c
13
+++ b/target/rx/cpu.c
17
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
14
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_reset_hold(Object *obj, ResetType type)
18
memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
15
* then prefer dest over source", which is float_2nan_prop_s_ab.
19
memory_region_add_subregion(get_system_memory(),
16
*/
20
sc->info->memmap[ASPEED_SDRAM], &bmc->ram);
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
21
- object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
18
+ /* Default NaN value: sign bit clear, set frac msb */
22
- &error_abort);
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
23
20
}
24
max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
21
25
&error_abort);
22
static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
26
--
23
--
27
2.20.1
24
2.34.1
28
29
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/46] pci: designware: Update MSI mapping when MSI address changes
[PULL 54/72] target/s390x: Set default NaN pattern explicitly
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
Set the default NaN pattern explicitly for s390x.
2
2
3
MSI mapping needs to be update when MSI address changes, so add the
4
code to do so.
5
6
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
7
Cc: Peter Maydell <peter.maydell@linaro.org>
8
Cc: Michael S. Tsirkin <mst@redhat.com>
9
Cc: qemu-devel@nongnu.org
10
Cc: qemu-arm@nongnu.org
11
Acked-by: Michael S. Tsirkin <mst@redhat.com>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-49-peter.maydell@linaro.org
14
---
6
---
15
hw/pci-host/designware.c | 2 ++
7
target/s390x/cpu.c | 2 ++
16
1 file changed, 2 insertions(+)
8
1 file changed, 2 insertions(+)
17
9
18
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
10
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
19
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/pci-host/designware.c
12
--- a/target/s390x/cpu.c
21
+++ b/hw/pci-host/designware.c
13
+++ b/target/s390x/cpu.c
22
@@ -XXX,XX +XXX,XX @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
14
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
23
case DESIGNWARE_PCIE_MSI_ADDR_LO:
15
set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
24
root->msi.base &= 0xFFFFFFFF00000000ULL;
16
set_float_infzeronan_rule(float_infzeronan_dnan_always,
25
root->msi.base |= val;
17
&env->fpu_status);
26
+ designware_pcie_root_update_msi_mapping(root);
18
+ /* Default NaN value: sign bit clear, frac msb set */
27
break;
19
+ set_float_default_nan_pattern(0b01000000, &env->fpu_status);
28
20
/* fall through */
29
case DESIGNWARE_PCIE_MSI_ADDR_HI:
21
case RESET_TYPE_S390_CPU_NORMAL:
30
root->msi.base &= 0x00000000FFFFFFFFULL;
22
env->psw.mask &= ~PSW_MASK_RI;
31
root->msi.base |= (uint64_t)val << 32;
32
+ designware_pcie_root_update_msi_mapping(root);
33
break;
34
35
case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
36
--
23
--
37
2.20.1
24
2.34.1
38
39
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/46] aspeed/timer: Status register contains reload for stopped timer
[PULL 55/72] target/sparc: Set default NaN pattern explicitly
1
From: Andrew Jeffery <andrew@aj.id.au>
1
Set the default NaN pattern explicitly for SPARC, and remove
2
the ifdef from parts64_default_nan.
2
3
3
From the datasheet:
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-50-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 5 +----
10
2 files changed, 3 insertions(+), 4 deletions(-)
4
11
5
This register stores the current status of counter #N. When timer
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
6
enable bit TMC30[N * b] is disabled, the reload register will be
7
loaded into this counter. When timer bit TMC30[N * b] is set, the
8
counter will start to decrement. CPU can update this register value
9
when enable bit is set.
10
11
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
12
Signed-off-by: Cédric Le Goater <clg@kaod.org>
13
Reviewed-by: Joel Stanley <joel@jms.id.au>
14
Message-id: 20190618165311.27066-9-clg@kaod.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/timer/aspeed_timer.c | 6 +++++-
18
1 file changed, 5 insertions(+), 1 deletion(-)
19
20
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
21
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/timer/aspeed_timer.c
14
--- a/target/sparc/cpu.c
23
+++ b/hw/timer/aspeed_timer.c
15
+++ b/target/sparc/cpu.c
24
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_timer_get_value(AspeedTimer *t, int reg)
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
25
17
set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
26
switch (reg) {
18
/* For inf * 0 + NaN, return the input NaN */
27
case TIMER_REG_STATUS:
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
28
- value = calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
20
+ /* Default NaN value: sign bit clear, all frac bits set */
29
+ if (timer_enabled(t)) {
21
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
30
+ value = calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
22
31
+ } else {
23
cpu_exec_realizefn(cs, &local_err);
32
+ value = t->reload;
24
if (local_err != NULL) {
33
+ }
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
34
break;
26
index XXXXXXX..XXXXXXX 100644
35
case TIMER_REG_RELOAD:
27
--- a/fpu/softfloat-specialize.c.inc
36
value = t->reload;
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
uint8_t dnan_pattern = status->default_nan_pattern;
31
32
if (dnan_pattern == 0) {
33
-#if defined(TARGET_SPARC)
34
- /* Sign bit clear, all frac bits set */
35
- dnan_pattern = 0b01111111;
36
-#elif defined(TARGET_HEXAGON)
37
+#if defined(TARGET_HEXAGON)
38
/* Sign bit set, all frac bits set. */
39
dnan_pattern = 0b11111111;
40
#else
37
--
41
--
38
2.20.1
42
2.34.1
39
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/46] aspeed: add a per SoC mapping for the interrupt space
[PULL 56/72] target/xtensa: Set default NaN pattern explicitly
1
From: Cédric Le Goater <clg@kaod.org>
1
Set the default NaN pattern explicitly for xtensa.
2
2
3
This will simplify the definition of new SoCs, like the AST2600 which
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
should use a different CPU and a different IRQ number layout.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-51-peter.maydell@linaro.org
6
---
7
target/xtensa/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
5
9
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
10
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Joel Stanley <joel@jms.id.au>
9
Message-id: 20190618165311.27066-2-clg@kaod.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/arm/aspeed_soc.h | 36 +++++++++++++++++++++++
13
hw/arm/aspeed_soc.c | 57 +++++++++++++++++++++++++++++++------
14
2 files changed, 85 insertions(+), 8 deletions(-)
15
16
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
17
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/aspeed_soc.h
12
--- a/target/xtensa/cpu.c
19
+++ b/include/hw/arm/aspeed_soc.h
13
+++ b/target/xtensa/cpu.c
20
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCInfo {
14
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
21
const char *fmc_typename;
15
/* For inf * 0 + NaN, return the input NaN */
22
const char **spi_typename;
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
23
int wdts_num;
17
set_no_signaling_nans(!dfpu, &env->fp_status);
24
+ const int *irqmap;
18
+ /* Default NaN value: sign bit clear, set frac msb */
25
} AspeedSoCInfo;
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
26
20
xtensa_use_first_nan(env, !dfpu);
27
typedef struct AspeedSoCClass {
28
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCClass {
29
#define ASPEED_SOC_GET_CLASS(obj) \
30
OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
31
32
+enum {
33
+ ASPEED_IOMEM,
34
+ ASPEED_UART1,
35
+ ASPEED_UART2,
36
+ ASPEED_UART3,
37
+ ASPEED_UART4,
38
+ ASPEED_UART5,
39
+ ASPEED_VUART,
40
+ ASPEED_FMC,
41
+ ASPEED_SPI1,
42
+ ASPEED_SPI2,
43
+ ASPEED_VIC,
44
+ ASPEED_SDMC,
45
+ ASPEED_SCU,
46
+ ASPEED_ADC,
47
+ ASPEED_SRAM,
48
+ ASPEED_GPIO,
49
+ ASPEED_RTC,
50
+ ASPEED_TIMER1,
51
+ ASPEED_TIMER2,
52
+ ASPEED_TIMER3,
53
+ ASPEED_TIMER4,
54
+ ASPEED_TIMER5,
55
+ ASPEED_TIMER6,
56
+ ASPEED_TIMER7,
57
+ ASPEED_TIMER8,
58
+ ASPEED_WDT,
59
+ ASPEED_PWM,
60
+ ASPEED_LPC,
61
+ ASPEED_IBT,
62
+ ASPEED_I2C,
63
+ ASPEED_ETH1,
64
+ ASPEED_ETH2,
65
+};
66
+
67
#endif /* ASPEED_SOC_H */
68
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/arm/aspeed_soc.c
71
+++ b/hw/arm/aspeed_soc.c
72
@@ -XXX,XX +XXX,XX @@
73
#define ASPEED_SOC_ETH1_BASE 0x1E660000
74
#define ASPEED_SOC_ETH2_BASE 0x1E680000
75
76
-static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
77
-static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
78
+static const int aspeed_soc_ast2400_irqmap[] = {
79
+ [ASPEED_UART1] = 9,
80
+ [ASPEED_UART2] = 32,
81
+ [ASPEED_UART3] = 33,
82
+ [ASPEED_UART4] = 34,
83
+ [ASPEED_UART5] = 10,
84
+ [ASPEED_VUART] = 8,
85
+ [ASPEED_FMC] = 19,
86
+ [ASPEED_SDMC] = 0,
87
+ [ASPEED_SCU] = 21,
88
+ [ASPEED_ADC] = 31,
89
+ [ASPEED_GPIO] = 20,
90
+ [ASPEED_RTC] = 22,
91
+ [ASPEED_TIMER1] = 16,
92
+ [ASPEED_TIMER2] = 17,
93
+ [ASPEED_TIMER3] = 18,
94
+ [ASPEED_TIMER4] = 35,
95
+ [ASPEED_TIMER5] = 36,
96
+ [ASPEED_TIMER6] = 37,
97
+ [ASPEED_TIMER7] = 38,
98
+ [ASPEED_TIMER8] = 39,
99
+ [ASPEED_WDT] = 27,
100
+ [ASPEED_PWM] = 28,
101
+ [ASPEED_LPC] = 8,
102
+ [ASPEED_IBT] = 8, /* LPC */
103
+ [ASPEED_I2C] = 12,
104
+ [ASPEED_ETH1] = 2,
105
+ [ASPEED_ETH2] = 3,
106
+};
107
108
#define AST2400_SDRAM_BASE 0x40000000
109
#define AST2500_SDRAM_BASE 0x80000000
110
111
+/* AST2500 uses the same IRQs as the AST2400 */
112
+#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
113
+
114
static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE };
115
static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
116
117
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
118
.fmc_typename = "aspeed.smc.fmc",
119
.spi_typename = aspeed_soc_ast2400_typenames,
120
.wdts_num = 2,
121
+ .irqmap = aspeed_soc_ast2400_irqmap,
122
}, {
123
.name = "ast2400-a1",
124
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
125
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
126
.fmc_typename = "aspeed.smc.fmc",
127
.spi_typename = aspeed_soc_ast2400_typenames,
128
.wdts_num = 2,
129
+ .irqmap = aspeed_soc_ast2400_irqmap,
130
}, {
131
.name = "ast2400",
132
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
133
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
134
.fmc_typename = "aspeed.smc.fmc",
135
.spi_typename = aspeed_soc_ast2400_typenames,
136
.wdts_num = 2,
137
+ .irqmap = aspeed_soc_ast2400_irqmap,
138
}, {
139
.name = "ast2500-a1",
140
.cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
141
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
142
.fmc_typename = "aspeed.smc.ast2500-fmc",
143
.spi_typename = aspeed_soc_ast2500_typenames,
144
.wdts_num = 3,
145
+ .irqmap = aspeed_soc_ast2500_irqmap,
146
},
147
};
148
149
+static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
150
+{
151
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
152
+
153
+ return qdev_get_gpio_in(DEVICE(&s->vic), sc->info->irqmap[ctrl]);
154
+}
155
+
156
static void aspeed_soc_init(Object *obj)
157
{
158
AspeedSoCState *s = ASPEED_SOC(obj);
159
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
160
return;
161
}
162
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
163
- for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
164
- qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
165
+ for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
166
+ qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
167
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
168
}
169
170
/* UART - attach an 8250 to the IO space as our UART5 */
171
if (serial_hd(0)) {
172
- qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
173
+ qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
174
serial_mm_init(get_system_memory(),
175
ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2,
176
uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
177
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
178
}
179
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
180
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
181
- qdev_get_gpio_in(DEVICE(&s->vic), 12));
182
+ aspeed_soc_get_irq(s, ASPEED_I2C));
183
184
/* FMC, The number of CS is set at the board level */
185
object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
186
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
187
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
188
s->fmc.ctrl->flash_window_base);
189
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
190
- qdev_get_gpio_in(DEVICE(&s->vic), 19));
191
+ aspeed_soc_get_irq(s, ASPEED_FMC));
192
193
/* SPI */
194
for (i = 0; i < sc->info->spis_num; i++) {
195
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
196
}
197
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, ASPEED_SOC_ETH1_BASE);
198
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
199
- qdev_get_gpio_in(DEVICE(&s->vic), 2));
200
+ aspeed_soc_get_irq(s, ASPEED_ETH1));
201
}
21
}
202
22
203
static void aspeed_soc_class_init(ObjectClass *oc, void *data)
204
--
23
--
205
2.20.1
24
2.34.1
206
207
diff view generated by jsdifflib
[Qemu-devel] [PULL 22/46] aspeed: Add support for the swift-bmc board
[PULL 57/72] target/hexagon: Set default NaN pattern explicitly
1
From: Adriana Kobylak <anoo@us.ibm.com>
1
Set the default NaN pattern explicitly for hexagon.
2
Remove the ifdef from parts64_default_nan(); the only
3
remaining unconverted targets all use the default case.
2
4
3
The Swift board is an OpenPOWER system hosting POWER processors.
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Add support for their BMC including the I2C devices as found on HW.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-52-peter.maydell@linaro.org
8
---
9
target/hexagon/cpu.c | 2 ++
10
fpu/softfloat-specialize.c.inc | 5 -----
11
2 files changed, 2 insertions(+), 5 deletions(-)
5
12
6
Signed-off-by: Adriana Kobylak <anoo@us.ibm.com>
13
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Reviewed-by: Joel Stanley <joel@jms.id.au>
9
Message-id: 20190618165311.27066-20-clg@kaod.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/aspeed.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++++
13
1 file changed, 50 insertions(+)
14
15
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
16
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/aspeed.c
15
--- a/target/hexagon/cpu.c
18
+++ b/hw/arm/aspeed.c
16
+++ b/target/hexagon/cpu.c
19
@@ -XXX,XX +XXX,XX @@ struct AspeedBoardState {
17
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
20
SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
18
21
SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
19
set_default_nan_mode(1, &env->fp_status);
22
20
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
23
+/* Swift hardware value: 0xF11AD206 */
21
+ /* Default NaN value: sign bit set, all frac bits set */
24
+#define SWIFT_BMC_HW_STRAP1 ( \
22
+ set_float_default_nan_pattern(0b11111111, &env->fp_status);
25
+ AST2500_HW_STRAP1_DEFAULTS | \
26
+ SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
27
+ SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
28
+ SCU_AST2500_HW_STRAP_UART_DEBUG | \
29
+ SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
30
+ SCU_H_PLL_BYPASS_EN | \
31
+ SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
32
+ SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
33
+
34
/* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
35
#define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
36
37
@@ -XXX,XX +XXX,XX @@ static void romulus_bmc_i2c_init(AspeedBoardState *bmc)
38
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
39
}
23
}
40
24
41
+static void swift_bmc_i2c_init(AspeedBoardState *bmc)
25
static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
42
+{
26
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
43
+ AspeedSoCState *soc = &bmc->soc;
27
index XXXXXXX..XXXXXXX 100644
44
+
28
--- a/fpu/softfloat-specialize.c.inc
45
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), "pca9552", 0x60);
29
+++ b/fpu/softfloat-specialize.c.inc
46
+
30
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
47
+ /* The swift board expects a TMP275 but a TMP105 is compatible */
31
uint8_t dnan_pattern = status->default_nan_pattern;
48
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x48);
32
49
+ /* The swift board expects a pca9551 but a pca9552 is compatible */
33
if (dnan_pattern == 0) {
50
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "pca9552", 0x60);
34
-#if defined(TARGET_HEXAGON)
51
+
35
- /* Sign bit set, all frac bits set. */
52
+ /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */
36
- dnan_pattern = 0b11111111;
53
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "ds1338", 0x32);
37
-#else
54
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x60);
38
/*
55
+
39
* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
56
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "tmp423", 0x4c);
40
* S390, SH4, TriCore, and Xtensa. Our other supported targets
57
+ /* The swift board expects a pca9539 but a pca9552 is compatible */
41
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
58
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "pca9552", 0x74);
42
/* sign bit clear, set frac msb */
59
+
43
dnan_pattern = 0b01000000;
60
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "tmp423", 0x4c);
44
}
61
+ /* The swift board expects a pca9539 but a pca9552 is compatible */
45
-#endif
62
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "pca9552",
46
}
63
+ 0x74);
47
assert(dnan_pattern != 0);
64
+
48
65
+ /* The swift board expects a TMP275 but a TMP105 is compatible */
66
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x48);
67
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x4a);
68
+}
69
+
70
static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
71
{
72
AspeedSoCState *soc = &bmc->soc;
73
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
74
.num_cs = 2,
75
.i2c_init = romulus_bmc_i2c_init,
76
.ram = 512 * MiB,
77
+ }, {
78
+ .name = MACHINE_TYPE_NAME("swift-bmc"),
79
+ .desc = "OpenPOWER Swift BMC (ARM1176)",
80
+ .soc_name = "ast2500-a1",
81
+ .hw_strap1 = SWIFT_BMC_HW_STRAP1,
82
+ .fmc_model = "mx66l1g45g",
83
+ .spi_model = "mx66l1g45g",
84
+ .num_cs = 2,
85
+ .i2c_init = swift_bmc_i2c_init,
86
+ .ram = 512 * MiB,
87
}, {
88
.name = MACHINE_TYPE_NAME("witherspoon-bmc"),
89
.desc = "OpenPOWER Witherspoon BMC (ARM1176)",
90
--
49
--
91
2.20.1
50
2.34.1
92
93
diff view generated by jsdifflib
[Qemu-devel] [PULL 38/46] target/arm: Declare get_phys_addr() function publicly
[PULL 58/72] target/riscv: Set default NaN pattern explicitly
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Set the default NaN pattern explicitly for riscv.
2
2
3
In the next commit we will split the TLB related routines of
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
this file, and this function will also be called in the new
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
file. Declare it in the "internals.h" header.
5
Message-id: 20241202131347.498124-53-peter.maydell@linaro.org
6
---
7
target/riscv/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
6
9
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
8
Message-id: 20190701132516.26392-12-philmd@redhat.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/internals.h | 16 ++++++++++++++++
13
target/arm/helper.c | 21 +++++----------------
14
2 files changed, 21 insertions(+), 16 deletions(-)
15
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
17
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/internals.h
12
--- a/target/riscv/cpu.c
19
+++ b/target/arm/internals.h
13
+++ b/target/riscv/cpu.c
20
@@ -XXX,XX +XXX,XX @@ static inline int exception_target_el(CPUARMState *env)
14
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
21
return target_el;
15
cs->exception_index = RISCV_EXCP_NONE;
22
}
16
env->load_res = -1;
23
17
set_default_nan_mode(1, &env->fp_status);
24
+#ifndef CONFIG_USER_ONLY
18
+ /* Default NaN value: sign bit clear, frac msb set */
25
+
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
26
+/* Cacheability and shareability attributes for a memory access */
20
env->vill = true;
27
+typedef struct ARMCacheAttrs {
28
+ unsigned int attrs:8; /* as in the MAIR register encoding */
29
+ unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */
30
+} ARMCacheAttrs;
31
+
32
+bool get_phys_addr(CPUARMState *env, target_ulong address,
33
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
34
+ hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
35
+ target_ulong *page_size,
36
+ ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
37
+
38
+#endif /* !CONFIG_USER_ONLY */
39
+
40
#endif
41
diff --git a/target/arm/helper.c b/target/arm/helper.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/helper.c
44
+++ b/target/arm/helper.c
45
@@ -XXX,XX +XXX,XX @@
46
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
47
21
48
#ifndef CONFIG_USER_ONLY
22
#ifndef CONFIG_USER_ONLY
49
-/* Cacheability and shareability attributes for a memory access */
50
-typedef struct ARMCacheAttrs {
51
- unsigned int attrs:8; /* as in the MAIR register encoding */
52
- unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */
53
-} ARMCacheAttrs;
54
-
55
-static bool get_phys_addr(CPUARMState *env, target_ulong address,
56
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
57
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
58
- target_ulong *page_size,
59
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
60
61
static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
62
MMUAccessType access_type, ARMMMUIdx mmu_idx,
63
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2)
64
* @fi: set to fault info if the translation fails
65
* @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
66
*/
67
-static bool get_phys_addr(CPUARMState *env, target_ulong address,
68
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
69
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
70
- target_ulong *page_size,
71
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
72
+bool get_phys_addr(CPUARMState *env, target_ulong address,
73
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
74
+ hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
75
+ target_ulong *page_size,
76
+ ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
77
{
78
if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
79
/* Call ourselves recursively to do the stage 1 and then stage 2
80
--
23
--
81
2.20.1
24
2.34.1
82
83
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/46] i.mx7d: Add no-op/unimplemented PCIE PHY IP block
[PULL 59/72] target/tricore: Set default NaN pattern explicitly
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
Set the default NaN pattern explicitly for tricore.
2
2
3
Add no-op/unimplemented PCIE PHY IP block. Needed by new kernels to
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
use PCIE.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-54-peter.maydell@linaro.org
6
---
7
target/tricore/helper.c | 2 ++
8
1 file changed, 2 insertions(+)
5
9
6
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
10
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
7
Cc: Peter Maydell <peter.maydell@linaro.org>
8
Cc: Michael S. Tsirkin <mst@redhat.com>
9
Cc: qemu-devel@nongnu.org
10
Cc: qemu-arm@nongnu.org
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
include/hw/arm/fsl-imx7.h | 3 +++
15
hw/arm/fsl-imx7.c | 5 +++++
16
2 files changed, 8 insertions(+)
17
18
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
19
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/fsl-imx7.h
12
--- a/target/tricore/helper.c
21
+++ b/include/hw/arm/fsl-imx7.h
13
+++ b/target/tricore/helper.c
22
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
14
@@ -XXX,XX +XXX,XX @@ void fpu_set_state(CPUTriCoreState *env)
23
FSL_IMX7_ADC2_ADDR = 0x30620000,
15
set_flush_to_zero(1, &env->fp_status);
24
FSL_IMX7_ADCn_SIZE = 0x1000,
16
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
25
17
set_default_nan_mode(1, &env->fp_status);
26
+ FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000,
18
+ /* Default NaN pattern: sign bit clear, frac msb set */
27
+ FSL_IMX7_PCIE_PHY_SIZE = 0x10000,
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
28
+
29
FSL_IMX7_GPC_ADDR = 0x303A0000,
30
31
FSL_IMX7_I2C1_ADDR = 0x30A20000,
32
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/fsl-imx7.c
35
+++ b/hw/arm/fsl-imx7.c
36
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
37
*/
38
create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR,
39
FSL_IMX7_DMA_APBH_SIZE);
40
+ /*
41
+ * PCIe PHY
42
+ */
43
+ create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
44
+ FSL_IMX7_PCIE_PHY_SIZE);
45
}
20
}
46
21
47
static void fsl_imx7_class_init(ObjectClass *oc, void *data)
22
uint32_t psw_read(CPUTriCoreState *env)
48
--
23
--
49
2.20.1
24
2.34.1
50
51
diff view generated by jsdifflib
[Qemu-devel] [PULL 36/46] target/arm: Move the DC ZVA helper into op_helper
[PULL 60/72] fpu: Remove default handling for dnan_pattern
1
From: Samuel Ortiz <sameo@linux.intel.com>
1
Now that all our targets have bene converted to explicitly specify
2
their pattern for the default NaN value we can remove the remaining
3
fallback code in parts64_default_nan().
2
4
3
Those helpers are a software implementation of the ARM v8 memory zeroing
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
op code. They should be moved to the op helper file, which is going to
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
eventually be built only when TCG is enabled.
7
Message-id: 20241202131347.498124-55-peter.maydell@linaro.org
8
---
9
fpu/softfloat-specialize.c.inc | 14 --------------
10
1 file changed, 14 deletions(-)
6
11
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
8
Reviewed-by: Robert Bradford <robert.bradford@intel.com>
9
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20190701132516.26392-10-philmd@redhat.com
13
[PMD: Rebased]
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
target/arm/helper.c | 92 -----------------------------------------
19
target/arm/op_helper.c | 93 ++++++++++++++++++++++++++++++++++++++++++
20
2 files changed, 93 insertions(+), 92 deletions(-)
21
22
diff --git a/target/arm/helper.c b/target/arm/helper.c
23
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/helper.c
14
--- a/fpu/softfloat-specialize.c.inc
25
+++ b/target/arm/helper.c
15
+++ b/fpu/softfloat-specialize.c.inc
26
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
16
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
27
#endif
17
uint64_t frac;
28
}
18
uint8_t dnan_pattern = status->default_nan_pattern;
29
19
30
-void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
20
- if (dnan_pattern == 0) {
31
-{
32
- /*
33
- * Implement DC ZVA, which zeroes a fixed-length block of memory.
34
- * Note that we do not implement the (architecturally mandated)
35
- * alignment fault for attempts to use this on Device memory
36
- * (which matches the usual QEMU behaviour of not implementing either
37
- * alignment faults or any memory attribute handling).
38
- */
39
-
40
- ARMCPU *cpu = env_archcpu(env);
41
- uint64_t blocklen = 4 << cpu->dcz_blocksize;
42
- uint64_t vaddr = vaddr_in & ~(blocklen - 1);
43
-
44
-#ifndef CONFIG_USER_ONLY
45
- {
46
- /*
21
- /*
47
- * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
22
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
48
- * the block size so we might have to do more than one TLB lookup.
23
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
49
- * We know that in fact for any v8 CPU the page size is at least 4K
24
- * do not have floating-point.
50
- * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
51
- * 1K as an artefact of legacy v5 subpage support being present in the
52
- * same QEMU executable. So in practice the hostaddr[] array has
53
- * two entries, given the current setting of TARGET_PAGE_BITS_MIN.
54
- */
25
- */
55
- int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
26
- if (snan_bit_is_one(status)) {
56
- void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)];
27
- /* sign bit clear, set all frac bits other than msb */
57
- int try, i;
28
- dnan_pattern = 0b00111111;
58
- unsigned mmu_idx = cpu_mmu_index(env, false);
29
- } else {
59
- TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
30
- /* sign bit clear, set frac msb */
60
-
31
- dnan_pattern = 0b01000000;
61
- assert(maxidx <= ARRAY_SIZE(hostaddr));
62
-
63
- for (try = 0; try < 2; try++) {
64
-
65
- for (i = 0; i < maxidx; i++) {
66
- hostaddr[i] = tlb_vaddr_to_host(env,
67
- vaddr + TARGET_PAGE_SIZE * i,
68
- 1, mmu_idx);
69
- if (!hostaddr[i]) {
70
- break;
71
- }
72
- }
73
- if (i == maxidx) {
74
- /*
75
- * If it's all in the TLB it's fair game for just writing to;
76
- * we know we don't need to update dirty status, etc.
77
- */
78
- for (i = 0; i < maxidx - 1; i++) {
79
- memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
80
- }
81
- memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
82
- return;
83
- }
84
- /*
85
- * OK, try a store and see if we can populate the tlb. This
86
- * might cause an exception if the memory isn't writable,
87
- * in which case we will longjmp out of here. We must for
88
- * this purpose use the actual register value passed to us
89
- * so that we get the fault address right.
90
- */
91
- helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC());
92
- /* Now we can populate the other TLB entries, if any */
93
- for (i = 0; i < maxidx; i++) {
94
- uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
95
- if (va != (vaddr_in & TARGET_PAGE_MASK)) {
96
- helper_ret_stb_mmu(env, va, 0, oi, GETPC());
97
- }
98
- }
99
- }
100
-
101
- /*
102
- * Slow path (probably attempt to do this to an I/O device or
103
- * similar, or clearing of a block of code we have translations
104
- * cached for). Just do a series of byte writes as the architecture
105
- * demands. It's not worth trying to use a cpu_physical_memory_map(),
106
- * memset(), unmap() sequence here because:
107
- * + we'd need to account for the blocksize being larger than a page
108
- * + the direct-RAM access case is almost always going to be dealt
109
- * with in the fastpath code above, so there's no speed benefit
110
- * + we would have to deal with the map returning NULL because the
111
- * bounce buffer was in use
112
- */
113
- for (i = 0; i < blocklen; i++) {
114
- helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC());
115
- }
32
- }
116
- }
33
- }
117
-#else
34
assert(dnan_pattern != 0);
118
- memset(g2h(vaddr), 0, blocklen);
35
119
-#endif
36
sign = dnan_pattern >> 7;
120
-}
121
-
122
/* Note that signed overflow is undefined in C. The following routines are
123
careful to use unsigned types where modulo arithmetic is required.
124
Failure to do so _will_ break on newer gcc. */
125
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
126
index XXXXXXX..XXXXXXX 100644
127
--- a/target/arm/op_helper.c
128
+++ b/target/arm/op_helper.c
129
@@ -XXX,XX +XXX,XX @@
130
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
131
*/
132
#include "qemu/osdep.h"
133
+#include "qemu/units.h"
134
#include "qemu/log.h"
135
#include "qemu/main-loop.h"
136
#include "cpu.h"
137
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
138
return ((uint32_t)x >> shift) | (x << (32 - shift));
139
}
140
}
141
+
142
+void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
143
+{
144
+ /*
145
+ * Implement DC ZVA, which zeroes a fixed-length block of memory.
146
+ * Note that we do not implement the (architecturally mandated)
147
+ * alignment fault for attempts to use this on Device memory
148
+ * (which matches the usual QEMU behaviour of not implementing either
149
+ * alignment faults or any memory attribute handling).
150
+ */
151
+
152
+ ARMCPU *cpu = env_archcpu(env);
153
+ uint64_t blocklen = 4 << cpu->dcz_blocksize;
154
+ uint64_t vaddr = vaddr_in & ~(blocklen - 1);
155
+
156
+#ifndef CONFIG_USER_ONLY
157
+ {
158
+ /*
159
+ * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
160
+ * the block size so we might have to do more than one TLB lookup.
161
+ * We know that in fact for any v8 CPU the page size is at least 4K
162
+ * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
163
+ * 1K as an artefact of legacy v5 subpage support being present in the
164
+ * same QEMU executable. So in practice the hostaddr[] array has
165
+ * two entries, given the current setting of TARGET_PAGE_BITS_MIN.
166
+ */
167
+ int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
168
+ void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)];
169
+ int try, i;
170
+ unsigned mmu_idx = cpu_mmu_index(env, false);
171
+ TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
172
+
173
+ assert(maxidx <= ARRAY_SIZE(hostaddr));
174
+
175
+ for (try = 0; try < 2; try++) {
176
+
177
+ for (i = 0; i < maxidx; i++) {
178
+ hostaddr[i] = tlb_vaddr_to_host(env,
179
+ vaddr + TARGET_PAGE_SIZE * i,
180
+ 1, mmu_idx);
181
+ if (!hostaddr[i]) {
182
+ break;
183
+ }
184
+ }
185
+ if (i == maxidx) {
186
+ /*
187
+ * If it's all in the TLB it's fair game for just writing to;
188
+ * we know we don't need to update dirty status, etc.
189
+ */
190
+ for (i = 0; i < maxidx - 1; i++) {
191
+ memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
192
+ }
193
+ memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
194
+ return;
195
+ }
196
+ /*
197
+ * OK, try a store and see if we can populate the tlb. This
198
+ * might cause an exception if the memory isn't writable,
199
+ * in which case we will longjmp out of here. We must for
200
+ * this purpose use the actual register value passed to us
201
+ * so that we get the fault address right.
202
+ */
203
+ helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC());
204
+ /* Now we can populate the other TLB entries, if any */
205
+ for (i = 0; i < maxidx; i++) {
206
+ uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
207
+ if (va != (vaddr_in & TARGET_PAGE_MASK)) {
208
+ helper_ret_stb_mmu(env, va, 0, oi, GETPC());
209
+ }
210
+ }
211
+ }
212
+
213
+ /*
214
+ * Slow path (probably attempt to do this to an I/O device or
215
+ * similar, or clearing of a block of code we have translations
216
+ * cached for). Just do a series of byte writes as the architecture
217
+ * demands. It's not worth trying to use a cpu_physical_memory_map(),
218
+ * memset(), unmap() sequence here because:
219
+ * + we'd need to account for the blocksize being larger than a page
220
+ * + the direct-RAM access case is almost always going to be dealt
221
+ * with in the fastpath code above, so there's no speed benefit
222
+ * + we would have to deal with the map returning NULL because the
223
+ * bounce buffer was in use
224
+ */
225
+ for (i = 0; i < blocklen; i++) {
226
+ helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC());
227
+ }
228
+ }
229
+#else
230
+ memset(g2h(vaddr), 0, blocklen);
231
+#endif
232
+}
233
--
37
--
234
2.20.1
38
2.34.1
235
236
diff view generated by jsdifflib
[Qemu-devel] [PULL 35/46] target/arm: Fix coding style issues
[PULL 61/72] softfloat: Inline pickNaNMulAdd
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Since we'll move this code around, fix its style first.
3
Inline pickNaNMulAdd into its only caller. This makes
4
one assert redundant with the immediately preceding IF.
4
5
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20190701132516.26392-9-philmd@redhat.com
8
Message-id: 20241203203949.483774-3-richard.henderson@linaro.org
9
[PMM: keep comment from old code in new location]
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
11
---
10
target/arm/translate.c | 11 ++++++-----
12
fpu/softfloat-parts.c.inc | 41 +++++++++++++++++++++++++-
11
target/arm/vfp_helper.c | 36 ++++++++++++++++++++++++------------
13
fpu/softfloat-specialize.c.inc | 54 ----------------------------------
12
2 files changed, 30 insertions(+), 17 deletions(-)
14
2 files changed, 40 insertions(+), 55 deletions(-)
13
15
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
18
--- a/fpu/softfloat-parts.c.inc
17
+++ b/target/arm/translate.c
19
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
loaded_base = 0;
20
loaded_var = NULL;
21
n = 0;
22
- for(i=0;i<16;i++) {
23
+ for (i = 0; i < 16; i++) {
24
if (insn & (1 << i))
25
n++;
26
}
27
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
28
}
29
}
30
j = 0;
31
- for(i=0;i<16;i++) {
32
+ for (i = 0; i < 16; i++) {
33
if (insn & (1 << i)) {
34
if (is_load) {
35
/* load */
36
@@ -XXX,XX +XXX,XX @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
37
return;
38
}
21
}
39
22
40
- for(i=0;i<16;i++) {
23
if (s->default_nan_mode) {
41
+ for (i = 0; i < 16; i++) {
24
+ /*
42
qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
25
+ * We guarantee not to require the target to tell us how to
43
- if ((i % 4) == 3)
26
+ * pick a NaN if we're always returning the default NaN.
44
+ if ((i % 4) == 3) {
27
+ * But if we're not in default-NaN mode then the target must
45
qemu_fprintf(f, "\n");
28
+ * specify.
46
- else
29
+ */
30
which = 3;
31
+ } else if (infzero) {
32
+ /*
33
+ * Inf * 0 + NaN -- some implementations return the
34
+ * default NaN here, and some return the input NaN.
35
+ */
36
+ switch (s->float_infzeronan_rule) {
37
+ case float_infzeronan_dnan_never:
38
+ which = 2;
39
+ break;
40
+ case float_infzeronan_dnan_always:
41
+ which = 3;
42
+ break;
43
+ case float_infzeronan_dnan_if_qnan:
44
+ which = is_qnan(c->cls) ? 3 : 2;
45
+ break;
46
+ default:
47
+ g_assert_not_reached();
48
+ }
49
} else {
50
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
51
+ FloatClass cls[3] = { a->cls, b->cls, c->cls };
52
+ Float3NaNPropRule rule = s->float_3nan_prop_rule;
53
+
54
+ assert(rule != float_3nan_prop_none);
55
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
56
+ /* We have at least one SNaN input and should prefer it */
57
+ do {
58
+ which = rule & R_3NAN_1ST_MASK;
59
+ rule >>= R_3NAN_1ST_LENGTH;
60
+ } while (!is_snan(cls[which]));
47
+ } else {
61
+ } else {
48
qemu_fprintf(f, " ");
62
+ do {
63
+ which = rule & R_3NAN_1ST_MASK;
64
+ rule >>= R_3NAN_1ST_LENGTH;
65
+ } while (!is_nan(cls[which]));
49
+ }
66
+ }
50
}
67
}
51
68
52
if (arm_feature(env, ARM_FEATURE_M)) {
69
if (which == 3) {
53
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
70
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
54
index XXXXXXX..XXXXXXX 100644
71
index XXXXXXX..XXXXXXX 100644
55
--- a/target/arm/vfp_helper.c
72
--- a/fpu/softfloat-specialize.c.inc
56
+++ b/target/arm/vfp_helper.c
73
+++ b/fpu/softfloat-specialize.c.inc
57
@@ -XXX,XX +XXX,XX @@ static inline int vfp_exceptbits_from_host(int host_bits)
74
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
58
{
75
}
59
int target_bits = 0;
60
61
- if (host_bits & float_flag_invalid)
62
+ if (host_bits & float_flag_invalid) {
63
target_bits |= 1;
64
- if (host_bits & float_flag_divbyzero)
65
+ }
66
+ if (host_bits & float_flag_divbyzero) {
67
target_bits |= 2;
68
- if (host_bits & float_flag_overflow)
69
+ }
70
+ if (host_bits & float_flag_overflow) {
71
target_bits |= 4;
72
- if (host_bits & (float_flag_underflow | float_flag_output_denormal))
73
+ }
74
+ if (host_bits & (float_flag_underflow | float_flag_output_denormal)) {
75
target_bits |= 8;
76
- if (host_bits & float_flag_inexact)
77
+ }
78
+ if (host_bits & float_flag_inexact) {
79
target_bits |= 0x10;
80
- if (host_bits & float_flag_input_denormal)
81
+ }
82
+ if (host_bits & float_flag_input_denormal) {
83
target_bits |= 0x80;
84
+ }
85
return target_bits;
86
}
76
}
87
77
88
@@ -XXX,XX +XXX,XX @@ static inline int vfp_exceptbits_to_host(int target_bits)
78
-/*----------------------------------------------------------------------------
89
{
79
-| Select which NaN to propagate for a three-input operation.
90
int host_bits = 0;
80
-| For the moment we assume that no CPU needs the 'larger significand'
91
81
-| information.
92
- if (target_bits & 1)
82
-| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
93
+ if (target_bits & 1) {
83
-*----------------------------------------------------------------------------*/
94
host_bits |= float_flag_invalid;
84
-static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
95
- if (target_bits & 2)
85
- bool infzero, bool have_snan, float_status *status)
96
+ }
86
-{
97
+ if (target_bits & 2) {
87
- FloatClass cls[3] = { a_cls, b_cls, c_cls };
98
host_bits |= float_flag_divbyzero;
88
- Float3NaNPropRule rule = status->float_3nan_prop_rule;
99
- if (target_bits & 4)
89
- int which;
100
+ }
90
-
101
+ if (target_bits & 4) {
91
- /*
102
host_bits |= float_flag_overflow;
92
- * We guarantee not to require the target to tell us how to
103
- if (target_bits & 8)
93
- * pick a NaN if we're always returning the default NaN.
104
+ }
94
- * But if we're not in default-NaN mode then the target must
105
+ if (target_bits & 8) {
95
- * specify.
106
host_bits |= float_flag_underflow;
96
- */
107
- if (target_bits & 0x10)
97
- assert(!status->default_nan_mode);
108
+ }
98
-
109
+ if (target_bits & 0x10) {
99
- if (infzero) {
110
host_bits |= float_flag_inexact;
100
- /*
111
- if (target_bits & 0x80)
101
- * Inf * 0 + NaN -- some implementations return the default NaN here,
112
+ }
102
- * and some return the input NaN.
113
+ if (target_bits & 0x80) {
103
- */
114
host_bits |= float_flag_input_denormal;
104
- switch (status->float_infzeronan_rule) {
115
+ }
105
- case float_infzeronan_dnan_never:
116
return host_bits;
106
- return 2;
117
}
107
- case float_infzeronan_dnan_always:
118
108
- return 3;
109
- case float_infzeronan_dnan_if_qnan:
110
- return is_qnan(c_cls) ? 3 : 2;
111
- default:
112
- g_assert_not_reached();
113
- }
114
- }
115
-
116
- assert(rule != float_3nan_prop_none);
117
- if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
118
- /* We have at least one SNaN input and should prefer it */
119
- do {
120
- which = rule & R_3NAN_1ST_MASK;
121
- rule >>= R_3NAN_1ST_LENGTH;
122
- } while (!is_snan(cls[which]));
123
- } else {
124
- do {
125
- which = rule & R_3NAN_1ST_MASK;
126
- rule >>= R_3NAN_1ST_LENGTH;
127
- } while (!is_nan(cls[which]));
128
- }
129
- return which;
130
-}
131
-
132
/*----------------------------------------------------------------------------
133
| Returns 1 if the double-precision floating-point value `a' is a quiet
134
| NaN; otherwise returns 0.
119
--
135
--
120
2.20.1
136
2.34.1
121
137
122
138
diff view generated by jsdifflib
[Qemu-devel] [PULL 34/46] target/arm: Fix multiline comment syntax
[PULL 62/72] softfloat: Use goto for default nan case in pick_nan_muladd
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Since commit 8c06fbdf36b checkpatch.pl enforce a new multiline
3
Remove "3" as a special case for which and simply
4
comment syntax. Since we'll move this code around, fix its style
4
branch to return the desired value.
5
first.
6
5
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20190701132516.26392-8-philmd@redhat.com
8
Message-id: 20241203203949.483774-4-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/helper.c | 237 ++++++++++++++++++++++++++--------------
11
fpu/softfloat-parts.c.inc | 20 ++++++++++----------
13
target/arm/op_helper.c | 54 ++++++---
12
1 file changed, 10 insertions(+), 10 deletions(-)
14
target/arm/vfp_helper.c | 3 +-
15
3 files changed, 196 insertions(+), 98 deletions(-)
16
13
17
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper.c
16
--- a/fpu/softfloat-parts.c.inc
20
+++ b/target/arm/helper.c
17
+++ b/fpu/softfloat-parts.c.inc
21
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr)
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
22
19
* But if we're not in default-NaN mode then the target must
23
uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
20
* specify.
24
{
25
- /* The TT instructions can be used by unprivileged code, but in
26
+ /*
27
+ * The TT instructions can be used by unprivileged code, but in
28
* user-only emulation we don't have the MPU.
29
* Luckily since we know we are NonSecure unprivileged (and that in
30
* turn means that the A flag wasn't specified), all the bits in the
31
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
32
return true;
33
34
pend_fault:
35
- /* By pending the exception at this point we are making
36
+ /*
37
+ * By pending the exception at this point we are making
38
* the IMPDEF choice "overridden exceptions pended" (see the
39
* MergeExcInfo() pseudocode). The other choice would be to not
40
* pend them now and then make a choice about which to throw away
41
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr,
42
return true;
43
44
pend_fault:
45
- /* By pending the exception at this point we are making
46
+ /*
47
+ * By pending the exception at this point we are making
48
* the IMPDEF choice "overridden exceptions pended" (see the
49
* MergeExcInfo() pseudocode). The other choice would be to not
50
* pend them now and then make a choice about which to throw away
51
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env)
52
*/
53
}
54
55
-/* Write to v7M CONTROL.SPSEL bit for the specified security bank.
56
+/*
57
+ * Write to v7M CONTROL.SPSEL bit for the specified security bank.
58
* This may change the current stack pointer between Main and Process
59
* stack pointers if it is done for the CONTROL register for the current
60
* security state.
61
@@ -XXX,XX +XXX,XX @@ static void write_v7m_control_spsel_for_secstate(CPUARMState *env,
62
}
63
}
64
65
-/* Write to v7M CONTROL.SPSEL bit. This may change the current
66
+/*
67
+ * Write to v7M CONTROL.SPSEL bit. This may change the current
68
* stack pointer between Main and Process stack pointers.
69
*/
70
static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel)
71
@@ -XXX,XX +XXX,XX @@ static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel)
72
73
void write_v7m_exception(CPUARMState *env, uint32_t new_exc)
74
{
75
- /* Write a new value to v7m.exception, thus transitioning into or out
76
+ /*
77
+ * Write a new value to v7m.exception, thus transitioning into or out
78
* of Handler mode; this may result in a change of active stack pointer.
79
*/
80
bool new_is_psp, old_is_psp = v7m_using_psp(env);
81
@@ -XXX,XX +XXX,XX @@ static void switch_v7m_security_state(CPUARMState *env, bool new_secstate)
82
return;
83
}
84
85
- /* All the banked state is accessed by looking at env->v7m.secure
86
+ /*
87
+ * All the banked state is accessed by looking at env->v7m.secure
88
* except for the stack pointer; rearrange the SP appropriately.
89
*/
90
new_ss_msp = env->v7m.other_ss_msp;
91
@@ -XXX,XX +XXX,XX @@ static void switch_v7m_security_state(CPUARMState *env, bool new_secstate)
92
93
void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
94
{
95
- /* Handle v7M BXNS:
96
+ /*
97
+ * Handle v7M BXNS:
98
* - if the return value is a magic value, do exception return (like BX)
99
* - otherwise bit 0 of the return value is the target security state
100
*/
101
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
102
}
103
104
if (dest >= min_magic) {
105
- /* This is an exception return magic value; put it where
106
+ /*
107
+ * This is an exception return magic value; put it where
108
* do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.
109
* Note that if we ever add gen_ss_advance() singlestep support to
110
* M profile this should count as an "instruction execution complete"
111
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
112
113
void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
114
{
115
- /* Handle v7M BLXNS:
116
+ /*
117
+ * Handle v7M BLXNS:
118
* - bit 0 of the destination address is the target security state
119
*/
120
121
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
122
assert(env->v7m.secure);
123
124
if (dest & 1) {
125
- /* target is Secure, so this is just a normal BLX,
126
+ /*
127
+ * Target is Secure, so this is just a normal BLX,
128
* except that the low bit doesn't indicate Thumb/not.
129
*/
21
*/
130
env->regs[14] = nextinst;
22
- which = 3;
131
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
23
+ goto default_nan;
132
env->regs[13] = sp;
24
} else if (infzero) {
133
env->regs[14] = 0xfeffffff;
25
/*
134
if (arm_v7m_is_handler_mode(env)) {
26
* Inf * 0 + NaN -- some implementations return the
135
- /* Write a dummy value to IPSR, to avoid leaking the current secure
27
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
136
+ /*
137
+ * Write a dummy value to IPSR, to avoid leaking the current secure
138
* exception number to non-secure code. This is guaranteed not
139
* to cause write_v7m_exception() to actually change stacks.
140
*/
28
*/
141
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
29
switch (s->float_infzeronan_rule) {
142
static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
30
case float_infzeronan_dnan_never:
143
bool spsel)
31
- which = 2;
144
{
32
break;
145
- /* Return a pointer to the location where we currently store the
33
case float_infzeronan_dnan_always:
146
+ /*
34
- which = 3;
147
+ * Return a pointer to the location where we currently store the
35
- break;
148
* stack pointer for the requested security state and thread mode.
36
+ goto default_nan;
149
* This pointer will become invalid if the CPU state is updated
37
case float_infzeronan_dnan_if_qnan:
150
* such that the stack pointers are switched around (eg changing
38
- which = is_qnan(c->cls) ? 3 : 2;
151
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
39
+ if (is_qnan(c->cls)) {
152
40
+ goto default_nan;
153
mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, targets_secure, true);
41
+ }
154
42
break;
155
- /* We don't do a get_phys_addr() here because the rules for vector
43
default:
156
+ /*
44
g_assert_not_reached();
157
+ * We don't do a get_phys_addr() here because the rules for vector
158
* loads are special: they always use the default memory map, and
159
* the default memory map permits reads from all addresses.
160
* Since there's no easy way to pass through to pmsav8_mpu_lookup()
161
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
162
return true;
163
164
load_fail:
165
- /* All vector table fetch fails are reported as HardFault, with
166
+ /*
167
+ * All vector table fetch fails are reported as HardFault, with
168
* HFSR.VECTTBL and .FORCED set. (FORCED is set because
169
* technically the underlying exception is a MemManage or BusFault
170
* that is escalated to HardFault.) This is a terminal exception,
171
@@ -XXX,XX +XXX,XX @@ static uint32_t v7m_integrity_sig(CPUARMState *env, uint32_t lr)
172
static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
173
bool ignore_faults)
174
{
175
- /* For v8M, push the callee-saves register part of the stack frame.
176
+ /*
177
+ * For v8M, push the callee-saves register part of the stack frame.
178
* Compare the v8M pseudocode PushCalleeStack().
179
* In the tailchaining case this may not be the current stack.
180
*/
181
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
182
return true;
183
}
184
185
- /* Write as much of the stack frame as we can. A write failure may
186
+ /*
187
+ * Write as much of the stack frame as we can. A write failure may
188
* cause us to pend a derived exception.
189
*/
190
sig = v7m_integrity_sig(env, lr);
191
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
192
static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
193
bool ignore_stackfaults)
194
{
195
- /* Do the "take the exception" parts of exception entry,
196
+ /*
197
+ * Do the "take the exception" parts of exception entry,
198
* but not the pushing of state to the stack. This is
199
* similar to the pseudocode ExceptionTaken() function.
200
*/
201
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
202
if (arm_feature(env, ARM_FEATURE_V8)) {
203
if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
204
(lr & R_V7M_EXCRET_S_MASK)) {
205
- /* The background code (the owner of the registers in the
206
+ /*
207
+ * The background code (the owner of the registers in the
208
* exception frame) is Secure. This means it may either already
209
* have or now needs to push callee-saves registers.
210
*/
211
if (targets_secure) {
212
if (dotailchain && !(lr & R_V7M_EXCRET_ES_MASK)) {
213
- /* We took an exception from Secure to NonSecure
214
+ /*
215
+ * We took an exception from Secure to NonSecure
216
* (which means the callee-saved registers got stacked)
217
* and are now tailchaining to a Secure exception.
218
* Clear DCRS so eventual return from this Secure
219
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
220
lr &= ~R_V7M_EXCRET_DCRS_MASK;
221
}
222
} else {
223
- /* We're going to a non-secure exception; push the
224
+ /*
225
+ * We're going to a non-secure exception; push the
226
* callee-saves registers to the stack now, if they're
227
* not already saved.
228
*/
229
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
230
lr |= R_V7M_EXCRET_SPSEL_MASK;
231
}
45
}
232
46
+ which = 2;
233
- /* Clear registers if necessary to prevent non-secure exception
47
} else {
234
+ /*
48
FloatClass cls[3] = { a->cls, b->cls, c->cls };
235
+ * Clear registers if necessary to prevent non-secure exception
49
Float3NaNPropRule rule = s->float_3nan_prop_rule;
236
* code being able to see register values from secure code.
50
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
237
* Where register values become architecturally UNKNOWN we leave
238
* them with their previous values.
239
*/
240
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
241
if (!targets_secure) {
242
- /* Always clear the caller-saved registers (they have been
243
+ /*
244
+ * Always clear the caller-saved registers (they have been
245
* pushed to the stack earlier in v7m_push_stack()).
246
* Clear callee-saved registers if the background code is
247
* Secure (in which case these regs were saved in
248
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
249
}
250
251
if (push_failed && !ignore_stackfaults) {
252
- /* Derived exception on callee-saves register stacking:
253
+ /*
254
+ * Derived exception on callee-saves register stacking:
255
* we might now want to take a different exception which
256
* targets a different security state, so try again from the top.
257
*/
258
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
259
return;
260
}
261
262
- /* Now we've done everything that might cause a derived exception
263
+ /*
264
+ * Now we've done everything that might cause a derived exception
265
* we can go ahead and activate whichever exception we're going to
266
* take (which might now be the derived exception).
267
*/
268
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr)
269
270
static bool v7m_push_stack(ARMCPU *cpu)
271
{
272
- /* Do the "set up stack frame" part of exception entry,
273
+ /*
274
+ * Do the "set up stack frame" part of exception entry,
275
* similar to pseudocode PushStack().
276
* Return true if we generate a derived exception (and so
277
* should ignore further stack faults trying to process
278
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_stack(ARMCPU *cpu)
279
}
51
}
280
}
52
}
281
53
282
- /* Write as much of the stack frame as we can. If we fail a stack
54
- if (which == 3) {
283
+ /*
55
- parts_default_nan(a, s);
284
+ * Write as much of the stack frame as we can. If we fail a stack
56
- return a;
285
* write this will result in a derived exception being pended
57
- }
286
* (which may be taken in preference to the one we started with
58
-
287
* if it has higher priority).
59
switch (which) {
288
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
60
case 0:
289
bool ftype;
61
break;
290
bool restore_s16_s31;
62
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
291
63
parts_silence_nan(a, s);
292
- /* If we're not in Handler mode then jumps to magic exception-exit
293
+ /*
294
+ * If we're not in Handler mode then jumps to magic exception-exit
295
* addresses don't have magic behaviour. However for the v8M
296
* security extensions the magic secure-function-return has to
297
* work in thread mode too, so to avoid doing an extra check in
298
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
299
return;
300
}
64
}
301
65
return a;
302
- /* In the spec pseudocode ExceptionReturn() is called directly
66
+
303
+ /*
67
+ default_nan:
304
+ * In the spec pseudocode ExceptionReturn() is called directly
68
+ parts_default_nan(a, s);
305
* from BXWritePC() and gets the full target PC value including
69
+ return a;
306
* bit zero. In QEMU's implementation we treat it as a normal
307
* jump-to-register (which is then caught later on), and so split
308
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
309
}
310
311
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
312
- /* EXC_RETURN.ES validation check (R_SMFL). We must do this before
313
+ /*
314
+ * EXC_RETURN.ES validation check (R_SMFL). We must do this before
315
* we pick which FAULTMASK to clear.
316
*/
317
if (!env->v7m.secure &&
318
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
319
}
320
321
if (env->v7m.exception != ARMV7M_EXCP_NMI) {
322
- /* Auto-clear FAULTMASK on return from other than NMI.
323
+ /*
324
+ * Auto-clear FAULTMASK on return from other than NMI.
325
* If the security extension is implemented then this only
326
* happens if the raw execution priority is >= 0; the
327
* value of the ES bit in the exception return value indicates
328
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
329
/* still an irq active now */
330
break;
331
case 1:
332
- /* we returned to base exception level, no nesting.
333
+ /*
334
+ * We returned to base exception level, no nesting.
335
* (In the pseudocode this is written using "NestedActivation != 1"
336
* where we have 'rettobase == false'.)
337
*/
338
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
339
340
if (arm_feature(env, ARM_FEATURE_V8)) {
341
if (!arm_feature(env, ARM_FEATURE_M_SECURITY)) {
342
- /* UNPREDICTABLE if S == 1 or DCRS == 0 or ES == 1 (R_XLCP);
343
+ /*
344
+ * UNPREDICTABLE if S == 1 or DCRS == 0 or ES == 1 (R_XLCP);
345
* we choose to take the UsageFault.
346
*/
347
if ((excret & R_V7M_EXCRET_S_MASK) ||
348
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
349
break;
350
case 13: /* Return to Thread using Process stack */
351
case 9: /* Return to Thread using Main stack */
352
- /* We only need to check NONBASETHRDENA for v7M, because in
353
+ /*
354
+ * We only need to check NONBASETHRDENA for v7M, because in
355
* v8M this bit does not exist (it is RES1).
356
*/
357
if (!rettobase &&
358
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
359
}
360
361
if (ufault) {
362
- /* Bad exception return: instead of popping the exception
363
+ /*
364
+ * Bad exception return: instead of popping the exception
365
* stack, directly take a usage fault on the current stack.
366
*/
367
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
368
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
369
switch_v7m_security_state(env, return_to_secure);
370
371
{
372
- /* The stack pointer we should be reading the exception frame from
373
+ /*
374
+ * The stack pointer we should be reading the exception frame from
375
* depends on bits in the magic exception return type value (and
376
* for v8M isn't necessarily the stack pointer we will eventually
377
* end up resuming execution with). Get a pointer to the location
378
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
379
v7m_stack_read(cpu, &xpsr, frameptr + 0x1c, mmu_idx);
380
381
if (!pop_ok) {
382
- /* v7m_stack_read() pended a fault, so take it (as a tail
383
+ /*
384
+ * v7m_stack_read() pended a fault, so take it (as a tail
385
* chained exception on the same stack frame)
386
*/
387
qemu_log_mask(CPU_LOG_INT, "...derived exception on unstacking\n");
388
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
389
return;
390
}
391
392
- /* Returning from an exception with a PC with bit 0 set is defined
393
+ /*
394
+ * Returning from an exception with a PC with bit 0 set is defined
395
* behaviour on v8M (bit 0 is ignored), but for v7M it was specified
396
* to be UNPREDICTABLE. In practice actual v7M hardware seems to ignore
397
* the lsbit, and there are several RTOSes out there which incorrectly
398
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
399
}
400
401
if (arm_feature(env, ARM_FEATURE_V8)) {
402
- /* For v8M we have to check whether the xPSR exception field
403
+ /*
404
+ * For v8M we have to check whether the xPSR exception field
405
* matches the EXCRET value for return to handler/thread
406
* before we commit to changing the SP and xPSR.
407
*/
408
bool will_be_handler = (xpsr & XPSR_EXCP) != 0;
409
if (return_to_handler != will_be_handler) {
410
- /* Take an INVPC UsageFault on the current stack.
411
+ /*
412
+ * Take an INVPC UsageFault on the current stack.
413
* By this point we will have switched to the security state
414
* for the background state, so this UsageFault will target
415
* that state.
416
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
417
frameptr += 0x40;
418
}
419
}
420
- /* Undo stack alignment (the SPREALIGN bit indicates that the original
421
+ /*
422
+ * Undo stack alignment (the SPREALIGN bit indicates that the original
423
* pre-exception SP was not 8-aligned and we added a padding word to
424
* align it, so we undo this by ORing in the bit that increases it
425
* from the current 8-aligned value to the 8-unaligned value. (Adding 4
426
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
427
V7M_CONTROL, SFPA, sfpa);
428
}
429
430
- /* The restored xPSR exception field will be zero if we're
431
+ /*
432
+ * The restored xPSR exception field will be zero if we're
433
* resuming in Thread mode. If that doesn't match what the
434
* exception return excret specified then this is a UsageFault.
435
* v7M requires we make this check here; v8M did it earlier.
436
*/
437
if (return_to_handler != arm_v7m_is_handler_mode(env)) {
438
- /* Take an INVPC UsageFault by pushing the stack again;
439
+ /*
440
+ * Take an INVPC UsageFault by pushing the stack again;
441
* we know we're v7M so this is never a Secure UsageFault.
442
*/
443
bool ignore_stackfaults;
444
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
445
446
static bool do_v7m_function_return(ARMCPU *cpu)
447
{
448
- /* v8M security extensions magic function return.
449
+ /*
450
+ * v8M security extensions magic function return.
451
* We may either:
452
* (1) throw an exception (longjump)
453
* (2) return true if we successfully handled the function return
454
@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
455
frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);
456
frameptr = *frame_sp_p;
457
458
- /* These loads may throw an exception (for MPU faults). We want to
459
+ /*
460
+ * These loads may throw an exception (for MPU faults). We want to
461
* do them as secure, so work out what MMU index that is.
462
*/
463
mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
464
@@ -XXX,XX +XXX,XX @@ static void arm_log_exception(int idx)
465
static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
466
uint32_t addr, uint16_t *insn)
467
{
468
- /* Load a 16-bit portion of a v7M instruction, returning true on success,
469
+ /*
470
+ * Load a 16-bit portion of a v7M instruction, returning true on success,
471
* or false on failure (in which case we will have pended the appropriate
472
* exception).
473
* We need to do the instruction fetch's MPU and SAU checks
474
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
475
476
v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
477
if (!sattrs.nsc || sattrs.ns) {
478
- /* This must be the second half of the insn, and it straddles a
479
+ /*
480
+ * This must be the second half of the insn, and it straddles a
481
* region boundary with the second half not being S&NSC.
482
*/
483
env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK;
484
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
485
486
static bool v7m_handle_execute_nsc(ARMCPU *cpu)
487
{
488
- /* Check whether this attempt to execute code in a Secure & NS-Callable
489
+ /*
490
+ * Check whether this attempt to execute code in a Secure & NS-Callable
491
* memory region is for an SG instruction; if so, then emulate the
492
* effect of the SG instruction and return true. Otherwise pend
493
* the correct kind of exception and return false.
494
@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
495
ARMMMUIdx mmu_idx;
496
uint16_t insn;
497
498
- /* We should never get here unless get_phys_addr_pmsav8() caused
499
+ /*
500
+ * We should never get here unless get_phys_addr_pmsav8() caused
501
* an exception for NS executing in S&NSC memory.
502
*/
503
assert(!env->v7m.secure);
504
@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
505
}
506
507
if (insn != 0xe97f) {
508
- /* Not an SG instruction first half (we choose the IMPDEF
509
+ /*
510
+ * Not an SG instruction first half (we choose the IMPDEF
511
* early-SG-check option).
512
*/
513
goto gen_invep;
514
@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
515
}
516
517
if (insn != 0xe97f) {
518
- /* Not an SG instruction second half (yes, both halves of the SG
519
+ /*
520
+ * Not an SG instruction second half (yes, both halves of the SG
521
* insn have the same hex value)
522
*/
523
goto gen_invep;
524
}
525
526
- /* OK, we have confirmed that we really have an SG instruction.
527
+ /*
528
+ * OK, we have confirmed that we really have an SG instruction.
529
* We know we're NS in S memory so don't need to repeat those checks.
530
*/
531
qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32
532
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
533
534
arm_log_exception(cs->exception_index);
535
536
- /* For exceptions we just mark as pending on the NVIC, and let that
537
- handle it. */
538
+ /*
539
+ * For exceptions we just mark as pending on the NVIC, and let that
540
+ * handle it.
541
+ */
542
switch (cs->exception_index) {
543
case EXCP_UDEF:
544
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
545
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
546
break;
547
case EXCP_PREFETCH_ABORT:
548
case EXCP_DATA_ABORT:
549
- /* Note that for M profile we don't have a guest facing FSR, but
550
+ /*
551
+ * Note that for M profile we don't have a guest facing FSR, but
552
* the env->exception.fsr will be populated by the code that
553
* raises the fault, in the A profile short-descriptor format.
554
*/
555
switch (env->exception.fsr & 0xf) {
556
case M_FAKE_FSR_NSC_EXEC:
557
- /* Exception generated when we try to execute code at an address
558
+ /*
559
+ * Exception generated when we try to execute code at an address
560
* which is marked as Secure & Non-Secure Callable and the CPU
561
* is in the Non-Secure state. The only instruction which can
562
* be executed like this is SG (and that only if both halves of
563
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
564
}
565
break;
566
case M_FAKE_FSR_SFAULT:
567
- /* Various flavours of SecureFault for attempts to execute or
568
+ /*
569
+ * Various flavours of SecureFault for attempts to execute or
570
* access data in the wrong security state.
571
*/
572
switch (cs->exception_index) {
573
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
574
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
575
break;
576
default:
577
- /* All other FSR values are either MPU faults or "can't happen
578
+ /*
579
+ * All other FSR values are either MPU faults or "can't happen
580
* for M profile" cases.
581
*/
582
switch (cs->exception_index) {
583
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
584
if (arm_feature(env, ARM_FEATURE_V8)) {
585
lr = R_V7M_EXCRET_RES1_MASK |
586
R_V7M_EXCRET_DCRS_MASK;
587
- /* The S bit indicates whether we should return to Secure
588
+ /*
589
+ * The S bit indicates whether we should return to Secure
590
* or NonSecure (ie our current state).
591
* The ES bit indicates whether we're taking this exception
592
* to Secure or NonSecure (ie our target state). We set it
593
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
594
v7m_exception_taken(cpu, lr, false, ignore_stackfaults);
595
}
70
}
596
71
597
-/* Function used to synchronize QEMU's AArch64 register set with AArch32
72
/*
598
+/*
599
+ * Function used to synchronize QEMU's AArch64 register set with AArch32
600
* register set. This is necessary when switching between AArch32 and AArch64
601
* execution state.
602
*/
603
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_32_to_64(CPUARMState *env)
604
env->xregs[i] = env->regs[i];
605
}
606
607
- /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
608
+ /*
609
+ * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
610
* Otherwise, they come from the banked user regs.
611
*/
612
if (mode == ARM_CPU_MODE_FIQ) {
613
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_32_to_64(CPUARMState *env)
614
}
615
}
616
617
- /* Registers x13-x23 are the various mode SP and FP registers. Registers
618
+ /*
619
+ * Registers x13-x23 are the various mode SP and FP registers. Registers
620
* r13 and r14 are only copied if we are in that mode, otherwise we copy
621
* from the mode banked register.
622
*/
623
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_32_to_64(CPUARMState *env)
624
env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
625
}
626
627
- /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
628
+ /*
629
+ * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
630
* mode, then we can copy from r8-r14. Otherwise, we copy from the
631
* FIQ bank for r8-r14.
632
*/
633
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_32_to_64(CPUARMState *env)
634
env->pc = env->regs[15];
635
}
636
637
-/* Function used to synchronize QEMU's AArch32 register set with AArch64
638
+/*
639
+ * Function used to synchronize QEMU's AArch32 register set with AArch64
640
* register set. This is necessary when switching between AArch32 and AArch64
641
* execution state.
642
*/
643
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_64_to_32(CPUARMState *env)
644
env->regs[i] = env->xregs[i];
645
}
646
647
- /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
648
+ /*
649
+ * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
650
* Otherwise, we copy x8-x12 into the banked user regs.
651
*/
652
if (mode == ARM_CPU_MODE_FIQ) {
653
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_64_to_32(CPUARMState *env)
654
}
655
}
656
657
- /* Registers r13 & r14 depend on the current mode.
658
+ /*
659
+ * Registers r13 & r14 depend on the current mode.
660
* If we are in a given mode, we copy the corresponding x registers to r13
661
* and r14. Otherwise, we copy the x register to the banked r13 and r14
662
* for the mode.
663
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_64_to_32(CPUARMState *env)
664
} else {
665
env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
666
667
- /* HYP is an exception in that it does not have its own banked r14 but
668
+ /*
669
+ * HYP is an exception in that it does not have its own banked r14 but
670
* shares the USR r14
671
*/
672
if (mode == ARM_CPU_MODE_HYP) {
673
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
674
return value;
675
}
676
case 0x94: /* CONTROL_NS */
677
- /* We have to handle this here because unprivileged Secure code
678
+ /*
679
+ * We have to handle this here because unprivileged Secure code
680
* can read the NS CONTROL register.
681
*/
682
if (!env->v7m.secure) {
683
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
684
return env->v7m.faultmask[M_REG_NS];
685
case 0x98: /* SP_NS */
686
{
687
- /* This gives the non-secure SP selected based on whether we're
688
+ /*
689
+ * This gives the non-secure SP selected based on whether we're
690
* currently in handler mode or not, using the NS CONTROL.SPSEL.
691
*/
692
bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
693
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
694
695
void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
696
{
697
- /* We're passed bits [11..0] of the instruction; extract
698
+ /*
699
+ * We're passed bits [11..0] of the instruction; extract
700
* SYSm and the mask bits.
701
* Invalid combinations of SYSm and mask are UNPREDICTABLE;
702
* we choose to treat them as if the mask bits were valid.
703
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
704
return;
705
case 0x98: /* SP_NS */
706
{
707
- /* This gives the non-secure SP selected based on whether we're
708
+ /*
709
+ * This gives the non-secure SP selected based on whether we're
710
* currently in handler mode or not, using the NS CONTROL.SPSEL.
711
*/
712
bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
713
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
714
bool targetsec = env->v7m.secure;
715
bool is_subpage;
716
717
- /* Work out what the security state and privilege level we're
718
+ /*
719
+ * Work out what the security state and privilege level we're
720
* interested in is...
721
*/
722
if (alt) {
723
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
724
/* ...and then figure out which MMU index this is */
725
mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, targetsec, targetpriv);
726
727
- /* We know that the MPU and SAU don't care about the access type
728
+ /*
729
+ * We know that the MPU and SAU don't care about the access type
730
* for our purposes beyond that we don't want to claim to be
731
* an insn fetch, so we arbitrarily call this a read.
732
*/
733
734
- /* MPU region info only available for privileged or if
735
+ /*
736
+ * MPU region info only available for privileged or if
737
* inspecting the other MPU state.
738
*/
739
if (arm_current_el(env) != 0 || alt) {
740
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
741
742
void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
743
{
744
- /* Implement DC ZVA, which zeroes a fixed-length block of memory.
745
+ /*
746
+ * Implement DC ZVA, which zeroes a fixed-length block of memory.
747
* Note that we do not implement the (architecturally mandated)
748
* alignment fault for attempts to use this on Device memory
749
* (which matches the usual QEMU behaviour of not implementing either
750
@@ -XXX,XX +XXX,XX @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
751
752
#ifndef CONFIG_USER_ONLY
753
{
754
- /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
755
+ /*
756
+ * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
757
* the block size so we might have to do more than one TLB lookup.
758
* We know that in fact for any v8 CPU the page size is at least 4K
759
* and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
760
@@ -XXX,XX +XXX,XX @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
761
}
762
}
763
if (i == maxidx) {
764
- /* If it's all in the TLB it's fair game for just writing to;
765
+ /*
766
+ * If it's all in the TLB it's fair game for just writing to;
767
* we know we don't need to update dirty status, etc.
768
*/
769
for (i = 0; i < maxidx - 1; i++) {
770
@@ -XXX,XX +XXX,XX @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
771
memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
772
return;
773
}
774
- /* OK, try a store and see if we can populate the tlb. This
775
+ /*
776
+ * OK, try a store and see if we can populate the tlb. This
777
* might cause an exception if the memory isn't writable,
778
* in which case we will longjmp out of here. We must for
779
* this purpose use the actual register value passed to us
780
@@ -XXX,XX +XXX,XX @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
781
}
782
}
783
784
- /* Slow path (probably attempt to do this to an I/O device or
785
+ /*
786
+ * Slow path (probably attempt to do this to an I/O device or
787
* similar, or clearing of a block of code we have translations
788
* cached for). Just do a series of byte writes as the architecture
789
* demands. It's not worth trying to use a cpu_physical_memory_map(),
790
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
791
index XXXXXXX..XXXXXXX 100644
792
--- a/target/arm/op_helper.c
793
+++ b/target/arm/op_helper.c
794
@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
795
{
796
uint32_t syn;
797
798
- /* ISV is only set for data aborts routed to EL2 and
799
+ /*
800
+ * ISV is only set for data aborts routed to EL2 and
801
* never for stage-1 page table walks faulting on stage 2.
802
*
803
* Furthermore, ISV is only set for certain kinds of load/stores.
804
@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
805
syn = syn_data_abort_no_iss(same_el,
806
ea, 0, s1ptw, is_write, fsc);
807
} else {
808
- /* Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
809
+ /*
810
+ * Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
811
* syndrome created at translation time.
812
* Now we create the runtime syndrome with the remaining fields.
813
*/
814
@@ -XXX,XX +XXX,XX @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type,
815
816
if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
817
arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
818
- /* LPAE format fault status register : bottom 6 bits are
819
+ /*
820
+ * LPAE format fault status register : bottom 6 bits are
821
* status code in the same form as needed for syndrome
822
*/
823
fsr = arm_fi_to_lfsc(fi);
824
fsc = extract32(fsr, 0, 6);
825
} else {
826
fsr = arm_fi_to_sfsc(fi);
827
- /* Short format FSR : this fault will never actually be reported
828
+ /*
829
+ * Short format FSR : this fault will never actually be reported
830
* to an EL that uses a syndrome register. Use a (currently)
831
* reserved FSR code in case the constructed syndrome does leak
832
* into the guest somehow.
833
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
834
arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
835
}
836
837
-/* arm_cpu_do_transaction_failed: handle a memory system error response
838
+/*
839
+ * arm_cpu_do_transaction_failed: handle a memory system error response
840
* (eg "no device/memory present at address") by raising an external abort
841
* exception
842
*/
843
@@ -XXX,XX +XXX,XX @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
844
int bt;
845
uint32_t contextidr;
846
847
- /* Links to unimplemented or non-context aware breakpoints are
848
+ /*
849
+ * Links to unimplemented or non-context aware breakpoints are
850
* CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
851
* as if linked to an UNKNOWN context-aware breakpoint (in which
852
* case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
853
@@ -XXX,XX +XXX,XX @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
854
855
bt = extract64(bcr, 20, 4);
856
857
- /* We match the whole register even if this is AArch32 using the
858
+ /*
859
+ * We match the whole register even if this is AArch32 using the
860
* short descriptor format (in which case it holds both PROCID and ASID),
861
* since we don't implement the optional v7 context ID masking.
862
*/
863
@@ -XXX,XX +XXX,XX @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
864
case 9: /* linked VMID match (reserved if no EL2) */
865
case 11: /* linked context ID and VMID match (reserved if no EL2) */
866
default:
867
- /* Links to Unlinked context breakpoints must generate no
868
+ /*
869
+ * Links to Unlinked context breakpoints must generate no
870
* events; we choose to do the same for reserved values too.
871
*/
872
return false;
873
@@ -XXX,XX +XXX,XX @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
874
CPUARMState *env = &cpu->env;
875
uint64_t cr;
876
int pac, hmc, ssc, wt, lbn;
877
- /* Note that for watchpoints the check is against the CPU security
878
+ /*
879
+ * Note that for watchpoints the check is against the CPU security
880
* state, not the S/NS attribute on the offending data access.
881
*/
882
bool is_secure = arm_is_secure(env);
883
@@ -XXX,XX +XXX,XX @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
884
}
885
cr = env->cp15.dbgwcr[n];
886
if (wp->hitattrs.user) {
887
- /* The LDRT/STRT/LDT/STT "unprivileged access" instructions should
888
+ /*
889
+ * The LDRT/STRT/LDT/STT "unprivileged access" instructions should
890
* match watchpoints as if they were accesses done at EL0, even if
891
* the CPU is at EL1 or higher.
892
*/
893
@@ -XXX,XX +XXX,XX @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
894
}
895
cr = env->cp15.dbgbcr[n];
896
}
897
- /* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
898
+ /*
899
+ * The WATCHPOINT_HIT flag guarantees us that the watchpoint is
900
* enabled and that the address and access type match; for breakpoints
901
* we know the address matched; check the remaining fields, including
902
* linked breakpoints. We rely on WCR and BCR having the same layout
903
@@ -XXX,XX +XXX,XX @@ static bool check_watchpoints(ARMCPU *cpu)
904
CPUARMState *env = &cpu->env;
905
int n;
906
907
- /* If watchpoints are disabled globally or we can't take debug
908
+ /*
909
+ * If watchpoints are disabled globally or we can't take debug
910
* exceptions here then watchpoint firings are ignored.
911
*/
912
if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
913
@@ -XXX,XX +XXX,XX @@ static bool check_breakpoints(ARMCPU *cpu)
914
CPUARMState *env = &cpu->env;
915
int n;
916
917
- /* If breakpoints are disabled globally or we can't take debug
918
+ /*
919
+ * If breakpoints are disabled globally or we can't take debug
920
* exceptions here then breakpoint firings are ignored.
921
*/
922
if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
923
@@ -XXX,XX +XXX,XX @@ void HELPER(check_breakpoints)(CPUARMState *env)
924
925
bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
926
{
927
- /* Called by core code when a CPU watchpoint fires; need to check if this
928
+ /*
929
+ * Called by core code when a CPU watchpoint fires; need to check if this
930
* is also an architectural watchpoint match.
931
*/
932
ARMCPU *cpu = ARM_CPU(cs);
933
@@ -XXX,XX +XXX,XX @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
934
ARMCPU *cpu = ARM_CPU(cs);
935
CPUARMState *env = &cpu->env;
936
937
- /* In BE32 system mode, target memory is stored byteswapped (on a
938
+ /*
939
+ * In BE32 system mode, target memory is stored byteswapped (on a
940
* little-endian host system), and by the time we reach here (via an
941
* opcode helper) the addresses of subword accesses have been adjusted
942
* to account for that, which means that watchpoints will not match.
943
@@ -XXX,XX +XXX,XX @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
944
945
void arm_debug_excp_handler(CPUState *cs)
946
{
947
- /* Called by core code when a watchpoint or breakpoint fires;
948
+ /*
949
+ * Called by core code when a watchpoint or breakpoint fires;
950
* need to check which one and raise the appropriate exception.
951
*/
952
ARMCPU *cpu = ARM_CPU(cs);
953
@@ -XXX,XX +XXX,XX @@ void arm_debug_excp_handler(CPUState *cs)
954
uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
955
bool same_el = (arm_debug_target_el(env) == arm_current_el(env));
956
957
- /* (1) GDB breakpoints should be handled first.
958
+ /*
959
+ * (1) GDB breakpoints should be handled first.
960
* (2) Do not raise a CPU exception if no CPU breakpoint has fired,
961
* since singlestep is also done by generating a debug internal
962
* exception.
963
@@ -XXX,XX +XXX,XX @@ void arm_debug_excp_handler(CPUState *cs)
964
}
965
966
env->exception.fsr = arm_debug_exception_fsr(env);
967
- /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
968
+ /*
969
+ * FAR is UNKNOWN: clear vaddress to avoid potentially exposing
970
* values to the guest that it shouldn't be able to see at its
971
* exception/security level.
972
*/
973
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
974
index XXXXXXX..XXXXXXX 100644
975
--- a/target/arm/vfp_helper.c
976
+++ b/target/arm/vfp_helper.c
977
@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
978
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
979
}
980
981
- /* The exception flags are ORed together when we read fpscr so we
982
+ /*
983
+ * The exception flags are ORed together when we read fpscr so we
984
* only need to preserve the current state in one of our
985
* float_status values.
986
*/
987
--
73
--
988
2.20.1
74
2.34.1
989
75
990
76
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/46] hw/arm/msf2-som: Exit when the cpu is not the expected one
[PULL 63/72] softfloat: Remove which from parts_pick_nan_muladd
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This machine correctly defines its default_cpu_type to cortex-m3
3
Assign the pointer return value to 'a' directly,
4
and report an error if the user requested another cpu_type,
4
rather than going through an intermediary index.
5
however it does not exit, and this can confuse users trying
6
to use another core:
7
5
8
$ qemu-system-arm -M emcraft-sf2 -cpu cortex-m4 -kernel test-m4.elf
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
qemu-system-arm: This board can only be used with CPU cortex-m3-arm-cpu
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
[output related to M3 core ...]
8
Message-id: 20241203203949.483774-5-richard.henderson@linaro.org
11
12
The CPU is indeed a M3 core:
13
14
(qemu) info qom-tree
15
/machine (emcraft-sf2-machine)
16
/unattached (container)
17
/device[0] (msf2-soc)
18
/armv7m (armv7m)
19
/cpu (cortex-m3-arm-cpu)
20
21
Add the missing exit() call to return to the shell.
22
23
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
24
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
25
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
26
Message-id: 20190617160136.29930-1-philmd@redhat.com
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
---
10
---
29
hw/arm/msf2-som.c | 1 +
11
fpu/softfloat-parts.c.inc | 32 ++++++++++----------------------
30
1 file changed, 1 insertion(+)
12
1 file changed, 10 insertions(+), 22 deletions(-)
31
13
32
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
33
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/msf2-som.c
16
--- a/fpu/softfloat-parts.c.inc
35
+++ b/hw/arm/msf2-som.c
17
+++ b/fpu/softfloat-parts.c.inc
36
@@ -XXX,XX +XXX,XX @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
37
if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
19
FloatPartsN *c, float_status *s,
38
error_report("This board can only be used with CPU %s",
20
int ab_mask, int abc_mask)
39
mc->default_cpu_type);
21
{
40
+ exit(1);
22
- int which;
23
bool infzero = (ab_mask == float_cmask_infzero);
24
bool have_snan = (abc_mask & float_cmask_snan);
25
+ FloatPartsN *ret;
26
27
if (unlikely(have_snan)) {
28
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
30
default:
31
g_assert_not_reached();
32
}
33
- which = 2;
34
+ ret = c;
35
} else {
36
- FloatClass cls[3] = { a->cls, b->cls, c->cls };
37
+ FloatPartsN *val[3] = { a, b, c };
38
Float3NaNPropRule rule = s->float_3nan_prop_rule;
39
40
assert(rule != float_3nan_prop_none);
41
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
42
/* We have at least one SNaN input and should prefer it */
43
do {
44
- which = rule & R_3NAN_1ST_MASK;
45
+ ret = val[rule & R_3NAN_1ST_MASK];
46
rule >>= R_3NAN_1ST_LENGTH;
47
- } while (!is_snan(cls[which]));
48
+ } while (!is_snan(ret->cls));
49
} else {
50
do {
51
- which = rule & R_3NAN_1ST_MASK;
52
+ ret = val[rule & R_3NAN_1ST_MASK];
53
rule >>= R_3NAN_1ST_LENGTH;
54
- } while (!is_nan(cls[which]));
55
+ } while (!is_nan(ret->cls));
56
}
41
}
57
}
42
58
43
memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
59
- switch (which) {
60
- case 0:
61
- break;
62
- case 1:
63
- a = b;
64
- break;
65
- case 2:
66
- a = c;
67
- break;
68
- default:
69
- g_assert_not_reached();
70
+ if (is_snan(ret->cls)) {
71
+ parts_silence_nan(ret, s);
72
}
73
- if (is_snan(a->cls)) {
74
- parts_silence_nan(a, s);
75
- }
76
- return a;
77
+ return ret;
78
79
default_nan:
80
parts_default_nan(a, s);
44
--
81
--
45
2.20.1
82
2.34.1
46
83
47
84
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/46] hw/arm/aspeed: Add RTC to SoC
[PULL 64/72] softfloat: Pad array size in pick_nan_muladd
1
From: Joel Stanley <joel@jms.id.au>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
All systems have an RTC.
3
While all indices into val[] should be in [0-2], the mask
4
applied is two bits. To help static analysis see there is
5
no possibility of read beyond the end of the array, pad the
6
array to 4 entries, with the final being (implicitly) NULL.
4
7
5
The IRQ is hooked up but the model does not use it at this stage. There
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
is no guest code that uses it, so this limitation is acceptable.
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
10
Message-id: 20241203203949.483774-6-richard.henderson@linaro.org
8
Signed-off-by: Joel Stanley <joel@jms.id.au>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20190618165311.27066-5-clg@kaod.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
12
---
13
include/hw/arm/aspeed_soc.h | 2 ++
13
fpu/softfloat-parts.c.inc | 2 +-
14
hw/arm/aspeed_soc.c | 13 +++++++++++++
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
2 files changed, 15 insertions(+)
16
15
17
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
18
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/aspeed_soc.h
18
--- a/fpu/softfloat-parts.c.inc
20
+++ b/include/hw/arm/aspeed_soc.h
19
+++ b/fpu/softfloat-parts.c.inc
21
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
22
#include "hw/misc/aspeed_scu.h"
21
}
23
#include "hw/misc/aspeed_sdmc.h"
22
ret = c;
24
#include "hw/timer/aspeed_timer.h"
23
} else {
25
+#include "hw/timer/aspeed_rtc.h"
24
- FloatPartsN *val[3] = { a, b, c };
26
#include "hw/i2c/aspeed_i2c.h"
25
+ FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c };
27
#include "hw/ssi/aspeed_smc.h"
26
Float3NaNPropRule rule = s->float_3nan_prop_rule;
28
#include "hw/watchdog/wdt_aspeed.h"
27
29
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
28
assert(rule != float_3nan_prop_none);
30
ARMCPU cpu;
31
MemoryRegion sram;
32
AspeedVICState vic;
33
+ AspeedRtcState rtc;
34
AspeedTimerCtrlState timerctrl;
35
AspeedI2CState i2c;
36
AspeedSCUState scu;
37
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/arm/aspeed_soc.c
40
+++ b/hw/arm/aspeed_soc.c
41
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
42
sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
43
TYPE_ASPEED_VIC);
44
45
+ sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
46
+ TYPE_ASPEED_RTC);
47
+
48
sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
49
sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
50
object_property_add_const_link(OBJECT(&s->timerctrl), "scu",
51
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
52
sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
53
qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
54
55
+ /* RTC */
56
+ object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
57
+ if (err) {
58
+ error_propagate(errp, err);
59
+ return;
60
+ }
61
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->info->memmap[ASPEED_RTC]);
62
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
63
+ aspeed_soc_get_irq(s, ASPEED_RTC));
64
+
65
/* Timer */
66
object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
67
if (err) {
68
--
29
--
69
2.20.1
30
2.34.1
70
31
71
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 27/46] hw/arm: Add arm SBSA reference machine, devices part
[PULL 65/72] softfloat: Move propagateFloatx80NaN to softfloat.c
1
From: Hongbo Zhang <hongbo.zhang@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Following the previous patch, this patch adds peripheral devices to the
3
This function is part of the public interface and
4
newly introduced SBSA-ref machine.
4
is not "specialized" to any target in any way.
5
5
6
Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 1561890034-15921-3-git-send-email-hongbo.zhang@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-7-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
hw/arm/sbsa-ref.c | 535 ++++++++++++++++++++++++++++++++++++++++++++++
11
fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++
12
1 file changed, 535 insertions(+)
12
fpu/softfloat-specialize.c.inc | 52 ----------------------------------
13
2 files changed, 52 insertions(+), 52 deletions(-)
13
14
14
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/sbsa-ref.c
17
--- a/fpu/softfloat.c
17
+++ b/hw/arm/sbsa-ref.c
18
+++ b/fpu/softfloat.c
18
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
19
*/
20
*zExpPtr = 1 - shiftCount;
20
21
}
21
#include "qemu/osdep.h"
22
22
+#include "qemu-common.h"
23
+/*----------------------------------------------------------------------------
23
#include "qapi/error.h"
24
+| Takes two extended double-precision floating-point values `a' and `b', one
24
#include "qemu/error-report.h"
25
+| of which is a NaN, and returns the appropriate NaN result. If either `a' or
25
#include "qemu/units.h"
26
+| `b' is a signaling NaN, the invalid exception is raised.
26
+#include "sysemu/device_tree.h"
27
+*----------------------------------------------------------------------------*/
27
#include "sysemu/numa.h"
28
#include "sysemu/sysemu.h"
29
#include "exec/address-spaces.h"
30
#include "exec/hwaddr.h"
31
#include "kvm_arm.h"
32
#include "hw/arm/boot.h"
33
+#include "hw/block/flash.h"
34
#include "hw/boards.h"
35
+#include "hw/ide/internal.h"
36
+#include "hw/ide/ahci_internal.h"
37
#include "hw/intc/arm_gicv3_common.h"
38
+#include "hw/loader.h"
39
+#include "hw/pci-host/gpex.h"
40
+#include "hw/usb.h"
41
+#include "net/net.h"
42
43
#define RAMLIMIT_GB 8192
44
#define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
45
46
+#define NUM_IRQS 256
47
+#define NUM_SMMU_IRQS 4
48
+#define NUM_SATA_PORTS 6
49
+
28
+
50
+#define VIRTUAL_PMU_IRQ 7
29
+floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
51
+#define ARCH_GIC_MAINT_IRQ 9
30
+{
52
+#define ARCH_TIMER_VIRT_IRQ 11
31
+ bool aIsLargerSignificand;
53
+#define ARCH_TIMER_S_EL1_IRQ 13
32
+ FloatClass a_cls, b_cls;
54
+#define ARCH_TIMER_NS_EL1_IRQ 14
55
+#define ARCH_TIMER_NS_EL2_IRQ 10
56
+
33
+
57
enum {
34
+ /* This is not complete, but is good enough for pickNaN. */
58
SBSA_FLASH,
35
+ a_cls = (!floatx80_is_any_nan(a)
59
SBSA_MEM,
36
+ ? float_class_normal
60
@@ -XXX,XX +XXX,XX @@ typedef struct {
37
+ : floatx80_is_signaling_nan(a, status)
61
void *fdt;
38
+ ? float_class_snan
62
int fdt_size;
39
+ : float_class_qnan);
63
int psci_conduit;
40
+ b_cls = (!floatx80_is_any_nan(b)
64
+ PFlashCFI01 *flash[2];
41
+ ? float_class_normal
65
} SBSAMachineState;
42
+ : floatx80_is_signaling_nan(b, status)
66
43
+ ? float_class_snan
67
#define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref")
44
+ : float_class_qnan);
68
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry sbsa_ref_memmap[] = {
69
[SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES },
70
};
71
72
+static const int sbsa_ref_irqmap[] = {
73
+ [SBSA_UART] = 1,
74
+ [SBSA_RTC] = 2,
75
+ [SBSA_PCIE] = 3, /* ... to 6 */
76
+ [SBSA_GPIO] = 7,
77
+ [SBSA_SECURE_UART] = 8,
78
+ [SBSA_SECURE_UART_MM] = 9,
79
+ [SBSA_AHCI] = 10,
80
+ [SBSA_EHCI] = 11,
81
+};
82
+
45
+
83
+/*
46
+ if (is_snan(a_cls) || is_snan(b_cls)) {
84
+ * Firmware on this machine only uses ACPI table to load OS, these limited
47
+ float_raise(float_flag_invalid, status);
85
+ * device tree nodes are just to let firmware know the info which varies from
86
+ * command line parameters, so it is not necessary to be fully compatible
87
+ * with the kernel CPU and NUMA binding rules.
88
+ */
89
+static void create_fdt(SBSAMachineState *sms)
90
+{
91
+ void *fdt = create_device_tree(&sms->fdt_size);
92
+ const MachineState *ms = MACHINE(sms);
93
+ int cpu;
94
+
95
+ if (!fdt) {
96
+ error_report("create_device_tree() failed");
97
+ exit(1);
98
+ }
48
+ }
99
+
49
+
100
+ sms->fdt = fdt;
50
+ if (status->default_nan_mode) {
101
+
51
+ return floatx80_default_nan(status);
102
+ qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref");
103
+ qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
104
+ qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
105
+
106
+ if (have_numa_distance) {
107
+ int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
108
+ uint32_t *matrix = g_malloc0(size);
109
+ int idx, i, j;
110
+
111
+ for (i = 0; i < nb_numa_nodes; i++) {
112
+ for (j = 0; j < nb_numa_nodes; j++) {
113
+ idx = (i * nb_numa_nodes + j) * 3;
114
+ matrix[idx + 0] = cpu_to_be32(i);
115
+ matrix[idx + 1] = cpu_to_be32(j);
116
+ matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]);
117
+ }
118
+ }
119
+
120
+ qemu_fdt_add_subnode(fdt, "/distance-map");
121
+ qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
122
+ matrix, size);
123
+ g_free(matrix);
124
+ }
52
+ }
125
+
53
+
126
+ qemu_fdt_add_subnode(sms->fdt, "/cpus");
54
+ if (a.low < b.low) {
55
+ aIsLargerSignificand = 0;
56
+ } else if (b.low < a.low) {
57
+ aIsLargerSignificand = 1;
58
+ } else {
59
+ aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
60
+ }
127
+
61
+
128
+ for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) {
62
+ if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
129
+ char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
63
+ if (is_snan(b_cls)) {
130
+ ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
64
+ return floatx80_silence_nan(b, status);
131
+ CPUState *cs = CPU(armcpu);
132
+
133
+ qemu_fdt_add_subnode(sms->fdt, nodename);
134
+
135
+ if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
136
+ qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id",
137
+ ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
138
+ }
65
+ }
139
+
66
+ return b;
140
+ g_free(nodename);
67
+ } else {
68
+ if (is_snan(a_cls)) {
69
+ return floatx80_silence_nan(a, status);
70
+ }
71
+ return a;
141
+ }
72
+ }
142
+}
73
+}
143
+
74
+
144
+#define SBSA_FLASH_SECTOR_SIZE (256 * KiB)
75
/*----------------------------------------------------------------------------
145
+
76
| Takes an abstract floating-point value having sign `zSign', exponent `zExp',
146
+static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms,
77
| and extended significand formed by the concatenation of `zSig0' and `zSig1',
147
+ const char *name,
78
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
148
+ const char *alias_prop_name)
79
index XXXXXXX..XXXXXXX 100644
149
+{
80
--- a/fpu/softfloat-specialize.c.inc
150
+ /*
81
+++ b/fpu/softfloat-specialize.c.inc
151
+ * Create a single flash device. We use the same parameters as
82
@@ -XXX,XX +XXX,XX @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
152
+ * the flash devices on the Versatile Express board.
83
return a;
153
+ */
154
+ DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
155
+
156
+ qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE);
157
+ qdev_prop_set_uint8(dev, "width", 4);
158
+ qdev_prop_set_uint8(dev, "device-width", 2);
159
+ qdev_prop_set_bit(dev, "big-endian", false);
160
+ qdev_prop_set_uint16(dev, "id0", 0x89);
161
+ qdev_prop_set_uint16(dev, "id1", 0x18);
162
+ qdev_prop_set_uint16(dev, "id2", 0x00);
163
+ qdev_prop_set_uint16(dev, "id3", 0x00);
164
+ qdev_prop_set_string(dev, "name", name);
165
+ object_property_add_child(OBJECT(sms), name, OBJECT(dev),
166
+ &error_abort);
167
+ object_property_add_alias(OBJECT(sms), alias_prop_name,
168
+ OBJECT(dev), "drive", &error_abort);
169
+ return PFLASH_CFI01(dev);
170
+}
171
+
172
+static void sbsa_flash_create(SBSAMachineState *sms)
173
+{
174
+ sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0");
175
+ sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1");
176
+}
177
+
178
+static void sbsa_flash_map1(PFlashCFI01 *flash,
179
+ hwaddr base, hwaddr size,
180
+ MemoryRegion *sysmem)
181
+{
182
+ DeviceState *dev = DEVICE(flash);
183
+
184
+ assert(size % SBSA_FLASH_SECTOR_SIZE == 0);
185
+ assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX);
186
+ qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE);
187
+ qdev_init_nofail(dev);
188
+
189
+ memory_region_add_subregion(sysmem, base,
190
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
191
+ 0));
192
+}
193
+
194
+static void sbsa_flash_map(SBSAMachineState *sms,
195
+ MemoryRegion *sysmem,
196
+ MemoryRegion *secure_sysmem)
197
+{
198
+ /*
199
+ * Map two flash devices to fill the SBSA_FLASH space in the memmap.
200
+ * sysmem is the system memory space. secure_sysmem is the secure view
201
+ * of the system, and the first flash device should be made visible only
202
+ * there. The second flash device is visible to both secure and nonsecure.
203
+ * If sysmem == secure_sysmem this means there is no separate Secure
204
+ * address space and both flash devices are generally visible.
205
+ */
206
+ hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2;
207
+ hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base;
208
+
209
+ sbsa_flash_map1(sms->flash[0], flashbase, flashsize,
210
+ secure_sysmem);
211
+ sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize,
212
+ sysmem);
213
+}
214
+
215
+static bool sbsa_firmware_init(SBSAMachineState *sms,
216
+ MemoryRegion *sysmem,
217
+ MemoryRegion *secure_sysmem)
218
+{
219
+ int i;
220
+ BlockBackend *pflash_blk0;
221
+
222
+ /* Map legacy -drive if=pflash to machine properties */
223
+ for (i = 0; i < ARRAY_SIZE(sms->flash); i++) {
224
+ pflash_cfi01_legacy_drive(sms->flash[i],
225
+ drive_get(IF_PFLASH, 0, i));
226
+ }
227
+
228
+ sbsa_flash_map(sms, sysmem, secure_sysmem);
229
+
230
+ pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]);
231
+
232
+ if (bios_name) {
233
+ char *fname;
234
+ MemoryRegion *mr;
235
+ int image_size;
236
+
237
+ if (pflash_blk0) {
238
+ error_report("The contents of the first flash device may be "
239
+ "specified with -bios or with -drive if=pflash... "
240
+ "but you cannot use both options at once");
241
+ exit(1);
242
+ }
243
+
244
+ /* Fall back to -bios */
245
+
246
+ fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
247
+ if (!fname) {
248
+ error_report("Could not find ROM image '%s'", bios_name);
249
+ exit(1);
250
+ }
251
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0);
252
+ image_size = load_image_mr(fname, mr);
253
+ g_free(fname);
254
+ if (image_size < 0) {
255
+ error_report("Could not load ROM image '%s'", bios_name);
256
+ exit(1);
257
+ }
258
+ }
259
+
260
+ return pflash_blk0 || bios_name;
261
+}
262
+
263
+static void create_secure_ram(SBSAMachineState *sms,
264
+ MemoryRegion *secure_sysmem)
265
+{
266
+ MemoryRegion *secram = g_new(MemoryRegion, 1);
267
+ hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base;
268
+ hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size;
269
+
270
+ memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size,
271
+ &error_fatal);
272
+ memory_region_add_subregion(secure_sysmem, base, secram);
273
+}
274
+
275
+static void create_gic(SBSAMachineState *sms, qemu_irq *pic)
276
+{
277
+ DeviceState *gicdev;
278
+ SysBusDevice *gicbusdev;
279
+ const char *gictype;
280
+ uint32_t redist0_capacity, redist0_count;
281
+ int i;
282
+
283
+ gictype = gicv3_class_name();
284
+
285
+ gicdev = qdev_create(NULL, gictype);
286
+ qdev_prop_set_uint32(gicdev, "revision", 3);
287
+ qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
288
+ /*
289
+ * Note that the num-irq property counts both internal and external
290
+ * interrupts; there are always 32 of the former (mandated by GIC spec).
291
+ */
292
+ qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
293
+ qdev_prop_set_bit(gicdev, "has-security-extensions", true);
294
+
295
+ redist0_capacity =
296
+ sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
297
+ redist0_count = MIN(smp_cpus, redist0_capacity);
298
+
299
+ qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1);
300
+ qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count);
301
+
302
+ qdev_init_nofail(gicdev);
303
+ gicbusdev = SYS_BUS_DEVICE(gicdev);
304
+ sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
305
+ sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base);
306
+
307
+ /*
308
+ * Wire the outputs from each CPU's generic timer and the GICv3
309
+ * maintenance interrupt signal to the appropriate GIC PPI inputs,
310
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
311
+ */
312
+ for (i = 0; i < smp_cpus; i++) {
313
+ DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
314
+ int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
315
+ int irq;
316
+ /*
317
+ * Mapping from the output timer irq lines from the CPU to the
318
+ * GIC PPI inputs used for this board.
319
+ */
320
+ const int timer_irq[] = {
321
+ [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
322
+ [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
323
+ [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
324
+ [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
325
+ };
326
+
327
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
328
+ qdev_connect_gpio_out(cpudev, irq,
329
+ qdev_get_gpio_in(gicdev,
330
+ ppibase + timer_irq[irq]));
331
+ }
332
+
333
+ qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
334
+ qdev_get_gpio_in(gicdev, ppibase
335
+ + ARCH_GIC_MAINT_IRQ));
336
+ qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
337
+ qdev_get_gpio_in(gicdev, ppibase
338
+ + VIRTUAL_PMU_IRQ));
339
+
340
+ sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
341
+ sysbus_connect_irq(gicbusdev, i + smp_cpus,
342
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
343
+ sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
344
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
345
+ sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
346
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
347
+ }
348
+
349
+ for (i = 0; i < NUM_IRQS; i++) {
350
+ pic[i] = qdev_get_gpio_in(gicdev, i);
351
+ }
352
+}
353
+
354
+static void create_uart(const SBSAMachineState *sms, qemu_irq *pic, int uart,
355
+ MemoryRegion *mem, Chardev *chr)
356
+{
357
+ hwaddr base = sbsa_ref_memmap[uart].base;
358
+ int irq = sbsa_ref_irqmap[uart];
359
+ DeviceState *dev = qdev_create(NULL, "pl011");
360
+ SysBusDevice *s = SYS_BUS_DEVICE(dev);
361
+
362
+ qdev_prop_set_chr(dev, "chardev", chr);
363
+ qdev_init_nofail(dev);
364
+ memory_region_add_subregion(mem, base,
365
+ sysbus_mmio_get_region(s, 0));
366
+ sysbus_connect_irq(s, 0, pic[irq]);
367
+}
368
+
369
+static void create_rtc(const SBSAMachineState *sms, qemu_irq *pic)
370
+{
371
+ hwaddr base = sbsa_ref_memmap[SBSA_RTC].base;
372
+ int irq = sbsa_ref_irqmap[SBSA_RTC];
373
+
374
+ sysbus_create_simple("pl031", base, pic[irq]);
375
+}
376
+
377
+static DeviceState *gpio_key_dev;
378
+static void sbsa_ref_powerdown_req(Notifier *n, void *opaque)
379
+{
380
+ /* use gpio Pin 3 for power button event */
381
+ qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
382
+}
383
+
384
+static Notifier sbsa_ref_powerdown_notifier = {
385
+ .notify = sbsa_ref_powerdown_req
386
+};
387
+
388
+static void create_gpio(const SBSAMachineState *sms, qemu_irq *pic)
389
+{
390
+ DeviceState *pl061_dev;
391
+ hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base;
392
+ int irq = sbsa_ref_irqmap[SBSA_GPIO];
393
+
394
+ pl061_dev = sysbus_create_simple("pl061", base, pic[irq]);
395
+
396
+ gpio_key_dev = sysbus_create_simple("gpio-key", -1,
397
+ qdev_get_gpio_in(pl061_dev, 3));
398
+
399
+ /* connect powerdown request */
400
+ qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier);
401
+}
402
+
403
+static void create_ahci(const SBSAMachineState *sms, qemu_irq *pic)
404
+{
405
+ hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base;
406
+ int irq = sbsa_ref_irqmap[SBSA_AHCI];
407
+ DeviceState *dev;
408
+ DriveInfo *hd[NUM_SATA_PORTS];
409
+ SysbusAHCIState *sysahci;
410
+ AHCIState *ahci;
411
+ int i;
412
+
413
+ dev = qdev_create(NULL, "sysbus-ahci");
414
+ qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS);
415
+ qdev_init_nofail(dev);
416
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
417
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irq]);
418
+
419
+ sysahci = SYSBUS_AHCI(dev);
420
+ ahci = &sysahci->ahci;
421
+ ide_drive_get(hd, ARRAY_SIZE(hd));
422
+ for (i = 0; i < ahci->ports; i++) {
423
+ if (hd[i] == NULL) {
424
+ continue;
425
+ }
426
+ ide_create_drive(&ahci->dev[i].port, 0, hd[i]);
427
+ }
428
+}
429
+
430
+static void create_ehci(const SBSAMachineState *sms, qemu_irq *pic)
431
+{
432
+ hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base;
433
+ int irq = sbsa_ref_irqmap[SBSA_EHCI];
434
+
435
+ sysbus_create_simple("platform-ehci-usb", base, pic[irq]);
436
+}
437
+
438
+static void create_smmu(const SBSAMachineState *sms, qemu_irq *pic,
439
+ PCIBus *bus)
440
+{
441
+ hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base;
442
+ int irq = sbsa_ref_irqmap[SBSA_SMMU];
443
+ DeviceState *dev;
444
+ int i;
445
+
446
+ dev = qdev_create(NULL, "arm-smmuv3");
447
+
448
+ object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
449
+ &error_abort);
450
+ qdev_init_nofail(dev);
451
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
452
+ for (i = 0; i < NUM_SMMU_IRQS; i++) {
453
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
454
+ }
455
+}
456
+
457
+static void create_pcie(SBSAMachineState *sms, qemu_irq *pic)
458
+{
459
+ hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base;
460
+ hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size;
461
+ hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base;
462
+ hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size;
463
+ hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base;
464
+ hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size;
465
+ hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base;
466
+ int irq = sbsa_ref_irqmap[SBSA_PCIE];
467
+ MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg;
468
+ MemoryRegion *ecam_alias, *ecam_reg;
469
+ DeviceState *dev;
470
+ PCIHostState *pci;
471
+ int i;
472
+
473
+ dev = qdev_create(NULL, TYPE_GPEX_HOST);
474
+ qdev_init_nofail(dev);
475
+
476
+ /* Map ECAM space */
477
+ ecam_alias = g_new0(MemoryRegion, 1);
478
+ ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
479
+ memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
480
+ ecam_reg, 0, size_ecam);
481
+ memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
482
+
483
+ /* Map the MMIO space */
484
+ mmio_alias = g_new0(MemoryRegion, 1);
485
+ mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
486
+ memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
487
+ mmio_reg, base_mmio, size_mmio);
488
+ memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
489
+
490
+ /* Map the MMIO_HIGH space */
491
+ mmio_alias_high = g_new0(MemoryRegion, 1);
492
+ memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high",
493
+ mmio_reg, base_mmio_high, size_mmio_high);
494
+ memory_region_add_subregion(get_system_memory(), base_mmio_high,
495
+ mmio_alias_high);
496
+
497
+ /* Map IO port space */
498
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
499
+
500
+ for (i = 0; i < GPEX_NUM_IRQS; i++) {
501
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
502
+ gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
503
+ }
504
+
505
+ pci = PCI_HOST_BRIDGE(dev);
506
+ if (pci->bus) {
507
+ for (i = 0; i < nb_nics; i++) {
508
+ NICInfo *nd = &nd_table[i];
509
+
510
+ if (!nd->model) {
511
+ nd->model = g_strdup("e1000e");
512
+ }
513
+
514
+ pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
515
+ }
516
+ }
517
+
518
+ pci_create_simple(pci->bus, -1, "VGA");
519
+
520
+ create_smmu(sms, pic, pci->bus);
521
+}
522
+
523
+static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size)
524
+{
525
+ const SBSAMachineState *board = container_of(binfo, SBSAMachineState,
526
+ bootinfo);
527
+
528
+ *fdt_size = board->fdt_size;
529
+ return board->fdt;
530
+}
531
+
532
static void sbsa_ref_init(MachineState *machine)
533
{
534
SBSAMachineState *sms = SBSA_MACHINE(machine);
535
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
536
MemoryRegion *sysmem = get_system_memory();
537
MemoryRegion *secure_sysmem = NULL;
538
MemoryRegion *ram = g_new(MemoryRegion, 1);
539
+ bool firmware_loaded;
540
const CPUArchIdList *possible_cpus;
541
int n, sbsa_max_cpus;
542
+ qemu_irq pic[NUM_IRQS];
543
544
if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) {
545
error_report("sbsa-ref: CPU type other than the built-in "
546
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
547
exit(1);
548
}
549
550
+ /*
551
+ * The Secure view of the world is the same as the NonSecure,
552
+ * but with a few extra devices. Create it as a container region
553
+ * containing the system memory at low priority; any secure-only
554
+ * devices go in at higher priority and take precedence.
555
+ */
556
+ secure_sysmem = g_new(MemoryRegion, 1);
557
+ memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
558
+ UINT64_MAX);
559
+ memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
560
+
561
+ firmware_loaded = sbsa_firmware_init(sms, sysmem,
562
+ secure_sysmem ?: sysmem);
563
+
564
+ if (machine->kernel_filename && firmware_loaded) {
565
+ error_report("sbsa-ref: No fw_cfg device on this machine, "
566
+ "so -kernel option is not supported when firmware loaded, "
567
+ "please load OS from hard disk instead");
568
+ exit(1);
569
+ }
570
+
571
/*
572
* This machine has EL3 enabled, external firmware should supply PSCI
573
* implementation, so the QEMU's internal PSCI is disabled.
574
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
575
machine->ram_size);
576
memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, ram);
577
578
+ create_fdt(sms);
579
+
580
+ create_secure_ram(sms, secure_sysmem);
581
+
582
+ create_gic(sms, pic);
583
+
584
+ create_uart(sms, pic, SBSA_UART, sysmem, serial_hd(0));
585
+ create_uart(sms, pic, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
586
+ /* Second secure UART for RAS and MM from EL0 */
587
+ create_uart(sms, pic, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2));
588
+
589
+ create_rtc(sms, pic);
590
+
591
+ create_gpio(sms, pic);
592
+
593
+ create_ahci(sms, pic);
594
+
595
+ create_ehci(sms, pic);
596
+
597
+ create_pcie(sms, pic);
598
+
599
sms->bootinfo.ram_size = machine->ram_size;
600
sms->bootinfo.kernel_filename = machine->kernel_filename;
601
sms->bootinfo.nb_cpus = smp_cpus;
602
sms->bootinfo.board_id = -1;
603
sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base;
604
+ sms->bootinfo.get_dtb = sbsa_ref_dtb;
605
+ sms->bootinfo.firmware_loaded = firmware_loaded;
606
arm_load_kernel(ARM_CPU(first_cpu), &sms->bootinfo);
607
}
84
}
608
85
609
@@ -XXX,XX +XXX,XX @@ sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx)
86
-/*----------------------------------------------------------------------------
610
return idx % nb_numa_nodes;
87
-| Takes two extended double-precision floating-point values `a' and `b', one
611
}
88
-| of which is a NaN, and returns the appropriate NaN result. If either `a' or
612
89
-| `b' is a signaling NaN, the invalid exception is raised.
613
+static void sbsa_ref_instance_init(Object *obj)
90
-*----------------------------------------------------------------------------*/
614
+{
91
-
615
+ SBSAMachineState *sms = SBSA_MACHINE(obj);
92
-floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
616
+
93
-{
617
+ sbsa_flash_create(sms);
94
- bool aIsLargerSignificand;
618
+}
95
- FloatClass a_cls, b_cls;
619
+
96
-
620
static void sbsa_ref_class_init(ObjectClass *oc, void *data)
97
- /* This is not complete, but is good enough for pickNaN. */
621
{
98
- a_cls = (!floatx80_is_any_nan(a)
622
MachineClass *mc = MACHINE_CLASS(oc);
99
- ? float_class_normal
623
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_class_init(ObjectClass *oc, void *data)
100
- : floatx80_is_signaling_nan(a, status)
624
static const TypeInfo sbsa_ref_info = {
101
- ? float_class_snan
625
.name = TYPE_SBSA_MACHINE,
102
- : float_class_qnan);
626
.parent = TYPE_MACHINE,
103
- b_cls = (!floatx80_is_any_nan(b)
627
+ .instance_init = sbsa_ref_instance_init,
104
- ? float_class_normal
628
.class_init = sbsa_ref_class_init,
105
- : floatx80_is_signaling_nan(b, status)
629
.instance_size = sizeof(SBSAMachineState),
106
- ? float_class_snan
630
};
107
- : float_class_qnan);
108
-
109
- if (is_snan(a_cls) || is_snan(b_cls)) {
110
- float_raise(float_flag_invalid, status);
111
- }
112
-
113
- if (status->default_nan_mode) {
114
- return floatx80_default_nan(status);
115
- }
116
-
117
- if (a.low < b.low) {
118
- aIsLargerSignificand = 0;
119
- } else if (b.low < a.low) {
120
- aIsLargerSignificand = 1;
121
- } else {
122
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
123
- }
124
-
125
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
126
- if (is_snan(b_cls)) {
127
- return floatx80_silence_nan(b, status);
128
- }
129
- return b;
130
- } else {
131
- if (is_snan(a_cls)) {
132
- return floatx80_silence_nan(a, status);
133
- }
134
- return a;
135
- }
136
-}
137
-
138
/*----------------------------------------------------------------------------
139
| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
140
| NaN; otherwise returns 0.
631
--
141
--
632
2.20.1
142
2.34.1
633
634
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/46] i.mx7d: Add no-op/unimplemented APBH DMA module
[PULL 66/72] softfloat: Use parts_pick_nan in propagateFloatx80NaN
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Instantiate no-op APBH DMA module. Needed to boot latest Linux kernel.
3
Unpacking and repacking the parts may be slightly more work
4
than we did before, but we get to reuse more code. For a
5
code path handling exceptional values, this is an improvement.
4
6
5
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Cc: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-8-richard.henderson@linaro.org
7
Cc: Michael S. Tsirkin <mst@redhat.com>
8
Cc: qemu-devel@nongnu.org
9
Cc: qemu-arm@nongnu.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
---
11
---
13
include/hw/arm/fsl-imx7.h | 3 +++
12
fpu/softfloat.c | 43 +++++--------------------------------------
14
hw/arm/fsl-imx7.c | 6 ++++++
13
1 file changed, 5 insertions(+), 38 deletions(-)
15
2 files changed, 9 insertions(+)
16
14
17
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/fsl-imx7.h
17
--- a/fpu/softfloat.c
20
+++ b/include/hw/arm/fsl-imx7.h
18
+++ b/fpu/softfloat.c
21
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
22
FSL_IMX7_PCIE_REG_SIZE = 16 * 1024,
20
23
21
floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
24
FSL_IMX7_GPR_ADDR = 0x30340000,
22
{
25
+
23
- bool aIsLargerSignificand;
26
+ FSL_IMX7_DMA_APBH_ADDR = 0x33000000,
24
- FloatClass a_cls, b_cls;
27
+ FSL_IMX7_DMA_APBH_SIZE = 0x2000,
25
+ FloatParts128 pa, pb, *pr;
28
};
26
29
27
- /* This is not complete, but is good enough for pickNaN. */
30
enum FslIMX7IRQs {
28
- a_cls = (!floatx80_is_any_nan(a)
31
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
29
- ? float_class_normal
32
index XXXXXXX..XXXXXXX 100644
30
- : floatx80_is_signaling_nan(a, status)
33
--- a/hw/arm/fsl-imx7.c
31
- ? float_class_snan
34
+++ b/hw/arm/fsl-imx7.c
32
- : float_class_qnan);
35
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
33
- b_cls = (!floatx80_is_any_nan(b)
36
*/
34
- ? float_class_normal
37
create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR,
35
- : floatx80_is_signaling_nan(b, status)
38
FSL_IMX7_LCDIF_SIZE);
36
- ? float_class_snan
39
+
37
- : float_class_qnan);
40
+ /*
38
-
41
+ * DMA APBH
39
- if (is_snan(a_cls) || is_snan(b_cls)) {
42
+ */
40
- float_raise(float_flag_invalid, status);
43
+ create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR,
41
- }
44
+ FSL_IMX7_DMA_APBH_SIZE);
42
-
43
- if (status->default_nan_mode) {
44
+ if (!floatx80_unpack_canonical(&pa, a, status) ||
45
+ !floatx80_unpack_canonical(&pb, b, status)) {
46
return floatx80_default_nan(status);
47
}
48
49
- if (a.low < b.low) {
50
- aIsLargerSignificand = 0;
51
- } else if (b.low < a.low) {
52
- aIsLargerSignificand = 1;
53
- } else {
54
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
55
- }
56
-
57
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
58
- if (is_snan(b_cls)) {
59
- return floatx80_silence_nan(b, status);
60
- }
61
- return b;
62
- } else {
63
- if (is_snan(a_cls)) {
64
- return floatx80_silence_nan(a, status);
65
- }
66
- return a;
67
- }
68
+ pr = parts_pick_nan(&pa, &pb, status);
69
+ return floatx80_round_pack_canonical(pr, status);
45
}
70
}
46
71
47
static void fsl_imx7_class_init(ObjectClass *oc, void *data)
72
/*----------------------------------------------------------------------------
48
--
73
--
49
2.20.1
74
2.34.1
50
51
diff view generated by jsdifflib
[Qemu-devel] [PULL 46/46] target/arm: Declare some M-profile functions publicly
[PULL 67/72] softfloat: Inline pickNaN
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
In the next commit we will split the M-profile functions from this
3
Inline pickNaN into its only caller. This makes one assert
4
file. Some function will be called out of helper.c. Declare them in
4
redundant with the immediately preceding IF.
5
the "internals.h" header.
5
6
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20241203203949.483774-9-richard.henderson@linaro.org
9
Message-id: 20190701132516.26392-22-philmd@redhat.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/internals.h | 42 ++++++++++++++++++++++++++++++++++++++++++
11
fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++----
13
target/arm/helper.c | 38 ++------------------------------------
12
fpu/softfloat-specialize.c.inc | 96 ----------------------------------
14
2 files changed, 44 insertions(+), 36 deletions(-)
13
2 files changed, 73 insertions(+), 105 deletions(-)
15
14
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
15
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/internals.h
17
--- a/fpu/softfloat-parts.c.inc
19
+++ b/target/arm/internals.h
18
+++ b/fpu/softfloat-parts.c.inc
20
@@ -XXX,XX +XXX,XX @@ static inline uint32_t v7m_sp_limit(CPUARMState *env)
19
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
20
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
21
float_status *s)
22
{
23
+ int cmp, which;
24
+
25
if (is_snan(a->cls) || is_snan(b->cls)) {
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
27
}
28
29
if (s->default_nan_mode) {
30
parts_default_nan(a, s);
31
- } else {
32
- int cmp = frac_cmp(a, b);
33
- if (cmp == 0) {
34
- cmp = a->sign < b->sign;
35
- }
36
+ return a;
37
+ }
38
39
- if (pickNaN(a->cls, b->cls, cmp > 0, s)) {
40
- a = b;
41
- }
42
+ cmp = frac_cmp(a, b);
43
+ if (cmp == 0) {
44
+ cmp = a->sign < b->sign;
45
+ }
46
+
47
+ switch (s->float_2nan_prop_rule) {
48
+ case float_2nan_prop_s_ab:
49
if (is_snan(a->cls)) {
50
- parts_silence_nan(a, s);
51
+ which = 0;
52
+ } else if (is_snan(b->cls)) {
53
+ which = 1;
54
+ } else if (is_qnan(a->cls)) {
55
+ which = 0;
56
+ } else {
57
+ which = 1;
58
}
59
+ break;
60
+ case float_2nan_prop_s_ba:
61
+ if (is_snan(b->cls)) {
62
+ which = 1;
63
+ } else if (is_snan(a->cls)) {
64
+ which = 0;
65
+ } else if (is_qnan(b->cls)) {
66
+ which = 1;
67
+ } else {
68
+ which = 0;
69
+ }
70
+ break;
71
+ case float_2nan_prop_ab:
72
+ which = is_nan(a->cls) ? 0 : 1;
73
+ break;
74
+ case float_2nan_prop_ba:
75
+ which = is_nan(b->cls) ? 1 : 0;
76
+ break;
77
+ case float_2nan_prop_x87:
78
+ /*
79
+ * This implements x87 NaN propagation rules:
80
+ * SNaN + QNaN => return the QNaN
81
+ * two SNaNs => return the one with the larger significand, silenced
82
+ * two QNaNs => return the one with the larger significand
83
+ * SNaN and a non-NaN => return the SNaN, silenced
84
+ * QNaN and a non-NaN => return the QNaN
85
+ *
86
+ * If we get down to comparing significands and they are the same,
87
+ * return the NaN with the positive sign bit (if any).
88
+ */
89
+ if (is_snan(a->cls)) {
90
+ if (is_snan(b->cls)) {
91
+ which = cmp > 0 ? 0 : 1;
92
+ } else {
93
+ which = is_qnan(b->cls) ? 1 : 0;
94
+ }
95
+ } else if (is_qnan(a->cls)) {
96
+ if (is_snan(b->cls) || !is_qnan(b->cls)) {
97
+ which = 0;
98
+ } else {
99
+ which = cmp > 0 ? 0 : 1;
100
+ }
101
+ } else {
102
+ which = 1;
103
+ }
104
+ break;
105
+ default:
106
+ g_assert_not_reached();
107
+ }
108
+
109
+ if (which) {
110
+ a = b;
111
+ }
112
+ if (is_snan(a->cls)) {
113
+ parts_silence_nan(a, s);
114
}
115
return a;
116
}
117
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
118
index XXXXXXX..XXXXXXX 100644
119
--- a/fpu/softfloat-specialize.c.inc
120
+++ b/fpu/softfloat-specialize.c.inc
121
@@ -XXX,XX +XXX,XX @@ bool float32_is_signaling_nan(float32 a_, float_status *status)
21
}
122
}
22
}
123
}
23
124
24
+/**
125
-/*----------------------------------------------------------------------------
25
+ * v7m_cpacr_pass:
126
-| Select which NaN to propagate for a two-input operation.
26
+ * Return true if the v7M CPACR permits access to the FPU for the specified
127
-| IEEE754 doesn't specify all the details of this, so the
27
+ * security state and privilege level.
128
-| algorithm is target-specific.
28
+ */
129
-| The routine is passed various bits of information about the
29
+static inline bool v7m_cpacr_pass(CPUARMState *env,
130
-| two NaNs and should return 0 to select NaN a and 1 for NaN b.
30
+ bool is_secure, bool is_priv)
131
-| Note that signalling NaNs are always squashed to quiet NaNs
31
+{
132
-| by the caller, by calling floatXX_silence_nan() before
32
+ switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {
133
-| returning them.
33
+ case 0:
134
-|
34
+ case 2: /* UNPREDICTABLE: we treat like 0 */
135
-| aIsLargerSignificand is only valid if both a and b are NaNs
35
+ return false;
136
-| of some kind, and is true if a has the larger significand,
36
+ case 1:
137
-| or if both a and b have the same significand but a is
37
+ return is_priv;
138
-| positive but b is negative. It is only needed for the x87
38
+ case 3:
139
-| tie-break rule.
39
+ return true;
140
-*----------------------------------------------------------------------------*/
40
+ default:
41
+ g_assert_not_reached();
42
+ }
43
+}
44
+
45
/**
46
* aarch32_mode_name(): Return name of the AArch32 CPU mode
47
* @psr: Program Status Register indicating CPU mode
48
@@ -XXX,XX +XXX,XX @@ static inline int exception_target_el(CPUARMState *env)
49
50
#ifndef CONFIG_USER_ONLY
51
52
+/* Security attributes for an address, as returned by v8m_security_lookup. */
53
+typedef struct V8M_SAttributes {
54
+ bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */
55
+ bool ns;
56
+ bool nsc;
57
+ uint8_t sregion;
58
+ bool srvalid;
59
+ uint8_t iregion;
60
+ bool irvalid;
61
+} V8M_SAttributes;
62
+
63
+void v8m_security_lookup(CPUARMState *env, uint32_t address,
64
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
65
+ V8M_SAttributes *sattrs);
66
+
67
+bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
68
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
69
+ hwaddr *phys_ptr, MemTxAttrs *txattrs,
70
+ int *prot, bool *is_subpage,
71
+ ARMMMUFaultInfo *fi, uint32_t *mregion);
72
+
73
/* Cacheability and shareability attributes for a memory access */
74
typedef struct ARMCacheAttrs {
75
unsigned int attrs:8; /* as in the MAIR register encoding */
76
diff --git a/target/arm/helper.c b/target/arm/helper.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/helper.c
79
+++ b/target/arm/helper.c
80
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
81
hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
82
target_ulong *page_size_ptr,
83
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
84
-
141
-
85
-/* Security attributes for an address, as returned by v8m_security_lookup. */
142
-static int pickNaN(FloatClass a_cls, FloatClass b_cls,
86
-typedef struct V8M_SAttributes {
143
- bool aIsLargerSignificand, float_status *status)
87
- bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */
144
-{
88
- bool ns;
145
- /*
89
- bool nsc;
146
- * We guarantee not to require the target to tell us how to
90
- uint8_t sregion;
147
- * pick a NaN if we're always returning the default NaN.
91
- bool srvalid;
148
- * But if we're not in default-NaN mode then the target must
92
- uint8_t iregion;
149
- * specify via set_float_2nan_prop_rule().
93
- bool irvalid;
150
- */
94
-} V8M_SAttributes;
151
- assert(!status->default_nan_mode);
95
-
152
-
96
-static void v8m_security_lookup(CPUARMState *env, uint32_t address,
153
- switch (status->float_2nan_prop_rule) {
97
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
154
- case float_2nan_prop_s_ab:
98
- V8M_SAttributes *sattrs);
155
- if (is_snan(a_cls)) {
99
#endif
156
- return 0;
100
157
- } else if (is_snan(b_cls)) {
101
static void switch_mode(CPUARMState *env, int mode);
158
- return 1;
102
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(int idx)
159
- } else if (is_qnan(a_cls)) {
103
}
160
- return 0;
104
}
161
- } else {
105
162
- return 1;
106
-/*
163
- }
107
- * Return true if the v7M CPACR permits access to the FPU for the specified
164
- break;
108
- * security state and privilege level.
165
- case float_2nan_prop_s_ba:
109
- */
166
- if (is_snan(b_cls)) {
110
-static bool v7m_cpacr_pass(CPUARMState *env, bool is_secure, bool is_priv)
167
- return 1;
111
-{
168
- } else if (is_snan(a_cls)) {
112
- switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {
169
- return 0;
113
- case 0:
170
- } else if (is_qnan(b_cls)) {
114
- case 2: /* UNPREDICTABLE: we treat like 0 */
171
- return 1;
115
- return false;
172
- } else {
116
- case 1:
173
- return 0;
117
- return is_priv;
174
- }
118
- case 3:
175
- break;
119
- return true;
176
- case float_2nan_prop_ab:
177
- if (is_nan(a_cls)) {
178
- return 0;
179
- } else {
180
- return 1;
181
- }
182
- break;
183
- case float_2nan_prop_ba:
184
- if (is_nan(b_cls)) {
185
- return 1;
186
- } else {
187
- return 0;
188
- }
189
- break;
190
- case float_2nan_prop_x87:
191
- /*
192
- * This implements x87 NaN propagation rules:
193
- * SNaN + QNaN => return the QNaN
194
- * two SNaNs => return the one with the larger significand, silenced
195
- * two QNaNs => return the one with the larger significand
196
- * SNaN and a non-NaN => return the SNaN, silenced
197
- * QNaN and a non-NaN => return the QNaN
198
- *
199
- * If we get down to comparing significands and they are the same,
200
- * return the NaN with the positive sign bit (if any).
201
- */
202
- if (is_snan(a_cls)) {
203
- if (is_snan(b_cls)) {
204
- return aIsLargerSignificand ? 0 : 1;
205
- }
206
- return is_qnan(b_cls) ? 1 : 0;
207
- } else if (is_qnan(a_cls)) {
208
- if (is_snan(b_cls) || !is_qnan(b_cls)) {
209
- return 0;
210
- } else {
211
- return aIsLargerSignificand ? 0 : 1;
212
- }
213
- } else {
214
- return 1;
215
- }
120
- default:
216
- default:
121
- g_assert_not_reached();
217
- g_assert_not_reached();
122
- }
218
- }
123
-}
219
-}
124
-
220
-
125
/*
221
/*----------------------------------------------------------------------------
126
* What kind of stack write are we doing? This affects how exceptions
222
| Returns 1 if the double-precision floating-point value `a' is a quiet
127
* generated during the stacking are treated.
223
| NaN; otherwise returns 0.
128
@@ -XXX,XX +XXX,XX @@ static bool v8m_is_sau_exempt(CPUARMState *env,
129
(address >= 0xe00ff000 && address <= 0xe00fffff);
130
}
131
132
-static void v8m_security_lookup(CPUARMState *env, uint32_t address,
133
+void v8m_security_lookup(CPUARMState *env, uint32_t address,
134
MMUAccessType access_type, ARMMMUIdx mmu_idx,
135
V8M_SAttributes *sattrs)
136
{
137
@@ -XXX,XX +XXX,XX @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address,
138
}
139
}
140
141
-static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
142
+bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
143
MMUAccessType access_type, ARMMMUIdx mmu_idx,
144
hwaddr *phys_ptr, MemTxAttrs *txattrs,
145
int *prot, bool *is_subpage,
146
--
224
--
147
2.20.1
225
2.34.1
148
226
149
227
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/46] hw: timer: Add ASPEED RTC device
[PULL 68/72] softfloat: Share code between parts_pick_nan cases
1
From: Joel Stanley <joel@jms.id.au>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The RTC is modeled to provide time and date functionality. It is
3
Remember if there was an SNaN, and use that to simplify
4
initialised at zero to match the hardware.
4
float_2nan_prop_s_{ab,ba} to only the snan component.
5
Then, fall through to the corresponding
6
float_2nan_prop_{ab,ba} case to handle any remaining
7
nans, which must be quiet.
5
8
6
There is no modelling of the alarm functionality, which includes the IRQ
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
line. As there is no guest code to exercise this function that is
8
acceptable for now.
9
10
Signed-off-by: Joel Stanley <joel@jms.id.au>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20190618165311.27066-4-clg@kaod.org
11
Message-id: 20241203203949.483774-10-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
13
---
15
hw/timer/Makefile.objs | 2 +-
14
fpu/softfloat-parts.c.inc | 32 ++++++++++++--------------------
16
include/hw/timer/aspeed_rtc.h | 31 ++++++
15
1 file changed, 12 insertions(+), 20 deletions(-)
17
hw/timer/aspeed_rtc.c | 180 ++++++++++++++++++++++++++++++++++
18
hw/timer/trace-events | 4 +
19
4 files changed, 216 insertions(+), 1 deletion(-)
20
create mode 100644 include/hw/timer/aspeed_rtc.h
21
create mode 100644 hw/timer/aspeed_rtc.c
22
16
23
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
24
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/timer/Makefile.objs
19
--- a/fpu/softfloat-parts.c.inc
26
+++ b/hw/timer/Makefile.objs
20
+++ b/fpu/softfloat-parts.c.inc
27
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
21
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
28
obj-$(CONFIG_ALLWINNER_A10_PIT) += allwinner-a10-pit.o
22
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
29
23
float_status *s)
30
common-obj-$(CONFIG_STM32F2XX_TIMER) += stm32f2xx_timer.o
24
{
31
-common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
25
+ bool have_snan = false;
32
+common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o aspeed_rtc.o
26
int cmp, which;
33
27
34
common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
28
if (is_snan(a->cls) || is_snan(b->cls)) {
35
common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o
29
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
36
diff --git a/include/hw/timer/aspeed_rtc.h b/include/hw/timer/aspeed_rtc.h
30
+ have_snan = true;
37
new file mode 100644
31
}
38
index XXXXXXX..XXXXXXX
32
39
--- /dev/null
33
if (s->default_nan_mode) {
40
+++ b/include/hw/timer/aspeed_rtc.h
34
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
41
@@ -XXX,XX +XXX,XX @@
35
42
+/*
36
switch (s->float_2nan_prop_rule) {
43
+ * ASPEED Real Time Clock
37
case float_2nan_prop_s_ab:
44
+ * Joel Stanley <joel@jms.id.au>
38
- if (is_snan(a->cls)) {
45
+ *
39
- which = 0;
46
+ * Copyright 2019 IBM Corp
40
- } else if (is_snan(b->cls)) {
47
+ * SPDX-License-Identifier: GPL-2.0-or-later
41
- which = 1;
48
+ */
42
- } else if (is_qnan(a->cls)) {
49
+#ifndef ASPEED_RTC_H
43
- which = 0;
50
+#define ASPEED_RTC_H
44
- } else {
51
+
45
- which = 1;
52
+#include <stdint.h>
46
+ if (have_snan) {
53
+
47
+ which = is_snan(a->cls) ? 0 : 1;
54
+#include "hw/hw.h"
48
+ break;
55
+#include "hw/irq.h"
49
}
56
+#include "hw/sysbus.h"
50
- break;
57
+
51
- case float_2nan_prop_s_ba:
58
+typedef struct AspeedRtcState {
52
- if (is_snan(b->cls)) {
59
+ SysBusDevice parent_obj;
53
- which = 1;
60
+
54
- } else if (is_snan(a->cls)) {
61
+ MemoryRegion iomem;
55
- which = 0;
62
+ qemu_irq irq;
56
- } else if (is_qnan(b->cls)) {
63
+
57
- which = 1;
64
+ uint32_t reg[0x18];
58
- } else {
65
+ int offset;
59
- which = 0;
66
+
60
- }
67
+} AspeedRtcState;
61
- break;
68
+
69
+#define TYPE_ASPEED_RTC "aspeed.rtc"
70
+#define ASPEED_RTC(obj) OBJECT_CHECK(AspeedRtcState, (obj), TYPE_ASPEED_RTC)
71
+
72
+#endif /* ASPEED_RTC_H */
73
diff --git a/hw/timer/aspeed_rtc.c b/hw/timer/aspeed_rtc.c
74
new file mode 100644
75
index XXXXXXX..XXXXXXX
76
--- /dev/null
77
+++ b/hw/timer/aspeed_rtc.c
78
@@ -XXX,XX +XXX,XX @@
79
+/*
80
+ * ASPEED Real Time Clock
81
+ * Joel Stanley <joel@jms.id.au>
82
+ *
83
+ * Copyright 2019 IBM Corp
84
+ * SPDX-License-Identifier: GPL-2.0-or-later
85
+ */
86
+
87
+#include "qemu/osdep.h"
88
+#include "qemu-common.h"
89
+#include "hw/timer/aspeed_rtc.h"
90
+#include "qemu/log.h"
91
+#include "qemu/timer.h"
92
+
93
+#include "trace.h"
94
+
95
+#define COUNTER1 (0x00 / 4)
96
+#define COUNTER2 (0x04 / 4)
97
+#define ALARM (0x08 / 4)
98
+#define CONTROL (0x10 / 4)
99
+#define ALARM_STATUS (0x14 / 4)
100
+
101
+#define RTC_UNLOCKED BIT(1)
102
+#define RTC_ENABLED BIT(0)
103
+
104
+static void aspeed_rtc_calc_offset(AspeedRtcState *rtc)
105
+{
106
+ struct tm tm;
107
+ uint32_t year, cent;
108
+ uint32_t reg1 = rtc->reg[COUNTER1];
109
+ uint32_t reg2 = rtc->reg[COUNTER2];
110
+
111
+ tm.tm_mday = (reg1 >> 24) & 0x1f;
112
+ tm.tm_hour = (reg1 >> 16) & 0x1f;
113
+ tm.tm_min = (reg1 >> 8) & 0x3f;
114
+ tm.tm_sec = (reg1 >> 0) & 0x3f;
115
+
116
+ cent = (reg2 >> 16) & 0x1f;
117
+ year = (reg2 >> 8) & 0x7f;
118
+ tm.tm_mon = ((reg2 >> 0) & 0x0f) - 1;
119
+ tm.tm_year = year + (cent * 100) - 1900;
120
+
121
+ rtc->offset = qemu_timedate_diff(&tm);
122
+}
123
+
124
+static uint32_t aspeed_rtc_get_counter(AspeedRtcState *rtc, int r)
125
+{
126
+ uint32_t year, cent;
127
+ struct tm now;
128
+
129
+ qemu_get_timedate(&now, rtc->offset);
130
+
131
+ switch (r) {
132
+ case COUNTER1:
133
+ return (now.tm_mday << 24) | (now.tm_hour << 16) |
134
+ (now.tm_min << 8) | now.tm_sec;
135
+ case COUNTER2:
136
+ cent = (now.tm_year + 1900) / 100;
137
+ year = now.tm_year % 100;
138
+ return ((cent & 0x1f) << 16) | ((year & 0x7f) << 8) |
139
+ ((now.tm_mon + 1) & 0xf);
140
+ default:
141
+ g_assert_not_reached();
142
+ }
143
+}
144
+
145
+static uint64_t aspeed_rtc_read(void *opaque, hwaddr addr,
146
+ unsigned size)
147
+{
148
+ AspeedRtcState *rtc = opaque;
149
+ uint64_t val;
150
+ uint32_t r = addr >> 2;
151
+
152
+ switch (r) {
153
+ case COUNTER1:
154
+ case COUNTER2:
155
+ if (rtc->reg[CONTROL] & RTC_ENABLED) {
156
+ rtc->reg[r] = aspeed_rtc_get_counter(rtc, r);
157
+ }
158
+ /* fall through */
62
+ /* fall through */
159
+ case CONTROL:
63
case float_2nan_prop_ab:
160
+ val = rtc->reg[r];
64
which = is_nan(a->cls) ? 0 : 1;
161
+ break;
65
break;
162
+ case ALARM:
66
+ case float_2nan_prop_s_ba:
163
+ case ALARM_STATUS:
67
+ if (have_snan) {
164
+ default:
68
+ which = is_snan(b->cls) ? 1 : 0;
165
+ qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx "\n", __func__, addr);
166
+ return 0;
167
+ }
168
+
169
+ trace_aspeed_rtc_read(addr, val);
170
+
171
+ return val;
172
+}
173
+
174
+static void aspeed_rtc_write(void *opaque, hwaddr addr,
175
+ uint64_t val, unsigned size)
176
+{
177
+ AspeedRtcState *rtc = opaque;
178
+ uint32_t r = addr >> 2;
179
+
180
+ switch (r) {
181
+ case COUNTER1:
182
+ case COUNTER2:
183
+ if (!(rtc->reg[CONTROL] & RTC_UNLOCKED)) {
184
+ break;
69
+ break;
185
+ }
70
+ }
186
+ /* fall through */
71
+ /* fall through */
187
+ case CONTROL:
72
case float_2nan_prop_ba:
188
+ rtc->reg[r] = val;
73
which = is_nan(b->cls) ? 1 : 0;
189
+ aspeed_rtc_calc_offset(rtc);
74
break;
190
+ break;
191
+ case ALARM:
192
+ case ALARM_STATUS:
193
+ default:
194
+ qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx "\n", __func__, addr);
195
+ break;
196
+ }
197
+ trace_aspeed_rtc_write(addr, val);
198
+}
199
+
200
+static void aspeed_rtc_reset(DeviceState *d)
201
+{
202
+ AspeedRtcState *rtc = ASPEED_RTC(d);
203
+
204
+ rtc->offset = 0;
205
+ memset(rtc->reg, 0, sizeof(rtc->reg));
206
+}
207
+
208
+static const MemoryRegionOps aspeed_rtc_ops = {
209
+ .read = aspeed_rtc_read,
210
+ .write = aspeed_rtc_write,
211
+ .endianness = DEVICE_NATIVE_ENDIAN,
212
+};
213
+
214
+static const VMStateDescription vmstate_aspeed_rtc = {
215
+ .name = TYPE_ASPEED_RTC,
216
+ .version_id = 1,
217
+ .fields = (VMStateField[]) {
218
+ VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18),
219
+ VMSTATE_INT32(offset, AspeedRtcState),
220
+ VMSTATE_INT32(offset, AspeedRtcState),
221
+ VMSTATE_END_OF_LIST()
222
+ }
223
+};
224
+
225
+static void aspeed_rtc_realize(DeviceState *dev, Error **errp)
226
+{
227
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
228
+ AspeedRtcState *s = ASPEED_RTC(dev);
229
+
230
+ sysbus_init_irq(sbd, &s->irq);
231
+
232
+ memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_rtc_ops, s,
233
+ "aspeed-rtc", 0x18ULL);
234
+ sysbus_init_mmio(sbd, &s->iomem);
235
+}
236
+
237
+static void aspeed_rtc_class_init(ObjectClass *klass, void *data)
238
+{
239
+ DeviceClass *dc = DEVICE_CLASS(klass);
240
+
241
+ dc->realize = aspeed_rtc_realize;
242
+ dc->vmsd = &vmstate_aspeed_rtc;
243
+ dc->reset = aspeed_rtc_reset;
244
+}
245
+
246
+static const TypeInfo aspeed_rtc_info = {
247
+ .name = TYPE_ASPEED_RTC,
248
+ .parent = TYPE_SYS_BUS_DEVICE,
249
+ .instance_size = sizeof(AspeedRtcState),
250
+ .class_init = aspeed_rtc_class_init,
251
+};
252
+
253
+static void aspeed_rtc_register_types(void)
254
+{
255
+ type_register_static(&aspeed_rtc_info);
256
+}
257
+
258
+type_init(aspeed_rtc_register_types)
259
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
260
index XXXXXXX..XXXXXXX 100644
261
--- a/hw/timer/trace-events
262
+++ b/hw/timer/trace-events
263
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_dualtimer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK A
264
cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB dualtimer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
265
cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
266
267
+# hw/timer/aspeed-rtc.c
268
+aspeed_rtc_read(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64
269
+aspeed_rtc_write(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64
270
+
271
# sun4v-rtc.c
272
sun4v_rtc_read(uint64_t addr, uint64_t value) "read: addr 0x%" PRIx64 " value 0x%" PRIx64
273
sun4v_rtc_write(uint64_t addr, uint64_t value) "write: addr 0x%" PRIx64 " value 0x%" PRIx64
274
--
75
--
275
2.20.1
76
2.34.1
276
277
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/46] hw/arm/boot: fix direct kernel boot with initrd
[PULL 69/72] softfloat: Sink frac_cmp in parts_pick_nan until needed
1
From: Andrew Jones <drjones@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Fix the condition used to check whether the initrd fits
3
Move the fractional comparison to the end of the
4
into RAM; in some cases if an initrd was also passed on
4
float_2nan_prop_x87 case. This is not required for
5
the command line we would get an error stating that it
5
any other 2nan propagation rule. Reorganize the
6
was too big to fit into RAM after the kernel. Despite the
6
x87 case itself to break out of the switch when the
7
error the loader continued anyway, though, so also add an
7
fractional comparison is not required.
8
exit(1) when the initrd is actually too big.
9
8
10
Fixes: 852dc64d665f ("hw/arm/boot: Diagnose layouts that put initrd or
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
DTB off the end of RAM")
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Andrew Jones <drjones@redhat.com>
11
Message-id: 20241203203949.483774-11-richard.henderson@linaro.org
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Message-id: 20190618125844.4863-1-drjones@redhat.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
13
---
17
hw/arm/boot.c | 3 ++-
14
fpu/softfloat-parts.c.inc | 19 +++++++++----------
18
1 file changed, 2 insertions(+), 1 deletion(-)
15
1 file changed, 9 insertions(+), 10 deletions(-)
19
16
20
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
21
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/boot.c
19
--- a/fpu/softfloat-parts.c.inc
23
+++ b/hw/arm/boot.c
20
+++ b/fpu/softfloat-parts.c.inc
24
@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
21
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
25
info->initrd_filename);
22
return a;
26
exit(1);
23
}
24
25
- cmp = frac_cmp(a, b);
26
- if (cmp == 0) {
27
- cmp = a->sign < b->sign;
28
- }
29
-
30
switch (s->float_2nan_prop_rule) {
31
case float_2nan_prop_s_ab:
32
if (have_snan) {
33
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
34
* return the NaN with the positive sign bit (if any).
35
*/
36
if (is_snan(a->cls)) {
37
- if (is_snan(b->cls)) {
38
- which = cmp > 0 ? 0 : 1;
39
- } else {
40
+ if (!is_snan(b->cls)) {
41
which = is_qnan(b->cls) ? 1 : 0;
42
+ break;
27
}
43
}
28
- if (info->initrd_start + initrd_size > info->ram_size) {
44
} else if (is_qnan(a->cls)) {
29
+ if (info->initrd_start + initrd_size > ram_end) {
45
if (is_snan(b->cls) || !is_qnan(b->cls)) {
30
error_report("could not load initrd '%s': "
46
which = 0;
31
"too big to fit into RAM after the kernel",
47
- } else {
32
info->initrd_filename);
48
- which = cmp > 0 ? 0 : 1;
33
+ exit(1);
49
+ break;
34
}
50
}
35
} else {
51
} else {
36
initrd_size = 0;
52
which = 1;
53
+ break;
54
}
55
+ cmp = frac_cmp(a, b);
56
+ if (cmp == 0) {
57
+ cmp = a->sign < b->sign;
58
+ }
59
+ which = cmp > 0 ? 0 : 1;
60
break;
61
default:
62
g_assert_not_reached();
37
--
63
--
38
2.20.1
64
2.34.1
39
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/46] aspeed/timer: Fix behaviour running Linux
[PULL 70/72] softfloat: Replace WHICH with RET in parts_pick_nan
1
From: Joel Stanley <joel@jms.id.au>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Linux kernel driver was updated in commit 4451d3f59f2a
3
Replace the "index" selecting between A and B with a result variable
4
("clocksource/drivers/fttmr010: Fix set_next_event handler) to fix an
4
of the proper type. This improves clarity within the function.
5
issue observed on hardware:
6
5
7
> RELOAD register is loaded into COUNT register when the aspeed timer
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
> is enabled, which means the next event may be delayed because timer
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
> interrupt won't be generated until <0xFFFFFFFF - current_count +
8
Message-id: 20241203203949.483774-12-richard.henderson@linaro.org
10
> cycles>.
11
12
When running under Qemu, the system appeared "laggy". The guest is now
13
scheduling timer events too regularly, starving the host of CPU time.
14
15
This patch modifies the timer model to attempt to schedule the timer
16
expiry as the guest requests, but if we have missed the deadline we
17
re interrupt and try again, which allows the guest to catch up.
18
19
Provides expected behaviour with old and new guest code.
20
21
Fixes: c04bd47db6b9 ("hw/timer: Add ASPEED timer device model")
22
Signed-off-by: Joel Stanley <joel@jms.id.au>
23
Signed-off-by: Cédric Le Goater <clg@kaod.org>
24
Message-id: 20190618165311.27066-8-clg@kaod.org
25
[clg: - merged a fix from Andrew Jeffery <andrew@aj.id.au>
26
"Fire interrupt on failure to meet deadline"
27
https://lists.ozlabs.org/pipermail/openbmc/2019-January/014641.html
28
- adapted commit log
29
- checkpatch fixes ]
30
Signed-off-by: Cédric Le Goater <clg@kaod.org>
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
---
10
---
33
hw/timer/aspeed_timer.c | 57 ++++++++++++++++++++++-------------------
11
fpu/softfloat-parts.c.inc | 28 +++++++++++++---------------
34
1 file changed, 30 insertions(+), 27 deletions(-)
12
1 file changed, 13 insertions(+), 15 deletions(-)
35
13
36
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
37
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/timer/aspeed_timer.c
16
--- a/fpu/softfloat-parts.c.inc
39
+++ b/hw/timer/aspeed_timer.c
17
+++ b/fpu/softfloat-parts.c.inc
40
@@ -XXX,XX +XXX,XX @@ static inline uint64_t calculate_time(struct AspeedTimer *t, uint32_t ticks)
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
41
19
float_status *s)
42
static uint64_t calculate_next(struct AspeedTimer *t)
43
{
20
{
44
- uint64_t next = 0;
21
bool have_snan = false;
45
- uint32_t rate = calculate_rate(t);
22
- int cmp, which;
46
+ uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
23
+ FloatPartsN *ret;
47
+ uint64_t next;
24
+ int cmp;
48
25
49
- while (!next) {
26
if (is_snan(a->cls) || is_snan(b->cls)) {
50
- /* We don't know the relationship between the values in the match
27
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
51
- * registers, so sort using MAX/MIN/zero. We sort in that order as the
28
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
52
- * timer counts down to zero. */
29
switch (s->float_2nan_prop_rule) {
53
- uint64_t seq[] = {
30
case float_2nan_prop_s_ab:
54
- calculate_time(t, MAX(t->match[0], t->match[1])),
31
if (have_snan) {
55
- calculate_time(t, MIN(t->match[0], t->match[1])),
32
- which = is_snan(a->cls) ? 0 : 1;
56
- calculate_time(t, 0),
33
+ ret = is_snan(a->cls) ? a : b;
57
- };
34
break;
58
- uint64_t reload_ns;
35
}
59
- uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
36
/* fall through */
60
+ /*
37
case float_2nan_prop_ab:
61
+ * We don't know the relationship between the values in the match
38
- which = is_nan(a->cls) ? 0 : 1;
62
+ * registers, so sort using MAX/MIN/zero. We sort in that order as
39
+ ret = is_nan(a->cls) ? a : b;
63
+ * the timer counts down to zero.
40
break;
64
+ */
41
case float_2nan_prop_s_ba:
65
42
if (have_snan) {
66
- if (now < seq[0]) {
43
- which = is_snan(b->cls) ? 1 : 0;
67
- next = seq[0];
44
+ ret = is_snan(b->cls) ? b : a;
68
- } else if (now < seq[1]) {
45
break;
69
- next = seq[1];
46
}
70
- } else if (now < seq[2]) {
47
/* fall through */
71
- next = seq[2];
48
case float_2nan_prop_ba:
72
- } else if (t->reload) {
49
- which = is_nan(b->cls) ? 1 : 0;
73
- reload_ns = muldiv64(t->reload, NANOSECONDS_PER_SECOND, rate);
50
+ ret = is_nan(b->cls) ? b : a;
74
- t->start = now - ((now - t->start) % reload_ns);
51
break;
75
- } else {
52
case float_2nan_prop_x87:
76
- /* no reload value, return 0 */
53
/*
77
- break;
54
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
78
- }
55
*/
79
+ next = calculate_time(t, MAX(t->match[0], t->match[1]));
56
if (is_snan(a->cls)) {
80
+ if (now < next) {
57
if (!is_snan(b->cls)) {
81
+ return next;
58
- which = is_qnan(b->cls) ? 1 : 0;
59
+ ret = is_qnan(b->cls) ? b : a;
60
break;
61
}
62
} else if (is_qnan(a->cls)) {
63
if (is_snan(b->cls) || !is_qnan(b->cls)) {
64
- which = 0;
65
+ ret = a;
66
break;
67
}
68
} else {
69
- which = 1;
70
+ ret = b;
71
break;
72
}
73
cmp = frac_cmp(a, b);
74
if (cmp == 0) {
75
cmp = a->sign < b->sign;
76
}
77
- which = cmp > 0 ? 0 : 1;
78
+ ret = cmp > 0 ? a : b;
79
break;
80
default:
81
g_assert_not_reached();
82
}
82
}
83
83
84
- return next;
84
- if (which) {
85
+ next = calculate_time(t, MIN(t->match[0], t->match[1]));
85
- a = b;
86
+ if (now < next) {
86
+ if (is_snan(ret->cls)) {
87
+ return next;
87
+ parts_silence_nan(ret, s);
88
+ }
88
}
89
+
89
- if (is_snan(a->cls)) {
90
+ next = calculate_time(t, 0);
90
- parts_silence_nan(a, s);
91
+ if (now < next) {
91
- }
92
+ return next;
92
- return a;
93
+ }
93
+ return ret;
94
+
95
+ /* We've missed all deadlines, fire interrupt and try again */
96
+ timer_del(&t->timer);
97
+
98
+ if (timer_overflow_interrupt(t)) {
99
+ t->level = !t->level;
100
+ qemu_set_irq(t->irq, t->level);
101
+ }
102
+
103
+ t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
104
+ return calculate_time(t, MAX(MAX(t->match[0], t->match[1]), 0));
105
}
94
}
106
95
107
static void aspeed_timer_mod(AspeedTimer *t)
96
static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
108
--
97
--
109
2.20.1
98
2.34.1
110
99
111
100
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/46] pci: designware: Update MSI mapping unconditionally
[PULL 71/72] MAINTAINERS: update email address for Leif Lindholm
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
2
2
3
Expression to calculate update_msi_mapping in code handling writes to
3
I'm migrating to Qualcomm's new open source email infrastructure, so
4
DESIGNWARE_PCIE_MSI_INTR0_ENABLE is missing an ! operator and should
4
update my email address, and update the mailmap to match.
5
be:
6
5
7
!!root->msi.intr[0].enable ^ !!val;
6
Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
8
7
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
9
so that MSI mapping is updated when enabled transitions from either
8
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
10
"none" -> "any" or "any" -> "none". Since that register shouldn't be
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
written to very often, change the code to update MSI mapping
10
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
unconditionally instead of trying to fix the update_msi_mapping logic.
11
Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com
13
14
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
15
Cc: Peter Maydell <peter.maydell@linaro.org>
16
Cc: Michael S. Tsirkin <mst@redhat.com>
17
Cc: qemu-devel@nongnu.org
18
Cc: qemu-arm@nongnu.org
19
Acked-by: Michael S. Tsirkin <mst@redhat.com>
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
13
---
23
hw/pci-host/designware.c | 10 ++--------
14
MAINTAINERS | 2 +-
24
1 file changed, 2 insertions(+), 8 deletions(-)
15
.mailmap | 5 +++--
16
2 files changed, 4 insertions(+), 3 deletions(-)
25
17
26
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
18
diff --git a/MAINTAINERS b/MAINTAINERS
27
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/pci-host/designware.c
20
--- a/MAINTAINERS
29
+++ b/hw/pci-host/designware.c
21
+++ b/MAINTAINERS
30
@@ -XXX,XX +XXX,XX @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
22
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
31
root->msi.base |= (uint64_t)val << 32;
23
SBSA-REF
32
break;
24
M: Radoslaw Biernacki <rad@semihalf.com>
33
25
M: Peter Maydell <peter.maydell@linaro.org>
34
- case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: {
26
-R: Leif Lindholm <quic_llindhol@quicinc.com>
35
- const bool update_msi_mapping = !root->msi.intr[0].enable ^ !!val;
27
+R: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
36
-
28
R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
37
+ case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
29
L: qemu-arm@nongnu.org
38
root->msi.intr[0].enable = val;
30
S: Maintained
39
-
31
diff --git a/.mailmap b/.mailmap
40
- if (update_msi_mapping) {
32
index XXXXXXX..XXXXXXX 100644
41
- designware_pcie_root_update_msi_mapping(root);
33
--- a/.mailmap
42
- }
34
+++ b/.mailmap
43
+ designware_pcie_root_update_msi_mapping(root);
35
@@ -XXX,XX +XXX,XX @@ Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
44
break;
36
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
45
- }
37
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
46
38
Juan Quintela <quintela@trasno.org> <quintela@redhat.com>
47
case DESIGNWARE_PCIE_MSI_INTR0_MASK:
39
-Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
48
root->msi.intr[0].mask = val;
40
-Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
41
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <quic_llindhol@quicinc.com>
42
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif.lindholm@linaro.org>
43
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif@nuviainc.com>
44
Luc Michel <luc@lmichel.fr> <luc.michel@git.antfield.fr>
45
Luc Michel <luc@lmichel.fr> <luc.michel@greensocs.com>
46
Luc Michel <luc@lmichel.fr> <lmichel@kalray.eu>
49
--
47
--
50
2.20.1
48
2.34.1
51
49
52
50
diff view generated by jsdifflib
[Qemu-devel] [PULL 26/46] hw/arm: Add arm SBSA reference machine, skeleton part
[PULL 72/72] MAINTAINERS: Add correct email address for Vikram Garhwal
1
From: Hongbo Zhang <hongbo.zhang@linaro.org>
1
From: Vikram Garhwal <vikram.garhwal@bytedance.com>
2
2
3
For AArch64, the existing "virt" machine is primarily meant to
3
Previously, maintainer role was paused due to inactive email id. Commit id:
4
run on KVM and execute virtualization workloads, but we need an
4
c009d715721861984c4987bcc78b7ee183e86d75.
5
environment as faithful as possible to physical hardware, for supporting
6
firmware and OS development for physical Aarch64 machines.
7
5
8
This patch introduces new machine type 'sbsa-ref' with main features:
6
Signed-off-by: Vikram Garhwal <vikram.garhwal@bytedance.com>
9
- Based on 'virt' machine type.
7
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
10
- A new memory map.
8
Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com
11
- CPU type cortex-a57.
12
- EL2 and EL3 are enabled.
13
- GIC version 3.
14
- System bus AHCI controller.
15
- System bus EHCI controller.
16
- CDROM and hard disc on AHCI bus.
17
- E1000E ethernet card on PCIE bus.
18
- VGA display adaptor on PCIE bus.
19
- No virtio devices.
20
- No fw_cfg device.
21
- No ACPI table supplied.
22
- Only minimal device tree nodes.
23
24
Arm Trusted Firmware and UEFI porting to this are done accordingly,
25
and the firmware should supply ACPI tables to the guest OS. The
26
minimal device tree nodes supplied by QEMU for this platform are only
27
to pass the dynamic info reflecting command line input to firmware,
28
not for loading the guest OS.
29
30
To make the review easier, this task is split into two patches, the
31
fundamental skeleton part and the peripheral devices part; this patch is
32
the first part.
33
34
Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org>
35
Message-id: 1561890034-15921-2-git-send-email-hongbo.zhang@linaro.org
36
[PMM: commit message tweaks; moved some bits between patch 1 and 2
37
to ensure patch 1 builds cleanly; removed unneeded lines from
38
Kconfig stanza; only provide board for qemu-system-aarch64, not
39
qemu-system-arm; added MAINTAINERS entry]
40
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
41
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
42
---
10
---
43
hw/arm/Makefile.objs | 1 +
11
MAINTAINERS | 2 ++
44
hw/arm/sbsa-ref.c | 271 ++++++++++++++++++++++++++++
12
1 file changed, 2 insertions(+)
45
MAINTAINERS | 8 +
46
default-configs/aarch64-softmmu.mak | 1 +
47
hw/arm/Kconfig | 14 ++
48
5 files changed, 295 insertions(+)
49
create mode 100644 hw/arm/sbsa-ref.c
50
13
51
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/arm/Makefile.objs
54
+++ b/hw/arm/Makefile.objs
55
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_SPITZ) += spitz.o
56
obj-$(CONFIG_TOSA) += tosa.o
57
obj-$(CONFIG_Z2) += z2.o
58
obj-$(CONFIG_REALVIEW) += realview.o
59
+obj-$(CONFIG_SBSA_REF) += sbsa-ref.o
60
obj-$(CONFIG_STELLARIS) += stellaris.o
61
obj-$(CONFIG_COLLIE) += collie.o
62
obj-$(CONFIG_VERSATILE) += versatilepb.o
63
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
64
new file mode 100644
65
index XXXXXXX..XXXXXXX
66
--- /dev/null
67
+++ b/hw/arm/sbsa-ref.c
68
@@ -XXX,XX +XXX,XX @@
69
+/*
70
+ * ARM SBSA Reference Platform emulation
71
+ *
72
+ * Copyright (c) 2018 Linaro Limited
73
+ * Written by Hongbo Zhang <hongbo.zhang@linaro.org>
74
+ *
75
+ * This program is free software; you can redistribute it and/or modify it
76
+ * under the terms and conditions of the GNU General Public License,
77
+ * version 2 or later, as published by the Free Software Foundation.
78
+ *
79
+ * This program is distributed in the hope it will be useful, but WITHOUT
80
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
81
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
82
+ * more details.
83
+ *
84
+ * You should have received a copy of the GNU General Public License along with
85
+ * this program. If not, see <http://www.gnu.org/licenses/>.
86
+ */
87
+
88
+#include "qemu/osdep.h"
89
+#include "qapi/error.h"
90
+#include "qemu/error-report.h"
91
+#include "qemu/units.h"
92
+#include "sysemu/numa.h"
93
+#include "sysemu/sysemu.h"
94
+#include "exec/address-spaces.h"
95
+#include "exec/hwaddr.h"
96
+#include "kvm_arm.h"
97
+#include "hw/arm/boot.h"
98
+#include "hw/boards.h"
99
+#include "hw/intc/arm_gicv3_common.h"
100
+
101
+#define RAMLIMIT_GB 8192
102
+#define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
103
+
104
+enum {
105
+ SBSA_FLASH,
106
+ SBSA_MEM,
107
+ SBSA_CPUPERIPHS,
108
+ SBSA_GIC_DIST,
109
+ SBSA_GIC_REDIST,
110
+ SBSA_SMMU,
111
+ SBSA_UART,
112
+ SBSA_RTC,
113
+ SBSA_PCIE,
114
+ SBSA_PCIE_MMIO,
115
+ SBSA_PCIE_MMIO_HIGH,
116
+ SBSA_PCIE_PIO,
117
+ SBSA_PCIE_ECAM,
118
+ SBSA_GPIO,
119
+ SBSA_SECURE_UART,
120
+ SBSA_SECURE_UART_MM,
121
+ SBSA_SECURE_MEM,
122
+ SBSA_AHCI,
123
+ SBSA_EHCI,
124
+};
125
+
126
+typedef struct MemMapEntry {
127
+ hwaddr base;
128
+ hwaddr size;
129
+} MemMapEntry;
130
+
131
+typedef struct {
132
+ MachineState parent;
133
+ struct arm_boot_info bootinfo;
134
+ int smp_cpus;
135
+ void *fdt;
136
+ int fdt_size;
137
+ int psci_conduit;
138
+} SBSAMachineState;
139
+
140
+#define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref")
141
+#define SBSA_MACHINE(obj) \
142
+ OBJECT_CHECK(SBSAMachineState, (obj), TYPE_SBSA_MACHINE)
143
+
144
+static const MemMapEntry sbsa_ref_memmap[] = {
145
+ /* 512M boot ROM */
146
+ [SBSA_FLASH] = { 0, 0x20000000 },
147
+ /* 512M secure memory */
148
+ [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 },
149
+ /* Space reserved for CPU peripheral devices */
150
+ [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 },
151
+ [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 },
152
+ [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 },
153
+ [SBSA_UART] = { 0x60000000, 0x00001000 },
154
+ [SBSA_RTC] = { 0x60010000, 0x00001000 },
155
+ [SBSA_GPIO] = { 0x60020000, 0x00001000 },
156
+ [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 },
157
+ [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 },
158
+ [SBSA_SMMU] = { 0x60050000, 0x00020000 },
159
+ /* Space here reserved for more SMMUs */
160
+ [SBSA_AHCI] = { 0x60100000, 0x00010000 },
161
+ [SBSA_EHCI] = { 0x60110000, 0x00010000 },
162
+ /* Space here reserved for other devices */
163
+ [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 },
164
+ /* 32-bit address PCIE MMIO space */
165
+ [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 },
166
+ /* 256M PCIE ECAM space */
167
+ [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 },
168
+ /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */
169
+ [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL },
170
+ [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES },
171
+};
172
+
173
+static void sbsa_ref_init(MachineState *machine)
174
+{
175
+ SBSAMachineState *sms = SBSA_MACHINE(machine);
176
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
177
+ MemoryRegion *sysmem = get_system_memory();
178
+ MemoryRegion *secure_sysmem = NULL;
179
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
180
+ const CPUArchIdList *possible_cpus;
181
+ int n, sbsa_max_cpus;
182
+
183
+ if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) {
184
+ error_report("sbsa-ref: CPU type other than the built-in "
185
+ "cortex-a57 not supported");
186
+ exit(1);
187
+ }
188
+
189
+ if (kvm_enabled()) {
190
+ error_report("sbsa-ref: KVM is not supported for this machine");
191
+ exit(1);
192
+ }
193
+
194
+ /*
195
+ * This machine has EL3 enabled, external firmware should supply PSCI
196
+ * implementation, so the QEMU's internal PSCI is disabled.
197
+ */
198
+ sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
199
+
200
+ sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
201
+
202
+ if (max_cpus > sbsa_max_cpus) {
203
+ error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
204
+ "supported by machine 'sbsa-ref' (%d)",
205
+ max_cpus, sbsa_max_cpus);
206
+ exit(1);
207
+ }
208
+
209
+ sms->smp_cpus = smp_cpus;
210
+
211
+ if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) {
212
+ error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB);
213
+ exit(1);
214
+ }
215
+
216
+ possible_cpus = mc->possible_cpu_arch_ids(machine);
217
+ for (n = 0; n < possible_cpus->len; n++) {
218
+ Object *cpuobj;
219
+ CPUState *cs;
220
+
221
+ if (n >= smp_cpus) {
222
+ break;
223
+ }
224
+
225
+ cpuobj = object_new(possible_cpus->cpus[n].type);
226
+ object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,
227
+ "mp-affinity", NULL);
228
+
229
+ cs = CPU(cpuobj);
230
+ cs->cpu_index = n;
231
+
232
+ numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
233
+ &error_fatal);
234
+
235
+ if (object_property_find(cpuobj, "reset-cbar", NULL)) {
236
+ object_property_set_int(cpuobj,
237
+ sbsa_ref_memmap[SBSA_CPUPERIPHS].base,
238
+ "reset-cbar", &error_abort);
239
+ }
240
+
241
+ object_property_set_link(cpuobj, OBJECT(sysmem), "memory",
242
+ &error_abort);
243
+
244
+ object_property_set_link(cpuobj, OBJECT(secure_sysmem),
245
+ "secure-memory", &error_abort);
246
+
247
+ object_property_set_bool(cpuobj, true, "realized", &error_fatal);
248
+ object_unref(cpuobj);
249
+ }
250
+
251
+ memory_region_allocate_system_memory(ram, NULL, "sbsa-ref.ram",
252
+ machine->ram_size);
253
+ memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, ram);
254
+
255
+ sms->bootinfo.ram_size = machine->ram_size;
256
+ sms->bootinfo.kernel_filename = machine->kernel_filename;
257
+ sms->bootinfo.nb_cpus = smp_cpus;
258
+ sms->bootinfo.board_id = -1;
259
+ sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base;
260
+ arm_load_kernel(ARM_CPU(first_cpu), &sms->bootinfo);
261
+}
262
+
263
+static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
264
+{
265
+ uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
266
+ return arm_cpu_mp_affinity(idx, clustersz);
267
+}
268
+
269
+static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms)
270
+{
271
+ SBSAMachineState *sms = SBSA_MACHINE(ms);
272
+ int n;
273
+
274
+ if (ms->possible_cpus) {
275
+ assert(ms->possible_cpus->len == max_cpus);
276
+ return ms->possible_cpus;
277
+ }
278
+
279
+ ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
280
+ sizeof(CPUArchId) * max_cpus);
281
+ ms->possible_cpus->len = max_cpus;
282
+ for (n = 0; n < ms->possible_cpus->len; n++) {
283
+ ms->possible_cpus->cpus[n].type = ms->cpu_type;
284
+ ms->possible_cpus->cpus[n].arch_id =
285
+ sbsa_ref_cpu_mp_affinity(sms, n);
286
+ ms->possible_cpus->cpus[n].props.has_thread_id = true;
287
+ ms->possible_cpus->cpus[n].props.thread_id = n;
288
+ }
289
+ return ms->possible_cpus;
290
+}
291
+
292
+static CpuInstanceProperties
293
+sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
294
+{
295
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
296
+ const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
297
+
298
+ assert(cpu_index < possible_cpus->len);
299
+ return possible_cpus->cpus[cpu_index].props;
300
+}
301
+
302
+static int64_t
303
+sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx)
304
+{
305
+ return idx % nb_numa_nodes;
306
+}
307
+
308
+static void sbsa_ref_class_init(ObjectClass *oc, void *data)
309
+{
310
+ MachineClass *mc = MACHINE_CLASS(oc);
311
+
312
+ mc->init = sbsa_ref_init;
313
+ mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine";
314
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57");
315
+ mc->max_cpus = 512;
316
+ mc->pci_allow_0_address = true;
317
+ mc->minimum_page_bits = 12;
318
+ mc->block_default_type = IF_IDE;
319
+ mc->no_cdrom = 1;
320
+ mc->default_ram_size = 1 * GiB;
321
+ mc->default_cpus = 4;
322
+ mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids;
323
+ mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props;
324
+ mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id;
325
+}
326
+
327
+static const TypeInfo sbsa_ref_info = {
328
+ .name = TYPE_SBSA_MACHINE,
329
+ .parent = TYPE_MACHINE,
330
+ .class_init = sbsa_ref_class_init,
331
+ .instance_size = sizeof(SBSAMachineState),
332
+};
333
+
334
+static void sbsa_ref_machine_init(void)
335
+{
336
+ type_register_static(&sbsa_ref_info);
337
+}
338
+
339
+type_init(sbsa_ref_machine_init);
340
diff --git a/MAINTAINERS b/MAINTAINERS
14
diff --git a/MAINTAINERS b/MAINTAINERS
341
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
342
--- a/MAINTAINERS
16
--- a/MAINTAINERS
343
+++ b/MAINTAINERS
17
+++ b/MAINTAINERS
344
@@ -XXX,XX +XXX,XX @@ F: include/hw/arm/fsl-imx6.h
18
@@ -XXX,XX +XXX,XX @@ F: tests/qtest/fuzz-sb16-test.c
345
F: include/hw/misc/imx6_*.h
19
346
F: include/hw/ssi/imx_spi.h
20
Xilinx CAN
347
21
M: Francisco Iglesias <francisco.iglesias@amd.com>
348
+SBSA-REF
22
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
349
+M: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
23
S: Maintained
350
+M: Peter Maydell <peter.maydell@linaro.org>
24
F: hw/net/can/xlnx-*
351
+R: Leif Lindholm <leif.lindholm@linaro.org>
25
F: include/hw/net/xlnx-*
352
+L: qemu-arm@nongnu.org
26
@@ -XXX,XX +XXX,XX @@ F: include/hw/rx/
353
+S: Maintained
27
CAN bus subsystem and hardware
354
+F: hw/arm/sbsa-ref.c
28
M: Pavel Pisa <pisa@cmp.felk.cvut.cz>
355
+
29
M: Francisco Iglesias <francisco.iglesias@amd.com>
356
Sharp SL-5500 (Collie) PDA
30
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
357
M: Peter Maydell <peter.maydell@linaro.org>
31
S: Maintained
358
L: qemu-arm@nongnu.org
32
W: https://canbus.pages.fel.cvut.cz/
359
diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-softmmu.mak
33
F: net/can/*
360
index XXXXXXX..XXXXXXX 100644
361
--- a/default-configs/aarch64-softmmu.mak
362
+++ b/default-configs/aarch64-softmmu.mak
363
@@ -XXX,XX +XXX,XX @@ include arm-softmmu.mak
364
365
CONFIG_XLNX_ZYNQMP_ARM=y
366
CONFIG_XLNX_VERSAL=y
367
+CONFIG_SBSA_REF=y
368
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
369
index XXXXXXX..XXXXXXX 100644
370
--- a/hw/arm/Kconfig
371
+++ b/hw/arm/Kconfig
372
@@ -XXX,XX +XXX,XX @@ config REALVIEW
373
select DS1338 # I2C RTC+NVRAM
374
select USB_OHCI
375
376
+config SBSA_REF
377
+ bool
378
+ imply PCI_DEVICES
379
+ select AHCI
380
+ select ARM_SMMUV3
381
+ select GPIO_KEY
382
+ select PCI_EXPRESS
383
+ select PCI_EXPRESS_GENERIC_BRIDGE
384
+ select PFLASH_CFI01
385
+ select PL011 # UART
386
+ select PL031 # RTC
387
+ select PL061 # GPIO
388
+ select USB_EHCI_SYSBUS
389
+
390
config SABRELITE
391
bool
392
select FSL_IMX6
393
--
34
--
394
2.20.1
35
2.34.1
395
396
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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