1
target-arm queue for softfreeze: this is quite big as I
1
The following changes since commit 8f6330a807f2642dc2a3cdf33347aa28a4c00a87:
2
was on holiday last week, so this is all just sneaking in
3
under the wire. I particularly wanted to get Philippe's
4
patches in before freeze as that sort of code-movement
5
patchset is painful to have to rebase.
6
2
7
thanks
3
Merge tag 'pull-maintainer-updates-060324-1' of https://gitlab.com/stsquad/qemu into staging (2024-03-06 16:56:20 +0000)
8
-- PMM
9
10
The following changes since commit ae9108f8f0746ce64d02afb1a216153a50926132:
11
12
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-4.1-pull-request' into staging (2019-07-01 15:55:40 +0100)
13
4
14
are available in the Git repository at:
5
are available in the Git repository at:
15
6
16
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190701
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240308
17
8
18
for you to fetch changes up to 787a7e76c2e93a48c47b324fea592c9910a70483:
9
for you to fetch changes up to bbf6c6dbead82292a20951eb1204442a6b838de9:
19
10
20
target/arm: Declare some M-profile functions publicly (2019-07-01 17:29:01 +0100)
11
target/arm: Move v7m-related code from cpu32.c into a separate file (2024-03-08 14:45:03 +0000)
21
12
22
----------------------------------------------------------------
13
----------------------------------------------------------------
23
target-arm queue:
14
target-arm queue:
24
* hw/arm/boot: fix direct kernel boot with initrd
15
* Implement FEAT_ECV
25
* hw/arm/msf2-som: Exit when the cpu is not the expected one
16
* STM32L4x5: Implement GPIO device
26
* i.mx7: fix bugs in PCI controller needed to boot recent kernels
17
* Fix 32-bit SMOPA
27
* aspeed: add RTC device
18
* Refactor v7m related code from cpu32.c into its own file
28
* aspeed: fix some timer device bugs
19
* hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
29
* aspeed: add swift-bmc board
30
* aspeed: vic: Add support for legacy register interface
31
* aspeed: add aspeed-xdma device
32
* Add new sbsa-ref board for aarch64
33
* target/arm: code refactoring in preparation for support of
34
compilation with TCG disabled
35
20
36
----------------------------------------------------------------
21
----------------------------------------------------------------
37
Adriana Kobylak (1):
22
Inès Varhol (3):
38
aspeed: Add support for the swift-bmc board
23
hw/gpio: Implement STM32L4x5 GPIO
24
hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC
25
tests/qtest: Add STM32L4x5 GPIO QTest testcase
39
26
40
Andrew Jeffery (3):
27
Peter Maydell (9):
41
aspeed/timer: Status register contains reload for stopped timer
28
target/arm: Move some register related defines to internals.h
42
aspeed/timer: Fix match calculations
29
target/arm: Timer _EL02 registers UNDEF for E2H == 0
43
aspeed: vic: Add support for legacy register interface
30
target/arm: use FIELD macro for CNTHCTL bit definitions
31
target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written
32
target/arm: Implement new FEAT_ECV trap bits
33
target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0
34
target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling
35
target/arm: Enable FEAT_ECV for 'max' CPU
36
hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
44
37
45
Andrew Jones (1):
38
Richard Henderson (1):
46
hw/arm/boot: fix direct kernel boot with initrd
39
target/arm: Fix 32-bit SMOPA
47
40
48
Andrey Smirnov (5):
41
Thomas Huth (1):
49
i.mx7d: Add no-op/unimplemented APBH DMA module
42
target/arm: Move v7m-related code from cpu32.c into a separate file
50
i.mx7d: Add no-op/unimplemented PCIE PHY IP block
51
pci: designware: Update MSI mapping unconditionally
52
pci: designware: Update MSI mapping when MSI address changes
53
i.mx7d: pci: Update PCI IRQ mapping to match HW
54
43
55
Christian Svensson (1):
44
MAINTAINERS | 1 +
56
aspeed/timer: Ensure positive muldiv delta
45
docs/system/arm/b-l475e-iot01a.rst | 2 +-
46
docs/system/arm/emulation.rst | 1 +
47
include/hw/arm/stm32l4x5_soc.h | 2 +
48
include/hw/gpio/stm32l4x5_gpio.h | 71 +++++
49
include/hw/misc/stm32l4x5_syscfg.h | 3 +-
50
include/hw/rtc/sun4v-rtc.h | 2 +-
51
target/arm/cpu-features.h | 10 +
52
target/arm/cpu.h | 129 +--------
53
target/arm/internals.h | 151 ++++++++++
54
hw/arm/stm32l4x5_soc.c | 71 ++++-
55
hw/gpio/stm32l4x5_gpio.c | 477 ++++++++++++++++++++++++++++++++
56
hw/misc/stm32l4x5_syscfg.c | 1 +
57
hw/rtc/sun4v-rtc.c | 2 +-
58
target/arm/helper.c | 189 ++++++++++++-
59
target/arm/tcg/cpu-v7m.c | 290 +++++++++++++++++++
60
target/arm/tcg/cpu32.c | 261 ------------------
61
target/arm/tcg/cpu64.c | 1 +
62
target/arm/tcg/sme_helper.c | 77 +++---
63
tests/qtest/stm32l4x5_gpio-test.c | 551 +++++++++++++++++++++++++++++++++++++
64
tests/tcg/aarch64/sme-smopa-1.c | 47 ++++
65
tests/tcg/aarch64/sme-smopa-2.c | 54 ++++
66
hw/arm/Kconfig | 3 +-
67
hw/gpio/Kconfig | 3 +
68
hw/gpio/meson.build | 1 +
69
hw/gpio/trace-events | 6 +
70
target/arm/meson.build | 3 +
71
target/arm/tcg/meson.build | 3 +
72
target/arm/trace-events | 1 +
73
tests/qtest/meson.build | 3 +-
74
tests/tcg/aarch64/Makefile.target | 2 +-
75
31 files changed, 1962 insertions(+), 456 deletions(-)
76
create mode 100644 include/hw/gpio/stm32l4x5_gpio.h
77
create mode 100644 hw/gpio/stm32l4x5_gpio.c
78
create mode 100644 target/arm/tcg/cpu-v7m.c
79
create mode 100644 tests/qtest/stm32l4x5_gpio-test.c
80
create mode 100644 tests/tcg/aarch64/sme-smopa-1.c
81
create mode 100644 tests/tcg/aarch64/sme-smopa-2.c
57
82
58
Cédric Le Goater (7):
59
aspeed: add a per SoC mapping for the interrupt space
60
aspeed: add a per SoC mapping for the memory space
61
aspeed: introduce a configurable number of CPU per machine
62
aspeed: add support for multiple NICs
63
aspeed: remove the "ram" link
64
aspeed: add a RAM memory region container
65
aspeed/smc: add a 'sdram_base' property
66
67
Eddie James (1):
68
hw/misc/aspeed_xdma: New device
69
70
Hongbo Zhang (2):
71
hw/arm: Add arm SBSA reference machine, skeleton part
72
hw/arm: Add arm SBSA reference machine, devices part
73
74
Jan Kiszka (1):
75
hw/arm/virt: Add support for Cortex-A7
76
77
Joel Stanley (4):
78
hw: timer: Add ASPEED RTC device
79
hw/arm/aspeed: Add RTC to SoC
80
aspeed/timer: Fix behaviour running Linux
81
aspeed: Link SCU to the watchdog
82
83
Philippe Mathieu-Daudé (19):
84
hw/arm/msf2-som: Exit when the cpu is not the expected one
85
target/arm: Makefile cleanup (Aarch64)
86
target/arm: Makefile cleanup (ARM)
87
target/arm: Makefile cleanup (KVM)
88
target/arm: Makefile cleanup (softmmu)
89
target/arm: Add copyright boilerplate
90
target/arm/helper: Remove unused include
91
target/arm: Fix multiline comment syntax
92
target/arm: Fix coding style issues
93
target/arm: Move CPU state dumping routines to cpu.c
94
target/arm: Declare get_phys_addr() function publicly
95
target/arm: Move TLB related routines to tlb_helper.c
96
target/arm/vfp_helper: Move code around
97
target/arm/vfp_helper: Extract vfp_set_fpscr_to_host()
98
target/arm/vfp_helper: Extract vfp_set_fpscr_from_host()
99
target/arm/vfp_helper: Restrict the SoftFloat use to TCG
100
target/arm: Restrict PSCI to TCG
101
target/arm: Declare arm_log_exception() function publicly
102
target/arm: Declare some M-profile functions publicly
103
104
Samuel Ortiz (1):
105
target/arm: Move the DC ZVA helper into op_helper
106
107
hw/arm/Makefile.objs | 1 +
108
hw/misc/Makefile.objs | 1 +
109
hw/timer/Makefile.objs | 2 +-
110
target/arm/Makefile.objs | 24 +-
111
include/hw/arm/aspeed_soc.h | 53 ++-
112
include/hw/arm/fsl-imx7.h | 14 +-
113
include/hw/misc/aspeed_xdma.h | 30 ++
114
include/hw/ssi/aspeed_smc.h | 3 +
115
include/hw/timer/aspeed_rtc.h | 31 ++
116
include/hw/watchdog/wdt_aspeed.h | 1 +
117
target/arm/cpu.h | 2 -
118
target/arm/internals.h | 69 ++-
119
target/arm/translate.h | 5 -
120
hw/arm/aspeed.c | 76 +++-
121
hw/arm/aspeed_soc.c | 262 +++++++++---
122
hw/arm/boot.c | 3 +-
123
hw/arm/fsl-imx7.c | 11 +
124
hw/arm/msf2-som.c | 1 +
125
hw/arm/sbsa-ref.c | 806 ++++++++++++++++++++++++++++++++++++
126
hw/arm/virt.c | 1 +
127
hw/intc/aspeed_vic.c | 105 +++--
128
hw/misc/aspeed_xdma.c | 165 ++++++++
129
hw/pci-host/designware.c | 18 +-
130
hw/ssi/aspeed_smc.c | 1 +
131
hw/timer/aspeed_rtc.c | 180 ++++++++
132
hw/timer/aspeed_timer.c | 76 ++--
133
hw/watchdog/wdt_aspeed.c | 20 +
134
target/arm/cpu.c | 232 ++++++++++-
135
target/arm/helper.c | 498 +++++++++-------------
136
target/arm/op_helper.c | 262 ++++++------
137
target/arm/tlb_helper.c | 200 +++++++++
138
target/arm/translate-a64.c | 128 ------
139
target/arm/translate.c | 91 +---
140
target/arm/vfp_helper.c | 199 +++++----
141
MAINTAINERS | 8 +
142
default-configs/aarch64-softmmu.mak | 1 +
143
hw/arm/Kconfig | 14 +
144
hw/misc/trace-events | 3 +
145
hw/timer/trace-events | 4 +
146
39 files changed, 2675 insertions(+), 926 deletions(-)
147
create mode 100644 include/hw/misc/aspeed_xdma.h
148
create mode 100644 include/hw/timer/aspeed_rtc.h
149
create mode 100644 hw/arm/sbsa-ref.c
150
create mode 100644 hw/misc/aspeed_xdma.c
151
create mode 100644 hw/timer/aspeed_rtc.c
152
create mode 100644 target/arm/tlb_helper.c
153
diff view generated by jsdifflib
Deleted patch
1
From: Andrew Jones <drjones@redhat.com>
2
1
3
Fix the condition used to check whether the initrd fits
4
into RAM; in some cases if an initrd was also passed on
5
the command line we would get an error stating that it
6
was too big to fit into RAM after the kernel. Despite the
7
error the loader continued anyway, though, so also add an
8
exit(1) when the initrd is actually too big.
9
10
Fixes: 852dc64d665f ("hw/arm/boot: Diagnose layouts that put initrd or
11
DTB off the end of RAM")
12
Signed-off-by: Andrew Jones <drjones@redhat.com>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Message-id: 20190618125844.4863-1-drjones@redhat.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/arm/boot.c | 3 ++-
18
1 file changed, 2 insertions(+), 1 deletion(-)
19
20
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/boot.c
23
+++ b/hw/arm/boot.c
24
@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
25
info->initrd_filename);
26
exit(1);
27
}
28
- if (info->initrd_start + initrd_size > info->ram_size) {
29
+ if (info->initrd_start + initrd_size > ram_end) {
30
error_report("could not load initrd '%s': "
31
"too big to fit into RAM after the kernel",
32
info->initrd_filename);
33
+ exit(1);
34
}
35
} else {
36
initrd_size = 0;
37
--
38
2.20.1
39
40
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
This machine correctly defines its default_cpu_type to cortex-m3
4
and report an error if the user requested another cpu_type,
5
however it does not exit, and this can confuse users trying
6
to use another core:
7
8
$ qemu-system-arm -M emcraft-sf2 -cpu cortex-m4 -kernel test-m4.elf
9
qemu-system-arm: This board can only be used with CPU cortex-m3-arm-cpu
10
[output related to M3 core ...]
11
12
The CPU is indeed a M3 core:
13
14
(qemu) info qom-tree
15
/machine (emcraft-sf2-machine)
16
/unattached (container)
17
/device[0] (msf2-soc)
18
/armv7m (armv7m)
19
/cpu (cortex-m3-arm-cpu)
20
21
Add the missing exit() call to return to the shell.
22
23
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
24
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
25
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
26
Message-id: 20190617160136.29930-1-philmd@redhat.com
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
---
29
hw/arm/msf2-som.c | 1 +
30
1 file changed, 1 insertion(+)
31
32
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/msf2-som.c
35
+++ b/hw/arm/msf2-som.c
36
@@ -XXX,XX +XXX,XX @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
37
if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
38
error_report("This board can only be used with CPU %s",
39
mc->default_cpu_type);
40
+ exit(1);
41
}
42
43
memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
44
--
45
2.20.1
46
47
diff view generated by jsdifflib
Deleted patch
1
From: Jan Kiszka <jan.kiszka@siemens.com>
2
1
3
Allow cortex-a7 to be used with the virt board; it supports
4
the v7VE features and there is no reason to deny this type.
5
6
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: fc5404f7-4d1d-c28f-6e48-d8799c82acc0@web.de
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/virt.c | 1 +
13
1 file changed, 1 insertion(+)
14
15
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/virt.c
18
+++ b/hw/arm/virt.c
19
@@ -XXX,XX +XXX,XX @@ static const int a15irqmap[] = {
20
};
21
22
static const char *valid_cpus[] = {
23
+ ARM_CPU_TYPE_NAME("cortex-a7"),
24
ARM_CPU_TYPE_NAME("cortex-a15"),
25
ARM_CPU_TYPE_NAME("cortex-a53"),
26
ARM_CPU_TYPE_NAME("cortex-a57"),
27
--
28
2.20.1
29
30
diff view generated by jsdifflib
Deleted patch
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
2
1
3
Instantiate no-op APBH DMA module. Needed to boot latest Linux kernel.
4
5
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
6
Cc: Peter Maydell <peter.maydell@linaro.org>
7
Cc: Michael S. Tsirkin <mst@redhat.com>
8
Cc: qemu-devel@nongnu.org
9
Cc: qemu-arm@nongnu.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/hw/arm/fsl-imx7.h | 3 +++
14
hw/arm/fsl-imx7.c | 6 ++++++
15
2 files changed, 9 insertions(+)
16
17
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/fsl-imx7.h
20
+++ b/include/hw/arm/fsl-imx7.h
21
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
22
FSL_IMX7_PCIE_REG_SIZE = 16 * 1024,
23
24
FSL_IMX7_GPR_ADDR = 0x30340000,
25
+
26
+ FSL_IMX7_DMA_APBH_ADDR = 0x33000000,
27
+ FSL_IMX7_DMA_APBH_SIZE = 0x2000,
28
};
29
30
enum FslIMX7IRQs {
31
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/fsl-imx7.c
34
+++ b/hw/arm/fsl-imx7.c
35
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
36
*/
37
create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR,
38
FSL_IMX7_LCDIF_SIZE);
39
+
40
+ /*
41
+ * DMA APBH
42
+ */
43
+ create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR,
44
+ FSL_IMX7_DMA_APBH_SIZE);
45
}
46
47
static void fsl_imx7_class_init(ObjectClass *oc, void *data)
48
--
49
2.20.1
50
51
diff view generated by jsdifflib
Deleted patch
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
2
1
3
Add no-op/unimplemented PCIE PHY IP block. Needed by new kernels to
4
use PCIE.
5
6
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
7
Cc: Peter Maydell <peter.maydell@linaro.org>
8
Cc: Michael S. Tsirkin <mst@redhat.com>
9
Cc: qemu-devel@nongnu.org
10
Cc: qemu-arm@nongnu.org
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
include/hw/arm/fsl-imx7.h | 3 +++
15
hw/arm/fsl-imx7.c | 5 +++++
16
2 files changed, 8 insertions(+)
17
18
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/fsl-imx7.h
21
+++ b/include/hw/arm/fsl-imx7.h
22
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
23
FSL_IMX7_ADC2_ADDR = 0x30620000,
24
FSL_IMX7_ADCn_SIZE = 0x1000,
25
26
+ FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000,
27
+ FSL_IMX7_PCIE_PHY_SIZE = 0x10000,
28
+
29
FSL_IMX7_GPC_ADDR = 0x303A0000,
30
31
FSL_IMX7_I2C1_ADDR = 0x30A20000,
32
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/fsl-imx7.c
35
+++ b/hw/arm/fsl-imx7.c
36
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
37
*/
38
create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR,
39
FSL_IMX7_DMA_APBH_SIZE);
40
+ /*
41
+ * PCIe PHY
42
+ */
43
+ create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
44
+ FSL_IMX7_PCIE_PHY_SIZE);
45
}
46
47
static void fsl_imx7_class_init(ObjectClass *oc, void *data)
48
--
49
2.20.1
50
51
diff view generated by jsdifflib
Deleted patch
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
2
1
3
Expression to calculate update_msi_mapping in code handling writes to
4
DESIGNWARE_PCIE_MSI_INTR0_ENABLE is missing an ! operator and should
5
be:
6
7
!!root->msi.intr[0].enable ^ !!val;
8
9
so that MSI mapping is updated when enabled transitions from either
10
"none" -> "any" or "any" -> "none". Since that register shouldn't be
11
written to very often, change the code to update MSI mapping
12
unconditionally instead of trying to fix the update_msi_mapping logic.
13
14
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
15
Cc: Peter Maydell <peter.maydell@linaro.org>
16
Cc: Michael S. Tsirkin <mst@redhat.com>
17
Cc: qemu-devel@nongnu.org
18
Cc: qemu-arm@nongnu.org
19
Acked-by: Michael S. Tsirkin <mst@redhat.com>
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
hw/pci-host/designware.c | 10 ++--------
24
1 file changed, 2 insertions(+), 8 deletions(-)
25
26
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/pci-host/designware.c
29
+++ b/hw/pci-host/designware.c
30
@@ -XXX,XX +XXX,XX @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
31
root->msi.base |= (uint64_t)val << 32;
32
break;
33
34
- case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: {
35
- const bool update_msi_mapping = !root->msi.intr[0].enable ^ !!val;
36
-
37
+ case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
38
root->msi.intr[0].enable = val;
39
-
40
- if (update_msi_mapping) {
41
- designware_pcie_root_update_msi_mapping(root);
42
- }
43
+ designware_pcie_root_update_msi_mapping(root);
44
break;
45
- }
46
47
case DESIGNWARE_PCIE_MSI_INTR0_MASK:
48
root->msi.intr[0].mask = val;
49
--
50
2.20.1
51
52
diff view generated by jsdifflib
Deleted patch
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
2
1
3
MSI mapping needs to be update when MSI address changes, so add the
4
code to do so.
5
6
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
7
Cc: Peter Maydell <peter.maydell@linaro.org>
8
Cc: Michael S. Tsirkin <mst@redhat.com>
9
Cc: qemu-devel@nongnu.org
10
Cc: qemu-arm@nongnu.org
11
Acked-by: Michael S. Tsirkin <mst@redhat.com>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/pci-host/designware.c | 2 ++
16
1 file changed, 2 insertions(+)
17
18
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/pci-host/designware.c
21
+++ b/hw/pci-host/designware.c
22
@@ -XXX,XX +XXX,XX @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
23
case DESIGNWARE_PCIE_MSI_ADDR_LO:
24
root->msi.base &= 0xFFFFFFFF00000000ULL;
25
root->msi.base |= val;
26
+ designware_pcie_root_update_msi_mapping(root);
27
break;
28
29
case DESIGNWARE_PCIE_MSI_ADDR_HI:
30
root->msi.base &= 0x00000000FFFFFFFFULL;
31
root->msi.base |= (uint64_t)val << 32;
32
+ designware_pcie_root_update_msi_mapping(root);
33
break;
34
35
case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
36
--
37
2.20.1
38
39
diff view generated by jsdifflib
Deleted patch
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
2
1
3
Datasheet for i.MX7 is incorrect and i.MX7's PCI IRQ mapping matches
4
that of i.MX6:
5
6
* INTD/MSI 122
7
* INTC 123
8
* INTB 124
9
* INTA 125
10
11
Fix all of the relevant code to reflect that fact. Needed by latest
12
Linux kernels.
13
14
(Reference: Linux kernel commit 538d6e9d597584e80 from an
15
NXP employee confirming that the datasheet is incorrect and
16
with a report of a test against hardware.)
17
18
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
19
Cc: Peter Maydell <peter.maydell@linaro.org>
20
Cc: Michael S. Tsirkin <mst@redhat.com>
21
Cc: qemu-devel@nongnu.org
22
Cc: qemu-arm@nongnu.org
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
[PMM: added ref to kernel commit confirming the datasheet error]
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
---
27
include/hw/arm/fsl-imx7.h | 8 ++++----
28
hw/pci-host/designware.c | 6 ++++--
29
2 files changed, 8 insertions(+), 6 deletions(-)
30
31
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
32
index XXXXXXX..XXXXXXX 100644
33
--- a/include/hw/arm/fsl-imx7.h
34
+++ b/include/hw/arm/fsl-imx7.h
35
@@ -XXX,XX +XXX,XX @@ enum FslIMX7IRQs {
36
FSL_IMX7_USB2_IRQ = 42,
37
FSL_IMX7_USB3_IRQ = 40,
38
39
- FSL_IMX7_PCI_INTA_IRQ = 122,
40
- FSL_IMX7_PCI_INTB_IRQ = 123,
41
- FSL_IMX7_PCI_INTC_IRQ = 124,
42
- FSL_IMX7_PCI_INTD_IRQ = 125,
43
+ FSL_IMX7_PCI_INTA_IRQ = 125,
44
+ FSL_IMX7_PCI_INTB_IRQ = 124,
45
+ FSL_IMX7_PCI_INTC_IRQ = 123,
46
+ FSL_IMX7_PCI_INTD_IRQ = 122,
47
48
FSL_IMX7_UART7_IRQ = 126,
49
50
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/hw/pci-host/designware.c
53
+++ b/hw/pci-host/designware.c
54
@@ -XXX,XX +XXX,XX @@
55
#define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff)
56
#define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C
57
58
+#define DESIGNWARE_PCIE_IRQ_MSI 3
59
+
60
static DesignwarePCIEHost *
61
designware_pcie_root_to_host(DesignwarePCIERoot *root)
62
{
63
@@ -XXX,XX +XXX,XX @@ static void designware_pcie_root_msi_write(void *opaque, hwaddr addr,
64
root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable;
65
66
if (root->msi.intr[0].status & ~root->msi.intr[0].mask) {
67
- qemu_set_irq(host->pci.irqs[0], 1);
68
+ qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 1);
69
}
70
}
71
72
@@ -XXX,XX +XXX,XX @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
73
case DESIGNWARE_PCIE_MSI_INTR0_STATUS:
74
root->msi.intr[0].status ^= val;
75
if (!root->msi.intr[0].status) {
76
- qemu_set_irq(host->pci.irqs[0], 0);
77
+ qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 0);
78
}
79
break;
80
81
--
82
2.20.1
83
84
diff view generated by jsdifflib
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
This will simplify the definition of new SoCs, like the AST2600 which
4
should use a different CPU and a different IRQ number layout.
5
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Joel Stanley <joel@jms.id.au>
9
Message-id: 20190618165311.27066-2-clg@kaod.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/arm/aspeed_soc.h | 36 +++++++++++++++++++++++
13
hw/arm/aspeed_soc.c | 57 +++++++++++++++++++++++++++++++------
14
2 files changed, 85 insertions(+), 8 deletions(-)
15
16
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/aspeed_soc.h
19
+++ b/include/hw/arm/aspeed_soc.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCInfo {
21
const char *fmc_typename;
22
const char **spi_typename;
23
int wdts_num;
24
+ const int *irqmap;
25
} AspeedSoCInfo;
26
27
typedef struct AspeedSoCClass {
28
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCClass {
29
#define ASPEED_SOC_GET_CLASS(obj) \
30
OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
31
32
+enum {
33
+ ASPEED_IOMEM,
34
+ ASPEED_UART1,
35
+ ASPEED_UART2,
36
+ ASPEED_UART3,
37
+ ASPEED_UART4,
38
+ ASPEED_UART5,
39
+ ASPEED_VUART,
40
+ ASPEED_FMC,
41
+ ASPEED_SPI1,
42
+ ASPEED_SPI2,
43
+ ASPEED_VIC,
44
+ ASPEED_SDMC,
45
+ ASPEED_SCU,
46
+ ASPEED_ADC,
47
+ ASPEED_SRAM,
48
+ ASPEED_GPIO,
49
+ ASPEED_RTC,
50
+ ASPEED_TIMER1,
51
+ ASPEED_TIMER2,
52
+ ASPEED_TIMER3,
53
+ ASPEED_TIMER4,
54
+ ASPEED_TIMER5,
55
+ ASPEED_TIMER6,
56
+ ASPEED_TIMER7,
57
+ ASPEED_TIMER8,
58
+ ASPEED_WDT,
59
+ ASPEED_PWM,
60
+ ASPEED_LPC,
61
+ ASPEED_IBT,
62
+ ASPEED_I2C,
63
+ ASPEED_ETH1,
64
+ ASPEED_ETH2,
65
+};
66
+
67
#endif /* ASPEED_SOC_H */
68
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/arm/aspeed_soc.c
71
+++ b/hw/arm/aspeed_soc.c
72
@@ -XXX,XX +XXX,XX @@
73
#define ASPEED_SOC_ETH1_BASE 0x1E660000
74
#define ASPEED_SOC_ETH2_BASE 0x1E680000
75
76
-static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
77
-static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
78
+static const int aspeed_soc_ast2400_irqmap[] = {
79
+ [ASPEED_UART1] = 9,
80
+ [ASPEED_UART2] = 32,
81
+ [ASPEED_UART3] = 33,
82
+ [ASPEED_UART4] = 34,
83
+ [ASPEED_UART5] = 10,
84
+ [ASPEED_VUART] = 8,
85
+ [ASPEED_FMC] = 19,
86
+ [ASPEED_SDMC] = 0,
87
+ [ASPEED_SCU] = 21,
88
+ [ASPEED_ADC] = 31,
89
+ [ASPEED_GPIO] = 20,
90
+ [ASPEED_RTC] = 22,
91
+ [ASPEED_TIMER1] = 16,
92
+ [ASPEED_TIMER2] = 17,
93
+ [ASPEED_TIMER3] = 18,
94
+ [ASPEED_TIMER4] = 35,
95
+ [ASPEED_TIMER5] = 36,
96
+ [ASPEED_TIMER6] = 37,
97
+ [ASPEED_TIMER7] = 38,
98
+ [ASPEED_TIMER8] = 39,
99
+ [ASPEED_WDT] = 27,
100
+ [ASPEED_PWM] = 28,
101
+ [ASPEED_LPC] = 8,
102
+ [ASPEED_IBT] = 8, /* LPC */
103
+ [ASPEED_I2C] = 12,
104
+ [ASPEED_ETH1] = 2,
105
+ [ASPEED_ETH2] = 3,
106
+};
107
108
#define AST2400_SDRAM_BASE 0x40000000
109
#define AST2500_SDRAM_BASE 0x80000000
110
111
+/* AST2500 uses the same IRQs as the AST2400 */
112
+#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
113
+
114
static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE };
115
static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
116
117
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
118
.fmc_typename = "aspeed.smc.fmc",
119
.spi_typename = aspeed_soc_ast2400_typenames,
120
.wdts_num = 2,
121
+ .irqmap = aspeed_soc_ast2400_irqmap,
122
}, {
123
.name = "ast2400-a1",
124
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
125
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
126
.fmc_typename = "aspeed.smc.fmc",
127
.spi_typename = aspeed_soc_ast2400_typenames,
128
.wdts_num = 2,
129
+ .irqmap = aspeed_soc_ast2400_irqmap,
130
}, {
131
.name = "ast2400",
132
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
133
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
134
.fmc_typename = "aspeed.smc.fmc",
135
.spi_typename = aspeed_soc_ast2400_typenames,
136
.wdts_num = 2,
137
+ .irqmap = aspeed_soc_ast2400_irqmap,
138
}, {
139
.name = "ast2500-a1",
140
.cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
141
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
142
.fmc_typename = "aspeed.smc.ast2500-fmc",
143
.spi_typename = aspeed_soc_ast2500_typenames,
144
.wdts_num = 3,
145
+ .irqmap = aspeed_soc_ast2500_irqmap,
146
},
147
};
148
149
+static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
150
+{
151
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
152
+
153
+ return qdev_get_gpio_in(DEVICE(&s->vic), sc->info->irqmap[ctrl]);
154
+}
155
+
156
static void aspeed_soc_init(Object *obj)
157
{
158
AspeedSoCState *s = ASPEED_SOC(obj);
159
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
160
return;
161
}
162
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
163
- for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
164
- qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
165
+ for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
166
+ qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
167
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
168
}
169
170
/* UART - attach an 8250 to the IO space as our UART5 */
171
if (serial_hd(0)) {
172
- qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
173
+ qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
174
serial_mm_init(get_system_memory(),
175
ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2,
176
uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
177
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
178
}
179
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
180
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
181
- qdev_get_gpio_in(DEVICE(&s->vic), 12));
182
+ aspeed_soc_get_irq(s, ASPEED_I2C));
183
184
/* FMC, The number of CS is set at the board level */
185
object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
186
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
187
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
188
s->fmc.ctrl->flash_window_base);
189
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
190
- qdev_get_gpio_in(DEVICE(&s->vic), 19));
191
+ aspeed_soc_get_irq(s, ASPEED_FMC));
192
193
/* SPI */
194
for (i = 0; i < sc->info->spis_num; i++) {
195
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
196
}
197
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, ASPEED_SOC_ETH1_BASE);
198
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
199
- qdev_get_gpio_in(DEVICE(&s->vic), 2));
200
+ aspeed_soc_get_irq(s, ASPEED_ETH1));
201
}
202
203
static void aspeed_soc_class_init(ObjectClass *oc, void *data)
204
--
205
2.20.1
206
207
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
cpu.h has a lot of #defines relating to CPU register fields.
2
Most of these aren't actually used outside target/arm code,
3
so there's no point in cluttering up the cpu.h file with them.
4
Move some easy ones to internals.h.
2
5
3
Suggested-by: Samuel Ortiz <sameo@linux.intel.com>
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Message-id: 20190701132516.26392-11-philmd@redhat.com
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20240301183219.2424889-2-peter.maydell@linaro.org
8
---
10
---
9
target/arm/cpu.h | 2 -
11
target/arm/cpu.h | 128 -----------------------------------------
10
target/arm/translate.h | 5 -
12
target/arm/internals.h | 128 +++++++++++++++++++++++++++++++++++++++++
11
target/arm/cpu.c | 226 +++++++++++++++++++++++++++++++++++++
13
2 files changed, 128 insertions(+), 128 deletions(-)
12
target/arm/translate-a64.c | 128 ---------------------
13
target/arm/translate.c | 88 ---------------
14
5 files changed, 226 insertions(+), 223 deletions(-)
15
14
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
17
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
18
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cpu);
19
@@ -XXX,XX +XXX,XX @@ typedef struct ARMGenericTimer {
21
void arm_v7m_cpu_do_interrupt(CPUState *cpu);
20
uint64_t ctl; /* Timer Control register */
22
bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
21
} ARMGenericTimer;
23
22
24
-void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags);
23
-#define VTCR_NSW (1u << 29)
25
-
24
-#define VTCR_NSA (1u << 30)
26
hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
25
-#define VSTCR_SW VTCR_NSW
27
MemTxAttrs *attrs);
26
-#define VSTCR_SA VTCR_NSA
28
27
-
29
diff --git a/target/arm/translate.h b/target/arm/translate.h
28
/* Define a maximum sized vector register.
29
* For 32-bit, this is a 128-bit NEON/AdvSIMD register.
30
* For 64-bit, this is a 2048-bit SVE register.
31
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
32
#define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */
33
#define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */
34
35
-/* Bit definitions for CPACR (AArch32 only) */
36
-FIELD(CPACR, CP10, 20, 2)
37
-FIELD(CPACR, CP11, 22, 2)
38
-FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */
39
-FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */
40
-FIELD(CPACR, ASEDIS, 31, 1)
41
-
42
-/* Bit definitions for CPACR_EL1 (AArch64 only) */
43
-FIELD(CPACR_EL1, ZEN, 16, 2)
44
-FIELD(CPACR_EL1, FPEN, 20, 2)
45
-FIELD(CPACR_EL1, SMEN, 24, 2)
46
-FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */
47
-
48
-/* Bit definitions for HCPTR (AArch32 only) */
49
-FIELD(HCPTR, TCP10, 10, 1)
50
-FIELD(HCPTR, TCP11, 11, 1)
51
-FIELD(HCPTR, TASE, 15, 1)
52
-FIELD(HCPTR, TTA, 20, 1)
53
-FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */
54
-FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */
55
-
56
-/* Bit definitions for CPTR_EL2 (AArch64 only) */
57
-FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */
58
-FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */
59
-FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */
60
-FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */
61
-FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */
62
-FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */
63
-FIELD(CPTR_EL2, TTA, 28, 1)
64
-FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */
65
-FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */
66
-
67
-/* Bit definitions for CPTR_EL3 (AArch64 only) */
68
-FIELD(CPTR_EL3, EZ, 8, 1)
69
-FIELD(CPTR_EL3, TFP, 10, 1)
70
-FIELD(CPTR_EL3, ESM, 12, 1)
71
-FIELD(CPTR_EL3, TTA, 20, 1)
72
-FIELD(CPTR_EL3, TAM, 30, 1)
73
-FIELD(CPTR_EL3, TCPAC, 31, 1)
74
-
75
-#define MDCR_MTPME (1U << 28)
76
-#define MDCR_TDCC (1U << 27)
77
-#define MDCR_HLP (1U << 26) /* MDCR_EL2 */
78
-#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */
79
-#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */
80
-#define MDCR_EPMAD (1U << 21)
81
-#define MDCR_EDAD (1U << 20)
82
-#define MDCR_TTRF (1U << 19)
83
-#define MDCR_STE (1U << 18) /* MDCR_EL3 */
84
-#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
85
-#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
86
-#define MDCR_SDD (1U << 16)
87
-#define MDCR_SPD (3U << 14)
88
-#define MDCR_TDRA (1U << 11)
89
-#define MDCR_TDOSA (1U << 10)
90
-#define MDCR_TDA (1U << 9)
91
-#define MDCR_TDE (1U << 8)
92
-#define MDCR_HPME (1U << 7)
93
-#define MDCR_TPM (1U << 6)
94
-#define MDCR_TPMCR (1U << 5)
95
-#define MDCR_HPMN (0x1fU)
96
-
97
-/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
98
-#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
99
- MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
100
- MDCR_STE | MDCR_SPME | MDCR_SPD)
101
-
102
#define CPSR_M (0x1fU)
103
#define CPSR_T (1U << 5)
104
#define CPSR_F (1U << 6)
105
@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TCPAC, 31, 1)
106
#define XPSR_NZCV CPSR_NZCV
107
#define XPSR_IT CPSR_IT
108
109
-#define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
110
-#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
111
-#define TTBCR_PD0 (1U << 4)
112
-#define TTBCR_PD1 (1U << 5)
113
-#define TTBCR_EPD0 (1U << 7)
114
-#define TTBCR_IRGN0 (3U << 8)
115
-#define TTBCR_ORGN0 (3U << 10)
116
-#define TTBCR_SH0 (3U << 12)
117
-#define TTBCR_T1SZ (3U << 16)
118
-#define TTBCR_A1 (1U << 22)
119
-#define TTBCR_EPD1 (1U << 23)
120
-#define TTBCR_IRGN1 (3U << 24)
121
-#define TTBCR_ORGN1 (3U << 26)
122
-#define TTBCR_SH1 (1U << 28)
123
-#define TTBCR_EAE (1U << 31)
124
-
125
-FIELD(VTCR, T0SZ, 0, 6)
126
-FIELD(VTCR, SL0, 6, 2)
127
-FIELD(VTCR, IRGN0, 8, 2)
128
-FIELD(VTCR, ORGN0, 10, 2)
129
-FIELD(VTCR, SH0, 12, 2)
130
-FIELD(VTCR, TG0, 14, 2)
131
-FIELD(VTCR, PS, 16, 3)
132
-FIELD(VTCR, VS, 19, 1)
133
-FIELD(VTCR, HA, 21, 1)
134
-FIELD(VTCR, HD, 22, 1)
135
-FIELD(VTCR, HWU59, 25, 1)
136
-FIELD(VTCR, HWU60, 26, 1)
137
-FIELD(VTCR, HWU61, 27, 1)
138
-FIELD(VTCR, HWU62, 28, 1)
139
-FIELD(VTCR, NSW, 29, 1)
140
-FIELD(VTCR, NSA, 30, 1)
141
-FIELD(VTCR, DS, 32, 1)
142
-FIELD(VTCR, SL2, 33, 1)
143
-
144
/* Bit definitions for ARMv8 SPSR (PSTATE) format.
145
* Only these are valid when in AArch64 mode; in
146
* AArch32 mode SPSRs are basically CPSR-format.
147
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
148
#define HCR_TWEDEN (1ULL << 59)
149
#define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
150
151
-#define HCRX_ENAS0 (1ULL << 0)
152
-#define HCRX_ENALS (1ULL << 1)
153
-#define HCRX_ENASR (1ULL << 2)
154
-#define HCRX_FNXS (1ULL << 3)
155
-#define HCRX_FGTNXS (1ULL << 4)
156
-#define HCRX_SMPME (1ULL << 5)
157
-#define HCRX_TALLINT (1ULL << 6)
158
-#define HCRX_VINMI (1ULL << 7)
159
-#define HCRX_VFNMI (1ULL << 8)
160
-#define HCRX_CMOW (1ULL << 9)
161
-#define HCRX_MCE2 (1ULL << 10)
162
-#define HCRX_MSCEN (1ULL << 11)
163
-
164
-#define HPFAR_NS (1ULL << 63)
165
-
166
#define SCR_NS (1ULL << 0)
167
#define SCR_IRQ (1ULL << 1)
168
#define SCR_FIQ (1ULL << 2)
169
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
170
#define SCR_GPF (1ULL << 48)
171
#define SCR_NSE (1ULL << 62)
172
173
-#define HSTR_TTEE (1 << 16)
174
-#define HSTR_TJDBX (1 << 17)
175
-
176
-#define CNTHCTL_CNTVMASK (1 << 18)
177
-#define CNTHCTL_CNTPMASK (1 << 19)
178
-
179
/* Return the current FPSCR value. */
180
uint32_t vfp_get_fpscr(CPUARMState *env);
181
void vfp_set_fpscr(CPUARMState *env, uint32_t val);
182
diff --git a/target/arm/internals.h b/target/arm/internals.h
30
index XXXXXXX..XXXXXXX 100644
183
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/translate.h
184
--- a/target/arm/internals.h
32
+++ b/target/arm/translate.h
185
+++ b/target/arm/internals.h
33
@@ -XXX,XX +XXX,XX @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
186
@@ -XXX,XX +XXX,XX @@ FIELD(DBGWCR, WT, 20, 1)
34
#ifdef TARGET_AARCH64
187
FIELD(DBGWCR, MASK, 24, 5)
35
void a64_translate_init(void);
188
FIELD(DBGWCR, SSCE, 29, 1)
36
void gen_a64_set_pc_im(uint64_t val);
189
37
-void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags);
190
+#define VTCR_NSW (1u << 29)
38
extern const TranslatorOps aarch64_translator_ops;
191
+#define VTCR_NSA (1u << 30)
39
#else
192
+#define VSTCR_SW VTCR_NSW
40
static inline void a64_translate_init(void)
193
+#define VSTCR_SA VTCR_NSA
41
@@ -XXX,XX +XXX,XX @@ static inline void a64_translate_init(void)
194
+
42
static inline void gen_a64_set_pc_im(uint64_t val)
195
+/* Bit definitions for CPACR (AArch32 only) */
43
{
196
+FIELD(CPACR, CP10, 20, 2)
44
}
197
+FIELD(CPACR, CP11, 22, 2)
45
-
198
+FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */
46
-static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
199
+FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */
47
-{
200
+FIELD(CPACR, ASEDIS, 31, 1)
48
-}
201
+
49
#endif
202
+/* Bit definitions for CPACR_EL1 (AArch64 only) */
50
203
+FIELD(CPACR_EL1, ZEN, 16, 2)
51
void arm_test_cc(DisasCompare *cmp, int cc);
204
+FIELD(CPACR_EL1, FPEN, 20, 2)
52
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
205
+FIELD(CPACR_EL1, SMEN, 24, 2)
53
index XXXXXXX..XXXXXXX 100644
206
+FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */
54
--- a/target/arm/cpu.c
207
+
55
+++ b/target/arm/cpu.c
208
+/* Bit definitions for HCPTR (AArch32 only) */
56
@@ -XXX,XX +XXX,XX @@
209
+FIELD(HCPTR, TCP10, 10, 1)
57
*/
210
+FIELD(HCPTR, TCP11, 11, 1)
58
211
+FIELD(HCPTR, TASE, 15, 1)
59
#include "qemu/osdep.h"
212
+FIELD(HCPTR, TTA, 20, 1)
60
+#include "qemu/qemu-print.h"
213
+FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */
61
#include "qemu-common.h"
214
+FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */
62
#include "target/arm/idau.h"
215
+
63
#include "qemu/module.h"
216
+/* Bit definitions for CPTR_EL2 (AArch64 only) */
64
@@ -XXX,XX +XXX,XX @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
217
+FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */
65
#endif
218
+FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */
66
}
219
+FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */
67
220
+FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */
68
+#ifdef TARGET_AARCH64
221
+FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */
69
+
222
+FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */
70
+static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
223
+FIELD(CPTR_EL2, TTA, 28, 1)
71
+{
224
+FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */
72
+ ARMCPU *cpu = ARM_CPU(cs);
225
+FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */
73
+ CPUARMState *env = &cpu->env;
226
+
74
+ uint32_t psr = pstate_read(env);
227
+/* Bit definitions for CPTR_EL3 (AArch64 only) */
75
+ int i;
228
+FIELD(CPTR_EL3, EZ, 8, 1)
76
+ int el = arm_current_el(env);
229
+FIELD(CPTR_EL3, TFP, 10, 1)
77
+ const char *ns_status;
230
+FIELD(CPTR_EL3, ESM, 12, 1)
78
+
231
+FIELD(CPTR_EL3, TTA, 20, 1)
79
+ qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
232
+FIELD(CPTR_EL3, TAM, 30, 1)
80
+ for (i = 0; i < 32; i++) {
233
+FIELD(CPTR_EL3, TCPAC, 31, 1)
81
+ if (i == 31) {
234
+
82
+ qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
235
+#define MDCR_MTPME (1U << 28)
83
+ } else {
236
+#define MDCR_TDCC (1U << 27)
84
+ qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
237
+#define MDCR_HLP (1U << 26) /* MDCR_EL2 */
85
+ (i + 2) % 3 ? " " : "\n");
238
+#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */
86
+ }
239
+#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */
87
+ }
240
+#define MDCR_EPMAD (1U << 21)
88
+
241
+#define MDCR_EDAD (1U << 20)
89
+ if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
242
+#define MDCR_TTRF (1U << 19)
90
+ ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
243
+#define MDCR_STE (1U << 18) /* MDCR_EL3 */
91
+ } else {
244
+#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
92
+ ns_status = "";
245
+#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
93
+ }
246
+#define MDCR_SDD (1U << 16)
94
+ qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
247
+#define MDCR_SPD (3U << 14)
95
+ psr,
248
+#define MDCR_TDRA (1U << 11)
96
+ psr & PSTATE_N ? 'N' : '-',
249
+#define MDCR_TDOSA (1U << 10)
97
+ psr & PSTATE_Z ? 'Z' : '-',
250
+#define MDCR_TDA (1U << 9)
98
+ psr & PSTATE_C ? 'C' : '-',
251
+#define MDCR_TDE (1U << 8)
99
+ psr & PSTATE_V ? 'V' : '-',
252
+#define MDCR_HPME (1U << 7)
100
+ ns_status,
253
+#define MDCR_TPM (1U << 6)
101
+ el,
254
+#define MDCR_TPMCR (1U << 5)
102
+ psr & PSTATE_SP ? 'h' : 't');
255
+#define MDCR_HPMN (0x1fU)
103
+
256
+
104
+ if (cpu_isar_feature(aa64_bti, cpu)) {
257
+/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
105
+ qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
258
+#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
106
+ }
259
+ MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
107
+ if (!(flags & CPU_DUMP_FPU)) {
260
+ MDCR_STE | MDCR_SPME | MDCR_SPD)
108
+ qemu_fprintf(f, "\n");
261
+
109
+ return;
262
+#define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
110
+ }
263
+#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
111
+ if (fp_exception_el(env, el) != 0) {
264
+#define TTBCR_PD0 (1U << 4)
112
+ qemu_fprintf(f, " FPU disabled\n");
265
+#define TTBCR_PD1 (1U << 5)
113
+ return;
266
+#define TTBCR_EPD0 (1U << 7)
114
+ }
267
+#define TTBCR_IRGN0 (3U << 8)
115
+ qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
268
+#define TTBCR_ORGN0 (3U << 10)
116
+ vfp_get_fpcr(env), vfp_get_fpsr(env));
269
+#define TTBCR_SH0 (3U << 12)
117
+
270
+#define TTBCR_T1SZ (3U << 16)
118
+ if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
271
+#define TTBCR_A1 (1U << 22)
119
+ int j, zcr_len = sve_zcr_len_for_el(env, el);
272
+#define TTBCR_EPD1 (1U << 23)
120
+
273
+#define TTBCR_IRGN1 (3U << 24)
121
+ for (i = 0; i <= FFR_PRED_NUM; i++) {
274
+#define TTBCR_ORGN1 (3U << 26)
122
+ bool eol;
275
+#define TTBCR_SH1 (1U << 28)
123
+ if (i == FFR_PRED_NUM) {
276
+#define TTBCR_EAE (1U << 31)
124
+ qemu_fprintf(f, "FFR=");
277
+
125
+ /* It's last, so end the line. */
278
+FIELD(VTCR, T0SZ, 0, 6)
126
+ eol = true;
279
+FIELD(VTCR, SL0, 6, 2)
127
+ } else {
280
+FIELD(VTCR, IRGN0, 8, 2)
128
+ qemu_fprintf(f, "P%02d=", i);
281
+FIELD(VTCR, ORGN0, 10, 2)
129
+ switch (zcr_len) {
282
+FIELD(VTCR, SH0, 12, 2)
130
+ case 0:
283
+FIELD(VTCR, TG0, 14, 2)
131
+ eol = i % 8 == 7;
284
+FIELD(VTCR, PS, 16, 3)
132
+ break;
285
+FIELD(VTCR, VS, 19, 1)
133
+ case 1:
286
+FIELD(VTCR, HA, 21, 1)
134
+ eol = i % 6 == 5;
287
+FIELD(VTCR, HD, 22, 1)
135
+ break;
288
+FIELD(VTCR, HWU59, 25, 1)
136
+ case 2:
289
+FIELD(VTCR, HWU60, 26, 1)
137
+ case 3:
290
+FIELD(VTCR, HWU61, 27, 1)
138
+ eol = i % 3 == 2;
291
+FIELD(VTCR, HWU62, 28, 1)
139
+ break;
292
+FIELD(VTCR, NSW, 29, 1)
140
+ default:
293
+FIELD(VTCR, NSA, 30, 1)
141
+ /* More than one quadword per predicate. */
294
+FIELD(VTCR, DS, 32, 1)
142
+ eol = true;
295
+FIELD(VTCR, SL2, 33, 1)
143
+ break;
296
+
144
+ }
297
+#define HCRX_ENAS0 (1ULL << 0)
145
+ }
298
+#define HCRX_ENALS (1ULL << 1)
146
+ for (j = zcr_len / 4; j >= 0; j--) {
299
+#define HCRX_ENASR (1ULL << 2)
147
+ int digits;
300
+#define HCRX_FNXS (1ULL << 3)
148
+ if (j * 4 + 4 <= zcr_len + 1) {
301
+#define HCRX_FGTNXS (1ULL << 4)
149
+ digits = 16;
302
+#define HCRX_SMPME (1ULL << 5)
150
+ } else {
303
+#define HCRX_TALLINT (1ULL << 6)
151
+ digits = (zcr_len % 4 + 1) * 4;
304
+#define HCRX_VINMI (1ULL << 7)
152
+ }
305
+#define HCRX_VFNMI (1ULL << 8)
153
+ qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
306
+#define HCRX_CMOW (1ULL << 9)
154
+ env->vfp.pregs[i].p[j],
307
+#define HCRX_MCE2 (1ULL << 10)
155
+ j ? ":" : eol ? "\n" : " ");
308
+#define HCRX_MSCEN (1ULL << 11)
156
+ }
309
+
157
+ }
310
+#define HPFAR_NS (1ULL << 63)
158
+
311
+
159
+ for (i = 0; i < 32; i++) {
312
+#define HSTR_TTEE (1 << 16)
160
+ if (zcr_len == 0) {
313
+#define HSTR_TJDBX (1 << 17)
161
+ qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
314
+
162
+ i, env->vfp.zregs[i].d[1],
315
+#define CNTHCTL_CNTVMASK (1 << 18)
163
+ env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
316
+#define CNTHCTL_CNTPMASK (1 << 19)
164
+ } else if (zcr_len == 1) {
317
+
165
+ qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
318
/* We use a few fake FSR values for internal purposes in M profile.
166
+ ":%016" PRIx64 ":%016" PRIx64 "\n",
319
* M profile cores don't have A/R format FSRs, but currently our
167
+ i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
320
* get_phys_addr() code assumes A/R profile and reports failures via
168
+ env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
169
+ } else {
170
+ for (j = zcr_len; j >= 0; j--) {
171
+ bool odd = (zcr_len - j) % 2 != 0;
172
+ if (j == zcr_len) {
173
+ qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
174
+ } else if (!odd) {
175
+ if (j > 0) {
176
+ qemu_fprintf(f, " [%x-%x]=", j, j - 1);
177
+ } else {
178
+ qemu_fprintf(f, " [%x]=", j);
179
+ }
180
+ }
181
+ qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
182
+ env->vfp.zregs[i].d[j * 2 + 1],
183
+ env->vfp.zregs[i].d[j * 2],
184
+ odd || j == 0 ? "\n" : ":");
185
+ }
186
+ }
187
+ }
188
+ } else {
189
+ for (i = 0; i < 32; i++) {
190
+ uint64_t *q = aa64_vfp_qreg(env, i);
191
+ qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
192
+ i, q[1], q[0], (i & 1 ? "\n" : " "));
193
+ }
194
+ }
195
+}
196
+
197
+#else
198
+
199
+static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
200
+{
201
+ g_assert_not_reached();
202
+}
203
+
204
+#endif
205
+
206
+static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
207
+{
208
+ ARMCPU *cpu = ARM_CPU(cs);
209
+ CPUARMState *env = &cpu->env;
210
+ int i;
211
+
212
+ if (is_a64(env)) {
213
+ aarch64_cpu_dump_state(cs, f, flags);
214
+ return;
215
+ }
216
+
217
+ for (i = 0; i < 16; i++) {
218
+ qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
219
+ if ((i % 4) == 3) {
220
+ qemu_fprintf(f, "\n");
221
+ } else {
222
+ qemu_fprintf(f, " ");
223
+ }
224
+ }
225
+
226
+ if (arm_feature(env, ARM_FEATURE_M)) {
227
+ uint32_t xpsr = xpsr_read(env);
228
+ const char *mode;
229
+ const char *ns_status = "";
230
+
231
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
232
+ ns_status = env->v7m.secure ? "S " : "NS ";
233
+ }
234
+
235
+ if (xpsr & XPSR_EXCP) {
236
+ mode = "handler";
237
+ } else {
238
+ if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
239
+ mode = "unpriv-thread";
240
+ } else {
241
+ mode = "priv-thread";
242
+ }
243
+ }
244
+
245
+ qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
246
+ xpsr,
247
+ xpsr & XPSR_N ? 'N' : '-',
248
+ xpsr & XPSR_Z ? 'Z' : '-',
249
+ xpsr & XPSR_C ? 'C' : '-',
250
+ xpsr & XPSR_V ? 'V' : '-',
251
+ xpsr & XPSR_T ? 'T' : 'A',
252
+ ns_status,
253
+ mode);
254
+ } else {
255
+ uint32_t psr = cpsr_read(env);
256
+ const char *ns_status = "";
257
+
258
+ if (arm_feature(env, ARM_FEATURE_EL3) &&
259
+ (psr & CPSR_M) != ARM_CPU_MODE_MON) {
260
+ ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
261
+ }
262
+
263
+ qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
264
+ psr,
265
+ psr & CPSR_N ? 'N' : '-',
266
+ psr & CPSR_Z ? 'Z' : '-',
267
+ psr & CPSR_C ? 'C' : '-',
268
+ psr & CPSR_V ? 'V' : '-',
269
+ psr & CPSR_T ? 'T' : 'A',
270
+ ns_status,
271
+ aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
272
+ }
273
+
274
+ if (flags & CPU_DUMP_FPU) {
275
+ int numvfpregs = 0;
276
+ if (arm_feature(env, ARM_FEATURE_VFP)) {
277
+ numvfpregs += 16;
278
+ }
279
+ if (arm_feature(env, ARM_FEATURE_VFP3)) {
280
+ numvfpregs += 16;
281
+ }
282
+ for (i = 0; i < numvfpregs; i++) {
283
+ uint64_t v = *aa32_vfp_dreg(env, i);
284
+ qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
285
+ i * 2, (uint32_t)v,
286
+ i * 2 + 1, (uint32_t)(v >> 32),
287
+ i, v);
288
+ }
289
+ qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
290
+ }
291
+}
292
+
293
uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
294
{
295
uint32_t Aff1 = idx / clustersz;
296
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
297
index XXXXXXX..XXXXXXX 100644
298
--- a/target/arm/translate-a64.c
299
+++ b/target/arm/translate-a64.c
300
@@ -XXX,XX +XXX,XX @@
301
#include "translate.h"
302
#include "internals.h"
303
#include "qemu/host-utils.h"
304
-#include "qemu/qemu-print.h"
305
306
#include "hw/semihosting/semihost.h"
307
#include "exec/gen-icount.h"
308
@@ -XXX,XX +XXX,XX @@ static void set_btype(DisasContext *s, int val)
309
s->btype = -1;
310
}
311
312
-void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
313
-{
314
- ARMCPU *cpu = ARM_CPU(cs);
315
- CPUARMState *env = &cpu->env;
316
- uint32_t psr = pstate_read(env);
317
- int i;
318
- int el = arm_current_el(env);
319
- const char *ns_status;
320
-
321
- qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
322
- for (i = 0; i < 32; i++) {
323
- if (i == 31) {
324
- qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
325
- } else {
326
- qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
327
- (i + 2) % 3 ? " " : "\n");
328
- }
329
- }
330
-
331
- if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
332
- ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
333
- } else {
334
- ns_status = "";
335
- }
336
- qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
337
- psr,
338
- psr & PSTATE_N ? 'N' : '-',
339
- psr & PSTATE_Z ? 'Z' : '-',
340
- psr & PSTATE_C ? 'C' : '-',
341
- psr & PSTATE_V ? 'V' : '-',
342
- ns_status,
343
- el,
344
- psr & PSTATE_SP ? 'h' : 't');
345
-
346
- if (cpu_isar_feature(aa64_bti, cpu)) {
347
- qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
348
- }
349
- if (!(flags & CPU_DUMP_FPU)) {
350
- qemu_fprintf(f, "\n");
351
- return;
352
- }
353
- if (fp_exception_el(env, el) != 0) {
354
- qemu_fprintf(f, " FPU disabled\n");
355
- return;
356
- }
357
- qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
358
- vfp_get_fpcr(env), vfp_get_fpsr(env));
359
-
360
- if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
361
- int j, zcr_len = sve_zcr_len_for_el(env, el);
362
-
363
- for (i = 0; i <= FFR_PRED_NUM; i++) {
364
- bool eol;
365
- if (i == FFR_PRED_NUM) {
366
- qemu_fprintf(f, "FFR=");
367
- /* It's last, so end the line. */
368
- eol = true;
369
- } else {
370
- qemu_fprintf(f, "P%02d=", i);
371
- switch (zcr_len) {
372
- case 0:
373
- eol = i % 8 == 7;
374
- break;
375
- case 1:
376
- eol = i % 6 == 5;
377
- break;
378
- case 2:
379
- case 3:
380
- eol = i % 3 == 2;
381
- break;
382
- default:
383
- /* More than one quadword per predicate. */
384
- eol = true;
385
- break;
386
- }
387
- }
388
- for (j = zcr_len / 4; j >= 0; j--) {
389
- int digits;
390
- if (j * 4 + 4 <= zcr_len + 1) {
391
- digits = 16;
392
- } else {
393
- digits = (zcr_len % 4 + 1) * 4;
394
- }
395
- qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
396
- env->vfp.pregs[i].p[j],
397
- j ? ":" : eol ? "\n" : " ");
398
- }
399
- }
400
-
401
- for (i = 0; i < 32; i++) {
402
- if (zcr_len == 0) {
403
- qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
404
- i, env->vfp.zregs[i].d[1],
405
- env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
406
- } else if (zcr_len == 1) {
407
- qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
408
- ":%016" PRIx64 ":%016" PRIx64 "\n",
409
- i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
410
- env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
411
- } else {
412
- for (j = zcr_len; j >= 0; j--) {
413
- bool odd = (zcr_len - j) % 2 != 0;
414
- if (j == zcr_len) {
415
- qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
416
- } else if (!odd) {
417
- if (j > 0) {
418
- qemu_fprintf(f, " [%x-%x]=", j, j - 1);
419
- } else {
420
- qemu_fprintf(f, " [%x]=", j);
421
- }
422
- }
423
- qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
424
- env->vfp.zregs[i].d[j * 2 + 1],
425
- env->vfp.zregs[i].d[j * 2],
426
- odd || j == 0 ? "\n" : ":");
427
- }
428
- }
429
- }
430
- } else {
431
- for (i = 0; i < 32; i++) {
432
- uint64_t *q = aa64_vfp_qreg(env, i);
433
- qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
434
- i, q[1], q[0], (i & 1 ? "\n" : " "));
435
- }
436
- }
437
-}
438
-
439
void gen_a64_set_pc_im(uint64_t val)
440
{
441
tcg_gen_movi_i64(cpu_pc, val);
442
diff --git a/target/arm/translate.c b/target/arm/translate.c
443
index XXXXXXX..XXXXXXX 100644
444
--- a/target/arm/translate.c
445
+++ b/target/arm/translate.c
446
@@ -XXX,XX +XXX,XX @@
447
#include "tcg-op-gvec.h"
448
#include "qemu/log.h"
449
#include "qemu/bitops.h"
450
-#include "qemu/qemu-print.h"
451
#include "arm_ldst.h"
452
#include "hw/semihosting/semihost.h"
453
454
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
455
translator_loop(ops, &dc.base, cpu, tb, max_insns);
456
}
457
458
-void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
459
-{
460
- ARMCPU *cpu = ARM_CPU(cs);
461
- CPUARMState *env = &cpu->env;
462
- int i;
463
-
464
- if (is_a64(env)) {
465
- aarch64_cpu_dump_state(cs, f, flags);
466
- return;
467
- }
468
-
469
- for (i = 0; i < 16; i++) {
470
- qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
471
- if ((i % 4) == 3) {
472
- qemu_fprintf(f, "\n");
473
- } else {
474
- qemu_fprintf(f, " ");
475
- }
476
- }
477
-
478
- if (arm_feature(env, ARM_FEATURE_M)) {
479
- uint32_t xpsr = xpsr_read(env);
480
- const char *mode;
481
- const char *ns_status = "";
482
-
483
- if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
484
- ns_status = env->v7m.secure ? "S " : "NS ";
485
- }
486
-
487
- if (xpsr & XPSR_EXCP) {
488
- mode = "handler";
489
- } else {
490
- if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
491
- mode = "unpriv-thread";
492
- } else {
493
- mode = "priv-thread";
494
- }
495
- }
496
-
497
- qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
498
- xpsr,
499
- xpsr & XPSR_N ? 'N' : '-',
500
- xpsr & XPSR_Z ? 'Z' : '-',
501
- xpsr & XPSR_C ? 'C' : '-',
502
- xpsr & XPSR_V ? 'V' : '-',
503
- xpsr & XPSR_T ? 'T' : 'A',
504
- ns_status,
505
- mode);
506
- } else {
507
- uint32_t psr = cpsr_read(env);
508
- const char *ns_status = "";
509
-
510
- if (arm_feature(env, ARM_FEATURE_EL3) &&
511
- (psr & CPSR_M) != ARM_CPU_MODE_MON) {
512
- ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
513
- }
514
-
515
- qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
516
- psr,
517
- psr & CPSR_N ? 'N' : '-',
518
- psr & CPSR_Z ? 'Z' : '-',
519
- psr & CPSR_C ? 'C' : '-',
520
- psr & CPSR_V ? 'V' : '-',
521
- psr & CPSR_T ? 'T' : 'A',
522
- ns_status,
523
- aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
524
- }
525
-
526
- if (flags & CPU_DUMP_FPU) {
527
- int numvfpregs = 0;
528
- if (arm_feature(env, ARM_FEATURE_VFP)) {
529
- numvfpregs += 16;
530
- }
531
- if (arm_feature(env, ARM_FEATURE_VFP3)) {
532
- numvfpregs += 16;
533
- }
534
- for (i = 0; i < numvfpregs; i++) {
535
- uint64_t v = *aa32_vfp_dreg(env, i);
536
- qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
537
- i * 2, (uint32_t)v,
538
- i * 2 + 1, (uint32_t)(v >> 32),
539
- i, v);
540
- }
541
- qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
542
- }
543
-}
544
-
545
void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb,
546
target_ulong *data)
547
{
548
--
321
--
549
2.20.1
322
2.34.1
550
323
551
324
diff view generated by jsdifflib
1
From: Samuel Ortiz <sameo@linux.intel.com>
1
The timer _EL02 registers should UNDEF for invalid accesses from EL2
2
or EL3 when HCR_EL2.E2H == 0, not take a cp access trap. We were
3
delivering the exception to EL2 with the wrong syndrome.
2
4
3
Those helpers are a software implementation of the ARM v8 memory zeroing
4
op code. They should be moved to the op helper file, which is going to
5
eventually be built only when TCG is enabled.
6
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Robert Bradford <robert.bradford@intel.com>
9
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20190701132516.26392-10-philmd@redhat.com
13
[PMD: Rebased]
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20240301183219.2424889-3-peter.maydell@linaro.org
17
---
8
---
18
target/arm/helper.c | 92 -----------------------------------------
9
target/arm/helper.c | 2 +-
19
target/arm/op_helper.c | 93 ++++++++++++++++++++++++++++++++++++++++++
10
1 file changed, 1 insertion(+), 1 deletion(-)
20
2 files changed, 93 insertions(+), 92 deletions(-)
21
11
22
diff --git a/target/arm/helper.c b/target/arm/helper.c
12
diff --git a/target/arm/helper.c b/target/arm/helper.c
23
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/helper.c
14
--- a/target/arm/helper.c
25
+++ b/target/arm/helper.c
15
+++ b/target/arm/helper.c
26
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
16
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
27
#endif
17
return CP_ACCESS_OK;
18
}
19
if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
20
- return CP_ACCESS_TRAP;
21
+ return CP_ACCESS_TRAP_UNCATEGORIZED;
22
}
23
return CP_ACCESS_OK;
28
}
24
}
29
30
-void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
31
-{
32
- /*
33
- * Implement DC ZVA, which zeroes a fixed-length block of memory.
34
- * Note that we do not implement the (architecturally mandated)
35
- * alignment fault for attempts to use this on Device memory
36
- * (which matches the usual QEMU behaviour of not implementing either
37
- * alignment faults or any memory attribute handling).
38
- */
39
-
40
- ARMCPU *cpu = env_archcpu(env);
41
- uint64_t blocklen = 4 << cpu->dcz_blocksize;
42
- uint64_t vaddr = vaddr_in & ~(blocklen - 1);
43
-
44
-#ifndef CONFIG_USER_ONLY
45
- {
46
- /*
47
- * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
48
- * the block size so we might have to do more than one TLB lookup.
49
- * We know that in fact for any v8 CPU the page size is at least 4K
50
- * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
51
- * 1K as an artefact of legacy v5 subpage support being present in the
52
- * same QEMU executable. So in practice the hostaddr[] array has
53
- * two entries, given the current setting of TARGET_PAGE_BITS_MIN.
54
- */
55
- int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
56
- void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)];
57
- int try, i;
58
- unsigned mmu_idx = cpu_mmu_index(env, false);
59
- TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
60
-
61
- assert(maxidx <= ARRAY_SIZE(hostaddr));
62
-
63
- for (try = 0; try < 2; try++) {
64
-
65
- for (i = 0; i < maxidx; i++) {
66
- hostaddr[i] = tlb_vaddr_to_host(env,
67
- vaddr + TARGET_PAGE_SIZE * i,
68
- 1, mmu_idx);
69
- if (!hostaddr[i]) {
70
- break;
71
- }
72
- }
73
- if (i == maxidx) {
74
- /*
75
- * If it's all in the TLB it's fair game for just writing to;
76
- * we know we don't need to update dirty status, etc.
77
- */
78
- for (i = 0; i < maxidx - 1; i++) {
79
- memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
80
- }
81
- memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
82
- return;
83
- }
84
- /*
85
- * OK, try a store and see if we can populate the tlb. This
86
- * might cause an exception if the memory isn't writable,
87
- * in which case we will longjmp out of here. We must for
88
- * this purpose use the actual register value passed to us
89
- * so that we get the fault address right.
90
- */
91
- helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC());
92
- /* Now we can populate the other TLB entries, if any */
93
- for (i = 0; i < maxidx; i++) {
94
- uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
95
- if (va != (vaddr_in & TARGET_PAGE_MASK)) {
96
- helper_ret_stb_mmu(env, va, 0, oi, GETPC());
97
- }
98
- }
99
- }
100
-
101
- /*
102
- * Slow path (probably attempt to do this to an I/O device or
103
- * similar, or clearing of a block of code we have translations
104
- * cached for). Just do a series of byte writes as the architecture
105
- * demands. It's not worth trying to use a cpu_physical_memory_map(),
106
- * memset(), unmap() sequence here because:
107
- * + we'd need to account for the blocksize being larger than a page
108
- * + the direct-RAM access case is almost always going to be dealt
109
- * with in the fastpath code above, so there's no speed benefit
110
- * + we would have to deal with the map returning NULL because the
111
- * bounce buffer was in use
112
- */
113
- for (i = 0; i < blocklen; i++) {
114
- helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC());
115
- }
116
- }
117
-#else
118
- memset(g2h(vaddr), 0, blocklen);
119
-#endif
120
-}
121
-
122
/* Note that signed overflow is undefined in C. The following routines are
123
careful to use unsigned types where modulo arithmetic is required.
124
Failure to do so _will_ break on newer gcc. */
125
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
126
index XXXXXXX..XXXXXXX 100644
127
--- a/target/arm/op_helper.c
128
+++ b/target/arm/op_helper.c
129
@@ -XXX,XX +XXX,XX @@
130
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
131
*/
132
#include "qemu/osdep.h"
133
+#include "qemu/units.h"
134
#include "qemu/log.h"
135
#include "qemu/main-loop.h"
136
#include "cpu.h"
137
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
138
return ((uint32_t)x >> shift) | (x << (32 - shift));
139
}
140
}
141
+
142
+void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
143
+{
144
+ /*
145
+ * Implement DC ZVA, which zeroes a fixed-length block of memory.
146
+ * Note that we do not implement the (architecturally mandated)
147
+ * alignment fault for attempts to use this on Device memory
148
+ * (which matches the usual QEMU behaviour of not implementing either
149
+ * alignment faults or any memory attribute handling).
150
+ */
151
+
152
+ ARMCPU *cpu = env_archcpu(env);
153
+ uint64_t blocklen = 4 << cpu->dcz_blocksize;
154
+ uint64_t vaddr = vaddr_in & ~(blocklen - 1);
155
+
156
+#ifndef CONFIG_USER_ONLY
157
+ {
158
+ /*
159
+ * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
160
+ * the block size so we might have to do more than one TLB lookup.
161
+ * We know that in fact for any v8 CPU the page size is at least 4K
162
+ * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
163
+ * 1K as an artefact of legacy v5 subpage support being present in the
164
+ * same QEMU executable. So in practice the hostaddr[] array has
165
+ * two entries, given the current setting of TARGET_PAGE_BITS_MIN.
166
+ */
167
+ int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
168
+ void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)];
169
+ int try, i;
170
+ unsigned mmu_idx = cpu_mmu_index(env, false);
171
+ TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
172
+
173
+ assert(maxidx <= ARRAY_SIZE(hostaddr));
174
+
175
+ for (try = 0; try < 2; try++) {
176
+
177
+ for (i = 0; i < maxidx; i++) {
178
+ hostaddr[i] = tlb_vaddr_to_host(env,
179
+ vaddr + TARGET_PAGE_SIZE * i,
180
+ 1, mmu_idx);
181
+ if (!hostaddr[i]) {
182
+ break;
183
+ }
184
+ }
185
+ if (i == maxidx) {
186
+ /*
187
+ * If it's all in the TLB it's fair game for just writing to;
188
+ * we know we don't need to update dirty status, etc.
189
+ */
190
+ for (i = 0; i < maxidx - 1; i++) {
191
+ memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
192
+ }
193
+ memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
194
+ return;
195
+ }
196
+ /*
197
+ * OK, try a store and see if we can populate the tlb. This
198
+ * might cause an exception if the memory isn't writable,
199
+ * in which case we will longjmp out of here. We must for
200
+ * this purpose use the actual register value passed to us
201
+ * so that we get the fault address right.
202
+ */
203
+ helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC());
204
+ /* Now we can populate the other TLB entries, if any */
205
+ for (i = 0; i < maxidx; i++) {
206
+ uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
207
+ if (va != (vaddr_in & TARGET_PAGE_MASK)) {
208
+ helper_ret_stb_mmu(env, va, 0, oi, GETPC());
209
+ }
210
+ }
211
+ }
212
+
213
+ /*
214
+ * Slow path (probably attempt to do this to an I/O device or
215
+ * similar, or clearing of a block of code we have translations
216
+ * cached for). Just do a series of byte writes as the architecture
217
+ * demands. It's not worth trying to use a cpu_physical_memory_map(),
218
+ * memset(), unmap() sequence here because:
219
+ * + we'd need to account for the blocksize being larger than a page
220
+ * + the direct-RAM access case is almost always going to be dealt
221
+ * with in the fastpath code above, so there's no speed benefit
222
+ * + we would have to deal with the map returning NULL because the
223
+ * bounce buffer was in use
224
+ */
225
+ for (i = 0; i < blocklen; i++) {
226
+ helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC());
227
+ }
228
+ }
229
+#else
230
+ memset(g2h(vaddr), 0, blocklen);
231
+#endif
232
+}
233
--
25
--
234
2.20.1
26
2.34.1
235
236
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
We prefer the FIELD macro over ad-hoc #defines for register bits;
2
switch CNTHCTL to that style before we add any more bits.
2
3
3
In the next commit we will split the M-profile functions from this
4
file. Some function will be called out of helper.c. Declare them in
5
the "internals.h" header.
6
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190701132516.26392-22-philmd@redhat.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20240301183219.2424889-4-peter.maydell@linaro.org
11
---
8
---
12
target/arm/internals.h | 42 ++++++++++++++++++++++++++++++++++++++++++
9
target/arm/internals.h | 27 +++++++++++++++++++++++++--
13
target/arm/helper.c | 38 ++------------------------------------
10
target/arm/helper.c | 9 ++++-----
14
2 files changed, 44 insertions(+), 36 deletions(-)
11
2 files changed, 29 insertions(+), 7 deletions(-)
15
12
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
13
diff --git a/target/arm/internals.h b/target/arm/internals.h
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/internals.h
15
--- a/target/arm/internals.h
19
+++ b/target/arm/internals.h
16
+++ b/target/arm/internals.h
20
@@ -XXX,XX +XXX,XX @@ static inline uint32_t v7m_sp_limit(CPUARMState *env)
17
@@ -XXX,XX +XXX,XX @@ FIELD(VTCR, SL2, 33, 1)
21
}
18
#define HSTR_TTEE (1 << 16)
22
}
19
#define HSTR_TJDBX (1 << 17)
23
20
24
+/**
21
-#define CNTHCTL_CNTVMASK (1 << 18)
25
+ * v7m_cpacr_pass:
22
-#define CNTHCTL_CNTPMASK (1 << 19)
26
+ * Return true if the v7M CPACR permits access to the FPU for the specified
23
+/*
27
+ * security state and privilege level.
24
+ * Depending on the value of HCR_EL2.E2H, bits 0 and 1
25
+ * have different bit definitions, and EL1PCTEN might be
26
+ * bit 0 or bit 10. We use _E2H1 and _E2H0 suffixes to
27
+ * disambiguate if necessary.
28
+ */
28
+ */
29
+static inline bool v7m_cpacr_pass(CPUARMState *env,
29
+FIELD(CNTHCTL, EL0PCTEN_E2H1, 0, 1)
30
+ bool is_secure, bool is_priv)
30
+FIELD(CNTHCTL, EL0VCTEN_E2H1, 1, 1)
31
+{
31
+FIELD(CNTHCTL, EL1PCTEN_E2H0, 0, 1)
32
+ switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {
32
+FIELD(CNTHCTL, EL1PCEN_E2H0, 1, 1)
33
+ case 0:
33
+FIELD(CNTHCTL, EVNTEN, 2, 1)
34
+ case 2: /* UNPREDICTABLE: we treat like 0 */
34
+FIELD(CNTHCTL, EVNTDIR, 3, 1)
35
+ return false;
35
+FIELD(CNTHCTL, EVNTI, 4, 4)
36
+ case 1:
36
+FIELD(CNTHCTL, EL0VTEN, 8, 1)
37
+ return is_priv;
37
+FIELD(CNTHCTL, EL0PTEN, 9, 1)
38
+ case 3:
38
+FIELD(CNTHCTL, EL1PCTEN_E2H1, 10, 1)
39
+ return true;
39
+FIELD(CNTHCTL, EL1PTEN, 11, 1)
40
+ default:
40
+FIELD(CNTHCTL, ECV, 12, 1)
41
+ g_assert_not_reached();
41
+FIELD(CNTHCTL, EL1TVT, 13, 1)
42
+ }
42
+FIELD(CNTHCTL, EL1TVCT, 14, 1)
43
+}
43
+FIELD(CNTHCTL, EL1NVPCT, 15, 1)
44
+
44
+FIELD(CNTHCTL, EL1NVVCT, 16, 1)
45
/**
45
+FIELD(CNTHCTL, EVNTIS, 17, 1)
46
* aarch32_mode_name(): Return name of the AArch32 CPU mode
46
+FIELD(CNTHCTL, CNTVMASK, 18, 1)
47
* @psr: Program Status Register indicating CPU mode
47
+FIELD(CNTHCTL, CNTPMASK, 19, 1)
48
@@ -XXX,XX +XXX,XX @@ static inline int exception_target_el(CPUARMState *env)
48
49
49
/* We use a few fake FSR values for internal purposes in M profile.
50
#ifndef CONFIG_USER_ONLY
50
* M profile cores don't have A/R format FSRs, but currently our
51
52
+/* Security attributes for an address, as returned by v8m_security_lookup. */
53
+typedef struct V8M_SAttributes {
54
+ bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */
55
+ bool ns;
56
+ bool nsc;
57
+ uint8_t sregion;
58
+ bool srvalid;
59
+ uint8_t iregion;
60
+ bool irvalid;
61
+} V8M_SAttributes;
62
+
63
+void v8m_security_lookup(CPUARMState *env, uint32_t address,
64
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
65
+ V8M_SAttributes *sattrs);
66
+
67
+bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
68
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
69
+ hwaddr *phys_ptr, MemTxAttrs *txattrs,
70
+ int *prot, bool *is_subpage,
71
+ ARMMMUFaultInfo *fi, uint32_t *mregion);
72
+
73
/* Cacheability and shareability attributes for a memory access */
74
typedef struct ARMCacheAttrs {
75
unsigned int attrs:8; /* as in the MAIR register encoding */
76
diff --git a/target/arm/helper.c b/target/arm/helper.c
51
diff --git a/target/arm/helper.c b/target/arm/helper.c
77
index XXXXXXX..XXXXXXX 100644
52
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/helper.c
53
--- a/target/arm/helper.c
79
+++ b/target/arm/helper.c
54
+++ b/target/arm/helper.c
80
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
55
@@ -XXX,XX +XXX,XX @@ static void gt_update_irq(ARMCPU *cpu, int timeridx)
81
hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
56
* It is RES0 in Secure and NonSecure state.
82
target_ulong *page_size_ptr,
57
*/
83
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
58
if ((ss == ARMSS_Root || ss == ARMSS_Realm) &&
59
- ((timeridx == GTIMER_VIRT && (cnthctl & CNTHCTL_CNTVMASK)) ||
60
- (timeridx == GTIMER_PHYS && (cnthctl & CNTHCTL_CNTPMASK)))) {
61
+ ((timeridx == GTIMER_VIRT && (cnthctl & R_CNTHCTL_CNTVMASK_MASK)) ||
62
+ (timeridx == GTIMER_PHYS && (cnthctl & R_CNTHCTL_CNTPMASK_MASK)))) {
63
irqstate = 0;
64
}
65
66
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
67
{
68
ARMCPU *cpu = env_archcpu(env);
69
uint32_t oldval = env->cp15.cnthctl_el2;
84
-
70
-
85
-/* Security attributes for an address, as returned by v8m_security_lookup. */
71
raw_write(env, ri, value);
86
-typedef struct V8M_SAttributes {
72
87
- bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */
73
- if ((oldval ^ value) & CNTHCTL_CNTVMASK) {
88
- bool ns;
74
+ if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) {
89
- bool nsc;
75
gt_update_irq(cpu, GTIMER_VIRT);
90
- uint8_t sregion;
76
- } else if ((oldval ^ value) & CNTHCTL_CNTPMASK) {
91
- bool srvalid;
77
+ } else if ((oldval ^ value) & R_CNTHCTL_CNTPMASK_MASK) {
92
- uint8_t iregion;
78
gt_update_irq(cpu, GTIMER_PHYS);
93
- bool irvalid;
94
-} V8M_SAttributes;
95
-
96
-static void v8m_security_lookup(CPUARMState *env, uint32_t address,
97
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
98
- V8M_SAttributes *sattrs);
99
#endif
100
101
static void switch_mode(CPUARMState *env, int mode);
102
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(int idx)
103
}
79
}
104
}
80
}
105
106
-/*
107
- * Return true if the v7M CPACR permits access to the FPU for the specified
108
- * security state and privilege level.
109
- */
110
-static bool v7m_cpacr_pass(CPUARMState *env, bool is_secure, bool is_priv)
111
-{
112
- switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {
113
- case 0:
114
- case 2: /* UNPREDICTABLE: we treat like 0 */
115
- return false;
116
- case 1:
117
- return is_priv;
118
- case 3:
119
- return true;
120
- default:
121
- g_assert_not_reached();
122
- }
123
-}
124
-
125
/*
126
* What kind of stack write are we doing? This affects how exceptions
127
* generated during the stacking are treated.
128
@@ -XXX,XX +XXX,XX @@ static bool v8m_is_sau_exempt(CPUARMState *env,
129
(address >= 0xe00ff000 && address <= 0xe00fffff);
130
}
131
132
-static void v8m_security_lookup(CPUARMState *env, uint32_t address,
133
+void v8m_security_lookup(CPUARMState *env, uint32_t address,
134
MMUAccessType access_type, ARMMMUIdx mmu_idx,
135
V8M_SAttributes *sattrs)
136
{
137
@@ -XXX,XX +XXX,XX @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address,
138
}
139
}
140
141
-static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
142
+bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
143
MMUAccessType access_type, ARMMMUIdx mmu_idx,
144
hwaddr *phys_ptr, MemTxAttrs *txattrs,
145
int *prot, bool *is_subpage,
146
--
81
--
147
2.20.1
82
2.34.1
148
83
149
84
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Don't allow the guest to write CNTHCTL_EL2 bits which don't exist.
2
This is not strictly architecturally required, but it is how we've
3
tended to implement registers more recently.
2
4
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
In particular, bits [19:18] are only present with FEAT_RME,
4
Message-id: 20190701132516.26392-7-philmd@redhat.com
6
and bits [17:12] will only be present with FEAT_ECV.
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20240301183219.2424889-5-peter.maydell@linaro.org
7
---
11
---
8
target/arm/helper.c | 2 --
12
target/arm/helper.c | 18 ++++++++++++++++++
9
1 file changed, 2 deletions(-)
13
1 file changed, 18 insertions(+)
10
14
11
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/helper.c
17
--- a/target/arm/helper.c
14
+++ b/target/arm/helper.c
18
+++ b/target/arm/helper.c
15
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
16
#include "exec/gdbstub.h"
20
{
17
#include "exec/helper-proto.h"
21
ARMCPU *cpu = env_archcpu(env);
18
#include "qemu/host-utils.h"
22
uint32_t oldval = env->cp15.cnthctl_el2;
19
-#include "sysemu/arch_init.h"
23
+ uint32_t valid_mask =
20
#include "sysemu/sysemu.h"
24
+ R_CNTHCTL_EL0PCTEN_E2H1_MASK |
21
#include "qemu/bitops.h"
25
+ R_CNTHCTL_EL0VCTEN_E2H1_MASK |
22
#include "qemu/crc32c.h"
26
+ R_CNTHCTL_EVNTEN_MASK |
23
@@ -XXX,XX +XXX,XX @@
27
+ R_CNTHCTL_EVNTDIR_MASK |
24
#include "hw/semihosting/semihost.h"
28
+ R_CNTHCTL_EVNTI_MASK |
25
#include "sysemu/cpus.h"
29
+ R_CNTHCTL_EL0VTEN_MASK |
26
#include "sysemu/kvm.h"
30
+ R_CNTHCTL_EL0PTEN_MASK |
27
-#include "fpu/softfloat.h"
31
+ R_CNTHCTL_EL1PCTEN_E2H1_MASK |
28
#include "qemu/range.h"
32
+ R_CNTHCTL_EL1PTEN_MASK;
29
#include "qapi/qapi-commands-target.h"
33
+
30
#include "qapi/error.h"
34
+ if (cpu_isar_feature(aa64_rme, cpu)) {
35
+ valid_mask |= R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK;
36
+ }
37
+
38
+ /* Clear RES0 bits */
39
+ value &= valid_mask;
40
+
41
raw_write(env, ri, value);
42
43
if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) {
31
--
44
--
32
2.20.1
45
2.34.1
33
34
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
The functionality defined by ID_AA64MMFR0_EL1.ECV == 1 is:
2
* four new trap bits for various counter and timer registers
3
* the CNTHCTL_EL2.EVNTIS and CNTKCTL_EL1.EVNTIS bits which control
4
scaling of the event stream. This is a no-op for us, because we don't
5
implement the event stream (our WFE is a NOP): all we need to do is
6
allow CNTHCTL_EL2.ENVTIS to be read and written.
7
* extensions to PMSCR_EL1.PCT, PMSCR_EL2.PCT, TRFCR_EL1.TS and
8
TRFCR_EL2.TS: these are all no-ops for us, because we don't implement
9
FEAT_SPE or FEAT_TRF.
10
* new registers CNTPCTSS_EL0 and NCTVCTSS_EL0 which are
11
"self-sychronizing" views of the CNTPCT_EL0 and CNTVCT_EL0, meaning
12
that no barriers are needed around their accesses. For us these
13
are just the same as the normal views, because all our sysregs are
14
inherently self-sychronizing.
2
15
3
In few commits we will split the M-profile functions from this
16
In this commit we implement the trap handling and permit the new
4
file, and this function will also be called in the new file.
17
CNTHCTL_EL2 bits to be written.
5
Declare it in the "internals.h" header.
6
Since it is in the middle of a block of M profile functions,
7
move it previous to this block to ease the later refactor.
8
18
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 20190701132516.26392-21-philmd@redhat.com
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 20240301183219.2424889-6-peter.maydell@linaro.org
13
---
22
---
14
target/arm/internals.h | 2 ++
23
target/arm/cpu-features.h | 5 ++++
15
target/arm/helper.c | 76 +++++++++++++++++++++---------------------
24
target/arm/helper.c | 51 +++++++++++++++++++++++++++++++++++----
16
2 files changed, 40 insertions(+), 38 deletions(-)
25
2 files changed, 51 insertions(+), 5 deletions(-)
17
26
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
27
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
19
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/internals.h
29
--- a/target/arm/cpu-features.h
21
+++ b/target/arm/internals.h
30
+++ b/target/arm/cpu-features.h
22
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
31
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
23
target_ulong *page_size,
32
return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
24
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
33
}
25
34
26
+void arm_log_exception(int idx);
35
+static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id)
36
+{
37
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0;
38
+}
27
+
39
+
28
#endif /* !CONFIG_USER_ONLY */
40
static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
29
41
{
30
#endif
42
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
31
diff --git a/target/arm/helper.c b/target/arm/helper.c
43
diff --git a/target/arm/helper.c b/target/arm/helper.c
32
index XXXXXXX..XXXXXXX 100644
44
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/helper.c
45
--- a/target/arm/helper.c
34
+++ b/target/arm/helper.c
46
+++ b/target/arm/helper.c
35
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
47
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
36
return target_el;
48
: !extract32(env->cp15.cnthctl_el2, 0, 1))) {
49
return CP_ACCESS_TRAP_EL2;
50
}
51
+ if (has_el2 && timeridx == GTIMER_VIRT) {
52
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVCT)) {
53
+ return CP_ACCESS_TRAP_EL2;
54
+ }
55
+ }
56
break;
57
}
58
return CP_ACCESS_OK;
59
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
60
}
61
}
62
}
63
+ if (has_el2 && timeridx == GTIMER_VIRT) {
64
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVT)) {
65
+ return CP_ACCESS_TRAP_EL2;
66
+ }
67
+ }
68
break;
69
}
70
return CP_ACCESS_OK;
71
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
72
if (cpu_isar_feature(aa64_rme, cpu)) {
73
valid_mask |= R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK;
74
}
75
+ if (cpu_isar_feature(aa64_ecv_traps, cpu)) {
76
+ valid_mask |=
77
+ R_CNTHCTL_EL1TVT_MASK |
78
+ R_CNTHCTL_EL1TVCT_MASK |
79
+ R_CNTHCTL_EL1NVPCT_MASK |
80
+ R_CNTHCTL_EL1NVVCT_MASK |
81
+ R_CNTHCTL_EVNTIS_MASK;
82
+ }
83
84
/* Clear RES0 bits */
85
value &= valid_mask;
86
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
87
{
88
if (arm_current_el(env) == 1) {
89
/* This must be a FEAT_NV access */
90
- /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */
91
return CP_ACCESS_OK;
92
}
93
if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
94
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
95
return CP_ACCESS_OK;
37
}
96
}
38
97
39
+void arm_log_exception(int idx)
98
+static CPAccessResult access_el1nvpct(CPUARMState *env, const ARMCPRegInfo *ri,
99
+ bool isread)
40
+{
100
+{
41
+ if (qemu_loglevel_mask(CPU_LOG_INT)) {
101
+ if (arm_current_el(env) == 1) {
42
+ const char *exc = NULL;
102
+ /* This must be a FEAT_NV access with NVx == 101 */
43
+ static const char * const excnames[] = {
103
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVPCT)) {
44
+ [EXCP_UDEF] = "Undefined Instruction",
104
+ return CP_ACCESS_TRAP_EL2;
45
+ [EXCP_SWI] = "SVC",
46
+ [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
47
+ [EXCP_DATA_ABORT] = "Data Abort",
48
+ [EXCP_IRQ] = "IRQ",
49
+ [EXCP_FIQ] = "FIQ",
50
+ [EXCP_BKPT] = "Breakpoint",
51
+ [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
52
+ [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
53
+ [EXCP_HVC] = "Hypervisor Call",
54
+ [EXCP_HYP_TRAP] = "Hypervisor Trap",
55
+ [EXCP_SMC] = "Secure Monitor Call",
56
+ [EXCP_VIRQ] = "Virtual IRQ",
57
+ [EXCP_VFIQ] = "Virtual FIQ",
58
+ [EXCP_SEMIHOST] = "Semihosting call",
59
+ [EXCP_NOCP] = "v7M NOCP UsageFault",
60
+ [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
61
+ [EXCP_STKOF] = "v8M STKOF UsageFault",
62
+ [EXCP_LAZYFP] = "v7M exception during lazy FP stacking",
63
+ [EXCP_LSERR] = "v8M LSERR UsageFault",
64
+ [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
65
+ };
66
+
67
+ if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
68
+ exc = excnames[idx];
69
+ }
105
+ }
70
+ if (!exc) {
71
+ exc = "unknown";
72
+ }
73
+ qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
74
+ }
106
+ }
107
+ return e2h_access(env, ri, isread);
75
+}
108
+}
76
+
109
+
77
/*
110
+static CPAccessResult access_el1nvvct(CPUARMState *env, const ARMCPRegInfo *ri,
78
* Return true if the v7M CPACR permits access to the FPU for the specified
111
+ bool isread)
79
* security state and privilege level.
112
+{
80
@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
113
+ if (arm_current_el(env) == 1) {
81
return true;
114
+ /* This must be a FEAT_NV access with NVx == 101 */
82
}
115
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVVCT)) {
83
116
+ return CP_ACCESS_TRAP_EL2;
84
-static void arm_log_exception(int idx)
117
+ }
85
-{
118
+ }
86
- if (qemu_loglevel_mask(CPU_LOG_INT)) {
119
+ return e2h_access(env, ri, isread);
87
- const char *exc = NULL;
120
+}
88
- static const char * const excnames[] = {
121
+
89
- [EXCP_UDEF] = "Undefined Instruction",
122
/* Test if system register redirection is to occur in the current state. */
90
- [EXCP_SWI] = "SVC",
123
static bool redirect_for_e2h(CPUARMState *env)
91
- [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
92
- [EXCP_DATA_ABORT] = "Data Abort",
93
- [EXCP_IRQ] = "IRQ",
94
- [EXCP_FIQ] = "FIQ",
95
- [EXCP_BKPT] = "Breakpoint",
96
- [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
97
- [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
98
- [EXCP_HVC] = "Hypervisor Call",
99
- [EXCP_HYP_TRAP] = "Hypervisor Trap",
100
- [EXCP_SMC] = "Secure Monitor Call",
101
- [EXCP_VIRQ] = "Virtual IRQ",
102
- [EXCP_VFIQ] = "Virtual FIQ",
103
- [EXCP_SEMIHOST] = "Semihosting call",
104
- [EXCP_NOCP] = "v7M NOCP UsageFault",
105
- [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
106
- [EXCP_STKOF] = "v8M STKOF UsageFault",
107
- [EXCP_LAZYFP] = "v7M exception during lazy FP stacking",
108
- [EXCP_LSERR] = "v8M LSERR UsageFault",
109
- [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
110
- };
111
-
112
- if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
113
- exc = excnames[idx];
114
- }
115
- if (!exc) {
116
- exc = "unknown";
117
- }
118
- qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
119
- }
120
-}
121
-
122
static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
123
uint32_t addr, uint16_t *insn)
124
{
124
{
125
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
126
{ .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64,
127
.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1,
128
.type = ARM_CP_IO | ARM_CP_ALIAS,
129
- .access = PL2_RW, .accessfn = e2h_access,
130
+ .access = PL2_RW, .accessfn = access_el1nvpct,
131
.nv2_redirect_offset = 0x180 | NV2_REDIR_NO_NV1,
132
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
133
.writefn = gt_phys_ctl_write, .raw_writefn = raw_write },
134
{ .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64,
135
.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1,
136
.type = ARM_CP_IO | ARM_CP_ALIAS,
137
- .access = PL2_RW, .accessfn = e2h_access,
138
+ .access = PL2_RW, .accessfn = access_el1nvvct,
139
.nv2_redirect_offset = 0x170 | NV2_REDIR_NO_NV1,
140
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
141
.writefn = gt_virt_ctl_write, .raw_writefn = raw_write },
142
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
143
.type = ARM_CP_IO | ARM_CP_ALIAS,
144
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
145
.nv2_redirect_offset = 0x178 | NV2_REDIR_NO_NV1,
146
- .access = PL2_RW, .accessfn = e2h_access,
147
+ .access = PL2_RW, .accessfn = access_el1nvpct,
148
.writefn = gt_phys_cval_write, .raw_writefn = raw_write },
149
{ .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64,
150
.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2,
151
.type = ARM_CP_IO | ARM_CP_ALIAS,
152
.nv2_redirect_offset = 0x168 | NV2_REDIR_NO_NV1,
153
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
154
- .access = PL2_RW, .accessfn = e2h_access,
155
+ .access = PL2_RW, .accessfn = access_el1nvvct,
156
.writefn = gt_virt_cval_write, .raw_writefn = raw_write },
157
#endif
158
};
125
--
159
--
126
2.20.1
160
2.34.1
127
128
diff view generated by jsdifflib
1
From: Cédric Le Goater <clg@kaod.org>
1
For FEAT_ECV, new registers CNTPCTSS_EL0 and CNTVCTSS_EL0 are
2
defined, which are "self-synchronized" views of the physical and
3
virtual counts as seen in the CNTPCT_EL0 and CNTVCT_EL0 registers
4
(meaning that no barriers are needed around accesses to them to
5
ensure that reads of them do not occur speculatively and out-of-order
6
with other instructions).
2
7
3
This will simplify the definition of new SoCs, like the AST2600 which
8
For QEMU, all our system registers are self-synchronized, so we can
4
should use a slightly different address space and have a different set
9
simply copy the existing implementation of CNTPCT_EL0 and CNTVCT_EL0
5
of controllers.
10
to the new register encodings.
6
11
7
Signed-off-by: Cédric Le Goater <clg@kaod.org>
12
This means we now implement all the functionality required for
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
ID_AA64MMFR0_EL1.ECV == 0b0001.
9
Reviewed-by: Joel Stanley <joel@jms.id.au>
14
10
Message-id: 20190618165311.27066-3-clg@kaod.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20240301183219.2424889-7-peter.maydell@linaro.org
12
---
18
---
13
include/hw/arm/aspeed_soc.h | 4 +-
19
target/arm/helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++
14
hw/arm/aspeed.c | 8 +--
20
1 file changed, 43 insertions(+)
15
hw/arm/aspeed_soc.c | 117 ++++++++++++++++++++++--------------
16
3 files changed, 78 insertions(+), 51 deletions(-)
17
21
18
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
22
diff --git a/target/arm/helper.c b/target/arm/helper.c
19
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/aspeed_soc.h
24
--- a/target/arm/helper.c
21
+++ b/include/hw/arm/aspeed_soc.h
25
+++ b/target/arm/helper.c
22
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCInfo {
26
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
23
const char *name;
27
},
24
const char *cpu_type;
25
uint32_t silicon_rev;
26
- hwaddr sdram_base;
27
uint64_t sram_size;
28
int spis_num;
29
- const hwaddr *spi_bases;
30
const char *fmc_typename;
31
const char **spi_typename;
32
int wdts_num;
33
const int *irqmap;
34
+ const hwaddr *memmap;
35
} AspeedSoCInfo;
36
37
typedef struct AspeedSoCClass {
38
@@ -XXX,XX +XXX,XX @@ enum {
39
ASPEED_I2C,
40
ASPEED_ETH1,
41
ASPEED_ETH2,
42
+ ASPEED_SDRAM,
43
};
28
};
44
29
45
#endif /* ASPEED_SOC_H */
30
+/*
46
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
31
+ * FEAT_ECV adds extra views of CNTVCT_EL0 and CNTPCT_EL0 which
47
index XXXXXXX..XXXXXXX 100644
32
+ * are "self-synchronizing". For QEMU all sysregs are self-synchronizing,
48
--- a/hw/arm/aspeed.c
33
+ * so our implementations here are identical to the normal registers.
49
+++ b/hw/arm/aspeed.c
34
+ */
50
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
35
+static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = {
51
&error_abort);
36
+ { .name = "CNTVCTSS", .cp = 15, .crm = 14, .opc1 = 9,
52
37
+ .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
53
memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
38
+ .accessfn = gt_vct_access,
54
- memory_region_add_subregion(get_system_memory(), sc->info->sdram_base,
39
+ .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
55
- &bmc->ram);
40
+ },
56
+ memory_region_add_subregion(get_system_memory(),
41
+ { .name = "CNTVCTSS_EL0", .state = ARM_CP_STATE_AA64,
57
+ sc->info->memmap[ASPEED_SDRAM], &bmc->ram);
42
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 6,
58
object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
43
+ .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
59
&error_abort);
44
+ .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
60
45
+ },
61
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
46
+ { .name = "CNTPCTSS", .cp = 15, .crm = 14, .opc1 = 8,
62
memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
47
+ .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
63
"max_ram", max_ram_size - ram_size);
48
+ .accessfn = gt_pct_access,
64
memory_region_add_subregion(get_system_memory(),
49
+ .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
65
- sc->info->sdram_base + ram_size,
50
+ },
66
+ sc->info->memmap[ASPEED_SDRAM] + ram_size,
51
+ { .name = "CNTPCTSS_EL0", .state = ARM_CP_STATE_AA64,
67
&bmc->max_ram);
52
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 5,
68
53
+ .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
69
aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);
54
+ .accessfn = gt_pct_access, .readfn = gt_cnt_read,
70
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
55
+ },
71
aspeed_board_binfo.initrd_filename = machine->initrd_filename;
72
aspeed_board_binfo.kernel_cmdline = machine->kernel_cmdline;
73
aspeed_board_binfo.ram_size = ram_size;
74
- aspeed_board_binfo.loader_start = sc->info->sdram_base;
75
+ aspeed_board_binfo.loader_start = sc->info->memmap[ASPEED_SDRAM];
76
77
if (cfg->i2c_init) {
78
cfg->i2c_init(bmc);
79
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/arm/aspeed_soc.c
82
+++ b/hw/arm/aspeed_soc.c
83
@@ -XXX,XX +XXX,XX @@
84
#include "hw/i2c/aspeed_i2c.h"
85
#include "net/net.h"
86
87
-#define ASPEED_SOC_UART_5_BASE 0x00184000
88
#define ASPEED_SOC_IOMEM_SIZE 0x00200000
89
-#define ASPEED_SOC_IOMEM_BASE 0x1E600000
90
-#define ASPEED_SOC_FMC_BASE 0x1E620000
91
-#define ASPEED_SOC_SPI_BASE 0x1E630000
92
-#define ASPEED_SOC_SPI2_BASE 0x1E631000
93
-#define ASPEED_SOC_VIC_BASE 0x1E6C0000
94
-#define ASPEED_SOC_SDMC_BASE 0x1E6E0000
95
-#define ASPEED_SOC_SCU_BASE 0x1E6E2000
96
-#define ASPEED_SOC_SRAM_BASE 0x1E720000
97
-#define ASPEED_SOC_TIMER_BASE 0x1E782000
98
-#define ASPEED_SOC_WDT_BASE 0x1E785000
99
-#define ASPEED_SOC_I2C_BASE 0x1E78A000
100
-#define ASPEED_SOC_ETH1_BASE 0x1E660000
101
-#define ASPEED_SOC_ETH2_BASE 0x1E680000
102
+
103
+static const hwaddr aspeed_soc_ast2400_memmap[] = {
104
+ [ASPEED_IOMEM] = 0x1E600000,
105
+ [ASPEED_FMC] = 0x1E620000,
106
+ [ASPEED_SPI1] = 0x1E630000,
107
+ [ASPEED_VIC] = 0x1E6C0000,
108
+ [ASPEED_SDMC] = 0x1E6E0000,
109
+ [ASPEED_SCU] = 0x1E6E2000,
110
+ [ASPEED_ADC] = 0x1E6E9000,
111
+ [ASPEED_SRAM] = 0x1E720000,
112
+ [ASPEED_GPIO] = 0x1E780000,
113
+ [ASPEED_RTC] = 0x1E781000,
114
+ [ASPEED_TIMER1] = 0x1E782000,
115
+ [ASPEED_WDT] = 0x1E785000,
116
+ [ASPEED_PWM] = 0x1E786000,
117
+ [ASPEED_LPC] = 0x1E789000,
118
+ [ASPEED_IBT] = 0x1E789140,
119
+ [ASPEED_I2C] = 0x1E78A000,
120
+ [ASPEED_ETH1] = 0x1E660000,
121
+ [ASPEED_ETH2] = 0x1E680000,
122
+ [ASPEED_UART1] = 0x1E783000,
123
+ [ASPEED_UART5] = 0x1E784000,
124
+ [ASPEED_VUART] = 0x1E787000,
125
+ [ASPEED_SDRAM] = 0x40000000,
126
+};
56
+};
127
+
57
+
128
+static const hwaddr aspeed_soc_ast2500_memmap[] = {
58
#else
129
+ [ASPEED_IOMEM] = 0x1E600000,
59
130
+ [ASPEED_FMC] = 0x1E620000,
60
/*
131
+ [ASPEED_SPI1] = 0x1E630000,
61
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
132
+ [ASPEED_SPI2] = 0x1E631000,
133
+ [ASPEED_VIC] = 0x1E6C0000,
134
+ [ASPEED_SDMC] = 0x1E6E0000,
135
+ [ASPEED_SCU] = 0x1E6E2000,
136
+ [ASPEED_ADC] = 0x1E6E9000,
137
+ [ASPEED_SRAM] = 0x1E720000,
138
+ [ASPEED_GPIO] = 0x1E780000,
139
+ [ASPEED_RTC] = 0x1E781000,
140
+ [ASPEED_TIMER1] = 0x1E782000,
141
+ [ASPEED_WDT] = 0x1E785000,
142
+ [ASPEED_PWM] = 0x1E786000,
143
+ [ASPEED_LPC] = 0x1E789000,
144
+ [ASPEED_IBT] = 0x1E789140,
145
+ [ASPEED_I2C] = 0x1E78A000,
146
+ [ASPEED_ETH1] = 0x1E660000,
147
+ [ASPEED_ETH2] = 0x1E680000,
148
+ [ASPEED_UART1] = 0x1E783000,
149
+ [ASPEED_UART5] = 0x1E784000,
150
+ [ASPEED_VUART] = 0x1E787000,
151
+ [ASPEED_SDRAM] = 0x80000000,
152
+};
153
154
static const int aspeed_soc_ast2400_irqmap[] = {
155
[ASPEED_UART1] = 9,
156
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2400_irqmap[] = {
157
[ASPEED_ETH2] = 3,
158
};
159
160
-#define AST2400_SDRAM_BASE 0x40000000
161
-#define AST2500_SDRAM_BASE 0x80000000
162
-
163
-/* AST2500 uses the same IRQs as the AST2400 */
164
#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
165
166
-static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE };
167
static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
168
-
169
-static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE,
170
- ASPEED_SOC_SPI2_BASE};
171
static const char *aspeed_soc_ast2500_typenames[] = {
172
"aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
173
174
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
175
.name = "ast2400-a0",
176
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
177
.silicon_rev = AST2400_A0_SILICON_REV,
178
- .sdram_base = AST2400_SDRAM_BASE,
179
.sram_size = 0x8000,
180
.spis_num = 1,
181
- .spi_bases = aspeed_soc_ast2400_spi_bases,
182
.fmc_typename = "aspeed.smc.fmc",
183
.spi_typename = aspeed_soc_ast2400_typenames,
184
.wdts_num = 2,
185
.irqmap = aspeed_soc_ast2400_irqmap,
186
+ .memmap = aspeed_soc_ast2400_memmap,
187
}, {
188
.name = "ast2400-a1",
189
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
190
.silicon_rev = AST2400_A1_SILICON_REV,
191
- .sdram_base = AST2400_SDRAM_BASE,
192
.sram_size = 0x8000,
193
.spis_num = 1,
194
- .spi_bases = aspeed_soc_ast2400_spi_bases,
195
.fmc_typename = "aspeed.smc.fmc",
196
.spi_typename = aspeed_soc_ast2400_typenames,
197
.wdts_num = 2,
198
.irqmap = aspeed_soc_ast2400_irqmap,
199
+ .memmap = aspeed_soc_ast2400_memmap,
200
}, {
201
.name = "ast2400",
202
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
203
.silicon_rev = AST2400_A0_SILICON_REV,
204
- .sdram_base = AST2400_SDRAM_BASE,
205
.sram_size = 0x8000,
206
.spis_num = 1,
207
- .spi_bases = aspeed_soc_ast2400_spi_bases,
208
.fmc_typename = "aspeed.smc.fmc",
209
.spi_typename = aspeed_soc_ast2400_typenames,
210
.wdts_num = 2,
211
.irqmap = aspeed_soc_ast2400_irqmap,
212
+ .memmap = aspeed_soc_ast2400_memmap,
213
}, {
214
.name = "ast2500-a1",
215
.cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
216
.silicon_rev = AST2500_A1_SILICON_REV,
217
- .sdram_base = AST2500_SDRAM_BASE,
218
.sram_size = 0x9000,
219
.spis_num = 2,
220
- .spi_bases = aspeed_soc_ast2500_spi_bases,
221
.fmc_typename = "aspeed.smc.ast2500-fmc",
222
.spi_typename = aspeed_soc_ast2500_typenames,
223
.wdts_num = 3,
224
.irqmap = aspeed_soc_ast2500_irqmap,
225
+ .memmap = aspeed_soc_ast2500_memmap,
226
},
62
},
227
};
63
};
228
64
229
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
65
+/*
230
Error *err = NULL, *local_err = NULL;
66
+ * CNTVCTSS_EL0 has the same trap conditions as CNTVCT_EL0, so it also
231
67
+ * is exposed to userspace by Linux.
232
/* IO space */
68
+ */
233
- create_unimplemented_device("aspeed_soc.io",
69
+static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = {
234
- ASPEED_SOC_IOMEM_BASE, ASPEED_SOC_IOMEM_SIZE);
70
+ { .name = "CNTVCTSS_EL0", .state = ARM_CP_STATE_AA64,
235
+ create_unimplemented_device("aspeed_soc.io", sc->info->memmap[ASPEED_IOMEM],
71
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 6,
236
+ ASPEED_SOC_IOMEM_SIZE);
72
+ .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
237
73
+ .readfn = gt_virt_cnt_read,
238
/* CPU */
74
+ },
239
object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
75
+};
240
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
76
+
241
error_propagate(errp, err);
77
#endif
242
return;
78
79
static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
80
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
81
if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
82
define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
243
}
83
}
244
- memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE,
84
+ if (cpu_isar_feature(aa64_ecv_traps, cpu)) {
245
- &s->sram);
85
+ define_arm_cp_regs(cpu, gen_timer_ecv_cp_reginfo);
246
+ memory_region_add_subregion(get_system_memory(),
86
+ }
247
+ sc->info->memmap[ASPEED_SRAM], &s->sram);
87
if (arm_feature(env, ARM_FEATURE_VAPA)) {
248
88
ARMCPRegInfo vapa_cp_reginfo[] = {
249
/* SCU */
89
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
250
object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
251
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
252
error_propagate(errp, err);
253
return;
254
}
255
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);
256
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->info->memmap[ASPEED_SCU]);
257
258
/* VIC */
259
object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
260
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
261
error_propagate(errp, err);
262
return;
263
}
264
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE);
265
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->info->memmap[ASPEED_VIC]);
266
sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
267
qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
268
sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
269
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
270
error_propagate(errp, err);
271
return;
272
}
273
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
274
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
275
+ sc->info->memmap[ASPEED_TIMER1]);
276
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
277
qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
278
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
279
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
280
/* UART - attach an 8250 to the IO space as our UART5 */
281
if (serial_hd(0)) {
282
qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
283
- serial_mm_init(get_system_memory(),
284
- ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2,
285
+ serial_mm_init(get_system_memory(), sc->info->memmap[ASPEED_UART5], 2,
286
uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
287
}
288
289
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
290
error_propagate(errp, err);
291
return;
292
}
293
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
294
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->info->memmap[ASPEED_I2C]);
295
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
296
aspeed_soc_get_irq(s, ASPEED_I2C));
297
298
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
299
error_propagate(errp, err);
300
return;
301
}
302
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE);
303
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->info->memmap[ASPEED_FMC]);
304
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
305
s->fmc.ctrl->flash_window_base);
306
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
307
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
308
error_propagate(errp, err);
309
return;
310
}
311
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, sc->info->spi_bases[i]);
312
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
313
+ sc->info->memmap[ASPEED_SPI1 + i]);
314
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
315
s->spi[i].ctrl->flash_window_base);
316
}
317
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
318
error_propagate(errp, err);
319
return;
320
}
321
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
322
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->info->memmap[ASPEED_SDMC]);
323
324
/* Watch dog */
325
for (i = 0; i < sc->info->wdts_num; i++) {
326
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
327
return;
328
}
329
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
330
- ASPEED_SOC_WDT_BASE + i * 0x20);
331
+ sc->info->memmap[ASPEED_WDT] + i * 0x20);
332
}
333
334
/* Net */
335
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
336
error_propagate(errp, err);
337
return;
338
}
339
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, ASPEED_SOC_ETH1_BASE);
340
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0,
341
+ sc->info->memmap[ASPEED_ETH1]);
342
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
343
aspeed_soc_get_irq(s, ASPEED_ETH1));
344
}
345
--
90
--
346
2.20.1
91
2.34.1
347
348
diff view generated by jsdifflib
1
From: Eddie James <eajames@linux.ibm.com>
1
When ID_AA64MMFR0_EL1.ECV is 0b0010, a new register CNTPOFF_EL2 is
2
implemented. This is similar to the existing CNTVOFF_EL2, except
3
that it controls a hypervisor-adjustable offset made to the physical
4
counter and timer.
2
5
3
The XDMA engine embedded in the Aspeed SOCs performs PCI DMA operations
6
Implement the handling for this register, which includes control/trap
4
between the SOC (acting as a BMC) and a host processor in a server.
7
bits in SCR_EL3 and CNTHCTL_EL2.
5
8
6
The XDMA engine exists on the AST2400, AST2500, and AST2600 SOCs, so
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
enable it for all of those. Add trace events on the important register
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
writes in the XDMA engine.
11
Message-id: 20240301183219.2424889-8-peter.maydell@linaro.org
12
---
13
target/arm/cpu-features.h | 5 +++
14
target/arm/cpu.h | 1 +
15
target/arm/helper.c | 68 +++++++++++++++++++++++++++++++++++++--
16
target/arm/trace-events | 1 +
17
4 files changed, 73 insertions(+), 2 deletions(-)
9
18
10
Signed-off-by: Eddie James <eajames@linux.ibm.com>
19
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Signed-off-by: Cédric Le Goater <clg@kaod.org>
13
Message-id: 20190618165311.27066-21-clg@kaod.org
14
[clg: - changed title ]
15
Signed-off-by: Cédric Le Goater <clg@kaod.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
hw/misc/Makefile.objs | 1 +
19
include/hw/arm/aspeed_soc.h | 3 +
20
include/hw/misc/aspeed_xdma.h | 30 +++++++
21
hw/arm/aspeed_soc.c | 17 ++++
22
hw/misc/aspeed_xdma.c | 165 ++++++++++++++++++++++++++++++++++
23
hw/misc/trace-events | 3 +
24
6 files changed, 219 insertions(+)
25
create mode 100644 include/hw/misc/aspeed_xdma.h
26
create mode 100644 hw/misc/aspeed_xdma.c
27
28
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
29
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/misc/Makefile.objs
21
--- a/target/arm/cpu-features.h
31
+++ b/hw/misc/Makefile.objs
22
+++ b/target/arm/cpu-features.h
32
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_ARMSSE_MHU) += armsse-mhu.o
23
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id)
33
24
return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0;
34
obj-$(CONFIG_PVPANIC) += pvpanic.o
35
obj-$(CONFIG_AUX) += auxbus.o
36
+obj-$(CONFIG_ASPEED_SOC) += aspeed_xdma.o
37
obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
38
obj-$(CONFIG_MSF2) += msf2-sysreg.o
39
obj-$(CONFIG_NRF51_SOC) += nrf51_rng.o
40
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
41
index XXXXXXX..XXXXXXX 100644
42
--- a/include/hw/arm/aspeed_soc.h
43
+++ b/include/hw/arm/aspeed_soc.h
44
@@ -XXX,XX +XXX,XX @@
45
#include "hw/intc/aspeed_vic.h"
46
#include "hw/misc/aspeed_scu.h"
47
#include "hw/misc/aspeed_sdmc.h"
48
+#include "hw/misc/aspeed_xdma.h"
49
#include "hw/timer/aspeed_timer.h"
50
#include "hw/timer/aspeed_rtc.h"
51
#include "hw/i2c/aspeed_i2c.h"
52
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
53
AspeedTimerCtrlState timerctrl;
54
AspeedI2CState i2c;
55
AspeedSCUState scu;
56
+ AspeedXDMAState xdma;
57
AspeedSMCState fmc;
58
AspeedSMCState spi[ASPEED_SPIS_NUM];
59
AspeedSDMCState sdmc;
60
@@ -XXX,XX +XXX,XX @@ enum {
61
ASPEED_ETH1,
62
ASPEED_ETH2,
63
ASPEED_SDRAM,
64
+ ASPEED_XDMA,
65
};
66
67
#endif /* ASPEED_SOC_H */
68
diff --git a/include/hw/misc/aspeed_xdma.h b/include/hw/misc/aspeed_xdma.h
69
new file mode 100644
70
index XXXXXXX..XXXXXXX
71
--- /dev/null
72
+++ b/include/hw/misc/aspeed_xdma.h
73
@@ -XXX,XX +XXX,XX @@
74
+/*
75
+ * ASPEED XDMA Controller
76
+ * Eddie James <eajames@linux.ibm.com>
77
+ *
78
+ * Copyright (C) 2019 IBM Corp.
79
+ * SPDX-License-Identifer: GPL-2.0-or-later
80
+ */
81
+
82
+#ifndef ASPEED_XDMA_H
83
+#define ASPEED_XDMA_H
84
+
85
+#include "hw/sysbus.h"
86
+
87
+#define TYPE_ASPEED_XDMA "aspeed.xdma"
88
+#define ASPEED_XDMA(obj) OBJECT_CHECK(AspeedXDMAState, (obj), TYPE_ASPEED_XDMA)
89
+
90
+#define ASPEED_XDMA_NUM_REGS (ASPEED_XDMA_REG_SIZE / sizeof(uint32_t))
91
+#define ASPEED_XDMA_REG_SIZE 0x7C
92
+
93
+typedef struct AspeedXDMAState {
94
+ SysBusDevice parent;
95
+
96
+ MemoryRegion iomem;
97
+ qemu_irq irq;
98
+
99
+ char bmc_cmdq_readp_set;
100
+ uint32_t regs[ASPEED_XDMA_NUM_REGS];
101
+} AspeedXDMAState;
102
+
103
+#endif /* ASPEED_XDMA_H */
104
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/hw/arm/aspeed_soc.c
107
+++ b/hw/arm/aspeed_soc.c
108
@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2400_memmap[] = {
109
[ASPEED_VIC] = 0x1E6C0000,
110
[ASPEED_SDMC] = 0x1E6E0000,
111
[ASPEED_SCU] = 0x1E6E2000,
112
+ [ASPEED_XDMA] = 0x1E6E7000,
113
[ASPEED_ADC] = 0x1E6E9000,
114
[ASPEED_SRAM] = 0x1E720000,
115
[ASPEED_GPIO] = 0x1E780000,
116
@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2500_memmap[] = {
117
[ASPEED_VIC] = 0x1E6C0000,
118
[ASPEED_SDMC] = 0x1E6E0000,
119
[ASPEED_SCU] = 0x1E6E2000,
120
+ [ASPEED_XDMA] = 0x1E6E7000,
121
[ASPEED_ADC] = 0x1E6E9000,
122
[ASPEED_SRAM] = 0x1E720000,
123
[ASPEED_GPIO] = 0x1E780000,
124
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2400_irqmap[] = {
125
[ASPEED_I2C] = 12,
126
[ASPEED_ETH1] = 2,
127
[ASPEED_ETH2] = 3,
128
+ [ASPEED_XDMA] = 6,
129
};
130
131
#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
132
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
133
sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
134
sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
135
}
136
+
137
+ sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
138
+ TYPE_ASPEED_XDMA);
139
}
25
}
140
26
141
static void aspeed_soc_realize(DeviceState *dev, Error **errp)
27
+static inline bool isar_feature_aa64_ecv(const ARMISARegisters *id)
142
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
143
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
144
aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
145
}
146
+
147
+ /* XDMA */
148
+ object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
149
+ if (err) {
150
+ error_propagate(errp, err);
151
+ return;
152
+ }
153
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
154
+ sc->info->memmap[ASPEED_XDMA]);
155
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
156
+ aspeed_soc_get_irq(s, ASPEED_XDMA));
157
}
158
static Property aspeed_soc_properties[] = {
159
DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
160
diff --git a/hw/misc/aspeed_xdma.c b/hw/misc/aspeed_xdma.c
161
new file mode 100644
162
index XXXXXXX..XXXXXXX
163
--- /dev/null
164
+++ b/hw/misc/aspeed_xdma.c
165
@@ -XXX,XX +XXX,XX @@
166
+/*
167
+ * ASPEED XDMA Controller
168
+ * Eddie James <eajames@linux.ibm.com>
169
+ *
170
+ * Copyright (C) 2019 IBM Corp
171
+ * SPDX-License-Identifer: GPL-2.0-or-later
172
+ */
173
+
174
+#include "qemu/osdep.h"
175
+#include "qemu/log.h"
176
+#include "qemu/error-report.h"
177
+#include "hw/misc/aspeed_xdma.h"
178
+#include "qapi/error.h"
179
+
180
+#include "trace.h"
181
+
182
+#define XDMA_BMC_CMDQ_ADDR 0x10
183
+#define XDMA_BMC_CMDQ_ENDP 0x14
184
+#define XDMA_BMC_CMDQ_WRP 0x18
185
+#define XDMA_BMC_CMDQ_W_MASK 0x0003FFFF
186
+#define XDMA_BMC_CMDQ_RDP 0x1C
187
+#define XDMA_BMC_CMDQ_RDP_MAGIC 0xEE882266
188
+#define XDMA_IRQ_ENG_CTRL 0x20
189
+#define XDMA_IRQ_ENG_CTRL_US_COMP BIT(4)
190
+#define XDMA_IRQ_ENG_CTRL_DS_COMP BIT(5)
191
+#define XDMA_IRQ_ENG_CTRL_W_MASK 0xBFEFF07F
192
+#define XDMA_IRQ_ENG_STAT 0x24
193
+#define XDMA_IRQ_ENG_STAT_US_COMP BIT(4)
194
+#define XDMA_IRQ_ENG_STAT_DS_COMP BIT(5)
195
+#define XDMA_IRQ_ENG_STAT_RESET 0xF8000000
196
+#define XDMA_MEM_SIZE 0x1000
197
+
198
+#define TO_REG(addr) ((addr) / sizeof(uint32_t))
199
+
200
+static uint64_t aspeed_xdma_read(void *opaque, hwaddr addr, unsigned int size)
201
+{
28
+{
202
+ uint32_t val = 0;
29
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 1;
203
+ AspeedXDMAState *xdma = opaque;
204
+
205
+ if (addr < ASPEED_XDMA_REG_SIZE) {
206
+ val = xdma->regs[TO_REG(addr)];
207
+ }
208
+
209
+ return (uint64_t)val;
210
+}
30
+}
211
+
31
+
212
+static void aspeed_xdma_write(void *opaque, hwaddr addr, uint64_t val,
32
static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
213
+ unsigned int size)
33
{
34
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
35
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/cpu.h
38
+++ b/target/arm/cpu.h
39
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
40
uint64_t c14_cntkctl; /* Timer Control register */
41
uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */
42
uint64_t cntvoff_el2; /* Counter Virtual Offset register */
43
+ uint64_t cntpoff_el2; /* Counter Physical Offset register */
44
ARMGenericTimer c14_timer[NUM_GTIMERS];
45
uint32_t c15_cpar; /* XScale Coprocessor Access Register */
46
uint32_t c15_ticonfig; /* TI925T configuration byte. */
47
diff --git a/target/arm/helper.c b/target/arm/helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/helper.c
50
+++ b/target/arm/helper.c
51
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
52
if (cpu_isar_feature(aa64_rme, cpu)) {
53
valid_mask |= SCR_NSE | SCR_GPF;
54
}
55
+ if (cpu_isar_feature(aa64_ecv, cpu)) {
56
+ valid_mask |= SCR_ECVEN;
57
+ }
58
} else {
59
valid_mask &= ~(SCR_RW | SCR_ST);
60
if (cpu_isar_feature(aa32_ras, cpu)) {
61
@@ -XXX,XX +XXX,XX @@ void gt_rme_post_el_change(ARMCPU *cpu, void *ignored)
62
gt_update_irq(cpu, GTIMER_PHYS);
63
}
64
65
+static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env)
214
+{
66
+{
215
+ unsigned int idx;
67
+ if ((env->cp15.scr_el3 & SCR_ECVEN) &&
216
+ uint32_t val32 = (uint32_t)val;
68
+ FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) &&
217
+ AspeedXDMAState *xdma = opaque;
69
+ arm_is_el2_enabled(env) &&
218
+
70
+ (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
219
+ if (addr >= ASPEED_XDMA_REG_SIZE) {
71
+ return env->cp15.cntpoff_el2;
220
+ return;
221
+ }
72
+ }
222
+
73
+ return 0;
223
+ switch (addr) {
224
+ case XDMA_BMC_CMDQ_ENDP:
225
+ xdma->regs[TO_REG(addr)] = val32 & XDMA_BMC_CMDQ_W_MASK;
226
+ break;
227
+ case XDMA_BMC_CMDQ_WRP:
228
+ idx = TO_REG(addr);
229
+ xdma->regs[idx] = val32 & XDMA_BMC_CMDQ_W_MASK;
230
+ xdma->regs[TO_REG(XDMA_BMC_CMDQ_RDP)] = xdma->regs[idx];
231
+
232
+ trace_aspeed_xdma_write(addr, val);
233
+
234
+ if (xdma->bmc_cmdq_readp_set) {
235
+ xdma->bmc_cmdq_readp_set = 0;
236
+ } else {
237
+ xdma->regs[TO_REG(XDMA_IRQ_ENG_STAT)] |=
238
+ XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP;
239
+
240
+ if (xdma->regs[TO_REG(XDMA_IRQ_ENG_CTRL)] &
241
+ (XDMA_IRQ_ENG_CTRL_US_COMP | XDMA_IRQ_ENG_CTRL_DS_COMP))
242
+ qemu_irq_raise(xdma->irq);
243
+ }
244
+ break;
245
+ case XDMA_BMC_CMDQ_RDP:
246
+ trace_aspeed_xdma_write(addr, val);
247
+
248
+ if (val32 == XDMA_BMC_CMDQ_RDP_MAGIC) {
249
+ xdma->bmc_cmdq_readp_set = 1;
250
+ }
251
+ break;
252
+ case XDMA_IRQ_ENG_CTRL:
253
+ xdma->regs[TO_REG(addr)] = val32 & XDMA_IRQ_ENG_CTRL_W_MASK;
254
+ break;
255
+ case XDMA_IRQ_ENG_STAT:
256
+ trace_aspeed_xdma_write(addr, val);
257
+
258
+ idx = TO_REG(addr);
259
+ if (val32 & (XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP)) {
260
+ xdma->regs[idx] &=
261
+ ~(XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP);
262
+ qemu_irq_lower(xdma->irq);
263
+ }
264
+ break;
265
+ default:
266
+ xdma->regs[TO_REG(addr)] = val32;
267
+ break;
268
+ }
269
+}
74
+}
270
+
75
+
271
+static const MemoryRegionOps aspeed_xdma_ops = {
76
+static uint64_t gt_phys_cnt_offset(CPUARMState *env)
272
+ .read = aspeed_xdma_read,
273
+ .write = aspeed_xdma_write,
274
+ .endianness = DEVICE_NATIVE_ENDIAN,
275
+ .valid.min_access_size = 4,
276
+ .valid.max_access_size = 4,
277
+};
278
+
279
+static void aspeed_xdma_realize(DeviceState *dev, Error **errp)
280
+{
77
+{
281
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
78
+ if (arm_current_el(env) >= 2) {
282
+ AspeedXDMAState *xdma = ASPEED_XDMA(dev);
79
+ return 0;
283
+
80
+ }
284
+ sysbus_init_irq(sbd, &xdma->irq);
81
+ return gt_phys_raw_cnt_offset(env);
285
+ memory_region_init_io(&xdma->iomem, OBJECT(xdma), &aspeed_xdma_ops, xdma,
286
+ TYPE_ASPEED_XDMA, XDMA_MEM_SIZE);
287
+ sysbus_init_mmio(sbd, &xdma->iomem);
288
+}
82
+}
289
+
83
+
290
+static void aspeed_xdma_reset(DeviceState *dev)
84
static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
85
{
86
ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
87
@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
88
* reset timer to when ISTATUS next has to change
89
*/
90
uint64_t offset = timeridx == GTIMER_VIRT ?
91
- cpu->env.cp15.cntvoff_el2 : 0;
92
+ cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env);
93
uint64_t count = gt_get_countervalue(&cpu->env);
94
/* Note that this must be unsigned 64 bit arithmetic: */
95
int istatus = count - offset >= gt->cval;
96
@@ -XXX,XX +XXX,XX @@ static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
97
98
static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
99
{
100
- return gt_get_countervalue(env);
101
+ return gt_get_countervalue(env) - gt_phys_cnt_offset(env);
102
}
103
104
static uint64_t gt_virt_cnt_offset(CPUARMState *env)
105
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
106
case GTIMER_HYPVIRT:
107
offset = gt_virt_cnt_offset(env);
108
break;
109
+ case GTIMER_PHYS:
110
+ offset = gt_phys_cnt_offset(env);
111
+ break;
112
}
113
114
return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
115
@@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
116
case GTIMER_HYPVIRT:
117
offset = gt_virt_cnt_offset(env);
118
break;
119
+ case GTIMER_PHYS:
120
+ offset = gt_phys_cnt_offset(env);
121
+ break;
122
}
123
124
trace_arm_gt_tval_write(timeridx, value);
125
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
126
R_CNTHCTL_EL1NVVCT_MASK |
127
R_CNTHCTL_EVNTIS_MASK;
128
}
129
+ if (cpu_isar_feature(aa64_ecv, cpu)) {
130
+ valid_mask |= R_CNTHCTL_ECV_MASK;
131
+ }
132
133
/* Clear RES0 bits */
134
value &= valid_mask;
135
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = {
136
},
137
};
138
139
+static CPAccessResult gt_cntpoff_access(CPUARMState *env,
140
+ const ARMCPRegInfo *ri,
141
+ bool isread)
291
+{
142
+{
292
+ AspeedXDMAState *xdma = ASPEED_XDMA(dev);
143
+ if (arm_current_el(env) == 2 && !(env->cp15.scr_el3 & SCR_ECVEN)) {
293
+
144
+ return CP_ACCESS_TRAP_EL3;
294
+ xdma->bmc_cmdq_readp_set = 0;
145
+ }
295
+ memset(xdma->regs, 0, ASPEED_XDMA_REG_SIZE);
146
+ return CP_ACCESS_OK;
296
+ xdma->regs[TO_REG(XDMA_IRQ_ENG_STAT)] = XDMA_IRQ_ENG_STAT_RESET;
297
+
298
+ qemu_irq_lower(xdma->irq);
299
+}
147
+}
300
+
148
+
301
+static const VMStateDescription aspeed_xdma_vmstate = {
149
+static void gt_cntpoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
302
+ .name = TYPE_ASPEED_XDMA,
150
+ uint64_t value)
303
+ .version_id = 1,
151
+{
304
+ .fields = (VMStateField[]) {
152
+ ARMCPU *cpu = env_archcpu(env);
305
+ VMSTATE_UINT32_ARRAY(regs, AspeedXDMAState, ASPEED_XDMA_NUM_REGS),
306
+ VMSTATE_END_OF_LIST(),
307
+ },
308
+};
309
+
153
+
310
+static void aspeed_xdma_class_init(ObjectClass *classp, void *data)
154
+ trace_arm_gt_cntpoff_write(value);
311
+{
155
+ raw_write(env, ri, value);
312
+ DeviceClass *dc = DEVICE_CLASS(classp);
156
+ gt_recalc_timer(cpu, GTIMER_PHYS);
313
+
314
+ dc->realize = aspeed_xdma_realize;
315
+ dc->reset = aspeed_xdma_reset;
316
+ dc->vmsd = &aspeed_xdma_vmstate;
317
+}
157
+}
318
+
158
+
319
+static const TypeInfo aspeed_xdma_info = {
159
+static const ARMCPRegInfo gen_timer_cntpoff_reginfo = {
320
+ .name = TYPE_ASPEED_XDMA,
160
+ .name = "CNTPOFF_EL2", .state = ARM_CP_STATE_AA64,
321
+ .parent = TYPE_SYS_BUS_DEVICE,
161
+ .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 6,
322
+ .instance_size = sizeof(AspeedXDMAState),
162
+ .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
323
+ .class_init = aspeed_xdma_class_init,
163
+ .accessfn = gt_cntpoff_access, .writefn = gt_cntpoff_write,
164
+ .nv2_redirect_offset = 0x1a8,
165
+ .fieldoffset = offsetof(CPUARMState, cp15.cntpoff_el2),
324
+};
166
+};
325
+
167
#else
326
+static void aspeed_xdma_register_type(void)
168
327
+{
169
/*
328
+ type_register_static(&aspeed_xdma_info);
170
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
329
+}
171
if (cpu_isar_feature(aa64_ecv_traps, cpu)) {
330
+type_init(aspeed_xdma_register_type);
172
define_arm_cp_regs(cpu, gen_timer_ecv_cp_reginfo);
331
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
173
}
174
+#ifndef CONFIG_USER_ONLY
175
+ if (cpu_isar_feature(aa64_ecv, cpu)) {
176
+ define_one_arm_cp_reg(cpu, &gen_timer_cntpoff_reginfo);
177
+ }
178
+#endif
179
if (arm_feature(env, ARM_FEATURE_VAPA)) {
180
ARMCPRegInfo vapa_cp_reginfo[] = {
181
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
182
diff --git a/target/arm/trace-events b/target/arm/trace-events
332
index XXXXXXX..XXXXXXX 100644
183
index XXXXXXX..XXXXXXX 100644
333
--- a/hw/misc/trace-events
184
--- a/target/arm/trace-events
334
+++ b/hw/misc/trace-events
185
+++ b/target/arm/trace-events
335
@@ -XXX,XX +XXX,XX @@ armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_I
186
@@ -XXX,XX +XXX,XX @@ arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write: timer %d value 0x%"
336
# armsse-mhu.c
187
arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value 0x%" PRIx64
337
armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
188
arm_gt_imask_toggle(int timer) "gt_ctl_write: timer %d IMASK toggle"
338
armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
189
arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value 0x%" PRIx64
339
+
190
+arm_gt_cntpoff_write(uint64_t value) "gt_cntpoff_write: value 0x%" PRIx64
340
+# aspeed_xdma.c
191
arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d"
341
+aspeed_xdma_write(uint64_t offset, uint64_t data) "XDMA write: offset 0x%" PRIx64 " data 0x%" PRIx64
192
193
# kvm.c
342
--
194
--
343
2.20.1
195
2.34.1
344
345
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Enable all FEAT_ECV features on the 'max' CPU.
2
2
3
Under KVM, the kernel gets the HVC call and handle the PSCI requests.
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20240301183219.2424889-9-peter.maydell@linaro.org
7
---
8
docs/system/arm/emulation.rst | 1 +
9
target/arm/tcg/cpu64.c | 1 +
10
2 files changed, 2 insertions(+)
4
11
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
6
Message-id: 20190701132516.26392-20-philmd@redhat.com
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/internals.h | 6 +++++-
11
1 file changed, 5 insertions(+), 1 deletion(-)
12
13
diff --git a/target/arm/internals.h b/target/arm/internals.h
14
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/internals.h
14
--- a/docs/system/arm/emulation.rst
16
+++ b/target/arm/internals.h
15
+++ b/docs/system/arm/emulation.rst
17
@@ -XXX,XX +XXX,XX @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
16
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
18
/* Callback function for when a watchpoint or breakpoint triggers. */
17
- FEAT_DotProd (Advanced SIMD dot product instructions)
19
void arm_debug_excp_handler(CPUState *cs);
18
- FEAT_DoubleFault (Double Fault Extension)
20
19
- FEAT_E0PD (Preventing EL0 access to halves of address maps)
21
-#ifdef CONFIG_USER_ONLY
20
+- FEAT_ECV (Enhanced Counter Virtualization)
22
+#if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG)
21
- FEAT_EPAC (Enhanced pointer authentication)
23
static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
22
- FEAT_ETS (Enhanced Translation Synchronization)
24
{
23
- FEAT_EVT (Enhanced Virtualization Traps)
25
return false;
24
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
26
}
25
index XXXXXXX..XXXXXXX 100644
27
+static inline void arm_handle_psci_call(ARMCPU *cpu)
26
--- a/target/arm/tcg/cpu64.c
28
+{
27
+++ b/target/arm/tcg/cpu64.c
29
+ g_assert_not_reached();
28
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
30
+}
29
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
31
#else
30
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
32
/* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
31
t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */
33
bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
32
+ t = FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */
33
cpu->isar.id_aa64mmfr0 = t;
34
35
t = cpu->isar.id_aa64mmfr1;
34
--
36
--
35
2.20.1
37
2.34.1
36
38
37
39
diff view generated by jsdifflib
1
From: Joel Stanley <joel@jms.id.au>
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
The RTC is modeled to provide time and date functionality. It is
3
Features supported :
4
initialised at zero to match the hardware.
4
- the 8 STM32L4x5 GPIOs are initialized with their reset values
5
(except IDR, see below)
6
- input mode : setting a pin in input mode "externally" (using input
7
irqs) results in an out irq (transmitted to SYSCFG)
8
- output mode : setting a bit in ODR sets the corresponding out irq
9
(if this line is configured in output mode)
10
- pull-up, pull-down
11
- push-pull, open-drain
5
12
6
There is no modelling of the alarm functionality, which includes the IRQ
13
Difference with the real GPIOs :
7
line. As there is no guest code to exercise this function that is
14
- Alternate Function and Analog mode aren't implemented :
8
acceptable for now.
15
pins in AF/Analog behave like pins in input mode
16
- floating pins stay at their last value
17
- register IDR reset values differ from the real one :
18
values are coherent with the other registers reset values
19
and the fact that AF/Analog modes aren't implemented
20
- setting I/O output speed isn't supported
21
- locking port bits isn't supported
22
- ADC function isn't supported
23
- GPIOH has 16 pins instead of 2 pins
24
- writing to registers LCKR, AFRL, AFRH and ASCR is ineffective
9
25
10
Signed-off-by: Joel Stanley <joel@jms.id.au>
26
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
12
Message-id: 20190618165311.27066-4-clg@kaod.org
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
29
Acked-by: Alistair Francis <alistair.francis@wdc.com>
30
Message-id: 20240305210444.310665-2-ines.varhol@telecom-paris.fr
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
32
---
15
hw/timer/Makefile.objs | 2 +-
33
MAINTAINERS | 1 +
16
include/hw/timer/aspeed_rtc.h | 31 ++++++
34
docs/system/arm/b-l475e-iot01a.rst | 2 +-
17
hw/timer/aspeed_rtc.c | 180 ++++++++++++++++++++++++++++++++++
35
include/hw/gpio/stm32l4x5_gpio.h | 70 +++++
18
hw/timer/trace-events | 4 +
36
hw/gpio/stm32l4x5_gpio.c | 477 +++++++++++++++++++++++++++++
19
4 files changed, 216 insertions(+), 1 deletion(-)
37
hw/gpio/Kconfig | 3 +
20
create mode 100644 include/hw/timer/aspeed_rtc.h
38
hw/gpio/meson.build | 1 +
21
create mode 100644 hw/timer/aspeed_rtc.c
39
hw/gpio/trace-events | 6 +
40
7 files changed, 559 insertions(+), 1 deletion(-)
41
create mode 100644 include/hw/gpio/stm32l4x5_gpio.h
42
create mode 100644 hw/gpio/stm32l4x5_gpio.c
22
43
23
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
44
diff --git a/MAINTAINERS b/MAINTAINERS
24
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/timer/Makefile.objs
46
--- a/MAINTAINERS
26
+++ b/hw/timer/Makefile.objs
47
+++ b/MAINTAINERS
27
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
48
@@ -XXX,XX +XXX,XX @@ F: hw/arm/stm32l4x5_soc.c
28
obj-$(CONFIG_ALLWINNER_A10_PIT) += allwinner-a10-pit.o
49
F: hw/misc/stm32l4x5_exti.c
29
50
F: hw/misc/stm32l4x5_syscfg.c
30
common-obj-$(CONFIG_STM32F2XX_TIMER) += stm32f2xx_timer.o
51
F: hw/misc/stm32l4x5_rcc.c
31
-common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
52
+F: hw/gpio/stm32l4x5_gpio.c
32
+common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o aspeed_rtc.o
53
F: include/hw/*/stm32l4x5_*.h
33
54
34
common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
55
B-L475E-IOT01A IoT Node
35
common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o
56
diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst
36
diff --git a/include/hw/timer/aspeed_rtc.h b/include/hw/timer/aspeed_rtc.h
57
index XXXXXXX..XXXXXXX 100644
58
--- a/docs/system/arm/b-l475e-iot01a.rst
59
+++ b/docs/system/arm/b-l475e-iot01a.rst
60
@@ -XXX,XX +XXX,XX @@ Currently B-L475E-IOT01A machine's only supports the following devices:
61
- STM32L4x5 EXTI (Extended interrupts and events controller)
62
- STM32L4x5 SYSCFG (System configuration controller)
63
- STM32L4x5 RCC (Reset and clock control)
64
+- STM32L4x5 GPIOs (General-purpose I/Os)
65
66
Missing devices
67
"""""""""""""""
68
@@ -XXX,XX +XXX,XX @@ Missing devices
69
The B-L475E-IOT01A does *not* support the following devices:
70
71
- Serial ports (UART)
72
-- General-purpose I/Os (GPIO)
73
- Analog to Digital Converter (ADC)
74
- SPI controller
75
- Timer controller (TIMER)
76
diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_gpio.h
37
new file mode 100644
77
new file mode 100644
38
index XXXXXXX..XXXXXXX
78
index XXXXXXX..XXXXXXX
39
--- /dev/null
79
--- /dev/null
40
+++ b/include/hw/timer/aspeed_rtc.h
80
+++ b/include/hw/gpio/stm32l4x5_gpio.h
41
@@ -XXX,XX +XXX,XX @@
81
@@ -XXX,XX +XXX,XX @@
42
+/*
82
+/*
43
+ * ASPEED Real Time Clock
83
+ * STM32L4x5 GPIO (General Purpose Input/Ouput)
44
+ * Joel Stanley <joel@jms.id.au>
45
+ *
84
+ *
46
+ * Copyright 2019 IBM Corp
85
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
86
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
87
+ *
47
+ * SPDX-License-Identifier: GPL-2.0-or-later
88
+ * SPDX-License-Identifier: GPL-2.0-or-later
89
+ *
90
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
91
+ * See the COPYING file in the top-level directory.
48
+ */
92
+ */
49
+#ifndef ASPEED_RTC_H
93
+
50
+#define ASPEED_RTC_H
94
+/*
51
+
95
+ * The reference used is the STMicroElectronics RM0351 Reference manual
52
+#include <stdint.h>
96
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
53
+
97
+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
54
+#include "hw/hw.h"
98
+ */
55
+#include "hw/irq.h"
99
+
100
+#ifndef HW_STM32L4X5_GPIO_H
101
+#define HW_STM32L4X5_GPIO_H
102
+
56
+#include "hw/sysbus.h"
103
+#include "hw/sysbus.h"
57
+
104
+#include "qom/object.h"
58
+typedef struct AspeedRtcState {
105
+
106
+#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"
107
+OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO)
108
+
109
+#define GPIO_NUM_PINS 16
110
+
111
+struct Stm32l4x5GpioState {
59
+ SysBusDevice parent_obj;
112
+ SysBusDevice parent_obj;
60
+
113
+
61
+ MemoryRegion iomem;
114
+ MemoryRegion mmio;
62
+ qemu_irq irq;
115
+
63
+
116
+ /* GPIO registers */
64
+ uint32_t reg[0x18];
117
+ uint32_t moder;
65
+ int offset;
118
+ uint32_t otyper;
66
+
119
+ uint32_t ospeedr;
67
+} AspeedRtcState;
120
+ uint32_t pupdr;
68
+
121
+ uint32_t idr;
69
+#define TYPE_ASPEED_RTC "aspeed.rtc"
122
+ uint32_t odr;
70
+#define ASPEED_RTC(obj) OBJECT_CHECK(AspeedRtcState, (obj), TYPE_ASPEED_RTC)
123
+ uint32_t lckr;
71
+
124
+ uint32_t afrl;
72
+#endif /* ASPEED_RTC_H */
125
+ uint32_t afrh;
73
diff --git a/hw/timer/aspeed_rtc.c b/hw/timer/aspeed_rtc.c
126
+ uint32_t ascr;
127
+
128
+ /* GPIO registers reset values */
129
+ uint32_t moder_reset;
130
+ uint32_t ospeedr_reset;
131
+ uint32_t pupdr_reset;
132
+
133
+ /*
134
+ * External driving of pins.
135
+ * The pins can be set externally through the device
136
+ * anonymous input GPIOs lines under certain conditions.
137
+ * The pin must not be in push-pull output mode,
138
+ * and can't be set high in open-drain mode.
139
+ * Pins driven externally and configured to
140
+ * output mode will in general be "disconnected"
141
+ * (see `get_gpio_pinmask_to_disconnect()`)
142
+ */
143
+ uint16_t disconnected_pins;
144
+ uint16_t pins_connected_high;
145
+
146
+ char *name;
147
+ Clock *clk;
148
+ qemu_irq pin[GPIO_NUM_PINS];
149
+};
150
+
151
+#endif
152
diff --git a/hw/gpio/stm32l4x5_gpio.c b/hw/gpio/stm32l4x5_gpio.c
74
new file mode 100644
153
new file mode 100644
75
index XXXXXXX..XXXXXXX
154
index XXXXXXX..XXXXXXX
76
--- /dev/null
155
--- /dev/null
77
+++ b/hw/timer/aspeed_rtc.c
156
+++ b/hw/gpio/stm32l4x5_gpio.c
78
@@ -XXX,XX +XXX,XX @@
157
@@ -XXX,XX +XXX,XX @@
79
+/*
158
+/*
80
+ * ASPEED Real Time Clock
159
+ * STM32L4x5 GPIO (General Purpose Input/Ouput)
81
+ * Joel Stanley <joel@jms.id.au>
82
+ *
160
+ *
83
+ * Copyright 2019 IBM Corp
161
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
162
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
163
+ *
84
+ * SPDX-License-Identifier: GPL-2.0-or-later
164
+ * SPDX-License-Identifier: GPL-2.0-or-later
165
+ *
166
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
167
+ * See the COPYING file in the top-level directory.
85
+ */
168
+ */
86
+
169
+
170
+/*
171
+ * The reference used is the STMicroElectronics RM0351 Reference manual
172
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
173
+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
174
+ */
175
+
87
+#include "qemu/osdep.h"
176
+#include "qemu/osdep.h"
88
+#include "qemu-common.h"
89
+#include "hw/timer/aspeed_rtc.h"
90
+#include "qemu/log.h"
177
+#include "qemu/log.h"
91
+#include "qemu/timer.h"
178
+#include "hw/gpio/stm32l4x5_gpio.h"
92
+
179
+#include "hw/irq.h"
180
+#include "hw/qdev-clock.h"
181
+#include "hw/qdev-properties.h"
182
+#include "qapi/visitor.h"
183
+#include "qapi/error.h"
184
+#include "migration/vmstate.h"
93
+#include "trace.h"
185
+#include "trace.h"
94
+
186
+
95
+#define COUNTER1 (0x00 / 4)
187
+#define GPIO_MODER 0x00
96
+#define COUNTER2 (0x04 / 4)
188
+#define GPIO_OTYPER 0x04
97
+#define ALARM (0x08 / 4)
189
+#define GPIO_OSPEEDR 0x08
98
+#define CONTROL (0x10 / 4)
190
+#define GPIO_PUPDR 0x0C
99
+#define ALARM_STATUS (0x14 / 4)
191
+#define GPIO_IDR 0x10
100
+
192
+#define GPIO_ODR 0x14
101
+#define RTC_UNLOCKED BIT(1)
193
+#define GPIO_BSRR 0x18
102
+#define RTC_ENABLED BIT(0)
194
+#define GPIO_LCKR 0x1C
103
+
195
+#define GPIO_AFRL 0x20
104
+static void aspeed_rtc_calc_offset(AspeedRtcState *rtc)
196
+#define GPIO_AFRH 0x24
105
+{
197
+#define GPIO_BRR 0x28
106
+ struct tm tm;
198
+#define GPIO_ASCR 0x2C
107
+ uint32_t year, cent;
199
+
108
+ uint32_t reg1 = rtc->reg[COUNTER1];
200
+/* 0b11111111_11111111_00000000_00000000 */
109
+ uint32_t reg2 = rtc->reg[COUNTER2];
201
+#define RESERVED_BITS_MASK 0xFFFF0000
110
+
202
+
111
+ tm.tm_mday = (reg1 >> 24) & 0x1f;
203
+static void update_gpio_idr(Stm32l4x5GpioState *s);
112
+ tm.tm_hour = (reg1 >> 16) & 0x1f;
204
+
113
+ tm.tm_min = (reg1 >> 8) & 0x3f;
205
+static bool is_pull_up(Stm32l4x5GpioState *s, unsigned pin)
114
+ tm.tm_sec = (reg1 >> 0) & 0x3f;
206
+{
115
+
207
+ return extract32(s->pupdr, 2 * pin, 2) == 1;
116
+ cent = (reg2 >> 16) & 0x1f;
208
+}
117
+ year = (reg2 >> 8) & 0x7f;
209
+
118
+ tm.tm_mon = ((reg2 >> 0) & 0x0f) - 1;
210
+static bool is_pull_down(Stm32l4x5GpioState *s, unsigned pin)
119
+ tm.tm_year = year + (cent * 100) - 1900;
211
+{
120
+
212
+ return extract32(s->pupdr, 2 * pin, 2) == 2;
121
+ rtc->offset = qemu_timedate_diff(&tm);
213
+}
122
+}
214
+
123
+
215
+static bool is_output(Stm32l4x5GpioState *s, unsigned pin)
124
+static uint32_t aspeed_rtc_get_counter(AspeedRtcState *rtc, int r)
216
+{
125
+{
217
+ return extract32(s->moder, 2 * pin, 2) == 1;
126
+ uint32_t year, cent;
218
+}
127
+ struct tm now;
219
+
128
+
220
+static bool is_open_drain(Stm32l4x5GpioState *s, unsigned pin)
129
+ qemu_get_timedate(&now, rtc->offset);
221
+{
130
+
222
+ return extract32(s->otyper, pin, 1) == 1;
131
+ switch (r) {
223
+}
132
+ case COUNTER1:
224
+
133
+ return (now.tm_mday << 24) | (now.tm_hour << 16) |
225
+static bool is_push_pull(Stm32l4x5GpioState *s, unsigned pin)
134
+ (now.tm_min << 8) | now.tm_sec;
226
+{
135
+ case COUNTER2:
227
+ return extract32(s->otyper, pin, 1) == 0;
136
+ cent = (now.tm_year + 1900) / 100;
228
+}
137
+ year = now.tm_year % 100;
229
+
138
+ return ((cent & 0x1f) << 16) | ((year & 0x7f) << 8) |
230
+static void stm32l4x5_gpio_reset_hold(Object *obj)
139
+ ((now.tm_mon + 1) & 0xf);
231
+{
232
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
233
+
234
+ s->moder = s->moder_reset;
235
+ s->otyper = 0x00000000;
236
+ s->ospeedr = s->ospeedr_reset;
237
+ s->pupdr = s->pupdr_reset;
238
+ s->idr = 0x00000000;
239
+ s->odr = 0x00000000;
240
+ s->lckr = 0x00000000;
241
+ s->afrl = 0x00000000;
242
+ s->afrh = 0x00000000;
243
+ s->ascr = 0x00000000;
244
+
245
+ s->disconnected_pins = 0xFFFF;
246
+ s->pins_connected_high = 0x0000;
247
+ update_gpio_idr(s);
248
+}
249
+
250
+static void stm32l4x5_gpio_set(void *opaque, int line, int level)
251
+{
252
+ Stm32l4x5GpioState *s = opaque;
253
+ /*
254
+ * The pin isn't set if line is configured in output mode
255
+ * except if level is 0 and the output is open-drain.
256
+ * This way there will be no short-circuit prone situations.
257
+ */
258
+ if (is_output(s, line) && !(is_open_drain(s, line) && (level == 0))) {
259
+ qemu_log_mask(LOG_GUEST_ERROR, "Line %d can't be driven externally\n",
260
+ line);
261
+ return;
262
+ }
263
+
264
+ s->disconnected_pins &= ~(1 << line);
265
+ if (level) {
266
+ s->pins_connected_high |= (1 << line);
267
+ } else {
268
+ s->pins_connected_high &= ~(1 << line);
269
+ }
270
+ trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins,
271
+ s->pins_connected_high);
272
+ update_gpio_idr(s);
273
+}
274
+
275
+
276
+static void update_gpio_idr(Stm32l4x5GpioState *s)
277
+{
278
+ uint32_t new_idr_mask = 0;
279
+ uint32_t new_idr = s->odr;
280
+ uint32_t old_idr = s->idr;
281
+ int new_pin_state, old_pin_state;
282
+
283
+ for (int i = 0; i < GPIO_NUM_PINS; i++) {
284
+ if (is_output(s, i)) {
285
+ if (is_push_pull(s, i)) {
286
+ new_idr_mask |= (1 << i);
287
+ } else if (!(s->odr & (1 << i))) {
288
+ /* open-drain ODR 0 */
289
+ new_idr_mask |= (1 << i);
290
+ /* open-drain ODR 1 */
291
+ } else if (!(s->disconnected_pins & (1 << i)) &&
292
+ !(s->pins_connected_high & (1 << i))) {
293
+ /* open-drain ODR 1 with pin connected low */
294
+ new_idr_mask |= (1 << i);
295
+ new_idr &= ~(1 << i);
296
+ /* open-drain ODR 1 with unactive pin */
297
+ } else if (is_pull_up(s, i)) {
298
+ new_idr_mask |= (1 << i);
299
+ } else if (is_pull_down(s, i)) {
300
+ new_idr_mask |= (1 << i);
301
+ new_idr &= ~(1 << i);
302
+ }
303
+ /*
304
+ * The only case left is for open-drain ODR 1
305
+ * with unactive pin without pull-up or pull-down :
306
+ * the value is floating.
307
+ */
308
+ /* input or analog mode with connected pin */
309
+ } else if (!(s->disconnected_pins & (1 << i))) {
310
+ if (s->pins_connected_high & (1 << i)) {
311
+ /* pin high */
312
+ new_idr_mask |= (1 << i);
313
+ new_idr |= (1 << i);
314
+ } else {
315
+ /* pin low */
316
+ new_idr_mask |= (1 << i);
317
+ new_idr &= ~(1 << i);
318
+ }
319
+ /* input or analog mode with disconnected pin */
320
+ } else {
321
+ if (is_pull_up(s, i)) {
322
+ /* pull-up */
323
+ new_idr_mask |= (1 << i);
324
+ new_idr |= (1 << i);
325
+ } else if (is_pull_down(s, i)) {
326
+ /* pull-down */
327
+ new_idr_mask |= (1 << i);
328
+ new_idr &= ~(1 << i);
329
+ }
330
+ /*
331
+ * The only case left is for a disconnected pin
332
+ * without pull-up or pull-down :
333
+ * the value is floating.
334
+ */
335
+ }
336
+ }
337
+
338
+ s->idr = (old_idr & ~new_idr_mask) | (new_idr & new_idr_mask);
339
+ trace_stm32l4x5_gpio_update_idr(s->name, old_idr, s->idr);
340
+
341
+ for (int i = 0; i < GPIO_NUM_PINS; i++) {
342
+ if (new_idr_mask & (1 << i)) {
343
+ new_pin_state = (new_idr & (1 << i)) > 0;
344
+ old_pin_state = (old_idr & (1 << i)) > 0;
345
+ if (new_pin_state > old_pin_state) {
346
+ qemu_irq_raise(s->pin[i]);
347
+ } else if (new_pin_state < old_pin_state) {
348
+ qemu_irq_lower(s->pin[i]);
349
+ }
350
+ }
351
+ }
352
+}
353
+
354
+/*
355
+ * Return mask of pins that are both configured in output
356
+ * mode and externally driven (except pins in open-drain
357
+ * mode externally set to 0).
358
+ */
359
+static uint32_t get_gpio_pinmask_to_disconnect(Stm32l4x5GpioState *s)
360
+{
361
+ uint32_t pins_to_disconnect = 0;
362
+ for (int i = 0; i < GPIO_NUM_PINS; i++) {
363
+ /* for each connected pin in output mode */
364
+ if (!(s->disconnected_pins & (1 << i)) && is_output(s, i)) {
365
+ /* if either push-pull or high level */
366
+ if (is_push_pull(s, i) || s->pins_connected_high & (1 << i)) {
367
+ pins_to_disconnect |= (1 << i);
368
+ qemu_log_mask(LOG_GUEST_ERROR,
369
+ "Line %d can't be driven externally\n",
370
+ i);
371
+ }
372
+ }
373
+ }
374
+ return pins_to_disconnect;
375
+}
376
+
377
+/*
378
+ * Set field `disconnected_pins` and call `update_gpio_idr()`
379
+ */
380
+static void disconnect_gpio_pins(Stm32l4x5GpioState *s, uint16_t lines)
381
+{
382
+ s->disconnected_pins |= lines;
383
+ trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins,
384
+ s->pins_connected_high);
385
+ update_gpio_idr(s);
386
+}
387
+
388
+static void disconnected_pins_set(Object *obj, Visitor *v,
389
+ const char *name, void *opaque, Error **errp)
390
+{
391
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
392
+ uint16_t value;
393
+ if (!visit_type_uint16(v, name, &value, errp)) {
394
+ return;
395
+ }
396
+ disconnect_gpio_pins(s, value);
397
+}
398
+
399
+static void disconnected_pins_get(Object *obj, Visitor *v,
400
+ const char *name, void *opaque, Error **errp)
401
+{
402
+ visit_type_uint16(v, name, (uint16_t *)opaque, errp);
403
+}
404
+
405
+static void clock_freq_get(Object *obj, Visitor *v,
406
+ const char *name, void *opaque, Error **errp)
407
+{
408
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
409
+ uint32_t clock_freq_hz = clock_get_hz(s->clk);
410
+ visit_type_uint32(v, name, &clock_freq_hz, errp);
411
+}
412
+
413
+static void stm32l4x5_gpio_write(void *opaque, hwaddr addr,
414
+ uint64_t val64, unsigned int size)
415
+{
416
+ Stm32l4x5GpioState *s = opaque;
417
+
418
+ uint32_t value = val64;
419
+ trace_stm32l4x5_gpio_write(s->name, addr, val64);
420
+
421
+ switch (addr) {
422
+ case GPIO_MODER:
423
+ s->moder = value;
424
+ disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s));
425
+ qemu_log_mask(LOG_UNIMP,
426
+ "%s: Analog and AF modes aren't supported\n\
427
+ Analog and AF mode behave like input mode\n",
428
+ __func__);
429
+ return;
430
+ case GPIO_OTYPER:
431
+ s->otyper = value & ~RESERVED_BITS_MASK;
432
+ disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s));
433
+ return;
434
+ case GPIO_OSPEEDR:
435
+ qemu_log_mask(LOG_UNIMP,
436
+ "%s: Changing I/O output speed isn't supported\n\
437
+ I/O speed is already maximal\n",
438
+ __func__);
439
+ s->ospeedr = value;
440
+ return;
441
+ case GPIO_PUPDR:
442
+ s->pupdr = value;
443
+ update_gpio_idr(s);
444
+ return;
445
+ case GPIO_IDR:
446
+ qemu_log_mask(LOG_UNIMP,
447
+ "%s: GPIO->IDR is read-only\n",
448
+ __func__);
449
+ return;
450
+ case GPIO_ODR:
451
+ s->odr = value & ~RESERVED_BITS_MASK;
452
+ update_gpio_idr(s);
453
+ return;
454
+ case GPIO_BSRR: {
455
+ uint32_t bits_to_reset = (value & RESERVED_BITS_MASK) >> GPIO_NUM_PINS;
456
+ uint32_t bits_to_set = value & ~RESERVED_BITS_MASK;
457
+ /* If both BSx and BRx are set, BSx has priority.*/
458
+ s->odr &= ~bits_to_reset;
459
+ s->odr |= bits_to_set;
460
+ update_gpio_idr(s);
461
+ return;
462
+ }
463
+ case GPIO_LCKR:
464
+ qemu_log_mask(LOG_UNIMP,
465
+ "%s: Locking port bits configuration isn't supported\n",
466
+ __func__);
467
+ s->lckr = value & ~RESERVED_BITS_MASK;
468
+ return;
469
+ case GPIO_AFRL:
470
+ qemu_log_mask(LOG_UNIMP,
471
+ "%s: Alternate functions aren't supported\n",
472
+ __func__);
473
+ s->afrl = value;
474
+ return;
475
+ case GPIO_AFRH:
476
+ qemu_log_mask(LOG_UNIMP,
477
+ "%s: Alternate functions aren't supported\n",
478
+ __func__);
479
+ s->afrh = value;
480
+ return;
481
+ case GPIO_BRR: {
482
+ uint32_t bits_to_reset = value & ~RESERVED_BITS_MASK;
483
+ s->odr &= ~bits_to_reset;
484
+ update_gpio_idr(s);
485
+ return;
486
+ }
487
+ case GPIO_ASCR:
488
+ qemu_log_mask(LOG_UNIMP,
489
+ "%s: ADC function isn't supported\n",
490
+ __func__);
491
+ s->ascr = value & ~RESERVED_BITS_MASK;
492
+ return;
140
+ default:
493
+ default:
141
+ g_assert_not_reached();
494
+ qemu_log_mask(LOG_GUEST_ERROR,
142
+ }
495
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
143
+}
496
+ }
144
+
497
+}
145
+static uint64_t aspeed_rtc_read(void *opaque, hwaddr addr,
498
+
146
+ unsigned size)
499
+static uint64_t stm32l4x5_gpio_read(void *opaque, hwaddr addr,
147
+{
500
+ unsigned int size)
148
+ AspeedRtcState *rtc = opaque;
501
+{
149
+ uint64_t val;
502
+ Stm32l4x5GpioState *s = opaque;
150
+ uint32_t r = addr >> 2;
503
+
151
+
504
+ trace_stm32l4x5_gpio_read(s->name, addr);
152
+ switch (r) {
505
+
153
+ case COUNTER1:
506
+ switch (addr) {
154
+ case COUNTER2:
507
+ case GPIO_MODER:
155
+ if (rtc->reg[CONTROL] & RTC_ENABLED) {
508
+ return s->moder;
156
+ rtc->reg[r] = aspeed_rtc_get_counter(rtc, r);
509
+ case GPIO_OTYPER:
157
+ }
510
+ return s->otyper;
158
+ /* fall through */
511
+ case GPIO_OSPEEDR:
159
+ case CONTROL:
512
+ return s->ospeedr;
160
+ val = rtc->reg[r];
513
+ case GPIO_PUPDR:
161
+ break;
514
+ return s->pupdr;
162
+ case ALARM:
515
+ case GPIO_IDR:
163
+ case ALARM_STATUS:
516
+ return s->idr;
517
+ case GPIO_ODR:
518
+ return s->odr;
519
+ case GPIO_BSRR:
520
+ return 0;
521
+ case GPIO_LCKR:
522
+ return s->lckr;
523
+ case GPIO_AFRL:
524
+ return s->afrl;
525
+ case GPIO_AFRH:
526
+ return s->afrh;
527
+ case GPIO_BRR:
528
+ return 0;
529
+ case GPIO_ASCR:
530
+ return s->ascr;
164
+ default:
531
+ default:
165
+ qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx "\n", __func__, addr);
532
+ qemu_log_mask(LOG_GUEST_ERROR,
533
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
166
+ return 0;
534
+ return 0;
167
+ }
535
+ }
168
+
536
+}
169
+ trace_aspeed_rtc_read(addr, val);
537
+
170
+
538
+static const MemoryRegionOps stm32l4x5_gpio_ops = {
171
+ return val;
539
+ .read = stm32l4x5_gpio_read,
172
+}
540
+ .write = stm32l4x5_gpio_write,
173
+
174
+static void aspeed_rtc_write(void *opaque, hwaddr addr,
175
+ uint64_t val, unsigned size)
176
+{
177
+ AspeedRtcState *rtc = opaque;
178
+ uint32_t r = addr >> 2;
179
+
180
+ switch (r) {
181
+ case COUNTER1:
182
+ case COUNTER2:
183
+ if (!(rtc->reg[CONTROL] & RTC_UNLOCKED)) {
184
+ break;
185
+ }
186
+ /* fall through */
187
+ case CONTROL:
188
+ rtc->reg[r] = val;
189
+ aspeed_rtc_calc_offset(rtc);
190
+ break;
191
+ case ALARM:
192
+ case ALARM_STATUS:
193
+ default:
194
+ qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx "\n", __func__, addr);
195
+ break;
196
+ }
197
+ trace_aspeed_rtc_write(addr, val);
198
+}
199
+
200
+static void aspeed_rtc_reset(DeviceState *d)
201
+{
202
+ AspeedRtcState *rtc = ASPEED_RTC(d);
203
+
204
+ rtc->offset = 0;
205
+ memset(rtc->reg, 0, sizeof(rtc->reg));
206
+}
207
+
208
+static const MemoryRegionOps aspeed_rtc_ops = {
209
+ .read = aspeed_rtc_read,
210
+ .write = aspeed_rtc_write,
211
+ .endianness = DEVICE_NATIVE_ENDIAN,
541
+ .endianness = DEVICE_NATIVE_ENDIAN,
542
+ .impl = {
543
+ .min_access_size = 4,
544
+ .max_access_size = 4,
545
+ .unaligned = false,
546
+ },
547
+ .valid = {
548
+ .min_access_size = 4,
549
+ .max_access_size = 4,
550
+ .unaligned = false,
551
+ },
212
+};
552
+};
213
+
553
+
214
+static const VMStateDescription vmstate_aspeed_rtc = {
554
+static void stm32l4x5_gpio_init(Object *obj)
215
+ .name = TYPE_ASPEED_RTC,
555
+{
556
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
557
+
558
+ memory_region_init_io(&s->mmio, obj, &stm32l4x5_gpio_ops, s,
559
+ TYPE_STM32L4X5_GPIO, 0x400);
560
+
561
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
562
+
563
+ qdev_init_gpio_out(DEVICE(obj), s->pin, GPIO_NUM_PINS);
564
+ qdev_init_gpio_in(DEVICE(obj), stm32l4x5_gpio_set, GPIO_NUM_PINS);
565
+
566
+ s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0);
567
+
568
+ object_property_add(obj, "disconnected-pins", "uint16",
569
+ disconnected_pins_get, disconnected_pins_set,
570
+ NULL, &s->disconnected_pins);
571
+ object_property_add(obj, "clock-freq-hz", "uint32",
572
+ clock_freq_get, NULL, NULL, NULL);
573
+}
574
+
575
+static void stm32l4x5_gpio_realize(DeviceState *dev, Error **errp)
576
+{
577
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(dev);
578
+ if (!clock_has_source(s->clk)) {
579
+ error_setg(errp, "GPIO: clk input must be connected");
580
+ return;
581
+ }
582
+}
583
+
584
+static const VMStateDescription vmstate_stm32l4x5_gpio = {
585
+ .name = TYPE_STM32L4X5_GPIO,
216
+ .version_id = 1,
586
+ .version_id = 1,
217
+ .fields = (VMStateField[]) {
587
+ .minimum_version_id = 1,
218
+ VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18),
588
+ .fields = (VMStateField[]){
219
+ VMSTATE_INT32(offset, AspeedRtcState),
589
+ VMSTATE_UINT32(moder, Stm32l4x5GpioState),
220
+ VMSTATE_INT32(offset, AspeedRtcState),
590
+ VMSTATE_UINT32(otyper, Stm32l4x5GpioState),
591
+ VMSTATE_UINT32(ospeedr, Stm32l4x5GpioState),
592
+ VMSTATE_UINT32(pupdr, Stm32l4x5GpioState),
593
+ VMSTATE_UINT32(idr, Stm32l4x5GpioState),
594
+ VMSTATE_UINT32(odr, Stm32l4x5GpioState),
595
+ VMSTATE_UINT32(lckr, Stm32l4x5GpioState),
596
+ VMSTATE_UINT32(afrl, Stm32l4x5GpioState),
597
+ VMSTATE_UINT32(afrh, Stm32l4x5GpioState),
598
+ VMSTATE_UINT32(ascr, Stm32l4x5GpioState),
599
+ VMSTATE_UINT16(disconnected_pins, Stm32l4x5GpioState),
600
+ VMSTATE_UINT16(pins_connected_high, Stm32l4x5GpioState),
221
+ VMSTATE_END_OF_LIST()
601
+ VMSTATE_END_OF_LIST()
222
+ }
602
+ }
223
+};
603
+};
224
+
604
+
225
+static void aspeed_rtc_realize(DeviceState *dev, Error **errp)
605
+static Property stm32l4x5_gpio_properties[] = {
226
+{
606
+ DEFINE_PROP_STRING("name", Stm32l4x5GpioState, name),
227
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
607
+ DEFINE_PROP_UINT32("mode-reset", Stm32l4x5GpioState, moder_reset, 0),
228
+ AspeedRtcState *s = ASPEED_RTC(dev);
608
+ DEFINE_PROP_UINT32("ospeed-reset", Stm32l4x5GpioState, ospeedr_reset, 0),
229
+
609
+ DEFINE_PROP_UINT32("pupd-reset", Stm32l4x5GpioState, pupdr_reset, 0),
230
+ sysbus_init_irq(sbd, &s->irq);
610
+ DEFINE_PROP_END_OF_LIST(),
231
+
611
+};
232
+ memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_rtc_ops, s,
612
+
233
+ "aspeed-rtc", 0x18ULL);
613
+static void stm32l4x5_gpio_class_init(ObjectClass *klass, void *data)
234
+ sysbus_init_mmio(sbd, &s->iomem);
235
+}
236
+
237
+static void aspeed_rtc_class_init(ObjectClass *klass, void *data)
238
+{
614
+{
239
+ DeviceClass *dc = DEVICE_CLASS(klass);
615
+ DeviceClass *dc = DEVICE_CLASS(klass);
240
+
616
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
241
+ dc->realize = aspeed_rtc_realize;
617
+
242
+ dc->vmsd = &vmstate_aspeed_rtc;
618
+ device_class_set_props(dc, stm32l4x5_gpio_properties);
243
+ dc->reset = aspeed_rtc_reset;
619
+ dc->vmsd = &vmstate_stm32l4x5_gpio;
244
+}
620
+ dc->realize = stm32l4x5_gpio_realize;
245
+
621
+ rc->phases.hold = stm32l4x5_gpio_reset_hold;
246
+static const TypeInfo aspeed_rtc_info = {
622
+}
247
+ .name = TYPE_ASPEED_RTC,
623
+
248
+ .parent = TYPE_SYS_BUS_DEVICE,
624
+static const TypeInfo stm32l4x5_gpio_types[] = {
249
+ .instance_size = sizeof(AspeedRtcState),
625
+ {
250
+ .class_init = aspeed_rtc_class_init,
626
+ .name = TYPE_STM32L4X5_GPIO,
627
+ .parent = TYPE_SYS_BUS_DEVICE,
628
+ .instance_size = sizeof(Stm32l4x5GpioState),
629
+ .instance_init = stm32l4x5_gpio_init,
630
+ .class_init = stm32l4x5_gpio_class_init,
631
+ },
251
+};
632
+};
252
+
633
+
253
+static void aspeed_rtc_register_types(void)
634
+DEFINE_TYPES(stm32l4x5_gpio_types)
254
+{
635
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
255
+ type_register_static(&aspeed_rtc_info);
256
+}
257
+
258
+type_init(aspeed_rtc_register_types)
259
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
260
index XXXXXXX..XXXXXXX 100644
636
index XXXXXXX..XXXXXXX 100644
261
--- a/hw/timer/trace-events
637
--- a/hw/gpio/Kconfig
262
+++ b/hw/timer/trace-events
638
+++ b/hw/gpio/Kconfig
263
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_dualtimer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK A
639
@@ -XXX,XX +XXX,XX @@ config GPIO_PWR
264
cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB dualtimer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
640
265
cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
641
config SIFIVE_GPIO
266
642
bool
267
+# hw/timer/aspeed-rtc.c
643
+
268
+aspeed_rtc_read(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64
644
+config STM32L4X5_GPIO
269
+aspeed_rtc_write(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64
645
+ bool
270
+
646
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
271
# sun4v-rtc.c
647
index XXXXXXX..XXXXXXX 100644
272
sun4v_rtc_read(uint64_t addr, uint64_t value) "read: addr 0x%" PRIx64 " value 0x%" PRIx64
648
--- a/hw/gpio/meson.build
273
sun4v_rtc_write(uint64_t addr, uint64_t value) "write: addr 0x%" PRIx64 " value 0x%" PRIx64
649
+++ b/hw/gpio/meson.build
650
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files(
651
'bcm2835_gpio.c',
652
'bcm2838_gpio.c'
653
))
654
+system_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_gpio.c'))
655
system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
656
system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
657
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
658
index XXXXXXX..XXXXXXX 100644
659
--- a/hw/gpio/trace-events
660
+++ b/hw/gpio/trace-events
661
@@ -XXX,XX +XXX,XX @@ sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " val
662
# aspeed_gpio.c
663
aspeed_gpio_read(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64
664
aspeed_gpio_write(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64
665
+
666
+# stm32l4x5_gpio.c
667
+stm32l4x5_gpio_read(char *gpio, uint64_t addr) "GPIO%s addr: 0x%" PRIx64 " "
668
+stm32l4x5_gpio_write(char *gpio, uint64_t addr, uint64_t data) "GPIO%s addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
669
+stm32l4x5_gpio_update_idr(char *gpio, uint32_t old_idr, uint32_t new_idr) "GPIO%s from: 0x%x to: 0x%x"
670
+stm32l4x5_gpio_pins(char *gpio, uint16_t disconnected, uint16_t high) "GPIO%s disconnected pins: 0x%x levels: 0x%x"
274
--
671
--
275
2.20.1
672
2.34.1
276
673
277
674
diff view generated by jsdifflib
Deleted patch
1
From: Joel Stanley <joel@jms.id.au>
2
1
3
All systems have an RTC.
4
5
The IRQ is hooked up but the model does not use it at this stage. There
6
is no guest code that uses it, so this limitation is acceptable.
7
8
Signed-off-by: Joel Stanley <joel@jms.id.au>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20190618165311.27066-5-clg@kaod.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/hw/arm/aspeed_soc.h | 2 ++
14
hw/arm/aspeed_soc.c | 13 +++++++++++++
15
2 files changed, 15 insertions(+)
16
17
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/aspeed_soc.h
20
+++ b/include/hw/arm/aspeed_soc.h
21
@@ -XXX,XX +XXX,XX @@
22
#include "hw/misc/aspeed_scu.h"
23
#include "hw/misc/aspeed_sdmc.h"
24
#include "hw/timer/aspeed_timer.h"
25
+#include "hw/timer/aspeed_rtc.h"
26
#include "hw/i2c/aspeed_i2c.h"
27
#include "hw/ssi/aspeed_smc.h"
28
#include "hw/watchdog/wdt_aspeed.h"
29
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
30
ARMCPU cpu;
31
MemoryRegion sram;
32
AspeedVICState vic;
33
+ AspeedRtcState rtc;
34
AspeedTimerCtrlState timerctrl;
35
AspeedI2CState i2c;
36
AspeedSCUState scu;
37
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/arm/aspeed_soc.c
40
+++ b/hw/arm/aspeed_soc.c
41
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
42
sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
43
TYPE_ASPEED_VIC);
44
45
+ sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
46
+ TYPE_ASPEED_RTC);
47
+
48
sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
49
sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
50
object_property_add_const_link(OBJECT(&s->timerctrl), "scu",
51
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
52
sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
53
qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
54
55
+ /* RTC */
56
+ object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
57
+ if (err) {
58
+ error_propagate(errp, err);
59
+ return;
60
+ }
61
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->info->memmap[ASPEED_RTC]);
62
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
63
+ aspeed_soc_get_irq(s, ASPEED_RTC));
64
+
65
/* Timer */
66
object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
67
if (err) {
68
--
69
2.20.1
70
71
diff view generated by jsdifflib
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
The current models of the Aspeed SoCs only have one CPU but future
4
ones will support SMP. Introduce a new num_cpus field at the SoC class
5
level to define the number of available CPUs per SoC and also
6
introduce a 'num-cpus' property to activate the CPUs configured for
7
the machine.
8
9
The max_cpus limit of the machine should depend on the SoC definition
10
but, unfortunately, these values are not available when the machine
11
class is initialized. This is the reason why we add a check on
12
num_cpus in the AspeedSoC realize handler.
13
14
SMP support will be activated when models for such SoCs are implemented.
15
16
Signed-off-by: Cédric Le Goater <clg@kaod.org>
17
Reviewed-by: Joel Stanley <joel@jms.id.au>
18
Message-id: 20190618165311.27066-6-clg@kaod.org
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
include/hw/arm/aspeed_soc.h | 5 ++++-
22
hw/arm/aspeed.c | 7 +++++--
23
hw/arm/aspeed_soc.c | 33 +++++++++++++++++++++++++++------
24
3 files changed, 36 insertions(+), 9 deletions(-)
25
26
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/arm/aspeed_soc.h
29
+++ b/include/hw/arm/aspeed_soc.h
30
@@ -XXX,XX +XXX,XX @@
31
32
#define ASPEED_SPIS_NUM 2
33
#define ASPEED_WDTS_NUM 3
34
+#define ASPEED_CPUS_NUM 2
35
36
typedef struct AspeedSoCState {
37
/*< private >*/
38
DeviceState parent;
39
40
/*< public >*/
41
- ARMCPU cpu;
42
+ ARMCPU cpu[ASPEED_CPUS_NUM];
43
+ uint32_t num_cpus;
44
MemoryRegion sram;
45
AspeedVICState vic;
46
AspeedRtcState rtc;
47
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCInfo {
48
int wdts_num;
49
const int *irqmap;
50
const hwaddr *memmap;
51
+ uint32_t num_cpus;
52
} AspeedSoCInfo;
53
54
typedef struct AspeedSoCClass {
55
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/arm/aspeed.c
58
+++ b/hw/arm/aspeed.c
59
@@ -XXX,XX +XXX,XX @@
60
#include "hw/misc/tmp105.h"
61
#include "qemu/log.h"
62
#include "sysemu/block-backend.h"
63
+#include "sysemu/sysemu.h"
64
#include "hw/loader.h"
65
#include "qemu/error-report.h"
66
#include "qemu/units.h"
67
68
static struct arm_boot_info aspeed_board_binfo = {
69
.board_id = -1, /* device-tree-only board */
70
- .nb_cpus = 1,
71
};
72
73
struct AspeedBoardState {
74
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
75
&error_abort);
76
object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs",
77
&error_abort);
78
+ object_property_set_int(OBJECT(&bmc->soc), smp_cpus, "num-cpus",
79
+ &error_abort);
80
if (machine->kernel_filename) {
81
/*
82
* When booting with a -kernel command line there is no u-boot
83
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
84
aspeed_board_binfo.kernel_cmdline = machine->kernel_cmdline;
85
aspeed_board_binfo.ram_size = ram_size;
86
aspeed_board_binfo.loader_start = sc->info->memmap[ASPEED_SDRAM];
87
+ aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus;
88
89
if (cfg->i2c_init) {
90
cfg->i2c_init(bmc);
91
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data)
92
93
mc->desc = board->desc;
94
mc->init = aspeed_machine_init;
95
- mc->max_cpus = 1;
96
+ mc->max_cpus = ASPEED_CPUS_NUM;
97
mc->no_sdcard = 1;
98
mc->no_floppy = 1;
99
mc->no_cdrom = 1;
100
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/hw/arm/aspeed_soc.c
103
+++ b/hw/arm/aspeed_soc.c
104
@@ -XXX,XX +XXX,XX @@
105
#include "hw/char/serial.h"
106
#include "qemu/log.h"
107
#include "qemu/module.h"
108
+#include "qemu/error-report.h"
109
#include "hw/i2c/aspeed_i2c.h"
110
#include "net/net.h"
111
112
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
113
.wdts_num = 2,
114
.irqmap = aspeed_soc_ast2400_irqmap,
115
.memmap = aspeed_soc_ast2400_memmap,
116
+ .num_cpus = 1,
117
}, {
118
.name = "ast2400-a1",
119
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
120
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
121
.wdts_num = 2,
122
.irqmap = aspeed_soc_ast2400_irqmap,
123
.memmap = aspeed_soc_ast2400_memmap,
124
+ .num_cpus = 1,
125
}, {
126
.name = "ast2400",
127
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
128
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
129
.wdts_num = 2,
130
.irqmap = aspeed_soc_ast2400_irqmap,
131
.memmap = aspeed_soc_ast2400_memmap,
132
+ .num_cpus = 1,
133
}, {
134
.name = "ast2500-a1",
135
.cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
136
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
137
.wdts_num = 3,
138
.irqmap = aspeed_soc_ast2500_irqmap,
139
.memmap = aspeed_soc_ast2500_memmap,
140
+ .num_cpus = 1,
141
},
142
};
143
144
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
145
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
146
int i;
147
148
- object_initialize_child(obj, "cpu", OBJECT(&s->cpu), sizeof(s->cpu),
149
- sc->info->cpu_type, &error_abort, NULL);
150
+ for (i = 0; i < sc->info->num_cpus; i++) {
151
+ object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
152
+ sizeof(s->cpu[i]), sc->info->cpu_type,
153
+ &error_abort, NULL);
154
+ }
155
156
sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
157
TYPE_ASPEED_SCU);
158
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
159
create_unimplemented_device("aspeed_soc.io", sc->info->memmap[ASPEED_IOMEM],
160
ASPEED_SOC_IOMEM_SIZE);
161
162
+ if (s->num_cpus > sc->info->num_cpus) {
163
+ warn_report("%s: invalid number of CPUs %d, using default %d",
164
+ sc->info->name, s->num_cpus, sc->info->num_cpus);
165
+ s->num_cpus = sc->info->num_cpus;
166
+ }
167
+
168
/* CPU */
169
- object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
170
- if (err) {
171
- error_propagate(errp, err);
172
- return;
173
+ for (i = 0; i < s->num_cpus; i++) {
174
+ object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
175
+ if (err) {
176
+ error_propagate(errp, err);
177
+ return;
178
+ }
179
}
180
181
/* SRAM */
182
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
183
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
184
aspeed_soc_get_irq(s, ASPEED_ETH1));
185
}
186
+static Property aspeed_soc_properties[] = {
187
+ DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
188
+ DEFINE_PROP_END_OF_LIST(),
189
+};
190
191
static void aspeed_soc_class_init(ObjectClass *oc, void *data)
192
{
193
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
194
dc->realize = aspeed_soc_realize;
195
/* Reason: Uses serial_hds and nd_table in realize() directly */
196
dc->user_creatable = false;
197
+ dc->props = aspeed_soc_properties;
198
}
199
200
static const TypeInfo aspeed_soc_type_info = {
201
--
202
2.20.1
203
204
diff view generated by jsdifflib
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
The Aspeed SoCs have two MACs. Extend the Aspeed model to support a
4
second NIC.
5
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7
Reviewed-by: Joel Stanley <joel@jms.id.au>
8
Message-id: 20190618165311.27066-7-clg@kaod.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/aspeed_soc.h | 3 ++-
12
hw/arm/aspeed_soc.c | 33 +++++++++++++++++++--------------
13
2 files changed, 21 insertions(+), 15 deletions(-)
14
15
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/aspeed_soc.h
18
+++ b/include/hw/arm/aspeed_soc.h
19
@@ -XXX,XX +XXX,XX @@
20
#define ASPEED_SPIS_NUM 2
21
#define ASPEED_WDTS_NUM 3
22
#define ASPEED_CPUS_NUM 2
23
+#define ASPEED_MACS_NUM 2
24
25
typedef struct AspeedSoCState {
26
/*< private >*/
27
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
28
AspeedSMCState spi[ASPEED_SPIS_NUM];
29
AspeedSDMCState sdmc;
30
AspeedWDTState wdt[ASPEED_WDTS_NUM];
31
- FTGMAC100State ftgmac100;
32
+ FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
33
} AspeedSoCState;
34
35
#define TYPE_ASPEED_SOC "aspeed-soc"
36
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/arm/aspeed_soc.c
39
+++ b/hw/arm/aspeed_soc.c
40
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
41
sc->info->silicon_rev);
42
}
43
44
- sysbus_init_child_obj(obj, "ftgmac100", OBJECT(&s->ftgmac100),
45
- sizeof(s->ftgmac100), TYPE_FTGMAC100);
46
+ for (i = 0; i < ASPEED_MACS_NUM; i++) {
47
+ sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
48
+ sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
49
+ }
50
}
51
52
static void aspeed_soc_realize(DeviceState *dev, Error **errp)
53
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
54
}
55
56
/* Net */
57
- qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]);
58
- object_property_set_bool(OBJECT(&s->ftgmac100), true, "aspeed", &err);
59
- object_property_set_bool(OBJECT(&s->ftgmac100), true, "realized",
60
- &local_err);
61
- error_propagate(&err, local_err);
62
- if (err) {
63
- error_propagate(errp, err);
64
- return;
65
+ for (i = 0; i < nb_nics; i++) {
66
+ qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
67
+ object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
68
+ &err);
69
+ object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
70
+ &local_err);
71
+ error_propagate(&err, local_err);
72
+ if (err) {
73
+ error_propagate(errp, err);
74
+ return;
75
+ }
76
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
77
+ sc->info->memmap[ASPEED_ETH1 + i]);
78
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
79
+ aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
80
}
81
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0,
82
- sc->info->memmap[ASPEED_ETH1]);
83
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
84
- aspeed_soc_get_irq(s, ASPEED_ETH1));
85
}
86
static Property aspeed_soc_properties[] = {
87
DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
88
--
89
2.20.1
90
91
diff view generated by jsdifflib
Deleted patch
1
From: Joel Stanley <joel@jms.id.au>
2
1
3
The Linux kernel driver was updated in commit 4451d3f59f2a
4
("clocksource/drivers/fttmr010: Fix set_next_event handler) to fix an
5
issue observed on hardware:
6
7
> RELOAD register is loaded into COUNT register when the aspeed timer
8
> is enabled, which means the next event may be delayed because timer
9
> interrupt won't be generated until <0xFFFFFFFF - current_count +
10
> cycles>.
11
12
When running under Qemu, the system appeared "laggy". The guest is now
13
scheduling timer events too regularly, starving the host of CPU time.
14
15
This patch modifies the timer model to attempt to schedule the timer
16
expiry as the guest requests, but if we have missed the deadline we
17
re interrupt and try again, which allows the guest to catch up.
18
19
Provides expected behaviour with old and new guest code.
20
21
Fixes: c04bd47db6b9 ("hw/timer: Add ASPEED timer device model")
22
Signed-off-by: Joel Stanley <joel@jms.id.au>
23
Signed-off-by: Cédric Le Goater <clg@kaod.org>
24
Message-id: 20190618165311.27066-8-clg@kaod.org
25
[clg: - merged a fix from Andrew Jeffery <andrew@aj.id.au>
26
"Fire interrupt on failure to meet deadline"
27
https://lists.ozlabs.org/pipermail/openbmc/2019-January/014641.html
28
- adapted commit log
29
- checkpatch fixes ]
30
Signed-off-by: Cédric Le Goater <clg@kaod.org>
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
---
33
hw/timer/aspeed_timer.c | 57 ++++++++++++++++++++++-------------------
34
1 file changed, 30 insertions(+), 27 deletions(-)
35
36
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/timer/aspeed_timer.c
39
+++ b/hw/timer/aspeed_timer.c
40
@@ -XXX,XX +XXX,XX @@ static inline uint64_t calculate_time(struct AspeedTimer *t, uint32_t ticks)
41
42
static uint64_t calculate_next(struct AspeedTimer *t)
43
{
44
- uint64_t next = 0;
45
- uint32_t rate = calculate_rate(t);
46
+ uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
47
+ uint64_t next;
48
49
- while (!next) {
50
- /* We don't know the relationship between the values in the match
51
- * registers, so sort using MAX/MIN/zero. We sort in that order as the
52
- * timer counts down to zero. */
53
- uint64_t seq[] = {
54
- calculate_time(t, MAX(t->match[0], t->match[1])),
55
- calculate_time(t, MIN(t->match[0], t->match[1])),
56
- calculate_time(t, 0),
57
- };
58
- uint64_t reload_ns;
59
- uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
60
+ /*
61
+ * We don't know the relationship between the values in the match
62
+ * registers, so sort using MAX/MIN/zero. We sort in that order as
63
+ * the timer counts down to zero.
64
+ */
65
66
- if (now < seq[0]) {
67
- next = seq[0];
68
- } else if (now < seq[1]) {
69
- next = seq[1];
70
- } else if (now < seq[2]) {
71
- next = seq[2];
72
- } else if (t->reload) {
73
- reload_ns = muldiv64(t->reload, NANOSECONDS_PER_SECOND, rate);
74
- t->start = now - ((now - t->start) % reload_ns);
75
- } else {
76
- /* no reload value, return 0 */
77
- break;
78
- }
79
+ next = calculate_time(t, MAX(t->match[0], t->match[1]));
80
+ if (now < next) {
81
+ return next;
82
}
83
84
- return next;
85
+ next = calculate_time(t, MIN(t->match[0], t->match[1]));
86
+ if (now < next) {
87
+ return next;
88
+ }
89
+
90
+ next = calculate_time(t, 0);
91
+ if (now < next) {
92
+ return next;
93
+ }
94
+
95
+ /* We've missed all deadlines, fire interrupt and try again */
96
+ timer_del(&t->timer);
97
+
98
+ if (timer_overflow_interrupt(t)) {
99
+ t->level = !t->level;
100
+ qemu_set_irq(t->irq, t->level);
101
+ }
102
+
103
+ t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
104
+ return calculate_time(t, MAX(MAX(t->match[0], t->match[1]), 0));
105
}
106
107
static void aspeed_timer_mod(AspeedTimer *t)
108
--
109
2.20.1
110
111
diff view generated by jsdifflib
Deleted patch
1
From: Andrew Jeffery <andrew@aj.id.au>
2
1
3
From the datasheet:
4
5
This register stores the current status of counter #N. When timer
6
enable bit TMC30[N * b] is disabled, the reload register will be
7
loaded into this counter. When timer bit TMC30[N * b] is set, the
8
counter will start to decrement. CPU can update this register value
9
when enable bit is set.
10
11
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
12
Signed-off-by: Cédric Le Goater <clg@kaod.org>
13
Reviewed-by: Joel Stanley <joel@jms.id.au>
14
Message-id: 20190618165311.27066-9-clg@kaod.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/timer/aspeed_timer.c | 6 +++++-
18
1 file changed, 5 insertions(+), 1 deletion(-)
19
20
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/timer/aspeed_timer.c
23
+++ b/hw/timer/aspeed_timer.c
24
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_timer_get_value(AspeedTimer *t, int reg)
25
26
switch (reg) {
27
case TIMER_REG_STATUS:
28
- value = calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
29
+ if (timer_enabled(t)) {
30
+ value = calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
31
+ } else {
32
+ value = t->reload;
33
+ }
34
break;
35
case TIMER_REG_RELOAD:
36
value = t->reload;
37
--
38
2.20.1
39
40
diff view generated by jsdifflib
Deleted patch
1
From: Andrew Jeffery <andrew@aj.id.au>
2
1
3
If the match value exceeds reload then we don't want to include it in
4
calculations for the next event.
5
6
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
7
Signed-off-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: 20190618165311.27066-10-clg@kaod.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/timer/aspeed_timer.c | 13 ++++++++++---
12
1 file changed, 10 insertions(+), 3 deletions(-)
13
14
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/timer/aspeed_timer.c
17
+++ b/hw/timer/aspeed_timer.c
18
@@ -XXX,XX +XXX,XX @@ static inline uint64_t calculate_time(struct AspeedTimer *t, uint32_t ticks)
19
return t->start + delta_ns;
20
}
21
22
+static inline uint32_t calculate_match(struct AspeedTimer *t, int i)
23
+{
24
+ return t->match[i] < t->reload ? t->match[i] : 0;
25
+}
26
+
27
static uint64_t calculate_next(struct AspeedTimer *t)
28
{
29
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
30
@@ -XXX,XX +XXX,XX @@ static uint64_t calculate_next(struct AspeedTimer *t)
31
* the timer counts down to zero.
32
*/
33
34
- next = calculate_time(t, MAX(t->match[0], t->match[1]));
35
+ next = calculate_time(t, MAX(calculate_match(t, 0), calculate_match(t, 1)));
36
if (now < next) {
37
return next;
38
}
39
40
- next = calculate_time(t, MIN(t->match[0], t->match[1]));
41
+ next = calculate_time(t, MIN(calculate_match(t, 0), calculate_match(t, 1)));
42
if (now < next) {
43
return next;
44
}
45
@@ -XXX,XX +XXX,XX @@ static uint64_t calculate_next(struct AspeedTimer *t)
46
qemu_set_irq(t->irq, t->level);
47
}
48
49
+ next = MAX(MAX(calculate_match(t, 0), calculate_match(t, 1)), 0);
50
t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
51
- return calculate_time(t, MAX(MAX(t->match[0], t->match[1]), 0));
52
+
53
+ return calculate_time(t, next);
54
}
55
56
static void aspeed_timer_mod(AspeedTimer *t)
57
--
58
2.20.1
59
60
diff view generated by jsdifflib
Deleted patch
1
From: Christian Svensson <bluecmd@google.com>
2
1
3
If the host decrements the counter register that results in a negative
4
delta. This is then passed to muldiv64 which only handles unsigned
5
numbers resulting in bogus results.
6
7
This fix ensures the delta being operated on is positive.
8
9
Test case: kexec a kernel using aspeed_timer and it will freeze on the
10
second bootup when the kernel initializes the timer. With this patch
11
that no longer happens and the timer appears to run OK.
12
13
Signed-off-by: Christian Svensson <bluecmd@google.com>
14
Signed-off-by: Cédric Le Goater <clg@kaod.org>
15
Reviewed-by: Joel Stanley <joel@jms.id.au>
16
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
17
Message-id: 20190618165311.27066-12-clg@kaod.org
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
hw/timer/aspeed_timer.c | 6 +++++-
21
1 file changed, 5 insertions(+), 1 deletion(-)
22
23
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/timer/aspeed_timer.c
26
+++ b/hw/timer/aspeed_timer.c
27
@@ -XXX,XX +XXX,XX @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
28
int64_t delta = (int64_t) value - (int64_t) calculate_ticks(t, now);
29
uint32_t rate = calculate_rate(t);
30
31
- t->start += muldiv64(delta, NANOSECONDS_PER_SECOND, rate);
32
+ if (delta >= 0) {
33
+ t->start += muldiv64(delta, NANOSECONDS_PER_SECOND, rate);
34
+ } else {
35
+ t->start -= muldiv64(-delta, NANOSECONDS_PER_SECOND, rate);
36
+ }
37
aspeed_timer_mod(t);
38
}
39
break;
40
--
41
2.20.1
42
43
diff view generated by jsdifflib
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
It has never been used as far as I can tell from the git history.
4
5
Signed-off-by: Cédric Le Goater <clg@kaod.org>
6
Reviewed-by: Joel Stanley <joel@jms.id.au>
7
Message-id: 20190618165311.27066-13-clg@kaod.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/arm/aspeed.c | 2 --
11
1 file changed, 2 deletions(-)
12
13
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/aspeed.c
16
+++ b/hw/arm/aspeed.c
17
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
18
memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
19
memory_region_add_subregion(get_system_memory(),
20
sc->info->memmap[ASPEED_SDRAM], &bmc->ram);
21
- object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
22
- &error_abort);
23
24
max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
25
&error_abort);
26
--
27
2.20.1
28
29
diff view generated by jsdifflib
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
The RAM memory region is defined after the SoC is realized when the
4
SDMC controller has checked that the defined RAM size for the machine
5
is correct. This is problematic for controller models requiring a link
6
on the RAM region, for DMA support in the SMC controller for instance.
7
8
Introduce a container memory region for the RAM that we can link into
9
the controllers early, before the SoC is realized. It will be
10
populated with the RAM region after the checks have be done.
11
12
Signed-off-by: Cédric Le Goater <clg@kaod.org>
13
Reviewed-by: Joel Stanley <joel@jms.id.au>
14
Message-id: 20190618165311.27066-14-clg@kaod.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/arm/aspeed.c | 13 +++++++++----
18
1 file changed, 9 insertions(+), 4 deletions(-)
19
20
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/aspeed.c
23
+++ b/hw/arm/aspeed.c
24
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info aspeed_board_binfo = {
25
26
struct AspeedBoardState {
27
AspeedSoCState soc;
28
+ MemoryRegion ram_container;
29
MemoryRegion ram;
30
MemoryRegion max_ram;
31
};
32
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
33
ram_addr_t max_ram_size;
34
35
bmc = g_new0(AspeedBoardState, 1);
36
+
37
+ memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container",
38
+ UINT32_MAX);
39
+
40
object_initialize_child(OBJECT(machine), "soc", &bmc->soc,
41
(sizeof(bmc->soc)), cfg->soc_name, &error_abort,
42
NULL);
43
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
44
&error_abort);
45
46
memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
47
+ memory_region_add_subregion(&bmc->ram_container, 0, &bmc->ram);
48
memory_region_add_subregion(get_system_memory(),
49
- sc->info->memmap[ASPEED_SDRAM], &bmc->ram);
50
+ sc->info->memmap[ASPEED_SDRAM],
51
+ &bmc->ram_container);
52
53
max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
54
&error_abort);
55
memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
56
"max_ram", max_ram_size - ram_size);
57
- memory_region_add_subregion(get_system_memory(),
58
- sc->info->memmap[ASPEED_SDRAM] + ram_size,
59
- &bmc->max_ram);
60
+ memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_ram);
61
62
aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);
63
aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort);
64
--
65
2.20.1
66
67
diff view generated by jsdifflib
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
The DRAM address of a DMA transaction depends on the DRAM base address
4
of the SoC. Inform the SMC controller model with this value.
5
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7
Reviewed-by: Joel Stanley <joel@jms.id.au>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190618165311.27066-15-clg@kaod.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/ssi/aspeed_smc.h | 3 +++
13
hw/arm/aspeed_soc.c | 6 ++++++
14
hw/ssi/aspeed_smc.c | 1 +
15
3 files changed, 10 insertions(+)
16
17
diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/ssi/aspeed_smc.h
20
+++ b/include/hw/ssi/aspeed_smc.h
21
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSMCState {
22
uint8_t r_timings;
23
uint8_t conf_enable_w0;
24
25
+ /* for DMA support */
26
+ uint64_t sdram_base;
27
+
28
AspeedSMCFlash *flashes;
29
30
uint8_t snoop_index;
31
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/aspeed_soc.c
34
+++ b/hw/arm/aspeed_soc.c
35
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
36
aspeed_soc_get_irq(s, ASPEED_I2C));
37
38
/* FMC, The number of CS is set at the board level */
39
+ object_property_set_int(OBJECT(&s->fmc), sc->info->memmap[ASPEED_SDRAM],
40
+ "sdram-base", &err);
41
+ if (err) {
42
+ error_propagate(errp, err);
43
+ return;
44
+ }
45
object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
46
if (err) {
47
error_propagate(errp, err);
48
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/ssi/aspeed_smc.c
51
+++ b/hw/ssi/aspeed_smc.c
52
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_smc = {
53
54
static Property aspeed_smc_properties[] = {
55
DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1),
56
+ DEFINE_PROP_UINT64("sdram-base", AspeedSMCState, sdram_base, 0),
57
DEFINE_PROP_END_OF_LIST(),
58
};
59
60
--
61
2.20.1
62
63
diff view generated by jsdifflib
Deleted patch
1
From: Adriana Kobylak <anoo@us.ibm.com>
2
1
3
The Swift board is an OpenPOWER system hosting POWER processors.
4
Add support for their BMC including the I2C devices as found on HW.
5
6
Signed-off-by: Adriana Kobylak <anoo@us.ibm.com>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Reviewed-by: Joel Stanley <joel@jms.id.au>
9
Message-id: 20190618165311.27066-20-clg@kaod.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/aspeed.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++++
13
1 file changed, 50 insertions(+)
14
15
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/aspeed.c
18
+++ b/hw/arm/aspeed.c
19
@@ -XXX,XX +XXX,XX @@ struct AspeedBoardState {
20
SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
21
SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
22
23
+/* Swift hardware value: 0xF11AD206 */
24
+#define SWIFT_BMC_HW_STRAP1 ( \
25
+ AST2500_HW_STRAP1_DEFAULTS | \
26
+ SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
27
+ SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
28
+ SCU_AST2500_HW_STRAP_UART_DEBUG | \
29
+ SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
30
+ SCU_H_PLL_BYPASS_EN | \
31
+ SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
32
+ SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
33
+
34
/* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
35
#define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
36
37
@@ -XXX,XX +XXX,XX @@ static void romulus_bmc_i2c_init(AspeedBoardState *bmc)
38
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
39
}
40
41
+static void swift_bmc_i2c_init(AspeedBoardState *bmc)
42
+{
43
+ AspeedSoCState *soc = &bmc->soc;
44
+
45
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), "pca9552", 0x60);
46
+
47
+ /* The swift board expects a TMP275 but a TMP105 is compatible */
48
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x48);
49
+ /* The swift board expects a pca9551 but a pca9552 is compatible */
50
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "pca9552", 0x60);
51
+
52
+ /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */
53
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "ds1338", 0x32);
54
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x60);
55
+
56
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "tmp423", 0x4c);
57
+ /* The swift board expects a pca9539 but a pca9552 is compatible */
58
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "pca9552", 0x74);
59
+
60
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "tmp423", 0x4c);
61
+ /* The swift board expects a pca9539 but a pca9552 is compatible */
62
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "pca9552",
63
+ 0x74);
64
+
65
+ /* The swift board expects a TMP275 but a TMP105 is compatible */
66
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x48);
67
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x4a);
68
+}
69
+
70
static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
71
{
72
AspeedSoCState *soc = &bmc->soc;
73
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
74
.num_cs = 2,
75
.i2c_init = romulus_bmc_i2c_init,
76
.ram = 512 * MiB,
77
+ }, {
78
+ .name = MACHINE_TYPE_NAME("swift-bmc"),
79
+ .desc = "OpenPOWER Swift BMC (ARM1176)",
80
+ .soc_name = "ast2500-a1",
81
+ .hw_strap1 = SWIFT_BMC_HW_STRAP1,
82
+ .fmc_model = "mx66l1g45g",
83
+ .spi_model = "mx66l1g45g",
84
+ .num_cs = 2,
85
+ .i2c_init = swift_bmc_i2c_init,
86
+ .ram = 512 * MiB,
87
}, {
88
.name = MACHINE_TYPE_NAME("witherspoon-bmc"),
89
.desc = "OpenPOWER Witherspoon BMC (ARM1176)",
90
--
91
2.20.1
92
93
diff view generated by jsdifflib
Deleted patch
1
From: Andrew Jeffery <andrew@aj.id.au>
2
1
3
The legacy interface only supported up to 32 IRQs, which became
4
restrictive around the AST2400 generation. QEMU support for the SoCs
5
started with the AST2400 along with an effort to reimplement and
6
upstream drivers for Linux, so up until this point the consumers of the
7
QEMU ASPEED support only required the 64 IRQ register interface.
8
9
In an effort to support older BMC firmware, add support for the 32 IRQ
10
interface.
11
12
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
13
Signed-off-by: Cédric Le Goater <clg@kaod.org>
14
Reviewed-by: Joel Stanley <joel@jms.id.au>
15
Message-id: 20190618165311.27066-22-clg@kaod.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
hw/intc/aspeed_vic.c | 105 ++++++++++++++++++++++++++-----------------
19
1 file changed, 63 insertions(+), 42 deletions(-)
20
21
diff --git a/hw/intc/aspeed_vic.c b/hw/intc/aspeed_vic.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/intc/aspeed_vic.c
24
+++ b/hw/intc/aspeed_vic.c
25
@@ -XXX,XX +XXX,XX @@ static void aspeed_vic_set_irq(void *opaque, int irq, int level)
26
27
static uint64_t aspeed_vic_read(void *opaque, hwaddr offset, unsigned size)
28
{
29
- uint64_t val;
30
- const bool high = !!(offset & 0x4);
31
- hwaddr n_offset = (offset & ~0x4);
32
AspeedVICState *s = (AspeedVICState *)opaque;
33
+ hwaddr n_offset;
34
+ uint64_t val;
35
+ bool high;
36
37
if (offset < AVIC_NEW_BASE_OFFSET) {
38
- qemu_log_mask(LOG_UNIMP, "%s: Ignoring read from legacy registers "
39
- "at 0x%" HWADDR_PRIx "[%u]\n", __func__, offset, size);
40
- return 0;
41
+ high = false;
42
+ n_offset = offset;
43
+ } else {
44
+ high = !!(offset & 0x4);
45
+ n_offset = (offset & ~0x4);
46
}
47
48
- n_offset -= AVIC_NEW_BASE_OFFSET;
49
-
50
switch (n_offset) {
51
- case 0x0: /* IRQ Status */
52
+ case 0x80: /* IRQ Status */
53
+ case 0x00:
54
val = s->raw & ~s->select & s->enable;
55
break;
56
- case 0x08: /* FIQ Status */
57
+ case 0x88: /* FIQ Status */
58
+ case 0x04:
59
val = s->raw & s->select & s->enable;
60
break;
61
- case 0x10: /* Raw Interrupt Status */
62
+ case 0x90: /* Raw Interrupt Status */
63
+ case 0x08:
64
val = s->raw;
65
break;
66
- case 0x18: /* Interrupt Selection */
67
+ case 0x98: /* Interrupt Selection */
68
+ case 0x0c:
69
val = s->select;
70
break;
71
- case 0x20: /* Interrupt Enable */
72
+ case 0xa0: /* Interrupt Enable */
73
+ case 0x10:
74
val = s->enable;
75
break;
76
- case 0x30: /* Software Interrupt */
77
+ case 0xb0: /* Software Interrupt */
78
+ case 0x18:
79
val = s->trigger;
80
break;
81
- case 0x40: /* Interrupt Sensitivity */
82
+ case 0xc0: /* Interrupt Sensitivity */
83
+ case 0x24:
84
val = s->sense;
85
break;
86
- case 0x48: /* Interrupt Both Edge Trigger Control */
87
+ case 0xc8: /* Interrupt Both Edge Trigger Control */
88
+ case 0x28:
89
val = s->dual_edge;
90
break;
91
- case 0x50: /* Interrupt Event */
92
+ case 0xd0: /* Interrupt Event */
93
+ case 0x2c:
94
val = s->event;
95
break;
96
- case 0x60: /* Edge Triggered Interrupt Status */
97
+ case 0xe0: /* Edge Triggered Interrupt Status */
98
val = s->raw & ~s->sense;
99
break;
100
/* Illegal */
101
- case 0x28: /* Interrupt Enable Clear */
102
- case 0x38: /* Software Interrupt Clear */
103
- case 0x58: /* Edge Triggered Interrupt Clear */
104
+ case 0xa8: /* Interrupt Enable Clear */
105
+ case 0xb8: /* Software Interrupt Clear */
106
+ case 0xd8: /* Edge Triggered Interrupt Clear */
107
qemu_log_mask(LOG_GUEST_ERROR,
108
"%s: Read of write-only register with offset 0x%"
109
HWADDR_PRIx "\n", __func__, offset);
110
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_vic_read(void *opaque, hwaddr offset, unsigned size)
111
}
112
if (high) {
113
val = extract64(val, 32, 19);
114
+ } else {
115
+ val = extract64(val, 0, 32);
116
}
117
trace_aspeed_vic_read(offset, size, val);
118
return val;
119
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_vic_read(void *opaque, hwaddr offset, unsigned size)
120
static void aspeed_vic_write(void *opaque, hwaddr offset, uint64_t data,
121
unsigned size)
122
{
123
- const bool high = !!(offset & 0x4);
124
- hwaddr n_offset = (offset & ~0x4);
125
AspeedVICState *s = (AspeedVICState *)opaque;
126
+ hwaddr n_offset;
127
+ bool high;
128
129
if (offset < AVIC_NEW_BASE_OFFSET) {
130
- qemu_log_mask(LOG_UNIMP,
131
- "%s: Ignoring write to legacy registers at 0x%"
132
- HWADDR_PRIx "[%u] <- 0x%" PRIx64 "\n", __func__, offset,
133
- size, data);
134
- return;
135
+ high = false;
136
+ n_offset = offset;
137
+ } else {
138
+ high = !!(offset & 0x4);
139
+ n_offset = (offset & ~0x4);
140
}
141
142
- n_offset -= AVIC_NEW_BASE_OFFSET;
143
trace_aspeed_vic_write(offset, size, data);
144
145
/* Given we have members using separate enable/clear registers, deposit64()
146
@@ -XXX,XX +XXX,XX @@ static void aspeed_vic_write(void *opaque, hwaddr offset, uint64_t data,
147
}
148
149
switch (n_offset) {
150
- case 0x18: /* Interrupt Selection */
151
+ case 0x98: /* Interrupt Selection */
152
+ case 0x0c:
153
/* Register has deposit64() semantics - overwrite requested 32 bits */
154
if (high) {
155
s->select &= AVIC_L_MASK;
156
@@ -XXX,XX +XXX,XX @@ static void aspeed_vic_write(void *opaque, hwaddr offset, uint64_t data,
157
}
158
s->select |= data;
159
break;
160
- case 0x20: /* Interrupt Enable */
161
+ case 0xa0: /* Interrupt Enable */
162
+ case 0x10:
163
s->enable |= data;
164
break;
165
- case 0x28: /* Interrupt Enable Clear */
166
+ case 0xa8: /* Interrupt Enable Clear */
167
+ case 0x14:
168
s->enable &= ~data;
169
break;
170
- case 0x30: /* Software Interrupt */
171
+ case 0xb0: /* Software Interrupt */
172
+ case 0x18:
173
qemu_log_mask(LOG_UNIMP, "%s: Software interrupts unavailable. "
174
"IRQs requested: 0x%016" PRIx64 "\n", __func__, data);
175
break;
176
- case 0x38: /* Software Interrupt Clear */
177
+ case 0xb8: /* Software Interrupt Clear */
178
+ case 0x1c:
179
qemu_log_mask(LOG_UNIMP, "%s: Software interrupts unavailable. "
180
"IRQs to be cleared: 0x%016" PRIx64 "\n", __func__, data);
181
break;
182
- case 0x50: /* Interrupt Event */
183
+ case 0xd0: /* Interrupt Event */
184
/* Register has deposit64() semantics - overwrite the top four valid
185
* IRQ bits, as only the top four IRQs (GPIOs) can change their event
186
* type */
187
@@ -XXX,XX +XXX,XX @@ static void aspeed_vic_write(void *opaque, hwaddr offset, uint64_t data,
188
"Ignoring invalid write to interrupt event register");
189
}
190
break;
191
- case 0x58: /* Edge Triggered Interrupt Clear */
192
+ case 0xd8: /* Edge Triggered Interrupt Clear */
193
+ case 0x38:
194
s->raw &= ~(data & ~s->sense);
195
break;
196
- case 0x00: /* IRQ Status */
197
- case 0x08: /* FIQ Status */
198
- case 0x10: /* Raw Interrupt Status */
199
- case 0x40: /* Interrupt Sensitivity */
200
- case 0x48: /* Interrupt Both Edge Trigger Control */
201
- case 0x60: /* Edge Triggered Interrupt Status */
202
+ case 0x80: /* IRQ Status */
203
+ case 0x00:
204
+ case 0x88: /* FIQ Status */
205
+ case 0x04:
206
+ case 0x90: /* Raw Interrupt Status */
207
+ case 0x08:
208
+ case 0xc0: /* Interrupt Sensitivity */
209
+ case 0x24:
210
+ case 0xc8: /* Interrupt Both Edge Trigger Control */
211
+ case 0x28:
212
+ case 0xe0: /* Edge Triggered Interrupt Status */
213
qemu_log_mask(LOG_GUEST_ERROR,
214
"%s: Write of read-only register with offset 0x%"
215
HWADDR_PRIx "\n", __func__, offset);
216
--
217
2.20.1
218
219
diff view generated by jsdifflib
Deleted patch
1
From: Joel Stanley <joel@jms.id.au>
2
1
3
The ast2500 uses the watchdog to reset the SDRAM controller. This
4
operation is usually performed by u-boot's memory training procedure,
5
and it is enabled by setting a bit in the SCU and then causing the
6
watchdog to expire. Therefore, we need the watchdog to be able to
7
access the SCU's register space.
8
9
This causes the watchdog to not perform a system reset when the bit is
10
set. In the future it could perform a reset of the SDMC model.
11
12
Signed-off-by: Joel Stanley <joel@jms.id.au>
13
Signed-off-by: Cédric Le Goater <clg@kaod.org>
14
Reviewed-by: Cédric Le Goater <clg@kaod.org>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
16
Message-id: 20190621065242.32535-1-joel@jms.id.au
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
include/hw/watchdog/wdt_aspeed.h | 1 +
20
hw/arm/aspeed_soc.c | 2 ++
21
hw/watchdog/wdt_aspeed.c | 20 ++++++++++++++++++++
22
3 files changed, 23 insertions(+)
23
24
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/watchdog/wdt_aspeed.h
27
+++ b/include/hw/watchdog/wdt_aspeed.h
28
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedWDTState {
29
MemoryRegion iomem;
30
uint32_t regs[ASPEED_WDT_REGS_MAX];
31
32
+ AspeedSCUState *scu;
33
uint32_t pclk_freq;
34
uint32_t silicon_rev;
35
uint32_t ext_pulse_width_mask;
36
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/arm/aspeed_soc.c
39
+++ b/hw/arm/aspeed_soc.c
40
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
41
sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
42
qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev",
43
sc->info->silicon_rev);
44
+ object_property_add_const_link(OBJECT(&s->wdt[i]), "scu",
45
+ OBJECT(&s->scu), &error_abort);
46
}
47
48
for (i = 0; i < ASPEED_MACS_NUM; i++) {
49
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
50
index XXXXXXX..XXXXXXX 100644
51
--- a/hw/watchdog/wdt_aspeed.c
52
+++ b/hw/watchdog/wdt_aspeed.c
53
@@ -XXX,XX +XXX,XX @@
54
55
#define WDT_RESTART_MAGIC 0x4755
56
57
+#define SCU_RESET_CONTROL1 (0x04 / 4)
58
+#define SCU_RESET_SDRAM BIT(0)
59
+
60
static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)
61
{
62
return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE;
63
@@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_timer_expired(void *dev)
64
{
65
AspeedWDTState *s = ASPEED_WDT(dev);
66
67
+ /* Do not reset on SDRAM controller reset */
68
+ if (s->scu->regs[SCU_RESET_CONTROL1] & SCU_RESET_SDRAM) {
69
+ timer_del(s->timer);
70
+ s->regs[WDT_CTRL] = 0;
71
+ return;
72
+ }
73
+
74
qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n");
75
watchdog_perform_action();
76
timer_del(s->timer);
77
@@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
78
{
79
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
80
AspeedWDTState *s = ASPEED_WDT(dev);
81
+ Error *err = NULL;
82
+ Object *obj;
83
+
84
+ obj = object_property_get_link(OBJECT(dev), "scu", &err);
85
+ if (!obj) {
86
+ error_propagate(errp, err);
87
+ error_prepend(errp, "required link 'scu' not found: ");
88
+ return;
89
+ }
90
+ s->scu = ASPEED_SCU(obj);
91
92
if (!is_supported_silicon_rev(s->silicon_rev)) {
93
error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
94
--
95
2.20.1
96
97
diff view generated by jsdifflib
1
From: Hongbo Zhang <hongbo.zhang@linaro.org>
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
Following the previous patch, this patch adds peripheral devices to the
3
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
4
newly introduced SBSA-ref machine.
4
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
5
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org>
6
Acked-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-id: 1561890034-15921-3-git-send-email-hongbo.zhang@linaro.org
7
Message-id: 20240305210444.310665-3-ines.varhol@telecom-paris.fr
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
9
---
11
hw/arm/sbsa-ref.c | 535 ++++++++++++++++++++++++++++++++++++++++++++++
10
include/hw/arm/stm32l4x5_soc.h | 2 +
12
1 file changed, 535 insertions(+)
11
include/hw/gpio/stm32l4x5_gpio.h | 1 +
13
12
include/hw/misc/stm32l4x5_syscfg.h | 3 +-
14
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
13
hw/arm/stm32l4x5_soc.c | 71 +++++++++++++++++++++++-------
15
index XXXXXXX..XXXXXXX 100644
14
hw/misc/stm32l4x5_syscfg.c | 1 +
16
--- a/hw/arm/sbsa-ref.c
15
hw/arm/Kconfig | 3 +-
17
+++ b/hw/arm/sbsa-ref.c
16
6 files changed, 63 insertions(+), 18 deletions(-)
18
@@ -XXX,XX +XXX,XX @@
17
19
*/
18
diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h
20
19
index XXXXXXX..XXXXXXX 100644
21
#include "qemu/osdep.h"
20
--- a/include/hw/arm/stm32l4x5_soc.h
22
+#include "qemu-common.h"
21
+++ b/include/hw/arm/stm32l4x5_soc.h
23
#include "qapi/error.h"
22
@@ -XXX,XX +XXX,XX @@
24
#include "qemu/error-report.h"
23
#include "hw/misc/stm32l4x5_syscfg.h"
25
#include "qemu/units.h"
24
#include "hw/misc/stm32l4x5_exti.h"
26
+#include "sysemu/device_tree.h"
25
#include "hw/misc/stm32l4x5_rcc.h"
27
#include "sysemu/numa.h"
26
+#include "hw/gpio/stm32l4x5_gpio.h"
27
#include "qom/object.h"
28
29
#define TYPE_STM32L4X5_SOC "stm32l4x5-soc"
30
@@ -XXX,XX +XXX,XX @@ struct Stm32l4x5SocState {
31
OrIRQState exti_or_gates[NUM_EXTI_OR_GATES];
32
Stm32l4x5SyscfgState syscfg;
33
Stm32l4x5RccState rcc;
34
+ Stm32l4x5GpioState gpio[NUM_GPIOS];
35
36
MemoryRegion sram1;
37
MemoryRegion sram2;
38
diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_gpio.h
39
index XXXXXXX..XXXXXXX 100644
40
--- a/include/hw/gpio/stm32l4x5_gpio.h
41
+++ b/include/hw/gpio/stm32l4x5_gpio.h
42
@@ -XXX,XX +XXX,XX @@
43
#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"
44
OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO)
45
46
+#define NUM_GPIOS 8
47
#define GPIO_NUM_PINS 16
48
49
struct Stm32l4x5GpioState {
50
diff --git a/include/hw/misc/stm32l4x5_syscfg.h b/include/hw/misc/stm32l4x5_syscfg.h
51
index XXXXXXX..XXXXXXX 100644
52
--- a/include/hw/misc/stm32l4x5_syscfg.h
53
+++ b/include/hw/misc/stm32l4x5_syscfg.h
54
@@ -XXX,XX +XXX,XX @@
55
56
#include "hw/sysbus.h"
57
#include "qom/object.h"
58
+#include "hw/gpio/stm32l4x5_gpio.h"
59
60
#define TYPE_STM32L4X5_SYSCFG "stm32l4x5-syscfg"
61
OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5SyscfgState, STM32L4X5_SYSCFG)
62
63
-#define NUM_GPIOS 8
64
-#define GPIO_NUM_PINS 16
65
#define SYSCFG_NUM_EXTICR 4
66
67
struct Stm32l4x5SyscfgState {
68
diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/arm/stm32l4x5_soc.c
71
+++ b/hw/arm/stm32l4x5_soc.c
72
@@ -XXX,XX +XXX,XX @@
28
#include "sysemu/sysemu.h"
73
#include "sysemu/sysemu.h"
29
#include "exec/address-spaces.h"
74
#include "hw/or-irq.h"
30
#include "exec/hwaddr.h"
75
#include "hw/arm/stm32l4x5_soc.h"
31
#include "kvm_arm.h"
76
+#include "hw/gpio/stm32l4x5_gpio.h"
32
#include "hw/arm/boot.h"
77
#include "hw/qdev-clock.h"
33
+#include "hw/block/flash.h"
78
#include "hw/misc/unimp.h"
34
#include "hw/boards.h"
79
35
+#include "hw/ide/internal.h"
80
@@ -XXX,XX +XXX,XX @@ static const int exti_or_gate1_lines_in[EXTI_OR_GATE1_NUM_LINES_IN] = {
36
+#include "hw/ide/ahci_internal.h"
81
16, 35, 36, 37, 38,
37
#include "hw/intc/arm_gicv3_common.h"
38
+#include "hw/loader.h"
39
+#include "hw/pci-host/gpex.h"
40
+#include "hw/usb.h"
41
+#include "net/net.h"
42
43
#define RAMLIMIT_GB 8192
44
#define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
45
46
+#define NUM_IRQS 256
47
+#define NUM_SMMU_IRQS 4
48
+#define NUM_SATA_PORTS 6
49
+
50
+#define VIRTUAL_PMU_IRQ 7
51
+#define ARCH_GIC_MAINT_IRQ 9
52
+#define ARCH_TIMER_VIRT_IRQ 11
53
+#define ARCH_TIMER_S_EL1_IRQ 13
54
+#define ARCH_TIMER_NS_EL1_IRQ 14
55
+#define ARCH_TIMER_NS_EL2_IRQ 10
56
+
57
enum {
58
SBSA_FLASH,
59
SBSA_MEM,
60
@@ -XXX,XX +XXX,XX @@ typedef struct {
61
void *fdt;
62
int fdt_size;
63
int psci_conduit;
64
+ PFlashCFI01 *flash[2];
65
} SBSAMachineState;
66
67
#define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref")
68
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry sbsa_ref_memmap[] = {
69
[SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES },
70
};
82
};
71
83
72
+static const int sbsa_ref_irqmap[] = {
84
+static const struct {
73
+ [SBSA_UART] = 1,
85
+ uint32_t addr;
74
+ [SBSA_RTC] = 2,
86
+ uint32_t moder_reset;
75
+ [SBSA_PCIE] = 3, /* ... to 6 */
87
+ uint32_t ospeedr_reset;
76
+ [SBSA_GPIO] = 7,
88
+ uint32_t pupdr_reset;
77
+ [SBSA_SECURE_UART] = 8,
89
+} stm32l4x5_gpio_cfg[NUM_GPIOS] = {
78
+ [SBSA_SECURE_UART_MM] = 9,
90
+ { 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 },
79
+ [SBSA_AHCI] = 10,
91
+ { 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 },
80
+ [SBSA_EHCI] = 11,
92
+ { 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
93
+ { 0x48000C00, 0xFFFFFFFF, 0x00000000, 0x00000000 },
94
+ { 0x48001000, 0xFFFFFFFF, 0x00000000, 0x00000000 },
95
+ { 0x48001400, 0xFFFFFFFF, 0x00000000, 0x00000000 },
96
+ { 0x48001800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
97
+ { 0x48001C00, 0x0000000F, 0x00000000, 0x00000000 },
81
+};
98
+};
82
+
99
+
83
+/*
100
static void stm32l4x5_soc_initfn(Object *obj)
84
+ * Firmware on this machine only uses ACPI table to load OS, these limited
101
{
85
+ * device tree nodes are just to let firmware know the info which varies from
102
Stm32l4x5SocState *s = STM32L4X5_SOC(obj);
86
+ * command line parameters, so it is not necessary to be fully compatible
103
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_initfn(Object *obj)
87
+ * with the kernel CPU and NUMA binding rules.
104
}
88
+ */
105
object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSCFG);
89
+static void create_fdt(SBSAMachineState *sms)
106
object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32L4X5_RCC);
90
+{
107
+
91
+ void *fdt = create_device_tree(&sms->fdt_size);
108
+ for (unsigned i = 0; i < NUM_GPIOS; i++) {
92
+ const MachineState *ms = MACHINE(sms);
109
+ g_autofree char *name = g_strdup_printf("gpio%c", 'a' + i);
93
+ int cpu;
110
+ object_initialize_child(obj, name, &s->gpio[i], TYPE_STM32L4X5_GPIO);
94
+
95
+ if (!fdt) {
96
+ error_report("create_device_tree() failed");
97
+ exit(1);
98
+ }
111
+ }
99
+
112
}
100
+ sms->fdt = fdt;
113
101
+
114
static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
102
+ qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref");
115
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
103
+ qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
116
Stm32l4x5SocState *s = STM32L4X5_SOC(dev_soc);
104
+ qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
117
const Stm32l4x5SocClass *sc = STM32L4X5_SOC_GET_CLASS(dev_soc);
105
+
118
MemoryRegion *system_memory = get_system_memory();
106
+ if (have_numa_distance) {
119
- DeviceState *armv7m;
107
+ int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
120
+ DeviceState *armv7m, *dev;
108
+ uint32_t *matrix = g_malloc0(size);
121
SysBusDevice *busdev;
109
+ int idx, i, j;
122
+ uint32_t pin_index;
110
+
123
111
+ for (i = 0; i < nb_numa_nodes; i++) {
124
if (!memory_region_init_rom(&s->flash, OBJECT(dev_soc), "flash",
112
+ for (j = 0; j < nb_numa_nodes; j++) {
125
sc->flash_size, errp)) {
113
+ idx = (i * nb_numa_nodes + j) * 3;
126
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
114
+ matrix[idx + 0] = cpu_to_be32(i);
127
return;
115
+ matrix[idx + 1] = cpu_to_be32(j);
128
}
116
+ matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]);
129
117
+ }
130
+ /* GPIOs */
131
+ for (unsigned i = 0; i < NUM_GPIOS; i++) {
132
+ g_autofree char *name = g_strdup_printf("%c", 'A' + i);
133
+ dev = DEVICE(&s->gpio[i]);
134
+ qdev_prop_set_string(dev, "name", name);
135
+ qdev_prop_set_uint32(dev, "mode-reset",
136
+ stm32l4x5_gpio_cfg[i].moder_reset);
137
+ qdev_prop_set_uint32(dev, "ospeed-reset",
138
+ stm32l4x5_gpio_cfg[i].ospeedr_reset);
139
+ qdev_prop_set_uint32(dev, "pupd-reset",
140
+ stm32l4x5_gpio_cfg[i].pupdr_reset);
141
+ busdev = SYS_BUS_DEVICE(&s->gpio[i]);
142
+ g_free(name);
143
+ name = g_strdup_printf("gpio%c-out", 'a' + i);
144
+ qdev_connect_clock_in(DEVICE(&s->gpio[i]), "clk",
145
+ qdev_get_clock_out(DEVICE(&(s->rcc)), name));
146
+ if (!sysbus_realize(busdev, errp)) {
147
+ return;
118
+ }
148
+ }
119
+
149
+ sysbus_mmio_map(busdev, 0, stm32l4x5_gpio_cfg[i].addr);
120
+ qemu_fdt_add_subnode(fdt, "/distance-map");
121
+ qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
122
+ matrix, size);
123
+ g_free(matrix);
124
+ }
150
+ }
125
+
151
+
126
+ qemu_fdt_add_subnode(sms->fdt, "/cpus");
152
/* System configuration controller */
127
+
153
busdev = SYS_BUS_DEVICE(&s->syscfg);
128
+ for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) {
154
if (!sysbus_realize(busdev, errp)) {
129
+ char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
155
return;
130
+ ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
156
}
131
+ CPUState *cs = CPU(armcpu);
157
sysbus_mmio_map(busdev, 0, SYSCFG_ADDR);
132
+
158
- /*
133
+ qemu_fdt_add_subnode(sms->fdt, nodename);
159
- * TODO: when the GPIO device is implemented, connect it
134
+
160
- * to SYCFG using `qdev_connect_gpio_out`, NUM_GPIOS and
135
+ if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
161
- * GPIO_NUM_PINS.
136
+ qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id",
162
- */
137
+ ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
163
+
138
+ }
164
+ for (unsigned i = 0; i < NUM_GPIOS; i++) {
139
+
165
+ for (unsigned j = 0; j < GPIO_NUM_PINS; j++) {
140
+ g_free(nodename);
166
+ pin_index = GPIO_NUM_PINS * i + j;
141
+ }
167
+ qdev_connect_gpio_out(DEVICE(&s->gpio[i]), j,
142
+}
168
+ qdev_get_gpio_in(DEVICE(&s->syscfg),
143
+
169
+ pin_index));
144
+#define SBSA_FLASH_SECTOR_SIZE (256 * KiB)
145
+
146
+static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms,
147
+ const char *name,
148
+ const char *alias_prop_name)
149
+{
150
+ /*
151
+ * Create a single flash device. We use the same parameters as
152
+ * the flash devices on the Versatile Express board.
153
+ */
154
+ DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
155
+
156
+ qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE);
157
+ qdev_prop_set_uint8(dev, "width", 4);
158
+ qdev_prop_set_uint8(dev, "device-width", 2);
159
+ qdev_prop_set_bit(dev, "big-endian", false);
160
+ qdev_prop_set_uint16(dev, "id0", 0x89);
161
+ qdev_prop_set_uint16(dev, "id1", 0x18);
162
+ qdev_prop_set_uint16(dev, "id2", 0x00);
163
+ qdev_prop_set_uint16(dev, "id3", 0x00);
164
+ qdev_prop_set_string(dev, "name", name);
165
+ object_property_add_child(OBJECT(sms), name, OBJECT(dev),
166
+ &error_abort);
167
+ object_property_add_alias(OBJECT(sms), alias_prop_name,
168
+ OBJECT(dev), "drive", &error_abort);
169
+ return PFLASH_CFI01(dev);
170
+}
171
+
172
+static void sbsa_flash_create(SBSAMachineState *sms)
173
+{
174
+ sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0");
175
+ sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1");
176
+}
177
+
178
+static void sbsa_flash_map1(PFlashCFI01 *flash,
179
+ hwaddr base, hwaddr size,
180
+ MemoryRegion *sysmem)
181
+{
182
+ DeviceState *dev = DEVICE(flash);
183
+
184
+ assert(size % SBSA_FLASH_SECTOR_SIZE == 0);
185
+ assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX);
186
+ qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE);
187
+ qdev_init_nofail(dev);
188
+
189
+ memory_region_add_subregion(sysmem, base,
190
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
191
+ 0));
192
+}
193
+
194
+static void sbsa_flash_map(SBSAMachineState *sms,
195
+ MemoryRegion *sysmem,
196
+ MemoryRegion *secure_sysmem)
197
+{
198
+ /*
199
+ * Map two flash devices to fill the SBSA_FLASH space in the memmap.
200
+ * sysmem is the system memory space. secure_sysmem is the secure view
201
+ * of the system, and the first flash device should be made visible only
202
+ * there. The second flash device is visible to both secure and nonsecure.
203
+ * If sysmem == secure_sysmem this means there is no separate Secure
204
+ * address space and both flash devices are generally visible.
205
+ */
206
+ hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2;
207
+ hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base;
208
+
209
+ sbsa_flash_map1(sms->flash[0], flashbase, flashsize,
210
+ secure_sysmem);
211
+ sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize,
212
+ sysmem);
213
+}
214
+
215
+static bool sbsa_firmware_init(SBSAMachineState *sms,
216
+ MemoryRegion *sysmem,
217
+ MemoryRegion *secure_sysmem)
218
+{
219
+ int i;
220
+ BlockBackend *pflash_blk0;
221
+
222
+ /* Map legacy -drive if=pflash to machine properties */
223
+ for (i = 0; i < ARRAY_SIZE(sms->flash); i++) {
224
+ pflash_cfi01_legacy_drive(sms->flash[i],
225
+ drive_get(IF_PFLASH, 0, i));
226
+ }
227
+
228
+ sbsa_flash_map(sms, sysmem, secure_sysmem);
229
+
230
+ pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]);
231
+
232
+ if (bios_name) {
233
+ char *fname;
234
+ MemoryRegion *mr;
235
+ int image_size;
236
+
237
+ if (pflash_blk0) {
238
+ error_report("The contents of the first flash device may be "
239
+ "specified with -bios or with -drive if=pflash... "
240
+ "but you cannot use both options at once");
241
+ exit(1);
242
+ }
243
+
244
+ /* Fall back to -bios */
245
+
246
+ fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
247
+ if (!fname) {
248
+ error_report("Could not find ROM image '%s'", bios_name);
249
+ exit(1);
250
+ }
251
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0);
252
+ image_size = load_image_mr(fname, mr);
253
+ g_free(fname);
254
+ if (image_size < 0) {
255
+ error_report("Could not load ROM image '%s'", bios_name);
256
+ exit(1);
257
+ }
170
+ }
258
+ }
171
+ }
259
+
172
260
+ return pflash_blk0 || bios_name;
173
/* EXTI device */
261
+}
174
busdev = SYS_BUS_DEVICE(&s->exti);
262
+
175
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
263
+static void create_secure_ram(SBSAMachineState *sms,
176
}
264
+ MemoryRegion *secure_sysmem)
177
}
265
+{
178
266
+ MemoryRegion *secram = g_new(MemoryRegion, 1);
179
- for (unsigned i = 0; i < 16; i++) {
267
+ hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base;
180
+ for (unsigned i = 0; i < GPIO_NUM_PINS; i++) {
268
+ hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size;
181
qdev_connect_gpio_out(DEVICE(&s->syscfg), i,
269
+
182
qdev_get_gpio_in(DEVICE(&s->exti), i));
270
+ memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size,
183
}
271
+ &error_fatal);
184
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
272
+ memory_region_add_subregion(secure_sysmem, base, secram);
185
/* RESERVED: 0x40024400, 0x7FDBC00 */
273
+}
186
274
+
187
/* AHB2 BUS */
275
+static void create_gic(SBSAMachineState *sms, qemu_irq *pic)
188
- create_unimplemented_device("GPIOA", 0x48000000, 0x400);
276
+{
189
- create_unimplemented_device("GPIOB", 0x48000400, 0x400);
277
+ DeviceState *gicdev;
190
- create_unimplemented_device("GPIOC", 0x48000800, 0x400);
278
+ SysBusDevice *gicbusdev;
191
- create_unimplemented_device("GPIOD", 0x48000C00, 0x400);
279
+ const char *gictype;
192
- create_unimplemented_device("GPIOE", 0x48001000, 0x400);
280
+ uint32_t redist0_capacity, redist0_count;
193
- create_unimplemented_device("GPIOF", 0x48001400, 0x400);
281
+ int i;
194
- create_unimplemented_device("GPIOG", 0x48001800, 0x400);
282
+
195
- create_unimplemented_device("GPIOH", 0x48001C00, 0x400);
283
+ gictype = gicv3_class_name();
196
/* RESERVED: 0x48002000, 0x7FDBC00 */
284
+
197
create_unimplemented_device("OTG_FS", 0x50000000, 0x40000);
285
+ gicdev = qdev_create(NULL, gictype);
198
create_unimplemented_device("ADC", 0x50040000, 0x400);
286
+ qdev_prop_set_uint32(gicdev, "revision", 3);
199
diff --git a/hw/misc/stm32l4x5_syscfg.c b/hw/misc/stm32l4x5_syscfg.c
287
+ qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
200
index XXXXXXX..XXXXXXX 100644
288
+ /*
201
--- a/hw/misc/stm32l4x5_syscfg.c
289
+ * Note that the num-irq property counts both internal and external
202
+++ b/hw/misc/stm32l4x5_syscfg.c
290
+ * interrupts; there are always 32 of the former (mandated by GIC spec).
203
@@ -XXX,XX +XXX,XX @@
291
+ */
204
#include "hw/irq.h"
292
+ qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
205
#include "migration/vmstate.h"
293
+ qdev_prop_set_bit(gicdev, "has-security-extensions", true);
206
#include "hw/misc/stm32l4x5_syscfg.h"
294
+
207
+#include "hw/gpio/stm32l4x5_gpio.h"
295
+ redist0_capacity =
208
296
+ sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
209
#define SYSCFG_MEMRMP 0x00
297
+ redist0_count = MIN(smp_cpus, redist0_capacity);
210
#define SYSCFG_CFGR1 0x04
298
+
211
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
299
+ qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1);
212
index XXXXXXX..XXXXXXX 100644
300
+ qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count);
213
--- a/hw/arm/Kconfig
301
+
214
+++ b/hw/arm/Kconfig
302
+ qdev_init_nofail(gicdev);
215
@@ -XXX,XX +XXX,XX @@ config STM32L4X5_SOC
303
+ gicbusdev = SYS_BUS_DEVICE(gicdev);
216
bool
304
+ sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
217
select ARM_V7M
305
+ sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base);
218
select OR_IRQ
306
+
219
- select STM32L4X5_SYSCFG
307
+ /*
220
select STM32L4X5_EXTI
308
+ * Wire the outputs from each CPU's generic timer and the GICv3
221
+ select STM32L4X5_SYSCFG
309
+ * maintenance interrupt signal to the appropriate GIC PPI inputs,
222
select STM32L4X5_RCC
310
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
223
+ select STM32L4X5_GPIO
311
+ */
224
312
+ for (i = 0; i < smp_cpus; i++) {
225
config XLNX_ZYNQMP_ARM
313
+ DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
226
bool
314
+ int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
315
+ int irq;
316
+ /*
317
+ * Mapping from the output timer irq lines from the CPU to the
318
+ * GIC PPI inputs used for this board.
319
+ */
320
+ const int timer_irq[] = {
321
+ [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
322
+ [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
323
+ [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
324
+ [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
325
+ };
326
+
327
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
328
+ qdev_connect_gpio_out(cpudev, irq,
329
+ qdev_get_gpio_in(gicdev,
330
+ ppibase + timer_irq[irq]));
331
+ }
332
+
333
+ qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
334
+ qdev_get_gpio_in(gicdev, ppibase
335
+ + ARCH_GIC_MAINT_IRQ));
336
+ qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
337
+ qdev_get_gpio_in(gicdev, ppibase
338
+ + VIRTUAL_PMU_IRQ));
339
+
340
+ sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
341
+ sysbus_connect_irq(gicbusdev, i + smp_cpus,
342
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
343
+ sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
344
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
345
+ sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
346
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
347
+ }
348
+
349
+ for (i = 0; i < NUM_IRQS; i++) {
350
+ pic[i] = qdev_get_gpio_in(gicdev, i);
351
+ }
352
+}
353
+
354
+static void create_uart(const SBSAMachineState *sms, qemu_irq *pic, int uart,
355
+ MemoryRegion *mem, Chardev *chr)
356
+{
357
+ hwaddr base = sbsa_ref_memmap[uart].base;
358
+ int irq = sbsa_ref_irqmap[uart];
359
+ DeviceState *dev = qdev_create(NULL, "pl011");
360
+ SysBusDevice *s = SYS_BUS_DEVICE(dev);
361
+
362
+ qdev_prop_set_chr(dev, "chardev", chr);
363
+ qdev_init_nofail(dev);
364
+ memory_region_add_subregion(mem, base,
365
+ sysbus_mmio_get_region(s, 0));
366
+ sysbus_connect_irq(s, 0, pic[irq]);
367
+}
368
+
369
+static void create_rtc(const SBSAMachineState *sms, qemu_irq *pic)
370
+{
371
+ hwaddr base = sbsa_ref_memmap[SBSA_RTC].base;
372
+ int irq = sbsa_ref_irqmap[SBSA_RTC];
373
+
374
+ sysbus_create_simple("pl031", base, pic[irq]);
375
+}
376
+
377
+static DeviceState *gpio_key_dev;
378
+static void sbsa_ref_powerdown_req(Notifier *n, void *opaque)
379
+{
380
+ /* use gpio Pin 3 for power button event */
381
+ qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
382
+}
383
+
384
+static Notifier sbsa_ref_powerdown_notifier = {
385
+ .notify = sbsa_ref_powerdown_req
386
+};
387
+
388
+static void create_gpio(const SBSAMachineState *sms, qemu_irq *pic)
389
+{
390
+ DeviceState *pl061_dev;
391
+ hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base;
392
+ int irq = sbsa_ref_irqmap[SBSA_GPIO];
393
+
394
+ pl061_dev = sysbus_create_simple("pl061", base, pic[irq]);
395
+
396
+ gpio_key_dev = sysbus_create_simple("gpio-key", -1,
397
+ qdev_get_gpio_in(pl061_dev, 3));
398
+
399
+ /* connect powerdown request */
400
+ qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier);
401
+}
402
+
403
+static void create_ahci(const SBSAMachineState *sms, qemu_irq *pic)
404
+{
405
+ hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base;
406
+ int irq = sbsa_ref_irqmap[SBSA_AHCI];
407
+ DeviceState *dev;
408
+ DriveInfo *hd[NUM_SATA_PORTS];
409
+ SysbusAHCIState *sysahci;
410
+ AHCIState *ahci;
411
+ int i;
412
+
413
+ dev = qdev_create(NULL, "sysbus-ahci");
414
+ qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS);
415
+ qdev_init_nofail(dev);
416
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
417
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irq]);
418
+
419
+ sysahci = SYSBUS_AHCI(dev);
420
+ ahci = &sysahci->ahci;
421
+ ide_drive_get(hd, ARRAY_SIZE(hd));
422
+ for (i = 0; i < ahci->ports; i++) {
423
+ if (hd[i] == NULL) {
424
+ continue;
425
+ }
426
+ ide_create_drive(&ahci->dev[i].port, 0, hd[i]);
427
+ }
428
+}
429
+
430
+static void create_ehci(const SBSAMachineState *sms, qemu_irq *pic)
431
+{
432
+ hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base;
433
+ int irq = sbsa_ref_irqmap[SBSA_EHCI];
434
+
435
+ sysbus_create_simple("platform-ehci-usb", base, pic[irq]);
436
+}
437
+
438
+static void create_smmu(const SBSAMachineState *sms, qemu_irq *pic,
439
+ PCIBus *bus)
440
+{
441
+ hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base;
442
+ int irq = sbsa_ref_irqmap[SBSA_SMMU];
443
+ DeviceState *dev;
444
+ int i;
445
+
446
+ dev = qdev_create(NULL, "arm-smmuv3");
447
+
448
+ object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
449
+ &error_abort);
450
+ qdev_init_nofail(dev);
451
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
452
+ for (i = 0; i < NUM_SMMU_IRQS; i++) {
453
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
454
+ }
455
+}
456
+
457
+static void create_pcie(SBSAMachineState *sms, qemu_irq *pic)
458
+{
459
+ hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base;
460
+ hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size;
461
+ hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base;
462
+ hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size;
463
+ hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base;
464
+ hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size;
465
+ hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base;
466
+ int irq = sbsa_ref_irqmap[SBSA_PCIE];
467
+ MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg;
468
+ MemoryRegion *ecam_alias, *ecam_reg;
469
+ DeviceState *dev;
470
+ PCIHostState *pci;
471
+ int i;
472
+
473
+ dev = qdev_create(NULL, TYPE_GPEX_HOST);
474
+ qdev_init_nofail(dev);
475
+
476
+ /* Map ECAM space */
477
+ ecam_alias = g_new0(MemoryRegion, 1);
478
+ ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
479
+ memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
480
+ ecam_reg, 0, size_ecam);
481
+ memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
482
+
483
+ /* Map the MMIO space */
484
+ mmio_alias = g_new0(MemoryRegion, 1);
485
+ mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
486
+ memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
487
+ mmio_reg, base_mmio, size_mmio);
488
+ memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
489
+
490
+ /* Map the MMIO_HIGH space */
491
+ mmio_alias_high = g_new0(MemoryRegion, 1);
492
+ memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high",
493
+ mmio_reg, base_mmio_high, size_mmio_high);
494
+ memory_region_add_subregion(get_system_memory(), base_mmio_high,
495
+ mmio_alias_high);
496
+
497
+ /* Map IO port space */
498
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
499
+
500
+ for (i = 0; i < GPEX_NUM_IRQS; i++) {
501
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
502
+ gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
503
+ }
504
+
505
+ pci = PCI_HOST_BRIDGE(dev);
506
+ if (pci->bus) {
507
+ for (i = 0; i < nb_nics; i++) {
508
+ NICInfo *nd = &nd_table[i];
509
+
510
+ if (!nd->model) {
511
+ nd->model = g_strdup("e1000e");
512
+ }
513
+
514
+ pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
515
+ }
516
+ }
517
+
518
+ pci_create_simple(pci->bus, -1, "VGA");
519
+
520
+ create_smmu(sms, pic, pci->bus);
521
+}
522
+
523
+static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size)
524
+{
525
+ const SBSAMachineState *board = container_of(binfo, SBSAMachineState,
526
+ bootinfo);
527
+
528
+ *fdt_size = board->fdt_size;
529
+ return board->fdt;
530
+}
531
+
532
static void sbsa_ref_init(MachineState *machine)
533
{
534
SBSAMachineState *sms = SBSA_MACHINE(machine);
535
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
536
MemoryRegion *sysmem = get_system_memory();
537
MemoryRegion *secure_sysmem = NULL;
538
MemoryRegion *ram = g_new(MemoryRegion, 1);
539
+ bool firmware_loaded;
540
const CPUArchIdList *possible_cpus;
541
int n, sbsa_max_cpus;
542
+ qemu_irq pic[NUM_IRQS];
543
544
if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) {
545
error_report("sbsa-ref: CPU type other than the built-in "
546
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
547
exit(1);
548
}
549
550
+ /*
551
+ * The Secure view of the world is the same as the NonSecure,
552
+ * but with a few extra devices. Create it as a container region
553
+ * containing the system memory at low priority; any secure-only
554
+ * devices go in at higher priority and take precedence.
555
+ */
556
+ secure_sysmem = g_new(MemoryRegion, 1);
557
+ memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
558
+ UINT64_MAX);
559
+ memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
560
+
561
+ firmware_loaded = sbsa_firmware_init(sms, sysmem,
562
+ secure_sysmem ?: sysmem);
563
+
564
+ if (machine->kernel_filename && firmware_loaded) {
565
+ error_report("sbsa-ref: No fw_cfg device on this machine, "
566
+ "so -kernel option is not supported when firmware loaded, "
567
+ "please load OS from hard disk instead");
568
+ exit(1);
569
+ }
570
+
571
/*
572
* This machine has EL3 enabled, external firmware should supply PSCI
573
* implementation, so the QEMU's internal PSCI is disabled.
574
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
575
machine->ram_size);
576
memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, ram);
577
578
+ create_fdt(sms);
579
+
580
+ create_secure_ram(sms, secure_sysmem);
581
+
582
+ create_gic(sms, pic);
583
+
584
+ create_uart(sms, pic, SBSA_UART, sysmem, serial_hd(0));
585
+ create_uart(sms, pic, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
586
+ /* Second secure UART for RAS and MM from EL0 */
587
+ create_uart(sms, pic, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2));
588
+
589
+ create_rtc(sms, pic);
590
+
591
+ create_gpio(sms, pic);
592
+
593
+ create_ahci(sms, pic);
594
+
595
+ create_ehci(sms, pic);
596
+
597
+ create_pcie(sms, pic);
598
+
599
sms->bootinfo.ram_size = machine->ram_size;
600
sms->bootinfo.kernel_filename = machine->kernel_filename;
601
sms->bootinfo.nb_cpus = smp_cpus;
602
sms->bootinfo.board_id = -1;
603
sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base;
604
+ sms->bootinfo.get_dtb = sbsa_ref_dtb;
605
+ sms->bootinfo.firmware_loaded = firmware_loaded;
606
arm_load_kernel(ARM_CPU(first_cpu), &sms->bootinfo);
607
}
608
609
@@ -XXX,XX +XXX,XX @@ sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx)
610
return idx % nb_numa_nodes;
611
}
612
613
+static void sbsa_ref_instance_init(Object *obj)
614
+{
615
+ SBSAMachineState *sms = SBSA_MACHINE(obj);
616
+
617
+ sbsa_flash_create(sms);
618
+}
619
+
620
static void sbsa_ref_class_init(ObjectClass *oc, void *data)
621
{
622
MachineClass *mc = MACHINE_CLASS(oc);
623
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_class_init(ObjectClass *oc, void *data)
624
static const TypeInfo sbsa_ref_info = {
625
.name = TYPE_SBSA_MACHINE,
626
.parent = TYPE_MACHINE,
627
+ .instance_init = sbsa_ref_instance_init,
628
.class_init = sbsa_ref_class_init,
629
.instance_size = sizeof(SBSAMachineState),
630
};
631
--
227
--
632
2.20.1
228
2.34.1
633
229
634
230
diff view generated by jsdifflib
1
From: Hongbo Zhang <hongbo.zhang@linaro.org>
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
For AArch64, the existing "virt" machine is primarily meant to
3
The testcase contains :
4
run on KVM and execute virtualization workloads, but we need an
4
- `test_idr_reset_value()` :
5
environment as faithful as possible to physical hardware, for supporting
5
Checks the reset values of MODER, OTYPER, PUPDR, ODR and IDR.
6
firmware and OS development for physical Aarch64 machines.
6
- `test_gpio_output_mode()` :
7
Checks that writing a bit in register ODR results in the corresponding
8
pin rising or lowering, if this pin is configured in output mode.
9
- `test_gpio_input_mode()` :
10
Checks that a input pin set high or low externally results
11
in the pin rising and lowering.
12
- `test_pull_up_pull_down()` :
13
Checks that a floating pin in pull-up/down mode is actually high/down.
14
- `test_push_pull()` :
15
Checks that a pin set externally is disconnected when configured in
16
push-pull output mode, and can't be set externally while in this mode.
17
- `test_open_drain()` :
18
Checks that a pin set externally high is disconnected when configured
19
in open-drain output mode, and can't be set high while in this mode.
20
- `test_bsrr_brr()` :
21
Checks that writing to BSRR and BRR has the desired result in ODR.
22
- `test_clock_enable()` :
23
Checks that GPIO clock is at the right frequency after enabling it.
7
24
8
This patch introduces new machine type 'sbsa-ref' with main features:
25
Acked-by: Thomas Huth <thuth@redhat.com>
9
- Based on 'virt' machine type.
26
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
10
- A new memory map.
27
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
11
- CPU type cortex-a57.
28
Message-id: 20240305210444.310665-4-ines.varhol@telecom-paris.fr
12
- EL2 and EL3 are enabled.
13
- GIC version 3.
14
- System bus AHCI controller.
15
- System bus EHCI controller.
16
- CDROM and hard disc on AHCI bus.
17
- E1000E ethernet card on PCIE bus.
18
- VGA display adaptor on PCIE bus.
19
- No virtio devices.
20
- No fw_cfg device.
21
- No ACPI table supplied.
22
- Only minimal device tree nodes.
23
24
Arm Trusted Firmware and UEFI porting to this are done accordingly,
25
and the firmware should supply ACPI tables to the guest OS. The
26
minimal device tree nodes supplied by QEMU for this platform are only
27
to pass the dynamic info reflecting command line input to firmware,
28
not for loading the guest OS.
29
30
To make the review easier, this task is split into two patches, the
31
fundamental skeleton part and the peripheral devices part; this patch is
32
the first part.
33
34
Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org>
35
Message-id: 1561890034-15921-2-git-send-email-hongbo.zhang@linaro.org
36
[PMM: commit message tweaks; moved some bits between patch 1 and 2
37
to ensure patch 1 builds cleanly; removed unneeded lines from
38
Kconfig stanza; only provide board for qemu-system-aarch64, not
39
qemu-system-arm; added MAINTAINERS entry]
40
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
41
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
42
---
30
---
43
hw/arm/Makefile.objs | 1 +
31
tests/qtest/stm32l4x5_gpio-test.c | 551 ++++++++++++++++++++++++++++++
44
hw/arm/sbsa-ref.c | 271 ++++++++++++++++++++++++++++
32
tests/qtest/meson.build | 3 +-
45
MAINTAINERS | 8 +
33
2 files changed, 553 insertions(+), 1 deletion(-)
46
default-configs/aarch64-softmmu.mak | 1 +
34
create mode 100644 tests/qtest/stm32l4x5_gpio-test.c
47
hw/arm/Kconfig | 14 ++
48
5 files changed, 295 insertions(+)
49
create mode 100644 hw/arm/sbsa-ref.c
50
35
51
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
36
diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio-test.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/arm/Makefile.objs
54
+++ b/hw/arm/Makefile.objs
55
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_SPITZ) += spitz.o
56
obj-$(CONFIG_TOSA) += tosa.o
57
obj-$(CONFIG_Z2) += z2.o
58
obj-$(CONFIG_REALVIEW) += realview.o
59
+obj-$(CONFIG_SBSA_REF) += sbsa-ref.o
60
obj-$(CONFIG_STELLARIS) += stellaris.o
61
obj-$(CONFIG_COLLIE) += collie.o
62
obj-$(CONFIG_VERSATILE) += versatilepb.o
63
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
64
new file mode 100644
37
new file mode 100644
65
index XXXXXXX..XXXXXXX
38
index XXXXXXX..XXXXXXX
66
--- /dev/null
39
--- /dev/null
67
+++ b/hw/arm/sbsa-ref.c
40
+++ b/tests/qtest/stm32l4x5_gpio-test.c
68
@@ -XXX,XX +XXX,XX @@
41
@@ -XXX,XX +XXX,XX @@
69
+/*
42
+/*
70
+ * ARM SBSA Reference Platform emulation
43
+ * QTest testcase for STM32L4x5_GPIO
71
+ *
44
+ *
72
+ * Copyright (c) 2018 Linaro Limited
45
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
73
+ * Written by Hongbo Zhang <hongbo.zhang@linaro.org>
46
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
74
+ *
47
+ *
75
+ * This program is free software; you can redistribute it and/or modify it
48
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
76
+ * under the terms and conditions of the GNU General Public License,
49
+ * See the COPYING file in the top-level directory.
77
+ * version 2 or later, as published by the Free Software Foundation.
78
+ *
79
+ * This program is distributed in the hope it will be useful, but WITHOUT
80
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
81
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
82
+ * more details.
83
+ *
84
+ * You should have received a copy of the GNU General Public License along with
85
+ * this program. If not, see <http://www.gnu.org/licenses/>.
86
+ */
50
+ */
87
+
51
+
88
+#include "qemu/osdep.h"
52
+#include "qemu/osdep.h"
89
+#include "qapi/error.h"
53
+#include "libqtest-single.h"
90
+#include "qemu/error-report.h"
54
+
91
+#include "qemu/units.h"
55
+#define GPIO_BASE_ADDR 0x48000000
92
+#include "sysemu/numa.h"
56
+#define GPIO_SIZE 0x400
93
+#include "sysemu/sysemu.h"
57
+#define NUM_GPIOS 8
94
+#include "exec/address-spaces.h"
58
+#define NUM_GPIO_PINS 16
95
+#include "exec/hwaddr.h"
59
+
96
+#include "kvm_arm.h"
60
+#define GPIO_A 0x48000000
97
+#include "hw/arm/boot.h"
61
+#define GPIO_B 0x48000400
98
+#include "hw/boards.h"
62
+#define GPIO_C 0x48000800
99
+#include "hw/intc/arm_gicv3_common.h"
63
+#define GPIO_D 0x48000C00
100
+
64
+#define GPIO_E 0x48001000
101
+#define RAMLIMIT_GB 8192
65
+#define GPIO_F 0x48001400
102
+#define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
66
+#define GPIO_G 0x48001800
103
+
67
+#define GPIO_H 0x48001C00
104
+enum {
68
+
105
+ SBSA_FLASH,
69
+#define MODER 0x00
106
+ SBSA_MEM,
70
+#define OTYPER 0x04
107
+ SBSA_CPUPERIPHS,
71
+#define PUPDR 0x0C
108
+ SBSA_GIC_DIST,
72
+#define IDR 0x10
109
+ SBSA_GIC_REDIST,
73
+#define ODR 0x14
110
+ SBSA_SMMU,
74
+#define BSRR 0x18
111
+ SBSA_UART,
75
+#define BRR 0x28
112
+ SBSA_RTC,
76
+
113
+ SBSA_PCIE,
77
+#define MODER_INPUT 0
114
+ SBSA_PCIE_MMIO,
78
+#define MODER_OUTPUT 1
115
+ SBSA_PCIE_MMIO_HIGH,
79
+
116
+ SBSA_PCIE_PIO,
80
+#define PUPDR_NONE 0
117
+ SBSA_PCIE_ECAM,
81
+#define PUPDR_PULLUP 1
118
+ SBSA_GPIO,
82
+#define PUPDR_PULLDOWN 2
119
+ SBSA_SECURE_UART,
83
+
120
+ SBSA_SECURE_UART_MM,
84
+#define OTYPER_PUSH_PULL 0
121
+ SBSA_SECURE_MEM,
85
+#define OTYPER_OPEN_DRAIN 1
122
+ SBSA_AHCI,
86
+
123
+ SBSA_EHCI,
87
+const uint32_t moder_reset[NUM_GPIOS] = {
88
+ 0xABFFFFFF,
89
+ 0xFFFFFEBF,
90
+ 0xFFFFFFFF,
91
+ 0xFFFFFFFF,
92
+ 0xFFFFFFFF,
93
+ 0xFFFFFFFF,
94
+ 0xFFFFFFFF,
95
+ 0x0000000F
124
+};
96
+};
125
+
97
+
126
+typedef struct MemMapEntry {
98
+const uint32_t pupdr_reset[NUM_GPIOS] = {
127
+ hwaddr base;
99
+ 0x64000000,
128
+ hwaddr size;
100
+ 0x00000100,
129
+} MemMapEntry;
101
+ 0x00000000,
130
+
102
+ 0x00000000,
131
+typedef struct {
103
+ 0x00000000,
132
+ MachineState parent;
104
+ 0x00000000,
133
+ struct arm_boot_info bootinfo;
105
+ 0x00000000,
134
+ int smp_cpus;
106
+ 0x00000000
135
+ void *fdt;
136
+ int fdt_size;
137
+ int psci_conduit;
138
+} SBSAMachineState;
139
+
140
+#define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref")
141
+#define SBSA_MACHINE(obj) \
142
+ OBJECT_CHECK(SBSAMachineState, (obj), TYPE_SBSA_MACHINE)
143
+
144
+static const MemMapEntry sbsa_ref_memmap[] = {
145
+ /* 512M boot ROM */
146
+ [SBSA_FLASH] = { 0, 0x20000000 },
147
+ /* 512M secure memory */
148
+ [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 },
149
+ /* Space reserved for CPU peripheral devices */
150
+ [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 },
151
+ [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 },
152
+ [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 },
153
+ [SBSA_UART] = { 0x60000000, 0x00001000 },
154
+ [SBSA_RTC] = { 0x60010000, 0x00001000 },
155
+ [SBSA_GPIO] = { 0x60020000, 0x00001000 },
156
+ [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 },
157
+ [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 },
158
+ [SBSA_SMMU] = { 0x60050000, 0x00020000 },
159
+ /* Space here reserved for more SMMUs */
160
+ [SBSA_AHCI] = { 0x60100000, 0x00010000 },
161
+ [SBSA_EHCI] = { 0x60110000, 0x00010000 },
162
+ /* Space here reserved for other devices */
163
+ [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 },
164
+ /* 32-bit address PCIE MMIO space */
165
+ [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 },
166
+ /* 256M PCIE ECAM space */
167
+ [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 },
168
+ /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */
169
+ [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL },
170
+ [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES },
171
+};
107
+};
172
+
108
+
173
+static void sbsa_ref_init(MachineState *machine)
109
+const uint32_t idr_reset[NUM_GPIOS] = {
174
+{
110
+ 0x0000A000,
175
+ SBSAMachineState *sms = SBSA_MACHINE(machine);
111
+ 0x00000010,
176
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
112
+ 0x00000000,
177
+ MemoryRegion *sysmem = get_system_memory();
113
+ 0x00000000,
178
+ MemoryRegion *secure_sysmem = NULL;
114
+ 0x00000000,
179
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
115
+ 0x00000000,
180
+ const CPUArchIdList *possible_cpus;
116
+ 0x00000000,
181
+ int n, sbsa_max_cpus;
117
+ 0x00000000
182
+
118
+};
183
+ if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) {
119
+
184
+ error_report("sbsa-ref: CPU type other than the built-in "
120
+static uint32_t gpio_readl(unsigned int gpio, unsigned int offset)
185
+ "cortex-a57 not supported");
121
+{
186
+ exit(1);
122
+ return readl(gpio + offset);
123
+}
124
+
125
+static void gpio_writel(unsigned int gpio, unsigned int offset, uint32_t value)
126
+{
127
+ writel(gpio + offset, value);
128
+}
129
+
130
+static void gpio_set_bit(unsigned int gpio, unsigned int reg,
131
+ unsigned int pin, uint32_t value)
132
+{
133
+ uint32_t mask = 0xFFFFFFFF & ~(0x1 << pin);
134
+ gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << pin);
135
+}
136
+
137
+static void gpio_set_2bits(unsigned int gpio, unsigned int reg,
138
+ unsigned int pin, uint32_t value)
139
+{
140
+ uint32_t offset = 2 * pin;
141
+ uint32_t mask = 0xFFFFFFFF & ~(0x3 << offset);
142
+ gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << offset);
143
+}
144
+
145
+static unsigned int get_gpio_id(uint32_t gpio_addr)
146
+{
147
+ return (gpio_addr - GPIO_BASE_ADDR) / GPIO_SIZE;
148
+}
149
+
150
+static void gpio_set_irq(unsigned int gpio, int num, int level)
151
+{
152
+ g_autofree char *name = g_strdup_printf("/machine/soc/gpio%c",
153
+ get_gpio_id(gpio) + 'a');
154
+ qtest_set_irq_in(global_qtest, name, NULL, num, level);
155
+}
156
+
157
+static void disconnect_all_pins(unsigned int gpio)
158
+{
159
+ g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c",
160
+ get_gpio_id(gpio) + 'a');
161
+ QDict *r;
162
+
163
+ r = qtest_qmp(global_qtest, "{ 'execute': 'qom-set', 'arguments': "
164
+ "{ 'path': %s, 'property': 'disconnected-pins', 'value': %d } }",
165
+ path, 0xFFFF);
166
+ g_assert_false(qdict_haskey(r, "error"));
167
+ qobject_unref(r);
168
+}
169
+
170
+static uint32_t get_disconnected_pins(unsigned int gpio)
171
+{
172
+ g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c",
173
+ get_gpio_id(gpio) + 'a');
174
+ uint32_t disconnected_pins = 0;
175
+ QDict *r;
176
+
177
+ r = qtest_qmp(global_qtest, "{ 'execute': 'qom-get', 'arguments':"
178
+ " { 'path': %s, 'property': 'disconnected-pins'} }", path);
179
+ g_assert_false(qdict_haskey(r, "error"));
180
+ disconnected_pins = qdict_get_int(r, "return");
181
+ qobject_unref(r);
182
+ return disconnected_pins;
183
+}
184
+
185
+static uint32_t reset(uint32_t gpio, unsigned int offset)
186
+{
187
+ switch (offset) {
188
+ case MODER:
189
+ return moder_reset[get_gpio_id(gpio)];
190
+ case PUPDR:
191
+ return pupdr_reset[get_gpio_id(gpio)];
192
+ case IDR:
193
+ return idr_reset[get_gpio_id(gpio)];
187
+ }
194
+ }
188
+
195
+ return 0x0;
189
+ if (kvm_enabled()) {
196
+}
190
+ error_report("sbsa-ref: KVM is not supported for this machine");
197
+
191
+ exit(1);
198
+static void system_reset(void)
192
+ }
199
+{
193
+
200
+ QDict *r;
194
+ /*
201
+ r = qtest_qmp(global_qtest, "{'execute': 'system_reset'}");
195
+ * This machine has EL3 enabled, external firmware should supply PSCI
202
+ g_assert_false(qdict_haskey(r, "error"));
196
+ * implementation, so the QEMU's internal PSCI is disabled.
203
+ qobject_unref(r);
197
+ */
204
+}
198
+ sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
205
+
199
+
206
+static void test_idr_reset_value(void)
200
+ sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
207
+{
201
+
208
+ /*
202
+ if (max_cpus > sbsa_max_cpus) {
209
+ * Checks that the values in MODER, OTYPER, PUPDR and ODR
203
+ error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
210
+ * after reset are correct, and that the value in IDR is
204
+ "supported by machine 'sbsa-ref' (%d)",
211
+ * coherent.
205
+ max_cpus, sbsa_max_cpus);
212
+ * Since AF and analog modes aren't implemented, IDR reset
206
+ exit(1);
213
+ * values aren't the same as with a real board.
207
+ }
214
+ *
208
+
215
+ * Register IDR contains the actual values of all GPIO pins.
209
+ sms->smp_cpus = smp_cpus;
216
+ * Its value depends on the pins' configuration
210
+
217
+ * (intput/output/analog : register MODER, push-pull/open-drain :
211
+ if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) {
218
+ * register OTYPER, pull-up/pull-down/none : register PUPDR)
212
+ error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB);
219
+ * and on the values stored in register ODR
213
+ exit(1);
220
+ * (in case the pin is in output mode).
214
+ }
221
+ */
215
+
222
+
216
+ possible_cpus = mc->possible_cpu_arch_ids(machine);
223
+ gpio_writel(GPIO_A, MODER, 0xDEADBEEF);
217
+ for (n = 0; n < possible_cpus->len; n++) {
224
+ gpio_writel(GPIO_A, ODR, 0xDEADBEEF);
218
+ Object *cpuobj;
225
+ gpio_writel(GPIO_A, OTYPER, 0xDEADBEEF);
219
+ CPUState *cs;
226
+ gpio_writel(GPIO_A, PUPDR, 0xDEADBEEF);
220
+
227
+
221
+ if (n >= smp_cpus) {
228
+ gpio_writel(GPIO_B, MODER, 0xDEADBEEF);
222
+ break;
229
+ gpio_writel(GPIO_B, ODR, 0xDEADBEEF);
223
+ }
230
+ gpio_writel(GPIO_B, OTYPER, 0xDEADBEEF);
224
+
231
+ gpio_writel(GPIO_B, PUPDR, 0xDEADBEEF);
225
+ cpuobj = object_new(possible_cpus->cpus[n].type);
232
+
226
+ object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,
233
+ gpio_writel(GPIO_C, MODER, 0xDEADBEEF);
227
+ "mp-affinity", NULL);
234
+ gpio_writel(GPIO_C, ODR, 0xDEADBEEF);
228
+
235
+ gpio_writel(GPIO_C, OTYPER, 0xDEADBEEF);
229
+ cs = CPU(cpuobj);
236
+ gpio_writel(GPIO_C, PUPDR, 0xDEADBEEF);
230
+ cs->cpu_index = n;
237
+
231
+
238
+ gpio_writel(GPIO_H, MODER, 0xDEADBEEF);
232
+ numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
239
+ gpio_writel(GPIO_H, ODR, 0xDEADBEEF);
233
+ &error_fatal);
240
+ gpio_writel(GPIO_H, OTYPER, 0xDEADBEEF);
234
+
241
+ gpio_writel(GPIO_H, PUPDR, 0xDEADBEEF);
235
+ if (object_property_find(cpuobj, "reset-cbar", NULL)) {
242
+
236
+ object_property_set_int(cpuobj,
243
+ system_reset();
237
+ sbsa_ref_memmap[SBSA_CPUPERIPHS].base,
244
+
238
+ "reset-cbar", &error_abort);
245
+ uint32_t moder = gpio_readl(GPIO_A, MODER);
239
+ }
246
+ uint32_t odr = gpio_readl(GPIO_A, ODR);
240
+
247
+ uint32_t otyper = gpio_readl(GPIO_A, OTYPER);
241
+ object_property_set_link(cpuobj, OBJECT(sysmem), "memory",
248
+ uint32_t pupdr = gpio_readl(GPIO_A, PUPDR);
242
+ &error_abort);
249
+ uint32_t idr = gpio_readl(GPIO_A, IDR);
243
+
250
+ /* 15: AF, 14: AF, 13: AF, 12: Analog ... */
244
+ object_property_set_link(cpuobj, OBJECT(secure_sysmem),
251
+ /* here AF is the same as Analog and Input mode */
245
+ "secure-memory", &error_abort);
252
+ g_assert_cmphex(moder, ==, reset(GPIO_A, MODER));
246
+
253
+ g_assert_cmphex(odr, ==, reset(GPIO_A, ODR));
247
+ object_property_set_bool(cpuobj, true, "realized", &error_fatal);
254
+ g_assert_cmphex(otyper, ==, reset(GPIO_A, OTYPER));
248
+ object_unref(cpuobj);
255
+ /* 15: pull-up, 14: pull-down, 13: pull-up, 12: neither ... */
249
+ }
256
+ g_assert_cmphex(pupdr, ==, reset(GPIO_A, PUPDR));
250
+
257
+ /* 15 : 1, 14: 0, 13: 1, 12 : reset value ... */
251
+ memory_region_allocate_system_memory(ram, NULL, "sbsa-ref.ram",
258
+ g_assert_cmphex(idr, ==, reset(GPIO_A, IDR));
252
+ machine->ram_size);
259
+
253
+ memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, ram);
260
+ moder = gpio_readl(GPIO_B, MODER);
254
+
261
+ odr = gpio_readl(GPIO_B, ODR);
255
+ sms->bootinfo.ram_size = machine->ram_size;
262
+ otyper = gpio_readl(GPIO_B, OTYPER);
256
+ sms->bootinfo.kernel_filename = machine->kernel_filename;
263
+ pupdr = gpio_readl(GPIO_B, PUPDR);
257
+ sms->bootinfo.nb_cpus = smp_cpus;
264
+ idr = gpio_readl(GPIO_B, IDR);
258
+ sms->bootinfo.board_id = -1;
265
+ /* ... 5: Analog, 4: AF, 3: AF, 2: Analog ... */
259
+ sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base;
266
+ /* here AF is the same as Analog and Input mode */
260
+ arm_load_kernel(ARM_CPU(first_cpu), &sms->bootinfo);
267
+ g_assert_cmphex(moder, ==, reset(GPIO_B, MODER));
261
+}
268
+ g_assert_cmphex(odr, ==, reset(GPIO_B, ODR));
262
+
269
+ g_assert_cmphex(otyper, ==, reset(GPIO_B, OTYPER));
263
+static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
270
+ /* ... 5: neither, 4: pull-up, 3: neither ... */
264
+{
271
+ g_assert_cmphex(pupdr, ==, reset(GPIO_B, PUPDR));
265
+ uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
272
+ /* ... 5 : reset value, 4 : 1, 3 : reset value ... */
266
+ return arm_cpu_mp_affinity(idx, clustersz);
273
+ g_assert_cmphex(idr, ==, reset(GPIO_B, IDR));
267
+}
274
+
268
+
275
+ moder = gpio_readl(GPIO_C, MODER);
269
+static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms)
276
+ odr = gpio_readl(GPIO_C, ODR);
270
+{
277
+ otyper = gpio_readl(GPIO_C, OTYPER);
271
+ SBSAMachineState *sms = SBSA_MACHINE(ms);
278
+ pupdr = gpio_readl(GPIO_C, PUPDR);
272
+ int n;
279
+ idr = gpio_readl(GPIO_C, IDR);
273
+
280
+ /* Analog, same as Input mode*/
274
+ if (ms->possible_cpus) {
281
+ g_assert_cmphex(moder, ==, reset(GPIO_C, MODER));
275
+ assert(ms->possible_cpus->len == max_cpus);
282
+ g_assert_cmphex(odr, ==, reset(GPIO_C, ODR));
276
+ return ms->possible_cpus;
283
+ g_assert_cmphex(otyper, ==, reset(GPIO_C, OTYPER));
277
+ }
284
+ /* no pull-up or pull-down */
278
+
285
+ g_assert_cmphex(pupdr, ==, reset(GPIO_C, PUPDR));
279
+ ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
286
+ /* reset value */
280
+ sizeof(CPUArchId) * max_cpus);
287
+ g_assert_cmphex(idr, ==, reset(GPIO_C, IDR));
281
+ ms->possible_cpus->len = max_cpus;
288
+
282
+ for (n = 0; n < ms->possible_cpus->len; n++) {
289
+ moder = gpio_readl(GPIO_H, MODER);
283
+ ms->possible_cpus->cpus[n].type = ms->cpu_type;
290
+ odr = gpio_readl(GPIO_H, ODR);
284
+ ms->possible_cpus->cpus[n].arch_id =
291
+ otyper = gpio_readl(GPIO_H, OTYPER);
285
+ sbsa_ref_cpu_mp_affinity(sms, n);
292
+ pupdr = gpio_readl(GPIO_H, PUPDR);
286
+ ms->possible_cpus->cpus[n].props.has_thread_id = true;
293
+ idr = gpio_readl(GPIO_H, IDR);
287
+ ms->possible_cpus->cpus[n].props.thread_id = n;
294
+ /* Analog, same as Input mode */
288
+ }
295
+ g_assert_cmphex(moder, ==, reset(GPIO_H, MODER));
289
+ return ms->possible_cpus;
296
+ g_assert_cmphex(odr, ==, reset(GPIO_H, ODR));
290
+}
297
+ g_assert_cmphex(otyper, ==, reset(GPIO_H, OTYPER));
291
+
298
+ /* no pull-up or pull-down */
292
+static CpuInstanceProperties
299
+ g_assert_cmphex(pupdr, ==, reset(GPIO_H, PUPDR));
293
+sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
300
+ /* reset value */
294
+{
301
+ g_assert_cmphex(idr, ==, reset(GPIO_H, IDR));
295
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
302
+}
296
+ const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
303
+
297
+
304
+static void test_gpio_output_mode(const void *data)
298
+ assert(cpu_index < possible_cpus->len);
305
+{
299
+ return possible_cpus->cpus[cpu_index].props;
306
+ /*
300
+}
307
+ * Checks that setting a bit in ODR sets the corresponding
301
+
308
+ * GPIO line high : it should set the right bit in IDR
302
+static int64_t
309
+ * and send an irq to syscfg.
303
+sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx)
310
+ * Additionally, it checks that values written to ODR
304
+{
311
+ * when not in output mode are stored and not discarded.
305
+ return idx % nb_numa_nodes;
312
+ */
306
+}
313
+ unsigned int pin = ((uint64_t)data) & 0xF;
307
+
314
+ uint32_t gpio = ((uint64_t)data) >> 32;
308
+static void sbsa_ref_class_init(ObjectClass *oc, void *data)
315
+ unsigned int gpio_id = get_gpio_id(gpio);
309
+{
316
+
310
+ MachineClass *mc = MACHINE_CLASS(oc);
317
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
311
+
318
+
312
+ mc->init = sbsa_ref_init;
319
+ /* Set a bit in ODR and check nothing happens */
313
+ mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine";
320
+ gpio_set_bit(gpio, ODR, pin, 1);
314
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57");
321
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
315
+ mc->max_cpus = 512;
322
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
316
+ mc->pci_allow_0_address = true;
323
+
317
+ mc->minimum_page_bits = 12;
324
+ /* Configure the relevant line as output and check the pin is high */
318
+ mc->block_default_type = IF_IDE;
325
+ gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
319
+ mc->no_cdrom = 1;
326
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
320
+ mc->default_ram_size = 1 * GiB;
327
+ g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
321
+ mc->default_cpus = 4;
328
+
322
+ mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids;
329
+ /* Reset the bit in ODR and check the pin is low */
323
+ mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props;
330
+ gpio_set_bit(gpio, ODR, pin, 0);
324
+ mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id;
331
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
325
+}
332
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
326
+
333
+
327
+static const TypeInfo sbsa_ref_info = {
334
+ /* Clean the test */
328
+ .name = TYPE_SBSA_MACHINE,
335
+ gpio_writel(gpio, ODR, reset(gpio, ODR));
329
+ .parent = TYPE_MACHINE,
336
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
330
+ .class_init = sbsa_ref_class_init,
337
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
331
+ .instance_size = sizeof(SBSAMachineState),
338
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
332
+};
339
+}
333
+
340
+
334
+static void sbsa_ref_machine_init(void)
341
+static void test_gpio_input_mode(const void *data)
335
+{
342
+{
336
+ type_register_static(&sbsa_ref_info);
343
+ /*
337
+}
344
+ * Test that setting a line high/low externally sets the
338
+
345
+ * corresponding GPIO line high/low : it should set the
339
+type_init(sbsa_ref_machine_init);
346
+ * right bit in IDR and send an irq to syscfg.
340
diff --git a/MAINTAINERS b/MAINTAINERS
347
+ */
348
+ unsigned int pin = ((uint64_t)data) & 0xF;
349
+ uint32_t gpio = ((uint64_t)data) >> 32;
350
+ unsigned int gpio_id = get_gpio_id(gpio);
351
+
352
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
353
+
354
+ /* Configure a line as input, raise it, and check that the pin is high */
355
+ gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
356
+ gpio_set_irq(gpio, pin, 1);
357
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
358
+ g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
359
+
360
+ /* Lower the line and check that the pin is low */
361
+ gpio_set_irq(gpio, pin, 0);
362
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
363
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
364
+
365
+ /* Clean the test */
366
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
367
+ disconnect_all_pins(gpio);
368
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
369
+}
370
+
371
+static void test_pull_up_pull_down(const void *data)
372
+{
373
+ /*
374
+ * Test that a floating pin with pull-up sets the pin
375
+ * high and vice-versa.
376
+ */
377
+ unsigned int pin = ((uint64_t)data) & 0xF;
378
+ uint32_t gpio = ((uint64_t)data) >> 32;
379
+ unsigned int gpio_id = get_gpio_id(gpio);
380
+
381
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
382
+
383
+ /* Configure a line as input with pull-up, check the line is set high */
384
+ gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
385
+ gpio_set_2bits(gpio, PUPDR, pin, PUPDR_PULLUP);
386
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
387
+ g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
388
+
389
+ /* Configure the line with pull-down, check the line is low */
390
+ gpio_set_2bits(gpio, PUPDR, pin, PUPDR_PULLDOWN);
391
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
392
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
393
+
394
+ /* Clean the test */
395
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
396
+ gpio_writel(gpio, PUPDR, reset(gpio, PUPDR));
397
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
398
+}
399
+
400
+static void test_push_pull(const void *data)
401
+{
402
+ /*
403
+ * Test that configuring a line in push-pull output mode
404
+ * disconnects the pin, that the pin can't be set or reset
405
+ * externally afterwards.
406
+ */
407
+ unsigned int pin = ((uint64_t)data) & 0xF;
408
+ uint32_t gpio = ((uint64_t)data) >> 32;
409
+ uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
410
+
411
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
412
+
413
+ /* Setting a line high externally, configuring it in push-pull output */
414
+ /* And checking the pin was disconnected */
415
+ gpio_set_irq(gpio, pin, 1);
416
+ gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
417
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
418
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
419
+
420
+ /* Setting a line low externally, configuring it in push-pull output */
421
+ /* And checking the pin was disconnected */
422
+ gpio_set_irq(gpio2, pin, 0);
423
+ gpio_set_bit(gpio2, ODR, pin, 1);
424
+ gpio_set_2bits(gpio2, MODER, pin, MODER_OUTPUT);
425
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF);
426
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR) | (1 << pin));
427
+
428
+ /* Trying to set a push-pull output pin, checking it doesn't work */
429
+ gpio_set_irq(gpio, pin, 1);
430
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
431
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
432
+
433
+ /* Trying to reset a push-pull output pin, checking it doesn't work */
434
+ gpio_set_irq(gpio2, pin, 0);
435
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF);
436
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR) | (1 << pin));
437
+
438
+ /* Clean the test */
439
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
440
+ gpio_writel(gpio2, ODR, reset(gpio2, ODR));
441
+ gpio_writel(gpio2, MODER, reset(gpio2, MODER));
442
+}
443
+
444
+static void test_open_drain(const void *data)
445
+{
446
+ /*
447
+ * Test that configuring a line in open-drain output mode
448
+ * disconnects a pin set high externally and that the pin
449
+ * can't be set high externally while configured in open-drain.
450
+ *
451
+ * However a pin set low externally shouldn't be disconnected,
452
+ * and it can be set low externally when in open-drain mode.
453
+ */
454
+ unsigned int pin = ((uint64_t)data) & 0xF;
455
+ uint32_t gpio = ((uint64_t)data) >> 32;
456
+ uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
457
+
458
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
459
+
460
+ /* Setting a line high externally, configuring it in open-drain output */
461
+ /* And checking the pin was disconnected */
462
+ gpio_set_irq(gpio, pin, 1);
463
+ gpio_set_bit(gpio, OTYPER, pin, OTYPER_OPEN_DRAIN);
464
+ gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
465
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
466
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
467
+
468
+ /* Setting a line low externally, configuring it in open-drain output */
469
+ /* And checking the pin wasn't disconnected */
470
+ gpio_set_irq(gpio2, pin, 0);
471
+ gpio_set_bit(gpio2, ODR, pin, 1);
472
+ gpio_set_bit(gpio2, OTYPER, pin, OTYPER_OPEN_DRAIN);
473
+ gpio_set_2bits(gpio2, MODER, pin, MODER_OUTPUT);
474
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF & ~(1 << pin));
475
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==,
476
+ reset(gpio2, IDR) & ~(1 << pin));
477
+
478
+ /* Trying to set a open-drain output pin, checking it doesn't work */
479
+ gpio_set_irq(gpio, pin, 1);
480
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
481
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
482
+
483
+ /* Trying to reset a open-drain output pin, checking it works */
484
+ gpio_set_bit(gpio, ODR, pin, 1);
485
+ gpio_set_irq(gpio, pin, 0);
486
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF & ~(1 << pin));
487
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==,
488
+ reset(gpio2, IDR) & ~(1 << pin));
489
+
490
+ /* Clean the test */
491
+ disconnect_all_pins(gpio2);
492
+ gpio_writel(gpio2, OTYPER, reset(gpio2, OTYPER));
493
+ gpio_writel(gpio2, ODR, reset(gpio2, ODR));
494
+ gpio_writel(gpio2, MODER, reset(gpio2, MODER));
495
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR));
496
+ disconnect_all_pins(gpio);
497
+ gpio_writel(gpio, OTYPER, reset(gpio, OTYPER));
498
+ gpio_writel(gpio, ODR, reset(gpio, ODR));
499
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
500
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
501
+}
502
+
503
+static void test_bsrr_brr(const void *data)
504
+{
505
+ /*
506
+ * Test that writing a '1' in BSS and BSRR
507
+ * has the desired effect on ODR.
508
+ * In BSRR, BSx has priority over BRx.
509
+ */
510
+ unsigned int pin = ((uint64_t)data) & 0xF;
511
+ uint32_t gpio = ((uint64_t)data) >> 32;
512
+
513
+ gpio_writel(gpio, BSRR, (1 << pin));
514
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
515
+
516
+ gpio_writel(gpio, BSRR, (1 << (pin + NUM_GPIO_PINS)));
517
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
518
+
519
+ gpio_writel(gpio, BSRR, (1 << pin));
520
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
521
+
522
+ gpio_writel(gpio, BRR, (1 << pin));
523
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
524
+
525
+ /* BSx should have priority over BRx */
526
+ gpio_writel(gpio, BSRR, (1 << pin) | (1 << (pin + NUM_GPIO_PINS)));
527
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
528
+
529
+ gpio_writel(gpio, BRR, (1 << pin));
530
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
531
+
532
+ gpio_writel(gpio, ODR, reset(gpio, ODR));
533
+}
534
+
535
+int main(int argc, char **argv)
536
+{
537
+ int ret;
538
+
539
+ g_test_init(&argc, &argv, NULL);
540
+ g_test_set_nonfatal_assertions();
541
+ qtest_add_func("stm32l4x5/gpio/test_idr_reset_value",
542
+ test_idr_reset_value);
543
+ /*
544
+ * The inputs for the tests (gpio and pin) can be changed,
545
+ * but the tests don't work for pins that are high at reset
546
+ * (GPIOA15, GPIO13 and GPIOB5).
547
+ * Specifically, rising the pin then checking `get_irq()`
548
+ * is problematic since the pin was already high.
549
+ */
550
+ qtest_add_data_func("stm32l4x5/gpio/test_gpioc5_output_mode",
551
+ (void *)((uint64_t)GPIO_C << 32 | 5),
552
+ test_gpio_output_mode);
553
+ qtest_add_data_func("stm32l4x5/gpio/test_gpioh3_output_mode",
554
+ (void *)((uint64_t)GPIO_H << 32 | 3),
555
+ test_gpio_output_mode);
556
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode1",
557
+ (void *)((uint64_t)GPIO_D << 32 | 6),
558
+ test_gpio_input_mode);
559
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode2",
560
+ (void *)((uint64_t)GPIO_C << 32 | 10),
561
+ test_gpio_input_mode);
562
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down1",
563
+ (void *)((uint64_t)GPIO_B << 32 | 5),
564
+ test_pull_up_pull_down);
565
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down2",
566
+ (void *)((uint64_t)GPIO_F << 32 | 1),
567
+ test_pull_up_pull_down);
568
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull1",
569
+ (void *)((uint64_t)GPIO_G << 32 | 6),
570
+ test_push_pull);
571
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull2",
572
+ (void *)((uint64_t)GPIO_H << 32 | 3),
573
+ test_push_pull);
574
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain1",
575
+ (void *)((uint64_t)GPIO_C << 32 | 4),
576
+ test_open_drain);
577
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain2",
578
+ (void *)((uint64_t)GPIO_E << 32 | 11),
579
+ test_open_drain);
580
+ qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr1",
581
+ (void *)((uint64_t)GPIO_A << 32 | 12),
582
+ test_bsrr_brr);
583
+ qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr2",
584
+ (void *)((uint64_t)GPIO_D << 32 | 0),
585
+ test_bsrr_brr);
586
+
587
+ qtest_start("-machine b-l475e-iot01a");
588
+ ret = g_test_run();
589
+ qtest_end();
590
+
591
+ return ret;
592
+}
593
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
341
index XXXXXXX..XXXXXXX 100644
594
index XXXXXXX..XXXXXXX 100644
342
--- a/MAINTAINERS
595
--- a/tests/qtest/meson.build
343
+++ b/MAINTAINERS
596
+++ b/tests/qtest/meson.build
344
@@ -XXX,XX +XXX,XX @@ F: include/hw/arm/fsl-imx6.h
597
@@ -XXX,XX +XXX,XX @@ qtests_aspeed = \
345
F: include/hw/misc/imx6_*.h
598
qtests_stm32l4x5 = \
346
F: include/hw/ssi/imx_spi.h
599
['stm32l4x5_exti-test',
347
600
'stm32l4x5_syscfg-test',
348
+SBSA-REF
601
- 'stm32l4x5_rcc-test']
349
+M: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
602
+ 'stm32l4x5_rcc-test',
350
+M: Peter Maydell <peter.maydell@linaro.org>
603
+ 'stm32l4x5_gpio-test']
351
+R: Leif Lindholm <leif.lindholm@linaro.org>
604
352
+L: qemu-arm@nongnu.org
605
qtests_arm = \
353
+S: Maintained
606
(config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \
354
+F: hw/arm/sbsa-ref.c
355
+
356
Sharp SL-5500 (Collie) PDA
357
M: Peter Maydell <peter.maydell@linaro.org>
358
L: qemu-arm@nongnu.org
359
diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-softmmu.mak
360
index XXXXXXX..XXXXXXX 100644
361
--- a/default-configs/aarch64-softmmu.mak
362
+++ b/default-configs/aarch64-softmmu.mak
363
@@ -XXX,XX +XXX,XX @@ include arm-softmmu.mak
364
365
CONFIG_XLNX_ZYNQMP_ARM=y
366
CONFIG_XLNX_VERSAL=y
367
+CONFIG_SBSA_REF=y
368
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
369
index XXXXXXX..XXXXXXX 100644
370
--- a/hw/arm/Kconfig
371
+++ b/hw/arm/Kconfig
372
@@ -XXX,XX +XXX,XX @@ config REALVIEW
373
select DS1338 # I2C RTC+NVRAM
374
select USB_OHCI
375
376
+config SBSA_REF
377
+ bool
378
+ imply PCI_DEVICES
379
+ select AHCI
380
+ select ARM_SMMUV3
381
+ select GPIO_KEY
382
+ select PCI_EXPRESS
383
+ select PCI_EXPRESS_GENERIC_BRIDGE
384
+ select PFLASH_CFI01
385
+ select PL011 # UART
386
+ select PL031 # RTC
387
+ select PL061 # GPIO
388
+ select USB_EHCI_SYSBUS
389
+
390
config SABRELITE
391
bool
392
select FSL_IMX6
393
--
607
--
394
2.20.1
608
2.34.1
395
609
396
610
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
Group Aarch64 rules together, TCG related ones at the bottom.
4
This will help when restricting TCG-only objects.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20190701132516.26392-2-philmd@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/Makefile.objs | 5 +++--
12
1 file changed, 3 insertions(+), 2 deletions(-)
13
14
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/Makefile.objs
17
+++ b/target/arm/Makefile.objs
18
@@ -XXX,XX +XXX,XX @@ obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
19
obj-y += translate.o op_helper.o helper.o cpu.o
20
obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o vfp_helper.o
21
obj-y += gdbstub.o
22
-obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o
23
-obj-$(TARGET_AARCH64) += pauth_helper.o
24
+obj-$(TARGET_AARCH64) += cpu64.o gdbstub64.o
25
obj-y += crypto_helper.o
26
obj-$(CONFIG_SOFTMMU) += arm-powerctl.o
27
28
@@ -XXX,XX +XXX,XX @@ target/arm/translate-sve.o: target/arm/decode-sve.inc.c
29
target/arm/translate.o: target/arm/decode-vfp.inc.c
30
target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
31
32
+obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o
33
obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o
34
+obj-$(TARGET_AARCH64) += pauth_helper.o
35
--
36
2.20.1
37
38
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
Group ARM objects together, TCG related ones at the bottom.
4
This will help when restricting TCG-only objects.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20190701132516.26392-3-philmd@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/Makefile.objs | 10 ++++++----
12
1 file changed, 6 insertions(+), 4 deletions(-)
13
14
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/Makefile.objs
17
+++ b/target/arm/Makefile.objs
18
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_KVM) += kvm.o
19
obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o
20
obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o
21
obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
22
-obj-y += translate.o op_helper.o helper.o cpu.o
23
-obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o vfp_helper.o
24
-obj-y += gdbstub.o
25
+obj-y += helper.o vfp_helper.o
26
+obj-y += cpu.o gdbstub.o
27
obj-$(TARGET_AARCH64) += cpu64.o gdbstub64.o
28
-obj-y += crypto_helper.o
29
obj-$(CONFIG_SOFTMMU) += arm-powerctl.o
30
31
DECODETREE = $(SRC_PATH)/scripts/decodetree.py
32
@@ -XXX,XX +XXX,XX @@ target/arm/translate-sve.o: target/arm/decode-sve.inc.c
33
target/arm/translate.o: target/arm/decode-vfp.inc.c
34
target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
35
36
+obj-y += translate.o op_helper.o
37
+obj-y += crypto_helper.o
38
+obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
39
+
40
obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o
41
obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o
42
obj-$(TARGET_AARCH64) += pauth_helper.o
43
--
44
2.20.1
45
46
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
Group KVM rules together.
4
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-id: 20190701132516.26392-4-philmd@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/Makefile.objs | 9 +++++----
11
1 file changed, 5 insertions(+), 4 deletions(-)
12
13
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/Makefile.objs
16
+++ b/target/arm/Makefile.objs
17
@@ -XXX,XX +XXX,XX @@
18
obj-y += arm-semi.o
19
obj-$(CONFIG_SOFTMMU) += machine.o psci.o arch_dump.o monitor.o
20
-obj-$(CONFIG_KVM) += kvm.o
21
-obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o
22
-obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o
23
-obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
24
obj-y += helper.o vfp_helper.o
25
obj-y += cpu.o gdbstub.o
26
obj-$(TARGET_AARCH64) += cpu64.o gdbstub64.o
27
obj-$(CONFIG_SOFTMMU) += arm-powerctl.o
28
29
+obj-$(CONFIG_KVM) += kvm.o
30
+obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o
31
+obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o
32
+obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
33
+
34
DECODETREE = $(SRC_PATH)/scripts/decodetree.py
35
36
target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE)
37
--
38
2.20.1
39
40
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
Group SOFTMMU objects together.
4
Since PSCI is TCG specific, keep it separate.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20190701132516.26392-5-philmd@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/Makefile.objs | 5 ++++-
12
1 file changed, 4 insertions(+), 1 deletion(-)
13
14
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/Makefile.objs
17
+++ b/target/arm/Makefile.objs
18
@@ -XXX,XX +XXX,XX @@
19
obj-y += arm-semi.o
20
-obj-$(CONFIG_SOFTMMU) += machine.o psci.o arch_dump.o monitor.o
21
obj-y += helper.o vfp_helper.o
22
obj-y += cpu.o gdbstub.o
23
obj-$(TARGET_AARCH64) += cpu64.o gdbstub64.o
24
+
25
+obj-$(CONFIG_SOFTMMU) += machine.o arch_dump.o monitor.o
26
obj-$(CONFIG_SOFTMMU) += arm-powerctl.o
27
28
obj-$(CONFIG_KVM) += kvm.o
29
@@ -XXX,XX +XXX,XX @@ obj-y += translate.o op_helper.o
30
obj-y += crypto_helper.o
31
obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
32
33
+obj-$(CONFIG_SOFTMMU) += psci.o
34
+
35
obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o
36
obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o
37
obj-$(TARGET_AARCH64) += pauth_helper.o
38
--
39
2.20.1
40
41
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
Reviewed-by: Robert Bradford <robert.bradford@intel.com>
4
Reviewed-by: Samuel Ortiz <sameo@linux.intel.com>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-id: 20190701132516.26392-6-philmd@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/helper.c | 7 +++++++
11
1 file changed, 7 insertions(+)
12
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
16
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@
18
+/*
19
+ * ARM generic helpers.
20
+ *
21
+ * This code is licensed under the GNU GPL v2 or later.
22
+ *
23
+ * SPDX-License-Identifier: GPL-2.0-or-later
24
+ */
25
#include "qemu/osdep.h"
26
#include "qemu/units.h"
27
#include "target/arm/idau.h"
28
--
29
2.20.1
30
31
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Since commit 8c06fbdf36b checkpatch.pl enforce a new multiline
3
While the 8-bit input elements are sequential in the input vector,
4
comment syntax. Since we'll move this code around, fix its style
4
the 32-bit output elements are not sequential in the output matrix.
5
first.
5
Do not attempt to compute 2 32-bit outputs at the same time.
6
6
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Cc: qemu-stable@nongnu.org
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Fixes: 23a5e3859f5 ("target/arm: Implement SME integer outer product")
9
Message-id: 20190701132516.26392-8-philmd@redhat.com
9
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2083
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Message-id: 20240305163931.242795-1-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
14
---
12
target/arm/helper.c | 237 ++++++++++++++++++++++++++--------------
15
target/arm/tcg/sme_helper.c | 77 ++++++++++++++++++-------------
13
target/arm/op_helper.c | 54 ++++++---
16
tests/tcg/aarch64/sme-smopa-1.c | 47 +++++++++++++++++++
14
target/arm/vfp_helper.c | 3 +-
17
tests/tcg/aarch64/sme-smopa-2.c | 54 ++++++++++++++++++++++
15
3 files changed, 196 insertions(+), 98 deletions(-)
18
tests/tcg/aarch64/Makefile.target | 2 +-
16
19
4 files changed, 147 insertions(+), 33 deletions(-)
17
diff --git a/target/arm/helper.c b/target/arm/helper.c
20
create mode 100644 tests/tcg/aarch64/sme-smopa-1.c
21
create mode 100644 tests/tcg/aarch64/sme-smopa-2.c
22
23
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
18
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper.c
25
--- a/target/arm/tcg/sme_helper.c
20
+++ b/target/arm/helper.c
26
+++ b/target/arm/tcg/sme_helper.c
21
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr)
27
@@ -XXX,XX +XXX,XX @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn,
22
23
uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
24
{
25
- /* The TT instructions can be used by unprivileged code, but in
26
+ /*
27
+ * The TT instructions can be used by unprivileged code, but in
28
* user-only emulation we don't have the MPU.
29
* Luckily since we know we are NonSecure unprivileged (and that in
30
* turn means that the A flag wasn't specified), all the bits in the
31
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
32
return true;
33
34
pend_fault:
35
- /* By pending the exception at this point we are making
36
+ /*
37
+ * By pending the exception at this point we are making
38
* the IMPDEF choice "overridden exceptions pended" (see the
39
* MergeExcInfo() pseudocode). The other choice would be to not
40
* pend them now and then make a choice about which to throw away
41
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr,
42
return true;
43
44
pend_fault:
45
- /* By pending the exception at this point we are making
46
+ /*
47
+ * By pending the exception at this point we are making
48
* the IMPDEF choice "overridden exceptions pended" (see the
49
* MergeExcInfo() pseudocode). The other choice would be to not
50
* pend them now and then make a choice about which to throw away
51
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env)
52
*/
53
}
54
55
-/* Write to v7M CONTROL.SPSEL bit for the specified security bank.
56
+/*
57
+ * Write to v7M CONTROL.SPSEL bit for the specified security bank.
58
* This may change the current stack pointer between Main and Process
59
* stack pointers if it is done for the CONTROL register for the current
60
* security state.
61
@@ -XXX,XX +XXX,XX @@ static void write_v7m_control_spsel_for_secstate(CPUARMState *env,
62
}
28
}
63
}
29
}
64
30
65
-/* Write to v7M CONTROL.SPSEL bit. This may change the current
31
-typedef uint64_t IMOPFn(uint64_t, uint64_t, uint64_t, uint8_t, bool);
66
+/*
32
+typedef uint32_t IMOPFn32(uint32_t, uint32_t, uint32_t, uint8_t, bool);
67
+ * Write to v7M CONTROL.SPSEL bit. This may change the current
33
+static inline void do_imopa_s(uint32_t *za, uint32_t *zn, uint32_t *zm,
68
* stack pointer between Main and Process stack pointers.
34
+ uint8_t *pn, uint8_t *pm,
69
*/
35
+ uint32_t desc, IMOPFn32 *fn)
70
static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel)
36
+{
71
@@ -XXX,XX +XXX,XX @@ static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel)
37
+ intptr_t row, col, oprsz = simd_oprsz(desc) / 4;
72
38
+ bool neg = simd_data(desc);
73
void write_v7m_exception(CPUARMState *env, uint32_t new_exc)
39
40
-static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm,
41
- uint8_t *pn, uint8_t *pm,
42
- uint32_t desc, IMOPFn *fn)
43
+ for (row = 0; row < oprsz; ++row) {
44
+ uint8_t pa = (pn[H1(row >> 1)] >> ((row & 1) * 4)) & 0xf;
45
+ uint32_t *za_row = &za[tile_vslice_index(row)];
46
+ uint32_t n = zn[H4(row)];
47
+
48
+ for (col = 0; col < oprsz; ++col) {
49
+ uint8_t pb = pm[H1(col >> 1)] >> ((col & 1) * 4);
50
+ uint32_t *a = &za_row[H4(col)];
51
+
52
+ *a = fn(n, zm[H4(col)], *a, pa & pb, neg);
53
+ }
54
+ }
55
+}
56
+
57
+typedef uint64_t IMOPFn64(uint64_t, uint64_t, uint64_t, uint8_t, bool);
58
+static inline void do_imopa_d(uint64_t *za, uint64_t *zn, uint64_t *zm,
59
+ uint8_t *pn, uint8_t *pm,
60
+ uint32_t desc, IMOPFn64 *fn)
74
{
61
{
75
- /* Write a new value to v7m.exception, thus transitioning into or out
62
intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
76
+ /*
63
bool neg = simd_data(desc);
77
+ * Write a new value to v7m.exception, thus transitioning into or out
64
@@ -XXX,XX +XXX,XX @@ static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm,
78
* of Handler mode; this may result in a change of active stack pointer.
79
*/
80
bool new_is_psp, old_is_psp = v7m_using_psp(env);
81
@@ -XXX,XX +XXX,XX @@ static void switch_v7m_security_state(CPUARMState *env, bool new_secstate)
82
return;
83
}
84
85
- /* All the banked state is accessed by looking at env->v7m.secure
86
+ /*
87
+ * All the banked state is accessed by looking at env->v7m.secure
88
* except for the stack pointer; rearrange the SP appropriately.
89
*/
90
new_ss_msp = env->v7m.other_ss_msp;
91
@@ -XXX,XX +XXX,XX @@ static void switch_v7m_security_state(CPUARMState *env, bool new_secstate)
92
93
void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
94
{
95
- /* Handle v7M BXNS:
96
+ /*
97
+ * Handle v7M BXNS:
98
* - if the return value is a magic value, do exception return (like BX)
99
* - otherwise bit 0 of the return value is the target security state
100
*/
101
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
102
}
103
104
if (dest >= min_magic) {
105
- /* This is an exception return magic value; put it where
106
+ /*
107
+ * This is an exception return magic value; put it where
108
* do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.
109
* Note that if we ever add gen_ss_advance() singlestep support to
110
* M profile this should count as an "instruction execution complete"
111
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
112
113
void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
114
{
115
- /* Handle v7M BLXNS:
116
+ /*
117
+ * Handle v7M BLXNS:
118
* - bit 0 of the destination address is the target security state
119
*/
120
121
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
122
assert(env->v7m.secure);
123
124
if (dest & 1) {
125
- /* target is Secure, so this is just a normal BLX,
126
+ /*
127
+ * Target is Secure, so this is just a normal BLX,
128
* except that the low bit doesn't indicate Thumb/not.
129
*/
130
env->regs[14] = nextinst;
131
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
132
env->regs[13] = sp;
133
env->regs[14] = 0xfeffffff;
134
if (arm_v7m_is_handler_mode(env)) {
135
- /* Write a dummy value to IPSR, to avoid leaking the current secure
136
+ /*
137
+ * Write a dummy value to IPSR, to avoid leaking the current secure
138
* exception number to non-secure code. This is guaranteed not
139
* to cause write_v7m_exception() to actually change stacks.
140
*/
141
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
142
static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
143
bool spsel)
144
{
145
- /* Return a pointer to the location where we currently store the
146
+ /*
147
+ * Return a pointer to the location where we currently store the
148
* stack pointer for the requested security state and thread mode.
149
* This pointer will become invalid if the CPU state is updated
150
* such that the stack pointers are switched around (eg changing
151
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
152
153
mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, targets_secure, true);
154
155
- /* We don't do a get_phys_addr() here because the rules for vector
156
+ /*
157
+ * We don't do a get_phys_addr() here because the rules for vector
158
* loads are special: they always use the default memory map, and
159
* the default memory map permits reads from all addresses.
160
* Since there's no easy way to pass through to pmsav8_mpu_lookup()
161
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
162
return true;
163
164
load_fail:
165
- /* All vector table fetch fails are reported as HardFault, with
166
+ /*
167
+ * All vector table fetch fails are reported as HardFault, with
168
* HFSR.VECTTBL and .FORCED set. (FORCED is set because
169
* technically the underlying exception is a MemManage or BusFault
170
* that is escalated to HardFault.) This is a terminal exception,
171
@@ -XXX,XX +XXX,XX @@ static uint32_t v7m_integrity_sig(CPUARMState *env, uint32_t lr)
172
static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
173
bool ignore_faults)
174
{
175
- /* For v8M, push the callee-saves register part of the stack frame.
176
+ /*
177
+ * For v8M, push the callee-saves register part of the stack frame.
178
* Compare the v8M pseudocode PushCalleeStack().
179
* In the tailchaining case this may not be the current stack.
180
*/
181
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
182
return true;
183
}
184
185
- /* Write as much of the stack frame as we can. A write failure may
186
+ /*
187
+ * Write as much of the stack frame as we can. A write failure may
188
* cause us to pend a derived exception.
189
*/
190
sig = v7m_integrity_sig(env, lr);
191
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
192
static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
193
bool ignore_stackfaults)
194
{
195
- /* Do the "take the exception" parts of exception entry,
196
+ /*
197
+ * Do the "take the exception" parts of exception entry,
198
* but not the pushing of state to the stack. This is
199
* similar to the pseudocode ExceptionTaken() function.
200
*/
201
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
202
if (arm_feature(env, ARM_FEATURE_V8)) {
203
if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
204
(lr & R_V7M_EXCRET_S_MASK)) {
205
- /* The background code (the owner of the registers in the
206
+ /*
207
+ * The background code (the owner of the registers in the
208
* exception frame) is Secure. This means it may either already
209
* have or now needs to push callee-saves registers.
210
*/
211
if (targets_secure) {
212
if (dotailchain && !(lr & R_V7M_EXCRET_ES_MASK)) {
213
- /* We took an exception from Secure to NonSecure
214
+ /*
215
+ * We took an exception from Secure to NonSecure
216
* (which means the callee-saved registers got stacked)
217
* and are now tailchaining to a Secure exception.
218
* Clear DCRS so eventual return from this Secure
219
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
220
lr &= ~R_V7M_EXCRET_DCRS_MASK;
221
}
222
} else {
223
- /* We're going to a non-secure exception; push the
224
+ /*
225
+ * We're going to a non-secure exception; push the
226
* callee-saves registers to the stack now, if they're
227
* not already saved.
228
*/
229
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
230
lr |= R_V7M_EXCRET_SPSEL_MASK;
231
}
232
233
- /* Clear registers if necessary to prevent non-secure exception
234
+ /*
235
+ * Clear registers if necessary to prevent non-secure exception
236
* code being able to see register values from secure code.
237
* Where register values become architecturally UNKNOWN we leave
238
* them with their previous values.
239
*/
240
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
241
if (!targets_secure) {
242
- /* Always clear the caller-saved registers (they have been
243
+ /*
244
+ * Always clear the caller-saved registers (they have been
245
* pushed to the stack earlier in v7m_push_stack()).
246
* Clear callee-saved registers if the background code is
247
* Secure (in which case these regs were saved in
248
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
249
}
250
251
if (push_failed && !ignore_stackfaults) {
252
- /* Derived exception on callee-saves register stacking:
253
+ /*
254
+ * Derived exception on callee-saves register stacking:
255
* we might now want to take a different exception which
256
* targets a different security state, so try again from the top.
257
*/
258
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
259
return;
260
}
261
262
- /* Now we've done everything that might cause a derived exception
263
+ /*
264
+ * Now we've done everything that might cause a derived exception
265
* we can go ahead and activate whichever exception we're going to
266
* take (which might now be the derived exception).
267
*/
268
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr)
269
270
static bool v7m_push_stack(ARMCPU *cpu)
271
{
272
- /* Do the "set up stack frame" part of exception entry,
273
+ /*
274
+ * Do the "set up stack frame" part of exception entry,
275
* similar to pseudocode PushStack().
276
* Return true if we generate a derived exception (and so
277
* should ignore further stack faults trying to process
278
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_stack(ARMCPU *cpu)
279
}
280
}
281
282
- /* Write as much of the stack frame as we can. If we fail a stack
283
+ /*
284
+ * Write as much of the stack frame as we can. If we fail a stack
285
* write this will result in a derived exception being pended
286
* (which may be taken in preference to the one we started with
287
* if it has higher priority).
288
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
289
bool ftype;
290
bool restore_s16_s31;
291
292
- /* If we're not in Handler mode then jumps to magic exception-exit
293
+ /*
294
+ * If we're not in Handler mode then jumps to magic exception-exit
295
* addresses don't have magic behaviour. However for the v8M
296
* security extensions the magic secure-function-return has to
297
* work in thread mode too, so to avoid doing an extra check in
298
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
299
return;
300
}
301
302
- /* In the spec pseudocode ExceptionReturn() is called directly
303
+ /*
304
+ * In the spec pseudocode ExceptionReturn() is called directly
305
* from BXWritePC() and gets the full target PC value including
306
* bit zero. In QEMU's implementation we treat it as a normal
307
* jump-to-register (which is then caught later on), and so split
308
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
309
}
310
311
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
312
- /* EXC_RETURN.ES validation check (R_SMFL). We must do this before
313
+ /*
314
+ * EXC_RETURN.ES validation check (R_SMFL). We must do this before
315
* we pick which FAULTMASK to clear.
316
*/
317
if (!env->v7m.secure &&
318
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
319
}
320
321
if (env->v7m.exception != ARMV7M_EXCP_NMI) {
322
- /* Auto-clear FAULTMASK on return from other than NMI.
323
+ /*
324
+ * Auto-clear FAULTMASK on return from other than NMI.
325
* If the security extension is implemented then this only
326
* happens if the raw execution priority is >= 0; the
327
* value of the ES bit in the exception return value indicates
328
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
329
/* still an irq active now */
330
break;
331
case 1:
332
- /* we returned to base exception level, no nesting.
333
+ /*
334
+ * We returned to base exception level, no nesting.
335
* (In the pseudocode this is written using "NestedActivation != 1"
336
* where we have 'rettobase == false'.)
337
*/
338
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
339
340
if (arm_feature(env, ARM_FEATURE_V8)) {
341
if (!arm_feature(env, ARM_FEATURE_M_SECURITY)) {
342
- /* UNPREDICTABLE if S == 1 or DCRS == 0 or ES == 1 (R_XLCP);
343
+ /*
344
+ * UNPREDICTABLE if S == 1 or DCRS == 0 or ES == 1 (R_XLCP);
345
* we choose to take the UsageFault.
346
*/
347
if ((excret & R_V7M_EXCRET_S_MASK) ||
348
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
349
break;
350
case 13: /* Return to Thread using Process stack */
351
case 9: /* Return to Thread using Main stack */
352
- /* We only need to check NONBASETHRDENA for v7M, because in
353
+ /*
354
+ * We only need to check NONBASETHRDENA for v7M, because in
355
* v8M this bit does not exist (it is RES1).
356
*/
357
if (!rettobase &&
358
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
359
}
360
361
if (ufault) {
362
- /* Bad exception return: instead of popping the exception
363
+ /*
364
+ * Bad exception return: instead of popping the exception
365
* stack, directly take a usage fault on the current stack.
366
*/
367
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
368
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
369
switch_v7m_security_state(env, return_to_secure);
370
371
{
372
- /* The stack pointer we should be reading the exception frame from
373
+ /*
374
+ * The stack pointer we should be reading the exception frame from
375
* depends on bits in the magic exception return type value (and
376
* for v8M isn't necessarily the stack pointer we will eventually
377
* end up resuming execution with). Get a pointer to the location
378
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
379
v7m_stack_read(cpu, &xpsr, frameptr + 0x1c, mmu_idx);
380
381
if (!pop_ok) {
382
- /* v7m_stack_read() pended a fault, so take it (as a tail
383
+ /*
384
+ * v7m_stack_read() pended a fault, so take it (as a tail
385
* chained exception on the same stack frame)
386
*/
387
qemu_log_mask(CPU_LOG_INT, "...derived exception on unstacking\n");
388
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
389
return;
390
}
391
392
- /* Returning from an exception with a PC with bit 0 set is defined
393
+ /*
394
+ * Returning from an exception with a PC with bit 0 set is defined
395
* behaviour on v8M (bit 0 is ignored), but for v7M it was specified
396
* to be UNPREDICTABLE. In practice actual v7M hardware seems to ignore
397
* the lsbit, and there are several RTOSes out there which incorrectly
398
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
399
}
400
401
if (arm_feature(env, ARM_FEATURE_V8)) {
402
- /* For v8M we have to check whether the xPSR exception field
403
+ /*
404
+ * For v8M we have to check whether the xPSR exception field
405
* matches the EXCRET value for return to handler/thread
406
* before we commit to changing the SP and xPSR.
407
*/
408
bool will_be_handler = (xpsr & XPSR_EXCP) != 0;
409
if (return_to_handler != will_be_handler) {
410
- /* Take an INVPC UsageFault on the current stack.
411
+ /*
412
+ * Take an INVPC UsageFault on the current stack.
413
* By this point we will have switched to the security state
414
* for the background state, so this UsageFault will target
415
* that state.
416
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
417
frameptr += 0x40;
418
}
419
}
420
- /* Undo stack alignment (the SPREALIGN bit indicates that the original
421
+ /*
422
+ * Undo stack alignment (the SPREALIGN bit indicates that the original
423
* pre-exception SP was not 8-aligned and we added a padding word to
424
* align it, so we undo this by ORing in the bit that increases it
425
* from the current 8-aligned value to the 8-unaligned value. (Adding 4
426
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
427
V7M_CONTROL, SFPA, sfpa);
428
}
429
430
- /* The restored xPSR exception field will be zero if we're
431
+ /*
432
+ * The restored xPSR exception field will be zero if we're
433
* resuming in Thread mode. If that doesn't match what the
434
* exception return excret specified then this is a UsageFault.
435
* v7M requires we make this check here; v8M did it earlier.
436
*/
437
if (return_to_handler != arm_v7m_is_handler_mode(env)) {
438
- /* Take an INVPC UsageFault by pushing the stack again;
439
+ /*
440
+ * Take an INVPC UsageFault by pushing the stack again;
441
* we know we're v7M so this is never a Secure UsageFault.
442
*/
443
bool ignore_stackfaults;
444
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
445
446
static bool do_v7m_function_return(ARMCPU *cpu)
447
{
448
- /* v8M security extensions magic function return.
449
+ /*
450
+ * v8M security extensions magic function return.
451
* We may either:
452
* (1) throw an exception (longjump)
453
* (2) return true if we successfully handled the function return
454
@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
455
frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);
456
frameptr = *frame_sp_p;
457
458
- /* These loads may throw an exception (for MPU faults). We want to
459
+ /*
460
+ * These loads may throw an exception (for MPU faults). We want to
461
* do them as secure, so work out what MMU index that is.
462
*/
463
mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
464
@@ -XXX,XX +XXX,XX @@ static void arm_log_exception(int idx)
465
static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
466
uint32_t addr, uint16_t *insn)
467
{
468
- /* Load a 16-bit portion of a v7M instruction, returning true on success,
469
+ /*
470
+ * Load a 16-bit portion of a v7M instruction, returning true on success,
471
* or false on failure (in which case we will have pended the appropriate
472
* exception).
473
* We need to do the instruction fetch's MPU and SAU checks
474
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
475
476
v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
477
if (!sattrs.nsc || sattrs.ns) {
478
- /* This must be the second half of the insn, and it straddles a
479
+ /*
480
+ * This must be the second half of the insn, and it straddles a
481
* region boundary with the second half not being S&NSC.
482
*/
483
env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK;
484
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
485
486
static bool v7m_handle_execute_nsc(ARMCPU *cpu)
487
{
488
- /* Check whether this attempt to execute code in a Secure & NS-Callable
489
+ /*
490
+ * Check whether this attempt to execute code in a Secure & NS-Callable
491
* memory region is for an SG instruction; if so, then emulate the
492
* effect of the SG instruction and return true. Otherwise pend
493
* the correct kind of exception and return false.
494
@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
495
ARMMMUIdx mmu_idx;
496
uint16_t insn;
497
498
- /* We should never get here unless get_phys_addr_pmsav8() caused
499
+ /*
500
+ * We should never get here unless get_phys_addr_pmsav8() caused
501
* an exception for NS executing in S&NSC memory.
502
*/
503
assert(!env->v7m.secure);
504
@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
505
}
506
507
if (insn != 0xe97f) {
508
- /* Not an SG instruction first half (we choose the IMPDEF
509
+ /*
510
+ * Not an SG instruction first half (we choose the IMPDEF
511
* early-SG-check option).
512
*/
513
goto gen_invep;
514
@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
515
}
516
517
if (insn != 0xe97f) {
518
- /* Not an SG instruction second half (yes, both halves of the SG
519
+ /*
520
+ * Not an SG instruction second half (yes, both halves of the SG
521
* insn have the same hex value)
522
*/
523
goto gen_invep;
524
}
525
526
- /* OK, we have confirmed that we really have an SG instruction.
527
+ /*
528
+ * OK, we have confirmed that we really have an SG instruction.
529
* We know we're NS in S memory so don't need to repeat those checks.
530
*/
531
qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32
532
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
533
534
arm_log_exception(cs->exception_index);
535
536
- /* For exceptions we just mark as pending on the NVIC, and let that
537
- handle it. */
538
+ /*
539
+ * For exceptions we just mark as pending on the NVIC, and let that
540
+ * handle it.
541
+ */
542
switch (cs->exception_index) {
543
case EXCP_UDEF:
544
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
545
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
546
break;
547
case EXCP_PREFETCH_ABORT:
548
case EXCP_DATA_ABORT:
549
- /* Note that for M profile we don't have a guest facing FSR, but
550
+ /*
551
+ * Note that for M profile we don't have a guest facing FSR, but
552
* the env->exception.fsr will be populated by the code that
553
* raises the fault, in the A profile short-descriptor format.
554
*/
555
switch (env->exception.fsr & 0xf) {
556
case M_FAKE_FSR_NSC_EXEC:
557
- /* Exception generated when we try to execute code at an address
558
+ /*
559
+ * Exception generated when we try to execute code at an address
560
* which is marked as Secure & Non-Secure Callable and the CPU
561
* is in the Non-Secure state. The only instruction which can
562
* be executed like this is SG (and that only if both halves of
563
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
564
}
565
break;
566
case M_FAKE_FSR_SFAULT:
567
- /* Various flavours of SecureFault for attempts to execute or
568
+ /*
569
+ * Various flavours of SecureFault for attempts to execute or
570
* access data in the wrong security state.
571
*/
572
switch (cs->exception_index) {
573
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
574
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
575
break;
576
default:
577
- /* All other FSR values are either MPU faults or "can't happen
578
+ /*
579
+ * All other FSR values are either MPU faults or "can't happen
580
* for M profile" cases.
581
*/
582
switch (cs->exception_index) {
583
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
584
if (arm_feature(env, ARM_FEATURE_V8)) {
585
lr = R_V7M_EXCRET_RES1_MASK |
586
R_V7M_EXCRET_DCRS_MASK;
587
- /* The S bit indicates whether we should return to Secure
588
+ /*
589
+ * The S bit indicates whether we should return to Secure
590
* or NonSecure (ie our current state).
591
* The ES bit indicates whether we're taking this exception
592
* to Secure or NonSecure (ie our target state). We set it
593
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
594
v7m_exception_taken(cpu, lr, false, ignore_stackfaults);
595
}
65
}
596
66
597
-/* Function used to synchronize QEMU's AArch64 register set with AArch32
67
#define DEF_IMOP_32(NAME, NTYPE, MTYPE) \
598
+/*
68
-static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \
599
+ * Function used to synchronize QEMU's AArch64 register set with AArch32
69
+static uint32_t NAME(uint32_t n, uint32_t m, uint32_t a, uint8_t p, bool neg) \
600
* register set. This is necessary when switching between AArch32 and AArch64
70
{ \
601
* execution state.
71
- uint32_t sum0 = 0, sum1 = 0; \
602
*/
72
+ uint32_t sum = 0; \
603
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_32_to_64(CPUARMState *env)
73
/* Apply P to N as a mask, making the inactive elements 0. */ \
604
env->xregs[i] = env->regs[i];
74
n &= expand_pred_b(p); \
605
}
75
- sum0 += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \
606
76
- sum0 += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \
607
- /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
77
- sum0 += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \
608
+ /*
78
- sum0 += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \
609
+ * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
79
- sum1 += (NTYPE)(n >> 32) * (MTYPE)(m >> 32); \
610
* Otherwise, they come from the banked user regs.
80
- sum1 += (NTYPE)(n >> 40) * (MTYPE)(m >> 40); \
611
*/
81
- sum1 += (NTYPE)(n >> 48) * (MTYPE)(m >> 48); \
612
if (mode == ARM_CPU_MODE_FIQ) {
82
- sum1 += (NTYPE)(n >> 56) * (MTYPE)(m >> 56); \
613
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_32_to_64(CPUARMState *env)
83
- if (neg) { \
614
}
84
- sum0 = (uint32_t)a - sum0, sum1 = (uint32_t)(a >> 32) - sum1; \
615
}
85
- } else { \
616
86
- sum0 = (uint32_t)a + sum0, sum1 = (uint32_t)(a >> 32) + sum1; \
617
- /* Registers x13-x23 are the various mode SP and FP registers. Registers
87
- } \
618
+ /*
88
- return ((uint64_t)sum1 << 32) | sum0; \
619
+ * Registers x13-x23 are the various mode SP and FP registers. Registers
89
+ sum += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \
620
* r13 and r14 are only copied if we are in that mode, otherwise we copy
90
+ sum += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \
621
* from the mode banked register.
91
+ sum += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \
622
*/
92
+ sum += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \
623
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_32_to_64(CPUARMState *env)
93
+ return neg ? a - sum : a + sum; \
624
env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
625
}
626
627
- /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
628
+ /*
629
+ * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
630
* mode, then we can copy from r8-r14. Otherwise, we copy from the
631
* FIQ bank for r8-r14.
632
*/
633
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_32_to_64(CPUARMState *env)
634
env->pc = env->regs[15];
635
}
94
}
636
95
637
-/* Function used to synchronize QEMU's AArch32 register set with AArch64
96
#define DEF_IMOP_64(NAME, NTYPE, MTYPE) \
638
+/*
97
@@ -XXX,XX +XXX,XX @@ DEF_IMOP_64(umopa_d, uint16_t, uint16_t)
639
+ * Function used to synchronize QEMU's AArch32 register set with AArch64
98
DEF_IMOP_64(sumopa_d, int16_t, uint16_t)
640
* register set. This is necessary when switching between AArch32 and AArch64
99
DEF_IMOP_64(usmopa_d, uint16_t, int16_t)
641
* execution state.
100
642
*/
101
-#define DEF_IMOPH(NAME) \
643
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_64_to_32(CPUARMState *env)
102
- void HELPER(sme_##NAME)(void *vza, void *vzn, void *vzm, void *vpn, \
644
env->regs[i] = env->xregs[i];
103
- void *vpm, uint32_t desc) \
645
}
104
- { do_imopa(vza, vzn, vzm, vpn, vpm, desc, NAME); }
646
105
+#define DEF_IMOPH(NAME, S) \
647
- /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
106
+ void HELPER(sme_##NAME##_##S)(void *vza, void *vzn, void *vzm, \
648
+ /*
107
+ void *vpn, void *vpm, uint32_t desc) \
649
+ * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
108
+ { do_imopa_##S(vza, vzn, vzm, vpn, vpm, desc, NAME##_##S); }
650
* Otherwise, we copy x8-x12 into the banked user regs.
109
651
*/
110
-DEF_IMOPH(smopa_s)
652
if (mode == ARM_CPU_MODE_FIQ) {
111
-DEF_IMOPH(umopa_s)
653
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_64_to_32(CPUARMState *env)
112
-DEF_IMOPH(sumopa_s)
654
}
113
-DEF_IMOPH(usmopa_s)
655
}
114
-DEF_IMOPH(smopa_d)
656
115
-DEF_IMOPH(umopa_d)
657
- /* Registers r13 & r14 depend on the current mode.
116
-DEF_IMOPH(sumopa_d)
658
+ /*
117
-DEF_IMOPH(usmopa_d)
659
+ * Registers r13 & r14 depend on the current mode.
118
+DEF_IMOPH(smopa, s)
660
* If we are in a given mode, we copy the corresponding x registers to r13
119
+DEF_IMOPH(umopa, s)
661
* and r14. Otherwise, we copy the x register to the banked r13 and r14
120
+DEF_IMOPH(sumopa, s)
662
* for the mode.
121
+DEF_IMOPH(usmopa, s)
663
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_64_to_32(CPUARMState *env)
122
+
664
} else {
123
+DEF_IMOPH(smopa, d)
665
env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
124
+DEF_IMOPH(umopa, d)
666
125
+DEF_IMOPH(sumopa, d)
667
- /* HYP is an exception in that it does not have its own banked r14 but
126
+DEF_IMOPH(usmopa, d)
668
+ /*
127
diff --git a/tests/tcg/aarch64/sme-smopa-1.c b/tests/tcg/aarch64/sme-smopa-1.c
669
+ * HYP is an exception in that it does not have its own banked r14 but
128
new file mode 100644
670
* shares the USR r14
129
index XXXXXXX..XXXXXXX
671
*/
130
--- /dev/null
672
if (mode == ARM_CPU_MODE_HYP) {
131
+++ b/tests/tcg/aarch64/sme-smopa-1.c
673
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
132
@@ -XXX,XX +XXX,XX @@
674
return value;
133
+#include <stdio.h>
675
}
134
+#include <string.h>
676
case 0x94: /* CONTROL_NS */
135
+
677
- /* We have to handle this here because unprivileged Secure code
136
+int main()
678
+ /*
137
+{
679
+ * We have to handle this here because unprivileged Secure code
138
+ static const int cmp[4][4] = {
680
* can read the NS CONTROL register.
139
+ { 110, 134, 158, 182 },
681
*/
140
+ { 390, 478, 566, 654 },
682
if (!env->v7m.secure) {
141
+ { 670, 822, 974, 1126 },
683
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
142
+ { 950, 1166, 1382, 1598 }
684
return env->v7m.faultmask[M_REG_NS];
143
+ };
685
case 0x98: /* SP_NS */
144
+ int dst[4][4];
686
{
145
+ int *tmp = &dst[0][0];
687
- /* This gives the non-secure SP selected based on whether we're
146
+
688
+ /*
147
+ asm volatile(
689
+ * This gives the non-secure SP selected based on whether we're
148
+ ".arch armv8-r+sme\n\t"
690
* currently in handler mode or not, using the NS CONTROL.SPSEL.
149
+ "smstart\n\t"
691
*/
150
+ "index z0.b, #0, #1\n\t"
692
bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
151
+ "movprfx z1, z0\n\t"
693
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
152
+ "add z1.b, z1.b, #16\n\t"
694
153
+ "ptrue p0.b\n\t"
695
void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
154
+ "smopa za0.s, p0/m, p0/m, z0.b, z1.b\n\t"
696
{
155
+ "ptrue p0.s, vl4\n\t"
697
- /* We're passed bits [11..0] of the instruction; extract
156
+ "mov w12, #0\n\t"
698
+ /*
157
+ "st1w { za0h.s[w12, #0] }, p0, [%0]\n\t"
699
+ * We're passed bits [11..0] of the instruction; extract
158
+ "add %0, %0, #16\n\t"
700
* SYSm and the mask bits.
159
+ "st1w { za0h.s[w12, #1] }, p0, [%0]\n\t"
701
* Invalid combinations of SYSm and mask are UNPREDICTABLE;
160
+ "add %0, %0, #16\n\t"
702
* we choose to treat them as if the mask bits were valid.
161
+ "st1w { za0h.s[w12, #2] }, p0, [%0]\n\t"
703
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
162
+ "add %0, %0, #16\n\t"
704
return;
163
+ "st1w { za0h.s[w12, #3] }, p0, [%0]\n\t"
705
case 0x98: /* SP_NS */
164
+ "smstop"
706
{
165
+ : "+r"(tmp) : : "memory");
707
- /* This gives the non-secure SP selected based on whether we're
166
+
708
+ /*
167
+ if (memcmp(cmp, dst, sizeof(dst)) == 0) {
709
+ * This gives the non-secure SP selected based on whether we're
168
+ return 0;
710
* currently in handler mode or not, using the NS CONTROL.SPSEL.
169
+ }
711
*/
170
+
712
bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
171
+ /* See above for correct results. */
713
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
172
+ for (int i = 0; i < 4; ++i) {
714
bool targetsec = env->v7m.secure;
173
+ for (int j = 0; j < 4; ++j) {
715
bool is_subpage;
174
+ printf("%6d", dst[i][j]);
716
175
+ }
717
- /* Work out what the security state and privilege level we're
176
+ printf("\n");
718
+ /*
177
+ }
719
+ * Work out what the security state and privilege level we're
178
+ return 1;
720
* interested in is...
179
+}
721
*/
180
diff --git a/tests/tcg/aarch64/sme-smopa-2.c b/tests/tcg/aarch64/sme-smopa-2.c
722
if (alt) {
181
new file mode 100644
723
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
182
index XXXXXXX..XXXXXXX
724
/* ...and then figure out which MMU index this is */
183
--- /dev/null
725
mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, targetsec, targetpriv);
184
+++ b/tests/tcg/aarch64/sme-smopa-2.c
726
185
@@ -XXX,XX +XXX,XX @@
727
- /* We know that the MPU and SAU don't care about the access type
186
+#include <stdio.h>
728
+ /*
187
+#include <string.h>
729
+ * We know that the MPU and SAU don't care about the access type
188
+
730
* for our purposes beyond that we don't want to claim to be
189
+int main()
731
* an insn fetch, so we arbitrarily call this a read.
190
+{
732
*/
191
+ static const long cmp[4][4] = {
733
192
+ { 110, 134, 158, 182 },
734
- /* MPU region info only available for privileged or if
193
+ { 390, 478, 566, 654 },
735
+ /*
194
+ { 670, 822, 974, 1126 },
736
+ * MPU region info only available for privileged or if
195
+ { 950, 1166, 1382, 1598 }
737
* inspecting the other MPU state.
196
+ };
738
*/
197
+ long dst[4][4];
739
if (arm_current_el(env) != 0 || alt) {
198
+ long *tmp = &dst[0][0];
740
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
199
+ long svl;
741
200
+
742
void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
201
+ /* Validate that we have a wide enough vector for 4 elements. */
743
{
202
+ asm(".arch armv8-r+sme-i64\n\trdsvl %0, #1" : "=r"(svl));
744
- /* Implement DC ZVA, which zeroes a fixed-length block of memory.
203
+ if (svl < 32) {
745
+ /*
204
+ return 0;
746
+ * Implement DC ZVA, which zeroes a fixed-length block of memory.
205
+ }
747
* Note that we do not implement the (architecturally mandated)
206
+
748
* alignment fault for attempts to use this on Device memory
207
+ asm volatile(
749
* (which matches the usual QEMU behaviour of not implementing either
208
+ "smstart\n\t"
750
@@ -XXX,XX +XXX,XX @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
209
+ "index z0.h, #0, #1\n\t"
751
210
+ "movprfx z1, z0\n\t"
752
#ifndef CONFIG_USER_ONLY
211
+ "add z1.h, z1.h, #16\n\t"
753
{
212
+ "ptrue p0.b\n\t"
754
- /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
213
+ "smopa za0.d, p0/m, p0/m, z0.h, z1.h\n\t"
755
+ /*
214
+ "ptrue p0.d, vl4\n\t"
756
+ * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
215
+ "mov w12, #0\n\t"
757
* the block size so we might have to do more than one TLB lookup.
216
+ "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t"
758
* We know that in fact for any v8 CPU the page size is at least 4K
217
+ "add %0, %0, #32\n\t"
759
* and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
218
+ "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t"
760
@@ -XXX,XX +XXX,XX @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
219
+ "mov w12, #2\n\t"
761
}
220
+ "add %0, %0, #32\n\t"
762
}
221
+ "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t"
763
if (i == maxidx) {
222
+ "add %0, %0, #32\n\t"
764
- /* If it's all in the TLB it's fair game for just writing to;
223
+ "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t"
765
+ /*
224
+ "smstop"
766
+ * If it's all in the TLB it's fair game for just writing to;
225
+ : "+r"(tmp) : : "memory");
767
* we know we don't need to update dirty status, etc.
226
+
768
*/
227
+ if (memcmp(cmp, dst, sizeof(dst)) == 0) {
769
for (i = 0; i < maxidx - 1; i++) {
228
+ return 0;
770
@@ -XXX,XX +XXX,XX @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
229
+ }
771
memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
230
+
772
return;
231
+ /* See above for correct results. */
773
}
232
+ for (int i = 0; i < 4; ++i) {
774
- /* OK, try a store and see if we can populate the tlb. This
233
+ for (int j = 0; j < 4; ++j) {
775
+ /*
234
+ printf("%6ld", dst[i][j]);
776
+ * OK, try a store and see if we can populate the tlb. This
235
+ }
777
* might cause an exception if the memory isn't writable,
236
+ printf("\n");
778
* in which case we will longjmp out of here. We must for
237
+ }
779
* this purpose use the actual register value passed to us
238
+ return 1;
780
@@ -XXX,XX +XXX,XX @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
239
+}
781
}
240
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
782
}
783
784
- /* Slow path (probably attempt to do this to an I/O device or
785
+ /*
786
+ * Slow path (probably attempt to do this to an I/O device or
787
* similar, or clearing of a block of code we have translations
788
* cached for). Just do a series of byte writes as the architecture
789
* demands. It's not worth trying to use a cpu_physical_memory_map(),
790
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
791
index XXXXXXX..XXXXXXX 100644
241
index XXXXXXX..XXXXXXX 100644
792
--- a/target/arm/op_helper.c
242
--- a/tests/tcg/aarch64/Makefile.target
793
+++ b/target/arm/op_helper.c
243
+++ b/tests/tcg/aarch64/Makefile.target
794
@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
244
@@ -XXX,XX +XXX,XX @@ endif
795
{
245
796
uint32_t syn;
246
# SME Tests
797
247
ifneq ($(CROSS_AS_HAS_ARMV9_SME),)
798
- /* ISV is only set for data aborts routed to EL2 and
248
-AARCH64_TESTS += sme-outprod1
799
+ /*
249
+AARCH64_TESTS += sme-outprod1 sme-smopa-1 sme-smopa-2
800
+ * ISV is only set for data aborts routed to EL2 and
250
endif
801
* never for stage-1 page table walks faulting on stage 2.
251
802
*
252
# System Registers Tests
803
* Furthermore, ISV is only set for certain kinds of load/stores.
804
@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
805
syn = syn_data_abort_no_iss(same_el,
806
ea, 0, s1ptw, is_write, fsc);
807
} else {
808
- /* Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
809
+ /*
810
+ * Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
811
* syndrome created at translation time.
812
* Now we create the runtime syndrome with the remaining fields.
813
*/
814
@@ -XXX,XX +XXX,XX @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type,
815
816
if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
817
arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
818
- /* LPAE format fault status register : bottom 6 bits are
819
+ /*
820
+ * LPAE format fault status register : bottom 6 bits are
821
* status code in the same form as needed for syndrome
822
*/
823
fsr = arm_fi_to_lfsc(fi);
824
fsc = extract32(fsr, 0, 6);
825
} else {
826
fsr = arm_fi_to_sfsc(fi);
827
- /* Short format FSR : this fault will never actually be reported
828
+ /*
829
+ * Short format FSR : this fault will never actually be reported
830
* to an EL that uses a syndrome register. Use a (currently)
831
* reserved FSR code in case the constructed syndrome does leak
832
* into the guest somehow.
833
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
834
arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
835
}
836
837
-/* arm_cpu_do_transaction_failed: handle a memory system error response
838
+/*
839
+ * arm_cpu_do_transaction_failed: handle a memory system error response
840
* (eg "no device/memory present at address") by raising an external abort
841
* exception
842
*/
843
@@ -XXX,XX +XXX,XX @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
844
int bt;
845
uint32_t contextidr;
846
847
- /* Links to unimplemented or non-context aware breakpoints are
848
+ /*
849
+ * Links to unimplemented or non-context aware breakpoints are
850
* CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
851
* as if linked to an UNKNOWN context-aware breakpoint (in which
852
* case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
853
@@ -XXX,XX +XXX,XX @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
854
855
bt = extract64(bcr, 20, 4);
856
857
- /* We match the whole register even if this is AArch32 using the
858
+ /*
859
+ * We match the whole register even if this is AArch32 using the
860
* short descriptor format (in which case it holds both PROCID and ASID),
861
* since we don't implement the optional v7 context ID masking.
862
*/
863
@@ -XXX,XX +XXX,XX @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
864
case 9: /* linked VMID match (reserved if no EL2) */
865
case 11: /* linked context ID and VMID match (reserved if no EL2) */
866
default:
867
- /* Links to Unlinked context breakpoints must generate no
868
+ /*
869
+ * Links to Unlinked context breakpoints must generate no
870
* events; we choose to do the same for reserved values too.
871
*/
872
return false;
873
@@ -XXX,XX +XXX,XX @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
874
CPUARMState *env = &cpu->env;
875
uint64_t cr;
876
int pac, hmc, ssc, wt, lbn;
877
- /* Note that for watchpoints the check is against the CPU security
878
+ /*
879
+ * Note that for watchpoints the check is against the CPU security
880
* state, not the S/NS attribute on the offending data access.
881
*/
882
bool is_secure = arm_is_secure(env);
883
@@ -XXX,XX +XXX,XX @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
884
}
885
cr = env->cp15.dbgwcr[n];
886
if (wp->hitattrs.user) {
887
- /* The LDRT/STRT/LDT/STT "unprivileged access" instructions should
888
+ /*
889
+ * The LDRT/STRT/LDT/STT "unprivileged access" instructions should
890
* match watchpoints as if they were accesses done at EL0, even if
891
* the CPU is at EL1 or higher.
892
*/
893
@@ -XXX,XX +XXX,XX @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
894
}
895
cr = env->cp15.dbgbcr[n];
896
}
897
- /* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
898
+ /*
899
+ * The WATCHPOINT_HIT flag guarantees us that the watchpoint is
900
* enabled and that the address and access type match; for breakpoints
901
* we know the address matched; check the remaining fields, including
902
* linked breakpoints. We rely on WCR and BCR having the same layout
903
@@ -XXX,XX +XXX,XX @@ static bool check_watchpoints(ARMCPU *cpu)
904
CPUARMState *env = &cpu->env;
905
int n;
906
907
- /* If watchpoints are disabled globally or we can't take debug
908
+ /*
909
+ * If watchpoints are disabled globally or we can't take debug
910
* exceptions here then watchpoint firings are ignored.
911
*/
912
if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
913
@@ -XXX,XX +XXX,XX @@ static bool check_breakpoints(ARMCPU *cpu)
914
CPUARMState *env = &cpu->env;
915
int n;
916
917
- /* If breakpoints are disabled globally or we can't take debug
918
+ /*
919
+ * If breakpoints are disabled globally or we can't take debug
920
* exceptions here then breakpoint firings are ignored.
921
*/
922
if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
923
@@ -XXX,XX +XXX,XX @@ void HELPER(check_breakpoints)(CPUARMState *env)
924
925
bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
926
{
927
- /* Called by core code when a CPU watchpoint fires; need to check if this
928
+ /*
929
+ * Called by core code when a CPU watchpoint fires; need to check if this
930
* is also an architectural watchpoint match.
931
*/
932
ARMCPU *cpu = ARM_CPU(cs);
933
@@ -XXX,XX +XXX,XX @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
934
ARMCPU *cpu = ARM_CPU(cs);
935
CPUARMState *env = &cpu->env;
936
937
- /* In BE32 system mode, target memory is stored byteswapped (on a
938
+ /*
939
+ * In BE32 system mode, target memory is stored byteswapped (on a
940
* little-endian host system), and by the time we reach here (via an
941
* opcode helper) the addresses of subword accesses have been adjusted
942
* to account for that, which means that watchpoints will not match.
943
@@ -XXX,XX +XXX,XX @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
944
945
void arm_debug_excp_handler(CPUState *cs)
946
{
947
- /* Called by core code when a watchpoint or breakpoint fires;
948
+ /*
949
+ * Called by core code when a watchpoint or breakpoint fires;
950
* need to check which one and raise the appropriate exception.
951
*/
952
ARMCPU *cpu = ARM_CPU(cs);
953
@@ -XXX,XX +XXX,XX @@ void arm_debug_excp_handler(CPUState *cs)
954
uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
955
bool same_el = (arm_debug_target_el(env) == arm_current_el(env));
956
957
- /* (1) GDB breakpoints should be handled first.
958
+ /*
959
+ * (1) GDB breakpoints should be handled first.
960
* (2) Do not raise a CPU exception if no CPU breakpoint has fired,
961
* since singlestep is also done by generating a debug internal
962
* exception.
963
@@ -XXX,XX +XXX,XX @@ void arm_debug_excp_handler(CPUState *cs)
964
}
965
966
env->exception.fsr = arm_debug_exception_fsr(env);
967
- /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
968
+ /*
969
+ * FAR is UNKNOWN: clear vaddress to avoid potentially exposing
970
* values to the guest that it shouldn't be able to see at its
971
* exception/security level.
972
*/
973
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
974
index XXXXXXX..XXXXXXX 100644
975
--- a/target/arm/vfp_helper.c
976
+++ b/target/arm/vfp_helper.c
977
@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
978
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
979
}
980
981
- /* The exception flags are ORed together when we read fpscr so we
982
+ /*
983
+ * The exception flags are ORed together when we read fpscr so we
984
* only need to preserve the current state in one of our
985
* float_status values.
986
*/
987
--
253
--
988
2.20.1
254
2.34.1
989
255
990
256
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
Since we'll move this code around, fix its style first.
4
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-id: 20190701132516.26392-9-philmd@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate.c | 11 ++++++-----
11
target/arm/vfp_helper.c | 36 ++++++++++++++++++++++++------------
12
2 files changed, 30 insertions(+), 17 deletions(-)
13
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
17
+++ b/target/arm/translate.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
19
loaded_base = 0;
20
loaded_var = NULL;
21
n = 0;
22
- for(i=0;i<16;i++) {
23
+ for (i = 0; i < 16; i++) {
24
if (insn & (1 << i))
25
n++;
26
}
27
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
28
}
29
}
30
j = 0;
31
- for(i=0;i<16;i++) {
32
+ for (i = 0; i < 16; i++) {
33
if (insn & (1 << i)) {
34
if (is_load) {
35
/* load */
36
@@ -XXX,XX +XXX,XX @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
37
return;
38
}
39
40
- for(i=0;i<16;i++) {
41
+ for (i = 0; i < 16; i++) {
42
qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
43
- if ((i % 4) == 3)
44
+ if ((i % 4) == 3) {
45
qemu_fprintf(f, "\n");
46
- else
47
+ } else {
48
qemu_fprintf(f, " ");
49
+ }
50
}
51
52
if (arm_feature(env, ARM_FEATURE_M)) {
53
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/target/arm/vfp_helper.c
56
+++ b/target/arm/vfp_helper.c
57
@@ -XXX,XX +XXX,XX @@ static inline int vfp_exceptbits_from_host(int host_bits)
58
{
59
int target_bits = 0;
60
61
- if (host_bits & float_flag_invalid)
62
+ if (host_bits & float_flag_invalid) {
63
target_bits |= 1;
64
- if (host_bits & float_flag_divbyzero)
65
+ }
66
+ if (host_bits & float_flag_divbyzero) {
67
target_bits |= 2;
68
- if (host_bits & float_flag_overflow)
69
+ }
70
+ if (host_bits & float_flag_overflow) {
71
target_bits |= 4;
72
- if (host_bits & (float_flag_underflow | float_flag_output_denormal))
73
+ }
74
+ if (host_bits & (float_flag_underflow | float_flag_output_denormal)) {
75
target_bits |= 8;
76
- if (host_bits & float_flag_inexact)
77
+ }
78
+ if (host_bits & float_flag_inexact) {
79
target_bits |= 0x10;
80
- if (host_bits & float_flag_input_denormal)
81
+ }
82
+ if (host_bits & float_flag_input_denormal) {
83
target_bits |= 0x80;
84
+ }
85
return target_bits;
86
}
87
88
@@ -XXX,XX +XXX,XX @@ static inline int vfp_exceptbits_to_host(int target_bits)
89
{
90
int host_bits = 0;
91
92
- if (target_bits & 1)
93
+ if (target_bits & 1) {
94
host_bits |= float_flag_invalid;
95
- if (target_bits & 2)
96
+ }
97
+ if (target_bits & 2) {
98
host_bits |= float_flag_divbyzero;
99
- if (target_bits & 4)
100
+ }
101
+ if (target_bits & 4) {
102
host_bits |= float_flag_overflow;
103
- if (target_bits & 8)
104
+ }
105
+ if (target_bits & 8) {
106
host_bits |= float_flag_underflow;
107
- if (target_bits & 0x10)
108
+ }
109
+ if (target_bits & 0x10) {
110
host_bits |= float_flag_inexact;
111
- if (target_bits & 0x80)
112
+ }
113
+ if (target_bits & 0x80) {
114
host_bits |= float_flag_input_denormal;
115
+ }
116
return host_bits;
117
}
118
119
--
120
2.20.1
121
122
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
In the next commit we will split the TLB related routines of
4
this file, and this function will also be called in the new
5
file. Declare it in the "internals.h" header.
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20190701132516.26392-12-philmd@redhat.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/internals.h | 16 ++++++++++++++++
13
target/arm/helper.c | 21 +++++----------------
14
2 files changed, 21 insertions(+), 16 deletions(-)
15
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/internals.h
19
+++ b/target/arm/internals.h
20
@@ -XXX,XX +XXX,XX @@ static inline int exception_target_el(CPUARMState *env)
21
return target_el;
22
}
23
24
+#ifndef CONFIG_USER_ONLY
25
+
26
+/* Cacheability and shareability attributes for a memory access */
27
+typedef struct ARMCacheAttrs {
28
+ unsigned int attrs:8; /* as in the MAIR register encoding */
29
+ unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */
30
+} ARMCacheAttrs;
31
+
32
+bool get_phys_addr(CPUARMState *env, target_ulong address,
33
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
34
+ hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
35
+ target_ulong *page_size,
36
+ ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
37
+
38
+#endif /* !CONFIG_USER_ONLY */
39
+
40
#endif
41
diff --git a/target/arm/helper.c b/target/arm/helper.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/helper.c
44
+++ b/target/arm/helper.c
45
@@ -XXX,XX +XXX,XX @@
46
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
47
48
#ifndef CONFIG_USER_ONLY
49
-/* Cacheability and shareability attributes for a memory access */
50
-typedef struct ARMCacheAttrs {
51
- unsigned int attrs:8; /* as in the MAIR register encoding */
52
- unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */
53
-} ARMCacheAttrs;
54
-
55
-static bool get_phys_addr(CPUARMState *env, target_ulong address,
56
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
57
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
58
- target_ulong *page_size,
59
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
60
61
static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
62
MMUAccessType access_type, ARMMMUIdx mmu_idx,
63
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2)
64
* @fi: set to fault info if the translation fails
65
* @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
66
*/
67
-static bool get_phys_addr(CPUARMState *env, target_ulong address,
68
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
69
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
70
- target_ulong *page_size,
71
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
72
+bool get_phys_addr(CPUARMState *env, target_ulong address,
73
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
74
+ hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
75
+ target_ulong *page_size,
76
+ ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
77
{
78
if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
79
/* Call ourselves recursively to do the stage 1 and then stage 2
80
--
81
2.20.1
82
83
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
The sun4v RTC device model added under commit a0e893039cf2ce0 in 2016
2
was unfortunately added with a license of GPL-v3-or-later, which is
3
not compatible with other QEMU code which has a GPL-v2-only license.
2
4
3
This code is specific to the SoftFloat floating-point
5
Relicense the code in the .c and the .h file to GPL-v2-or-later,
4
implementation, which is only used by TCG.
6
to make it compatible with the rest of QEMU.
5
7
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Cc: qemu-stable@nongnu.org
7
Message-id: 20190701132516.26392-18-philmd@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Paolo Bonzini (for Red Hat) <pbonzini@redhat.com>
11
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
12
Signed-off-by: Markus Armbruster <armbru@redhat.com>
13
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
15
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
16
Acked-by: Alex Bennée <alex.bennee@linaro.org>
17
Message-id: 20240223161300.938542-1-peter.maydell@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
19
---
11
target/arm/vfp_helper.c | 26 +++++++++++++++++++++++---
20
include/hw/rtc/sun4v-rtc.h | 2 +-
12
1 file changed, 23 insertions(+), 3 deletions(-)
21
hw/rtc/sun4v-rtc.c | 2 +-
22
2 files changed, 2 insertions(+), 2 deletions(-)
13
23
14
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
24
diff --git a/include/hw/rtc/sun4v-rtc.h b/include/hw/rtc/sun4v-rtc.h
15
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/vfp_helper.c
26
--- a/include/hw/rtc/sun4v-rtc.h
17
+++ b/target/arm/vfp_helper.c
27
+++ b/include/hw/rtc/sun4v-rtc.h
18
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@
29
*
30
* Copyright (c) 2016 Artyom Tarasenko
31
*
32
- * This code is licensed under the GNU GPL v3 or (at your option) any later
33
+ * This code is licensed under the GNU GPL v2 or (at your option) any later
34
* version.
19
*/
35
*/
20
36
21
#include "qemu/osdep.h"
37
diff --git a/hw/rtc/sun4v-rtc.c b/hw/rtc/sun4v-rtc.c
22
-#include "qemu/log.h"
38
index XXXXXXX..XXXXXXX 100644
23
#include "cpu.h"
39
--- a/hw/rtc/sun4v-rtc.c
24
#include "exec/helper-proto.h"
40
+++ b/hw/rtc/sun4v-rtc.c
25
-#include "fpu/softfloat.h"
41
@@ -XXX,XX +XXX,XX @@
26
#include "internals.h"
42
*
27
-
43
* Copyright (c) 2016 Artyom Tarasenko
28
+#ifdef CONFIG_TCG
44
*
29
+#include "qemu/log.h"
45
- * This code is licensed under the GNU GPL v3 or (at your option) any later
30
+#include "fpu/softfloat.h"
46
+ * This code is licensed under the GNU GPL v2 or (at your option) any later
31
+#endif
47
* version.
32
48
*/
33
/* VFP support. We follow the convention used for VFP instructions:
49
34
Single precision routines have a "s" suffix, double precision a
35
"d" suffix. */
36
37
+#ifdef CONFIG_TCG
38
+
39
/* Convert host exception flags to vfp form. */
40
static inline int vfp_exceptbits_from_host(int host_bits)
41
{
42
@@ -XXX,XX +XXX,XX @@ static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
43
set_float_exception_flags(0, &env->vfp.standard_fp_status);
44
}
45
46
+#else
47
+
48
+static uint32_t vfp_get_fpscr_from_host(CPUARMState *env)
49
+{
50
+ return 0;
51
+}
52
+
53
+static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
54
+{
55
+}
56
+
57
+#endif
58
+
59
uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
60
{
61
uint32_t i, fpscr;
62
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val)
63
HELPER(vfp_set_fpscr)(env, val);
64
}
65
66
+#ifdef CONFIG_TCG
67
+
68
#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
69
70
#define VFP_BINOP(name) \
71
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frint64_d)(float64 f, void *fpst)
72
{
73
return frint_d(f, fpst, 64);
74
}
75
+
76
+#endif
77
--
50
--
78
2.20.1
51
2.34.1
79
52
80
53
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Thomas Huth <thuth@redhat.com>
2
2
3
These routines are TCG specific.
3
Move the code to a separate file so that we do not have to compile
4
The arm_deliver_fault() function is only used within the new
4
it anymore if CONFIG_ARM_V7M is not set.
5
helper. Make it static.
6
5
7
Suggested-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Thomas Huth <thuth@redhat.com>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-id: 20240308141051.536599-2-thuth@redhat.com
9
Message-id: 20190701132516.26392-13-philmd@redhat.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
target/arm/Makefile.objs | 1 +
11
target/arm/tcg/cpu-v7m.c | 290 +++++++++++++++++++++++++++++++++++++
14
target/arm/internals.h | 3 -
12
target/arm/tcg/cpu32.c | 261 ---------------------------------
15
target/arm/cpu.c | 6 +-
13
target/arm/meson.build | 3 +
16
target/arm/helper.c | 53 -----------
14
target/arm/tcg/meson.build | 3 +
17
target/arm/op_helper.c | 135 --------------------------
15
4 files changed, 296 insertions(+), 261 deletions(-)
18
target/arm/tlb_helper.c | 200 +++++++++++++++++++++++++++++++++++++++
16
create mode 100644 target/arm/tcg/cpu-v7m.c
19
6 files changed, 205 insertions(+), 193 deletions(-)
20
create mode 100644 target/arm/tlb_helper.c
21
17
22
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
18
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/Makefile.objs
25
+++ b/target/arm/Makefile.objs
26
@@ -XXX,XX +XXX,XX @@ target/arm/translate-sve.o: target/arm/decode-sve.inc.c
27
target/arm/translate.o: target/arm/decode-vfp.inc.c
28
target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
29
30
+obj-y += tlb_helper.o
31
obj-y += translate.o op_helper.o
32
obj-y += crypto_helper.o
33
obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
34
diff --git a/target/arm/internals.h b/target/arm/internals.h
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/internals.h
37
+++ b/target/arm/internals.h
38
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
39
MMUAccessType access_type, int mmu_idx,
40
bool probe, uintptr_t retaddr);
41
42
-void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type,
43
- int mmu_idx, ARMMMUFaultInfo *fi) QEMU_NORETURN;
44
-
45
/* Return true if the stage 1 translation regime is using LPAE format page
46
* tables */
47
bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
48
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/cpu.c
51
+++ b/target/arm/cpu.c
52
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
53
cc->gdb_write_register = arm_cpu_gdb_write_register;
54
#ifndef CONFIG_USER_ONLY
55
cc->do_interrupt = arm_cpu_do_interrupt;
56
- cc->do_unaligned_access = arm_cpu_do_unaligned_access;
57
- cc->do_transaction_failed = arm_cpu_do_transaction_failed;
58
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
59
cc->asidx_from_attrs = arm_asidx_from_attrs;
60
cc->vmsd = &vmstate_arm_cpu;
61
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
62
#ifdef CONFIG_TCG
63
cc->tcg_initialize = arm_translate_init;
64
cc->tlb_fill = arm_cpu_tlb_fill;
65
+#if !defined(CONFIG_USER_ONLY)
66
+ cc->do_unaligned_access = arm_cpu_do_unaligned_access;
67
+ cc->do_transaction_failed = arm_cpu_do_transaction_failed;
68
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
69
#endif
70
}
71
72
diff --git a/target/arm/helper.c b/target/arm/helper.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/target/arm/helper.c
75
+++ b/target/arm/helper.c
76
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
77
78
#endif
79
80
-bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
81
- MMUAccessType access_type, int mmu_idx,
82
- bool probe, uintptr_t retaddr)
83
-{
84
- ARMCPU *cpu = ARM_CPU(cs);
85
-
86
-#ifdef CONFIG_USER_ONLY
87
- cpu->env.exception.vaddress = address;
88
- if (access_type == MMU_INST_FETCH) {
89
- cs->exception_index = EXCP_PREFETCH_ABORT;
90
- } else {
91
- cs->exception_index = EXCP_DATA_ABORT;
92
- }
93
- cpu_loop_exit_restore(cs, retaddr);
94
-#else
95
- hwaddr phys_addr;
96
- target_ulong page_size;
97
- int prot, ret;
98
- MemTxAttrs attrs = {};
99
- ARMMMUFaultInfo fi = {};
100
-
101
- /*
102
- * Walk the page table and (if the mapping exists) add the page
103
- * to the TLB. On success, return true. Otherwise, if probing,
104
- * return false. Otherwise populate fsr with ARM DFSR/IFSR fault
105
- * register format, and signal the fault.
106
- */
107
- ret = get_phys_addr(&cpu->env, address, access_type,
108
- core_to_arm_mmu_idx(&cpu->env, mmu_idx),
109
- &phys_addr, &attrs, &prot, &page_size, &fi, NULL);
110
- if (likely(!ret)) {
111
- /*
112
- * Map a single [sub]page. Regions smaller than our declared
113
- * target page size are handled specially, so for those we
114
- * pass in the exact addresses.
115
- */
116
- if (page_size >= TARGET_PAGE_SIZE) {
117
- phys_addr &= TARGET_PAGE_MASK;
118
- address &= TARGET_PAGE_MASK;
119
- }
120
- tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
121
- prot, mmu_idx, page_size);
122
- return true;
123
- } else if (probe) {
124
- return false;
125
- } else {
126
- /* now we have a real cpu fault */
127
- cpu_restore_state(cs, retaddr, true);
128
- arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
129
- }
130
-#endif
131
-}
132
-
133
/* Note that signed overflow is undefined in C. The following routines are
134
careful to use unsigned types where modulo arithmetic is required.
135
Failure to do so _will_ break on newer gcc. */
136
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
137
index XXXXXXX..XXXXXXX 100644
138
--- a/target/arm/op_helper.c
139
+++ b/target/arm/op_helper.c
140
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn,
141
return val;
142
}
143
144
-#if !defined(CONFIG_USER_ONLY)
145
-
146
-static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
147
- unsigned int target_el,
148
- bool same_el, bool ea,
149
- bool s1ptw, bool is_write,
150
- int fsc)
151
-{
152
- uint32_t syn;
153
-
154
- /*
155
- * ISV is only set for data aborts routed to EL2 and
156
- * never for stage-1 page table walks faulting on stage 2.
157
- *
158
- * Furthermore, ISV is only set for certain kinds of load/stores.
159
- * If the template syndrome does not have ISV set, we should leave
160
- * it cleared.
161
- *
162
- * See ARMv8 specs, D7-1974:
163
- * ISS encoding for an exception from a Data Abort, the
164
- * ISV field.
165
- */
166
- if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) {
167
- syn = syn_data_abort_no_iss(same_el,
168
- ea, 0, s1ptw, is_write, fsc);
169
- } else {
170
- /*
171
- * Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
172
- * syndrome created at translation time.
173
- * Now we create the runtime syndrome with the remaining fields.
174
- */
175
- syn = syn_data_abort_with_iss(same_el,
176
- 0, 0, 0, 0, 0,
177
- ea, 0, s1ptw, is_write, fsc,
178
- false);
179
- /* Merge the runtime syndrome with the template syndrome. */
180
- syn |= template_syn;
181
- }
182
- return syn;
183
-}
184
-
185
-void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type,
186
- int mmu_idx, ARMMMUFaultInfo *fi)
187
-{
188
- CPUARMState *env = &cpu->env;
189
- int target_el;
190
- bool same_el;
191
- uint32_t syn, exc, fsr, fsc;
192
- ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
193
-
194
- target_el = exception_target_el(env);
195
- if (fi->stage2) {
196
- target_el = 2;
197
- env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
198
- }
199
- same_el = (arm_current_el(env) == target_el);
200
-
201
- if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
202
- arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
203
- /*
204
- * LPAE format fault status register : bottom 6 bits are
205
- * status code in the same form as needed for syndrome
206
- */
207
- fsr = arm_fi_to_lfsc(fi);
208
- fsc = extract32(fsr, 0, 6);
209
- } else {
210
- fsr = arm_fi_to_sfsc(fi);
211
- /*
212
- * Short format FSR : this fault will never actually be reported
213
- * to an EL that uses a syndrome register. Use a (currently)
214
- * reserved FSR code in case the constructed syndrome does leak
215
- * into the guest somehow.
216
- */
217
- fsc = 0x3f;
218
- }
219
-
220
- if (access_type == MMU_INST_FETCH) {
221
- syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc);
222
- exc = EXCP_PREFETCH_ABORT;
223
- } else {
224
- syn = merge_syn_data_abort(env->exception.syndrome, target_el,
225
- same_el, fi->ea, fi->s1ptw,
226
- access_type == MMU_DATA_STORE,
227
- fsc);
228
- if (access_type == MMU_DATA_STORE
229
- && arm_feature(env, ARM_FEATURE_V6)) {
230
- fsr |= (1 << 11);
231
- }
232
- exc = EXCP_DATA_ABORT;
233
- }
234
-
235
- env->exception.vaddress = addr;
236
- env->exception.fsr = fsr;
237
- raise_exception(env, exc, syn, target_el);
238
-}
239
-
240
-/* Raise a data fault alignment exception for the specified virtual address */
241
-void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
242
- MMUAccessType access_type,
243
- int mmu_idx, uintptr_t retaddr)
244
-{
245
- ARMCPU *cpu = ARM_CPU(cs);
246
- ARMMMUFaultInfo fi = {};
247
-
248
- /* now we have a real cpu fault */
249
- cpu_restore_state(cs, retaddr, true);
250
-
251
- fi.type = ARMFault_Alignment;
252
- arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
253
-}
254
-
255
-/*
256
- * arm_cpu_do_transaction_failed: handle a memory system error response
257
- * (eg "no device/memory present at address") by raising an external abort
258
- * exception
259
- */
260
-void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
261
- vaddr addr, unsigned size,
262
- MMUAccessType access_type,
263
- int mmu_idx, MemTxAttrs attrs,
264
- MemTxResult response, uintptr_t retaddr)
265
-{
266
- ARMCPU *cpu = ARM_CPU(cs);
267
- ARMMMUFaultInfo fi = {};
268
-
269
- /* now we have a real cpu fault */
270
- cpu_restore_state(cs, retaddr, true);
271
-
272
- fi.ea = arm_extabort_type(response);
273
- fi.type = ARMFault_SyncExternal;
274
- arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi);
275
-}
276
-
277
-#endif /* !defined(CONFIG_USER_ONLY) */
278
-
279
void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t newvalue)
280
{
281
/*
282
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
283
new file mode 100644
19
new file mode 100644
284
index XXXXXXX..XXXXXXX
20
index XXXXXXX..XXXXXXX
285
--- /dev/null
21
--- /dev/null
286
+++ b/target/arm/tlb_helper.c
22
+++ b/target/arm/tcg/cpu-v7m.c
287
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@
288
+/*
24
+/*
289
+ * ARM TLB (Translation lookaside buffer) helpers.
25
+ * QEMU ARMv7-M TCG-only CPUs.
26
+ *
27
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
290
+ *
28
+ *
291
+ * This code is licensed under the GNU GPL v2 or later.
29
+ * This code is licensed under the GNU GPL v2 or later.
292
+ *
30
+ *
293
+ * SPDX-License-Identifier: GPL-2.0-or-later
31
+ * SPDX-License-Identifier: GPL-2.0-or-later
294
+ */
32
+ */
33
+
295
+#include "qemu/osdep.h"
34
+#include "qemu/osdep.h"
296
+#include "cpu.h"
35
+#include "cpu.h"
36
+#include "hw/core/tcg-cpu-ops.h"
297
+#include "internals.h"
37
+#include "internals.h"
298
+#include "exec/exec-all.h"
299
+
38
+
300
+#if !defined(CONFIG_USER_ONLY)
39
+#if !defined(CONFIG_USER_ONLY)
301
+
40
+
302
+static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
41
+#include "hw/intc/armv7m_nvic.h"
303
+ unsigned int target_el,
42
+
304
+ bool same_el, bool ea,
43
+static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
305
+ bool s1ptw, bool is_write,
44
+{
306
+ int fsc)
45
+ CPUClass *cc = CPU_GET_CLASS(cs);
307
+{
46
+ ARMCPU *cpu = ARM_CPU(cs);
308
+ uint32_t syn;
47
+ CPUARMState *env = &cpu->env;
48
+ bool ret = false;
309
+
49
+
310
+ /*
50
+ /*
311
+ * ISV is only set for data aborts routed to EL2 and
51
+ * ARMv7-M interrupt masking works differently than -A or -R.
312
+ * never for stage-1 page table walks faulting on stage 2.
52
+ * There is no FIQ/IRQ distinction. Instead of I and F bits
313
+ *
53
+ * masking FIQ and IRQ interrupts, an exception is taken only
314
+ * Furthermore, ISV is only set for certain kinds of load/stores.
54
+ * if it is higher priority than the current execution priority
315
+ * If the template syndrome does not have ISV set, we should leave
55
+ * (which depends on state like BASEPRI, FAULTMASK and the
316
+ * it cleared.
56
+ * currently active exception).
317
+ *
318
+ * See ARMv8 specs, D7-1974:
319
+ * ISS encoding for an exception from a Data Abort, the
320
+ * ISV field.
321
+ */
57
+ */
322
+ if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) {
58
+ if (interrupt_request & CPU_INTERRUPT_HARD
323
+ syn = syn_data_abort_no_iss(same_el,
59
+ && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
324
+ ea, 0, s1ptw, is_write, fsc);
60
+ cs->exception_index = EXCP_IRQ;
325
+ } else {
61
+ cc->tcg_ops->do_interrupt(cs);
326
+ /*
62
+ ret = true;
327
+ * Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
328
+ * syndrome created at translation time.
329
+ * Now we create the runtime syndrome with the remaining fields.
330
+ */
331
+ syn = syn_data_abort_with_iss(same_el,
332
+ 0, 0, 0, 0, 0,
333
+ ea, 0, s1ptw, is_write, fsc,
334
+ false);
335
+ /* Merge the runtime syndrome with the template syndrome. */
336
+ syn |= template_syn;
337
+ }
63
+ }
338
+ return syn;
64
+ return ret;
339
+}
65
+}
340
+
66
+
341
+static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
67
+#endif /* !CONFIG_USER_ONLY */
342
+ MMUAccessType access_type,
68
+
343
+ int mmu_idx, ARMMMUFaultInfo *fi)
69
+static void cortex_m0_initfn(Object *obj)
344
+{
70
+{
345
+ CPUARMState *env = &cpu->env;
71
+ ARMCPU *cpu = ARM_CPU(obj);
346
+ int target_el;
72
+ set_feature(&cpu->env, ARM_FEATURE_V6);
347
+ bool same_el;
73
+ set_feature(&cpu->env, ARM_FEATURE_M);
348
+ uint32_t syn, exc, fsr, fsc;
74
+
349
+ ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
75
+ cpu->midr = 0x410cc200;
350
+
76
+
351
+ target_el = exception_target_el(env);
77
+ /*
352
+ if (fi->stage2) {
78
+ * These ID register values are not guest visible, because
353
+ target_el = 2;
79
+ * we do not implement the Main Extension. They must be set
354
+ env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
80
+ * to values corresponding to the Cortex-M0's implemented
81
+ * features, because QEMU generally controls its emulation
82
+ * by looking at ID register fields. We use the same values as
83
+ * for the M3.
84
+ */
85
+ cpu->isar.id_pfr0 = 0x00000030;
86
+ cpu->isar.id_pfr1 = 0x00000200;
87
+ cpu->isar.id_dfr0 = 0x00100000;
88
+ cpu->id_afr0 = 0x00000000;
89
+ cpu->isar.id_mmfr0 = 0x00000030;
90
+ cpu->isar.id_mmfr1 = 0x00000000;
91
+ cpu->isar.id_mmfr2 = 0x00000000;
92
+ cpu->isar.id_mmfr3 = 0x00000000;
93
+ cpu->isar.id_isar0 = 0x01141110;
94
+ cpu->isar.id_isar1 = 0x02111000;
95
+ cpu->isar.id_isar2 = 0x21112231;
96
+ cpu->isar.id_isar3 = 0x01111110;
97
+ cpu->isar.id_isar4 = 0x01310102;
98
+ cpu->isar.id_isar5 = 0x00000000;
99
+ cpu->isar.id_isar6 = 0x00000000;
100
+}
101
+
102
+static void cortex_m3_initfn(Object *obj)
103
+{
104
+ ARMCPU *cpu = ARM_CPU(obj);
105
+ set_feature(&cpu->env, ARM_FEATURE_V7);
106
+ set_feature(&cpu->env, ARM_FEATURE_M);
107
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
108
+ cpu->midr = 0x410fc231;
109
+ cpu->pmsav7_dregion = 8;
110
+ cpu->isar.id_pfr0 = 0x00000030;
111
+ cpu->isar.id_pfr1 = 0x00000200;
112
+ cpu->isar.id_dfr0 = 0x00100000;
113
+ cpu->id_afr0 = 0x00000000;
114
+ cpu->isar.id_mmfr0 = 0x00000030;
115
+ cpu->isar.id_mmfr1 = 0x00000000;
116
+ cpu->isar.id_mmfr2 = 0x00000000;
117
+ cpu->isar.id_mmfr3 = 0x00000000;
118
+ cpu->isar.id_isar0 = 0x01141110;
119
+ cpu->isar.id_isar1 = 0x02111000;
120
+ cpu->isar.id_isar2 = 0x21112231;
121
+ cpu->isar.id_isar3 = 0x01111110;
122
+ cpu->isar.id_isar4 = 0x01310102;
123
+ cpu->isar.id_isar5 = 0x00000000;
124
+ cpu->isar.id_isar6 = 0x00000000;
125
+}
126
+
127
+static void cortex_m4_initfn(Object *obj)
128
+{
129
+ ARMCPU *cpu = ARM_CPU(obj);
130
+
131
+ set_feature(&cpu->env, ARM_FEATURE_V7);
132
+ set_feature(&cpu->env, ARM_FEATURE_M);
133
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
134
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
135
+ cpu->midr = 0x410fc240; /* r0p0 */
136
+ cpu->pmsav7_dregion = 8;
137
+ cpu->isar.mvfr0 = 0x10110021;
138
+ cpu->isar.mvfr1 = 0x11000011;
139
+ cpu->isar.mvfr2 = 0x00000000;
140
+ cpu->isar.id_pfr0 = 0x00000030;
141
+ cpu->isar.id_pfr1 = 0x00000200;
142
+ cpu->isar.id_dfr0 = 0x00100000;
143
+ cpu->id_afr0 = 0x00000000;
144
+ cpu->isar.id_mmfr0 = 0x00000030;
145
+ cpu->isar.id_mmfr1 = 0x00000000;
146
+ cpu->isar.id_mmfr2 = 0x00000000;
147
+ cpu->isar.id_mmfr3 = 0x00000000;
148
+ cpu->isar.id_isar0 = 0x01141110;
149
+ cpu->isar.id_isar1 = 0x02111000;
150
+ cpu->isar.id_isar2 = 0x21112231;
151
+ cpu->isar.id_isar3 = 0x01111110;
152
+ cpu->isar.id_isar4 = 0x01310102;
153
+ cpu->isar.id_isar5 = 0x00000000;
154
+ cpu->isar.id_isar6 = 0x00000000;
155
+}
156
+
157
+static void cortex_m7_initfn(Object *obj)
158
+{
159
+ ARMCPU *cpu = ARM_CPU(obj);
160
+
161
+ set_feature(&cpu->env, ARM_FEATURE_V7);
162
+ set_feature(&cpu->env, ARM_FEATURE_M);
163
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
164
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
165
+ cpu->midr = 0x411fc272; /* r1p2 */
166
+ cpu->pmsav7_dregion = 8;
167
+ cpu->isar.mvfr0 = 0x10110221;
168
+ cpu->isar.mvfr1 = 0x12000011;
169
+ cpu->isar.mvfr2 = 0x00000040;
170
+ cpu->isar.id_pfr0 = 0x00000030;
171
+ cpu->isar.id_pfr1 = 0x00000200;
172
+ cpu->isar.id_dfr0 = 0x00100000;
173
+ cpu->id_afr0 = 0x00000000;
174
+ cpu->isar.id_mmfr0 = 0x00100030;
175
+ cpu->isar.id_mmfr1 = 0x00000000;
176
+ cpu->isar.id_mmfr2 = 0x01000000;
177
+ cpu->isar.id_mmfr3 = 0x00000000;
178
+ cpu->isar.id_isar0 = 0x01101110;
179
+ cpu->isar.id_isar1 = 0x02112000;
180
+ cpu->isar.id_isar2 = 0x20232231;
181
+ cpu->isar.id_isar3 = 0x01111131;
182
+ cpu->isar.id_isar4 = 0x01310132;
183
+ cpu->isar.id_isar5 = 0x00000000;
184
+ cpu->isar.id_isar6 = 0x00000000;
185
+}
186
+
187
+static void cortex_m33_initfn(Object *obj)
188
+{
189
+ ARMCPU *cpu = ARM_CPU(obj);
190
+
191
+ set_feature(&cpu->env, ARM_FEATURE_V8);
192
+ set_feature(&cpu->env, ARM_FEATURE_M);
193
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
194
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
195
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
196
+ cpu->midr = 0x410fd213; /* r0p3 */
197
+ cpu->pmsav7_dregion = 16;
198
+ cpu->sau_sregion = 8;
199
+ cpu->isar.mvfr0 = 0x10110021;
200
+ cpu->isar.mvfr1 = 0x11000011;
201
+ cpu->isar.mvfr2 = 0x00000040;
202
+ cpu->isar.id_pfr0 = 0x00000030;
203
+ cpu->isar.id_pfr1 = 0x00000210;
204
+ cpu->isar.id_dfr0 = 0x00200000;
205
+ cpu->id_afr0 = 0x00000000;
206
+ cpu->isar.id_mmfr0 = 0x00101F40;
207
+ cpu->isar.id_mmfr1 = 0x00000000;
208
+ cpu->isar.id_mmfr2 = 0x01000000;
209
+ cpu->isar.id_mmfr3 = 0x00000000;
210
+ cpu->isar.id_isar0 = 0x01101110;
211
+ cpu->isar.id_isar1 = 0x02212000;
212
+ cpu->isar.id_isar2 = 0x20232232;
213
+ cpu->isar.id_isar3 = 0x01111131;
214
+ cpu->isar.id_isar4 = 0x01310132;
215
+ cpu->isar.id_isar5 = 0x00000000;
216
+ cpu->isar.id_isar6 = 0x00000000;
217
+ cpu->clidr = 0x00000000;
218
+ cpu->ctr = 0x8000c000;
219
+}
220
+
221
+static void cortex_m55_initfn(Object *obj)
222
+{
223
+ ARMCPU *cpu = ARM_CPU(obj);
224
+
225
+ set_feature(&cpu->env, ARM_FEATURE_V8);
226
+ set_feature(&cpu->env, ARM_FEATURE_V8_1M);
227
+ set_feature(&cpu->env, ARM_FEATURE_M);
228
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
229
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
230
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
231
+ cpu->midr = 0x410fd221; /* r0p1 */
232
+ cpu->revidr = 0;
233
+ cpu->pmsav7_dregion = 16;
234
+ cpu->sau_sregion = 8;
235
+ /* These are the MVFR* values for the FPU + full MVE configuration */
236
+ cpu->isar.mvfr0 = 0x10110221;
237
+ cpu->isar.mvfr1 = 0x12100211;
238
+ cpu->isar.mvfr2 = 0x00000040;
239
+ cpu->isar.id_pfr0 = 0x20000030;
240
+ cpu->isar.id_pfr1 = 0x00000230;
241
+ cpu->isar.id_dfr0 = 0x10200000;
242
+ cpu->id_afr0 = 0x00000000;
243
+ cpu->isar.id_mmfr0 = 0x00111040;
244
+ cpu->isar.id_mmfr1 = 0x00000000;
245
+ cpu->isar.id_mmfr2 = 0x01000000;
246
+ cpu->isar.id_mmfr3 = 0x00000011;
247
+ cpu->isar.id_isar0 = 0x01103110;
248
+ cpu->isar.id_isar1 = 0x02212000;
249
+ cpu->isar.id_isar2 = 0x20232232;
250
+ cpu->isar.id_isar3 = 0x01111131;
251
+ cpu->isar.id_isar4 = 0x01310132;
252
+ cpu->isar.id_isar5 = 0x00000000;
253
+ cpu->isar.id_isar6 = 0x00000000;
254
+ cpu->clidr = 0x00000000; /* caches not implemented */
255
+ cpu->ctr = 0x8303c003;
256
+}
257
+
258
+static const TCGCPUOps arm_v7m_tcg_ops = {
259
+ .initialize = arm_translate_init,
260
+ .synchronize_from_tb = arm_cpu_synchronize_from_tb,
261
+ .debug_excp_handler = arm_debug_excp_handler,
262
+ .restore_state_to_opc = arm_restore_state_to_opc,
263
+
264
+#ifdef CONFIG_USER_ONLY
265
+ .record_sigsegv = arm_cpu_record_sigsegv,
266
+ .record_sigbus = arm_cpu_record_sigbus,
267
+#else
268
+ .tlb_fill = arm_cpu_tlb_fill,
269
+ .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
270
+ .do_interrupt = arm_v7m_cpu_do_interrupt,
271
+ .do_transaction_failed = arm_cpu_do_transaction_failed,
272
+ .do_unaligned_access = arm_cpu_do_unaligned_access,
273
+ .adjust_watchpoint_address = arm_adjust_watchpoint_address,
274
+ .debug_check_watchpoint = arm_debug_check_watchpoint,
275
+ .debug_check_breakpoint = arm_debug_check_breakpoint,
276
+#endif /* !CONFIG_USER_ONLY */
277
+};
278
+
279
+static void arm_v7m_class_init(ObjectClass *oc, void *data)
280
+{
281
+ ARMCPUClass *acc = ARM_CPU_CLASS(oc);
282
+ CPUClass *cc = CPU_CLASS(oc);
283
+
284
+ acc->info = data;
285
+ cc->tcg_ops = &arm_v7m_tcg_ops;
286
+ cc->gdb_core_xml_file = "arm-m-profile.xml";
287
+}
288
+
289
+static const ARMCPUInfo arm_v7m_cpus[] = {
290
+ { .name = "cortex-m0", .initfn = cortex_m0_initfn,
291
+ .class_init = arm_v7m_class_init },
292
+ { .name = "cortex-m3", .initfn = cortex_m3_initfn,
293
+ .class_init = arm_v7m_class_init },
294
+ { .name = "cortex-m4", .initfn = cortex_m4_initfn,
295
+ .class_init = arm_v7m_class_init },
296
+ { .name = "cortex-m7", .initfn = cortex_m7_initfn,
297
+ .class_init = arm_v7m_class_init },
298
+ { .name = "cortex-m33", .initfn = cortex_m33_initfn,
299
+ .class_init = arm_v7m_class_init },
300
+ { .name = "cortex-m55", .initfn = cortex_m55_initfn,
301
+ .class_init = arm_v7m_class_init },
302
+};
303
+
304
+static void arm_v7m_cpu_register_types(void)
305
+{
306
+ size_t i;
307
+
308
+ for (i = 0; i < ARRAY_SIZE(arm_v7m_cpus); ++i) {
309
+ arm_cpu_register(&arm_v7m_cpus[i]);
355
+ }
310
+ }
356
+ same_el = (arm_current_el(env) == target_el);
311
+}
357
+
312
+
358
+ if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
313
+type_init(arm_v7m_cpu_register_types)
359
+ arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
314
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
360
+ /*
315
index XXXXXXX..XXXXXXX 100644
361
+ * LPAE format fault status register : bottom 6 bits are
316
--- a/target/arm/tcg/cpu32.c
362
+ * status code in the same form as needed for syndrome
317
+++ b/target/arm/tcg/cpu32.c
363
+ */
318
@@ -XXX,XX +XXX,XX @@
364
+ fsr = arm_fi_to_lfsc(fi);
319
#include "hw/boards.h"
365
+ fsc = extract32(fsr, 0, 6);
320
#endif
366
+ } else {
321
#include "cpregs.h"
367
+ fsr = arm_fi_to_sfsc(fi);
322
-#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
368
+ /*
323
-#include "hw/intc/armv7m_nvic.h"
369
+ * Short format FSR : this fault will never actually be reported
324
-#endif
370
+ * to an EL that uses a syndrome register. Use a (currently)
325
371
+ * reserved FSR code in case the constructed syndrome does leak
326
372
+ * into the guest somehow.
327
/* Share AArch32 -cpu max features with AArch64. */
373
+ */
328
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
374
+ fsc = 0x3f;
329
/* CPU models. These are not needed for the AArch64 linux-user build. */
375
+ }
330
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
376
+
331
377
+ if (access_type == MMU_INST_FETCH) {
332
-#if !defined(CONFIG_USER_ONLY)
378
+ syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc);
333
-static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
379
+ exc = EXCP_PREFETCH_ABORT;
334
-{
380
+ } else {
335
- CPUClass *cc = CPU_GET_CLASS(cs);
381
+ syn = merge_syn_data_abort(env->exception.syndrome, target_el,
336
- ARMCPU *cpu = ARM_CPU(cs);
382
+ same_el, fi->ea, fi->s1ptw,
337
- CPUARMState *env = &cpu->env;
383
+ access_type == MMU_DATA_STORE,
338
- bool ret = false;
384
+ fsc);
339
-
385
+ if (access_type == MMU_DATA_STORE
340
- /*
386
+ && arm_feature(env, ARM_FEATURE_V6)) {
341
- * ARMv7-M interrupt masking works differently than -A or -R.
387
+ fsr |= (1 << 11);
342
- * There is no FIQ/IRQ distinction. Instead of I and F bits
388
+ }
343
- * masking FIQ and IRQ interrupts, an exception is taken only
389
+ exc = EXCP_DATA_ABORT;
344
- * if it is higher priority than the current execution priority
390
+ }
345
- * (which depends on state like BASEPRI, FAULTMASK and the
391
+
346
- * currently active exception).
392
+ env->exception.vaddress = addr;
347
- */
393
+ env->exception.fsr = fsr;
348
- if (interrupt_request & CPU_INTERRUPT_HARD
394
+ raise_exception(env, exc, syn, target_el);
349
- && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
395
+}
350
- cs->exception_index = EXCP_IRQ;
396
+
351
- cc->tcg_ops->do_interrupt(cs);
397
+/* Raise a data fault alignment exception for the specified virtual address */
352
- ret = true;
398
+void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
353
- }
399
+ MMUAccessType access_type,
354
- return ret;
400
+ int mmu_idx, uintptr_t retaddr)
355
-}
401
+{
356
-#endif /* !CONFIG_USER_ONLY */
402
+ ARMCPU *cpu = ARM_CPU(cs);
357
-
403
+ ARMMMUFaultInfo fi = {};
358
static void arm926_initfn(Object *obj)
404
+
359
{
405
+ /* now we have a real cpu fault */
360
ARMCPU *cpu = ARM_CPU(obj);
406
+ cpu_restore_state(cs, retaddr, true);
361
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
407
+
362
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
408
+ fi.type = ARMFault_Alignment;
363
}
409
+ arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
364
410
+}
365
-static void cortex_m0_initfn(Object *obj)
411
+
366
-{
412
+/*
367
- ARMCPU *cpu = ARM_CPU(obj);
413
+ * arm_cpu_do_transaction_failed: handle a memory system error response
368
- set_feature(&cpu->env, ARM_FEATURE_V6);
414
+ * (eg "no device/memory present at address") by raising an external abort
369
- set_feature(&cpu->env, ARM_FEATURE_M);
415
+ * exception
370
-
416
+ */
371
- cpu->midr = 0x410cc200;
417
+void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
372
-
418
+ vaddr addr, unsigned size,
373
- /*
419
+ MMUAccessType access_type,
374
- * These ID register values are not guest visible, because
420
+ int mmu_idx, MemTxAttrs attrs,
375
- * we do not implement the Main Extension. They must be set
421
+ MemTxResult response, uintptr_t retaddr)
376
- * to values corresponding to the Cortex-M0's implemented
422
+{
377
- * features, because QEMU generally controls its emulation
423
+ ARMCPU *cpu = ARM_CPU(cs);
378
- * by looking at ID register fields. We use the same values as
424
+ ARMMMUFaultInfo fi = {};
379
- * for the M3.
425
+
380
- */
426
+ /* now we have a real cpu fault */
381
- cpu->isar.id_pfr0 = 0x00000030;
427
+ cpu_restore_state(cs, retaddr, true);
382
- cpu->isar.id_pfr1 = 0x00000200;
428
+
383
- cpu->isar.id_dfr0 = 0x00100000;
429
+ fi.ea = arm_extabort_type(response);
384
- cpu->id_afr0 = 0x00000000;
430
+ fi.type = ARMFault_SyncExternal;
385
- cpu->isar.id_mmfr0 = 0x00000030;
431
+ arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi);
386
- cpu->isar.id_mmfr1 = 0x00000000;
432
+}
387
- cpu->isar.id_mmfr2 = 0x00000000;
433
+
388
- cpu->isar.id_mmfr3 = 0x00000000;
434
+#endif /* !defined(CONFIG_USER_ONLY) */
389
- cpu->isar.id_isar0 = 0x01141110;
435
+
390
- cpu->isar.id_isar1 = 0x02111000;
436
+bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
391
- cpu->isar.id_isar2 = 0x21112231;
437
+ MMUAccessType access_type, int mmu_idx,
392
- cpu->isar.id_isar3 = 0x01111110;
438
+ bool probe, uintptr_t retaddr)
393
- cpu->isar.id_isar4 = 0x01310102;
439
+{
394
- cpu->isar.id_isar5 = 0x00000000;
440
+ ARMCPU *cpu = ARM_CPU(cs);
395
- cpu->isar.id_isar6 = 0x00000000;
441
+
396
-}
442
+#ifdef CONFIG_USER_ONLY
397
-
443
+ cpu->env.exception.vaddress = address;
398
-static void cortex_m3_initfn(Object *obj)
444
+ if (access_type == MMU_INST_FETCH) {
399
-{
445
+ cs->exception_index = EXCP_PREFETCH_ABORT;
400
- ARMCPU *cpu = ARM_CPU(obj);
446
+ } else {
401
- set_feature(&cpu->env, ARM_FEATURE_V7);
447
+ cs->exception_index = EXCP_DATA_ABORT;
402
- set_feature(&cpu->env, ARM_FEATURE_M);
448
+ }
403
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
449
+ cpu_loop_exit_restore(cs, retaddr);
404
- cpu->midr = 0x410fc231;
450
+#else
405
- cpu->pmsav7_dregion = 8;
451
+ hwaddr phys_addr;
406
- cpu->isar.id_pfr0 = 0x00000030;
452
+ target_ulong page_size;
407
- cpu->isar.id_pfr1 = 0x00000200;
453
+ int prot, ret;
408
- cpu->isar.id_dfr0 = 0x00100000;
454
+ MemTxAttrs attrs = {};
409
- cpu->id_afr0 = 0x00000000;
455
+ ARMMMUFaultInfo fi = {};
410
- cpu->isar.id_mmfr0 = 0x00000030;
456
+
411
- cpu->isar.id_mmfr1 = 0x00000000;
457
+ /*
412
- cpu->isar.id_mmfr2 = 0x00000000;
458
+ * Walk the page table and (if the mapping exists) add the page
413
- cpu->isar.id_mmfr3 = 0x00000000;
459
+ * to the TLB. On success, return true. Otherwise, if probing,
414
- cpu->isar.id_isar0 = 0x01141110;
460
+ * return false. Otherwise populate fsr with ARM DFSR/IFSR fault
415
- cpu->isar.id_isar1 = 0x02111000;
461
+ * register format, and signal the fault.
416
- cpu->isar.id_isar2 = 0x21112231;
462
+ */
417
- cpu->isar.id_isar3 = 0x01111110;
463
+ ret = get_phys_addr(&cpu->env, address, access_type,
418
- cpu->isar.id_isar4 = 0x01310102;
464
+ core_to_arm_mmu_idx(&cpu->env, mmu_idx),
419
- cpu->isar.id_isar5 = 0x00000000;
465
+ &phys_addr, &attrs, &prot, &page_size, &fi, NULL);
420
- cpu->isar.id_isar6 = 0x00000000;
466
+ if (likely(!ret)) {
421
-}
467
+ /*
422
-
468
+ * Map a single [sub]page. Regions smaller than our declared
423
-static void cortex_m4_initfn(Object *obj)
469
+ * target page size are handled specially, so for those we
424
-{
470
+ * pass in the exact addresses.
425
- ARMCPU *cpu = ARM_CPU(obj);
471
+ */
426
-
472
+ if (page_size >= TARGET_PAGE_SIZE) {
427
- set_feature(&cpu->env, ARM_FEATURE_V7);
473
+ phys_addr &= TARGET_PAGE_MASK;
428
- set_feature(&cpu->env, ARM_FEATURE_M);
474
+ address &= TARGET_PAGE_MASK;
429
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
475
+ }
430
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
476
+ tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
431
- cpu->midr = 0x410fc240; /* r0p0 */
477
+ prot, mmu_idx, page_size);
432
- cpu->pmsav7_dregion = 8;
478
+ return true;
433
- cpu->isar.mvfr0 = 0x10110021;
479
+ } else if (probe) {
434
- cpu->isar.mvfr1 = 0x11000011;
480
+ return false;
435
- cpu->isar.mvfr2 = 0x00000000;
481
+ } else {
436
- cpu->isar.id_pfr0 = 0x00000030;
482
+ /* now we have a real cpu fault */
437
- cpu->isar.id_pfr1 = 0x00000200;
483
+ cpu_restore_state(cs, retaddr, true);
438
- cpu->isar.id_dfr0 = 0x00100000;
484
+ arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
439
- cpu->id_afr0 = 0x00000000;
485
+ }
440
- cpu->isar.id_mmfr0 = 0x00000030;
486
+#endif
441
- cpu->isar.id_mmfr1 = 0x00000000;
487
+}
442
- cpu->isar.id_mmfr2 = 0x00000000;
443
- cpu->isar.id_mmfr3 = 0x00000000;
444
- cpu->isar.id_isar0 = 0x01141110;
445
- cpu->isar.id_isar1 = 0x02111000;
446
- cpu->isar.id_isar2 = 0x21112231;
447
- cpu->isar.id_isar3 = 0x01111110;
448
- cpu->isar.id_isar4 = 0x01310102;
449
- cpu->isar.id_isar5 = 0x00000000;
450
- cpu->isar.id_isar6 = 0x00000000;
451
-}
452
-
453
-static void cortex_m7_initfn(Object *obj)
454
-{
455
- ARMCPU *cpu = ARM_CPU(obj);
456
-
457
- set_feature(&cpu->env, ARM_FEATURE_V7);
458
- set_feature(&cpu->env, ARM_FEATURE_M);
459
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
460
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
461
- cpu->midr = 0x411fc272; /* r1p2 */
462
- cpu->pmsav7_dregion = 8;
463
- cpu->isar.mvfr0 = 0x10110221;
464
- cpu->isar.mvfr1 = 0x12000011;
465
- cpu->isar.mvfr2 = 0x00000040;
466
- cpu->isar.id_pfr0 = 0x00000030;
467
- cpu->isar.id_pfr1 = 0x00000200;
468
- cpu->isar.id_dfr0 = 0x00100000;
469
- cpu->id_afr0 = 0x00000000;
470
- cpu->isar.id_mmfr0 = 0x00100030;
471
- cpu->isar.id_mmfr1 = 0x00000000;
472
- cpu->isar.id_mmfr2 = 0x01000000;
473
- cpu->isar.id_mmfr3 = 0x00000000;
474
- cpu->isar.id_isar0 = 0x01101110;
475
- cpu->isar.id_isar1 = 0x02112000;
476
- cpu->isar.id_isar2 = 0x20232231;
477
- cpu->isar.id_isar3 = 0x01111131;
478
- cpu->isar.id_isar4 = 0x01310132;
479
- cpu->isar.id_isar5 = 0x00000000;
480
- cpu->isar.id_isar6 = 0x00000000;
481
-}
482
-
483
-static void cortex_m33_initfn(Object *obj)
484
-{
485
- ARMCPU *cpu = ARM_CPU(obj);
486
-
487
- set_feature(&cpu->env, ARM_FEATURE_V8);
488
- set_feature(&cpu->env, ARM_FEATURE_M);
489
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
490
- set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
491
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
492
- cpu->midr = 0x410fd213; /* r0p3 */
493
- cpu->pmsav7_dregion = 16;
494
- cpu->sau_sregion = 8;
495
- cpu->isar.mvfr0 = 0x10110021;
496
- cpu->isar.mvfr1 = 0x11000011;
497
- cpu->isar.mvfr2 = 0x00000040;
498
- cpu->isar.id_pfr0 = 0x00000030;
499
- cpu->isar.id_pfr1 = 0x00000210;
500
- cpu->isar.id_dfr0 = 0x00200000;
501
- cpu->id_afr0 = 0x00000000;
502
- cpu->isar.id_mmfr0 = 0x00101F40;
503
- cpu->isar.id_mmfr1 = 0x00000000;
504
- cpu->isar.id_mmfr2 = 0x01000000;
505
- cpu->isar.id_mmfr3 = 0x00000000;
506
- cpu->isar.id_isar0 = 0x01101110;
507
- cpu->isar.id_isar1 = 0x02212000;
508
- cpu->isar.id_isar2 = 0x20232232;
509
- cpu->isar.id_isar3 = 0x01111131;
510
- cpu->isar.id_isar4 = 0x01310132;
511
- cpu->isar.id_isar5 = 0x00000000;
512
- cpu->isar.id_isar6 = 0x00000000;
513
- cpu->clidr = 0x00000000;
514
- cpu->ctr = 0x8000c000;
515
-}
516
-
517
-static void cortex_m55_initfn(Object *obj)
518
-{
519
- ARMCPU *cpu = ARM_CPU(obj);
520
-
521
- set_feature(&cpu->env, ARM_FEATURE_V8);
522
- set_feature(&cpu->env, ARM_FEATURE_V8_1M);
523
- set_feature(&cpu->env, ARM_FEATURE_M);
524
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
525
- set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
526
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
527
- cpu->midr = 0x410fd221; /* r0p1 */
528
- cpu->revidr = 0;
529
- cpu->pmsav7_dregion = 16;
530
- cpu->sau_sregion = 8;
531
- /* These are the MVFR* values for the FPU + full MVE configuration */
532
- cpu->isar.mvfr0 = 0x10110221;
533
- cpu->isar.mvfr1 = 0x12100211;
534
- cpu->isar.mvfr2 = 0x00000040;
535
- cpu->isar.id_pfr0 = 0x20000030;
536
- cpu->isar.id_pfr1 = 0x00000230;
537
- cpu->isar.id_dfr0 = 0x10200000;
538
- cpu->id_afr0 = 0x00000000;
539
- cpu->isar.id_mmfr0 = 0x00111040;
540
- cpu->isar.id_mmfr1 = 0x00000000;
541
- cpu->isar.id_mmfr2 = 0x01000000;
542
- cpu->isar.id_mmfr3 = 0x00000011;
543
- cpu->isar.id_isar0 = 0x01103110;
544
- cpu->isar.id_isar1 = 0x02212000;
545
- cpu->isar.id_isar2 = 0x20232232;
546
- cpu->isar.id_isar3 = 0x01111131;
547
- cpu->isar.id_isar4 = 0x01310132;
548
- cpu->isar.id_isar5 = 0x00000000;
549
- cpu->isar.id_isar6 = 0x00000000;
550
- cpu->clidr = 0x00000000; /* caches not implemented */
551
- cpu->ctr = 0x8303c003;
552
-}
553
-
554
static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
555
/* Dummy the TCM region regs for the moment */
556
{ .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
557
@@ -XXX,XX +XXX,XX @@ static void pxa270c5_initfn(Object *obj)
558
cpu->reset_sctlr = 0x00000078;
559
}
560
561
-static const TCGCPUOps arm_v7m_tcg_ops = {
562
- .initialize = arm_translate_init,
563
- .synchronize_from_tb = arm_cpu_synchronize_from_tb,
564
- .debug_excp_handler = arm_debug_excp_handler,
565
- .restore_state_to_opc = arm_restore_state_to_opc,
566
-
567
-#ifdef CONFIG_USER_ONLY
568
- .record_sigsegv = arm_cpu_record_sigsegv,
569
- .record_sigbus = arm_cpu_record_sigbus,
570
-#else
571
- .tlb_fill = arm_cpu_tlb_fill,
572
- .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
573
- .do_interrupt = arm_v7m_cpu_do_interrupt,
574
- .do_transaction_failed = arm_cpu_do_transaction_failed,
575
- .do_unaligned_access = arm_cpu_do_unaligned_access,
576
- .adjust_watchpoint_address = arm_adjust_watchpoint_address,
577
- .debug_check_watchpoint = arm_debug_check_watchpoint,
578
- .debug_check_breakpoint = arm_debug_check_breakpoint,
579
-#endif /* !CONFIG_USER_ONLY */
580
-};
581
-
582
-static void arm_v7m_class_init(ObjectClass *oc, void *data)
583
-{
584
- ARMCPUClass *acc = ARM_CPU_CLASS(oc);
585
- CPUClass *cc = CPU_CLASS(oc);
586
-
587
- acc->info = data;
588
- cc->tcg_ops = &arm_v7m_tcg_ops;
589
- cc->gdb_core_xml_file = "arm-m-profile.xml";
590
-}
591
-
592
#ifndef TARGET_AARCH64
593
/*
594
* -cpu max: a CPU with as many features enabled as our emulation supports.
595
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = {
596
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
597
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
598
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
599
- { .name = "cortex-m0", .initfn = cortex_m0_initfn,
600
- .class_init = arm_v7m_class_init },
601
- { .name = "cortex-m3", .initfn = cortex_m3_initfn,
602
- .class_init = arm_v7m_class_init },
603
- { .name = "cortex-m4", .initfn = cortex_m4_initfn,
604
- .class_init = arm_v7m_class_init },
605
- { .name = "cortex-m7", .initfn = cortex_m7_initfn,
606
- .class_init = arm_v7m_class_init },
607
- { .name = "cortex-m33", .initfn = cortex_m33_initfn,
608
- .class_init = arm_v7m_class_init },
609
- { .name = "cortex-m55", .initfn = cortex_m55_initfn,
610
- .class_init = arm_v7m_class_init },
611
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
612
{ .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
613
{ .name = "cortex-r52", .initfn = cortex_r52_initfn },
614
diff --git a/target/arm/meson.build b/target/arm/meson.build
615
index XXXXXXX..XXXXXXX 100644
616
--- a/target/arm/meson.build
617
+++ b/target/arm/meson.build
618
@@ -XXX,XX +XXX,XX @@ arm_system_ss.add(files(
619
'ptw.c',
620
))
621
622
+arm_user_ss = ss.source_set()
623
+
624
subdir('hvf')
625
626
if 'CONFIG_TCG' in config_all_accel
627
@@ -XXX,XX +XXX,XX @@ endif
628
629
target_arch += {'arm': arm_ss}
630
target_system_arch += {'arm': arm_system_ss}
631
+target_user_arch += {'arm': arm_user_ss}
632
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
633
index XXXXXXX..XXXXXXX 100644
634
--- a/target/arm/tcg/meson.build
635
+++ b/target/arm/tcg/meson.build
636
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
637
arm_system_ss.add(files(
638
'psci.c',
639
))
640
+
641
+arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c'))
642
+arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c'))
488
--
643
--
489
2.20.1
644
2.34.1
490
491
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
To ease the review of the next commit,
4
move the vfp_exceptbits_to_host() function directly after
5
vfp_exceptbits_from_host(). Amusingly the diff shows we
6
are moving vfp_get_fpscr().
7
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190701132516.26392-15-philmd@redhat.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/vfp_helper.c | 52 ++++++++++++++++++++---------------------
14
1 file changed, 26 insertions(+), 26 deletions(-)
15
16
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/vfp_helper.c
19
+++ b/target/arm/vfp_helper.c
20
@@ -XXX,XX +XXX,XX @@ static inline int vfp_exceptbits_from_host(int host_bits)
21
return target_bits;
22
}
23
24
-uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
25
-{
26
- uint32_t i, fpscr;
27
-
28
- fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
29
- | (env->vfp.vec_len << 16)
30
- | (env->vfp.vec_stride << 20);
31
-
32
- i = get_float_exception_flags(&env->vfp.fp_status);
33
- i |= get_float_exception_flags(&env->vfp.standard_fp_status);
34
- /* FZ16 does not generate an input denormal exception. */
35
- i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
36
- & ~float_flag_input_denormal);
37
- fpscr |= vfp_exceptbits_from_host(i);
38
-
39
- i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
40
- fpscr |= i ? FPCR_QC : 0;
41
-
42
- return fpscr;
43
-}
44
-
45
-uint32_t vfp_get_fpscr(CPUARMState *env)
46
-{
47
- return HELPER(vfp_get_fpscr)(env);
48
-}
49
-
50
/* Convert vfp exception flags to target form. */
51
static inline int vfp_exceptbits_to_host(int target_bits)
52
{
53
@@ -XXX,XX +XXX,XX @@ static inline int vfp_exceptbits_to_host(int target_bits)
54
return host_bits;
55
}
56
57
+uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
58
+{
59
+ uint32_t i, fpscr;
60
+
61
+ fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
62
+ | (env->vfp.vec_len << 16)
63
+ | (env->vfp.vec_stride << 20);
64
+
65
+ i = get_float_exception_flags(&env->vfp.fp_status);
66
+ i |= get_float_exception_flags(&env->vfp.standard_fp_status);
67
+ /* FZ16 does not generate an input denormal exception. */
68
+ i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
69
+ & ~float_flag_input_denormal);
70
+ fpscr |= vfp_exceptbits_from_host(i);
71
+
72
+ i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
73
+ fpscr |= i ? FPCR_QC : 0;
74
+
75
+ return fpscr;
76
+}
77
+
78
+uint32_t vfp_get_fpscr(CPUARMState *env)
79
+{
80
+ return HELPER(vfp_get_fpscr)(env);
81
+}
82
+
83
void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
84
{
85
int i;
86
--
87
2.20.1
88
89
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
The vfp_set_fpscr() helper contains code specific to the host
4
floating point implementation (here the SoftFloat library).
5
Extract this code to vfp_set_fpscr_to_host().
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20190701132516.26392-16-philmd@redhat.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/vfp_helper.c | 127 +++++++++++++++++++++-------------------
13
1 file changed, 66 insertions(+), 61 deletions(-)
14
15
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/vfp_helper.c
18
+++ b/target/arm/vfp_helper.c
19
@@ -XXX,XX +XXX,XX @@ static inline int vfp_exceptbits_to_host(int target_bits)
20
return host_bits;
21
}
22
23
-uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
24
-{
25
- uint32_t i, fpscr;
26
-
27
- fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
28
- | (env->vfp.vec_len << 16)
29
- | (env->vfp.vec_stride << 20);
30
-
31
- i = get_float_exception_flags(&env->vfp.fp_status);
32
- i |= get_float_exception_flags(&env->vfp.standard_fp_status);
33
- /* FZ16 does not generate an input denormal exception. */
34
- i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
35
- & ~float_flag_input_denormal);
36
- fpscr |= vfp_exceptbits_from_host(i);
37
-
38
- i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
39
- fpscr |= i ? FPCR_QC : 0;
40
-
41
- return fpscr;
42
-}
43
-
44
-uint32_t vfp_get_fpscr(CPUARMState *env)
45
-{
46
- return HELPER(vfp_get_fpscr)(env);
47
-}
48
-
49
-void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
50
+static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
51
{
52
int i;
53
uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];
54
55
- /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
56
- if (!cpu_isar_feature(aa64_fp16, env_archcpu(env))) {
57
- val &= ~FPCR_FZ16;
58
- }
59
-
60
- if (arm_feature(env, ARM_FEATURE_M)) {
61
- /*
62
- * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
63
- * and also for the trapped-exception-handling bits IxE.
64
- */
65
- val &= 0xf7c0009f;
66
- }
67
-
68
- /*
69
- * We don't implement trapped exception handling, so the
70
- * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
71
- *
72
- * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC
73
- * (which are stored in fp_status), and the other RES0 bits
74
- * in between, then we clear all of the low 16 bits.
75
- */
76
- env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
77
- env->vfp.vec_len = (val >> 16) & 7;
78
- env->vfp.vec_stride = (val >> 20) & 3;
79
-
80
- /*
81
- * The bit we set within fpscr_q is arbitrary; the register as a
82
- * whole being zero/non-zero is what counts.
83
- */
84
- env->vfp.qc[0] = val & FPCR_QC;
85
- env->vfp.qc[1] = 0;
86
- env->vfp.qc[2] = 0;
87
- env->vfp.qc[3] = 0;
88
-
89
changed ^= val;
90
if (changed & (3 << 22)) {
91
i = (val >> 22) & 3;
92
@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
93
set_float_exception_flags(0, &env->vfp.standard_fp_status);
94
}
95
96
+uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
97
+{
98
+ uint32_t i, fpscr;
99
+
100
+ fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
101
+ | (env->vfp.vec_len << 16)
102
+ | (env->vfp.vec_stride << 20);
103
+
104
+ i = get_float_exception_flags(&env->vfp.fp_status);
105
+ i |= get_float_exception_flags(&env->vfp.standard_fp_status);
106
+ /* FZ16 does not generate an input denormal exception. */
107
+ i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
108
+ & ~float_flag_input_denormal);
109
+ fpscr |= vfp_exceptbits_from_host(i);
110
+
111
+ i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
112
+ fpscr |= i ? FPCR_QC : 0;
113
+
114
+ return fpscr;
115
+}
116
+
117
+uint32_t vfp_get_fpscr(CPUARMState *env)
118
+{
119
+ return HELPER(vfp_get_fpscr)(env);
120
+}
121
+
122
+void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
123
+{
124
+ /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
125
+ if (!cpu_isar_feature(aa64_fp16, env_archcpu(env))) {
126
+ val &= ~FPCR_FZ16;
127
+ }
128
+
129
+ if (arm_feature(env, ARM_FEATURE_M)) {
130
+ /*
131
+ * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
132
+ * and also for the trapped-exception-handling bits IxE.
133
+ */
134
+ val &= 0xf7c0009f;
135
+ }
136
+
137
+ /*
138
+ * We don't implement trapped exception handling, so the
139
+ * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
140
+ *
141
+ * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC
142
+ * (which are stored in fp_status), and the other RES0 bits
143
+ * in between, then we clear all of the low 16 bits.
144
+ */
145
+ env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
146
+ env->vfp.vec_len = (val >> 16) & 7;
147
+ env->vfp.vec_stride = (val >> 20) & 3;
148
+
149
+ /*
150
+ * The bit we set within fpscr_q is arbitrary; the register as a
151
+ * whole being zero/non-zero is what counts.
152
+ */
153
+ env->vfp.qc[0] = val & FPCR_QC;
154
+ env->vfp.qc[1] = 0;
155
+ env->vfp.qc[2] = 0;
156
+ env->vfp.qc[3] = 0;
157
+
158
+ vfp_set_fpscr_to_host(env, val);
159
+}
160
+
161
void vfp_set_fpscr(CPUARMState *env, uint32_t val)
162
{
163
HELPER(vfp_set_fpscr)(env, val);
164
--
165
2.20.1
166
167
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
The vfp_set_fpscr() helper contains code specific to the host
4
floating point implementation (here the SoftFloat library).
5
Extract this code to vfp_set_fpscr_from_host().
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20190701132516.26392-17-philmd@redhat.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/vfp_helper.c | 19 +++++++++++++------
13
1 file changed, 13 insertions(+), 6 deletions(-)
14
15
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/vfp_helper.c
18
+++ b/target/arm/vfp_helper.c
19
@@ -XXX,XX +XXX,XX @@ static inline int vfp_exceptbits_to_host(int target_bits)
20
return host_bits;
21
}
22
23
+static uint32_t vfp_get_fpscr_from_host(CPUARMState *env)
24
+{
25
+ uint32_t i;
26
+
27
+ i = get_float_exception_flags(&env->vfp.fp_status);
28
+ i |= get_float_exception_flags(&env->vfp.standard_fp_status);
29
+ /* FZ16 does not generate an input denormal exception. */
30
+ i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
31
+ & ~float_flag_input_denormal);
32
+ return vfp_exceptbits_from_host(i);
33
+}
34
+
35
static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
36
{
37
int i;
38
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
39
| (env->vfp.vec_len << 16)
40
| (env->vfp.vec_stride << 20);
41
42
- i = get_float_exception_flags(&env->vfp.fp_status);
43
- i |= get_float_exception_flags(&env->vfp.standard_fp_status);
44
- /* FZ16 does not generate an input denormal exception. */
45
- i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
46
- & ~float_flag_input_denormal);
47
- fpscr |= vfp_exceptbits_from_host(i);
48
+ fpscr |= vfp_get_fpscr_from_host(env);
49
50
i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
51
fpscr |= i ? FPCR_QC : 0;
52
--
53
2.20.1
54
55
diff view generated by jsdifflib