[Qemu-devel] [PULL 00/46] target-arm queue
[PULL 00/24] target-arm queue
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target-arm queue for softfreeze: this is quite big as I
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The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:
2
was on holiday last week, so this is all just sneaking in
3
under the wire. I particularly wanted to get Philippe's
4
patches in before freeze as that sort of code-movement
5
patchset is painful to have to rebase.
6
2
7
thanks
3
Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)
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-- PMM
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The following changes since commit ae9108f8f0746ce64d02afb1a216153a50926132:
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12
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-4.1-pull-request' into staging (2019-07-01 15:55:40 +0100)
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4
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are available in the Git repository at:
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are available in the Git repository at:
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6
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190701
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702
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8
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for you to fetch changes up to 787a7e76c2e93a48c47b324fea592c9910a70483:
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for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:
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20
target/arm: Declare some M-profile functions publicly (2019-07-01 17:29:01 +0100)
11
target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)
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12
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----------------------------------------------------------------
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----------------------------------------------------------------
23
target-arm queue:
14
target-arm queue:
24
* hw/arm/boot: fix direct kernel boot with initrd
15
* more MVE instructions
25
* hw/arm/msf2-som: Exit when the cpu is not the expected one
16
* hw/gpio/gpio_pwr: use shutdown function for reboot
26
* i.mx7: fix bugs in PCI controller needed to boot recent kernels
17
* target/arm: Check NaN mode before silencing NaN
27
* aspeed: add RTC device
18
* tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
28
* aspeed: fix some timer device bugs
19
* hw/arm: Add basic power management to raspi.
29
* aspeed: add swift-bmc board
20
* docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc
30
* aspeed: vic: Add support for legacy register interface
31
* aspeed: add aspeed-xdma device
32
* Add new sbsa-ref board for aarch64
33
* target/arm: code refactoring in preparation for support of
34
compilation with TCG disabled
35
21
36
----------------------------------------------------------------
22
----------------------------------------------------------------
37
Adriana Kobylak (1):
23
Joe Komlodi (1):
38
aspeed: Add support for the swift-bmc board
24
target/arm: Check NaN mode before silencing NaN
39
25
40
Andrew Jeffery (3):
26
Maxim Uvarov (1):
41
aspeed/timer: Status register contains reload for stopped timer
27
hw/gpio/gpio_pwr: use shutdown function for reboot
42
aspeed/timer: Fix match calculations
43
aspeed: vic: Add support for legacy register interface
44
28
45
Andrew Jones (1):
29
Nolan Leake (1):
46
hw/arm/boot: fix direct kernel boot with initrd
30
hw/arm: Add basic power management to raspi.
47
31
48
Andrey Smirnov (5):
32
Patrick Venture (2):
49
i.mx7d: Add no-op/unimplemented APBH DMA module
33
docs/system/arm: Add quanta-q7l1-bmc reference
50
i.mx7d: Add no-op/unimplemented PCIE PHY IP block
34
docs/system/arm: Add quanta-gbs-bmc reference
51
pci: designware: Update MSI mapping unconditionally
52
pci: designware: Update MSI mapping when MSI address changes
53
i.mx7d: pci: Update PCI IRQ mapping to match HW
54
35
55
Christian Svensson (1):
36
Peter Maydell (18):
56
aspeed/timer: Ensure positive muldiv delta
37
target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
38
target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
39
target/arm: Make asimd_imm_const() public
40
target/arm: Use asimd_imm_const for A64 decode
41
target/arm: Use dup_const() instead of bitfield_replicate()
42
target/arm: Implement MVE logical immediate insns
43
target/arm: Implement MVE vector shift left by immediate insns
44
target/arm: Implement MVE vector shift right by immediate insns
45
target/arm: Implement MVE VSHLL
46
target/arm: Implement MVE VSRI, VSLI
47
target/arm: Implement MVE VSHRN, VRSHRN
48
target/arm: Implement MVE saturating narrowing shifts
49
target/arm: Implement MVE VSHLC
50
target/arm: Implement MVE VADDLV
51
target/arm: Implement MVE long shifts by immediate
52
target/arm: Implement MVE long shifts by register
53
target/arm: Implement MVE shifts by immediate
54
target/arm: Implement MVE shifts by register
57
55
58
Cédric Le Goater (7):
56
Philippe Mathieu-Daudé (1):
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aspeed: add a per SoC mapping for the interrupt space
57
tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
60
aspeed: add a per SoC mapping for the memory space
61
aspeed: introduce a configurable number of CPU per machine
62
aspeed: add support for multiple NICs
63
aspeed: remove the "ram" link
64
aspeed: add a RAM memory region container
65
aspeed/smc: add a 'sdram_base' property
66
58
67
Eddie James (1):
59
docs/system/arm/aspeed.rst | 1 +
68
hw/misc/aspeed_xdma: New device
60
docs/system/arm/nuvoton.rst | 5 +-
61
include/hw/arm/bcm2835_peripherals.h | 3 +-
62
include/hw/misc/bcm2835_powermgt.h | 29 ++
63
target/arm/helper-mve.h | 108 +++++++
64
target/arm/translate.h | 41 +++
65
target/arm/mve.decode | 177 ++++++++++-
66
target/arm/t32.decode | 71 ++++-
67
hw/arm/bcm2835_peripherals.c | 13 +-
68
hw/gpio/gpio_pwr.c | 2 +-
69
hw/misc/bcm2835_powermgt.c | 160 ++++++++++
70
target/arm/helper-a64.c | 12 +-
71
target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++--
72
target/arm/translate-a64.c | 86 +-----
73
target/arm/translate-mve.c | 261 +++++++++++++++-
74
target/arm/translate-neon.c | 81 -----
75
target/arm/translate.c | 327 +++++++++++++++++++-
76
target/arm/vfp_helper.c | 24 +-
77
hw/misc/meson.build | 1 +
78
tests/acceptance/boot_linux_console.py | 43 +++
79
20 files changed, 1760 insertions(+), 209 deletions(-)
80
create mode 100644 include/hw/misc/bcm2835_powermgt.h
81
create mode 100644 hw/misc/bcm2835_powermgt.c
69
82
70
Hongbo Zhang (2):
71
hw/arm: Add arm SBSA reference machine, skeleton part
72
hw/arm: Add arm SBSA reference machine, devices part
73
74
Jan Kiszka (1):
75
hw/arm/virt: Add support for Cortex-A7
76
77
Joel Stanley (4):
78
hw: timer: Add ASPEED RTC device
79
hw/arm/aspeed: Add RTC to SoC
80
aspeed/timer: Fix behaviour running Linux
81
aspeed: Link SCU to the watchdog
82
83
Philippe Mathieu-Daudé (19):
84
hw/arm/msf2-som: Exit when the cpu is not the expected one
85
target/arm: Makefile cleanup (Aarch64)
86
target/arm: Makefile cleanup (ARM)
87
target/arm: Makefile cleanup (KVM)
88
target/arm: Makefile cleanup (softmmu)
89
target/arm: Add copyright boilerplate
90
target/arm/helper: Remove unused include
91
target/arm: Fix multiline comment syntax
92
target/arm: Fix coding style issues
93
target/arm: Move CPU state dumping routines to cpu.c
94
target/arm: Declare get_phys_addr() function publicly
95
target/arm: Move TLB related routines to tlb_helper.c
96
target/arm/vfp_helper: Move code around
97
target/arm/vfp_helper: Extract vfp_set_fpscr_to_host()
98
target/arm/vfp_helper: Extract vfp_set_fpscr_from_host()
99
target/arm/vfp_helper: Restrict the SoftFloat use to TCG
100
target/arm: Restrict PSCI to TCG
101
target/arm: Declare arm_log_exception() function publicly
102
target/arm: Declare some M-profile functions publicly
103
104
Samuel Ortiz (1):
105
target/arm: Move the DC ZVA helper into op_helper
106
107
hw/arm/Makefile.objs | 1 +
108
hw/misc/Makefile.objs | 1 +
109
hw/timer/Makefile.objs | 2 +-
110
target/arm/Makefile.objs | 24 +-
111
include/hw/arm/aspeed_soc.h | 53 ++-
112
include/hw/arm/fsl-imx7.h | 14 +-
113
include/hw/misc/aspeed_xdma.h | 30 ++
114
include/hw/ssi/aspeed_smc.h | 3 +
115
include/hw/timer/aspeed_rtc.h | 31 ++
116
include/hw/watchdog/wdt_aspeed.h | 1 +
117
target/arm/cpu.h | 2 -
118
target/arm/internals.h | 69 ++-
119
target/arm/translate.h | 5 -
120
hw/arm/aspeed.c | 76 +++-
121
hw/arm/aspeed_soc.c | 262 +++++++++---
122
hw/arm/boot.c | 3 +-
123
hw/arm/fsl-imx7.c | 11 +
124
hw/arm/msf2-som.c | 1 +
125
hw/arm/sbsa-ref.c | 806 ++++++++++++++++++++++++++++++++++++
126
hw/arm/virt.c | 1 +
127
hw/intc/aspeed_vic.c | 105 +++--
128
hw/misc/aspeed_xdma.c | 165 ++++++++
129
hw/pci-host/designware.c | 18 +-
130
hw/ssi/aspeed_smc.c | 1 +
131
hw/timer/aspeed_rtc.c | 180 ++++++++
132
hw/timer/aspeed_timer.c | 76 ++--
133
hw/watchdog/wdt_aspeed.c | 20 +
134
target/arm/cpu.c | 232 ++++++++++-
135
target/arm/helper.c | 498 +++++++++-------------
136
target/arm/op_helper.c | 262 ++++++------
137
target/arm/tlb_helper.c | 200 +++++++++
138
target/arm/translate-a64.c | 128 ------
139
target/arm/translate.c | 91 +---
140
target/arm/vfp_helper.c | 199 +++++----
141
MAINTAINERS | 8 +
142
default-configs/aarch64-softmmu.mak | 1 +
143
hw/arm/Kconfig | 14 +
144
hw/misc/trace-events | 3 +
145
hw/timer/trace-events | 4 +
146
39 files changed, 2675 insertions(+), 926 deletions(-)
147
create mode 100644 include/hw/misc/aspeed_xdma.h
148
create mode 100644 include/hw/timer/aspeed_rtc.h
149
create mode 100644 hw/arm/sbsa-ref.c
150
create mode 100644 hw/misc/aspeed_xdma.c
151
create mode 100644 hw/timer/aspeed_rtc.c
152
create mode 100644 target/arm/tlb_helper.c
153
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/46] hw/arm/boot: fix direct kernel boot with initrd
Deleted patch
1
From: Andrew Jones <drjones@redhat.com>
2
1
3
Fix the condition used to check whether the initrd fits
4
into RAM; in some cases if an initrd was also passed on
5
the command line we would get an error stating that it
6
was too big to fit into RAM after the kernel. Despite the
7
error the loader continued anyway, though, so also add an
8
exit(1) when the initrd is actually too big.
9
10
Fixes: 852dc64d665f ("hw/arm/boot: Diagnose layouts that put initrd or
11
DTB off the end of RAM")
12
Signed-off-by: Andrew Jones <drjones@redhat.com>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Message-id: 20190618125844.4863-1-drjones@redhat.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/arm/boot.c | 3 ++-
18
1 file changed, 2 insertions(+), 1 deletion(-)
19
20
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/boot.c
23
+++ b/hw/arm/boot.c
24
@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
25
info->initrd_filename);
26
exit(1);
27
}
28
- if (info->initrd_start + initrd_size > info->ram_size) {
29
+ if (info->initrd_start + initrd_size > ram_end) {
30
error_report("could not load initrd '%s': "
31
"too big to fit into RAM after the kernel",
32
info->initrd_filename);
33
+ exit(1);
34
}
35
} else {
36
initrd_size = 0;
37
--
38
2.20.1
39
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/46] hw/arm/msf2-som: Exit when the cpu is not the expected one
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
This machine correctly defines its default_cpu_type to cortex-m3
4
and report an error if the user requested another cpu_type,
5
however it does not exit, and this can confuse users trying
6
to use another core:
7
8
$ qemu-system-arm -M emcraft-sf2 -cpu cortex-m4 -kernel test-m4.elf
9
qemu-system-arm: This board can only be used with CPU cortex-m3-arm-cpu
10
[output related to M3 core ...]
11
12
The CPU is indeed a M3 core:
13
14
(qemu) info qom-tree
15
/machine (emcraft-sf2-machine)
16
/unattached (container)
17
/device[0] (msf2-soc)
18
/armv7m (armv7m)
19
/cpu (cortex-m3-arm-cpu)
20
21
Add the missing exit() call to return to the shell.
22
23
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
24
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
25
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
26
Message-id: 20190617160136.29930-1-philmd@redhat.com
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
---
29
hw/arm/msf2-som.c | 1 +
30
1 file changed, 1 insertion(+)
31
32
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/msf2-som.c
35
+++ b/hw/arm/msf2-som.c
36
@@ -XXX,XX +XXX,XX @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
37
if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
38
error_report("This board can only be used with CPU %s",
39
mc->default_cpu_type);
40
+ exit(1);
41
}
42
43
memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
44
--
45
2.20.1
46
47
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/46] hw/arm/virt: Add support for Cortex-A7
[PULL 01/24] docs/system/arm: Add quanta-q7l1-bmc reference
1
From: Jan Kiszka <jan.kiszka@siemens.com>
1
From: Patrick Venture <venture@google.com>
2
2
3
Allow cortex-a7 to be used with the virt board; it supports
3
Adds a line-item reference to the supported quanta-q71l-bmc aspeed
4
the v7VE features and there is no reason to deny this type.
4
entry.
5
5
6
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
6
Signed-off-by: Patrick Venture <venture@google.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: fc5404f7-4d1d-c28f-6e48-d8799c82acc0@web.de
8
Message-id: 20210615192848.1065297-2-venture@google.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
hw/arm/virt.c | 1 +
11
docs/system/arm/aspeed.rst | 1 +
13
1 file changed, 1 insertion(+)
12
1 file changed, 1 insertion(+)
14
13
15
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/virt.c
16
--- a/docs/system/arm/aspeed.rst
18
+++ b/hw/arm/virt.c
17
+++ b/docs/system/arm/aspeed.rst
19
@@ -XXX,XX +XXX,XX @@ static const int a15irqmap[] = {
18
@@ -XXX,XX +XXX,XX @@ etc.
20
};
19
AST2400 SoC based machines :
21
20
22
static const char *valid_cpus[] = {
21
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
23
+ ARM_CPU_TYPE_NAME("cortex-a7"),
22
+- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
24
ARM_CPU_TYPE_NAME("cortex-a15"),
23
25
ARM_CPU_TYPE_NAME("cortex-a53"),
24
AST2500 SoC based machines :
26
ARM_CPU_TYPE_NAME("cortex-a57"),
25
27
--
26
--
28
2.20.1
27
2.20.1
29
28
30
29
diff view generated by jsdifflib
[Qemu-devel] [PULL 28/46] target/arm: Makefile cleanup (Aarch64)
[PULL 02/24] docs/system/arm: Add quanta-gbs-bmc reference
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Patrick Venture <venture@google.com>
2
2
3
Group Aarch64 rules together, TCG related ones at the bottom.
3
Add line item reference to quanta-gbs-bmc machine.
4
This will help when restricting TCG-only objects.
5
4
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Signed-off-by: Patrick Venture <venture@google.com>
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: 20190701132516.26392-2-philmd@redhat.com
7
Message-id: 20210615192848.1065297-3-venture@google.com
8
[PMM: fixed underline Sphinx warning]
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/Makefile.objs | 5 +++--
11
docs/system/arm/nuvoton.rst | 5 +++--
12
1 file changed, 3 insertions(+), 2 deletions(-)
12
1 file changed, 3 insertions(+), 2 deletions(-)
13
13
14
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
14
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/Makefile.objs
16
--- a/docs/system/arm/nuvoton.rst
17
+++ b/target/arm/Makefile.objs
17
+++ b/docs/system/arm/nuvoton.rst
18
@@ -XXX,XX +XXX,XX @@ obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
18
@@ -XXX,XX +XXX,XX @@
19
obj-y += translate.o op_helper.o helper.o cpu.o
19
-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
20
obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o vfp_helper.o
20
-=====================================================
21
obj-y += gdbstub.o
21
+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
22
-obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o
22
+================================================================
23
-obj-$(TARGET_AARCH64) += pauth_helper.o
23
24
+obj-$(TARGET_AARCH64) += cpu64.o gdbstub64.o
24
The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
25
obj-y += crypto_helper.o
25
designed to be used as Baseboard Management Controllers (BMCs) in various
26
obj-$(CONFIG_SOFTMMU) += arm-powerctl.o
26
@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
27
27
The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
28
@@ -XXX,XX +XXX,XX @@ target/arm/translate-sve.o: target/arm/decode-sve.inc.c
28
Hyperscale applications. The following machines are based on this chip :
29
target/arm/translate.o: target/arm/decode-vfp.inc.c
29
30
target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
30
+- ``quanta-gbs-bmc`` Quanta GBS server BMC
31
31
- ``quanta-gsj`` Quanta GSJ server BMC
32
+obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o
32
33
obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o
33
There are also two more SoCs, NPCM710 and NPCM705, which are single-core
34
+obj-$(TARGET_AARCH64) += pauth_helper.o
35
--
34
--
36
2.20.1
35
2.20.1
37
36
38
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 23/46] hw/misc/aspeed_xdma: New device
[PULL 03/24] hw/arm: Add basic power management to raspi.
1
From: Eddie James <eajames@linux.ibm.com>
1
From: Nolan Leake <nolan@sigbus.net>
2
2
3
The XDMA engine embedded in the Aspeed SOCs performs PCI DMA operations
3
This is just enough to make reboot and poweroff work. Works for
4
between the SOC (acting as a BMC) and a host processor in a server.
4
linux, u-boot, and the arm trusted firmware. Not tested, but should
5
5
work for plan9, and bare-metal/hobby OSes, since they seem to generally
6
The XDMA engine exists on the AST2400, AST2500, and AST2600 SOCs, so
6
do what linux does for reset.
7
enable it for all of those. Add trace events on the important register
7
8
writes in the XDMA engine.
8
The watchdog timer functionality is not yet implemented.
9
9
10
Signed-off-by: Eddie James <eajames@linux.ibm.com>
10
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Signed-off-by: Nolan Leake <nolan@sigbus.net>
12
Signed-off-by: Cédric Le Goater <clg@kaod.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20190618165311.27066-21-clg@kaod.org
13
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
[clg: - changed title ]
14
Message-id: 20210625210209.1870217-1-nolan@sigbus.net
15
Signed-off-by: Cédric Le Goater <clg@kaod.org>
15
[PMM: tweaked commit title; fixed region size to 0x200;
16
moved header file to include/]
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
---
18
hw/misc/Makefile.objs | 1 +
19
include/hw/arm/bcm2835_peripherals.h | 3 +-
19
include/hw/arm/aspeed_soc.h | 3 +
20
include/hw/misc/bcm2835_powermgt.h | 29 +++++
20
include/hw/misc/aspeed_xdma.h | 30 +++++++
21
hw/arm/bcm2835_peripherals.c | 13 ++-
21
hw/arm/aspeed_soc.c | 17 ++++
22
hw/misc/bcm2835_powermgt.c | 160 +++++++++++++++++++++++++++
22
hw/misc/aspeed_xdma.c | 165 ++++++++++++++++++++++++++++++++++
23
hw/misc/meson.build | 1 +
23
hw/misc/trace-events | 3 +
24
5 files changed, 204 insertions(+), 2 deletions(-)
24
6 files changed, 219 insertions(+)
25
create mode 100644 include/hw/misc/bcm2835_powermgt.h
25
create mode 100644 include/hw/misc/aspeed_xdma.h
26
create mode 100644 hw/misc/bcm2835_powermgt.c
26
create mode 100644 hw/misc/aspeed_xdma.c
27
27
28
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
28
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
29
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/misc/Makefile.objs
30
--- a/include/hw/arm/bcm2835_peripherals.h
31
+++ b/hw/misc/Makefile.objs
31
+++ b/include/hw/arm/bcm2835_peripherals.h
32
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_ARMSSE_MHU) += armsse-mhu.o
33
34
obj-$(CONFIG_PVPANIC) += pvpanic.o
35
obj-$(CONFIG_AUX) += auxbus.o
36
+obj-$(CONFIG_ASPEED_SOC) += aspeed_xdma.o
37
obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
38
obj-$(CONFIG_MSF2) += msf2-sysreg.o
39
obj-$(CONFIG_NRF51_SOC) += nrf51_rng.o
40
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
41
index XXXXXXX..XXXXXXX 100644
42
--- a/include/hw/arm/aspeed_soc.h
43
+++ b/include/hw/arm/aspeed_soc.h
44
@@ -XXX,XX +XXX,XX @@
32
@@ -XXX,XX +XXX,XX @@
45
#include "hw/intc/aspeed_vic.h"
33
#include "hw/misc/bcm2835_mphi.h"
46
#include "hw/misc/aspeed_scu.h"
34
#include "hw/misc/bcm2835_thermal.h"
47
#include "hw/misc/aspeed_sdmc.h"
35
#include "hw/misc/bcm2835_cprman.h"
48
+#include "hw/misc/aspeed_xdma.h"
36
+#include "hw/misc/bcm2835_powermgt.h"
49
#include "hw/timer/aspeed_timer.h"
37
#include "hw/sd/sdhci.h"
50
#include "hw/timer/aspeed_rtc.h"
38
#include "hw/sd/bcm2835_sdhost.h"
51
#include "hw/i2c/aspeed_i2c.h"
39
#include "hw/gpio/bcm2835_gpio.h"
52
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
40
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
53
AspeedTimerCtrlState timerctrl;
41
BCM2835MphiState mphi;
54
AspeedI2CState i2c;
42
UnimplementedDeviceState txp;
55
AspeedSCUState scu;
43
UnimplementedDeviceState armtmr;
56
+ AspeedXDMAState xdma;
44
- UnimplementedDeviceState powermgt;
57
AspeedSMCState fmc;
45
+ BCM2835PowerMgtState powermgt;
58
AspeedSMCState spi[ASPEED_SPIS_NUM];
46
BCM2835CprmanState cprman;
59
AspeedSDMCState sdmc;
47
PL011State uart0;
60
@@ -XXX,XX +XXX,XX @@ enum {
48
BCM2835AuxState aux;
61
ASPEED_ETH1,
49
diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
62
ASPEED_ETH2,
63
ASPEED_SDRAM,
64
+ ASPEED_XDMA,
65
};
66
67
#endif /* ASPEED_SOC_H */
68
diff --git a/include/hw/misc/aspeed_xdma.h b/include/hw/misc/aspeed_xdma.h
69
new file mode 100644
50
new file mode 100644
70
index XXXXXXX..XXXXXXX
51
index XXXXXXX..XXXXXXX
71
--- /dev/null
52
--- /dev/null
72
+++ b/include/hw/misc/aspeed_xdma.h
53
+++ b/include/hw/misc/bcm2835_powermgt.h
73
@@ -XXX,XX +XXX,XX @@
54
@@ -XXX,XX +XXX,XX @@
74
+/*
55
+/*
75
+ * ASPEED XDMA Controller
56
+ * BCM2835 Power Management emulation
76
+ * Eddie James <eajames@linux.ibm.com>
57
+ *
77
+ *
58
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
78
+ * Copyright (C) 2019 IBM Corp.
59
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
79
+ * SPDX-License-Identifer: GPL-2.0-or-later
60
+ *
61
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
62
+ * See the COPYING file in the top-level directory.
80
+ */
63
+ */
81
+
64
+
82
+#ifndef ASPEED_XDMA_H
65
+#ifndef BCM2835_POWERMGT_H
83
+#define ASPEED_XDMA_H
66
+#define BCM2835_POWERMGT_H
84
+
67
+
85
+#include "hw/sysbus.h"
68
+#include "hw/sysbus.h"
86
+
69
+#include "qom/object.h"
87
+#define TYPE_ASPEED_XDMA "aspeed.xdma"
70
+
88
+#define ASPEED_XDMA(obj) OBJECT_CHECK(AspeedXDMAState, (obj), TYPE_ASPEED_XDMA)
71
+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
89
+
72
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
90
+#define ASPEED_XDMA_NUM_REGS (ASPEED_XDMA_REG_SIZE / sizeof(uint32_t))
73
+
91
+#define ASPEED_XDMA_REG_SIZE 0x7C
74
+struct BCM2835PowerMgtState {
92
+
75
+ SysBusDevice busdev;
93
+typedef struct AspeedXDMAState {
94
+ SysBusDevice parent;
95
+
96
+ MemoryRegion iomem;
76
+ MemoryRegion iomem;
97
+ qemu_irq irq;
77
+
98
+
78
+ uint32_t rstc;
99
+ char bmc_cmdq_readp_set;
79
+ uint32_t rsts;
100
+ uint32_t regs[ASPEED_XDMA_NUM_REGS];
80
+ uint32_t wdog;
101
+} AspeedXDMAState;
81
+};
102
+
82
+
103
+#endif /* ASPEED_XDMA_H */
83
+#endif
104
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
84
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
105
index XXXXXXX..XXXXXXX 100644
85
index XXXXXXX..XXXXXXX 100644
106
--- a/hw/arm/aspeed_soc.c
86
--- a/hw/arm/bcm2835_peripherals.c
107
+++ b/hw/arm/aspeed_soc.c
87
+++ b/hw/arm/bcm2835_peripherals.c
108
@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2400_memmap[] = {
88
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
109
[ASPEED_VIC] = 0x1E6C0000,
89
110
[ASPEED_SDMC] = 0x1E6E0000,
90
object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
111
[ASPEED_SCU] = 0x1E6E2000,
91
OBJECT(&s->gpu_bus_mr));
112
+ [ASPEED_XDMA] = 0x1E6E7000,
92
+
113
[ASPEED_ADC] = 0x1E6E9000,
93
+ /* Power Management */
114
[ASPEED_SRAM] = 0x1E720000,
94
+ object_initialize_child(obj, "powermgt", &s->powermgt,
115
[ASPEED_GPIO] = 0x1E780000,
95
+ TYPE_BCM2835_POWERMGT);
116
@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2500_memmap[] = {
117
[ASPEED_VIC] = 0x1E6C0000,
118
[ASPEED_SDMC] = 0x1E6E0000,
119
[ASPEED_SCU] = 0x1E6E2000,
120
+ [ASPEED_XDMA] = 0x1E6E7000,
121
[ASPEED_ADC] = 0x1E6E9000,
122
[ASPEED_SRAM] = 0x1E720000,
123
[ASPEED_GPIO] = 0x1E780000,
124
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2400_irqmap[] = {
125
[ASPEED_I2C] = 12,
126
[ASPEED_ETH1] = 2,
127
[ASPEED_ETH2] = 3,
128
+ [ASPEED_XDMA] = 6,
129
};
130
131
#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
132
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
133
sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
134
sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
135
}
136
+
137
+ sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
138
+ TYPE_ASPEED_XDMA);
139
}
96
}
140
97
141
static void aspeed_soc_realize(DeviceState *dev, Error **errp)
98
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
142
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
99
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
143
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
100
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
144
aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
101
INTERRUPT_USB));
145
}
102
146
+
103
+ /* Power Management */
147
+ /* XDMA */
104
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
148
+ object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
149
+ if (err) {
150
+ error_propagate(errp, err);
151
+ return;
105
+ return;
152
+ }
106
+ }
153
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
107
+
154
+ sc->info->memmap[ASPEED_XDMA]);
108
+ memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
155
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
109
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
156
+ aspeed_soc_get_irq(s, ASPEED_XDMA));
110
+
157
}
111
create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
158
static Property aspeed_soc_properties[] = {
112
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
159
DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
113
- create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
160
diff --git a/hw/misc/aspeed_xdma.c b/hw/misc/aspeed_xdma.c
114
create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
115
create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
116
create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
117
diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
161
new file mode 100644
118
new file mode 100644
162
index XXXXXXX..XXXXXXX
119
index XXXXXXX..XXXXXXX
163
--- /dev/null
120
--- /dev/null
164
+++ b/hw/misc/aspeed_xdma.c
121
+++ b/hw/misc/bcm2835_powermgt.c
165
@@ -XXX,XX +XXX,XX @@
122
@@ -XXX,XX +XXX,XX @@
166
+/*
123
+/*
167
+ * ASPEED XDMA Controller
124
+ * BCM2835 Power Management emulation
168
+ * Eddie James <eajames@linux.ibm.com>
125
+ *
169
+ *
126
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
170
+ * Copyright (C) 2019 IBM Corp
127
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
171
+ * SPDX-License-Identifer: GPL-2.0-or-later
128
+ *
129
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
130
+ * See the COPYING file in the top-level directory.
172
+ */
131
+ */
173
+
132
+
174
+#include "qemu/osdep.h"
133
+#include "qemu/osdep.h"
175
+#include "qemu/log.h"
134
+#include "qemu/log.h"
176
+#include "qemu/error-report.h"
135
+#include "qemu/module.h"
177
+#include "hw/misc/aspeed_xdma.h"
136
+#include "hw/misc/bcm2835_powermgt.h"
178
+#include "qapi/error.h"
137
+#include "migration/vmstate.h"
179
+
138
+#include "sysemu/runstate.h"
180
+#include "trace.h"
139
+
181
+
140
+#define PASSWORD 0x5a000000
182
+#define XDMA_BMC_CMDQ_ADDR 0x10
141
+#define PASSWORD_MASK 0xff000000
183
+#define XDMA_BMC_CMDQ_ENDP 0x14
142
+
184
+#define XDMA_BMC_CMDQ_WRP 0x18
143
+#define R_RSTC 0x1c
185
+#define XDMA_BMC_CMDQ_W_MASK 0x0003FFFF
144
+#define V_RSTC_RESET 0x20
186
+#define XDMA_BMC_CMDQ_RDP 0x1C
145
+#define R_RSTS 0x20
187
+#define XDMA_BMC_CMDQ_RDP_MAGIC 0xEE882266
146
+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
188
+#define XDMA_IRQ_ENG_CTRL 0x20
147
+#define R_WDOG 0x24
189
+#define XDMA_IRQ_ENG_CTRL_US_COMP BIT(4)
148
+
190
+#define XDMA_IRQ_ENG_CTRL_DS_COMP BIT(5)
149
+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
191
+#define XDMA_IRQ_ENG_CTRL_W_MASK 0xBFEFF07F
150
+ unsigned size)
192
+#define XDMA_IRQ_ENG_STAT 0x24
151
+{
193
+#define XDMA_IRQ_ENG_STAT_US_COMP BIT(4)
152
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
194
+#define XDMA_IRQ_ENG_STAT_DS_COMP BIT(5)
153
+ uint32_t res = 0;
195
+#define XDMA_IRQ_ENG_STAT_RESET 0xF8000000
154
+
196
+#define XDMA_MEM_SIZE 0x1000
155
+ switch (offset) {
197
+
156
+ case R_RSTC:
198
+#define TO_REG(addr) ((addr) / sizeof(uint32_t))
157
+ res = s->rstc;
199
+
158
+ break;
200
+static uint64_t aspeed_xdma_read(void *opaque, hwaddr addr, unsigned int size)
159
+ case R_RSTS:
201
+{
160
+ res = s->rsts;
202
+ uint32_t val = 0;
161
+ break;
203
+ AspeedXDMAState *xdma = opaque;
162
+ case R_WDOG:
204
+
163
+ res = s->wdog;
205
+ if (addr < ASPEED_XDMA_REG_SIZE) {
164
+ break;
206
+ val = xdma->regs[TO_REG(addr)];
165
+
207
+ }
166
+ default:
208
+
167
+ qemu_log_mask(LOG_UNIMP,
209
+ return (uint64_t)val;
168
+ "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
210
+}
169
+ "\n", offset);
211
+
170
+ res = 0;
212
+static void aspeed_xdma_write(void *opaque, hwaddr addr, uint64_t val,
171
+ break;
213
+ unsigned int size)
172
+ }
214
+{
173
+
215
+ unsigned int idx;
174
+ return res;
216
+ uint32_t val32 = (uint32_t)val;
175
+}
217
+ AspeedXDMAState *xdma = opaque;
176
+
218
+
177
+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
219
+ if (addr >= ASPEED_XDMA_REG_SIZE) {
178
+ uint64_t value, unsigned size)
179
+{
180
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
181
+
182
+ if ((value & PASSWORD_MASK) != PASSWORD) {
183
+ qemu_log_mask(LOG_GUEST_ERROR,
184
+ "bcm2835_powermgt_write: Bad password 0x%"PRIx64
185
+ " at offset 0x%08"HWADDR_PRIx"\n",
186
+ value, offset);
220
+ return;
187
+ return;
221
+ }
188
+ }
222
+
189
+
223
+ switch (addr) {
190
+ value = value & ~PASSWORD_MASK;
224
+ case XDMA_BMC_CMDQ_ENDP:
191
+
225
+ xdma->regs[TO_REG(addr)] = val32 & XDMA_BMC_CMDQ_W_MASK;
192
+ switch (offset) {
226
+ break;
193
+ case R_RSTC:
227
+ case XDMA_BMC_CMDQ_WRP:
194
+ s->rstc = value;
228
+ idx = TO_REG(addr);
195
+ if (value & V_RSTC_RESET) {
229
+ xdma->regs[idx] = val32 & XDMA_BMC_CMDQ_W_MASK;
196
+ if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
230
+ xdma->regs[TO_REG(XDMA_BMC_CMDQ_RDP)] = xdma->regs[idx];
197
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
231
+
198
+ } else {
232
+ trace_aspeed_xdma_write(addr, val);
199
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
233
+
200
+ }
234
+ if (xdma->bmc_cmdq_readp_set) {
235
+ xdma->bmc_cmdq_readp_set = 0;
236
+ } else {
237
+ xdma->regs[TO_REG(XDMA_IRQ_ENG_STAT)] |=
238
+ XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP;
239
+
240
+ if (xdma->regs[TO_REG(XDMA_IRQ_ENG_CTRL)] &
241
+ (XDMA_IRQ_ENG_CTRL_US_COMP | XDMA_IRQ_ENG_CTRL_DS_COMP))
242
+ qemu_irq_raise(xdma->irq);
243
+ }
201
+ }
244
+ break;
202
+ break;
245
+ case XDMA_BMC_CMDQ_RDP:
203
+ case R_RSTS:
246
+ trace_aspeed_xdma_write(addr, val);
204
+ qemu_log_mask(LOG_UNIMP,
247
+
205
+ "bcm2835_powermgt_write: RSTS\n");
248
+ if (val32 == XDMA_BMC_CMDQ_RDP_MAGIC) {
206
+ s->rsts = value;
249
+ xdma->bmc_cmdq_readp_set = 1;
207
+ break;
250
+ }
208
+ case R_WDOG:
251
+ break;
209
+ qemu_log_mask(LOG_UNIMP,
252
+ case XDMA_IRQ_ENG_CTRL:
210
+ "bcm2835_powermgt_write: WDOG\n");
253
+ xdma->regs[TO_REG(addr)] = val32 & XDMA_IRQ_ENG_CTRL_W_MASK;
211
+ s->wdog = value;
254
+ break;
212
+ break;
255
+ case XDMA_IRQ_ENG_STAT:
213
+
256
+ trace_aspeed_xdma_write(addr, val);
257
+
258
+ idx = TO_REG(addr);
259
+ if (val32 & (XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP)) {
260
+ xdma->regs[idx] &=
261
+ ~(XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP);
262
+ qemu_irq_lower(xdma->irq);
263
+ }
264
+ break;
265
+ default:
214
+ default:
266
+ xdma->regs[TO_REG(addr)] = val32;
215
+ qemu_log_mask(LOG_UNIMP,
267
+ break;
216
+ "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
268
+ }
217
+ "\n", offset);
269
+}
218
+ break;
270
+
219
+ }
271
+static const MemoryRegionOps aspeed_xdma_ops = {
220
+}
272
+ .read = aspeed_xdma_read,
221
+
273
+ .write = aspeed_xdma_write,
222
+static const MemoryRegionOps bcm2835_powermgt_ops = {
223
+ .read = bcm2835_powermgt_read,
224
+ .write = bcm2835_powermgt_write,
274
+ .endianness = DEVICE_NATIVE_ENDIAN,
225
+ .endianness = DEVICE_NATIVE_ENDIAN,
275
+ .valid.min_access_size = 4,
226
+ .impl.min_access_size = 4,
276
+ .valid.max_access_size = 4,
227
+ .impl.max_access_size = 4,
277
+};
228
+};
278
+
229
+
279
+static void aspeed_xdma_realize(DeviceState *dev, Error **errp)
230
+static const VMStateDescription vmstate_bcm2835_powermgt = {
280
+{
231
+ .name = TYPE_BCM2835_POWERMGT,
281
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
282
+ AspeedXDMAState *xdma = ASPEED_XDMA(dev);
283
+
284
+ sysbus_init_irq(sbd, &xdma->irq);
285
+ memory_region_init_io(&xdma->iomem, OBJECT(xdma), &aspeed_xdma_ops, xdma,
286
+ TYPE_ASPEED_XDMA, XDMA_MEM_SIZE);
287
+ sysbus_init_mmio(sbd, &xdma->iomem);
288
+}
289
+
290
+static void aspeed_xdma_reset(DeviceState *dev)
291
+{
292
+ AspeedXDMAState *xdma = ASPEED_XDMA(dev);
293
+
294
+ xdma->bmc_cmdq_readp_set = 0;
295
+ memset(xdma->regs, 0, ASPEED_XDMA_REG_SIZE);
296
+ xdma->regs[TO_REG(XDMA_IRQ_ENG_STAT)] = XDMA_IRQ_ENG_STAT_RESET;
297
+
298
+ qemu_irq_lower(xdma->irq);
299
+}
300
+
301
+static const VMStateDescription aspeed_xdma_vmstate = {
302
+ .name = TYPE_ASPEED_XDMA,
303
+ .version_id = 1,
232
+ .version_id = 1,
233
+ .minimum_version_id = 1,
304
+ .fields = (VMStateField[]) {
234
+ .fields = (VMStateField[]) {
305
+ VMSTATE_UINT32_ARRAY(regs, AspeedXDMAState, ASPEED_XDMA_NUM_REGS),
235
+ VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
306
+ VMSTATE_END_OF_LIST(),
236
+ VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
307
+ },
237
+ VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
308
+};
238
+ VMSTATE_END_OF_LIST()
309
+
239
+ }
310
+static void aspeed_xdma_class_init(ObjectClass *classp, void *data)
240
+};
311
+{
241
+
312
+ DeviceClass *dc = DEVICE_CLASS(classp);
242
+static void bcm2835_powermgt_init(Object *obj)
313
+
243
+{
314
+ dc->realize = aspeed_xdma_realize;
244
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
315
+ dc->reset = aspeed_xdma_reset;
245
+
316
+ dc->vmsd = &aspeed_xdma_vmstate;
246
+ memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
317
+}
247
+ TYPE_BCM2835_POWERMGT, 0x200);
318
+
248
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
319
+static const TypeInfo aspeed_xdma_info = {
249
+}
320
+ .name = TYPE_ASPEED_XDMA,
250
+
251
+static void bcm2835_powermgt_reset(DeviceState *dev)
252
+{
253
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
254
+
255
+ /* https://elinux.org/BCM2835_registers#PM */
256
+ s->rstc = 0x00000102;
257
+ s->rsts = 0x00001000;
258
+ s->wdog = 0x00000000;
259
+}
260
+
261
+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
262
+{
263
+ DeviceClass *dc = DEVICE_CLASS(klass);
264
+
265
+ dc->reset = bcm2835_powermgt_reset;
266
+ dc->vmsd = &vmstate_bcm2835_powermgt;
267
+}
268
+
269
+static TypeInfo bcm2835_powermgt_info = {
270
+ .name = TYPE_BCM2835_POWERMGT,
321
+ .parent = TYPE_SYS_BUS_DEVICE,
271
+ .parent = TYPE_SYS_BUS_DEVICE,
322
+ .instance_size = sizeof(AspeedXDMAState),
272
+ .instance_size = sizeof(BCM2835PowerMgtState),
323
+ .class_init = aspeed_xdma_class_init,
273
+ .class_init = bcm2835_powermgt_class_init,
324
+};
274
+ .instance_init = bcm2835_powermgt_init,
325
+
275
+};
326
+static void aspeed_xdma_register_type(void)
276
+
327
+{
277
+static void bcm2835_powermgt_register_types(void)
328
+ type_register_static(&aspeed_xdma_info);
278
+{
329
+}
279
+ type_register_static(&bcm2835_powermgt_info);
330
+type_init(aspeed_xdma_register_type);
280
+}
331
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
281
+
282
+type_init(bcm2835_powermgt_register_types)
283
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
332
index XXXXXXX..XXXXXXX 100644
284
index XXXXXXX..XXXXXXX 100644
333
--- a/hw/misc/trace-events
285
--- a/hw/misc/meson.build
334
+++ b/hw/misc/trace-events
286
+++ b/hw/misc/meson.build
335
@@ -XXX,XX +XXX,XX @@ armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_I
287
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
336
# armsse-mhu.c
288
'bcm2835_rng.c',
337
armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
289
'bcm2835_thermal.c',
338
armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
290
'bcm2835_cprman.c',
339
+
291
+ 'bcm2835_powermgt.c',
340
+# aspeed_xdma.c
292
))
341
+aspeed_xdma_write(uint64_t offset, uint64_t data) "XDMA write: offset 0x%" PRIx64 " data 0x%" PRIx64
293
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
294
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
342
--
295
--
343
2.20.1
296
2.20.1
344
297
345
298
diff view generated by jsdifflib
[Qemu-devel] [PULL 44/46] target/arm: Restrict PSCI to TCG
[PULL 04/24] tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Under KVM, the kernel gets the HVC call and handle the PSCI requests.
3
Add a test booting and quickly shutdown a raspi2 machine,
4
to test the power management model:
4
5
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
6
Message-id: 20190701132516.26392-20-philmd@redhat.com
7
console: [ 0.000000] Booting Linux on physical CPU 0xf00
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
9
console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
10
console: [ 0.000000] CPU: div instructions available: patching division code
11
console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
12
console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
13
...
14
console: Boot successful.
15
console: cat /proc/cpuinfo
16
console: / # cat /proc/cpuinfo
17
...
18
console: processor : 3
19
console: model name : ARMv7 Processor rev 5 (v7l)
20
console: BogoMIPS : 125.00
21
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
22
console: CPU implementer : 0x41
23
console: CPU architecture: 7
24
console: CPU variant : 0x0
25
console: CPU part : 0xc07
26
console: CPU revision : 5
27
console: Hardware : BCM2835
28
console: Revision : 0000
29
console: Serial : 0000000000000000
30
console: cat /proc/iomem
31
console: / # cat /proc/iomem
32
console: 00000000-3bffffff : System RAM
33
console: 00008000-00afffff : Kernel code
34
console: 00c00000-00d468ef : Kernel data
35
console: 3f006000-3f006fff : dwc_otg
36
console: 3f007000-3f007eff : /soc/dma@7e007000
37
console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
38
console: 3f100000-3f100027 : /soc/watchdog@7e100000
39
console: 3f101000-3f102fff : /soc/cprman@7e101000
40
console: 3f200000-3f2000b3 : /soc/gpio@7e200000
41
PASS (24.59 s)
42
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
43
JOB TIME : 25.02 s
44
45
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
46
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
47
Message-id: 20210531113837.1689775-1-f4bug@amsat.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
48
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
49
---
10
target/arm/internals.h | 6 +++++-
50
tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
11
1 file changed, 5 insertions(+), 1 deletion(-)
51
1 file changed, 43 insertions(+)
12
52
13
diff --git a/target/arm/internals.h b/target/arm/internals.h
53
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
14
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/internals.h
55
--- a/tests/acceptance/boot_linux_console.py
16
+++ b/target/arm/internals.h
56
+++ b/tests/acceptance/boot_linux_console.py
17
@@ -XXX,XX +XXX,XX @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
57
@@ -XXX,XX +XXX,XX @@
18
/* Callback function for when a watchpoint or breakpoint triggers. */
58
from avocado import skip
19
void arm_debug_excp_handler(CPUState *cs);
59
from avocado import skipUnless
20
60
from avocado_qemu import Test
21
-#ifdef CONFIG_USER_ONLY
61
+from avocado_qemu import exec_command
22
+#if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG)
62
from avocado_qemu import exec_command_and_wait_for_pattern
23
static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
63
from avocado_qemu import interrupt_interactive_console_until_pattern
24
{
64
from avocado_qemu import wait_for_console_pattern
25
return false;
65
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
26
}
66
"""
27
+static inline void arm_handle_psci_call(ARMCPU *cpu)
67
self.do_test_arm_raspi2(0)
28
+{
68
29
+ g_assert_not_reached();
69
+ def test_arm_raspi2_initrd(self):
30
+}
70
+ """
31
#else
71
+ :avocado: tags=arch:arm
32
/* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
72
+ :avocado: tags=machine:raspi2
33
bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
73
+ """
74
+ deb_url = ('http://archive.raspberrypi.org/debian/'
75
+ 'pool/main/r/raspberrypi-firmware/'
76
+ 'raspberrypi-kernel_1.20190215-1_armhf.deb')
77
+ deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
78
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
79
+ kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
80
+ dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
81
+
82
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
83
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
84
+ 'arm/rootfs-armv7a.cpio.gz')
85
+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
86
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
87
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
88
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
89
+
90
+ self.vm.set_console()
91
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
92
+ 'earlycon=pl011,0x3f201000 console=ttyAMA0 '
93
+ 'panic=-1 noreboot ' +
94
+ 'dwc_otg.fiq_fsm_enable=0')
95
+ self.vm.add_args('-kernel', kernel_path,
96
+ '-dtb', dtb_path,
97
+ '-initrd', initrd_path,
98
+ '-append', kernel_command_line,
99
+ '-no-reboot')
100
+ self.vm.launch()
101
+ self.wait_for_console_pattern('Boot successful.')
102
+
103
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
104
+ 'BCM2835')
105
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
106
+ '/soc/cprman@7e101000')
107
+ exec_command(self, 'halt')
108
+ # Wait for VM to shut down gracefully
109
+ self.vm.wait()
110
+
111
def test_arm_exynos4210_initrd(self):
112
"""
113
:avocado: tags=arch:arm
34
--
114
--
35
2.20.1
115
2.20.1
36
116
37
117
diff view generated by jsdifflib
[Qemu-devel] [PULL 42/46] target/arm/vfp_helper: Extract vfp_set_fpscr_from_host()
[PULL 05/24] target/arm: Check NaN mode before silencing NaN
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Joe Komlodi <joe.komlodi@xilinx.com>
2
2
3
The vfp_set_fpscr() helper contains code specific to the host
3
If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
4
floating point implementation (here the SoftFloat library).
4
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
5
Extract this code to vfp_set_fpscr_from_host().
5
assert due to fpst->default_nan_mode being set.
6
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
To avoid this, we check to see what NaN mode we're running in before we call
8
Message-id: 20190701132516.26392-17-philmd@redhat.com
8
floatxx_silence_nan().
9
10
Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
15
---
12
target/arm/vfp_helper.c | 19 +++++++++++++------
16
target/arm/helper-a64.c | 12 +++++++++---
13
1 file changed, 13 insertions(+), 6 deletions(-)
17
target/arm/vfp_helper.c | 24 ++++++++++++++++++------
18
2 files changed, 27 insertions(+), 9 deletions(-)
14
19
20
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper-a64.c
23
+++ b/target/arm/helper-a64.c
24
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
25
float16 nan = a;
26
if (float16_is_signaling_nan(a, fpst)) {
27
float_raise(float_flag_invalid, fpst);
28
- nan = float16_silence_nan(a, fpst);
29
+ if (!fpst->default_nan_mode) {
30
+ nan = float16_silence_nan(a, fpst);
31
+ }
32
}
33
if (fpst->default_nan_mode) {
34
nan = float16_default_nan(fpst);
35
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
36
float32 nan = a;
37
if (float32_is_signaling_nan(a, fpst)) {
38
float_raise(float_flag_invalid, fpst);
39
- nan = float32_silence_nan(a, fpst);
40
+ if (!fpst->default_nan_mode) {
41
+ nan = float32_silence_nan(a, fpst);
42
+ }
43
}
44
if (fpst->default_nan_mode) {
45
nan = float32_default_nan(fpst);
46
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
47
float64 nan = a;
48
if (float64_is_signaling_nan(a, fpst)) {
49
float_raise(float_flag_invalid, fpst);
50
- nan = float64_silence_nan(a, fpst);
51
+ if (!fpst->default_nan_mode) {
52
+ nan = float64_silence_nan(a, fpst);
53
+ }
54
}
55
if (fpst->default_nan_mode) {
56
nan = float64_default_nan(fpst);
15
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
57
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
16
index XXXXXXX..XXXXXXX 100644
58
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/vfp_helper.c
59
--- a/target/arm/vfp_helper.c
18
+++ b/target/arm/vfp_helper.c
60
+++ b/target/arm/vfp_helper.c
19
@@ -XXX,XX +XXX,XX @@ static inline int vfp_exceptbits_to_host(int target_bits)
61
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
20
return host_bits;
62
float16 nan = f16;
21
}
63
if (float16_is_signaling_nan(f16, fpst)) {
22
64
float_raise(float_flag_invalid, fpst);
23
+static uint32_t vfp_get_fpscr_from_host(CPUARMState *env)
65
- nan = float16_silence_nan(f16, fpst);
24
+{
66
+ if (!fpst->default_nan_mode) {
25
+ uint32_t i;
67
+ nan = float16_silence_nan(f16, fpst);
26
+
68
+ }
27
+ i = get_float_exception_flags(&env->vfp.fp_status);
69
}
28
+ i |= get_float_exception_flags(&env->vfp.standard_fp_status);
70
if (fpst->default_nan_mode) {
29
+ /* FZ16 does not generate an input denormal exception. */
71
nan = float16_default_nan(fpst);
30
+ i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
72
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
31
+ & ~float_flag_input_denormal);
73
float32 nan = f32;
32
+ return vfp_exceptbits_from_host(i);
74
if (float32_is_signaling_nan(f32, fpst)) {
33
+}
75
float_raise(float_flag_invalid, fpst);
34
+
76
- nan = float32_silence_nan(f32, fpst);
35
static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
77
+ if (!fpst->default_nan_mode) {
36
{
78
+ nan = float32_silence_nan(f32, fpst);
37
int i;
79
+ }
38
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
80
}
39
| (env->vfp.vec_len << 16)
81
if (fpst->default_nan_mode) {
40
| (env->vfp.vec_stride << 20);
82
nan = float32_default_nan(fpst);
41
83
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
42
- i = get_float_exception_flags(&env->vfp.fp_status);
84
float64 nan = f64;
43
- i |= get_float_exception_flags(&env->vfp.standard_fp_status);
85
if (float64_is_signaling_nan(f64, fpst)) {
44
- /* FZ16 does not generate an input denormal exception. */
86
float_raise(float_flag_invalid, fpst);
45
- i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
87
- nan = float64_silence_nan(f64, fpst);
46
- & ~float_flag_input_denormal);
88
+ if (!fpst->default_nan_mode) {
47
- fpscr |= vfp_exceptbits_from_host(i);
89
+ nan = float64_silence_nan(f64, fpst);
48
+ fpscr |= vfp_get_fpscr_from_host(env);
90
+ }
49
91
}
50
i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
92
if (fpst->default_nan_mode) {
51
fpscr |= i ? FPCR_QC : 0;
93
nan = float64_default_nan(fpst);
94
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
95
float16 nan = f16;
96
if (float16_is_signaling_nan(f16, s)) {
97
float_raise(float_flag_invalid, s);
98
- nan = float16_silence_nan(f16, s);
99
+ if (!s->default_nan_mode) {
100
+ nan = float16_silence_nan(f16, fpstp);
101
+ }
102
}
103
if (s->default_nan_mode) {
104
nan = float16_default_nan(s);
105
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
106
float32 nan = f32;
107
if (float32_is_signaling_nan(f32, s)) {
108
float_raise(float_flag_invalid, s);
109
- nan = float32_silence_nan(f32, s);
110
+ if (!s->default_nan_mode) {
111
+ nan = float32_silence_nan(f32, fpstp);
112
+ }
113
}
114
if (s->default_nan_mode) {
115
nan = float32_default_nan(s);
116
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
117
float64 nan = f64;
118
if (float64_is_signaling_nan(f64, s)) {
119
float_raise(float_flag_invalid, s);
120
- nan = float64_silence_nan(f64, s);
121
+ if (!s->default_nan_mode) {
122
+ nan = float64_silence_nan(f64, fpstp);
123
+ }
124
}
125
if (s->default_nan_mode) {
126
nan = float64_default_nan(s);
52
--
127
--
53
2.20.1
128
2.20.1
54
129
55
130
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/46] i.mx7d: pci: Update PCI IRQ mapping to match HW
[PULL 06/24] hw/gpio/gpio_pwr: use shutdown function for reboot
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Maxim Uvarov <maxim.uvarov@linaro.org>
2
2
3
Datasheet for i.MX7 is incorrect and i.MX7's PCI IRQ mapping matches
3
qemu has 2 type of functions: shutdown and reboot. Shutdown
4
that of i.MX6:
4
function has to be used for machine shutdown. Otherwise we cause
5
a reset with a bogus "cause" value, when we intended a shutdown.
5
6
6
* INTD/MSI 122
7
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
7
* INTC 123
8
* INTB 124
9
* INTA 125
10
11
Fix all of the relevant code to reflect that fact. Needed by latest
12
Linux kernels.
13
14
(Reference: Linux kernel commit 538d6e9d597584e80 from an
15
NXP employee confirming that the datasheet is incorrect and
16
with a report of a test against hardware.)
17
18
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
19
Cc: Peter Maydell <peter.maydell@linaro.org>
20
Cc: Michael S. Tsirkin <mst@redhat.com>
21
Cc: qemu-devel@nongnu.org
22
Cc: qemu-arm@nongnu.org
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
[PMM: added ref to kernel commit confirming the datasheet error]
9
Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
10
[PMM: tweaked commit message]
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
---
12
---
27
include/hw/arm/fsl-imx7.h | 8 ++++----
13
hw/gpio/gpio_pwr.c | 2 +-
28
hw/pci-host/designware.c | 6 ++++--
14
1 file changed, 1 insertion(+), 1 deletion(-)
29
2 files changed, 8 insertions(+), 6 deletions(-)
30
15
31
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
16
diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
32
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
33
--- a/include/hw/arm/fsl-imx7.h
18
--- a/hw/gpio/gpio_pwr.c
34
+++ b/include/hw/arm/fsl-imx7.h
19
+++ b/hw/gpio/gpio_pwr.c
35
@@ -XXX,XX +XXX,XX @@ enum FslIMX7IRQs {
20
@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
36
FSL_IMX7_USB2_IRQ = 42,
21
static void gpio_pwr_shutdown(void *opaque, int n, int level)
37
FSL_IMX7_USB3_IRQ = 40,
38
39
- FSL_IMX7_PCI_INTA_IRQ = 122,
40
- FSL_IMX7_PCI_INTB_IRQ = 123,
41
- FSL_IMX7_PCI_INTC_IRQ = 124,
42
- FSL_IMX7_PCI_INTD_IRQ = 125,
43
+ FSL_IMX7_PCI_INTA_IRQ = 125,
44
+ FSL_IMX7_PCI_INTB_IRQ = 124,
45
+ FSL_IMX7_PCI_INTC_IRQ = 123,
46
+ FSL_IMX7_PCI_INTD_IRQ = 122,
47
48
FSL_IMX7_UART7_IRQ = 126,
49
50
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/hw/pci-host/designware.c
53
+++ b/hw/pci-host/designware.c
54
@@ -XXX,XX +XXX,XX @@
55
#define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff)
56
#define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C
57
58
+#define DESIGNWARE_PCIE_IRQ_MSI 3
59
+
60
static DesignwarePCIEHost *
61
designware_pcie_root_to_host(DesignwarePCIERoot *root)
62
{
22
{
63
@@ -XXX,XX +XXX,XX @@ static void designware_pcie_root_msi_write(void *opaque, hwaddr addr,
23
if (level) {
64
root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable;
24
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
65
25
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
66
if (root->msi.intr[0].status & ~root->msi.intr[0].mask) {
67
- qemu_set_irq(host->pci.irqs[0], 1);
68
+ qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 1);
69
}
26
}
70
}
27
}
71
72
@@ -XXX,XX +XXX,XX @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
73
case DESIGNWARE_PCIE_MSI_INTR0_STATUS:
74
root->msi.intr[0].status ^= val;
75
if (!root->msi.intr[0].status) {
76
- qemu_set_irq(host->pci.irqs[0], 0);
77
+ qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 0);
78
}
79
break;
80
28
81
--
29
--
82
2.20.1
30
2.20.1
83
31
84
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 34/46] target/arm: Fix multiline comment syntax
[PULL 07/24] target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
In do_ldst(), the calculation of the offset needs to be based on the
2
size of the memory access, not the size of the elements in the
3
vector. This meant we were getting it wrong for the widening and
4
narrowing variants of the various VLDR and VSTR insns.
2
5
3
Since commit 8c06fbdf36b checkpatch.pl enforce a new multiline
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
comment syntax. Since we'll move this code around, fix its style
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
first.
8
Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
9
---
10
target/arm/translate-mve.c | 17 +++++++++--------
11
1 file changed, 9 insertions(+), 8 deletions(-)
6
12
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190701132516.26392-8-philmd@redhat.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/helper.c | 237 ++++++++++++++++++++++++++--------------
13
target/arm/op_helper.c | 54 ++++++---
14
target/arm/vfp_helper.c | 3 +-
15
3 files changed, 196 insertions(+), 98 deletions(-)
16
17
diff --git a/target/arm/helper.c b/target/arm/helper.c
18
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper.c
15
--- a/target/arm/translate-mve.c
20
+++ b/target/arm/helper.c
16
+++ b/target/arm/translate-mve.c
21
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr)
17
@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
22
23
uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
24
{
25
- /* The TT instructions can be used by unprivileged code, but in
26
+ /*
27
+ * The TT instructions can be used by unprivileged code, but in
28
* user-only emulation we don't have the MPU.
29
* Luckily since we know we are NonSecure unprivileged (and that in
30
* turn means that the A flag wasn't specified), all the bits in the
31
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
32
return true;
33
34
pend_fault:
35
- /* By pending the exception at this point we are making
36
+ /*
37
+ * By pending the exception at this point we are making
38
* the IMPDEF choice "overridden exceptions pended" (see the
39
* MergeExcInfo() pseudocode). The other choice would be to not
40
* pend them now and then make a choice about which to throw away
41
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr,
42
return true;
43
44
pend_fault:
45
- /* By pending the exception at this point we are making
46
+ /*
47
+ * By pending the exception at this point we are making
48
* the IMPDEF choice "overridden exceptions pended" (see the
49
* MergeExcInfo() pseudocode). The other choice would be to not
50
* pend them now and then make a choice about which to throw away
51
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env)
52
*/
53
}
54
55
-/* Write to v7M CONTROL.SPSEL bit for the specified security bank.
56
+/*
57
+ * Write to v7M CONTROL.SPSEL bit for the specified security bank.
58
* This may change the current stack pointer between Main and Process
59
* stack pointers if it is done for the CONTROL register for the current
60
* security state.
61
@@ -XXX,XX +XXX,XX @@ static void write_v7m_control_spsel_for_secstate(CPUARMState *env,
62
}
18
}
63
}
19
}
64
20
65
-/* Write to v7M CONTROL.SPSEL bit. This may change the current
21
-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
66
+/*
22
+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
67
+ * Write to v7M CONTROL.SPSEL bit. This may change the current
23
+ unsigned msize)
68
* stack pointer between Main and Process stack pointers.
69
*/
70
static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel)
71
@@ -XXX,XX +XXX,XX @@ static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel)
72
73
void write_v7m_exception(CPUARMState *env, uint32_t new_exc)
74
{
24
{
75
- /* Write a new value to v7m.exception, thus transitioning into or out
25
TCGv_i32 addr;
76
+ /*
26
uint32_t offset;
77
+ * Write a new value to v7m.exception, thus transitioning into or out
27
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
78
* of Handler mode; this may result in a change of active stack pointer.
79
*/
80
bool new_is_psp, old_is_psp = v7m_using_psp(env);
81
@@ -XXX,XX +XXX,XX @@ static void switch_v7m_security_state(CPUARMState *env, bool new_secstate)
82
return;
83
}
84
85
- /* All the banked state is accessed by looking at env->v7m.secure
86
+ /*
87
+ * All the banked state is accessed by looking at env->v7m.secure
88
* except for the stack pointer; rearrange the SP appropriately.
89
*/
90
new_ss_msp = env->v7m.other_ss_msp;
91
@@ -XXX,XX +XXX,XX @@ static void switch_v7m_security_state(CPUARMState *env, bool new_secstate)
92
93
void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
94
{
95
- /* Handle v7M BXNS:
96
+ /*
97
+ * Handle v7M BXNS:
98
* - if the return value is a magic value, do exception return (like BX)
99
* - otherwise bit 0 of the return value is the target security state
100
*/
101
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
102
}
103
104
if (dest >= min_magic) {
105
- /* This is an exception return magic value; put it where
106
+ /*
107
+ * This is an exception return magic value; put it where
108
* do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.
109
* Note that if we ever add gen_ss_advance() singlestep support to
110
* M profile this should count as an "instruction execution complete"
111
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
112
113
void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
114
{
115
- /* Handle v7M BLXNS:
116
+ /*
117
+ * Handle v7M BLXNS:
118
* - bit 0 of the destination address is the target security state
119
*/
120
121
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
122
assert(env->v7m.secure);
123
124
if (dest & 1) {
125
- /* target is Secure, so this is just a normal BLX,
126
+ /*
127
+ * Target is Secure, so this is just a normal BLX,
128
* except that the low bit doesn't indicate Thumb/not.
129
*/
130
env->regs[14] = nextinst;
131
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
132
env->regs[13] = sp;
133
env->regs[14] = 0xfeffffff;
134
if (arm_v7m_is_handler_mode(env)) {
135
- /* Write a dummy value to IPSR, to avoid leaking the current secure
136
+ /*
137
+ * Write a dummy value to IPSR, to avoid leaking the current secure
138
* exception number to non-secure code. This is guaranteed not
139
* to cause write_v7m_exception() to actually change stacks.
140
*/
141
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
142
static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
143
bool spsel)
144
{
145
- /* Return a pointer to the location where we currently store the
146
+ /*
147
+ * Return a pointer to the location where we currently store the
148
* stack pointer for the requested security state and thread mode.
149
* This pointer will become invalid if the CPU state is updated
150
* such that the stack pointers are switched around (eg changing
151
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
152
153
mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, targets_secure, true);
154
155
- /* We don't do a get_phys_addr() here because the rules for vector
156
+ /*
157
+ * We don't do a get_phys_addr() here because the rules for vector
158
* loads are special: they always use the default memory map, and
159
* the default memory map permits reads from all addresses.
160
* Since there's no easy way to pass through to pmsav8_mpu_lookup()
161
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
162
return true;
163
164
load_fail:
165
- /* All vector table fetch fails are reported as HardFault, with
166
+ /*
167
+ * All vector table fetch fails are reported as HardFault, with
168
* HFSR.VECTTBL and .FORCED set. (FORCED is set because
169
* technically the underlying exception is a MemManage or BusFault
170
* that is escalated to HardFault.) This is a terminal exception,
171
@@ -XXX,XX +XXX,XX @@ static uint32_t v7m_integrity_sig(CPUARMState *env, uint32_t lr)
172
static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
173
bool ignore_faults)
174
{
175
- /* For v8M, push the callee-saves register part of the stack frame.
176
+ /*
177
+ * For v8M, push the callee-saves register part of the stack frame.
178
* Compare the v8M pseudocode PushCalleeStack().
179
* In the tailchaining case this may not be the current stack.
180
*/
181
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
182
return true;
28
return true;
183
}
29
}
184
30
185
- /* Write as much of the stack frame as we can. A write failure may
31
- offset = a->imm << a->size;
186
+ /*
32
+ offset = a->imm << msize;
187
+ * Write as much of the stack frame as we can. A write failure may
33
if (!a->a) {
188
* cause us to pend a derived exception.
34
offset = -offset;
189
*/
35
}
190
sig = v7m_integrity_sig(env, lr);
36
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
191
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
37
{ gen_helper_mve_vstrw, gen_helper_mve_vldrw },
192
static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
38
{ NULL, NULL }
193
bool ignore_stackfaults)
39
};
40
- return do_ldst(s, a, ldstfns[a->size][a->l]);
41
+ return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
42
}
43
44
-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \
45
+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \
46
static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \
47
{ \
48
static MVEGenLdStFn * const ldstfns[2][2] = { \
49
{ gen_helper_mve_##ST, gen_helper_mve_##SLD }, \
50
{ NULL, gen_helper_mve_##ULD }, \
51
}; \
52
- return do_ldst(s, a, ldstfns[a->u][a->l]); \
53
+ return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \
54
}
55
56
-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
57
-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
58
-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
59
+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
60
+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
61
+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
62
63
static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
194
{
64
{
195
- /* Do the "take the exception" parts of exception entry,
196
+ /*
197
+ * Do the "take the exception" parts of exception entry,
198
* but not the pushing of state to the stack. This is
199
* similar to the pseudocode ExceptionTaken() function.
200
*/
201
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
202
if (arm_feature(env, ARM_FEATURE_V8)) {
203
if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
204
(lr & R_V7M_EXCRET_S_MASK)) {
205
- /* The background code (the owner of the registers in the
206
+ /*
207
+ * The background code (the owner of the registers in the
208
* exception frame) is Secure. This means it may either already
209
* have or now needs to push callee-saves registers.
210
*/
211
if (targets_secure) {
212
if (dotailchain && !(lr & R_V7M_EXCRET_ES_MASK)) {
213
- /* We took an exception from Secure to NonSecure
214
+ /*
215
+ * We took an exception from Secure to NonSecure
216
* (which means the callee-saved registers got stacked)
217
* and are now tailchaining to a Secure exception.
218
* Clear DCRS so eventual return from this Secure
219
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
220
lr &= ~R_V7M_EXCRET_DCRS_MASK;
221
}
222
} else {
223
- /* We're going to a non-secure exception; push the
224
+ /*
225
+ * We're going to a non-secure exception; push the
226
* callee-saves registers to the stack now, if they're
227
* not already saved.
228
*/
229
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
230
lr |= R_V7M_EXCRET_SPSEL_MASK;
231
}
232
233
- /* Clear registers if necessary to prevent non-secure exception
234
+ /*
235
+ * Clear registers if necessary to prevent non-secure exception
236
* code being able to see register values from secure code.
237
* Where register values become architecturally UNKNOWN we leave
238
* them with their previous values.
239
*/
240
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
241
if (!targets_secure) {
242
- /* Always clear the caller-saved registers (they have been
243
+ /*
244
+ * Always clear the caller-saved registers (they have been
245
* pushed to the stack earlier in v7m_push_stack()).
246
* Clear callee-saved registers if the background code is
247
* Secure (in which case these regs were saved in
248
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
249
}
250
251
if (push_failed && !ignore_stackfaults) {
252
- /* Derived exception on callee-saves register stacking:
253
+ /*
254
+ * Derived exception on callee-saves register stacking:
255
* we might now want to take a different exception which
256
* targets a different security state, so try again from the top.
257
*/
258
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
259
return;
260
}
261
262
- /* Now we've done everything that might cause a derived exception
263
+ /*
264
+ * Now we've done everything that might cause a derived exception
265
* we can go ahead and activate whichever exception we're going to
266
* take (which might now be the derived exception).
267
*/
268
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr)
269
270
static bool v7m_push_stack(ARMCPU *cpu)
271
{
272
- /* Do the "set up stack frame" part of exception entry,
273
+ /*
274
+ * Do the "set up stack frame" part of exception entry,
275
* similar to pseudocode PushStack().
276
* Return true if we generate a derived exception (and so
277
* should ignore further stack faults trying to process
278
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_stack(ARMCPU *cpu)
279
}
280
}
281
282
- /* Write as much of the stack frame as we can. If we fail a stack
283
+ /*
284
+ * Write as much of the stack frame as we can. If we fail a stack
285
* write this will result in a derived exception being pended
286
* (which may be taken in preference to the one we started with
287
* if it has higher priority).
288
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
289
bool ftype;
290
bool restore_s16_s31;
291
292
- /* If we're not in Handler mode then jumps to magic exception-exit
293
+ /*
294
+ * If we're not in Handler mode then jumps to magic exception-exit
295
* addresses don't have magic behaviour. However for the v8M
296
* security extensions the magic secure-function-return has to
297
* work in thread mode too, so to avoid doing an extra check in
298
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
299
return;
300
}
301
302
- /* In the spec pseudocode ExceptionReturn() is called directly
303
+ /*
304
+ * In the spec pseudocode ExceptionReturn() is called directly
305
* from BXWritePC() and gets the full target PC value including
306
* bit zero. In QEMU's implementation we treat it as a normal
307
* jump-to-register (which is then caught later on), and so split
308
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
309
}
310
311
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
312
- /* EXC_RETURN.ES validation check (R_SMFL). We must do this before
313
+ /*
314
+ * EXC_RETURN.ES validation check (R_SMFL). We must do this before
315
* we pick which FAULTMASK to clear.
316
*/
317
if (!env->v7m.secure &&
318
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
319
}
320
321
if (env->v7m.exception != ARMV7M_EXCP_NMI) {
322
- /* Auto-clear FAULTMASK on return from other than NMI.
323
+ /*
324
+ * Auto-clear FAULTMASK on return from other than NMI.
325
* If the security extension is implemented then this only
326
* happens if the raw execution priority is >= 0; the
327
* value of the ES bit in the exception return value indicates
328
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
329
/* still an irq active now */
330
break;
331
case 1:
332
- /* we returned to base exception level, no nesting.
333
+ /*
334
+ * We returned to base exception level, no nesting.
335
* (In the pseudocode this is written using "NestedActivation != 1"
336
* where we have 'rettobase == false'.)
337
*/
338
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
339
340
if (arm_feature(env, ARM_FEATURE_V8)) {
341
if (!arm_feature(env, ARM_FEATURE_M_SECURITY)) {
342
- /* UNPREDICTABLE if S == 1 or DCRS == 0 or ES == 1 (R_XLCP);
343
+ /*
344
+ * UNPREDICTABLE if S == 1 or DCRS == 0 or ES == 1 (R_XLCP);
345
* we choose to take the UsageFault.
346
*/
347
if ((excret & R_V7M_EXCRET_S_MASK) ||
348
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
349
break;
350
case 13: /* Return to Thread using Process stack */
351
case 9: /* Return to Thread using Main stack */
352
- /* We only need to check NONBASETHRDENA for v7M, because in
353
+ /*
354
+ * We only need to check NONBASETHRDENA for v7M, because in
355
* v8M this bit does not exist (it is RES1).
356
*/
357
if (!rettobase &&
358
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
359
}
360
361
if (ufault) {
362
- /* Bad exception return: instead of popping the exception
363
+ /*
364
+ * Bad exception return: instead of popping the exception
365
* stack, directly take a usage fault on the current stack.
366
*/
367
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
368
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
369
switch_v7m_security_state(env, return_to_secure);
370
371
{
372
- /* The stack pointer we should be reading the exception frame from
373
+ /*
374
+ * The stack pointer we should be reading the exception frame from
375
* depends on bits in the magic exception return type value (and
376
* for v8M isn't necessarily the stack pointer we will eventually
377
* end up resuming execution with). Get a pointer to the location
378
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
379
v7m_stack_read(cpu, &xpsr, frameptr + 0x1c, mmu_idx);
380
381
if (!pop_ok) {
382
- /* v7m_stack_read() pended a fault, so take it (as a tail
383
+ /*
384
+ * v7m_stack_read() pended a fault, so take it (as a tail
385
* chained exception on the same stack frame)
386
*/
387
qemu_log_mask(CPU_LOG_INT, "...derived exception on unstacking\n");
388
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
389
return;
390
}
391
392
- /* Returning from an exception with a PC with bit 0 set is defined
393
+ /*
394
+ * Returning from an exception with a PC with bit 0 set is defined
395
* behaviour on v8M (bit 0 is ignored), but for v7M it was specified
396
* to be UNPREDICTABLE. In practice actual v7M hardware seems to ignore
397
* the lsbit, and there are several RTOSes out there which incorrectly
398
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
399
}
400
401
if (arm_feature(env, ARM_FEATURE_V8)) {
402
- /* For v8M we have to check whether the xPSR exception field
403
+ /*
404
+ * For v8M we have to check whether the xPSR exception field
405
* matches the EXCRET value for return to handler/thread
406
* before we commit to changing the SP and xPSR.
407
*/
408
bool will_be_handler = (xpsr & XPSR_EXCP) != 0;
409
if (return_to_handler != will_be_handler) {
410
- /* Take an INVPC UsageFault on the current stack.
411
+ /*
412
+ * Take an INVPC UsageFault on the current stack.
413
* By this point we will have switched to the security state
414
* for the background state, so this UsageFault will target
415
* that state.
416
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
417
frameptr += 0x40;
418
}
419
}
420
- /* Undo stack alignment (the SPREALIGN bit indicates that the original
421
+ /*
422
+ * Undo stack alignment (the SPREALIGN bit indicates that the original
423
* pre-exception SP was not 8-aligned and we added a padding word to
424
* align it, so we undo this by ORing in the bit that increases it
425
* from the current 8-aligned value to the 8-unaligned value. (Adding 4
426
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
427
V7M_CONTROL, SFPA, sfpa);
428
}
429
430
- /* The restored xPSR exception field will be zero if we're
431
+ /*
432
+ * The restored xPSR exception field will be zero if we're
433
* resuming in Thread mode. If that doesn't match what the
434
* exception return excret specified then this is a UsageFault.
435
* v7M requires we make this check here; v8M did it earlier.
436
*/
437
if (return_to_handler != arm_v7m_is_handler_mode(env)) {
438
- /* Take an INVPC UsageFault by pushing the stack again;
439
+ /*
440
+ * Take an INVPC UsageFault by pushing the stack again;
441
* we know we're v7M so this is never a Secure UsageFault.
442
*/
443
bool ignore_stackfaults;
444
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
445
446
static bool do_v7m_function_return(ARMCPU *cpu)
447
{
448
- /* v8M security extensions magic function return.
449
+ /*
450
+ * v8M security extensions magic function return.
451
* We may either:
452
* (1) throw an exception (longjump)
453
* (2) return true if we successfully handled the function return
454
@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
455
frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);
456
frameptr = *frame_sp_p;
457
458
- /* These loads may throw an exception (for MPU faults). We want to
459
+ /*
460
+ * These loads may throw an exception (for MPU faults). We want to
461
* do them as secure, so work out what MMU index that is.
462
*/
463
mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
464
@@ -XXX,XX +XXX,XX @@ static void arm_log_exception(int idx)
465
static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
466
uint32_t addr, uint16_t *insn)
467
{
468
- /* Load a 16-bit portion of a v7M instruction, returning true on success,
469
+ /*
470
+ * Load a 16-bit portion of a v7M instruction, returning true on success,
471
* or false on failure (in which case we will have pended the appropriate
472
* exception).
473
* We need to do the instruction fetch's MPU and SAU checks
474
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
475
476
v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
477
if (!sattrs.nsc || sattrs.ns) {
478
- /* This must be the second half of the insn, and it straddles a
479
+ /*
480
+ * This must be the second half of the insn, and it straddles a
481
* region boundary with the second half not being S&NSC.
482
*/
483
env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK;
484
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
485
486
static bool v7m_handle_execute_nsc(ARMCPU *cpu)
487
{
488
- /* Check whether this attempt to execute code in a Secure & NS-Callable
489
+ /*
490
+ * Check whether this attempt to execute code in a Secure & NS-Callable
491
* memory region is for an SG instruction; if so, then emulate the
492
* effect of the SG instruction and return true. Otherwise pend
493
* the correct kind of exception and return false.
494
@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
495
ARMMMUIdx mmu_idx;
496
uint16_t insn;
497
498
- /* We should never get here unless get_phys_addr_pmsav8() caused
499
+ /*
500
+ * We should never get here unless get_phys_addr_pmsav8() caused
501
* an exception for NS executing in S&NSC memory.
502
*/
503
assert(!env->v7m.secure);
504
@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
505
}
506
507
if (insn != 0xe97f) {
508
- /* Not an SG instruction first half (we choose the IMPDEF
509
+ /*
510
+ * Not an SG instruction first half (we choose the IMPDEF
511
* early-SG-check option).
512
*/
513
goto gen_invep;
514
@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
515
}
516
517
if (insn != 0xe97f) {
518
- /* Not an SG instruction second half (yes, both halves of the SG
519
+ /*
520
+ * Not an SG instruction second half (yes, both halves of the SG
521
* insn have the same hex value)
522
*/
523
goto gen_invep;
524
}
525
526
- /* OK, we have confirmed that we really have an SG instruction.
527
+ /*
528
+ * OK, we have confirmed that we really have an SG instruction.
529
* We know we're NS in S memory so don't need to repeat those checks.
530
*/
531
qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32
532
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
533
534
arm_log_exception(cs->exception_index);
535
536
- /* For exceptions we just mark as pending on the NVIC, and let that
537
- handle it. */
538
+ /*
539
+ * For exceptions we just mark as pending on the NVIC, and let that
540
+ * handle it.
541
+ */
542
switch (cs->exception_index) {
543
case EXCP_UDEF:
544
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
545
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
546
break;
547
case EXCP_PREFETCH_ABORT:
548
case EXCP_DATA_ABORT:
549
- /* Note that for M profile we don't have a guest facing FSR, but
550
+ /*
551
+ * Note that for M profile we don't have a guest facing FSR, but
552
* the env->exception.fsr will be populated by the code that
553
* raises the fault, in the A profile short-descriptor format.
554
*/
555
switch (env->exception.fsr & 0xf) {
556
case M_FAKE_FSR_NSC_EXEC:
557
- /* Exception generated when we try to execute code at an address
558
+ /*
559
+ * Exception generated when we try to execute code at an address
560
* which is marked as Secure & Non-Secure Callable and the CPU
561
* is in the Non-Secure state. The only instruction which can
562
* be executed like this is SG (and that only if both halves of
563
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
564
}
565
break;
566
case M_FAKE_FSR_SFAULT:
567
- /* Various flavours of SecureFault for attempts to execute or
568
+ /*
569
+ * Various flavours of SecureFault for attempts to execute or
570
* access data in the wrong security state.
571
*/
572
switch (cs->exception_index) {
573
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
574
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
575
break;
576
default:
577
- /* All other FSR values are either MPU faults or "can't happen
578
+ /*
579
+ * All other FSR values are either MPU faults or "can't happen
580
* for M profile" cases.
581
*/
582
switch (cs->exception_index) {
583
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
584
if (arm_feature(env, ARM_FEATURE_V8)) {
585
lr = R_V7M_EXCRET_RES1_MASK |
586
R_V7M_EXCRET_DCRS_MASK;
587
- /* The S bit indicates whether we should return to Secure
588
+ /*
589
+ * The S bit indicates whether we should return to Secure
590
* or NonSecure (ie our current state).
591
* The ES bit indicates whether we're taking this exception
592
* to Secure or NonSecure (ie our target state). We set it
593
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
594
v7m_exception_taken(cpu, lr, false, ignore_stackfaults);
595
}
596
597
-/* Function used to synchronize QEMU's AArch64 register set with AArch32
598
+/*
599
+ * Function used to synchronize QEMU's AArch64 register set with AArch32
600
* register set. This is necessary when switching between AArch32 and AArch64
601
* execution state.
602
*/
603
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_32_to_64(CPUARMState *env)
604
env->xregs[i] = env->regs[i];
605
}
606
607
- /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
608
+ /*
609
+ * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
610
* Otherwise, they come from the banked user regs.
611
*/
612
if (mode == ARM_CPU_MODE_FIQ) {
613
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_32_to_64(CPUARMState *env)
614
}
615
}
616
617
- /* Registers x13-x23 are the various mode SP and FP registers. Registers
618
+ /*
619
+ * Registers x13-x23 are the various mode SP and FP registers. Registers
620
* r13 and r14 are only copied if we are in that mode, otherwise we copy
621
* from the mode banked register.
622
*/
623
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_32_to_64(CPUARMState *env)
624
env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
625
}
626
627
- /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
628
+ /*
629
+ * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
630
* mode, then we can copy from r8-r14. Otherwise, we copy from the
631
* FIQ bank for r8-r14.
632
*/
633
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_32_to_64(CPUARMState *env)
634
env->pc = env->regs[15];
635
}
636
637
-/* Function used to synchronize QEMU's AArch32 register set with AArch64
638
+/*
639
+ * Function used to synchronize QEMU's AArch32 register set with AArch64
640
* register set. This is necessary when switching between AArch32 and AArch64
641
* execution state.
642
*/
643
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_64_to_32(CPUARMState *env)
644
env->regs[i] = env->xregs[i];
645
}
646
647
- /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
648
+ /*
649
+ * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
650
* Otherwise, we copy x8-x12 into the banked user regs.
651
*/
652
if (mode == ARM_CPU_MODE_FIQ) {
653
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_64_to_32(CPUARMState *env)
654
}
655
}
656
657
- /* Registers r13 & r14 depend on the current mode.
658
+ /*
659
+ * Registers r13 & r14 depend on the current mode.
660
* If we are in a given mode, we copy the corresponding x registers to r13
661
* and r14. Otherwise, we copy the x register to the banked r13 and r14
662
* for the mode.
663
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_64_to_32(CPUARMState *env)
664
} else {
665
env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
666
667
- /* HYP is an exception in that it does not have its own banked r14 but
668
+ /*
669
+ * HYP is an exception in that it does not have its own banked r14 but
670
* shares the USR r14
671
*/
672
if (mode == ARM_CPU_MODE_HYP) {
673
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
674
return value;
675
}
676
case 0x94: /* CONTROL_NS */
677
- /* We have to handle this here because unprivileged Secure code
678
+ /*
679
+ * We have to handle this here because unprivileged Secure code
680
* can read the NS CONTROL register.
681
*/
682
if (!env->v7m.secure) {
683
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
684
return env->v7m.faultmask[M_REG_NS];
685
case 0x98: /* SP_NS */
686
{
687
- /* This gives the non-secure SP selected based on whether we're
688
+ /*
689
+ * This gives the non-secure SP selected based on whether we're
690
* currently in handler mode or not, using the NS CONTROL.SPSEL.
691
*/
692
bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
693
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
694
695
void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
696
{
697
- /* We're passed bits [11..0] of the instruction; extract
698
+ /*
699
+ * We're passed bits [11..0] of the instruction; extract
700
* SYSm and the mask bits.
701
* Invalid combinations of SYSm and mask are UNPREDICTABLE;
702
* we choose to treat them as if the mask bits were valid.
703
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
704
return;
705
case 0x98: /* SP_NS */
706
{
707
- /* This gives the non-secure SP selected based on whether we're
708
+ /*
709
+ * This gives the non-secure SP selected based on whether we're
710
* currently in handler mode or not, using the NS CONTROL.SPSEL.
711
*/
712
bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
713
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
714
bool targetsec = env->v7m.secure;
715
bool is_subpage;
716
717
- /* Work out what the security state and privilege level we're
718
+ /*
719
+ * Work out what the security state and privilege level we're
720
* interested in is...
721
*/
722
if (alt) {
723
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
724
/* ...and then figure out which MMU index this is */
725
mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, targetsec, targetpriv);
726
727
- /* We know that the MPU and SAU don't care about the access type
728
+ /*
729
+ * We know that the MPU and SAU don't care about the access type
730
* for our purposes beyond that we don't want to claim to be
731
* an insn fetch, so we arbitrarily call this a read.
732
*/
733
734
- /* MPU region info only available for privileged or if
735
+ /*
736
+ * MPU region info only available for privileged or if
737
* inspecting the other MPU state.
738
*/
739
if (arm_current_el(env) != 0 || alt) {
740
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
741
742
void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
743
{
744
- /* Implement DC ZVA, which zeroes a fixed-length block of memory.
745
+ /*
746
+ * Implement DC ZVA, which zeroes a fixed-length block of memory.
747
* Note that we do not implement the (architecturally mandated)
748
* alignment fault for attempts to use this on Device memory
749
* (which matches the usual QEMU behaviour of not implementing either
750
@@ -XXX,XX +XXX,XX @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
751
752
#ifndef CONFIG_USER_ONLY
753
{
754
- /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
755
+ /*
756
+ * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
757
* the block size so we might have to do more than one TLB lookup.
758
* We know that in fact for any v8 CPU the page size is at least 4K
759
* and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
760
@@ -XXX,XX +XXX,XX @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
761
}
762
}
763
if (i == maxidx) {
764
- /* If it's all in the TLB it's fair game for just writing to;
765
+ /*
766
+ * If it's all in the TLB it's fair game for just writing to;
767
* we know we don't need to update dirty status, etc.
768
*/
769
for (i = 0; i < maxidx - 1; i++) {
770
@@ -XXX,XX +XXX,XX @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
771
memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
772
return;
773
}
774
- /* OK, try a store and see if we can populate the tlb. This
775
+ /*
776
+ * OK, try a store and see if we can populate the tlb. This
777
* might cause an exception if the memory isn't writable,
778
* in which case we will longjmp out of here. We must for
779
* this purpose use the actual register value passed to us
780
@@ -XXX,XX +XXX,XX @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
781
}
782
}
783
784
- /* Slow path (probably attempt to do this to an I/O device or
785
+ /*
786
+ * Slow path (probably attempt to do this to an I/O device or
787
* similar, or clearing of a block of code we have translations
788
* cached for). Just do a series of byte writes as the architecture
789
* demands. It's not worth trying to use a cpu_physical_memory_map(),
790
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
791
index XXXXXXX..XXXXXXX 100644
792
--- a/target/arm/op_helper.c
793
+++ b/target/arm/op_helper.c
794
@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
795
{
796
uint32_t syn;
797
798
- /* ISV is only set for data aborts routed to EL2 and
799
+ /*
800
+ * ISV is only set for data aborts routed to EL2 and
801
* never for stage-1 page table walks faulting on stage 2.
802
*
803
* Furthermore, ISV is only set for certain kinds of load/stores.
804
@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
805
syn = syn_data_abort_no_iss(same_el,
806
ea, 0, s1ptw, is_write, fsc);
807
} else {
808
- /* Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
809
+ /*
810
+ * Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
811
* syndrome created at translation time.
812
* Now we create the runtime syndrome with the remaining fields.
813
*/
814
@@ -XXX,XX +XXX,XX @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type,
815
816
if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
817
arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
818
- /* LPAE format fault status register : bottom 6 bits are
819
+ /*
820
+ * LPAE format fault status register : bottom 6 bits are
821
* status code in the same form as needed for syndrome
822
*/
823
fsr = arm_fi_to_lfsc(fi);
824
fsc = extract32(fsr, 0, 6);
825
} else {
826
fsr = arm_fi_to_sfsc(fi);
827
- /* Short format FSR : this fault will never actually be reported
828
+ /*
829
+ * Short format FSR : this fault will never actually be reported
830
* to an EL that uses a syndrome register. Use a (currently)
831
* reserved FSR code in case the constructed syndrome does leak
832
* into the guest somehow.
833
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
834
arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
835
}
836
837
-/* arm_cpu_do_transaction_failed: handle a memory system error response
838
+/*
839
+ * arm_cpu_do_transaction_failed: handle a memory system error response
840
* (eg "no device/memory present at address") by raising an external abort
841
* exception
842
*/
843
@@ -XXX,XX +XXX,XX @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
844
int bt;
845
uint32_t contextidr;
846
847
- /* Links to unimplemented or non-context aware breakpoints are
848
+ /*
849
+ * Links to unimplemented or non-context aware breakpoints are
850
* CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
851
* as if linked to an UNKNOWN context-aware breakpoint (in which
852
* case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
853
@@ -XXX,XX +XXX,XX @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
854
855
bt = extract64(bcr, 20, 4);
856
857
- /* We match the whole register even if this is AArch32 using the
858
+ /*
859
+ * We match the whole register even if this is AArch32 using the
860
* short descriptor format (in which case it holds both PROCID and ASID),
861
* since we don't implement the optional v7 context ID masking.
862
*/
863
@@ -XXX,XX +XXX,XX @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
864
case 9: /* linked VMID match (reserved if no EL2) */
865
case 11: /* linked context ID and VMID match (reserved if no EL2) */
866
default:
867
- /* Links to Unlinked context breakpoints must generate no
868
+ /*
869
+ * Links to Unlinked context breakpoints must generate no
870
* events; we choose to do the same for reserved values too.
871
*/
872
return false;
873
@@ -XXX,XX +XXX,XX @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
874
CPUARMState *env = &cpu->env;
875
uint64_t cr;
876
int pac, hmc, ssc, wt, lbn;
877
- /* Note that for watchpoints the check is against the CPU security
878
+ /*
879
+ * Note that for watchpoints the check is against the CPU security
880
* state, not the S/NS attribute on the offending data access.
881
*/
882
bool is_secure = arm_is_secure(env);
883
@@ -XXX,XX +XXX,XX @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
884
}
885
cr = env->cp15.dbgwcr[n];
886
if (wp->hitattrs.user) {
887
- /* The LDRT/STRT/LDT/STT "unprivileged access" instructions should
888
+ /*
889
+ * The LDRT/STRT/LDT/STT "unprivileged access" instructions should
890
* match watchpoints as if they were accesses done at EL0, even if
891
* the CPU is at EL1 or higher.
892
*/
893
@@ -XXX,XX +XXX,XX @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
894
}
895
cr = env->cp15.dbgbcr[n];
896
}
897
- /* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
898
+ /*
899
+ * The WATCHPOINT_HIT flag guarantees us that the watchpoint is
900
* enabled and that the address and access type match; for breakpoints
901
* we know the address matched; check the remaining fields, including
902
* linked breakpoints. We rely on WCR and BCR having the same layout
903
@@ -XXX,XX +XXX,XX @@ static bool check_watchpoints(ARMCPU *cpu)
904
CPUARMState *env = &cpu->env;
905
int n;
906
907
- /* If watchpoints are disabled globally or we can't take debug
908
+ /*
909
+ * If watchpoints are disabled globally or we can't take debug
910
* exceptions here then watchpoint firings are ignored.
911
*/
912
if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
913
@@ -XXX,XX +XXX,XX @@ static bool check_breakpoints(ARMCPU *cpu)
914
CPUARMState *env = &cpu->env;
915
int n;
916
917
- /* If breakpoints are disabled globally or we can't take debug
918
+ /*
919
+ * If breakpoints are disabled globally or we can't take debug
920
* exceptions here then breakpoint firings are ignored.
921
*/
922
if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
923
@@ -XXX,XX +XXX,XX @@ void HELPER(check_breakpoints)(CPUARMState *env)
924
925
bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
926
{
927
- /* Called by core code when a CPU watchpoint fires; need to check if this
928
+ /*
929
+ * Called by core code when a CPU watchpoint fires; need to check if this
930
* is also an architectural watchpoint match.
931
*/
932
ARMCPU *cpu = ARM_CPU(cs);
933
@@ -XXX,XX +XXX,XX @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
934
ARMCPU *cpu = ARM_CPU(cs);
935
CPUARMState *env = &cpu->env;
936
937
- /* In BE32 system mode, target memory is stored byteswapped (on a
938
+ /*
939
+ * In BE32 system mode, target memory is stored byteswapped (on a
940
* little-endian host system), and by the time we reach here (via an
941
* opcode helper) the addresses of subword accesses have been adjusted
942
* to account for that, which means that watchpoints will not match.
943
@@ -XXX,XX +XXX,XX @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
944
945
void arm_debug_excp_handler(CPUState *cs)
946
{
947
- /* Called by core code when a watchpoint or breakpoint fires;
948
+ /*
949
+ * Called by core code when a watchpoint or breakpoint fires;
950
* need to check which one and raise the appropriate exception.
951
*/
952
ARMCPU *cpu = ARM_CPU(cs);
953
@@ -XXX,XX +XXX,XX @@ void arm_debug_excp_handler(CPUState *cs)
954
uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
955
bool same_el = (arm_debug_target_el(env) == arm_current_el(env));
956
957
- /* (1) GDB breakpoints should be handled first.
958
+ /*
959
+ * (1) GDB breakpoints should be handled first.
960
* (2) Do not raise a CPU exception if no CPU breakpoint has fired,
961
* since singlestep is also done by generating a debug internal
962
* exception.
963
@@ -XXX,XX +XXX,XX @@ void arm_debug_excp_handler(CPUState *cs)
964
}
965
966
env->exception.fsr = arm_debug_exception_fsr(env);
967
- /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
968
+ /*
969
+ * FAR is UNKNOWN: clear vaddress to avoid potentially exposing
970
* values to the guest that it shouldn't be able to see at its
971
* exception/security level.
972
*/
973
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
974
index XXXXXXX..XXXXXXX 100644
975
--- a/target/arm/vfp_helper.c
976
+++ b/target/arm/vfp_helper.c
977
@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
978
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
979
}
980
981
- /* The exception flags are ORed together when we read fpscr so we
982
+ /*
983
+ * The exception flags are ORed together when we read fpscr so we
984
* only need to preserve the current state in one of our
985
* float_status values.
986
*/
987
--
65
--
988
2.20.1
66
2.20.1
989
67
990
68
diff view generated by jsdifflib
[Qemu-devel] [PULL 43/46] target/arm/vfp_helper: Restrict the SoftFloat use to TCG
[PULL 08/24] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
2
insns had some bugs:
3
* the 32x32 multiply of elements was being done as 32x32->32,
4
not 32x32->64
5
* we were incorrectly maintaining the accumulator in its full
6
72-bit form across all 4 beats of the insn; in the pseudocode
7
it is squashed back into the 64 bits of the RdaHi:RdaLo
8
registers after each beat
2
9
3
This code is specific to the SoftFloat floating-point
10
In particular, fixing the second of these allows us to recast
4
implementation, which is only used by TCG.
11
the implementation to avoid 128-bit arithmetic entirely.
5
12
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Since the element size here is always 4, we can also drop the
7
Message-id: 20190701132516.26392-18-philmd@redhat.com
14
parameterization of ESIZE to make the code a little more readable.
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
16
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
10
---
20
---
11
target/arm/vfp_helper.c | 26 +++++++++++++++++++++++---
21
target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
12
1 file changed, 23 insertions(+), 3 deletions(-)
22
1 file changed, 21 insertions(+), 17 deletions(-)
13
23
14
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
24
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
15
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/vfp_helper.c
26
--- a/target/arm/mve_helper.c
17
+++ b/target/arm/vfp_helper.c
27
+++ b/target/arm/mve_helper.c
18
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@
19
*/
29
*/
20
30
21
#include "qemu/osdep.h"
31
#include "qemu/osdep.h"
22
-#include "qemu/log.h"
32
-#include "qemu/int128.h"
23
#include "cpu.h"
33
#include "cpu.h"
24
#include "exec/helper-proto.h"
25
-#include "fpu/softfloat.h"
26
#include "internals.h"
34
#include "internals.h"
27
-
35
#include "vec_internal.h"
28
+#ifdef CONFIG_TCG
36
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
29
+#include "qemu/log.h"
37
DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
30
+#include "fpu/softfloat.h"
38
31
+#endif
39
/*
32
40
- * Rounding multiply add long dual accumulate high: we must keep
33
/* VFP support. We follow the convention used for VFP instructions:
41
- * a 72-bit internal accumulator value and return the top 64 bits.
34
Single precision routines have a "s" suffix, double precision a
42
+ * Rounding multiply add long dual accumulate high. In the pseudocode
35
"d" suffix. */
43
+ * this is implemented with a 72-bit internal accumulator value of which
36
44
+ * the top 64 bits are returned. We optimize this to avoid having to
37
+#ifdef CONFIG_TCG
45
+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
38
+
46
+ * is squashed back into 64-bits after each beat.
39
/* Convert host exception flags to vfp form. */
47
*/
40
static inline int vfp_exceptbits_from_host(int host_bits)
48
-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \
41
{
49
+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \
42
@@ -XXX,XX +XXX,XX @@ static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
50
uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
43
set_float_exception_flags(0, &env->vfp.standard_fp_status);
51
void *vm, uint64_t a) \
44
}
52
{ \
45
53
uint16_t mask = mve_element_mask(env); \
46
+#else
54
unsigned e; \
47
+
55
TYPE *n = vn, *m = vm; \
48
+static uint32_t vfp_get_fpscr_from_host(CPUARMState *env)
56
- Int128 acc = int128_lshift(TO128(a), 8); \
49
+{
57
- for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
50
+ return 0;
58
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
51
+}
59
if (mask & 1) { \
52
+
60
+ LTYPE mul; \
53
+static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
61
if (e & 1) { \
54
+{
62
- acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
55
+}
63
- m[H##ESIZE(e)])); \
56
+
64
+ mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \
57
+#endif
65
+ if (SUB) { \
58
+
66
+ mul = -mul; \
59
uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
67
+ } \
60
{
68
} else { \
61
uint32_t i, fpscr;
69
- acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
62
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val)
70
- m[H##ESIZE(e)])); \
63
HELPER(vfp_set_fpscr)(env, val);
71
+ mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \
64
}
72
} \
65
73
- acc = int128_add(acc, int128_make64(1 << 7)); \
66
+#ifdef CONFIG_TCG
74
+ mul = (mul >> 8) + ((mul >> 7) & 1); \
67
+
75
+ a += mul; \
68
#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
76
} \
69
77
} \
70
#define VFP_BINOP(name) \
78
mve_advance_vpt(env); \
71
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frint64_d)(float64 f, void *fpst)
79
- return int128_getlo(int128_rshift(acc, 8)); \
72
{
80
+ return a; \
73
return frint_d(f, fpst, 64);
81
}
74
}
82
75
+
83
-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
76
+#endif
84
-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
85
+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
86
+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
87
88
-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
89
+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
90
91
-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
92
-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
93
+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
94
+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
95
96
/* Vector add across vector */
97
#define DO_VADDV(OP, ESIZE, TYPE) \
77
--
98
--
78
2.20.1
99
2.20.1
79
100
80
101
diff view generated by jsdifflib
[Qemu-devel] [PULL 36/46] target/arm: Move the DC ZVA helper into op_helper
[PULL 09/24] target/arm: Make asimd_imm_const() public
1
From: Samuel Ortiz <sameo@linux.intel.com>
1
The function asimd_imm_const() in translate-neon.c is an
2
implementation of the pseudocode AdvSIMDExpandImm(), which we will
3
also want for MVE. Move the implementation to translate.c, with a
4
prototype in translate.h.
2
5
3
Those helpers are a software implementation of the ARM v8 memory zeroing
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
op code. They should be moved to the op helper file, which is going to
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
eventually be built only when TCG is enabled.
8
Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
9
---
10
target/arm/translate.h | 16 ++++++++++
11
target/arm/translate-neon.c | 63 -------------------------------------
12
target/arm/translate.c | 57 +++++++++++++++++++++++++++++++++
13
3 files changed, 73 insertions(+), 63 deletions(-)
6
14
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
8
Reviewed-by: Robert Bradford <robert.bradford@intel.com>
9
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20190701132516.26392-10-philmd@redhat.com
13
[PMD: Rebased]
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
target/arm/helper.c | 92 -----------------------------------------
19
target/arm/op_helper.c | 93 ++++++++++++++++++++++++++++++++++++++++++
20
2 files changed, 93 insertions(+), 92 deletions(-)
21
22
diff --git a/target/arm/helper.c b/target/arm/helper.c
23
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/helper.c
17
--- a/target/arm/translate.h
25
+++ b/target/arm/helper.c
18
+++ b/target/arm/translate.h
26
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
27
#endif
20
return opc | s->be_data;
28
}
21
}
29
22
30
-void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
23
+/**
24
+ * asimd_imm_const: Expand an encoded SIMD constant value
25
+ *
26
+ * Expand a SIMD constant value. This is essentially the pseudocode
27
+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
28
+ * VMVN and VBIC (when cmode < 14 && op == 1).
29
+ *
30
+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
31
+ * callers must catch this.
32
+ *
33
+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
34
+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
35
+ * we produce an immediate constant value of 0 in these cases.
36
+ */
37
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
38
+
39
#endif /* TARGET_ARM_TRANSLATE_H */
40
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/translate-neon.c
43
+++ b/target/arm/translate-neon.c
44
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
45
DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
46
DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
47
48
-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
31
-{
49
-{
32
- /*
50
- /*
33
- * Implement DC ZVA, which zeroes a fixed-length block of memory.
51
- * Expand the encoded constant.
34
- * Note that we do not implement the (architecturally mandated)
52
- * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
35
- * alignment fault for attempts to use this on Device memory
53
- * We choose to not special-case this and will behave as if a
36
- * (which matches the usual QEMU behaviour of not implementing either
54
- * valid constant encoding of 0 had been given.
37
- * alignment faults or any memory attribute handling).
55
- * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
38
- */
56
- */
57
- switch (cmode) {
58
- case 0: case 1:
59
- /* no-op */
60
- break;
61
- case 2: case 3:
62
- imm <<= 8;
63
- break;
64
- case 4: case 5:
65
- imm <<= 16;
66
- break;
67
- case 6: case 7:
68
- imm <<= 24;
69
- break;
70
- case 8: case 9:
71
- imm |= imm << 16;
72
- break;
73
- case 10: case 11:
74
- imm = (imm << 8) | (imm << 24);
75
- break;
76
- case 12:
77
- imm = (imm << 8) | 0xff;
78
- break;
79
- case 13:
80
- imm = (imm << 16) | 0xffff;
81
- break;
82
- case 14:
83
- if (op) {
84
- /*
85
- * This is the only case where the top and bottom 32 bits
86
- * of the encoded constant differ.
87
- */
88
- uint64_t imm64 = 0;
89
- int n;
39
-
90
-
40
- ARMCPU *cpu = env_archcpu(env);
91
- for (n = 0; n < 8; n++) {
41
- uint64_t blocklen = 4 << cpu->dcz_blocksize;
92
- if (imm & (1 << n)) {
42
- uint64_t vaddr = vaddr_in & ~(blocklen - 1);
93
- imm64 |= (0xffULL << (n * 8));
43
-
44
-#ifndef CONFIG_USER_ONLY
45
- {
46
- /*
47
- * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
48
- * the block size so we might have to do more than one TLB lookup.
49
- * We know that in fact for any v8 CPU the page size is at least 4K
50
- * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
51
- * 1K as an artefact of legacy v5 subpage support being present in the
52
- * same QEMU executable. So in practice the hostaddr[] array has
53
- * two entries, given the current setting of TARGET_PAGE_BITS_MIN.
54
- */
55
- int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
56
- void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)];
57
- int try, i;
58
- unsigned mmu_idx = cpu_mmu_index(env, false);
59
- TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
60
-
61
- assert(maxidx <= ARRAY_SIZE(hostaddr));
62
-
63
- for (try = 0; try < 2; try++) {
64
-
65
- for (i = 0; i < maxidx; i++) {
66
- hostaddr[i] = tlb_vaddr_to_host(env,
67
- vaddr + TARGET_PAGE_SIZE * i,
68
- 1, mmu_idx);
69
- if (!hostaddr[i]) {
70
- break;
71
- }
94
- }
72
- }
95
- }
73
- if (i == maxidx) {
96
- return imm64;
74
- /*
75
- * If it's all in the TLB it's fair game for just writing to;
76
- * we know we don't need to update dirty status, etc.
77
- */
78
- for (i = 0; i < maxidx - 1; i++) {
79
- memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
80
- }
81
- memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
82
- return;
83
- }
84
- /*
85
- * OK, try a store and see if we can populate the tlb. This
86
- * might cause an exception if the memory isn't writable,
87
- * in which case we will longjmp out of here. We must for
88
- * this purpose use the actual register value passed to us
89
- * so that we get the fault address right.
90
- */
91
- helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC());
92
- /* Now we can populate the other TLB entries, if any */
93
- for (i = 0; i < maxidx; i++) {
94
- uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
95
- if (va != (vaddr_in & TARGET_PAGE_MASK)) {
96
- helper_ret_stb_mmu(env, va, 0, oi, GETPC());
97
- }
98
- }
99
- }
97
- }
100
-
98
- imm |= (imm << 8) | (imm << 16) | (imm << 24);
101
- /*
99
- break;
102
- * Slow path (probably attempt to do this to an I/O device or
100
- case 15:
103
- * similar, or clearing of a block of code we have translations
101
- imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
104
- * cached for). Just do a series of byte writes as the architecture
102
- | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
105
- * demands. It's not worth trying to use a cpu_physical_memory_map(),
103
- break;
106
- * memset(), unmap() sequence here because:
107
- * + we'd need to account for the blocksize being larger than a page
108
- * + the direct-RAM access case is almost always going to be dealt
109
- * with in the fastpath code above, so there's no speed benefit
110
- * + we would have to deal with the map returning NULL because the
111
- * bounce buffer was in use
112
- */
113
- for (i = 0; i < blocklen; i++) {
114
- helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC());
115
- }
116
- }
104
- }
117
-#else
105
- if (op) {
118
- memset(g2h(vaddr), 0, blocklen);
106
- imm = ~imm;
119
-#endif
107
- }
108
- return dup_const(MO_32, imm);
120
-}
109
-}
121
-
110
-
122
/* Note that signed overflow is undefined in C. The following routines are
111
static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
123
careful to use unsigned types where modulo arithmetic is required.
112
GVecGen2iFn *fn)
124
Failure to do so _will_ break on newer gcc. */
113
{
125
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
114
diff --git a/target/arm/translate.c b/target/arm/translate.c
126
index XXXXXXX..XXXXXXX 100644
115
index XXXXXXX..XXXXXXX 100644
127
--- a/target/arm/op_helper.c
116
--- a/target/arm/translate.c
128
+++ b/target/arm/op_helper.c
117
+++ b/target/arm/translate.c
129
@@ -XXX,XX +XXX,XX @@
118
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
130
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
119
a64_translate_init();
131
*/
132
#include "qemu/osdep.h"
133
+#include "qemu/units.h"
134
#include "qemu/log.h"
135
#include "qemu/main-loop.h"
136
#include "cpu.h"
137
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
138
return ((uint32_t)x >> shift) | (x << (32 - shift));
139
}
140
}
120
}
121
122
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
123
+{
124
+ /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
125
+ switch (cmode) {
126
+ case 0: case 1:
127
+ /* no-op */
128
+ break;
129
+ case 2: case 3:
130
+ imm <<= 8;
131
+ break;
132
+ case 4: case 5:
133
+ imm <<= 16;
134
+ break;
135
+ case 6: case 7:
136
+ imm <<= 24;
137
+ break;
138
+ case 8: case 9:
139
+ imm |= imm << 16;
140
+ break;
141
+ case 10: case 11:
142
+ imm = (imm << 8) | (imm << 24);
143
+ break;
144
+ case 12:
145
+ imm = (imm << 8) | 0xff;
146
+ break;
147
+ case 13:
148
+ imm = (imm << 16) | 0xffff;
149
+ break;
150
+ case 14:
151
+ if (op) {
152
+ /*
153
+ * This is the only case where the top and bottom 32 bits
154
+ * of the encoded constant differ.
155
+ */
156
+ uint64_t imm64 = 0;
157
+ int n;
141
+
158
+
142
+void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
159
+ for (n = 0; n < 8; n++) {
143
+{
160
+ if (imm & (1 << n)) {
144
+ /*
161
+ imm64 |= (0xffULL << (n * 8));
145
+ * Implement DC ZVA, which zeroes a fixed-length block of memory.
146
+ * Note that we do not implement the (architecturally mandated)
147
+ * alignment fault for attempts to use this on Device memory
148
+ * (which matches the usual QEMU behaviour of not implementing either
149
+ * alignment faults or any memory attribute handling).
150
+ */
151
+
152
+ ARMCPU *cpu = env_archcpu(env);
153
+ uint64_t blocklen = 4 << cpu->dcz_blocksize;
154
+ uint64_t vaddr = vaddr_in & ~(blocklen - 1);
155
+
156
+#ifndef CONFIG_USER_ONLY
157
+ {
158
+ /*
159
+ * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
160
+ * the block size so we might have to do more than one TLB lookup.
161
+ * We know that in fact for any v8 CPU the page size is at least 4K
162
+ * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
163
+ * 1K as an artefact of legacy v5 subpage support being present in the
164
+ * same QEMU executable. So in practice the hostaddr[] array has
165
+ * two entries, given the current setting of TARGET_PAGE_BITS_MIN.
166
+ */
167
+ int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
168
+ void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)];
169
+ int try, i;
170
+ unsigned mmu_idx = cpu_mmu_index(env, false);
171
+ TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
172
+
173
+ assert(maxidx <= ARRAY_SIZE(hostaddr));
174
+
175
+ for (try = 0; try < 2; try++) {
176
+
177
+ for (i = 0; i < maxidx; i++) {
178
+ hostaddr[i] = tlb_vaddr_to_host(env,
179
+ vaddr + TARGET_PAGE_SIZE * i,
180
+ 1, mmu_idx);
181
+ if (!hostaddr[i]) {
182
+ break;
183
+ }
162
+ }
184
+ }
163
+ }
185
+ if (i == maxidx) {
164
+ return imm64;
186
+ /*
187
+ * If it's all in the TLB it's fair game for just writing to;
188
+ * we know we don't need to update dirty status, etc.
189
+ */
190
+ for (i = 0; i < maxidx - 1; i++) {
191
+ memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
192
+ }
193
+ memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
194
+ return;
195
+ }
196
+ /*
197
+ * OK, try a store and see if we can populate the tlb. This
198
+ * might cause an exception if the memory isn't writable,
199
+ * in which case we will longjmp out of here. We must for
200
+ * this purpose use the actual register value passed to us
201
+ * so that we get the fault address right.
202
+ */
203
+ helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC());
204
+ /* Now we can populate the other TLB entries, if any */
205
+ for (i = 0; i < maxidx; i++) {
206
+ uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
207
+ if (va != (vaddr_in & TARGET_PAGE_MASK)) {
208
+ helper_ret_stb_mmu(env, va, 0, oi, GETPC());
209
+ }
210
+ }
211
+ }
165
+ }
166
+ imm |= (imm << 8) | (imm << 16) | (imm << 24);
167
+ break;
168
+ case 15:
169
+ imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
170
+ | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
171
+ break;
172
+ }
173
+ if (op) {
174
+ imm = ~imm;
175
+ }
176
+ return dup_const(MO_32, imm);
177
+}
212
+
178
+
213
+ /*
179
/* Generate a label used for skipping this instruction */
214
+ * Slow path (probably attempt to do this to an I/O device or
180
void arm_gen_condlabel(DisasContext *s)
215
+ * similar, or clearing of a block of code we have translations
181
{
216
+ * cached for). Just do a series of byte writes as the architecture
217
+ * demands. It's not worth trying to use a cpu_physical_memory_map(),
218
+ * memset(), unmap() sequence here because:
219
+ * + we'd need to account for the blocksize being larger than a page
220
+ * + the direct-RAM access case is almost always going to be dealt
221
+ * with in the fastpath code above, so there's no speed benefit
222
+ * + we would have to deal with the map returning NULL because the
223
+ * bounce buffer was in use
224
+ */
225
+ for (i = 0; i < blocklen; i++) {
226
+ helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC());
227
+ }
228
+ }
229
+#else
230
+ memset(g2h(vaddr), 0, blocklen);
231
+#endif
232
+}
233
--
182
--
234
2.20.1
183
2.20.1
235
184
236
185
diff view generated by jsdifflib
[Qemu-devel] [PULL 37/46] target/arm: Move CPU state dumping routines to cpu.c
[PULL 10/24] target/arm: Use asimd_imm_const for A64 decode
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
The A64 AdvSIMD modified-immediate grouping uses almost the same
2
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
3
which we add the AArch64-specific case for cmode 15 op 1) instead of
4
reimplementing it all.
2
5
3
Suggested-by: Samuel Ortiz <sameo@linux.intel.com>
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Message-id: 20190701132516.26392-11-philmd@redhat.com
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
8
---
9
---
9
target/arm/cpu.h | 2 -
10
target/arm/translate.h | 3 +-
10
target/arm/translate.h | 5 -
11
target/arm/translate-a64.c | 86 ++++----------------------------------
11
target/arm/cpu.c | 226 +++++++++++++++++++++++++++++++++++++
12
target/arm/translate.c | 17 +++++++-
12
target/arm/translate-a64.c | 128 ---------------------
13
3 files changed, 24 insertions(+), 82 deletions(-)
13
target/arm/translate.c | 88 ---------------
14
5 files changed, 226 insertions(+), 223 deletions(-)
15
14
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cpu);
21
void arm_v7m_cpu_do_interrupt(CPUState *cpu);
22
bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
23
24
-void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags);
25
-
26
hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
27
MemTxAttrs *attrs);
28
29
diff --git a/target/arm/translate.h b/target/arm/translate.h
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
30
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/translate.h
17
--- a/target/arm/translate.h
32
+++ b/target/arm/translate.h
18
+++ b/target/arm/translate.h
33
@@ -XXX,XX +XXX,XX @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
34
#ifdef TARGET_AARCH64
20
* VMVN and VBIC (when cmode < 14 && op == 1).
35
void a64_translate_init(void);
21
*
36
void gen_a64_set_pc_im(uint64_t val);
22
* The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
37
-void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags);
23
- * callers must catch this.
38
extern const TranslatorOps aarch64_translator_ops;
24
+ * callers must catch this; we return the 64-bit constant value defined
39
#else
25
+ * for AArch64.
40
static inline void a64_translate_init(void)
26
*
41
@@ -XXX,XX +XXX,XX @@ static inline void a64_translate_init(void)
27
* cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
42
static inline void gen_a64_set_pc_im(uint64_t val)
28
* is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
43
{
44
}
45
-
46
-static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
47
-{
48
-}
49
#endif
50
51
void arm_test_cc(DisasCompare *cmp, int cc);
52
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/cpu.c
55
+++ b/target/arm/cpu.c
56
@@ -XXX,XX +XXX,XX @@
57
*/
58
59
#include "qemu/osdep.h"
60
+#include "qemu/qemu-print.h"
61
#include "qemu-common.h"
62
#include "target/arm/idau.h"
63
#include "qemu/module.h"
64
@@ -XXX,XX +XXX,XX @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
65
#endif
66
}
67
68
+#ifdef TARGET_AARCH64
69
+
70
+static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
71
+{
72
+ ARMCPU *cpu = ARM_CPU(cs);
73
+ CPUARMState *env = &cpu->env;
74
+ uint32_t psr = pstate_read(env);
75
+ int i;
76
+ int el = arm_current_el(env);
77
+ const char *ns_status;
78
+
79
+ qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
80
+ for (i = 0; i < 32; i++) {
81
+ if (i == 31) {
82
+ qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
83
+ } else {
84
+ qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
85
+ (i + 2) % 3 ? " " : "\n");
86
+ }
87
+ }
88
+
89
+ if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
90
+ ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
91
+ } else {
92
+ ns_status = "";
93
+ }
94
+ qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
95
+ psr,
96
+ psr & PSTATE_N ? 'N' : '-',
97
+ psr & PSTATE_Z ? 'Z' : '-',
98
+ psr & PSTATE_C ? 'C' : '-',
99
+ psr & PSTATE_V ? 'V' : '-',
100
+ ns_status,
101
+ el,
102
+ psr & PSTATE_SP ? 'h' : 't');
103
+
104
+ if (cpu_isar_feature(aa64_bti, cpu)) {
105
+ qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
106
+ }
107
+ if (!(flags & CPU_DUMP_FPU)) {
108
+ qemu_fprintf(f, "\n");
109
+ return;
110
+ }
111
+ if (fp_exception_el(env, el) != 0) {
112
+ qemu_fprintf(f, " FPU disabled\n");
113
+ return;
114
+ }
115
+ qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
116
+ vfp_get_fpcr(env), vfp_get_fpsr(env));
117
+
118
+ if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
119
+ int j, zcr_len = sve_zcr_len_for_el(env, el);
120
+
121
+ for (i = 0; i <= FFR_PRED_NUM; i++) {
122
+ bool eol;
123
+ if (i == FFR_PRED_NUM) {
124
+ qemu_fprintf(f, "FFR=");
125
+ /* It's last, so end the line. */
126
+ eol = true;
127
+ } else {
128
+ qemu_fprintf(f, "P%02d=", i);
129
+ switch (zcr_len) {
130
+ case 0:
131
+ eol = i % 8 == 7;
132
+ break;
133
+ case 1:
134
+ eol = i % 6 == 5;
135
+ break;
136
+ case 2:
137
+ case 3:
138
+ eol = i % 3 == 2;
139
+ break;
140
+ default:
141
+ /* More than one quadword per predicate. */
142
+ eol = true;
143
+ break;
144
+ }
145
+ }
146
+ for (j = zcr_len / 4; j >= 0; j--) {
147
+ int digits;
148
+ if (j * 4 + 4 <= zcr_len + 1) {
149
+ digits = 16;
150
+ } else {
151
+ digits = (zcr_len % 4 + 1) * 4;
152
+ }
153
+ qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
154
+ env->vfp.pregs[i].p[j],
155
+ j ? ":" : eol ? "\n" : " ");
156
+ }
157
+ }
158
+
159
+ for (i = 0; i < 32; i++) {
160
+ if (zcr_len == 0) {
161
+ qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
162
+ i, env->vfp.zregs[i].d[1],
163
+ env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
164
+ } else if (zcr_len == 1) {
165
+ qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
166
+ ":%016" PRIx64 ":%016" PRIx64 "\n",
167
+ i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
168
+ env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
169
+ } else {
170
+ for (j = zcr_len; j >= 0; j--) {
171
+ bool odd = (zcr_len - j) % 2 != 0;
172
+ if (j == zcr_len) {
173
+ qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
174
+ } else if (!odd) {
175
+ if (j > 0) {
176
+ qemu_fprintf(f, " [%x-%x]=", j, j - 1);
177
+ } else {
178
+ qemu_fprintf(f, " [%x]=", j);
179
+ }
180
+ }
181
+ qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
182
+ env->vfp.zregs[i].d[j * 2 + 1],
183
+ env->vfp.zregs[i].d[j * 2],
184
+ odd || j == 0 ? "\n" : ":");
185
+ }
186
+ }
187
+ }
188
+ } else {
189
+ for (i = 0; i < 32; i++) {
190
+ uint64_t *q = aa64_vfp_qreg(env, i);
191
+ qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
192
+ i, q[1], q[0], (i & 1 ? "\n" : " "));
193
+ }
194
+ }
195
+}
196
+
197
+#else
198
+
199
+static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
200
+{
201
+ g_assert_not_reached();
202
+}
203
+
204
+#endif
205
+
206
+static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
207
+{
208
+ ARMCPU *cpu = ARM_CPU(cs);
209
+ CPUARMState *env = &cpu->env;
210
+ int i;
211
+
212
+ if (is_a64(env)) {
213
+ aarch64_cpu_dump_state(cs, f, flags);
214
+ return;
215
+ }
216
+
217
+ for (i = 0; i < 16; i++) {
218
+ qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
219
+ if ((i % 4) == 3) {
220
+ qemu_fprintf(f, "\n");
221
+ } else {
222
+ qemu_fprintf(f, " ");
223
+ }
224
+ }
225
+
226
+ if (arm_feature(env, ARM_FEATURE_M)) {
227
+ uint32_t xpsr = xpsr_read(env);
228
+ const char *mode;
229
+ const char *ns_status = "";
230
+
231
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
232
+ ns_status = env->v7m.secure ? "S " : "NS ";
233
+ }
234
+
235
+ if (xpsr & XPSR_EXCP) {
236
+ mode = "handler";
237
+ } else {
238
+ if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
239
+ mode = "unpriv-thread";
240
+ } else {
241
+ mode = "priv-thread";
242
+ }
243
+ }
244
+
245
+ qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
246
+ xpsr,
247
+ xpsr & XPSR_N ? 'N' : '-',
248
+ xpsr & XPSR_Z ? 'Z' : '-',
249
+ xpsr & XPSR_C ? 'C' : '-',
250
+ xpsr & XPSR_V ? 'V' : '-',
251
+ xpsr & XPSR_T ? 'T' : 'A',
252
+ ns_status,
253
+ mode);
254
+ } else {
255
+ uint32_t psr = cpsr_read(env);
256
+ const char *ns_status = "";
257
+
258
+ if (arm_feature(env, ARM_FEATURE_EL3) &&
259
+ (psr & CPSR_M) != ARM_CPU_MODE_MON) {
260
+ ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
261
+ }
262
+
263
+ qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
264
+ psr,
265
+ psr & CPSR_N ? 'N' : '-',
266
+ psr & CPSR_Z ? 'Z' : '-',
267
+ psr & CPSR_C ? 'C' : '-',
268
+ psr & CPSR_V ? 'V' : '-',
269
+ psr & CPSR_T ? 'T' : 'A',
270
+ ns_status,
271
+ aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
272
+ }
273
+
274
+ if (flags & CPU_DUMP_FPU) {
275
+ int numvfpregs = 0;
276
+ if (arm_feature(env, ARM_FEATURE_VFP)) {
277
+ numvfpregs += 16;
278
+ }
279
+ if (arm_feature(env, ARM_FEATURE_VFP3)) {
280
+ numvfpregs += 16;
281
+ }
282
+ for (i = 0; i < numvfpregs; i++) {
283
+ uint64_t v = *aa32_vfp_dreg(env, i);
284
+ qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
285
+ i * 2, (uint32_t)v,
286
+ i * 2 + 1, (uint32_t)(v >> 32),
287
+ i, v);
288
+ }
289
+ qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
290
+ }
291
+}
292
+
293
uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
294
{
295
uint32_t Aff1 = idx / clustersz;
296
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
29
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
297
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
298
--- a/target/arm/translate-a64.c
31
--- a/target/arm/translate-a64.c
299
+++ b/target/arm/translate-a64.c
32
+++ b/target/arm/translate-a64.c
300
@@ -XXX,XX +XXX,XX @@
33
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
301
#include "translate.h"
34
{
302
#include "internals.h"
35
int rd = extract32(insn, 0, 5);
303
#include "qemu/host-utils.h"
36
int cmode = extract32(insn, 12, 4);
304
-#include "qemu/qemu-print.h"
37
- int cmode_3_1 = extract32(cmode, 1, 3);
305
38
- int cmode_0 = extract32(cmode, 0, 1);
306
#include "hw/semihosting/semihost.h"
39
int o2 = extract32(insn, 11, 1);
307
#include "exec/gen-icount.h"
40
uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
308
@@ -XXX,XX +XXX,XX @@ static void set_btype(DisasContext *s, int val)
41
bool is_neg = extract32(insn, 29, 1);
309
s->btype = -1;
42
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
310
}
43
return;
311
44
}
312
-void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
45
313
-{
46
- /* See AdvSIMDExpandImm() in ARM ARM */
314
- ARMCPU *cpu = ARM_CPU(cs);
47
- switch (cmode_3_1) {
315
- CPUARMState *env = &cpu->env;
48
- case 0: /* Replicate(Zeros(24):imm8, 2) */
316
- uint32_t psr = pstate_read(env);
49
- case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
317
- int i;
50
- case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
318
- int el = arm_current_el(env);
51
- case 3: /* Replicate(imm8:Zeros(24), 2) */
319
- const char *ns_status;
52
- {
320
-
53
- int shift = cmode_3_1 * 8;
321
- qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
54
- imm = bitfield_replicate(abcdefgh << shift, 32);
322
- for (i = 0; i < 32; i++) {
55
- break;
323
- if (i == 31) {
56
- }
324
- qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
57
- case 4: /* Replicate(Zeros(8):imm8, 4) */
58
- case 5: /* Replicate(imm8:Zeros(8), 4) */
59
- {
60
- int shift = (cmode_3_1 & 0x1) * 8;
61
- imm = bitfield_replicate(abcdefgh << shift, 16);
62
- break;
63
- }
64
- case 6:
65
- if (cmode_0) {
66
- /* Replicate(Zeros(8):imm8:Ones(16), 2) */
67
- imm = (abcdefgh << 16) | 0xffff;
325
- } else {
68
- } else {
326
- qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
69
- /* Replicate(Zeros(16):imm8:Ones(8), 2) */
327
- (i + 2) % 3 ? " " : "\n");
70
- imm = (abcdefgh << 8) | 0xff;
328
- }
71
- }
329
- }
72
- imm = bitfield_replicate(imm, 32);
330
-
73
- break;
331
- if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
74
- case 7:
332
- ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
75
- if (!cmode_0 && !is_neg) {
333
- } else {
76
- imm = bitfield_replicate(abcdefgh, 8);
334
- ns_status = "";
77
- } else if (!cmode_0 && is_neg) {
335
- }
78
- int i;
336
- qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
79
- imm = 0;
337
- psr,
80
- for (i = 0; i < 8; i++) {
338
- psr & PSTATE_N ? 'N' : '-',
81
- if ((abcdefgh) & (1 << i)) {
339
- psr & PSTATE_Z ? 'Z' : '-',
82
- imm |= 0xffULL << (i * 8);
340
- psr & PSTATE_C ? 'C' : '-',
341
- psr & PSTATE_V ? 'V' : '-',
342
- ns_status,
343
- el,
344
- psr & PSTATE_SP ? 'h' : 't');
345
-
346
- if (cpu_isar_feature(aa64_bti, cpu)) {
347
- qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
348
- }
349
- if (!(flags & CPU_DUMP_FPU)) {
350
- qemu_fprintf(f, "\n");
351
- return;
352
- }
353
- if (fp_exception_el(env, el) != 0) {
354
- qemu_fprintf(f, " FPU disabled\n");
355
- return;
356
- }
357
- qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
358
- vfp_get_fpcr(env), vfp_get_fpsr(env));
359
-
360
- if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
361
- int j, zcr_len = sve_zcr_len_for_el(env, el);
362
-
363
- for (i = 0; i <= FFR_PRED_NUM; i++) {
364
- bool eol;
365
- if (i == FFR_PRED_NUM) {
366
- qemu_fprintf(f, "FFR=");
367
- /* It's last, so end the line. */
368
- eol = true;
369
- } else {
370
- qemu_fprintf(f, "P%02d=", i);
371
- switch (zcr_len) {
372
- case 0:
373
- eol = i % 8 == 7;
374
- break;
375
- case 1:
376
- eol = i % 6 == 5;
377
- break;
378
- case 2:
379
- case 3:
380
- eol = i % 3 == 2;
381
- break;
382
- default:
383
- /* More than one quadword per predicate. */
384
- eol = true;
385
- break;
386
- }
83
- }
387
- }
84
- }
388
- for (j = zcr_len / 4; j >= 0; j--) {
85
- } else if (cmode_0) {
389
- int digits;
86
- if (is_neg) {
390
- if (j * 4 + 4 <= zcr_len + 1) {
87
- imm = (abcdefgh & 0x3f) << 48;
391
- digits = 16;
88
- if (abcdefgh & 0x80) {
89
- imm |= 0x8000000000000000ULL;
90
- }
91
- if (abcdefgh & 0x40) {
92
- imm |= 0x3fc0000000000000ULL;
392
- } else {
93
- } else {
393
- digits = (zcr_len % 4 + 1) * 4;
94
- imm |= 0x4000000000000000ULL;
394
- }
95
- }
395
- qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
396
- env->vfp.pregs[i].p[j],
397
- j ? ":" : eol ? "\n" : " ");
398
- }
399
- }
400
-
401
- for (i = 0; i < 32; i++) {
402
- if (zcr_len == 0) {
403
- qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
404
- i, env->vfp.zregs[i].d[1],
405
- env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
406
- } else if (zcr_len == 1) {
407
- qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
408
- ":%016" PRIx64 ":%016" PRIx64 "\n",
409
- i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
410
- env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
411
- } else {
96
- } else {
412
- for (j = zcr_len; j >= 0; j--) {
97
- if (o2) {
413
- bool odd = (zcr_len - j) % 2 != 0;
98
- /* FMOV (vector, immediate) - half-precision */
414
- if (j == zcr_len) {
99
- imm = vfp_expand_imm(MO_16, abcdefgh);
415
- qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
100
- /* now duplicate across the lanes */
416
- } else if (!odd) {
101
- imm = bitfield_replicate(imm, 16);
417
- if (j > 0) {
102
- } else {
418
- qemu_fprintf(f, " [%x-%x]=", j, j - 1);
103
- imm = (abcdefgh & 0x3f) << 19;
419
- } else {
104
- if (abcdefgh & 0x80) {
420
- qemu_fprintf(f, " [%x]=", j);
105
- imm |= 0x80000000;
421
- }
422
- }
106
- }
423
- qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
107
- if (abcdefgh & 0x40) {
424
- env->vfp.zregs[i].d[j * 2 + 1],
108
- imm |= 0x3e000000;
425
- env->vfp.zregs[i].d[j * 2],
109
- } else {
426
- odd || j == 0 ? "\n" : ":");
110
- imm |= 0x40000000;
111
- }
112
- imm |= (imm << 32);
427
- }
113
- }
428
- }
114
- }
429
- }
115
- }
430
- } else {
116
- break;
431
- for (i = 0; i < 32; i++) {
117
- default:
432
- uint64_t *q = aa64_vfp_qreg(env, i);
118
- g_assert_not_reached();
433
- qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
434
- i, q[1], q[0], (i & 1 ? "\n" : " "));
435
- }
436
- }
119
- }
437
-}
438
-
120
-
439
void gen_a64_set_pc_im(uint64_t val)
121
- if (cmode_3_1 != 7 && is_neg) {
440
{
122
- imm = ~imm;
441
tcg_gen_movi_i64(cpu_pc, val);
123
+ if (cmode == 15 && o2 && !is_neg) {
124
+ /* FMOV (vector, immediate) - half-precision */
125
+ imm = vfp_expand_imm(MO_16, abcdefgh);
126
+ /* now duplicate across the lanes */
127
+ imm = bitfield_replicate(imm, 16);
128
+ } else {
129
+ imm = asimd_imm_const(abcdefgh, cmode, is_neg);
130
}
131
132
if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
442
diff --git a/target/arm/translate.c b/target/arm/translate.c
133
diff --git a/target/arm/translate.c b/target/arm/translate.c
443
index XXXXXXX..XXXXXXX 100644
134
index XXXXXXX..XXXXXXX 100644
444
--- a/target/arm/translate.c
135
--- a/target/arm/translate.c
445
+++ b/target/arm/translate.c
136
+++ b/target/arm/translate.c
446
@@ -XXX,XX +XXX,XX @@
137
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
447
#include "tcg-op-gvec.h"
138
case 14:
448
#include "qemu/log.h"
139
if (op) {
449
#include "qemu/bitops.h"
140
/*
450
-#include "qemu/qemu-print.h"
141
- * This is the only case where the top and bottom 32 bits
451
#include "arm_ldst.h"
142
- * of the encoded constant differ.
452
#include "hw/semihosting/semihost.h"
143
+ * This and cmode == 15 op == 1 are the only cases where
453
144
+ * the top and bottom 32 bits of the encoded constant differ.
454
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
145
*/
455
translator_loop(ops, &dc.base, cpu, tb, max_insns);
146
uint64_t imm64 = 0;
456
}
147
int n;
457
148
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
458
-void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
149
imm |= (imm << 8) | (imm << 16) | (imm << 24);
459
-{
150
break;
460
- ARMCPU *cpu = ARM_CPU(cs);
151
case 15:
461
- CPUARMState *env = &cpu->env;
152
+ if (op) {
462
- int i;
153
+ /* Reserved encoding for AArch32; valid for AArch64 */
463
-
154
+ uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
464
- if (is_a64(env)) {
155
+ if (imm & 0x80) {
465
- aarch64_cpu_dump_state(cs, f, flags);
156
+ imm64 |= 0x8000000000000000ULL;
466
- return;
157
+ }
467
- }
158
+ if (imm & 0x40) {
468
-
159
+ imm64 |= 0x3fc0000000000000ULL;
469
- for (i = 0; i < 16; i++) {
160
+ } else {
470
- qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
161
+ imm64 |= 0x4000000000000000ULL;
471
- if ((i % 4) == 3) {
162
+ }
472
- qemu_fprintf(f, "\n");
163
+ return imm64;
473
- } else {
164
+ }
474
- qemu_fprintf(f, " ");
165
imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
475
- }
166
| ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
476
- }
167
break;
477
-
478
- if (arm_feature(env, ARM_FEATURE_M)) {
479
- uint32_t xpsr = xpsr_read(env);
480
- const char *mode;
481
- const char *ns_status = "";
482
-
483
- if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
484
- ns_status = env->v7m.secure ? "S " : "NS ";
485
- }
486
-
487
- if (xpsr & XPSR_EXCP) {
488
- mode = "handler";
489
- } else {
490
- if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
491
- mode = "unpriv-thread";
492
- } else {
493
- mode = "priv-thread";
494
- }
495
- }
496
-
497
- qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
498
- xpsr,
499
- xpsr & XPSR_N ? 'N' : '-',
500
- xpsr & XPSR_Z ? 'Z' : '-',
501
- xpsr & XPSR_C ? 'C' : '-',
502
- xpsr & XPSR_V ? 'V' : '-',
503
- xpsr & XPSR_T ? 'T' : 'A',
504
- ns_status,
505
- mode);
506
- } else {
507
- uint32_t psr = cpsr_read(env);
508
- const char *ns_status = "";
509
-
510
- if (arm_feature(env, ARM_FEATURE_EL3) &&
511
- (psr & CPSR_M) != ARM_CPU_MODE_MON) {
512
- ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
513
- }
514
-
515
- qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
516
- psr,
517
- psr & CPSR_N ? 'N' : '-',
518
- psr & CPSR_Z ? 'Z' : '-',
519
- psr & CPSR_C ? 'C' : '-',
520
- psr & CPSR_V ? 'V' : '-',
521
- psr & CPSR_T ? 'T' : 'A',
522
- ns_status,
523
- aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
524
- }
525
-
526
- if (flags & CPU_DUMP_FPU) {
527
- int numvfpregs = 0;
528
- if (arm_feature(env, ARM_FEATURE_VFP)) {
529
- numvfpregs += 16;
530
- }
531
- if (arm_feature(env, ARM_FEATURE_VFP3)) {
532
- numvfpregs += 16;
533
- }
534
- for (i = 0; i < numvfpregs; i++) {
535
- uint64_t v = *aa32_vfp_dreg(env, i);
536
- qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
537
- i * 2, (uint32_t)v,
538
- i * 2 + 1, (uint32_t)(v >> 32),
539
- i, v);
540
- }
541
- qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
542
- }
543
-}
544
-
545
void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb,
546
target_ulong *data)
547
{
548
--
168
--
549
2.20.1
169
2.20.1
550
170
551
171
diff view generated by jsdifflib
[Qemu-devel] [PULL 40/46] target/arm/vfp_helper: Move code around
[PULL 11/24] target/arm: Use dup_const() instead of bitfield_replicate()
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Use dup_const() instead of bitfield_replicate() in
2
disas_simd_mod_imm().
2
3
3
To ease the review of the next commit,
4
(We can't replace the other use of bitfield_replicate() in this file,
4
move the vfp_exceptbits_to_host() function directly after
5
in logic_imm_decode_wmask(), because that location needs to handle 2
5
vfp_exceptbits_from_host(). Amusingly the diff shows we
6
and 4 bit elements, which dup_const() cannot.)
6
are moving vfp_get_fpscr().
7
7
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190701132516.26392-15-philmd@redhat.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
12
---
11
---
13
target/arm/vfp_helper.c | 52 ++++++++++++++++++++---------------------
12
target/arm/translate-a64.c | 2 +-
14
1 file changed, 26 insertions(+), 26 deletions(-)
13
1 file changed, 1 insertion(+), 1 deletion(-)
15
14
16
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/vfp_helper.c
17
--- a/target/arm/translate-a64.c
19
+++ b/target/arm/vfp_helper.c
18
+++ b/target/arm/translate-a64.c
20
@@ -XXX,XX +XXX,XX @@ static inline int vfp_exceptbits_from_host(int host_bits)
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
21
return target_bits;
20
/* FMOV (vector, immediate) - half-precision */
22
}
21
imm = vfp_expand_imm(MO_16, abcdefgh);
23
22
/* now duplicate across the lanes */
24
-uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
23
- imm = bitfield_replicate(imm, 16);
25
-{
24
+ imm = dup_const(MO_16, imm);
26
- uint32_t i, fpscr;
25
} else {
27
-
26
imm = asimd_imm_const(abcdefgh, cmode, is_neg);
28
- fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
27
}
29
- | (env->vfp.vec_len << 16)
30
- | (env->vfp.vec_stride << 20);
31
-
32
- i = get_float_exception_flags(&env->vfp.fp_status);
33
- i |= get_float_exception_flags(&env->vfp.standard_fp_status);
34
- /* FZ16 does not generate an input denormal exception. */
35
- i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
36
- & ~float_flag_input_denormal);
37
- fpscr |= vfp_exceptbits_from_host(i);
38
-
39
- i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
40
- fpscr |= i ? FPCR_QC : 0;
41
-
42
- return fpscr;
43
-}
44
-
45
-uint32_t vfp_get_fpscr(CPUARMState *env)
46
-{
47
- return HELPER(vfp_get_fpscr)(env);
48
-}
49
-
50
/* Convert vfp exception flags to target form. */
51
static inline int vfp_exceptbits_to_host(int target_bits)
52
{
53
@@ -XXX,XX +XXX,XX @@ static inline int vfp_exceptbits_to_host(int target_bits)
54
return host_bits;
55
}
56
57
+uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
58
+{
59
+ uint32_t i, fpscr;
60
+
61
+ fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
62
+ | (env->vfp.vec_len << 16)
63
+ | (env->vfp.vec_stride << 20);
64
+
65
+ i = get_float_exception_flags(&env->vfp.fp_status);
66
+ i |= get_float_exception_flags(&env->vfp.standard_fp_status);
67
+ /* FZ16 does not generate an input denormal exception. */
68
+ i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
69
+ & ~float_flag_input_denormal);
70
+ fpscr |= vfp_exceptbits_from_host(i);
71
+
72
+ i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
73
+ fpscr |= i ? FPCR_QC : 0;
74
+
75
+ return fpscr;
76
+}
77
+
78
+uint32_t vfp_get_fpscr(CPUARMState *env)
79
+{
80
+ return HELPER(vfp_get_fpscr)(env);
81
+}
82
+
83
void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
84
{
85
int i;
86
--
28
--
87
2.20.1
29
2.20.1
88
30
89
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/46] aspeed/timer: Fix behaviour running Linux
[PULL 12/24] target/arm: Implement MVE logical immediate insns
1
From: Joel Stanley <joel@jms.id.au>
1
Implement the MVE logical-immediate insns (VMOV, VMVN,
2
VORR and VBIC). These have essentially the same encoding
3
as their Neon equivalents, and we implement the decode
4
in the same way.
2
5
3
The Linux kernel driver was updated in commit 4451d3f59f2a
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
("clocksource/drivers/fttmr010: Fix set_next_event handler) to fix an
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
issue observed on hardware:
8
Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
9
---
10
target/arm/helper-mve.h | 4 +++
11
target/arm/mve.decode | 17 +++++++++++++
12
target/arm/mve_helper.c | 24 ++++++++++++++++++
13
target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
14
4 files changed, 95 insertions(+)
6
15
7
> RELOAD register is loaded into COUNT register when the aspeed timer
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
8
> is enabled, which means the next event may be delayed because timer
9
> interrupt won't be generated until <0xFFFFFFFF - current_count +
10
> cycles>.
11
12
When running under Qemu, the system appeared "laggy". The guest is now
13
scheduling timer events too regularly, starving the host of CPU time.
14
15
This patch modifies the timer model to attempt to schedule the timer
16
expiry as the guest requests, but if we have missed the deadline we
17
re interrupt and try again, which allows the guest to catch up.
18
19
Provides expected behaviour with old and new guest code.
20
21
Fixes: c04bd47db6b9 ("hw/timer: Add ASPEED timer device model")
22
Signed-off-by: Joel Stanley <joel@jms.id.au>
23
Signed-off-by: Cédric Le Goater <clg@kaod.org>
24
Message-id: 20190618165311.27066-8-clg@kaod.org
25
[clg: - merged a fix from Andrew Jeffery <andrew@aj.id.au>
26
"Fire interrupt on failure to meet deadline"
27
https://lists.ozlabs.org/pipermail/openbmc/2019-January/014641.html
28
- adapted commit log
29
- checkpatch fixes ]
30
Signed-off-by: Cédric Le Goater <clg@kaod.org>
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
---
33
hw/timer/aspeed_timer.c | 57 ++++++++++++++++++++++-------------------
34
1 file changed, 30 insertions(+), 27 deletions(-)
35
36
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
37
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/timer/aspeed_timer.c
18
--- a/target/arm/helper-mve.h
39
+++ b/hw/timer/aspeed_timer.c
19
+++ b/target/arm/helper-mve.h
40
@@ -XXX,XX +XXX,XX @@ static inline uint64_t calculate_time(struct AspeedTimer *t, uint32_t ticks)
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
41
21
DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
42
static uint64_t calculate_next(struct AspeedTimer *t)
22
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
43
{
23
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
44
- uint64_t next = 0;
24
+
45
- uint32_t rate = calculate_rate(t);
25
+DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
46
+ uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
26
+DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
47
+ uint64_t next;
27
+DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
48
28
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
49
- while (!next) {
29
index XXXXXXX..XXXXXXX 100644
50
- /* We don't know the relationship between the values in the match
30
--- a/target/arm/mve.decode
51
- * registers, so sort using MAX/MIN/zero. We sort in that order as the
31
+++ b/target/arm/mve.decode
52
- * timer counts down to zero. */
32
@@ -XXX,XX +XXX,XX @@
53
- uint64_t seq[] = {
33
# VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
54
- calculate_time(t, MAX(t->match[0], t->match[1])),
34
%size_28 28:1 !function=plus_1
55
- calculate_time(t, MIN(t->match[0], t->match[1])),
35
56
- calculate_time(t, 0),
36
+# 1imm format immediate
57
- };
37
+%imm_28_16_0 28:1 16:3 0:4
58
- uint64_t reload_ns;
38
+
59
- uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
39
&vldr_vstr rn qd imm p a w size l u
60
+ /*
40
&1op qd qm size
61
+ * We don't know the relationship between the values in the match
41
&2op qd qm qn size
62
+ * registers, so sort using MAX/MIN/zero. We sort in that order as
42
&2scalar qd qn rm size
63
+ * the timer counts down to zero.
43
+&1imm qd imm cmode op
64
+ */
44
65
45
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
66
- if (now < seq[0]) {
46
# Note that both Rn and Qd are 3 bits only (no D bit)
67
- next = seq[0];
47
@@ -XXX,XX +XXX,XX @@
68
- } else if (now < seq[1]) {
48
@2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0
69
- next = seq[1];
49
@2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \
70
- } else if (now < seq[2]) {
50
size=%size_28
71
- next = seq[2];
51
+@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0
72
- } else if (t->reload) {
52
73
- reload_ns = muldiv64(t->reload, NANOSECONDS_PER_SECOND, rate);
53
# The _rev suffix indicates that Vn and Vm are reversed. This is
74
- t->start = now - ((now - t->start) % reload_ns);
54
# the case for shifts. In the Arm ARM these insns are documented
75
- } else {
55
@@ -XXX,XX +XXX,XX @@ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd
76
- /* no reload value, return 0 */
56
# Predicate operations
77
- break;
57
%mask_22_13 22:1 13:3
78
- }
58
VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
79
+ next = calculate_time(t, MAX(t->match[0], t->match[1]));
59
+
80
+ if (now < next) {
60
+# Logical immediate operations (1 reg and modified-immediate)
81
+ return next;
61
+
82
}
62
+# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but
83
63
+# not in a way we can conveniently represent in decodetree without
84
- return next;
64
+# a lot of repetition:
85
+ next = calculate_time(t, MIN(t->match[0], t->match[1]));
65
+# VORR: op=0, (cmode & 1) && cmode < 12
86
+ if (now < next) {
66
+# VBIC: op=1, (cmode & 1) && cmode < 12
87
+ return next;
67
+# VMOV: everything else
68
+# So we have a single decode line and check the cmode/op in the
69
+# trans function.
70
+Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
71
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/mve_helper.c
74
+++ b/target/arm/mve_helper.c
75
@@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG)
76
DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
77
DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
78
79
+/*
80
+ * 1 operand immediates: Vda is destination and possibly also one source.
81
+ * All these insns work at 64-bit widths.
82
+ */
83
+#define DO_1OP_IMM(OP, FN) \
84
+ void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \
85
+ { \
86
+ uint64_t *da = vda; \
87
+ uint16_t mask = mve_element_mask(env); \
88
+ unsigned e; \
89
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
90
+ mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \
91
+ } \
92
+ mve_advance_vpt(env); \
88
+ }
93
+ }
89
+
94
+
90
+ next = calculate_time(t, 0);
95
+#define DO_MOVI(N, I) (I)
91
+ if (now < next) {
96
+#define DO_ANDI(N, I) ((N) & (I))
92
+ return next;
97
+#define DO_ORRI(N, I) ((N) | (I))
98
+
99
+DO_1OP_IMM(vmovi, DO_MOVI)
100
+DO_1OP_IMM(vandi, DO_ANDI)
101
+DO_1OP_IMM(vorri, DO_ORRI)
102
+
103
#define DO_2OP(OP, ESIZE, TYPE, FN) \
104
void HELPER(glue(mve_, OP))(CPUARMState *env, \
105
void *vd, void *vn, void *vm) \
106
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/translate-mve.c
109
+++ b/target/arm/translate-mve.c
110
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
111
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
112
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
113
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
114
+typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
115
116
/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
117
static inline long mve_qreg_offset(unsigned reg)
118
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
119
mve_update_eci(s);
120
return true;
121
}
122
+
123
+static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
124
+{
125
+ TCGv_ptr qd;
126
+ uint64_t imm;
127
+
128
+ if (!dc_isar_feature(aa32_mve, s) ||
129
+ !mve_check_qreg_bank(s, a->qd) ||
130
+ !fn) {
131
+ return false;
132
+ }
133
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
134
+ return true;
93
+ }
135
+ }
94
+
136
+
95
+ /* We've missed all deadlines, fire interrupt and try again */
137
+ imm = asimd_imm_const(a->imm, a->cmode, a->op);
96
+ timer_del(&t->timer);
97
+
138
+
98
+ if (timer_overflow_interrupt(t)) {
139
+ qd = mve_qreg_ptr(a->qd);
99
+ t->level = !t->level;
140
+ fn(cpu_env, qd, tcg_constant_i64(imm));
100
+ qemu_set_irq(t->irq, t->level);
141
+ tcg_temp_free_ptr(qd);
142
+ mve_update_eci(s);
143
+ return true;
144
+}
145
+
146
+static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
147
+{
148
+ /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
149
+ MVEGenOneOpImmFn *fn;
150
+
151
+ if ((a->cmode & 1) && a->cmode < 12) {
152
+ if (a->op) {
153
+ /*
154
+ * For op=1, the immediate will be inverted by asimd_imm_const(),
155
+ * so the VBIC becomes a logical AND operation.
156
+ */
157
+ fn = gen_helper_mve_vandi;
158
+ } else {
159
+ fn = gen_helper_mve_vorri;
160
+ }
161
+ } else {
162
+ /* There is one unallocated cmode/op combination in this space */
163
+ if (a->cmode == 15 && a->op == 1) {
164
+ return false;
165
+ }
166
+ /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
167
+ fn = gen_helper_mve_vmovi;
101
+ }
168
+ }
102
+
169
+ return do_1imm(s, a, fn);
103
+ t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
170
+}
104
+ return calculate_time(t, MAX(MAX(t->match[0], t->match[1]), 0));
105
}
106
107
static void aspeed_timer_mod(AspeedTimer *t)
108
--
171
--
109
2.20.1
172
2.20.1
110
173
111
174
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/46] i.mx7d: Add no-op/unimplemented APBH DMA module
[PULL 13/24] target/arm: Implement MVE vector shift left by immediate insns
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
2
2
and VQSHLU.
3
Instantiate no-op APBH DMA module. Needed to boot latest Linux kernel.
3
4
4
The size-and-immediate encoding here is the same as Neon, and we
5
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
5
handle it the same way neon-dp.decode does.
6
Cc: Peter Maydell <peter.maydell@linaro.org>
6
7
Cc: Michael S. Tsirkin <mst@redhat.com>
8
Cc: qemu-devel@nongnu.org
9
Cc: qemu-arm@nongnu.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
12
---
10
---
13
include/hw/arm/fsl-imx7.h | 3 +++
11
target/arm/helper-mve.h | 16 +++++++++++
14
hw/arm/fsl-imx7.c | 6 ++++++
12
target/arm/mve.decode | 23 +++++++++++++++
15
2 files changed, 9 insertions(+)
13
target/arm/mve_helper.c | 57 ++++++++++++++++++++++++++++++++++++++
16
14
target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
17
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
15
4 files changed, 147 insertions(+)
18
index XXXXXXX..XXXXXXX 100644
16
19
--- a/include/hw/arm/fsl-imx7.h
17
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
20
+++ b/include/hw/arm/fsl-imx7.h
18
index XXXXXXX..XXXXXXX 100644
21
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
19
--- a/target/arm/helper-mve.h
22
FSL_IMX7_PCIE_REG_SIZE = 16 * 1024,
20
+++ b/target/arm/helper-mve.h
23
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
24
FSL_IMX7_GPR_ADDR = 0x30340000,
22
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
25
+
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
26
+ FSL_IMX7_DMA_APBH_ADDR = 0x33000000,
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
27
+ FSL_IMX7_DMA_APBH_SIZE = 0x2000,
25
+
28
};
26
+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
27
+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
enum FslIMX7IRQs {
28
+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
29
+
32
index XXXXXXX..XXXXXXX 100644
30
+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
--- a/hw/arm/fsl-imx7.c
31
+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
+++ b/hw/arm/fsl-imx7.c
32
+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
33
+
36
*/
34
+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR,
35
+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
FSL_IMX7_LCDIF_SIZE);
36
+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/mve.decode
44
+++ b/target/arm/mve.decode
45
@@ -XXX,XX +XXX,XX @@
46
&2op qd qm qn size
47
&2scalar qd qn rm size
48
&1imm qd imm cmode op
49
+&2shift qd qm shift size
50
51
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
52
# Note that both Rn and Qd are 3 bits only (no D bit)
53
@@ -XXX,XX +XXX,XX @@
54
@2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
55
@2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
56
57
+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
58
+@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
59
+@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
60
+
61
# Vector loads and stores
62
63
# Widening loads and narrowing stores:
64
@@ -XXX,XX +XXX,XX @@ VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
65
# So we have a single decode line and check the cmode/op in the
66
# trans function.
67
Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
68
+
69
+# Shifts by immediate
70
+
71
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
72
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
73
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
74
+
75
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
76
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
77
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
78
+
79
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
80
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
81
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
82
+
83
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
84
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
85
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
86
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/target/arm/mve_helper.c
89
+++ b/target/arm/mve_helper.c
90
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
91
WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
92
#define DO_UQRSHL_OP(N, M, satp) \
93
WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
94
+#define DO_SUQSHL_OP(N, M, satp) \
95
+ WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
96
97
DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
98
DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
99
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
100
DO_VADDV(vaddvub, 1, uint8_t)
101
DO_VADDV(vaddvuh, 2, uint16_t)
102
DO_VADDV(vaddvuw, 4, uint32_t)
103
+
104
+/* Shifts by immediate */
105
+#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
106
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
107
+ void *vm, uint32_t shift) \
108
+ { \
109
+ TYPE *d = vd, *m = vm; \
110
+ uint16_t mask = mve_element_mask(env); \
111
+ unsigned e; \
112
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
113
+ mergemask(&d[H##ESIZE(e)], \
114
+ FN(m[H##ESIZE(e)], shift), mask); \
115
+ } \
116
+ mve_advance_vpt(env); \
117
+ }
118
+
119
+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \
120
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
121
+ void *vm, uint32_t shift) \
122
+ { \
123
+ TYPE *d = vd, *m = vm; \
124
+ uint16_t mask = mve_element_mask(env); \
125
+ unsigned e; \
126
+ bool qc = false; \
127
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
128
+ bool sat = false; \
129
+ mergemask(&d[H##ESIZE(e)], \
130
+ FN(m[H##ESIZE(e)], shift, &sat), mask); \
131
+ qc |= sat & mask & 1; \
132
+ } \
133
+ if (qc) { \
134
+ env->vfp.qc[0] = qc; \
135
+ } \
136
+ mve_advance_vpt(env); \
137
+ }
138
+
139
+/* provide unsigned 2-op shift helpers for all sizes */
140
+#define DO_2SHIFT_U(OP, FN) \
141
+ DO_2SHIFT(OP##b, 1, uint8_t, FN) \
142
+ DO_2SHIFT(OP##h, 2, uint16_t, FN) \
143
+ DO_2SHIFT(OP##w, 4, uint32_t, FN)
144
+
145
+#define DO_2SHIFT_SAT_U(OP, FN) \
146
+ DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
147
+ DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \
148
+ DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
149
+#define DO_2SHIFT_SAT_S(OP, FN) \
150
+ DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \
151
+ DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \
152
+ DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
153
+
154
+DO_2SHIFT_U(vshli_u, DO_VSHLU)
155
+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
156
+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
157
+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
158
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
159
index XXXXXXX..XXXXXXX 100644
160
--- a/target/arm/translate-mve.c
161
+++ b/target/arm/translate-mve.c
162
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
163
typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
164
typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
165
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
166
+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
167
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
168
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
169
typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
170
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
171
}
172
return do_1imm(s, a, fn);
173
}
174
+
175
+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
176
+ bool negateshift)
177
+{
178
+ TCGv_ptr qd, qm;
179
+ int shift = a->shift;
180
+
181
+ if (!dc_isar_feature(aa32_mve, s) ||
182
+ !mve_check_qreg_bank(s, a->qd | a->qm) ||
183
+ !fn) {
184
+ return false;
185
+ }
186
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
187
+ return true;
188
+ }
39
+
189
+
40
+ /*
190
+ /*
41
+ * DMA APBH
191
+ * When we handle a right shift insn using a left-shift helper
192
+ * which permits a negative shift count to indicate a right-shift,
193
+ * we must negate the shift count.
42
+ */
194
+ */
43
+ create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR,
195
+ if (negateshift) {
44
+ FSL_IMX7_DMA_APBH_SIZE);
196
+ shift = -shift;
45
}
197
+ }
46
198
+
47
static void fsl_imx7_class_init(ObjectClass *oc, void *data)
199
+ qd = mve_qreg_ptr(a->qd);
200
+ qm = mve_qreg_ptr(a->qm);
201
+ fn(cpu_env, qd, qm, tcg_constant_i32(shift));
202
+ tcg_temp_free_ptr(qd);
203
+ tcg_temp_free_ptr(qm);
204
+ mve_update_eci(s);
205
+ return true;
206
+}
207
+
208
+#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \
209
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
210
+ { \
211
+ static MVEGenTwoOpShiftFn * const fns[] = { \
212
+ gen_helper_mve_##FN##b, \
213
+ gen_helper_mve_##FN##h, \
214
+ gen_helper_mve_##FN##w, \
215
+ NULL, \
216
+ }; \
217
+ return do_2shift(s, a, fns[a->size], NEGATESHIFT); \
218
+ }
219
+
220
+DO_2SHIFT(VSHLI, vshli_u, false)
221
+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
222
+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
223
+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
48
--
224
--
49
2.20.1
225
2.20.1
50
226
51
227
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/46] i.mx7d: Add no-op/unimplemented PCIE PHY IP block
Deleted patch
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
2
1
3
Add no-op/unimplemented PCIE PHY IP block. Needed by new kernels to
4
use PCIE.
5
6
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
7
Cc: Peter Maydell <peter.maydell@linaro.org>
8
Cc: Michael S. Tsirkin <mst@redhat.com>
9
Cc: qemu-devel@nongnu.org
10
Cc: qemu-arm@nongnu.org
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
include/hw/arm/fsl-imx7.h | 3 +++
15
hw/arm/fsl-imx7.c | 5 +++++
16
2 files changed, 8 insertions(+)
17
18
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/fsl-imx7.h
21
+++ b/include/hw/arm/fsl-imx7.h
22
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
23
FSL_IMX7_ADC2_ADDR = 0x30620000,
24
FSL_IMX7_ADCn_SIZE = 0x1000,
25
26
+ FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000,
27
+ FSL_IMX7_PCIE_PHY_SIZE = 0x10000,
28
+
29
FSL_IMX7_GPC_ADDR = 0x303A0000,
30
31
FSL_IMX7_I2C1_ADDR = 0x30A20000,
32
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/fsl-imx7.c
35
+++ b/hw/arm/fsl-imx7.c
36
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
37
*/
38
create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR,
39
FSL_IMX7_DMA_APBH_SIZE);
40
+ /*
41
+ * PCIe PHY
42
+ */
43
+ create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
44
+ FSL_IMX7_PCIE_PHY_SIZE);
45
}
46
47
static void fsl_imx7_class_init(ObjectClass *oc, void *data)
48
--
49
2.20.1
50
51
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/46] pci: designware: Update MSI mapping unconditionally
Deleted patch
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
2
1
3
Expression to calculate update_msi_mapping in code handling writes to
4
DESIGNWARE_PCIE_MSI_INTR0_ENABLE is missing an ! operator and should
5
be:
6
7
!!root->msi.intr[0].enable ^ !!val;
8
9
so that MSI mapping is updated when enabled transitions from either
10
"none" -> "any" or "any" -> "none". Since that register shouldn't be
11
written to very often, change the code to update MSI mapping
12
unconditionally instead of trying to fix the update_msi_mapping logic.
13
14
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
15
Cc: Peter Maydell <peter.maydell@linaro.org>
16
Cc: Michael S. Tsirkin <mst@redhat.com>
17
Cc: qemu-devel@nongnu.org
18
Cc: qemu-arm@nongnu.org
19
Acked-by: Michael S. Tsirkin <mst@redhat.com>
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
hw/pci-host/designware.c | 10 ++--------
24
1 file changed, 2 insertions(+), 8 deletions(-)
25
26
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/pci-host/designware.c
29
+++ b/hw/pci-host/designware.c
30
@@ -XXX,XX +XXX,XX @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
31
root->msi.base |= (uint64_t)val << 32;
32
break;
33
34
- case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: {
35
- const bool update_msi_mapping = !root->msi.intr[0].enable ^ !!val;
36
-
37
+ case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
38
root->msi.intr[0].enable = val;
39
-
40
- if (update_msi_mapping) {
41
- designware_pcie_root_update_msi_mapping(root);
42
- }
43
+ designware_pcie_root_update_msi_mapping(root);
44
break;
45
- }
46
47
case DESIGNWARE_PCIE_MSI_INTR0_MASK:
48
root->msi.intr[0].mask = val;
49
--
50
2.20.1
51
52
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/46] pci: designware: Update MSI mapping when MSI address changes
Deleted patch
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
2
1
3
MSI mapping needs to be update when MSI address changes, so add the
4
code to do so.
5
6
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
7
Cc: Peter Maydell <peter.maydell@linaro.org>
8
Cc: Michael S. Tsirkin <mst@redhat.com>
9
Cc: qemu-devel@nongnu.org
10
Cc: qemu-arm@nongnu.org
11
Acked-by: Michael S. Tsirkin <mst@redhat.com>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/pci-host/designware.c | 2 ++
16
1 file changed, 2 insertions(+)
17
18
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/pci-host/designware.c
21
+++ b/hw/pci-host/designware.c
22
@@ -XXX,XX +XXX,XX @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
23
case DESIGNWARE_PCIE_MSI_ADDR_LO:
24
root->msi.base &= 0xFFFFFFFF00000000ULL;
25
root->msi.base |= val;
26
+ designware_pcie_root_update_msi_mapping(root);
27
break;
28
29
case DESIGNWARE_PCIE_MSI_ADDR_HI:
30
root->msi.base &= 0x00000000FFFFFFFFULL;
31
root->msi.base |= (uint64_t)val << 32;
32
+ designware_pcie_root_update_msi_mapping(root);
33
break;
34
35
case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
36
--
37
2.20.1
38
39
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/46] aspeed: add a per SoC mapping for the interrupt space
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
This will simplify the definition of new SoCs, like the AST2600 which
4
should use a different CPU and a different IRQ number layout.
5
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Joel Stanley <joel@jms.id.au>
9
Message-id: 20190618165311.27066-2-clg@kaod.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/arm/aspeed_soc.h | 36 +++++++++++++++++++++++
13
hw/arm/aspeed_soc.c | 57 +++++++++++++++++++++++++++++++------
14
2 files changed, 85 insertions(+), 8 deletions(-)
15
16
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/aspeed_soc.h
19
+++ b/include/hw/arm/aspeed_soc.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCInfo {
21
const char *fmc_typename;
22
const char **spi_typename;
23
int wdts_num;
24
+ const int *irqmap;
25
} AspeedSoCInfo;
26
27
typedef struct AspeedSoCClass {
28
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCClass {
29
#define ASPEED_SOC_GET_CLASS(obj) \
30
OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
31
32
+enum {
33
+ ASPEED_IOMEM,
34
+ ASPEED_UART1,
35
+ ASPEED_UART2,
36
+ ASPEED_UART3,
37
+ ASPEED_UART4,
38
+ ASPEED_UART5,
39
+ ASPEED_VUART,
40
+ ASPEED_FMC,
41
+ ASPEED_SPI1,
42
+ ASPEED_SPI2,
43
+ ASPEED_VIC,
44
+ ASPEED_SDMC,
45
+ ASPEED_SCU,
46
+ ASPEED_ADC,
47
+ ASPEED_SRAM,
48
+ ASPEED_GPIO,
49
+ ASPEED_RTC,
50
+ ASPEED_TIMER1,
51
+ ASPEED_TIMER2,
52
+ ASPEED_TIMER3,
53
+ ASPEED_TIMER4,
54
+ ASPEED_TIMER5,
55
+ ASPEED_TIMER6,
56
+ ASPEED_TIMER7,
57
+ ASPEED_TIMER8,
58
+ ASPEED_WDT,
59
+ ASPEED_PWM,
60
+ ASPEED_LPC,
61
+ ASPEED_IBT,
62
+ ASPEED_I2C,
63
+ ASPEED_ETH1,
64
+ ASPEED_ETH2,
65
+};
66
+
67
#endif /* ASPEED_SOC_H */
68
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/arm/aspeed_soc.c
71
+++ b/hw/arm/aspeed_soc.c
72
@@ -XXX,XX +XXX,XX @@
73
#define ASPEED_SOC_ETH1_BASE 0x1E660000
74
#define ASPEED_SOC_ETH2_BASE 0x1E680000
75
76
-static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
77
-static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
78
+static const int aspeed_soc_ast2400_irqmap[] = {
79
+ [ASPEED_UART1] = 9,
80
+ [ASPEED_UART2] = 32,
81
+ [ASPEED_UART3] = 33,
82
+ [ASPEED_UART4] = 34,
83
+ [ASPEED_UART5] = 10,
84
+ [ASPEED_VUART] = 8,
85
+ [ASPEED_FMC] = 19,
86
+ [ASPEED_SDMC] = 0,
87
+ [ASPEED_SCU] = 21,
88
+ [ASPEED_ADC] = 31,
89
+ [ASPEED_GPIO] = 20,
90
+ [ASPEED_RTC] = 22,
91
+ [ASPEED_TIMER1] = 16,
92
+ [ASPEED_TIMER2] = 17,
93
+ [ASPEED_TIMER3] = 18,
94
+ [ASPEED_TIMER4] = 35,
95
+ [ASPEED_TIMER5] = 36,
96
+ [ASPEED_TIMER6] = 37,
97
+ [ASPEED_TIMER7] = 38,
98
+ [ASPEED_TIMER8] = 39,
99
+ [ASPEED_WDT] = 27,
100
+ [ASPEED_PWM] = 28,
101
+ [ASPEED_LPC] = 8,
102
+ [ASPEED_IBT] = 8, /* LPC */
103
+ [ASPEED_I2C] = 12,
104
+ [ASPEED_ETH1] = 2,
105
+ [ASPEED_ETH2] = 3,
106
+};
107
108
#define AST2400_SDRAM_BASE 0x40000000
109
#define AST2500_SDRAM_BASE 0x80000000
110
111
+/* AST2500 uses the same IRQs as the AST2400 */
112
+#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
113
+
114
static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE };
115
static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
116
117
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
118
.fmc_typename = "aspeed.smc.fmc",
119
.spi_typename = aspeed_soc_ast2400_typenames,
120
.wdts_num = 2,
121
+ .irqmap = aspeed_soc_ast2400_irqmap,
122
}, {
123
.name = "ast2400-a1",
124
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
125
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
126
.fmc_typename = "aspeed.smc.fmc",
127
.spi_typename = aspeed_soc_ast2400_typenames,
128
.wdts_num = 2,
129
+ .irqmap = aspeed_soc_ast2400_irqmap,
130
}, {
131
.name = "ast2400",
132
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
133
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
134
.fmc_typename = "aspeed.smc.fmc",
135
.spi_typename = aspeed_soc_ast2400_typenames,
136
.wdts_num = 2,
137
+ .irqmap = aspeed_soc_ast2400_irqmap,
138
}, {
139
.name = "ast2500-a1",
140
.cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
141
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
142
.fmc_typename = "aspeed.smc.ast2500-fmc",
143
.spi_typename = aspeed_soc_ast2500_typenames,
144
.wdts_num = 3,
145
+ .irqmap = aspeed_soc_ast2500_irqmap,
146
},
147
};
148
149
+static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
150
+{
151
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
152
+
153
+ return qdev_get_gpio_in(DEVICE(&s->vic), sc->info->irqmap[ctrl]);
154
+}
155
+
156
static void aspeed_soc_init(Object *obj)
157
{
158
AspeedSoCState *s = ASPEED_SOC(obj);
159
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
160
return;
161
}
162
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
163
- for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
164
- qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
165
+ for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
166
+ qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
167
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
168
}
169
170
/* UART - attach an 8250 to the IO space as our UART5 */
171
if (serial_hd(0)) {
172
- qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
173
+ qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
174
serial_mm_init(get_system_memory(),
175
ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2,
176
uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
177
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
178
}
179
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
180
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
181
- qdev_get_gpio_in(DEVICE(&s->vic), 12));
182
+ aspeed_soc_get_irq(s, ASPEED_I2C));
183
184
/* FMC, The number of CS is set at the board level */
185
object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
186
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
187
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
188
s->fmc.ctrl->flash_window_base);
189
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
190
- qdev_get_gpio_in(DEVICE(&s->vic), 19));
191
+ aspeed_soc_get_irq(s, ASPEED_FMC));
192
193
/* SPI */
194
for (i = 0; i < sc->info->spis_num; i++) {
195
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
196
}
197
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, ASPEED_SOC_ETH1_BASE);
198
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
199
- qdev_get_gpio_in(DEVICE(&s->vic), 2));
200
+ aspeed_soc_get_irq(s, ASPEED_ETH1));
201
}
202
203
static void aspeed_soc_class_init(ObjectClass *oc, void *data)
204
--
205
2.20.1
206
207
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/46] aspeed: add a per SoC mapping for the memory space
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
This will simplify the definition of new SoCs, like the AST2600 which
4
should use a slightly different address space and have a different set
5
of controllers.
6
7
Signed-off-by: Cédric Le Goater <clg@kaod.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Joel Stanley <joel@jms.id.au>
10
Message-id: 20190618165311.27066-3-clg@kaod.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/hw/arm/aspeed_soc.h | 4 +-
14
hw/arm/aspeed.c | 8 +--
15
hw/arm/aspeed_soc.c | 117 ++++++++++++++++++++++--------------
16
3 files changed, 78 insertions(+), 51 deletions(-)
17
18
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/aspeed_soc.h
21
+++ b/include/hw/arm/aspeed_soc.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCInfo {
23
const char *name;
24
const char *cpu_type;
25
uint32_t silicon_rev;
26
- hwaddr sdram_base;
27
uint64_t sram_size;
28
int spis_num;
29
- const hwaddr *spi_bases;
30
const char *fmc_typename;
31
const char **spi_typename;
32
int wdts_num;
33
const int *irqmap;
34
+ const hwaddr *memmap;
35
} AspeedSoCInfo;
36
37
typedef struct AspeedSoCClass {
38
@@ -XXX,XX +XXX,XX @@ enum {
39
ASPEED_I2C,
40
ASPEED_ETH1,
41
ASPEED_ETH2,
42
+ ASPEED_SDRAM,
43
};
44
45
#endif /* ASPEED_SOC_H */
46
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/aspeed.c
49
+++ b/hw/arm/aspeed.c
50
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
51
&error_abort);
52
53
memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
54
- memory_region_add_subregion(get_system_memory(), sc->info->sdram_base,
55
- &bmc->ram);
56
+ memory_region_add_subregion(get_system_memory(),
57
+ sc->info->memmap[ASPEED_SDRAM], &bmc->ram);
58
object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
59
&error_abort);
60
61
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
62
memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
63
"max_ram", max_ram_size - ram_size);
64
memory_region_add_subregion(get_system_memory(),
65
- sc->info->sdram_base + ram_size,
66
+ sc->info->memmap[ASPEED_SDRAM] + ram_size,
67
&bmc->max_ram);
68
69
aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);
70
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
71
aspeed_board_binfo.initrd_filename = machine->initrd_filename;
72
aspeed_board_binfo.kernel_cmdline = machine->kernel_cmdline;
73
aspeed_board_binfo.ram_size = ram_size;
74
- aspeed_board_binfo.loader_start = sc->info->sdram_base;
75
+ aspeed_board_binfo.loader_start = sc->info->memmap[ASPEED_SDRAM];
76
77
if (cfg->i2c_init) {
78
cfg->i2c_init(bmc);
79
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/arm/aspeed_soc.c
82
+++ b/hw/arm/aspeed_soc.c
83
@@ -XXX,XX +XXX,XX @@
84
#include "hw/i2c/aspeed_i2c.h"
85
#include "net/net.h"
86
87
-#define ASPEED_SOC_UART_5_BASE 0x00184000
88
#define ASPEED_SOC_IOMEM_SIZE 0x00200000
89
-#define ASPEED_SOC_IOMEM_BASE 0x1E600000
90
-#define ASPEED_SOC_FMC_BASE 0x1E620000
91
-#define ASPEED_SOC_SPI_BASE 0x1E630000
92
-#define ASPEED_SOC_SPI2_BASE 0x1E631000
93
-#define ASPEED_SOC_VIC_BASE 0x1E6C0000
94
-#define ASPEED_SOC_SDMC_BASE 0x1E6E0000
95
-#define ASPEED_SOC_SCU_BASE 0x1E6E2000
96
-#define ASPEED_SOC_SRAM_BASE 0x1E720000
97
-#define ASPEED_SOC_TIMER_BASE 0x1E782000
98
-#define ASPEED_SOC_WDT_BASE 0x1E785000
99
-#define ASPEED_SOC_I2C_BASE 0x1E78A000
100
-#define ASPEED_SOC_ETH1_BASE 0x1E660000
101
-#define ASPEED_SOC_ETH2_BASE 0x1E680000
102
+
103
+static const hwaddr aspeed_soc_ast2400_memmap[] = {
104
+ [ASPEED_IOMEM] = 0x1E600000,
105
+ [ASPEED_FMC] = 0x1E620000,
106
+ [ASPEED_SPI1] = 0x1E630000,
107
+ [ASPEED_VIC] = 0x1E6C0000,
108
+ [ASPEED_SDMC] = 0x1E6E0000,
109
+ [ASPEED_SCU] = 0x1E6E2000,
110
+ [ASPEED_ADC] = 0x1E6E9000,
111
+ [ASPEED_SRAM] = 0x1E720000,
112
+ [ASPEED_GPIO] = 0x1E780000,
113
+ [ASPEED_RTC] = 0x1E781000,
114
+ [ASPEED_TIMER1] = 0x1E782000,
115
+ [ASPEED_WDT] = 0x1E785000,
116
+ [ASPEED_PWM] = 0x1E786000,
117
+ [ASPEED_LPC] = 0x1E789000,
118
+ [ASPEED_IBT] = 0x1E789140,
119
+ [ASPEED_I2C] = 0x1E78A000,
120
+ [ASPEED_ETH1] = 0x1E660000,
121
+ [ASPEED_ETH2] = 0x1E680000,
122
+ [ASPEED_UART1] = 0x1E783000,
123
+ [ASPEED_UART5] = 0x1E784000,
124
+ [ASPEED_VUART] = 0x1E787000,
125
+ [ASPEED_SDRAM] = 0x40000000,
126
+};
127
+
128
+static const hwaddr aspeed_soc_ast2500_memmap[] = {
129
+ [ASPEED_IOMEM] = 0x1E600000,
130
+ [ASPEED_FMC] = 0x1E620000,
131
+ [ASPEED_SPI1] = 0x1E630000,
132
+ [ASPEED_SPI2] = 0x1E631000,
133
+ [ASPEED_VIC] = 0x1E6C0000,
134
+ [ASPEED_SDMC] = 0x1E6E0000,
135
+ [ASPEED_SCU] = 0x1E6E2000,
136
+ [ASPEED_ADC] = 0x1E6E9000,
137
+ [ASPEED_SRAM] = 0x1E720000,
138
+ [ASPEED_GPIO] = 0x1E780000,
139
+ [ASPEED_RTC] = 0x1E781000,
140
+ [ASPEED_TIMER1] = 0x1E782000,
141
+ [ASPEED_WDT] = 0x1E785000,
142
+ [ASPEED_PWM] = 0x1E786000,
143
+ [ASPEED_LPC] = 0x1E789000,
144
+ [ASPEED_IBT] = 0x1E789140,
145
+ [ASPEED_I2C] = 0x1E78A000,
146
+ [ASPEED_ETH1] = 0x1E660000,
147
+ [ASPEED_ETH2] = 0x1E680000,
148
+ [ASPEED_UART1] = 0x1E783000,
149
+ [ASPEED_UART5] = 0x1E784000,
150
+ [ASPEED_VUART] = 0x1E787000,
151
+ [ASPEED_SDRAM] = 0x80000000,
152
+};
153
154
static const int aspeed_soc_ast2400_irqmap[] = {
155
[ASPEED_UART1] = 9,
156
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2400_irqmap[] = {
157
[ASPEED_ETH2] = 3,
158
};
159
160
-#define AST2400_SDRAM_BASE 0x40000000
161
-#define AST2500_SDRAM_BASE 0x80000000
162
-
163
-/* AST2500 uses the same IRQs as the AST2400 */
164
#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
165
166
-static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE };
167
static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
168
-
169
-static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE,
170
- ASPEED_SOC_SPI2_BASE};
171
static const char *aspeed_soc_ast2500_typenames[] = {
172
"aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
173
174
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
175
.name = "ast2400-a0",
176
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
177
.silicon_rev = AST2400_A0_SILICON_REV,
178
- .sdram_base = AST2400_SDRAM_BASE,
179
.sram_size = 0x8000,
180
.spis_num = 1,
181
- .spi_bases = aspeed_soc_ast2400_spi_bases,
182
.fmc_typename = "aspeed.smc.fmc",
183
.spi_typename = aspeed_soc_ast2400_typenames,
184
.wdts_num = 2,
185
.irqmap = aspeed_soc_ast2400_irqmap,
186
+ .memmap = aspeed_soc_ast2400_memmap,
187
}, {
188
.name = "ast2400-a1",
189
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
190
.silicon_rev = AST2400_A1_SILICON_REV,
191
- .sdram_base = AST2400_SDRAM_BASE,
192
.sram_size = 0x8000,
193
.spis_num = 1,
194
- .spi_bases = aspeed_soc_ast2400_spi_bases,
195
.fmc_typename = "aspeed.smc.fmc",
196
.spi_typename = aspeed_soc_ast2400_typenames,
197
.wdts_num = 2,
198
.irqmap = aspeed_soc_ast2400_irqmap,
199
+ .memmap = aspeed_soc_ast2400_memmap,
200
}, {
201
.name = "ast2400",
202
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
203
.silicon_rev = AST2400_A0_SILICON_REV,
204
- .sdram_base = AST2400_SDRAM_BASE,
205
.sram_size = 0x8000,
206
.spis_num = 1,
207
- .spi_bases = aspeed_soc_ast2400_spi_bases,
208
.fmc_typename = "aspeed.smc.fmc",
209
.spi_typename = aspeed_soc_ast2400_typenames,
210
.wdts_num = 2,
211
.irqmap = aspeed_soc_ast2400_irqmap,
212
+ .memmap = aspeed_soc_ast2400_memmap,
213
}, {
214
.name = "ast2500-a1",
215
.cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
216
.silicon_rev = AST2500_A1_SILICON_REV,
217
- .sdram_base = AST2500_SDRAM_BASE,
218
.sram_size = 0x9000,
219
.spis_num = 2,
220
- .spi_bases = aspeed_soc_ast2500_spi_bases,
221
.fmc_typename = "aspeed.smc.ast2500-fmc",
222
.spi_typename = aspeed_soc_ast2500_typenames,
223
.wdts_num = 3,
224
.irqmap = aspeed_soc_ast2500_irqmap,
225
+ .memmap = aspeed_soc_ast2500_memmap,
226
},
227
};
228
229
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
230
Error *err = NULL, *local_err = NULL;
231
232
/* IO space */
233
- create_unimplemented_device("aspeed_soc.io",
234
- ASPEED_SOC_IOMEM_BASE, ASPEED_SOC_IOMEM_SIZE);
235
+ create_unimplemented_device("aspeed_soc.io", sc->info->memmap[ASPEED_IOMEM],
236
+ ASPEED_SOC_IOMEM_SIZE);
237
238
/* CPU */
239
object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
240
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
241
error_propagate(errp, err);
242
return;
243
}
244
- memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE,
245
- &s->sram);
246
+ memory_region_add_subregion(get_system_memory(),
247
+ sc->info->memmap[ASPEED_SRAM], &s->sram);
248
249
/* SCU */
250
object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
251
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
252
error_propagate(errp, err);
253
return;
254
}
255
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);
256
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->info->memmap[ASPEED_SCU]);
257
258
/* VIC */
259
object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
260
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
261
error_propagate(errp, err);
262
return;
263
}
264
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE);
265
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->info->memmap[ASPEED_VIC]);
266
sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
267
qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
268
sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
269
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
270
error_propagate(errp, err);
271
return;
272
}
273
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
274
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
275
+ sc->info->memmap[ASPEED_TIMER1]);
276
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
277
qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
278
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
279
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
280
/* UART - attach an 8250 to the IO space as our UART5 */
281
if (serial_hd(0)) {
282
qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
283
- serial_mm_init(get_system_memory(),
284
- ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2,
285
+ serial_mm_init(get_system_memory(), sc->info->memmap[ASPEED_UART5], 2,
286
uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
287
}
288
289
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
290
error_propagate(errp, err);
291
return;
292
}
293
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
294
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->info->memmap[ASPEED_I2C]);
295
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
296
aspeed_soc_get_irq(s, ASPEED_I2C));
297
298
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
299
error_propagate(errp, err);
300
return;
301
}
302
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE);
303
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->info->memmap[ASPEED_FMC]);
304
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
305
s->fmc.ctrl->flash_window_base);
306
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
307
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
308
error_propagate(errp, err);
309
return;
310
}
311
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, sc->info->spi_bases[i]);
312
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
313
+ sc->info->memmap[ASPEED_SPI1 + i]);
314
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
315
s->spi[i].ctrl->flash_window_base);
316
}
317
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
318
error_propagate(errp, err);
319
return;
320
}
321
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
322
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->info->memmap[ASPEED_SDMC]);
323
324
/* Watch dog */
325
for (i = 0; i < sc->info->wdts_num; i++) {
326
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
327
return;
328
}
329
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
330
- ASPEED_SOC_WDT_BASE + i * 0x20);
331
+ sc->info->memmap[ASPEED_WDT] + i * 0x20);
332
}
333
334
/* Net */
335
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
336
error_propagate(errp, err);
337
return;
338
}
339
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, ASPEED_SOC_ETH1_BASE);
340
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0,
341
+ sc->info->memmap[ASPEED_ETH1]);
342
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
343
aspeed_soc_get_irq(s, ASPEED_ETH1));
344
}
345
--
346
2.20.1
347
348
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/46] aspeed/timer: Fix match calculations
[PULL 14/24] target/arm: Implement MVE vector shift right by immediate insns
1
From: Andrew Jeffery <andrew@aj.id.au>
1
Implement the MVE vector shift right by immediate insns VSHRI and
2
VRSHRI. As with Neon, we implement these by using helper functions
3
which perform left shifts but allow negative shift counts to indicate
4
right shifts.
2
5
3
If the match value exceeds reload then we don't want to include it in
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
calculations for the next event.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
9
---
10
target/arm/helper-mve.h | 12 ++++++++++++
11
target/arm/translate.h | 20 ++++++++++++++++++++
12
target/arm/mve.decode | 28 ++++++++++++++++++++++++++++
13
target/arm/mve_helper.c | 7 +++++++
14
target/arm/translate-mve.c | 5 +++++
15
target/arm/translate-neon.c | 18 ------------------
16
6 files changed, 72 insertions(+), 18 deletions(-)
5
17
6
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
7
Signed-off-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: 20190618165311.27066-10-clg@kaod.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/timer/aspeed_timer.c | 13 ++++++++++---
12
1 file changed, 10 insertions(+), 3 deletions(-)
13
14
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
15
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/timer/aspeed_timer.c
20
--- a/target/arm/helper-mve.h
17
+++ b/hw/timer/aspeed_timer.c
21
+++ b/target/arm/helper-mve.h
18
@@ -XXX,XX +XXX,XX @@ static inline uint64_t calculate_time(struct AspeedTimer *t, uint32_t ticks)
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
19
return t->start + delta_ns;
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
25
26
+DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+
30
DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+
42
+DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
45
diff --git a/target/arm/translate.h b/target/arm/translate.h
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/translate.h
48
+++ b/target/arm/translate.h
49
@@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x)
50
return x * 2 + 1;
20
}
51
}
21
52
22
+static inline uint32_t calculate_match(struct AspeedTimer *t, int i)
53
+static inline int rsub_64(DisasContext *s, int x)
23
+{
54
+{
24
+ return t->match[i] < t->reload ? t->match[i] : 0;
55
+ return 64 - x;
25
+}
56
+}
26
+
57
+
27
static uint64_t calculate_next(struct AspeedTimer *t)
58
+static inline int rsub_32(DisasContext *s, int x)
59
+{
60
+ return 32 - x;
61
+}
62
+
63
+static inline int rsub_16(DisasContext *s, int x)
64
+{
65
+ return 16 - x;
66
+}
67
+
68
+static inline int rsub_8(DisasContext *s, int x)
69
+{
70
+ return 8 - x;
71
+}
72
+
73
static inline int arm_dc_feature(DisasContext *dc, int feature)
28
{
74
{
29
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
75
return (dc->features & (1ULL << feature)) != 0;
30
@@ -XXX,XX +XXX,XX @@ static uint64_t calculate_next(struct AspeedTimer *t)
76
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
31
* the timer counts down to zero.
77
index XXXXXXX..XXXXXXX 100644
32
*/
78
--- a/target/arm/mve.decode
33
79
+++ b/target/arm/mve.decode
34
- next = calculate_time(t, MAX(t->match[0], t->match[1]));
80
@@ -XXX,XX +XXX,XX @@
35
+ next = calculate_time(t, MAX(calculate_match(t, 0), calculate_match(t, 1)));
81
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
36
if (now < next) {
82
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
37
return next;
83
38
}
84
+# Right shifts are encoded as N - shift, where N is the element size in bits.
39
85
+%rshift_i5 16:5 !function=rsub_32
40
- next = calculate_time(t, MIN(t->match[0], t->match[1]));
86
+%rshift_i4 16:4 !function=rsub_16
41
+ next = calculate_time(t, MIN(calculate_match(t, 0), calculate_match(t, 1)));
87
+%rshift_i3 16:3 !function=rsub_8
42
if (now < next) {
43
return next;
44
}
45
@@ -XXX,XX +XXX,XX @@ static uint64_t calculate_next(struct AspeedTimer *t)
46
qemu_set_irq(t->irq, t->level);
47
}
48
49
+ next = MAX(MAX(calculate_match(t, 0), calculate_match(t, 1)), 0);
50
t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
51
- return calculate_time(t, MAX(MAX(t->match[0], t->match[1]), 0));
52
+
88
+
53
+ return calculate_time(t, next);
89
+@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \
90
+ size=0 shift=%rshift_i3
91
+@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \
92
+ size=1 shift=%rshift_i4
93
+@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \
94
+ size=2 shift=%rshift_i5
95
+
96
# Vector loads and stores
97
98
# Widening loads and narrowing stores:
99
@@ -XXX,XX +XXX,XX @@ VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
100
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
101
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
102
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
103
+
104
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
105
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
106
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
107
+
108
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
109
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
110
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
111
+
112
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
113
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
114
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
115
+
116
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
117
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
118
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
119
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/target/arm/mve_helper.c
122
+++ b/target/arm/mve_helper.c
123
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
124
DO_2SHIFT(OP##b, 1, uint8_t, FN) \
125
DO_2SHIFT(OP##h, 2, uint16_t, FN) \
126
DO_2SHIFT(OP##w, 4, uint32_t, FN)
127
+#define DO_2SHIFT_S(OP, FN) \
128
+ DO_2SHIFT(OP##b, 1, int8_t, FN) \
129
+ DO_2SHIFT(OP##h, 2, int16_t, FN) \
130
+ DO_2SHIFT(OP##w, 4, int32_t, FN)
131
132
#define DO_2SHIFT_SAT_U(OP, FN) \
133
DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
134
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
135
DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
136
137
DO_2SHIFT_U(vshli_u, DO_VSHLU)
138
+DO_2SHIFT_S(vshli_s, DO_VSHLS)
139
DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
140
DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
141
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
142
+DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
143
+DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
144
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
145
index XXXXXXX..XXXXXXX 100644
146
--- a/target/arm/translate-mve.c
147
+++ b/target/arm/translate-mve.c
148
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false)
149
DO_2SHIFT(VQSHLI_S, vqshli_s, false)
150
DO_2SHIFT(VQSHLI_U, vqshli_u, false)
151
DO_2SHIFT(VQSHLUI, vqshlui_s, false)
152
+/* These right shifts use a left-shift helper with negated shift count */
153
+DO_2SHIFT(VSHRI_S, vshli_s, true)
154
+DO_2SHIFT(VSHRI_U, vshli_u, true)
155
+DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
+DO_2SHIFT(VRSHRI_U, vrshli_u, true)
157
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
158
index XXXXXXX..XXXXXXX 100644
159
--- a/target/arm/translate-neon.c
160
+++ b/target/arm/translate-neon.c
161
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
162
return x + 1;
54
}
163
}
55
164
56
static void aspeed_timer_mod(AspeedTimer *t)
165
-static inline int rsub_64(DisasContext *s, int x)
166
-{
167
- return 64 - x;
168
-}
169
-
170
-static inline int rsub_32(DisasContext *s, int x)
171
-{
172
- return 32 - x;
173
-}
174
-static inline int rsub_16(DisasContext *s, int x)
175
-{
176
- return 16 - x;
177
-}
178
-static inline int rsub_8(DisasContext *s, int x)
179
-{
180
- return 8 - x;
181
-}
182
-
183
static inline int neon_3same_fp_size(DisasContext *s, int x)
184
{
185
/* Convert 0==fp32, 1==fp16 into a MO_* value */
57
--
186
--
58
2.20.1
187
2.20.1
59
188
60
189
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/46] hw: timer: Add ASPEED RTC device
[PULL 15/24] target/arm: Implement MVE VSHLL
1
From: Joel Stanley <joel@jms.id.au>
1
Implement the MVE VHLL (vector shift left long) insn. This has two
2
encodings: the T1 encoding is the usual shift-by-immediate format,
3
and the T2 encoding is a special case where the shift count is always
4
equal to the element size.
2
5
3
The RTC is modeled to provide time and date functionality. It is
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
initialised at zero to match the hardware.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
9
---
10
target/arm/helper-mve.h | 9 +++++++
11
target/arm/mve.decode | 53 +++++++++++++++++++++++++++++++++++---
12
target/arm/mve_helper.c | 32 +++++++++++++++++++++++
13
target/arm/translate-mve.c | 15 +++++++++++
14
4 files changed, 105 insertions(+), 4 deletions(-)
5
15
6
There is no modelling of the alarm functionality, which includes the IRQ
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
7
line. As there is no guest code to exercise this function that is
8
acceptable for now.
9
10
Signed-off-by: Joel Stanley <joel@jms.id.au>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20190618165311.27066-4-clg@kaod.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/timer/Makefile.objs | 2 +-
16
include/hw/timer/aspeed_rtc.h | 31 ++++++
17
hw/timer/aspeed_rtc.c | 180 ++++++++++++++++++++++++++++++++++
18
hw/timer/trace-events | 4 +
19
4 files changed, 216 insertions(+), 1 deletion(-)
20
create mode 100644 include/hw/timer/aspeed_rtc.h
21
create mode 100644 hw/timer/aspeed_rtc.c
22
23
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
24
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/timer/Makefile.objs
18
--- a/target/arm/helper-mve.h
26
+++ b/hw/timer/Makefile.objs
19
+++ b/target/arm/helper-mve.h
27
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
obj-$(CONFIG_ALLWINNER_A10_PIT) += allwinner-a10-pit.o
21
DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
22
DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
common-obj-$(CONFIG_STM32F2XX_TIMER) += stm32f2xx_timer.o
23
DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
-common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
24
+
32
+common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o aspeed_rtc.o
25
+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
26
+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
27
+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o
28
+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
diff --git a/include/hw/timer/aspeed_rtc.h b/include/hw/timer/aspeed_rtc.h
29
+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
new file mode 100644
30
+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
index XXXXXXX..XXXXXXX
31
+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
--- /dev/null
32
+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+++ b/include/hw/timer/aspeed_rtc.h
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/mve.decode
36
+++ b/target/arm/mve.decode
41
@@ -XXX,XX +XXX,XX @@
37
@@ -XXX,XX +XXX,XX @@
42
+/*
38
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
43
+ * ASPEED Real Time Clock
39
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
44
+ * Joel Stanley <joel@jms.id.au>
40
45
+ *
41
+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
46
+ * Copyright 2019 IBM Corp
42
+@2_shll_h .... .... ... 1 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
47
+ * SPDX-License-Identifier: GPL-2.0-or-later
43
+# VSHLL encoding T2 where shift == esize
48
+ */
44
+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
49
+#ifndef ASPEED_RTC_H
45
+ qd=%qd qm=%qm size=0 shift=8
50
+#define ASPEED_RTC_H
46
+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
47
+ qd=%qd qm=%qm size=1 shift=16
51
+
48
+
52
+#include <stdint.h>
49
# Right shifts are encoded as N - shift, where N is the element size in bits.
53
+
50
%rshift_i5 16:5 !function=rsub_32
54
+#include "hw/hw.h"
51
%rshift_i4 16:4 !function=rsub_16
55
+#include "hw/irq.h"
52
@@ -XXX,XX +XXX,XX @@ VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
56
+#include "hw/sysbus.h"
53
VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
57
+
54
VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
58
+typedef struct AspeedRtcState {
55
59
+ SysBusDevice parent_obj;
56
-VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
60
+
57
-VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
61
+ MemoryRegion iomem;
58
+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
62
+ qemu_irq irq;
59
+# overlaps what would be size=0b11 VMULH/VRMULH
63
+
64
+ uint32_t reg[0x18];
65
+ int offset;
66
+
67
+} AspeedRtcState;
68
+
69
+#define TYPE_ASPEED_RTC "aspeed.rtc"
70
+#define ASPEED_RTC(obj) OBJECT_CHECK(AspeedRtcState, (obj), TYPE_ASPEED_RTC)
71
+
72
+#endif /* ASPEED_RTC_H */
73
diff --git a/hw/timer/aspeed_rtc.c b/hw/timer/aspeed_rtc.c
74
new file mode 100644
75
index XXXXXXX..XXXXXXX
76
--- /dev/null
77
+++ b/hw/timer/aspeed_rtc.c
78
@@ -XXX,XX +XXX,XX @@
79
+/*
80
+ * ASPEED Real Time Clock
81
+ * Joel Stanley <joel@jms.id.au>
82
+ *
83
+ * Copyright 2019 IBM Corp
84
+ * SPDX-License-Identifier: GPL-2.0-or-later
85
+ */
86
+
87
+#include "qemu/osdep.h"
88
+#include "qemu-common.h"
89
+#include "hw/timer/aspeed_rtc.h"
90
+#include "qemu/log.h"
91
+#include "qemu/timer.h"
92
+
93
+#include "trace.h"
94
+
95
+#define COUNTER1 (0x00 / 4)
96
+#define COUNTER2 (0x04 / 4)
97
+#define ALARM (0x08 / 4)
98
+#define CONTROL (0x10 / 4)
99
+#define ALARM_STATUS (0x14 / 4)
100
+
101
+#define RTC_UNLOCKED BIT(1)
102
+#define RTC_ENABLED BIT(0)
103
+
104
+static void aspeed_rtc_calc_offset(AspeedRtcState *rtc)
105
+{
60
+{
106
+ struct tm tm;
61
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
107
+ uint32_t year, cent;
62
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
108
+ uint32_t reg1 = rtc->reg[COUNTER1];
63
109
+ uint32_t reg2 = rtc->reg[COUNTER2];
64
-VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
110
+
65
-VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
111
+ tm.tm_mday = (reg1 >> 24) & 0x1f;
66
+ VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
112
+ tm.tm_hour = (reg1 >> 16) & 0x1f;
113
+ tm.tm_min = (reg1 >> 8) & 0x3f;
114
+ tm.tm_sec = (reg1 >> 0) & 0x3f;
115
+
116
+ cent = (reg2 >> 16) & 0x1f;
117
+ year = (reg2 >> 8) & 0x7f;
118
+ tm.tm_mon = ((reg2 >> 0) & 0x0f) - 1;
119
+ tm.tm_year = year + (cent * 100) - 1900;
120
+
121
+ rtc->offset = qemu_timedate_diff(&tm);
122
+}
67
+}
123
+
68
+
124
+static uint32_t aspeed_rtc_get_counter(AspeedRtcState *rtc, int r)
125
+{
69
+{
126
+ uint32_t year, cent;
70
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
127
+ struct tm now;
71
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
128
+
72
+
129
+ qemu_get_timedate(&now, rtc->offset);
73
+ VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
130
+
131
+ switch (r) {
132
+ case COUNTER1:
133
+ return (now.tm_mday << 24) | (now.tm_hour << 16) |
134
+ (now.tm_min << 8) | now.tm_sec;
135
+ case COUNTER2:
136
+ cent = (now.tm_year + 1900) / 100;
137
+ year = now.tm_year % 100;
138
+ return ((cent & 0x1f) << 16) | ((year & 0x7f) << 8) |
139
+ ((now.tm_mon + 1) & 0xf);
140
+ default:
141
+ g_assert_not_reached();
142
+ }
143
+}
74
+}
144
+
75
+
145
+static uint64_t aspeed_rtc_read(void *opaque, hwaddr addr,
146
+ unsigned size)
147
+{
76
+{
148
+ AspeedRtcState *rtc = opaque;
77
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
149
+ uint64_t val;
78
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
150
+ uint32_t r = addr >> 2;
151
+
79
+
152
+ switch (r) {
80
+ VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
153
+ case COUNTER1:
81
+}
154
+ case COUNTER2:
82
+
155
+ if (rtc->reg[CONTROL] & RTC_ENABLED) {
83
+{
156
+ rtc->reg[r] = aspeed_rtc_get_counter(rtc, r);
84
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
157
+ }
85
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
158
+ /* fall through */
86
+
159
+ case CONTROL:
87
+ VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
160
+ val = rtc->reg[r];
88
+}
161
+ break;
89
162
+ case ALARM:
90
VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
163
+ case ALARM_STATUS:
91
VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
164
+ default:
92
@@ -XXX,XX +XXX,XX @@ VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
165
+ qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx "\n", __func__, addr);
93
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
166
+ return 0;
94
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
95
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
96
+
97
+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
98
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
99
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
100
+
101
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
102
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
103
+
104
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
105
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
106
+
107
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
108
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
109
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
110
index XXXXXXX..XXXXXXX 100644
111
--- a/target/arm/mve_helper.c
112
+++ b/target/arm/mve_helper.c
113
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
114
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
115
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
116
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
117
+
118
+/*
119
+ * Long shifts taking half-sized inputs from top or bottom of the input
120
+ * vector and producing a double-width result. ESIZE, TYPE are for
121
+ * the input, and LESIZE, LTYPE for the output.
122
+ * Unlike the normal shift helpers, we do not handle negative shift counts,
123
+ * because the long shift is strictly left-only.
124
+ */
125
+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \
126
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
127
+ void *vm, uint32_t shift) \
128
+ { \
129
+ LTYPE *d = vd; \
130
+ TYPE *m = vm; \
131
+ uint16_t mask = mve_element_mask(env); \
132
+ unsigned le; \
133
+ assert(shift <= 16); \
134
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
135
+ LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \
136
+ mergemask(&d[H##LESIZE(le)], r, mask); \
137
+ } \
138
+ mve_advance_vpt(env); \
167
+ }
139
+ }
168
+
140
+
169
+ trace_aspeed_rtc_read(addr, val);
141
+#define DO_VSHLL_ALL(OP, TOP) \
142
+ DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \
143
+ DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \
144
+ DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \
145
+ DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \
170
+
146
+
171
+ return val;
147
+DO_VSHLL_ALL(vshllb, false)
172
+}
148
+DO_VSHLL_ALL(vshllt, true)
149
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
150
index XXXXXXX..XXXXXXX 100644
151
--- a/target/arm/translate-mve.c
152
+++ b/target/arm/translate-mve.c
153
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
154
DO_2SHIFT(VSHRI_U, vshli_u, true)
155
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
173
+
157
+
174
+static void aspeed_rtc_write(void *opaque, hwaddr addr,
158
+#define DO_VSHLL(INSN, FN) \
175
+ uint64_t val, unsigned size)
159
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
176
+{
160
+ { \
177
+ AspeedRtcState *rtc = opaque;
161
+ static MVEGenTwoOpShiftFn * const fns[] = { \
178
+ uint32_t r = addr >> 2;
162
+ gen_helper_mve_##FN##b, \
163
+ gen_helper_mve_##FN##h, \
164
+ }; \
165
+ return do_2shift(s, a, fns[a->size], false); \
166
+ }
179
+
167
+
180
+ switch (r) {
168
+DO_VSHLL(VSHLL_BS, vshllbs)
181
+ case COUNTER1:
169
+DO_VSHLL(VSHLL_BU, vshllbu)
182
+ case COUNTER2:
170
+DO_VSHLL(VSHLL_TS, vshllts)
183
+ if (!(rtc->reg[CONTROL] & RTC_UNLOCKED)) {
171
+DO_VSHLL(VSHLL_TU, vshlltu)
184
+ break;
185
+ }
186
+ /* fall through */
187
+ case CONTROL:
188
+ rtc->reg[r] = val;
189
+ aspeed_rtc_calc_offset(rtc);
190
+ break;
191
+ case ALARM:
192
+ case ALARM_STATUS:
193
+ default:
194
+ qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx "\n", __func__, addr);
195
+ break;
196
+ }
197
+ trace_aspeed_rtc_write(addr, val);
198
+}
199
+
200
+static void aspeed_rtc_reset(DeviceState *d)
201
+{
202
+ AspeedRtcState *rtc = ASPEED_RTC(d);
203
+
204
+ rtc->offset = 0;
205
+ memset(rtc->reg, 0, sizeof(rtc->reg));
206
+}
207
+
208
+static const MemoryRegionOps aspeed_rtc_ops = {
209
+ .read = aspeed_rtc_read,
210
+ .write = aspeed_rtc_write,
211
+ .endianness = DEVICE_NATIVE_ENDIAN,
212
+};
213
+
214
+static const VMStateDescription vmstate_aspeed_rtc = {
215
+ .name = TYPE_ASPEED_RTC,
216
+ .version_id = 1,
217
+ .fields = (VMStateField[]) {
218
+ VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18),
219
+ VMSTATE_INT32(offset, AspeedRtcState),
220
+ VMSTATE_INT32(offset, AspeedRtcState),
221
+ VMSTATE_END_OF_LIST()
222
+ }
223
+};
224
+
225
+static void aspeed_rtc_realize(DeviceState *dev, Error **errp)
226
+{
227
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
228
+ AspeedRtcState *s = ASPEED_RTC(dev);
229
+
230
+ sysbus_init_irq(sbd, &s->irq);
231
+
232
+ memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_rtc_ops, s,
233
+ "aspeed-rtc", 0x18ULL);
234
+ sysbus_init_mmio(sbd, &s->iomem);
235
+}
236
+
237
+static void aspeed_rtc_class_init(ObjectClass *klass, void *data)
238
+{
239
+ DeviceClass *dc = DEVICE_CLASS(klass);
240
+
241
+ dc->realize = aspeed_rtc_realize;
242
+ dc->vmsd = &vmstate_aspeed_rtc;
243
+ dc->reset = aspeed_rtc_reset;
244
+}
245
+
246
+static const TypeInfo aspeed_rtc_info = {
247
+ .name = TYPE_ASPEED_RTC,
248
+ .parent = TYPE_SYS_BUS_DEVICE,
249
+ .instance_size = sizeof(AspeedRtcState),
250
+ .class_init = aspeed_rtc_class_init,
251
+};
252
+
253
+static void aspeed_rtc_register_types(void)
254
+{
255
+ type_register_static(&aspeed_rtc_info);
256
+}
257
+
258
+type_init(aspeed_rtc_register_types)
259
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
260
index XXXXXXX..XXXXXXX 100644
261
--- a/hw/timer/trace-events
262
+++ b/hw/timer/trace-events
263
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_dualtimer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK A
264
cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB dualtimer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
265
cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
266
267
+# hw/timer/aspeed-rtc.c
268
+aspeed_rtc_read(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64
269
+aspeed_rtc_write(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " value 0x%08" PRIx64
270
+
271
# sun4v-rtc.c
272
sun4v_rtc_read(uint64_t addr, uint64_t value) "read: addr 0x%" PRIx64 " value 0x%" PRIx64
273
sun4v_rtc_write(uint64_t addr, uint64_t value) "write: addr 0x%" PRIx64 " value 0x%" PRIx64
274
--
172
--
275
2.20.1
173
2.20.1
276
174
277
175
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/46] hw/arm/aspeed: Add RTC to SoC
Deleted patch
1
From: Joel Stanley <joel@jms.id.au>
2
1
3
All systems have an RTC.
4
5
The IRQ is hooked up but the model does not use it at this stage. There
6
is no guest code that uses it, so this limitation is acceptable.
7
8
Signed-off-by: Joel Stanley <joel@jms.id.au>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20190618165311.27066-5-clg@kaod.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/hw/arm/aspeed_soc.h | 2 ++
14
hw/arm/aspeed_soc.c | 13 +++++++++++++
15
2 files changed, 15 insertions(+)
16
17
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/aspeed_soc.h
20
+++ b/include/hw/arm/aspeed_soc.h
21
@@ -XXX,XX +XXX,XX @@
22
#include "hw/misc/aspeed_scu.h"
23
#include "hw/misc/aspeed_sdmc.h"
24
#include "hw/timer/aspeed_timer.h"
25
+#include "hw/timer/aspeed_rtc.h"
26
#include "hw/i2c/aspeed_i2c.h"
27
#include "hw/ssi/aspeed_smc.h"
28
#include "hw/watchdog/wdt_aspeed.h"
29
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
30
ARMCPU cpu;
31
MemoryRegion sram;
32
AspeedVICState vic;
33
+ AspeedRtcState rtc;
34
AspeedTimerCtrlState timerctrl;
35
AspeedI2CState i2c;
36
AspeedSCUState scu;
37
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/arm/aspeed_soc.c
40
+++ b/hw/arm/aspeed_soc.c
41
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
42
sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
43
TYPE_ASPEED_VIC);
44
45
+ sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
46
+ TYPE_ASPEED_RTC);
47
+
48
sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
49
sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
50
object_property_add_const_link(OBJECT(&s->timerctrl), "scu",
51
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
52
sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
53
qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
54
55
+ /* RTC */
56
+ object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
57
+ if (err) {
58
+ error_propagate(errp, err);
59
+ return;
60
+ }
61
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->info->memmap[ASPEED_RTC]);
62
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
63
+ aspeed_soc_get_irq(s, ASPEED_RTC));
64
+
65
/* Timer */
66
object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
67
if (err) {
68
--
69
2.20.1
70
71
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/46] aspeed: introduce a configurable number of CPU per machine
[PULL 16/24] target/arm: Implement MVE VSRI, VSLI
1
From: Cédric Le Goater <clg@kaod.org>
1
Implement the MVE VSRI and VSLI insns, which perform a
2
shift-and-insert operation.
2
3
3
The current models of the Aspeed SoCs only have one CPU but future
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
ones will support SMP. Introduce a new num_cpus field at the SoC class
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
level to define the number of available CPUs per SoC and also
6
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
6
introduce a 'num-cpus' property to activate the CPUs configured for
7
---
7
the machine.
8
target/arm/helper-mve.h | 8 ++++++++
9
target/arm/mve.decode | 9 ++++++++
10
target/arm/mve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++
11
target/arm/translate-mve.c | 3 +++
12
4 files changed, 62 insertions(+)
8
13
9
The max_cpus limit of the machine should depend on the SoC definition
14
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
10
but, unfortunately, these values are not available when the machine
11
class is initialized. This is the reason why we add a check on
12
num_cpus in the AspeedSoC realize handler.
13
14
SMP support will be activated when models for such SoCs are implemented.
15
16
Signed-off-by: Cédric Le Goater <clg@kaod.org>
17
Reviewed-by: Joel Stanley <joel@jms.id.au>
18
Message-id: 20190618165311.27066-6-clg@kaod.org
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
include/hw/arm/aspeed_soc.h | 5 ++++-
22
hw/arm/aspeed.c | 7 +++++--
23
hw/arm/aspeed_soc.c | 33 +++++++++++++++++++++++++++------
24
3 files changed, 36 insertions(+), 9 deletions(-)
25
26
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
27
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/arm/aspeed_soc.h
16
--- a/target/arm/helper-mve.h
29
+++ b/include/hw/arm/aspeed_soc.h
17
+++ b/target/arm/helper-mve.h
30
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
19
DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
#define ASPEED_SPIS_NUM 2
20
DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
#define ASPEED_WDTS_NUM 3
21
DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
+#define ASPEED_CPUS_NUM 2
22
+
35
23
+DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
typedef struct AspeedSoCState {
24
+DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
/*< private >*/
25
+DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
DeviceState parent;
26
+
39
27
+DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
/*< public >*/
28
+DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
- ARMCPU cpu;
29
+DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
+ ARMCPU cpu[ASPEED_CPUS_NUM];
30
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
43
+ uint32_t num_cpus;
44
MemoryRegion sram;
45
AspeedVICState vic;
46
AspeedRtcState rtc;
47
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCInfo {
48
int wdts_num;
49
const int *irqmap;
50
const hwaddr *memmap;
51
+ uint32_t num_cpus;
52
} AspeedSoCInfo;
53
54
typedef struct AspeedSoCClass {
55
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
56
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/arm/aspeed.c
32
--- a/target/arm/mve.decode
58
+++ b/hw/arm/aspeed.c
33
+++ b/target/arm/mve.decode
59
@@ -XXX,XX +XXX,XX @@
34
@@ -XXX,XX +XXX,XX @@ VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
60
#include "hw/misc/tmp105.h"
35
61
#include "qemu/log.h"
36
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
62
#include "sysemu/block-backend.h"
37
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
63
+#include "sysemu/sysemu.h"
38
+
64
#include "hw/loader.h"
39
+# Shift-and-insert
65
#include "qemu/error-report.h"
40
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b
66
#include "qemu/units.h"
41
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h
67
42
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
68
static struct arm_boot_info aspeed_board_binfo = {
43
+
69
.board_id = -1, /* device-tree-only board */
44
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
70
- .nb_cpus = 1,
45
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
71
};
46
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
72
47
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
73
struct AspeedBoardState {
74
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
75
&error_abort);
76
object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs",
77
&error_abort);
78
+ object_property_set_int(OBJECT(&bmc->soc), smp_cpus, "num-cpus",
79
+ &error_abort);
80
if (machine->kernel_filename) {
81
/*
82
* When booting with a -kernel command line there is no u-boot
83
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
84
aspeed_board_binfo.kernel_cmdline = machine->kernel_cmdline;
85
aspeed_board_binfo.ram_size = ram_size;
86
aspeed_board_binfo.loader_start = sc->info->memmap[ASPEED_SDRAM];
87
+ aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus;
88
89
if (cfg->i2c_init) {
90
cfg->i2c_init(bmc);
91
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data)
92
93
mc->desc = board->desc;
94
mc->init = aspeed_machine_init;
95
- mc->max_cpus = 1;
96
+ mc->max_cpus = ASPEED_CPUS_NUM;
97
mc->no_sdcard = 1;
98
mc->no_floppy = 1;
99
mc->no_cdrom = 1;
100
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
101
index XXXXXXX..XXXXXXX 100644
48
index XXXXXXX..XXXXXXX 100644
102
--- a/hw/arm/aspeed_soc.c
49
--- a/target/arm/mve_helper.c
103
+++ b/hw/arm/aspeed_soc.c
50
+++ b/target/arm/mve_helper.c
104
@@ -XXX,XX +XXX,XX @@
51
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
105
#include "hw/char/serial.h"
52
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
106
#include "qemu/log.h"
53
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
107
#include "qemu/module.h"
54
108
+#include "qemu/error-report.h"
55
+/* Shift-and-insert; we always work with 64 bits at a time */
109
#include "hw/i2c/aspeed_i2c.h"
56
+#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \
110
#include "net/net.h"
57
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
111
58
+ void *vm, uint32_t shift) \
112
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
59
+ { \
113
.wdts_num = 2,
60
+ uint64_t *d = vd, *m = vm; \
114
.irqmap = aspeed_soc_ast2400_irqmap,
61
+ uint16_t mask; \
115
.memmap = aspeed_soc_ast2400_memmap,
62
+ uint64_t shiftmask; \
116
+ .num_cpus = 1,
63
+ unsigned e; \
117
}, {
64
+ if (shift == 0 || shift == ESIZE * 8) { \
118
.name = "ast2400-a1",
65
+ /* \
119
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
66
+ * Only VSLI can shift by 0; only VSRI can shift by <dt>. \
120
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
67
+ * The generic logic would give the right answer for 0 but \
121
.wdts_num = 2,
68
+ * fails for <dt>. \
122
.irqmap = aspeed_soc_ast2400_irqmap,
69
+ */ \
123
.memmap = aspeed_soc_ast2400_memmap,
70
+ goto done; \
124
+ .num_cpus = 1,
71
+ } \
125
}, {
72
+ assert(shift < ESIZE * 8); \
126
.name = "ast2400",
73
+ mask = mve_element_mask(env); \
127
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
74
+ /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \
128
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
75
+ shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \
129
.wdts_num = 2,
76
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
130
.irqmap = aspeed_soc_ast2400_irqmap,
77
+ uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \
131
.memmap = aspeed_soc_ast2400_memmap,
78
+ (d[H8(e)] & ~shiftmask); \
132
+ .num_cpus = 1,
79
+ mergemask(&d[H8(e)], r, mask); \
133
}, {
80
+ } \
134
.name = "ast2500-a1",
81
+done: \
135
.cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
82
+ mve_advance_vpt(env); \
136
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
137
.wdts_num = 3,
138
.irqmap = aspeed_soc_ast2500_irqmap,
139
.memmap = aspeed_soc_ast2500_memmap,
140
+ .num_cpus = 1,
141
},
142
};
143
144
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
145
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
146
int i;
147
148
- object_initialize_child(obj, "cpu", OBJECT(&s->cpu), sizeof(s->cpu),
149
- sc->info->cpu_type, &error_abort, NULL);
150
+ for (i = 0; i < sc->info->num_cpus; i++) {
151
+ object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
152
+ sizeof(s->cpu[i]), sc->info->cpu_type,
153
+ &error_abort, NULL);
154
+ }
155
156
sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
157
TYPE_ASPEED_SCU);
158
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
159
create_unimplemented_device("aspeed_soc.io", sc->info->memmap[ASPEED_IOMEM],
160
ASPEED_SOC_IOMEM_SIZE);
161
162
+ if (s->num_cpus > sc->info->num_cpus) {
163
+ warn_report("%s: invalid number of CPUs %d, using default %d",
164
+ sc->info->name, s->num_cpus, sc->info->num_cpus);
165
+ s->num_cpus = sc->info->num_cpus;
166
+ }
83
+ }
167
+
84
+
168
/* CPU */
85
+#define DO_SHL(N, SHIFT) ((N) << (SHIFT))
169
- object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
86
+#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
170
- if (err) {
87
+#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
171
- error_propagate(errp, err);
88
+#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
172
- return;
89
+
173
+ for (i = 0; i < s->num_cpus; i++) {
90
+DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
174
+ object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
91
+DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
175
+ if (err) {
92
+DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
176
+ error_propagate(errp, err);
93
+DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
177
+ return;
94
+DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
178
+ }
95
+DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
179
}
96
+
180
97
/*
181
/* SRAM */
98
* Long shifts taking half-sized inputs from top or bottom of the input
182
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
99
* vector and producing a double-width result. ESIZE, TYPE are for
183
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
184
aspeed_soc_get_irq(s, ASPEED_ETH1));
101
index XXXXXXX..XXXXXXX 100644
185
}
102
--- a/target/arm/translate-mve.c
186
+static Property aspeed_soc_properties[] = {
103
+++ b/target/arm/translate-mve.c
187
+ DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
104
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true)
188
+ DEFINE_PROP_END_OF_LIST(),
105
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
189
+};
106
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
190
107
191
static void aspeed_soc_class_init(ObjectClass *oc, void *data)
108
+DO_2SHIFT(VSRI, vsri, false)
192
{
109
+DO_2SHIFT(VSLI, vsli, false)
193
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
110
+
194
dc->realize = aspeed_soc_realize;
111
#define DO_VSHLL(INSN, FN) \
195
/* Reason: Uses serial_hds and nd_table in realize() directly */
112
static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
196
dc->user_creatable = false;
113
{ \
197
+ dc->props = aspeed_soc_properties;
198
}
199
200
static const TypeInfo aspeed_soc_type_info = {
201
--
114
--
202
2.20.1
115
2.20.1
203
116
204
117
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/46] aspeed: add support for multiple NICs
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
The Aspeed SoCs have two MACs. Extend the Aspeed model to support a
4
second NIC.
5
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7
Reviewed-by: Joel Stanley <joel@jms.id.au>
8
Message-id: 20190618165311.27066-7-clg@kaod.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/aspeed_soc.h | 3 ++-
12
hw/arm/aspeed_soc.c | 33 +++++++++++++++++++--------------
13
2 files changed, 21 insertions(+), 15 deletions(-)
14
15
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/aspeed_soc.h
18
+++ b/include/hw/arm/aspeed_soc.h
19
@@ -XXX,XX +XXX,XX @@
20
#define ASPEED_SPIS_NUM 2
21
#define ASPEED_WDTS_NUM 3
22
#define ASPEED_CPUS_NUM 2
23
+#define ASPEED_MACS_NUM 2
24
25
typedef struct AspeedSoCState {
26
/*< private >*/
27
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
28
AspeedSMCState spi[ASPEED_SPIS_NUM];
29
AspeedSDMCState sdmc;
30
AspeedWDTState wdt[ASPEED_WDTS_NUM];
31
- FTGMAC100State ftgmac100;
32
+ FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
33
} AspeedSoCState;
34
35
#define TYPE_ASPEED_SOC "aspeed-soc"
36
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/arm/aspeed_soc.c
39
+++ b/hw/arm/aspeed_soc.c
40
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
41
sc->info->silicon_rev);
42
}
43
44
- sysbus_init_child_obj(obj, "ftgmac100", OBJECT(&s->ftgmac100),
45
- sizeof(s->ftgmac100), TYPE_FTGMAC100);
46
+ for (i = 0; i < ASPEED_MACS_NUM; i++) {
47
+ sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
48
+ sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
49
+ }
50
}
51
52
static void aspeed_soc_realize(DeviceState *dev, Error **errp)
53
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
54
}
55
56
/* Net */
57
- qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]);
58
- object_property_set_bool(OBJECT(&s->ftgmac100), true, "aspeed", &err);
59
- object_property_set_bool(OBJECT(&s->ftgmac100), true, "realized",
60
- &local_err);
61
- error_propagate(&err, local_err);
62
- if (err) {
63
- error_propagate(errp, err);
64
- return;
65
+ for (i = 0; i < nb_nics; i++) {
66
+ qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
67
+ object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
68
+ &err);
69
+ object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
70
+ &local_err);
71
+ error_propagate(&err, local_err);
72
+ if (err) {
73
+ error_propagate(errp, err);
74
+ return;
75
+ }
76
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
77
+ sc->info->memmap[ASPEED_ETH1 + i]);
78
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
79
+ aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
80
}
81
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0,
82
- sc->info->memmap[ASPEED_ETH1]);
83
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
84
- aspeed_soc_get_irq(s, ASPEED_ETH1));
85
}
86
static Property aspeed_soc_properties[] = {
87
DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
88
--
89
2.20.1
90
91
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/46] aspeed/timer: Status register contains reload for stopped timer
Deleted patch
1
From: Andrew Jeffery <andrew@aj.id.au>
2
1
3
From the datasheet:
4
5
This register stores the current status of counter #N. When timer
6
enable bit TMC30[N * b] is disabled, the reload register will be
7
loaded into this counter. When timer bit TMC30[N * b] is set, the
8
counter will start to decrement. CPU can update this register value
9
when enable bit is set.
10
11
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
12
Signed-off-by: Cédric Le Goater <clg@kaod.org>
13
Reviewed-by: Joel Stanley <joel@jms.id.au>
14
Message-id: 20190618165311.27066-9-clg@kaod.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/timer/aspeed_timer.c | 6 +++++-
18
1 file changed, 5 insertions(+), 1 deletion(-)
19
20
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/timer/aspeed_timer.c
23
+++ b/hw/timer/aspeed_timer.c
24
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_timer_get_value(AspeedTimer *t, int reg)
25
26
switch (reg) {
27
case TIMER_REG_STATUS:
28
- value = calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
29
+ if (timer_enabled(t)) {
30
+ value = calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
31
+ } else {
32
+ value = t->reload;
33
+ }
34
break;
35
case TIMER_REG_RELOAD:
36
value = t->reload;
37
--
38
2.20.1
39
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/46] aspeed/timer: Ensure positive muldiv delta
Deleted patch
1
From: Christian Svensson <bluecmd@google.com>
2
1
3
If the host decrements the counter register that results in a negative
4
delta. This is then passed to muldiv64 which only handles unsigned
5
numbers resulting in bogus results.
6
7
This fix ensures the delta being operated on is positive.
8
9
Test case: kexec a kernel using aspeed_timer and it will freeze on the
10
second bootup when the kernel initializes the timer. With this patch
11
that no longer happens and the timer appears to run OK.
12
13
Signed-off-by: Christian Svensson <bluecmd@google.com>
14
Signed-off-by: Cédric Le Goater <clg@kaod.org>
15
Reviewed-by: Joel Stanley <joel@jms.id.au>
16
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
17
Message-id: 20190618165311.27066-12-clg@kaod.org
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
hw/timer/aspeed_timer.c | 6 +++++-
21
1 file changed, 5 insertions(+), 1 deletion(-)
22
23
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/timer/aspeed_timer.c
26
+++ b/hw/timer/aspeed_timer.c
27
@@ -XXX,XX +XXX,XX @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
28
int64_t delta = (int64_t) value - (int64_t) calculate_ticks(t, now);
29
uint32_t rate = calculate_rate(t);
30
31
- t->start += muldiv64(delta, NANOSECONDS_PER_SECOND, rate);
32
+ if (delta >= 0) {
33
+ t->start += muldiv64(delta, NANOSECONDS_PER_SECOND, rate);
34
+ } else {
35
+ t->start -= muldiv64(-delta, NANOSECONDS_PER_SECOND, rate);
36
+ }
37
aspeed_timer_mod(t);
38
}
39
break;
40
--
41
2.20.1
42
43
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/46] aspeed: remove the "ram" link
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
It has never been used as far as I can tell from the git history.
4
5
Signed-off-by: Cédric Le Goater <clg@kaod.org>
6
Reviewed-by: Joel Stanley <joel@jms.id.au>
7
Message-id: 20190618165311.27066-13-clg@kaod.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/arm/aspeed.c | 2 --
11
1 file changed, 2 deletions(-)
12
13
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/aspeed.c
16
+++ b/hw/arm/aspeed.c
17
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
18
memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
19
memory_region_add_subregion(get_system_memory(),
20
sc->info->memmap[ASPEED_SDRAM], &bmc->ram);
21
- object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
22
- &error_abort);
23
24
max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
25
&error_abort);
26
--
27
2.20.1
28
29
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/46] aspeed: add a RAM memory region container
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
The RAM memory region is defined after the SoC is realized when the
4
SDMC controller has checked that the defined RAM size for the machine
5
is correct. This is problematic for controller models requiring a link
6
on the RAM region, for DMA support in the SMC controller for instance.
7
8
Introduce a container memory region for the RAM that we can link into
9
the controllers early, before the SoC is realized. It will be
10
populated with the RAM region after the checks have be done.
11
12
Signed-off-by: Cédric Le Goater <clg@kaod.org>
13
Reviewed-by: Joel Stanley <joel@jms.id.au>
14
Message-id: 20190618165311.27066-14-clg@kaod.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/arm/aspeed.c | 13 +++++++++----
18
1 file changed, 9 insertions(+), 4 deletions(-)
19
20
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/aspeed.c
23
+++ b/hw/arm/aspeed.c
24
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info aspeed_board_binfo = {
25
26
struct AspeedBoardState {
27
AspeedSoCState soc;
28
+ MemoryRegion ram_container;
29
MemoryRegion ram;
30
MemoryRegion max_ram;
31
};
32
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
33
ram_addr_t max_ram_size;
34
35
bmc = g_new0(AspeedBoardState, 1);
36
+
37
+ memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container",
38
+ UINT32_MAX);
39
+
40
object_initialize_child(OBJECT(machine), "soc", &bmc->soc,
41
(sizeof(bmc->soc)), cfg->soc_name, &error_abort,
42
NULL);
43
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
44
&error_abort);
45
46
memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
47
+ memory_region_add_subregion(&bmc->ram_container, 0, &bmc->ram);
48
memory_region_add_subregion(get_system_memory(),
49
- sc->info->memmap[ASPEED_SDRAM], &bmc->ram);
50
+ sc->info->memmap[ASPEED_SDRAM],
51
+ &bmc->ram_container);
52
53
max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
54
&error_abort);
55
memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
56
"max_ram", max_ram_size - ram_size);
57
- memory_region_add_subregion(get_system_memory(),
58
- sc->info->memmap[ASPEED_SDRAM] + ram_size,
59
- &bmc->max_ram);
60
+ memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_ram);
61
62
aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);
63
aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort);
64
--
65
2.20.1
66
67
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/46] aspeed/smc: add a 'sdram_base' property
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
The DRAM address of a DMA transaction depends on the DRAM base address
4
of the SoC. Inform the SMC controller model with this value.
5
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7
Reviewed-by: Joel Stanley <joel@jms.id.au>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190618165311.27066-15-clg@kaod.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/ssi/aspeed_smc.h | 3 +++
13
hw/arm/aspeed_soc.c | 6 ++++++
14
hw/ssi/aspeed_smc.c | 1 +
15
3 files changed, 10 insertions(+)
16
17
diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/ssi/aspeed_smc.h
20
+++ b/include/hw/ssi/aspeed_smc.h
21
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSMCState {
22
uint8_t r_timings;
23
uint8_t conf_enable_w0;
24
25
+ /* for DMA support */
26
+ uint64_t sdram_base;
27
+
28
AspeedSMCFlash *flashes;
29
30
uint8_t snoop_index;
31
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/aspeed_soc.c
34
+++ b/hw/arm/aspeed_soc.c
35
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
36
aspeed_soc_get_irq(s, ASPEED_I2C));
37
38
/* FMC, The number of CS is set at the board level */
39
+ object_property_set_int(OBJECT(&s->fmc), sc->info->memmap[ASPEED_SDRAM],
40
+ "sdram-base", &err);
41
+ if (err) {
42
+ error_propagate(errp, err);
43
+ return;
44
+ }
45
object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
46
if (err) {
47
error_propagate(errp, err);
48
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/ssi/aspeed_smc.c
51
+++ b/hw/ssi/aspeed_smc.c
52
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_smc = {
53
54
static Property aspeed_smc_properties[] = {
55
DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1),
56
+ DEFINE_PROP_UINT64("sdram-base", AspeedSMCState, sdram_base, 0),
57
DEFINE_PROP_END_OF_LIST(),
58
};
59
60
--
61
2.20.1
62
63
diff view generated by jsdifflib
[Qemu-devel] [PULL 22/46] aspeed: Add support for the swift-bmc board
Deleted patch
1
From: Adriana Kobylak <anoo@us.ibm.com>
2
1
3
The Swift board is an OpenPOWER system hosting POWER processors.
4
Add support for their BMC including the I2C devices as found on HW.
5
6
Signed-off-by: Adriana Kobylak <anoo@us.ibm.com>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Reviewed-by: Joel Stanley <joel@jms.id.au>
9
Message-id: 20190618165311.27066-20-clg@kaod.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/aspeed.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++++
13
1 file changed, 50 insertions(+)
14
15
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/aspeed.c
18
+++ b/hw/arm/aspeed.c
19
@@ -XXX,XX +XXX,XX @@ struct AspeedBoardState {
20
SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
21
SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
22
23
+/* Swift hardware value: 0xF11AD206 */
24
+#define SWIFT_BMC_HW_STRAP1 ( \
25
+ AST2500_HW_STRAP1_DEFAULTS | \
26
+ SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
27
+ SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
28
+ SCU_AST2500_HW_STRAP_UART_DEBUG | \
29
+ SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
30
+ SCU_H_PLL_BYPASS_EN | \
31
+ SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
32
+ SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
33
+
34
/* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
35
#define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
36
37
@@ -XXX,XX +XXX,XX @@ static void romulus_bmc_i2c_init(AspeedBoardState *bmc)
38
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
39
}
40
41
+static void swift_bmc_i2c_init(AspeedBoardState *bmc)
42
+{
43
+ AspeedSoCState *soc = &bmc->soc;
44
+
45
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), "pca9552", 0x60);
46
+
47
+ /* The swift board expects a TMP275 but a TMP105 is compatible */
48
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x48);
49
+ /* The swift board expects a pca9551 but a pca9552 is compatible */
50
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "pca9552", 0x60);
51
+
52
+ /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */
53
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "ds1338", 0x32);
54
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x60);
55
+
56
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "tmp423", 0x4c);
57
+ /* The swift board expects a pca9539 but a pca9552 is compatible */
58
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "pca9552", 0x74);
59
+
60
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "tmp423", 0x4c);
61
+ /* The swift board expects a pca9539 but a pca9552 is compatible */
62
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "pca9552",
63
+ 0x74);
64
+
65
+ /* The swift board expects a TMP275 but a TMP105 is compatible */
66
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x48);
67
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x4a);
68
+}
69
+
70
static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
71
{
72
AspeedSoCState *soc = &bmc->soc;
73
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
74
.num_cs = 2,
75
.i2c_init = romulus_bmc_i2c_init,
76
.ram = 512 * MiB,
77
+ }, {
78
+ .name = MACHINE_TYPE_NAME("swift-bmc"),
79
+ .desc = "OpenPOWER Swift BMC (ARM1176)",
80
+ .soc_name = "ast2500-a1",
81
+ .hw_strap1 = SWIFT_BMC_HW_STRAP1,
82
+ .fmc_model = "mx66l1g45g",
83
+ .spi_model = "mx66l1g45g",
84
+ .num_cs = 2,
85
+ .i2c_init = swift_bmc_i2c_init,
86
+ .ram = 512 * MiB,
87
}, {
88
.name = MACHINE_TYPE_NAME("witherspoon-bmc"),
89
.desc = "OpenPOWER Witherspoon BMC (ARM1176)",
90
--
91
2.20.1
92
93
diff view generated by jsdifflib
[Qemu-devel] [PULL 24/46] aspeed: vic: Add support for legacy register interface
Deleted patch
1
From: Andrew Jeffery <andrew@aj.id.au>
2
1
3
The legacy interface only supported up to 32 IRQs, which became
4
restrictive around the AST2400 generation. QEMU support for the SoCs
5
started with the AST2400 along with an effort to reimplement and
6
upstream drivers for Linux, so up until this point the consumers of the
7
QEMU ASPEED support only required the 64 IRQ register interface.
8
9
In an effort to support older BMC firmware, add support for the 32 IRQ
10
interface.
11
12
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
13
Signed-off-by: Cédric Le Goater <clg@kaod.org>
14
Reviewed-by: Joel Stanley <joel@jms.id.au>
15
Message-id: 20190618165311.27066-22-clg@kaod.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
hw/intc/aspeed_vic.c | 105 ++++++++++++++++++++++++++-----------------
19
1 file changed, 63 insertions(+), 42 deletions(-)
20
21
diff --git a/hw/intc/aspeed_vic.c b/hw/intc/aspeed_vic.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/intc/aspeed_vic.c
24
+++ b/hw/intc/aspeed_vic.c
25
@@ -XXX,XX +XXX,XX @@ static void aspeed_vic_set_irq(void *opaque, int irq, int level)
26
27
static uint64_t aspeed_vic_read(void *opaque, hwaddr offset, unsigned size)
28
{
29
- uint64_t val;
30
- const bool high = !!(offset & 0x4);
31
- hwaddr n_offset = (offset & ~0x4);
32
AspeedVICState *s = (AspeedVICState *)opaque;
33
+ hwaddr n_offset;
34
+ uint64_t val;
35
+ bool high;
36
37
if (offset < AVIC_NEW_BASE_OFFSET) {
38
- qemu_log_mask(LOG_UNIMP, "%s: Ignoring read from legacy registers "
39
- "at 0x%" HWADDR_PRIx "[%u]\n", __func__, offset, size);
40
- return 0;
41
+ high = false;
42
+ n_offset = offset;
43
+ } else {
44
+ high = !!(offset & 0x4);
45
+ n_offset = (offset & ~0x4);
46
}
47
48
- n_offset -= AVIC_NEW_BASE_OFFSET;
49
-
50
switch (n_offset) {
51
- case 0x0: /* IRQ Status */
52
+ case 0x80: /* IRQ Status */
53
+ case 0x00:
54
val = s->raw & ~s->select & s->enable;
55
break;
56
- case 0x08: /* FIQ Status */
57
+ case 0x88: /* FIQ Status */
58
+ case 0x04:
59
val = s->raw & s->select & s->enable;
60
break;
61
- case 0x10: /* Raw Interrupt Status */
62
+ case 0x90: /* Raw Interrupt Status */
63
+ case 0x08:
64
val = s->raw;
65
break;
66
- case 0x18: /* Interrupt Selection */
67
+ case 0x98: /* Interrupt Selection */
68
+ case 0x0c:
69
val = s->select;
70
break;
71
- case 0x20: /* Interrupt Enable */
72
+ case 0xa0: /* Interrupt Enable */
73
+ case 0x10:
74
val = s->enable;
75
break;
76
- case 0x30: /* Software Interrupt */
77
+ case 0xb0: /* Software Interrupt */
78
+ case 0x18:
79
val = s->trigger;
80
break;
81
- case 0x40: /* Interrupt Sensitivity */
82
+ case 0xc0: /* Interrupt Sensitivity */
83
+ case 0x24:
84
val = s->sense;
85
break;
86
- case 0x48: /* Interrupt Both Edge Trigger Control */
87
+ case 0xc8: /* Interrupt Both Edge Trigger Control */
88
+ case 0x28:
89
val = s->dual_edge;
90
break;
91
- case 0x50: /* Interrupt Event */
92
+ case 0xd0: /* Interrupt Event */
93
+ case 0x2c:
94
val = s->event;
95
break;
96
- case 0x60: /* Edge Triggered Interrupt Status */
97
+ case 0xe0: /* Edge Triggered Interrupt Status */
98
val = s->raw & ~s->sense;
99
break;
100
/* Illegal */
101
- case 0x28: /* Interrupt Enable Clear */
102
- case 0x38: /* Software Interrupt Clear */
103
- case 0x58: /* Edge Triggered Interrupt Clear */
104
+ case 0xa8: /* Interrupt Enable Clear */
105
+ case 0xb8: /* Software Interrupt Clear */
106
+ case 0xd8: /* Edge Triggered Interrupt Clear */
107
qemu_log_mask(LOG_GUEST_ERROR,
108
"%s: Read of write-only register with offset 0x%"
109
HWADDR_PRIx "\n", __func__, offset);
110
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_vic_read(void *opaque, hwaddr offset, unsigned size)
111
}
112
if (high) {
113
val = extract64(val, 32, 19);
114
+ } else {
115
+ val = extract64(val, 0, 32);
116
}
117
trace_aspeed_vic_read(offset, size, val);
118
return val;
119
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_vic_read(void *opaque, hwaddr offset, unsigned size)
120
static void aspeed_vic_write(void *opaque, hwaddr offset, uint64_t data,
121
unsigned size)
122
{
123
- const bool high = !!(offset & 0x4);
124
- hwaddr n_offset = (offset & ~0x4);
125
AspeedVICState *s = (AspeedVICState *)opaque;
126
+ hwaddr n_offset;
127
+ bool high;
128
129
if (offset < AVIC_NEW_BASE_OFFSET) {
130
- qemu_log_mask(LOG_UNIMP,
131
- "%s: Ignoring write to legacy registers at 0x%"
132
- HWADDR_PRIx "[%u] <- 0x%" PRIx64 "\n", __func__, offset,
133
- size, data);
134
- return;
135
+ high = false;
136
+ n_offset = offset;
137
+ } else {
138
+ high = !!(offset & 0x4);
139
+ n_offset = (offset & ~0x4);
140
}
141
142
- n_offset -= AVIC_NEW_BASE_OFFSET;
143
trace_aspeed_vic_write(offset, size, data);
144
145
/* Given we have members using separate enable/clear registers, deposit64()
146
@@ -XXX,XX +XXX,XX @@ static void aspeed_vic_write(void *opaque, hwaddr offset, uint64_t data,
147
}
148
149
switch (n_offset) {
150
- case 0x18: /* Interrupt Selection */
151
+ case 0x98: /* Interrupt Selection */
152
+ case 0x0c:
153
/* Register has deposit64() semantics - overwrite requested 32 bits */
154
if (high) {
155
s->select &= AVIC_L_MASK;
156
@@ -XXX,XX +XXX,XX @@ static void aspeed_vic_write(void *opaque, hwaddr offset, uint64_t data,
157
}
158
s->select |= data;
159
break;
160
- case 0x20: /* Interrupt Enable */
161
+ case 0xa0: /* Interrupt Enable */
162
+ case 0x10:
163
s->enable |= data;
164
break;
165
- case 0x28: /* Interrupt Enable Clear */
166
+ case 0xa8: /* Interrupt Enable Clear */
167
+ case 0x14:
168
s->enable &= ~data;
169
break;
170
- case 0x30: /* Software Interrupt */
171
+ case 0xb0: /* Software Interrupt */
172
+ case 0x18:
173
qemu_log_mask(LOG_UNIMP, "%s: Software interrupts unavailable. "
174
"IRQs requested: 0x%016" PRIx64 "\n", __func__, data);
175
break;
176
- case 0x38: /* Software Interrupt Clear */
177
+ case 0xb8: /* Software Interrupt Clear */
178
+ case 0x1c:
179
qemu_log_mask(LOG_UNIMP, "%s: Software interrupts unavailable. "
180
"IRQs to be cleared: 0x%016" PRIx64 "\n", __func__, data);
181
break;
182
- case 0x50: /* Interrupt Event */
183
+ case 0xd0: /* Interrupt Event */
184
/* Register has deposit64() semantics - overwrite the top four valid
185
* IRQ bits, as only the top four IRQs (GPIOs) can change their event
186
* type */
187
@@ -XXX,XX +XXX,XX @@ static void aspeed_vic_write(void *opaque, hwaddr offset, uint64_t data,
188
"Ignoring invalid write to interrupt event register");
189
}
190
break;
191
- case 0x58: /* Edge Triggered Interrupt Clear */
192
+ case 0xd8: /* Edge Triggered Interrupt Clear */
193
+ case 0x38:
194
s->raw &= ~(data & ~s->sense);
195
break;
196
- case 0x00: /* IRQ Status */
197
- case 0x08: /* FIQ Status */
198
- case 0x10: /* Raw Interrupt Status */
199
- case 0x40: /* Interrupt Sensitivity */
200
- case 0x48: /* Interrupt Both Edge Trigger Control */
201
- case 0x60: /* Edge Triggered Interrupt Status */
202
+ case 0x80: /* IRQ Status */
203
+ case 0x00:
204
+ case 0x88: /* FIQ Status */
205
+ case 0x04:
206
+ case 0x90: /* Raw Interrupt Status */
207
+ case 0x08:
208
+ case 0xc0: /* Interrupt Sensitivity */
209
+ case 0x24:
210
+ case 0xc8: /* Interrupt Both Edge Trigger Control */
211
+ case 0x28:
212
+ case 0xe0: /* Edge Triggered Interrupt Status */
213
qemu_log_mask(LOG_GUEST_ERROR,
214
"%s: Write of read-only register with offset 0x%"
215
HWADDR_PRIx "\n", __func__, offset);
216
--
217
2.20.1
218
219
diff view generated by jsdifflib
[Qemu-devel] [PULL 27/46] hw/arm: Add arm SBSA reference machine, devices part
[PULL 17/24] target/arm: Implement MVE VSHRN, VRSHRN
1
From: Hongbo Zhang <hongbo.zhang@linaro.org>
1
Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
2
2
3
Following the previous patch, this patch adds peripheral devices to the
3
do_urshr() is borrowed from sve_helper.c.
4
newly introduced SBSA-ref machine.
5
4
6
Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org>
7
Message-id: 1561890034-15921-3-git-send-email-hongbo.zhang@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
10
---
8
---
11
hw/arm/sbsa-ref.c | 535 ++++++++++++++++++++++++++++++++++++++++++++++
9
target/arm/helper-mve.h | 10 ++++++++++
12
1 file changed, 535 insertions(+)
10
target/arm/mve.decode | 11 +++++++++++
11
target/arm/mve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++
12
target/arm/translate-mve.c | 15 ++++++++++++++
13
4 files changed, 76 insertions(+)
13
14
14
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/sbsa-ref.c
17
--- a/target/arm/helper-mve.h
17
+++ b/hw/arm/sbsa-ref.c
18
+++ b/target/arm/helper-mve.h
18
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
19
*/
20
DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
21
DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
#include "qemu/osdep.h"
22
DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
+#include "qemu-common.h"
23
#include "qapi/error.h"
24
#include "qemu/error-report.h"
25
#include "qemu/units.h"
26
+#include "sysemu/device_tree.h"
27
#include "sysemu/numa.h"
28
#include "sysemu/sysemu.h"
29
#include "exec/address-spaces.h"
30
#include "exec/hwaddr.h"
31
#include "kvm_arm.h"
32
#include "hw/arm/boot.h"
33
+#include "hw/block/flash.h"
34
#include "hw/boards.h"
35
+#include "hw/ide/internal.h"
36
+#include "hw/ide/ahci_internal.h"
37
#include "hw/intc/arm_gicv3_common.h"
38
+#include "hw/loader.h"
39
+#include "hw/pci-host/gpex.h"
40
+#include "hw/usb.h"
41
+#include "net/net.h"
42
43
#define RAMLIMIT_GB 8192
44
#define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
45
46
+#define NUM_IRQS 256
47
+#define NUM_SMMU_IRQS 4
48
+#define NUM_SATA_PORTS 6
49
+
23
+
50
+#define VIRTUAL_PMU_IRQ 7
24
+DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
51
+#define ARCH_GIC_MAINT_IRQ 9
25
+DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
52
+#define ARCH_TIMER_VIRT_IRQ 11
26
+DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
53
+#define ARCH_TIMER_S_EL1_IRQ 13
27
+DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
54
+#define ARCH_TIMER_NS_EL1_IRQ 14
55
+#define ARCH_TIMER_NS_EL2_IRQ 10
56
+
28
+
57
enum {
29
+DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
58
SBSA_FLASH,
30
+DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
59
SBSA_MEM,
31
+DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
60
@@ -XXX,XX +XXX,XX @@ typedef struct {
32
+DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
61
void *fdt;
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
62
int fdt_size;
34
index XXXXXXX..XXXXXXX 100644
63
int psci_conduit;
35
--- a/target/arm/mve.decode
64
+ PFlashCFI01 *flash[2];
36
+++ b/target/arm/mve.decode
65
} SBSAMachineState;
37
@@ -XXX,XX +XXX,XX @@ VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
66
38
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
67
#define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref")
39
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
68
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry sbsa_ref_memmap[] = {
40
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
69
[SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES },
41
+
70
};
42
+# Narrowing shifts (which only support b and h sizes)
71
43
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
72
+static const int sbsa_ref_irqmap[] = {
44
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
73
+ [SBSA_UART] = 1,
45
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
74
+ [SBSA_RTC] = 2,
46
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
75
+ [SBSA_PCIE] = 3, /* ... to 6 */
47
+
76
+ [SBSA_GPIO] = 7,
48
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
77
+ [SBSA_SECURE_UART] = 8,
49
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
78
+ [SBSA_SECURE_UART_MM] = 9,
50
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
79
+ [SBSA_AHCI] = 10,
51
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
80
+ [SBSA_EHCI] = 11,
52
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
81
+};
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/mve_helper.c
55
+++ b/target/arm/mve_helper.c
56
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
57
58
DO_VSHLL_ALL(vshllb, false)
59
DO_VSHLL_ALL(vshllt, true)
82
+
60
+
83
+/*
61
+/*
84
+ * Firmware on this machine only uses ACPI table to load OS, these limited
62
+ * Narrowing right shifts, taking a double sized input, shifting it
85
+ * device tree nodes are just to let firmware know the info which varies from
63
+ * and putting the result in either the top or bottom half of the output.
86
+ * command line parameters, so it is not necessary to be fully compatible
64
+ * ESIZE, TYPE are the output, and LESIZE, LTYPE the input.
87
+ * with the kernel CPU and NUMA binding rules.
88
+ */
65
+ */
89
+static void create_fdt(SBSAMachineState *sms)
66
+#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
90
+{
67
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
91
+ void *fdt = create_device_tree(&sms->fdt_size);
68
+ void *vm, uint32_t shift) \
92
+ const MachineState *ms = MACHINE(sms);
69
+ { \
93
+ int cpu;
70
+ LTYPE *m = vm; \
94
+
71
+ TYPE *d = vd; \
95
+ if (!fdt) {
72
+ uint16_t mask = mve_element_mask(env); \
96
+ error_report("create_device_tree() failed");
73
+ unsigned le; \
97
+ exit(1);
74
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
75
+ TYPE r = FN(m[H##LESIZE(le)], shift); \
76
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
77
+ } \
78
+ mve_advance_vpt(env); \
98
+ }
79
+ }
99
+
80
+
100
+ sms->fdt = fdt;
81
+#define DO_VSHRN_ALL(OP, FN) \
82
+ DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \
83
+ DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \
84
+ DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \
85
+ DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
101
+
86
+
102
+ qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref");
87
+static inline uint64_t do_urshr(uint64_t x, unsigned sh)
103
+ qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
88
+{
104
+ qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
89
+ if (likely(sh < 64)) {
105
+
90
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
106
+ if (have_numa_distance) {
91
+ } else if (sh == 64) {
107
+ int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
92
+ return x >> 63;
108
+ uint32_t *matrix = g_malloc0(size);
93
+ } else {
109
+ int idx, i, j;
94
+ return 0;
110
+
111
+ for (i = 0; i < nb_numa_nodes; i++) {
112
+ for (j = 0; j < nb_numa_nodes; j++) {
113
+ idx = (i * nb_numa_nodes + j) * 3;
114
+ matrix[idx + 0] = cpu_to_be32(i);
115
+ matrix[idx + 1] = cpu_to_be32(j);
116
+ matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]);
117
+ }
118
+ }
119
+
120
+ qemu_fdt_add_subnode(fdt, "/distance-map");
121
+ qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
122
+ matrix, size);
123
+ g_free(matrix);
124
+ }
125
+
126
+ qemu_fdt_add_subnode(sms->fdt, "/cpus");
127
+
128
+ for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) {
129
+ char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
130
+ ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
131
+ CPUState *cs = CPU(armcpu);
132
+
133
+ qemu_fdt_add_subnode(sms->fdt, nodename);
134
+
135
+ if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
136
+ qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id",
137
+ ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
138
+ }
139
+
140
+ g_free(nodename);
141
+ }
95
+ }
142
+}
96
+}
143
+
97
+
144
+#define SBSA_FLASH_SECTOR_SIZE (256 * KiB)
98
+DO_VSHRN_ALL(vshrn, DO_SHR)
99
+DO_VSHRN_ALL(vrshrn, do_urshr)
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/arm/translate-mve.c
103
+++ b/target/arm/translate-mve.c
104
@@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs)
105
DO_VSHLL(VSHLL_BU, vshllbu)
106
DO_VSHLL(VSHLL_TS, vshllts)
107
DO_VSHLL(VSHLL_TU, vshlltu)
145
+
108
+
146
+static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms,
109
+#define DO_2SHIFT_N(INSN, FN) \
147
+ const char *name,
110
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
148
+ const char *alias_prop_name)
111
+ { \
149
+{
112
+ static MVEGenTwoOpShiftFn * const fns[] = { \
150
+ /*
113
+ gen_helper_mve_##FN##b, \
151
+ * Create a single flash device. We use the same parameters as
114
+ gen_helper_mve_##FN##h, \
152
+ * the flash devices on the Versatile Express board.
115
+ }; \
153
+ */
116
+ return do_2shift(s, a, fns[a->size], false); \
154
+ DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
155
+
156
+ qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE);
157
+ qdev_prop_set_uint8(dev, "width", 4);
158
+ qdev_prop_set_uint8(dev, "device-width", 2);
159
+ qdev_prop_set_bit(dev, "big-endian", false);
160
+ qdev_prop_set_uint16(dev, "id0", 0x89);
161
+ qdev_prop_set_uint16(dev, "id1", 0x18);
162
+ qdev_prop_set_uint16(dev, "id2", 0x00);
163
+ qdev_prop_set_uint16(dev, "id3", 0x00);
164
+ qdev_prop_set_string(dev, "name", name);
165
+ object_property_add_child(OBJECT(sms), name, OBJECT(dev),
166
+ &error_abort);
167
+ object_property_add_alias(OBJECT(sms), alias_prop_name,
168
+ OBJECT(dev), "drive", &error_abort);
169
+ return PFLASH_CFI01(dev);
170
+}
171
+
172
+static void sbsa_flash_create(SBSAMachineState *sms)
173
+{
174
+ sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0");
175
+ sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1");
176
+}
177
+
178
+static void sbsa_flash_map1(PFlashCFI01 *flash,
179
+ hwaddr base, hwaddr size,
180
+ MemoryRegion *sysmem)
181
+{
182
+ DeviceState *dev = DEVICE(flash);
183
+
184
+ assert(size % SBSA_FLASH_SECTOR_SIZE == 0);
185
+ assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX);
186
+ qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE);
187
+ qdev_init_nofail(dev);
188
+
189
+ memory_region_add_subregion(sysmem, base,
190
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
191
+ 0));
192
+}
193
+
194
+static void sbsa_flash_map(SBSAMachineState *sms,
195
+ MemoryRegion *sysmem,
196
+ MemoryRegion *secure_sysmem)
197
+{
198
+ /*
199
+ * Map two flash devices to fill the SBSA_FLASH space in the memmap.
200
+ * sysmem is the system memory space. secure_sysmem is the secure view
201
+ * of the system, and the first flash device should be made visible only
202
+ * there. The second flash device is visible to both secure and nonsecure.
203
+ * If sysmem == secure_sysmem this means there is no separate Secure
204
+ * address space and both flash devices are generally visible.
205
+ */
206
+ hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2;
207
+ hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base;
208
+
209
+ sbsa_flash_map1(sms->flash[0], flashbase, flashsize,
210
+ secure_sysmem);
211
+ sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize,
212
+ sysmem);
213
+}
214
+
215
+static bool sbsa_firmware_init(SBSAMachineState *sms,
216
+ MemoryRegion *sysmem,
217
+ MemoryRegion *secure_sysmem)
218
+{
219
+ int i;
220
+ BlockBackend *pflash_blk0;
221
+
222
+ /* Map legacy -drive if=pflash to machine properties */
223
+ for (i = 0; i < ARRAY_SIZE(sms->flash); i++) {
224
+ pflash_cfi01_legacy_drive(sms->flash[i],
225
+ drive_get(IF_PFLASH, 0, i));
226
+ }
117
+ }
227
+
118
+
228
+ sbsa_flash_map(sms, sysmem, secure_sysmem);
119
+DO_2SHIFT_N(VSHRNB, vshrnb)
229
+
120
+DO_2SHIFT_N(VSHRNT, vshrnt)
230
+ pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]);
121
+DO_2SHIFT_N(VRSHRNB, vrshrnb)
231
+
122
+DO_2SHIFT_N(VRSHRNT, vrshrnt)
232
+ if (bios_name) {
233
+ char *fname;
234
+ MemoryRegion *mr;
235
+ int image_size;
236
+
237
+ if (pflash_blk0) {
238
+ error_report("The contents of the first flash device may be "
239
+ "specified with -bios or with -drive if=pflash... "
240
+ "but you cannot use both options at once");
241
+ exit(1);
242
+ }
243
+
244
+ /* Fall back to -bios */
245
+
246
+ fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
247
+ if (!fname) {
248
+ error_report("Could not find ROM image '%s'", bios_name);
249
+ exit(1);
250
+ }
251
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0);
252
+ image_size = load_image_mr(fname, mr);
253
+ g_free(fname);
254
+ if (image_size < 0) {
255
+ error_report("Could not load ROM image '%s'", bios_name);
256
+ exit(1);
257
+ }
258
+ }
259
+
260
+ return pflash_blk0 || bios_name;
261
+}
262
+
263
+static void create_secure_ram(SBSAMachineState *sms,
264
+ MemoryRegion *secure_sysmem)
265
+{
266
+ MemoryRegion *secram = g_new(MemoryRegion, 1);
267
+ hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base;
268
+ hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size;
269
+
270
+ memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size,
271
+ &error_fatal);
272
+ memory_region_add_subregion(secure_sysmem, base, secram);
273
+}
274
+
275
+static void create_gic(SBSAMachineState *sms, qemu_irq *pic)
276
+{
277
+ DeviceState *gicdev;
278
+ SysBusDevice *gicbusdev;
279
+ const char *gictype;
280
+ uint32_t redist0_capacity, redist0_count;
281
+ int i;
282
+
283
+ gictype = gicv3_class_name();
284
+
285
+ gicdev = qdev_create(NULL, gictype);
286
+ qdev_prop_set_uint32(gicdev, "revision", 3);
287
+ qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
288
+ /*
289
+ * Note that the num-irq property counts both internal and external
290
+ * interrupts; there are always 32 of the former (mandated by GIC spec).
291
+ */
292
+ qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
293
+ qdev_prop_set_bit(gicdev, "has-security-extensions", true);
294
+
295
+ redist0_capacity =
296
+ sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
297
+ redist0_count = MIN(smp_cpus, redist0_capacity);
298
+
299
+ qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1);
300
+ qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count);
301
+
302
+ qdev_init_nofail(gicdev);
303
+ gicbusdev = SYS_BUS_DEVICE(gicdev);
304
+ sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
305
+ sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base);
306
+
307
+ /*
308
+ * Wire the outputs from each CPU's generic timer and the GICv3
309
+ * maintenance interrupt signal to the appropriate GIC PPI inputs,
310
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
311
+ */
312
+ for (i = 0; i < smp_cpus; i++) {
313
+ DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
314
+ int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
315
+ int irq;
316
+ /*
317
+ * Mapping from the output timer irq lines from the CPU to the
318
+ * GIC PPI inputs used for this board.
319
+ */
320
+ const int timer_irq[] = {
321
+ [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
322
+ [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
323
+ [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
324
+ [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
325
+ };
326
+
327
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
328
+ qdev_connect_gpio_out(cpudev, irq,
329
+ qdev_get_gpio_in(gicdev,
330
+ ppibase + timer_irq[irq]));
331
+ }
332
+
333
+ qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
334
+ qdev_get_gpio_in(gicdev, ppibase
335
+ + ARCH_GIC_MAINT_IRQ));
336
+ qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
337
+ qdev_get_gpio_in(gicdev, ppibase
338
+ + VIRTUAL_PMU_IRQ));
339
+
340
+ sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
341
+ sysbus_connect_irq(gicbusdev, i + smp_cpus,
342
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
343
+ sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
344
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
345
+ sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
346
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
347
+ }
348
+
349
+ for (i = 0; i < NUM_IRQS; i++) {
350
+ pic[i] = qdev_get_gpio_in(gicdev, i);
351
+ }
352
+}
353
+
354
+static void create_uart(const SBSAMachineState *sms, qemu_irq *pic, int uart,
355
+ MemoryRegion *mem, Chardev *chr)
356
+{
357
+ hwaddr base = sbsa_ref_memmap[uart].base;
358
+ int irq = sbsa_ref_irqmap[uart];
359
+ DeviceState *dev = qdev_create(NULL, "pl011");
360
+ SysBusDevice *s = SYS_BUS_DEVICE(dev);
361
+
362
+ qdev_prop_set_chr(dev, "chardev", chr);
363
+ qdev_init_nofail(dev);
364
+ memory_region_add_subregion(mem, base,
365
+ sysbus_mmio_get_region(s, 0));
366
+ sysbus_connect_irq(s, 0, pic[irq]);
367
+}
368
+
369
+static void create_rtc(const SBSAMachineState *sms, qemu_irq *pic)
370
+{
371
+ hwaddr base = sbsa_ref_memmap[SBSA_RTC].base;
372
+ int irq = sbsa_ref_irqmap[SBSA_RTC];
373
+
374
+ sysbus_create_simple("pl031", base, pic[irq]);
375
+}
376
+
377
+static DeviceState *gpio_key_dev;
378
+static void sbsa_ref_powerdown_req(Notifier *n, void *opaque)
379
+{
380
+ /* use gpio Pin 3 for power button event */
381
+ qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
382
+}
383
+
384
+static Notifier sbsa_ref_powerdown_notifier = {
385
+ .notify = sbsa_ref_powerdown_req
386
+};
387
+
388
+static void create_gpio(const SBSAMachineState *sms, qemu_irq *pic)
389
+{
390
+ DeviceState *pl061_dev;
391
+ hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base;
392
+ int irq = sbsa_ref_irqmap[SBSA_GPIO];
393
+
394
+ pl061_dev = sysbus_create_simple("pl061", base, pic[irq]);
395
+
396
+ gpio_key_dev = sysbus_create_simple("gpio-key", -1,
397
+ qdev_get_gpio_in(pl061_dev, 3));
398
+
399
+ /* connect powerdown request */
400
+ qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier);
401
+}
402
+
403
+static void create_ahci(const SBSAMachineState *sms, qemu_irq *pic)
404
+{
405
+ hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base;
406
+ int irq = sbsa_ref_irqmap[SBSA_AHCI];
407
+ DeviceState *dev;
408
+ DriveInfo *hd[NUM_SATA_PORTS];
409
+ SysbusAHCIState *sysahci;
410
+ AHCIState *ahci;
411
+ int i;
412
+
413
+ dev = qdev_create(NULL, "sysbus-ahci");
414
+ qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS);
415
+ qdev_init_nofail(dev);
416
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
417
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irq]);
418
+
419
+ sysahci = SYSBUS_AHCI(dev);
420
+ ahci = &sysahci->ahci;
421
+ ide_drive_get(hd, ARRAY_SIZE(hd));
422
+ for (i = 0; i < ahci->ports; i++) {
423
+ if (hd[i] == NULL) {
424
+ continue;
425
+ }
426
+ ide_create_drive(&ahci->dev[i].port, 0, hd[i]);
427
+ }
428
+}
429
+
430
+static void create_ehci(const SBSAMachineState *sms, qemu_irq *pic)
431
+{
432
+ hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base;
433
+ int irq = sbsa_ref_irqmap[SBSA_EHCI];
434
+
435
+ sysbus_create_simple("platform-ehci-usb", base, pic[irq]);
436
+}
437
+
438
+static void create_smmu(const SBSAMachineState *sms, qemu_irq *pic,
439
+ PCIBus *bus)
440
+{
441
+ hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base;
442
+ int irq = sbsa_ref_irqmap[SBSA_SMMU];
443
+ DeviceState *dev;
444
+ int i;
445
+
446
+ dev = qdev_create(NULL, "arm-smmuv3");
447
+
448
+ object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
449
+ &error_abort);
450
+ qdev_init_nofail(dev);
451
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
452
+ for (i = 0; i < NUM_SMMU_IRQS; i++) {
453
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
454
+ }
455
+}
456
+
457
+static void create_pcie(SBSAMachineState *sms, qemu_irq *pic)
458
+{
459
+ hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base;
460
+ hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size;
461
+ hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base;
462
+ hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size;
463
+ hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base;
464
+ hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size;
465
+ hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base;
466
+ int irq = sbsa_ref_irqmap[SBSA_PCIE];
467
+ MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg;
468
+ MemoryRegion *ecam_alias, *ecam_reg;
469
+ DeviceState *dev;
470
+ PCIHostState *pci;
471
+ int i;
472
+
473
+ dev = qdev_create(NULL, TYPE_GPEX_HOST);
474
+ qdev_init_nofail(dev);
475
+
476
+ /* Map ECAM space */
477
+ ecam_alias = g_new0(MemoryRegion, 1);
478
+ ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
479
+ memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
480
+ ecam_reg, 0, size_ecam);
481
+ memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
482
+
483
+ /* Map the MMIO space */
484
+ mmio_alias = g_new0(MemoryRegion, 1);
485
+ mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
486
+ memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
487
+ mmio_reg, base_mmio, size_mmio);
488
+ memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
489
+
490
+ /* Map the MMIO_HIGH space */
491
+ mmio_alias_high = g_new0(MemoryRegion, 1);
492
+ memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high",
493
+ mmio_reg, base_mmio_high, size_mmio_high);
494
+ memory_region_add_subregion(get_system_memory(), base_mmio_high,
495
+ mmio_alias_high);
496
+
497
+ /* Map IO port space */
498
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
499
+
500
+ for (i = 0; i < GPEX_NUM_IRQS; i++) {
501
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
502
+ gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
503
+ }
504
+
505
+ pci = PCI_HOST_BRIDGE(dev);
506
+ if (pci->bus) {
507
+ for (i = 0; i < nb_nics; i++) {
508
+ NICInfo *nd = &nd_table[i];
509
+
510
+ if (!nd->model) {
511
+ nd->model = g_strdup("e1000e");
512
+ }
513
+
514
+ pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
515
+ }
516
+ }
517
+
518
+ pci_create_simple(pci->bus, -1, "VGA");
519
+
520
+ create_smmu(sms, pic, pci->bus);
521
+}
522
+
523
+static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size)
524
+{
525
+ const SBSAMachineState *board = container_of(binfo, SBSAMachineState,
526
+ bootinfo);
527
+
528
+ *fdt_size = board->fdt_size;
529
+ return board->fdt;
530
+}
531
+
532
static void sbsa_ref_init(MachineState *machine)
533
{
534
SBSAMachineState *sms = SBSA_MACHINE(machine);
535
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
536
MemoryRegion *sysmem = get_system_memory();
537
MemoryRegion *secure_sysmem = NULL;
538
MemoryRegion *ram = g_new(MemoryRegion, 1);
539
+ bool firmware_loaded;
540
const CPUArchIdList *possible_cpus;
541
int n, sbsa_max_cpus;
542
+ qemu_irq pic[NUM_IRQS];
543
544
if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) {
545
error_report("sbsa-ref: CPU type other than the built-in "
546
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
547
exit(1);
548
}
549
550
+ /*
551
+ * The Secure view of the world is the same as the NonSecure,
552
+ * but with a few extra devices. Create it as a container region
553
+ * containing the system memory at low priority; any secure-only
554
+ * devices go in at higher priority and take precedence.
555
+ */
556
+ secure_sysmem = g_new(MemoryRegion, 1);
557
+ memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
558
+ UINT64_MAX);
559
+ memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
560
+
561
+ firmware_loaded = sbsa_firmware_init(sms, sysmem,
562
+ secure_sysmem ?: sysmem);
563
+
564
+ if (machine->kernel_filename && firmware_loaded) {
565
+ error_report("sbsa-ref: No fw_cfg device on this machine, "
566
+ "so -kernel option is not supported when firmware loaded, "
567
+ "please load OS from hard disk instead");
568
+ exit(1);
569
+ }
570
+
571
/*
572
* This machine has EL3 enabled, external firmware should supply PSCI
573
* implementation, so the QEMU's internal PSCI is disabled.
574
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
575
machine->ram_size);
576
memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, ram);
577
578
+ create_fdt(sms);
579
+
580
+ create_secure_ram(sms, secure_sysmem);
581
+
582
+ create_gic(sms, pic);
583
+
584
+ create_uart(sms, pic, SBSA_UART, sysmem, serial_hd(0));
585
+ create_uart(sms, pic, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
586
+ /* Second secure UART for RAS and MM from EL0 */
587
+ create_uart(sms, pic, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2));
588
+
589
+ create_rtc(sms, pic);
590
+
591
+ create_gpio(sms, pic);
592
+
593
+ create_ahci(sms, pic);
594
+
595
+ create_ehci(sms, pic);
596
+
597
+ create_pcie(sms, pic);
598
+
599
sms->bootinfo.ram_size = machine->ram_size;
600
sms->bootinfo.kernel_filename = machine->kernel_filename;
601
sms->bootinfo.nb_cpus = smp_cpus;
602
sms->bootinfo.board_id = -1;
603
sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base;
604
+ sms->bootinfo.get_dtb = sbsa_ref_dtb;
605
+ sms->bootinfo.firmware_loaded = firmware_loaded;
606
arm_load_kernel(ARM_CPU(first_cpu), &sms->bootinfo);
607
}
608
609
@@ -XXX,XX +XXX,XX @@ sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx)
610
return idx % nb_numa_nodes;
611
}
612
613
+static void sbsa_ref_instance_init(Object *obj)
614
+{
615
+ SBSAMachineState *sms = SBSA_MACHINE(obj);
616
+
617
+ sbsa_flash_create(sms);
618
+}
619
+
620
static void sbsa_ref_class_init(ObjectClass *oc, void *data)
621
{
622
MachineClass *mc = MACHINE_CLASS(oc);
623
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_class_init(ObjectClass *oc, void *data)
624
static const TypeInfo sbsa_ref_info = {
625
.name = TYPE_SBSA_MACHINE,
626
.parent = TYPE_MACHINE,
627
+ .instance_init = sbsa_ref_instance_init,
628
.class_init = sbsa_ref_class_init,
629
.instance_size = sizeof(SBSAMachineState),
630
};
631
--
123
--
632
2.20.1
124
2.20.1
633
125
634
126
diff view generated by jsdifflib
[Qemu-devel] [PULL 46/46] target/arm: Declare some M-profile functions publicly
[PULL 18/24] target/arm: Implement MVE saturating narrowing shifts
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Implement the MVE saturating shift-right-and-narrow insns
2
2
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
3
In the next commit we will split the M-profile functions from this
3
4
file. Some function will be called out of helper.c. Declare them in
4
do_srshr() is borrowed from sve_helper.c.
5
the "internals.h" header.
5
6
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190701132516.26392-22-philmd@redhat.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
11
---
9
---
12
target/arm/internals.h | 42 ++++++++++++++++++++++++++++++++++++++++++
10
target/arm/helper-mve.h | 30 +++++++++++
13
target/arm/helper.c | 38 ++------------------------------------
11
target/arm/mve.decode | 28 ++++++++++
14
2 files changed, 44 insertions(+), 36 deletions(-)
12
target/arm/mve_helper.c | 104 +++++++++++++++++++++++++++++++++++++
15
13
target/arm/translate-mve.c | 12 +++++
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
14
4 files changed, 174 insertions(+)
17
index XXXXXXX..XXXXXXX 100644
15
18
--- a/target/arm/internals.h
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
19
+++ b/target/arm/internals.h
17
index XXXXXXX..XXXXXXX 100644
20
@@ -XXX,XX +XXX,XX @@ static inline uint32_t v7m_sp_limit(CPUARMState *env)
18
--- a/target/arm/helper-mve.h
19
+++ b/target/arm/helper-mve.h
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
+
25
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+
30
+DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
+
35
+DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
+DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+
40
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+
45
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
46
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
47
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
48
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
49
+
50
+DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
51
+DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
52
+DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
53
+DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
54
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
55
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/mve.decode
57
+++ b/target/arm/mve.decode
58
@@ -XXX,XX +XXX,XX @@ VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
59
VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
60
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
61
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
62
+
63
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
64
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
65
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
66
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
67
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
68
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
69
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
70
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
71
+
72
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
73
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
74
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
75
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
76
+
77
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
78
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
79
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
80
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
81
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
82
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
83
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
84
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
85
+
86
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
87
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
88
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
89
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
90
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/arm/mve_helper.c
93
+++ b/target/arm/mve_helper.c
94
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
21
}
95
}
22
}
96
}
23
97
24
+/**
98
+static inline int64_t do_srshr(int64_t x, unsigned sh)
25
+ * v7m_cpacr_pass:
26
+ * Return true if the v7M CPACR permits access to the FPU for the specified
27
+ * security state and privilege level.
28
+ */
29
+static inline bool v7m_cpacr_pass(CPUARMState *env,
30
+ bool is_secure, bool is_priv)
31
+{
99
+{
32
+ switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {
100
+ if (likely(sh < 64)) {
33
+ case 0:
101
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
34
+ case 2: /* UNPREDICTABLE: we treat like 0 */
102
+ } else {
35
+ return false;
103
+ /* Rounding the sign bit always produces 0. */
36
+ case 1:
104
+ return 0;
37
+ return is_priv;
38
+ case 3:
39
+ return true;
40
+ default:
41
+ g_assert_not_reached();
42
+ }
105
+ }
43
+}
106
+}
44
+
107
+
45
/**
108
DO_VSHRN_ALL(vshrn, DO_SHR)
46
* aarch32_mode_name(): Return name of the AArch32 CPU mode
109
DO_VSHRN_ALL(vrshrn, do_urshr)
47
* @psr: Program Status Register indicating CPU mode
110
+
48
@@ -XXX,XX +XXX,XX @@ static inline int exception_target_el(CPUARMState *env)
111
+static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
49
112
+ bool *satp)
50
#ifndef CONFIG_USER_ONLY
113
+{
51
114
+ if (val > max) {
52
+/* Security attributes for an address, as returned by v8m_security_lookup. */
115
+ *satp = true;
53
+typedef struct V8M_SAttributes {
116
+ return max;
54
+ bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */
117
+ } else if (val < min) {
55
+ bool ns;
118
+ *satp = true;
56
+ bool nsc;
119
+ return min;
57
+ uint8_t sregion;
120
+ } else {
58
+ bool srvalid;
121
+ return val;
59
+ uint8_t iregion;
122
+ }
60
+ bool irvalid;
123
+}
61
+} V8M_SAttributes;
124
+
62
+
125
+/* Saturating narrowing right shifts */
63
+void v8m_security_lookup(CPUARMState *env, uint32_t address,
126
+#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
64
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
127
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
65
+ V8M_SAttributes *sattrs);
128
+ void *vm, uint32_t shift) \
66
+
129
+ { \
67
+bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
130
+ LTYPE *m = vm; \
68
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
131
+ TYPE *d = vd; \
69
+ hwaddr *phys_ptr, MemTxAttrs *txattrs,
132
+ uint16_t mask = mve_element_mask(env); \
70
+ int *prot, bool *is_subpage,
133
+ bool qc = false; \
71
+ ARMMMUFaultInfo *fi, uint32_t *mregion);
134
+ unsigned le; \
72
+
135
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
73
/* Cacheability and shareability attributes for a memory access */
136
+ bool sat = false; \
74
typedef struct ARMCacheAttrs {
137
+ TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \
75
unsigned int attrs:8; /* as in the MAIR register encoding */
138
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
76
diff --git a/target/arm/helper.c b/target/arm/helper.c
139
+ qc |= sat && (mask & 1 << (TOP * ESIZE)); \
77
index XXXXXXX..XXXXXXX 100644
140
+ } \
78
--- a/target/arm/helper.c
141
+ if (qc) { \
79
+++ b/target/arm/helper.c
142
+ env->vfp.qc[0] = qc; \
80
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
143
+ } \
81
hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
144
+ mve_advance_vpt(env); \
82
target_ulong *page_size_ptr,
145
+ }
83
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
146
+
84
-
147
+#define DO_VSHRN_SAT_UB(BOP, TOP, FN) \
85
-/* Security attributes for an address, as returned by v8m_security_lookup. */
148
+ DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \
86
-typedef struct V8M_SAttributes {
149
+ DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
87
- bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */
150
+
88
- bool ns;
151
+#define DO_VSHRN_SAT_UH(BOP, TOP, FN) \
89
- bool nsc;
152
+ DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \
90
- uint8_t sregion;
153
+ DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
91
- bool srvalid;
154
+
92
- uint8_t iregion;
155
+#define DO_VSHRN_SAT_SB(BOP, TOP, FN) \
93
- bool irvalid;
156
+ DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \
94
-} V8M_SAttributes;
157
+ DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
95
-
158
+
96
-static void v8m_security_lookup(CPUARMState *env, uint32_t address,
159
+#define DO_VSHRN_SAT_SH(BOP, TOP, FN) \
97
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
160
+ DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \
98
- V8M_SAttributes *sattrs);
161
+ DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
99
#endif
162
+
100
163
+#define DO_SHRN_SB(N, M, SATP) \
101
static void switch_mode(CPUARMState *env, int mode);
164
+ do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
102
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(int idx)
165
+#define DO_SHRN_UB(N, M, SATP) \
103
}
166
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
104
}
167
+#define DO_SHRUN_B(N, M, SATP) \
105
168
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
106
-/*
169
+
107
- * Return true if the v7M CPACR permits access to the FPU for the specified
170
+#define DO_SHRN_SH(N, M, SATP) \
108
- * security state and privilege level.
171
+ do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
109
- */
172
+#define DO_SHRN_UH(N, M, SATP) \
110
-static bool v7m_cpacr_pass(CPUARMState *env, bool is_secure, bool is_priv)
173
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
111
-{
174
+#define DO_SHRUN_H(N, M, SATP) \
112
- switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {
175
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
113
- case 0:
176
+
114
- case 2: /* UNPREDICTABLE: we treat like 0 */
177
+#define DO_RSHRN_SB(N, M, SATP) \
115
- return false;
178
+ do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
116
- case 1:
179
+#define DO_RSHRN_UB(N, M, SATP) \
117
- return is_priv;
180
+ do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
118
- case 3:
181
+#define DO_RSHRUN_B(N, M, SATP) \
119
- return true;
182
+ do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
120
- default:
183
+
121
- g_assert_not_reached();
184
+#define DO_RSHRN_SH(N, M, SATP) \
122
- }
185
+ do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
123
-}
186
+#define DO_RSHRN_UH(N, M, SATP) \
124
-
187
+ do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
125
/*
188
+#define DO_RSHRUN_H(N, M, SATP) \
126
* What kind of stack write are we doing? This affects how exceptions
189
+ do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
127
* generated during the stacking are treated.
190
+
128
@@ -XXX,XX +XXX,XX @@ static bool v8m_is_sau_exempt(CPUARMState *env,
191
+DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
129
(address >= 0xe00ff000 && address <= 0xe00fffff);
192
+DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
130
}
193
+DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
131
194
+DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
132
-static void v8m_security_lookup(CPUARMState *env, uint32_t address,
195
+DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
133
+void v8m_security_lookup(CPUARMState *env, uint32_t address,
196
+DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
134
MMUAccessType access_type, ARMMMUIdx mmu_idx,
197
+
135
V8M_SAttributes *sattrs)
198
+DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
136
{
199
+DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
137
@@ -XXX,XX +XXX,XX @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address,
200
+DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
138
}
201
+DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
139
}
202
+DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
140
203
+DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
141
-static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
204
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
142
+bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
205
index XXXXXXX..XXXXXXX 100644
143
MMUAccessType access_type, ARMMMUIdx mmu_idx,
206
--- a/target/arm/translate-mve.c
144
hwaddr *phys_ptr, MemTxAttrs *txattrs,
207
+++ b/target/arm/translate-mve.c
145
int *prot, bool *is_subpage,
208
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
209
DO_2SHIFT_N(VSHRNT, vshrnt)
210
DO_2SHIFT_N(VRSHRNB, vrshrnb)
211
DO_2SHIFT_N(VRSHRNT, vrshrnt)
212
+DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
213
+DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
214
+DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
215
+DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
216
+DO_2SHIFT_N(VQSHRUNB, vqshrunb)
217
+DO_2SHIFT_N(VQSHRUNT, vqshrunt)
218
+DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
219
+DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
220
+DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
221
+DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
222
+DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
223
+DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
146
--
224
--
147
2.20.1
225
2.20.1
148
226
149
227
diff view generated by jsdifflib
[Qemu-devel] [PULL 39/46] target/arm: Move TLB related routines to tlb_helper.c
[PULL 19/24] target/arm: Implement MVE VSHLC
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Implement the MVE VSHLC insn, which performs a shift left of the
2
entire vector with carry in bits provided from a general purpose
3
register and carry out bits written back to that register.
2
4
3
These routines are TCG specific.
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
The arm_deliver_fault() function is only used within the new
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
helper. Make it static.
7
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
8
---
9
target/arm/helper-mve.h | 2 ++
10
target/arm/mve.decode | 2 ++
11
target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++++++++++++
12
target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
13
4 files changed, 72 insertions(+)
6
14
7
Suggested-by: Alex Bennée <alex.bennee@linaro.org>
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190701132516.26392-13-philmd@redhat.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/Makefile.objs | 1 +
14
target/arm/internals.h | 3 -
15
target/arm/cpu.c | 6 +-
16
target/arm/helper.c | 53 -----------
17
target/arm/op_helper.c | 135 --------------------------
18
target/arm/tlb_helper.c | 200 +++++++++++++++++++++++++++++++++++++++
19
6 files changed, 205 insertions(+), 193 deletions(-)
20
create mode 100644 target/arm/tlb_helper.c
21
22
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
23
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/Makefile.objs
17
--- a/target/arm/helper-mve.h
25
+++ b/target/arm/Makefile.objs
18
+++ b/target/arm/helper-mve.h
26
@@ -XXX,XX +XXX,XX @@ target/arm/translate-sve.o: target/arm/decode-sve.inc.c
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
target/arm/translate.o: target/arm/decode-vfp.inc.c
20
DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
21
DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
22
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
+obj-y += tlb_helper.o
23
+
31
obj-y += translate.o op_helper.o
24
+DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
32
obj-y += crypto_helper.o
25
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
33
obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
34
diff --git a/target/arm/internals.h b/target/arm/internals.h
35
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/internals.h
27
--- a/target/arm/mve.decode
37
+++ b/target/arm/internals.h
28
+++ b/target/arm/mve.decode
38
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
29
@@ -XXX,XX +XXX,XX @@ VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
39
MMUAccessType access_type, int mmu_idx,
30
VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
40
bool probe, uintptr_t retaddr);
31
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
41
32
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
42
-void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type,
33
+
43
- int mmu_idx, ARMMMUFaultInfo *fi) QEMU_NORETURN;
34
+VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
44
-
35
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
45
/* Return true if the stage 1 translation regime is using LPAE format page
46
* tables */
47
bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
48
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
49
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/cpu.c
37
--- a/target/arm/mve_helper.c
51
+++ b/target/arm/cpu.c
38
+++ b/target/arm/mve_helper.c
52
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
39
@@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
53
cc->gdb_write_register = arm_cpu_gdb_write_register;
40
DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
54
#ifndef CONFIG_USER_ONLY
41
DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
55
cc->do_interrupt = arm_cpu_do_interrupt;
42
DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
56
- cc->do_unaligned_access = arm_cpu_do_unaligned_access;
57
- cc->do_transaction_failed = arm_cpu_do_transaction_failed;
58
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
59
cc->asidx_from_attrs = arm_asidx_from_attrs;
60
cc->vmsd = &vmstate_arm_cpu;
61
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
62
#ifdef CONFIG_TCG
63
cc->tcg_initialize = arm_translate_init;
64
cc->tlb_fill = arm_cpu_tlb_fill;
65
+#if !defined(CONFIG_USER_ONLY)
66
+ cc->do_unaligned_access = arm_cpu_do_unaligned_access;
67
+ cc->do_transaction_failed = arm_cpu_do_transaction_failed;
68
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
69
#endif
70
}
71
72
diff --git a/target/arm/helper.c b/target/arm/helper.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/target/arm/helper.c
75
+++ b/target/arm/helper.c
76
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
77
78
#endif
79
80
-bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
81
- MMUAccessType access_type, int mmu_idx,
82
- bool probe, uintptr_t retaddr)
83
-{
84
- ARMCPU *cpu = ARM_CPU(cs);
85
-
86
-#ifdef CONFIG_USER_ONLY
87
- cpu->env.exception.vaddress = address;
88
- if (access_type == MMU_INST_FETCH) {
89
- cs->exception_index = EXCP_PREFETCH_ABORT;
90
- } else {
91
- cs->exception_index = EXCP_DATA_ABORT;
92
- }
93
- cpu_loop_exit_restore(cs, retaddr);
94
-#else
95
- hwaddr phys_addr;
96
- target_ulong page_size;
97
- int prot, ret;
98
- MemTxAttrs attrs = {};
99
- ARMMMUFaultInfo fi = {};
100
-
101
- /*
102
- * Walk the page table and (if the mapping exists) add the page
103
- * to the TLB. On success, return true. Otherwise, if probing,
104
- * return false. Otherwise populate fsr with ARM DFSR/IFSR fault
105
- * register format, and signal the fault.
106
- */
107
- ret = get_phys_addr(&cpu->env, address, access_type,
108
- core_to_arm_mmu_idx(&cpu->env, mmu_idx),
109
- &phys_addr, &attrs, &prot, &page_size, &fi, NULL);
110
- if (likely(!ret)) {
111
- /*
112
- * Map a single [sub]page. Regions smaller than our declared
113
- * target page size are handled specially, so for those we
114
- * pass in the exact addresses.
115
- */
116
- if (page_size >= TARGET_PAGE_SIZE) {
117
- phys_addr &= TARGET_PAGE_MASK;
118
- address &= TARGET_PAGE_MASK;
119
- }
120
- tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
121
- prot, mmu_idx, page_size);
122
- return true;
123
- } else if (probe) {
124
- return false;
125
- } else {
126
- /* now we have a real cpu fault */
127
- cpu_restore_state(cs, retaddr, true);
128
- arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
129
- }
130
-#endif
131
-}
132
-
133
/* Note that signed overflow is undefined in C. The following routines are
134
careful to use unsigned types where modulo arithmetic is required.
135
Failure to do so _will_ break on newer gcc. */
136
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
137
index XXXXXXX..XXXXXXX 100644
138
--- a/target/arm/op_helper.c
139
+++ b/target/arm/op_helper.c
140
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn,
141
return val;
142
}
143
144
-#if !defined(CONFIG_USER_ONLY)
145
-
146
-static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
147
- unsigned int target_el,
148
- bool same_el, bool ea,
149
- bool s1ptw, bool is_write,
150
- int fsc)
151
-{
152
- uint32_t syn;
153
-
154
- /*
155
- * ISV is only set for data aborts routed to EL2 and
156
- * never for stage-1 page table walks faulting on stage 2.
157
- *
158
- * Furthermore, ISV is only set for certain kinds of load/stores.
159
- * If the template syndrome does not have ISV set, we should leave
160
- * it cleared.
161
- *
162
- * See ARMv8 specs, D7-1974:
163
- * ISS encoding for an exception from a Data Abort, the
164
- * ISV field.
165
- */
166
- if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) {
167
- syn = syn_data_abort_no_iss(same_el,
168
- ea, 0, s1ptw, is_write, fsc);
169
- } else {
170
- /*
171
- * Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
172
- * syndrome created at translation time.
173
- * Now we create the runtime syndrome with the remaining fields.
174
- */
175
- syn = syn_data_abort_with_iss(same_el,
176
- 0, 0, 0, 0, 0,
177
- ea, 0, s1ptw, is_write, fsc,
178
- false);
179
- /* Merge the runtime syndrome with the template syndrome. */
180
- syn |= template_syn;
181
- }
182
- return syn;
183
-}
184
-
185
-void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type,
186
- int mmu_idx, ARMMMUFaultInfo *fi)
187
-{
188
- CPUARMState *env = &cpu->env;
189
- int target_el;
190
- bool same_el;
191
- uint32_t syn, exc, fsr, fsc;
192
- ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
193
-
194
- target_el = exception_target_el(env);
195
- if (fi->stage2) {
196
- target_el = 2;
197
- env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
198
- }
199
- same_el = (arm_current_el(env) == target_el);
200
-
201
- if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
202
- arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
203
- /*
204
- * LPAE format fault status register : bottom 6 bits are
205
- * status code in the same form as needed for syndrome
206
- */
207
- fsr = arm_fi_to_lfsc(fi);
208
- fsc = extract32(fsr, 0, 6);
209
- } else {
210
- fsr = arm_fi_to_sfsc(fi);
211
- /*
212
- * Short format FSR : this fault will never actually be reported
213
- * to an EL that uses a syndrome register. Use a (currently)
214
- * reserved FSR code in case the constructed syndrome does leak
215
- * into the guest somehow.
216
- */
217
- fsc = 0x3f;
218
- }
219
-
220
- if (access_type == MMU_INST_FETCH) {
221
- syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc);
222
- exc = EXCP_PREFETCH_ABORT;
223
- } else {
224
- syn = merge_syn_data_abort(env->exception.syndrome, target_el,
225
- same_el, fi->ea, fi->s1ptw,
226
- access_type == MMU_DATA_STORE,
227
- fsc);
228
- if (access_type == MMU_DATA_STORE
229
- && arm_feature(env, ARM_FEATURE_V6)) {
230
- fsr |= (1 << 11);
231
- }
232
- exc = EXCP_DATA_ABORT;
233
- }
234
-
235
- env->exception.vaddress = addr;
236
- env->exception.fsr = fsr;
237
- raise_exception(env, exc, syn, target_el);
238
-}
239
-
240
-/* Raise a data fault alignment exception for the specified virtual address */
241
-void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
242
- MMUAccessType access_type,
243
- int mmu_idx, uintptr_t retaddr)
244
-{
245
- ARMCPU *cpu = ARM_CPU(cs);
246
- ARMMMUFaultInfo fi = {};
247
-
248
- /* now we have a real cpu fault */
249
- cpu_restore_state(cs, retaddr, true);
250
-
251
- fi.type = ARMFault_Alignment;
252
- arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
253
-}
254
-
255
-/*
256
- * arm_cpu_do_transaction_failed: handle a memory system error response
257
- * (eg "no device/memory present at address") by raising an external abort
258
- * exception
259
- */
260
-void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
261
- vaddr addr, unsigned size,
262
- MMUAccessType access_type,
263
- int mmu_idx, MemTxAttrs attrs,
264
- MemTxResult response, uintptr_t retaddr)
265
-{
266
- ARMCPU *cpu = ARM_CPU(cs);
267
- ARMMMUFaultInfo fi = {};
268
-
269
- /* now we have a real cpu fault */
270
- cpu_restore_state(cs, retaddr, true);
271
-
272
- fi.ea = arm_extabort_type(response);
273
- fi.type = ARMFault_SyncExternal;
274
- arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi);
275
-}
276
-
277
-#endif /* !defined(CONFIG_USER_ONLY) */
278
-
279
void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t newvalue)
280
{
281
/*
282
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
283
new file mode 100644
284
index XXXXXXX..XXXXXXX
285
--- /dev/null
286
+++ b/target/arm/tlb_helper.c
287
@@ -XXX,XX +XXX,XX @@
288
+/*
289
+ * ARM TLB (Translation lookaside buffer) helpers.
290
+ *
291
+ * This code is licensed under the GNU GPL v2 or later.
292
+ *
293
+ * SPDX-License-Identifier: GPL-2.0-or-later
294
+ */
295
+#include "qemu/osdep.h"
296
+#include "cpu.h"
297
+#include "internals.h"
298
+#include "exec/exec-all.h"
299
+
43
+
300
+#if !defined(CONFIG_USER_ONLY)
44
+uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
301
+
45
+ uint32_t shift)
302
+static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
303
+ unsigned int target_el,
304
+ bool same_el, bool ea,
305
+ bool s1ptw, bool is_write,
306
+ int fsc)
307
+{
46
+{
308
+ uint32_t syn;
47
+ uint32_t *d = vd;
48
+ uint16_t mask = mve_element_mask(env);
49
+ unsigned e;
50
+ uint32_t r;
309
+
51
+
310
+ /*
52
+ /*
311
+ * ISV is only set for data aborts routed to EL2 and
53
+ * For each 32-bit element, we shift it left, bringing in the
312
+ * never for stage-1 page table walks faulting on stage 2.
54
+ * low 'shift' bits of rdm at the bottom. Bits shifted out at
313
+ *
55
+ * the top become the new rdm, if the predicate mask permits.
314
+ * Furthermore, ISV is only set for certain kinds of load/stores.
56
+ * The final rdm value is returned to update the register.
315
+ * If the template syndrome does not have ISV set, we should leave
57
+ * shift == 0 here means "shift by 32 bits".
316
+ * it cleared.
317
+ *
318
+ * See ARMv8 specs, D7-1974:
319
+ * ISS encoding for an exception from a Data Abort, the
320
+ * ISV field.
321
+ */
58
+ */
322
+ if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) {
59
+ if (shift == 0) {
323
+ syn = syn_data_abort_no_iss(same_el,
60
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
324
+ ea, 0, s1ptw, is_write, fsc);
61
+ r = rdm;
62
+ if (mask & 1) {
63
+ rdm = d[H4(e)];
64
+ }
65
+ mergemask(&d[H4(e)], r, mask);
66
+ }
325
+ } else {
67
+ } else {
326
+ /*
68
+ uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
327
+ * Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
69
+
328
+ * syndrome created at translation time.
70
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
329
+ * Now we create the runtime syndrome with the remaining fields.
71
+ r = (d[H4(e)] << shift) | (rdm & shiftmask);
330
+ */
72
+ if (mask & 1) {
331
+ syn = syn_data_abort_with_iss(same_el,
73
+ rdm = d[H4(e)] >> (32 - shift);
332
+ 0, 0, 0, 0, 0,
74
+ }
333
+ ea, 0, s1ptw, is_write, fsc,
75
+ mergemask(&d[H4(e)], r, mask);
334
+ false);
76
+ }
335
+ /* Merge the runtime syndrome with the template syndrome. */
336
+ syn |= template_syn;
337
+ }
77
+ }
338
+ return syn;
78
+ mve_advance_vpt(env);
79
+ return rdm;
339
+}
80
+}
81
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/arm/translate-mve.c
84
+++ b/target/arm/translate-mve.c
85
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
86
DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
87
DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
88
DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
340
+
89
+
341
+static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
90
+static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
342
+ MMUAccessType access_type,
343
+ int mmu_idx, ARMMMUFaultInfo *fi)
344
+{
91
+{
345
+ CPUARMState *env = &cpu->env;
92
+ /*
346
+ int target_el;
93
+ * Whole Vector Left Shift with Carry. The carry is taken
347
+ bool same_el;
94
+ * from a general purpose register and written back there.
348
+ uint32_t syn, exc, fsr, fsc;
95
+ * An imm of 0 means "shift by 32".
349
+ ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
96
+ */
97
+ TCGv_ptr qd;
98
+ TCGv_i32 rdm;
350
+
99
+
351
+ target_el = exception_target_el(env);
100
+ if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
352
+ if (fi->stage2) {
101
+ return false;
353
+ target_el = 2;
354
+ env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
355
+ }
102
+ }
356
+ same_el = (arm_current_el(env) == target_el);
103
+ if (a->rdm == 13 || a->rdm == 15) {
357
+
104
+ /* CONSTRAINED UNPREDICTABLE: we UNDEF */
358
+ if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
105
+ return false;
359
+ arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
106
+ }
360
+ /*
107
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
361
+ * LPAE format fault status register : bottom 6 bits are
108
+ return true;
362
+ * status code in the same form as needed for syndrome
363
+ */
364
+ fsr = arm_fi_to_lfsc(fi);
365
+ fsc = extract32(fsr, 0, 6);
366
+ } else {
367
+ fsr = arm_fi_to_sfsc(fi);
368
+ /*
369
+ * Short format FSR : this fault will never actually be reported
370
+ * to an EL that uses a syndrome register. Use a (currently)
371
+ * reserved FSR code in case the constructed syndrome does leak
372
+ * into the guest somehow.
373
+ */
374
+ fsc = 0x3f;
375
+ }
109
+ }
376
+
110
+
377
+ if (access_type == MMU_INST_FETCH) {
111
+ qd = mve_qreg_ptr(a->qd);
378
+ syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc);
112
+ rdm = load_reg(s, a->rdm);
379
+ exc = EXCP_PREFETCH_ABORT;
113
+ gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
380
+ } else {
114
+ store_reg(s, a->rdm, rdm);
381
+ syn = merge_syn_data_abort(env->exception.syndrome, target_el,
115
+ tcg_temp_free_ptr(qd);
382
+ same_el, fi->ea, fi->s1ptw,
116
+ mve_update_eci(s);
383
+ access_type == MMU_DATA_STORE,
117
+ return true;
384
+ fsc);
385
+ if (access_type == MMU_DATA_STORE
386
+ && arm_feature(env, ARM_FEATURE_V6)) {
387
+ fsr |= (1 << 11);
388
+ }
389
+ exc = EXCP_DATA_ABORT;
390
+ }
391
+
392
+ env->exception.vaddress = addr;
393
+ env->exception.fsr = fsr;
394
+ raise_exception(env, exc, syn, target_el);
395
+}
396
+
397
+/* Raise a data fault alignment exception for the specified virtual address */
398
+void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
399
+ MMUAccessType access_type,
400
+ int mmu_idx, uintptr_t retaddr)
401
+{
402
+ ARMCPU *cpu = ARM_CPU(cs);
403
+ ARMMMUFaultInfo fi = {};
404
+
405
+ /* now we have a real cpu fault */
406
+ cpu_restore_state(cs, retaddr, true);
407
+
408
+ fi.type = ARMFault_Alignment;
409
+ arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
410
+}
411
+
412
+/*
413
+ * arm_cpu_do_transaction_failed: handle a memory system error response
414
+ * (eg "no device/memory present at address") by raising an external abort
415
+ * exception
416
+ */
417
+void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
418
+ vaddr addr, unsigned size,
419
+ MMUAccessType access_type,
420
+ int mmu_idx, MemTxAttrs attrs,
421
+ MemTxResult response, uintptr_t retaddr)
422
+{
423
+ ARMCPU *cpu = ARM_CPU(cs);
424
+ ARMMMUFaultInfo fi = {};
425
+
426
+ /* now we have a real cpu fault */
427
+ cpu_restore_state(cs, retaddr, true);
428
+
429
+ fi.ea = arm_extabort_type(response);
430
+ fi.type = ARMFault_SyncExternal;
431
+ arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi);
432
+}
433
+
434
+#endif /* !defined(CONFIG_USER_ONLY) */
435
+
436
+bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
437
+ MMUAccessType access_type, int mmu_idx,
438
+ bool probe, uintptr_t retaddr)
439
+{
440
+ ARMCPU *cpu = ARM_CPU(cs);
441
+
442
+#ifdef CONFIG_USER_ONLY
443
+ cpu->env.exception.vaddress = address;
444
+ if (access_type == MMU_INST_FETCH) {
445
+ cs->exception_index = EXCP_PREFETCH_ABORT;
446
+ } else {
447
+ cs->exception_index = EXCP_DATA_ABORT;
448
+ }
449
+ cpu_loop_exit_restore(cs, retaddr);
450
+#else
451
+ hwaddr phys_addr;
452
+ target_ulong page_size;
453
+ int prot, ret;
454
+ MemTxAttrs attrs = {};
455
+ ARMMMUFaultInfo fi = {};
456
+
457
+ /*
458
+ * Walk the page table and (if the mapping exists) add the page
459
+ * to the TLB. On success, return true. Otherwise, if probing,
460
+ * return false. Otherwise populate fsr with ARM DFSR/IFSR fault
461
+ * register format, and signal the fault.
462
+ */
463
+ ret = get_phys_addr(&cpu->env, address, access_type,
464
+ core_to_arm_mmu_idx(&cpu->env, mmu_idx),
465
+ &phys_addr, &attrs, &prot, &page_size, &fi, NULL);
466
+ if (likely(!ret)) {
467
+ /*
468
+ * Map a single [sub]page. Regions smaller than our declared
469
+ * target page size are handled specially, so for those we
470
+ * pass in the exact addresses.
471
+ */
472
+ if (page_size >= TARGET_PAGE_SIZE) {
473
+ phys_addr &= TARGET_PAGE_MASK;
474
+ address &= TARGET_PAGE_MASK;
475
+ }
476
+ tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
477
+ prot, mmu_idx, page_size);
478
+ return true;
479
+ } else if (probe) {
480
+ return false;
481
+ } else {
482
+ /* now we have a real cpu fault */
483
+ cpu_restore_state(cs, retaddr, true);
484
+ arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
485
+ }
486
+#endif
487
+}
118
+}
488
--
119
--
489
2.20.1
120
2.20.1
490
121
491
122
diff view generated by jsdifflib
[Qemu-devel] [PULL 41/46] target/arm/vfp_helper: Extract vfp_set_fpscr_to_host()
[PULL 20/24] target/arm: Implement MVE VADDLV
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Implement the MVE VADDLV insn; this is similar to VADDV, except
2
that it accumulates 32-bit elements into a 64-bit accumulator
3
stored in a pair of general-purpose registers.
2
4
3
The vfp_set_fpscr() helper contains code specific to the host
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
floating point implementation (here the SoftFloat library).
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Extract this code to vfp_set_fpscr_to_host().
7
Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
8
---
9
target/arm/helper-mve.h | 3 ++
10
target/arm/mve.decode | 6 +++-
11
target/arm/mve_helper.c | 19 ++++++++++++
12
target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
13
4 files changed, 90 insertions(+), 1 deletion(-)
6
14
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
8
Message-id: 20190701132516.26392-16-philmd@redhat.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/vfp_helper.c | 127 +++++++++++++++++++++-------------------
13
1 file changed, 66 insertions(+), 61 deletions(-)
14
15
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/vfp_helper.c
17
--- a/target/arm/helper-mve.h
18
+++ b/target/arm/vfp_helper.c
18
+++ b/target/arm/helper-mve.h
19
@@ -XXX,XX +XXX,XX @@ static inline int vfp_exceptbits_to_host(int target_bits)
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
20
return host_bits;
20
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
21
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
23
+DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)
24
+DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)
25
+
26
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
27
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
28
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
29
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/mve.decode
32
+++ b/target/arm/mve.decode
33
@@ -XXX,XX +XXX,XX @@ VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
34
VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
35
36
# Vector add across vector
37
-VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
38
+{
39
+ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
40
+ VADDLV 111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \
41
+ rdahi=%rdahi rdalo=%rdalo
42
+}
43
44
# Predicate operations
45
%mask_22_13 22:1 13:3
46
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/mve_helper.c
49
+++ b/target/arm/mve_helper.c
50
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t)
51
DO_VADDV(vaddvuh, 2, uint16_t)
52
DO_VADDV(vaddvuw, 4, uint32_t)
53
54
+#define DO_VADDLV(OP, TYPE, LTYPE) \
55
+ uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
56
+ uint64_t ra) \
57
+ { \
58
+ uint16_t mask = mve_element_mask(env); \
59
+ unsigned e; \
60
+ TYPE *m = vm; \
61
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
62
+ if (mask & 1) { \
63
+ ra += (LTYPE)m[H4(e)]; \
64
+ } \
65
+ } \
66
+ mve_advance_vpt(env); \
67
+ return ra; \
68
+ } \
69
+
70
+DO_VADDLV(vaddlv_s, int32_t, int64_t)
71
+DO_VADDLV(vaddlv_u, uint32_t, uint64_t)
72
+
73
/* Shifts by immediate */
74
#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
75
void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
76
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/translate-mve.c
79
+++ b/target/arm/translate-mve.c
80
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
81
return true;
21
}
82
}
22
83
23
-uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
84
+static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
24
-{
25
- uint32_t i, fpscr;
26
-
27
- fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
28
- | (env->vfp.vec_len << 16)
29
- | (env->vfp.vec_stride << 20);
30
-
31
- i = get_float_exception_flags(&env->vfp.fp_status);
32
- i |= get_float_exception_flags(&env->vfp.standard_fp_status);
33
- /* FZ16 does not generate an input denormal exception. */
34
- i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
35
- & ~float_flag_input_denormal);
36
- fpscr |= vfp_exceptbits_from_host(i);
37
-
38
- i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
39
- fpscr |= i ? FPCR_QC : 0;
40
-
41
- return fpscr;
42
-}
43
-
44
-uint32_t vfp_get_fpscr(CPUARMState *env)
45
-{
46
- return HELPER(vfp_get_fpscr)(env);
47
-}
48
-
49
-void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
50
+static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
51
{
52
int i;
53
uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];
54
55
- /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
56
- if (!cpu_isar_feature(aa64_fp16, env_archcpu(env))) {
57
- val &= ~FPCR_FZ16;
58
- }
59
-
60
- if (arm_feature(env, ARM_FEATURE_M)) {
61
- /*
62
- * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
63
- * and also for the trapped-exception-handling bits IxE.
64
- */
65
- val &= 0xf7c0009f;
66
- }
67
-
68
- /*
69
- * We don't implement trapped exception handling, so the
70
- * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
71
- *
72
- * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC
73
- * (which are stored in fp_status), and the other RES0 bits
74
- * in between, then we clear all of the low 16 bits.
75
- */
76
- env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
77
- env->vfp.vec_len = (val >> 16) & 7;
78
- env->vfp.vec_stride = (val >> 20) & 3;
79
-
80
- /*
81
- * The bit we set within fpscr_q is arbitrary; the register as a
82
- * whole being zero/non-zero is what counts.
83
- */
84
- env->vfp.qc[0] = val & FPCR_QC;
85
- env->vfp.qc[1] = 0;
86
- env->vfp.qc[2] = 0;
87
- env->vfp.qc[3] = 0;
88
-
89
changed ^= val;
90
if (changed & (3 << 22)) {
91
i = (val >> 22) & 3;
92
@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
93
set_float_exception_flags(0, &env->vfp.standard_fp_status);
94
}
95
96
+uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
97
+{
85
+{
98
+ uint32_t i, fpscr;
86
+ /*
87
+ * Vector Add Long Across Vector: accumulate the 32-bit
88
+ * elements of the vector into a 64-bit result stored in
89
+ * a pair of general-purpose registers.
90
+ * No need to check Qm's bank: it is only 3 bits in decode.
91
+ */
92
+ TCGv_ptr qm;
93
+ TCGv_i64 rda;
94
+ TCGv_i32 rdalo, rdahi;
99
+
95
+
100
+ fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
96
+ if (!dc_isar_feature(aa32_mve, s)) {
101
+ | (env->vfp.vec_len << 16)
97
+ return false;
102
+ | (env->vfp.vec_stride << 20);
103
+
104
+ i = get_float_exception_flags(&env->vfp.fp_status);
105
+ i |= get_float_exception_flags(&env->vfp.standard_fp_status);
106
+ /* FZ16 does not generate an input denormal exception. */
107
+ i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
108
+ & ~float_flag_input_denormal);
109
+ fpscr |= vfp_exceptbits_from_host(i);
110
+
111
+ i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
112
+ fpscr |= i ? FPCR_QC : 0;
113
+
114
+ return fpscr;
115
+}
116
+
117
+uint32_t vfp_get_fpscr(CPUARMState *env)
118
+{
119
+ return HELPER(vfp_get_fpscr)(env);
120
+}
121
+
122
+void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
123
+{
124
+ /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
125
+ if (!cpu_isar_feature(aa64_fp16, env_archcpu(env))) {
126
+ val &= ~FPCR_FZ16;
127
+ }
98
+ }
128
+
99
+ /*
129
+ if (arm_feature(env, ARM_FEATURE_M)) {
100
+ * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
130
+ /*
101
+ * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
131
+ * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
102
+ */
132
+ * and also for the trapped-exception-handling bits IxE.
103
+ if (a->rdahi == 13 || a->rdahi == 15) {
133
+ */
104
+ return false;
134
+ val &= 0xf7c0009f;
105
+ }
106
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
107
+ return true;
135
+ }
108
+ }
136
+
109
+
137
+ /*
110
+ /*
138
+ * We don't implement trapped exception handling, so the
111
+ * This insn is subject to beat-wise execution. Partial execution
139
+ * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
112
+ * of an A=0 (no-accumulate) insn which does not execute the first
140
+ *
113
+ * beat must start with the current value of RdaHi:RdaLo, not zero.
141
+ * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC
142
+ * (which are stored in fp_status), and the other RES0 bits
143
+ * in between, then we clear all of the low 16 bits.
144
+ */
114
+ */
145
+ env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
115
+ if (a->a || mve_skip_first_beat(s)) {
146
+ env->vfp.vec_len = (val >> 16) & 7;
116
+ /* Accumulate input from RdaHi:RdaLo */
147
+ env->vfp.vec_stride = (val >> 20) & 3;
117
+ rda = tcg_temp_new_i64();
118
+ rdalo = load_reg(s, a->rdalo);
119
+ rdahi = load_reg(s, a->rdahi);
120
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
121
+ tcg_temp_free_i32(rdalo);
122
+ tcg_temp_free_i32(rdahi);
123
+ } else {
124
+ /* Accumulate starting at zero */
125
+ rda = tcg_const_i64(0);
126
+ }
148
+
127
+
149
+ /*
128
+ qm = mve_qreg_ptr(a->qm);
150
+ * The bit we set within fpscr_q is arbitrary; the register as a
129
+ if (a->u) {
151
+ * whole being zero/non-zero is what counts.
130
+ gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
152
+ */
131
+ } else {
153
+ env->vfp.qc[0] = val & FPCR_QC;
132
+ gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
154
+ env->vfp.qc[1] = 0;
133
+ }
155
+ env->vfp.qc[2] = 0;
134
+ tcg_temp_free_ptr(qm);
156
+ env->vfp.qc[3] = 0;
157
+
135
+
158
+ vfp_set_fpscr_to_host(env, val);
136
+ rdalo = tcg_temp_new_i32();
137
+ rdahi = tcg_temp_new_i32();
138
+ tcg_gen_extrl_i64_i32(rdalo, rda);
139
+ tcg_gen_extrh_i64_i32(rdahi, rda);
140
+ store_reg(s, a->rdalo, rdalo);
141
+ store_reg(s, a->rdahi, rdahi);
142
+ tcg_temp_free_i64(rda);
143
+ mve_update_eci(s);
144
+ return true;
159
+}
145
+}
160
+
146
+
161
void vfp_set_fpscr(CPUARMState *env, uint32_t val)
147
static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
162
{
148
{
163
HELPER(vfp_set_fpscr)(env, val);
149
TCGv_ptr qd;
164
--
150
--
165
2.20.1
151
2.20.1
166
152
167
153
diff view generated by jsdifflib
[Qemu-devel] [PULL 45/46] target/arm: Declare arm_log_exception() function publicly
[PULL 21/24] target/arm: Implement MVE long shifts by immediate
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
The MVE extension to v8.1M includes some new shift instructions which
2
2
sit entirely within the non-coprocessor part of the encoding space
3
In few commits we will split the M-profile functions from this
3
and which operate only on general-purpose registers. They take up
4
file, and this function will also be called in the new file.
4
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
5
Declare it in the "internals.h" header.
5
with Rm == 13 or 15.
6
Since it is in the middle of a block of M profile functions,
6
7
move it previous to this block to ease the later refactor.
7
Implement the long shifts by immediate, which perform shifts on a
8
8
pair of general-purpose registers treated as a 64-bit quantity, with
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
an immediate shift count between 1 and 32.
10
Message-id: 20190701132516.26392-21-philmd@redhat.com
10
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
12
the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
13
cases where v8.1M now requires that. (Trying to change MOVS and ORRS
14
is too difficult, because the functions that generate the code are
15
shared between a dozen different kinds of arithmetic or logical
16
instruction for all A32, T16 and T32 encodings, and for some insns
17
and some encodings Rm==13,15 are valid.)
18
19
We make the helper functions we need for UQSHLL and SQSHLL take
20
a 32-bit value which the helper casts to int8_t because we'll need
21
these helpers also for the shift-by-register insns, where the shift
22
count might be < 0 or > 32.
23
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
13
---
27
---
14
target/arm/internals.h | 2 ++
28
target/arm/helper-mve.h | 3 ++
15
target/arm/helper.c | 76 +++++++++++++++++++++---------------------
29
target/arm/translate.h | 1 +
16
2 files changed, 40 insertions(+), 38 deletions(-)
30
target/arm/t32.decode | 28 +++++++++++++
17
31
target/arm/mve_helper.c | 10 +++++
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
32
target/arm/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++
19
index XXXXXXX..XXXXXXX 100644
33
5 files changed, 132 insertions(+)
20
--- a/target/arm/internals.h
34
21
+++ b/target/arm/internals.h
35
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
22
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
36
index XXXXXXX..XXXXXXX 100644
23
target_ulong *page_size,
37
--- a/target/arm/helper-mve.h
24
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
38
+++ b/target/arm/helper-mve.h
25
39
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+void arm_log_exception(int idx);
40
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+
41
28
#endif /* !CONFIG_USER_ONLY */
42
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
29
43
+
30
#endif
44
+DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
31
diff --git a/target/arm/helper.c b/target/arm/helper.c
45
+DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
32
index XXXXXXX..XXXXXXX 100644
46
diff --git a/target/arm/translate.h b/target/arm/translate.h
33
--- a/target/arm/helper.c
47
index XXXXXXX..XXXXXXX 100644
34
+++ b/target/arm/helper.c
48
--- a/target/arm/translate.h
35
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
49
+++ b/target/arm/translate.h
36
return target_el;
50
@@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
37
}
51
typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
38
52
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
39
+void arm_log_exception(int idx)
53
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
40
+{
54
+typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
41
+ if (qemu_loglevel_mask(CPU_LOG_INT)) {
55
42
+ const char *exc = NULL;
56
/**
43
+ static const char * const excnames[] = {
57
* arm_tbflags_from_tb:
44
+ [EXCP_UDEF] = "Undefined Instruction",
58
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
45
+ [EXCP_SWI] = "SVC",
59
index XXXXXXX..XXXXXXX 100644
46
+ [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
60
--- a/target/arm/t32.decode
47
+ [EXCP_DATA_ABORT] = "Data Abort",
61
+++ b/target/arm/t32.decode
48
+ [EXCP_IRQ] = "IRQ",
62
@@ -XXX,XX +XXX,XX @@
49
+ [EXCP_FIQ] = "FIQ",
63
&mcr !extern cp opc1 crn crm opc2 rt
50
+ [EXCP_BKPT] = "Breakpoint",
64
&mcrr !extern cp opc1 crm rt rt2
51
+ [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
65
52
+ [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
66
+&mve_shl_ri rdalo rdahi shim
53
+ [EXCP_HVC] = "Hypervisor Call",
67
+
54
+ [EXCP_HYP_TRAP] = "Hypervisor Trap",
68
+# rdahi: bits [3:1] from insn, bit 0 is 1
55
+ [EXCP_SMC] = "Secure Monitor Call",
69
+# rdalo: bits [3:1] from insn, bit 0 is 0
56
+ [EXCP_VIRQ] = "Virtual IRQ",
70
+%rdahi_9 9:3 !function=times_2_plus_1
57
+ [EXCP_VFIQ] = "Virtual FIQ",
71
+%rdalo_17 17:3 !function=times_2
58
+ [EXCP_SEMIHOST] = "Semihosting call",
72
+
59
+ [EXCP_NOCP] = "v7M NOCP UsageFault",
73
# Data-processing (register)
60
+ [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
74
61
+ [EXCP_STKOF] = "v8M STKOF UsageFault",
75
%imm5_12_6 12:3 6:2
62
+ [EXCP_LAZYFP] = "v7M exception during lazy FP stacking",
76
@@ -XXX,XX +XXX,XX @@
63
+ [EXCP_LSERR] = "v8M LSERR UsageFault",
77
@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
64
+ [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
78
&s_rrr_shi shim=%imm5_12_6 s=1 rd=0
65
+ };
79
66
+
80
+@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
67
+ if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
81
+ &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
68
+ exc = excnames[idx];
82
+
69
+ }
83
{
70
+ if (!exc) {
84
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
71
+ exc = "unknown";
85
AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi
72
+ }
86
}
73
+ qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
87
BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
74
+ }
88
{
89
+ # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
90
+ # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE
91
+ # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that
92
+ # they explicitly call unallocated_encoding() for cases that must UNDEF
93
+ # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting
94
+ # the rest fall through (where ORR_rrri and MOV_rxri will end up
95
+ # handling them as r13 and r15 accesses with the same semantics as A32).
96
+ [
97
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
98
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
99
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
100
+
101
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
102
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
103
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
104
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
105
+ ]
106
+
107
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
108
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
109
}
110
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
111
index XXXXXXX..XXXXXXX 100644
112
--- a/target/arm/mve_helper.c
113
+++ b/target/arm/mve_helper.c
114
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
115
mve_advance_vpt(env);
116
return rdm;
117
}
118
+
119
+uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
120
+{
121
+ return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
122
+}
123
+
124
+uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
125
+{
126
+ return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
+}
128
diff --git a/target/arm/translate.c b/target/arm/translate.c
129
index XXXXXXX..XXXXXXX 100644
130
--- a/target/arm/translate.c
131
+++ b/target/arm/translate.c
132
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
133
return true;
134
}
135
136
+/*
137
+ * v8.1M MVE wide-shifts
138
+ */
139
+static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a,
140
+ WideShiftImmFn *fn)
141
+{
142
+ TCGv_i64 rda;
143
+ TCGv_i32 rdalo, rdahi;
144
+
145
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
146
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
147
+ return false;
148
+ }
149
+ if (a->rdahi == 15) {
150
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
151
+ return false;
152
+ }
153
+ if (!dc_isar_feature(aa32_mve, s) ||
154
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
155
+ a->rdahi == 13) {
156
+ /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */
157
+ unallocated_encoding(s);
158
+ return true;
159
+ }
160
+
161
+ if (a->shim == 0) {
162
+ a->shim = 32;
163
+ }
164
+
165
+ rda = tcg_temp_new_i64();
166
+ rdalo = load_reg(s, a->rdalo);
167
+ rdahi = load_reg(s, a->rdahi);
168
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
169
+
170
+ fn(rda, rda, a->shim);
171
+
172
+ tcg_gen_extrl_i64_i32(rdalo, rda);
173
+ tcg_gen_extrh_i64_i32(rdahi, rda);
174
+ store_reg(s, a->rdalo, rdalo);
175
+ store_reg(s, a->rdahi, rdahi);
176
+ tcg_temp_free_i64(rda);
177
+
178
+ return true;
179
+}
180
+
181
+static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a)
182
+{
183
+ return do_mve_shl_ri(s, a, tcg_gen_sari_i64);
184
+}
185
+
186
+static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a)
187
+{
188
+ return do_mve_shl_ri(s, a, tcg_gen_shli_i64);
189
+}
190
+
191
+static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)
192
+{
193
+ return do_mve_shl_ri(s, a, tcg_gen_shri_i64);
194
+}
195
+
196
+static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
197
+{
198
+ gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));
199
+}
200
+
201
+static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
202
+{
203
+ return do_mve_shl_ri(s, a, gen_mve_sqshll);
204
+}
205
+
206
+static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
207
+{
208
+ gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));
209
+}
210
+
211
+static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
212
+{
213
+ return do_mve_shl_ri(s, a, gen_mve_uqshll);
214
+}
215
+
216
+static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
217
+{
218
+ return do_mve_shl_ri(s, a, gen_srshr64_i64);
219
+}
220
+
221
+static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
222
+{
223
+ return do_mve_shl_ri(s, a, gen_urshr64_i64);
75
+}
224
+}
76
+
225
+
77
/*
226
/*
78
* Return true if the v7M CPACR permits access to the FPU for the specified
227
* Multiply and multiply accumulate
79
* security state and privilege level.
228
*/
80
@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
81
return true;
82
}
83
84
-static void arm_log_exception(int idx)
85
-{
86
- if (qemu_loglevel_mask(CPU_LOG_INT)) {
87
- const char *exc = NULL;
88
- static const char * const excnames[] = {
89
- [EXCP_UDEF] = "Undefined Instruction",
90
- [EXCP_SWI] = "SVC",
91
- [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
92
- [EXCP_DATA_ABORT] = "Data Abort",
93
- [EXCP_IRQ] = "IRQ",
94
- [EXCP_FIQ] = "FIQ",
95
- [EXCP_BKPT] = "Breakpoint",
96
- [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
97
- [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
98
- [EXCP_HVC] = "Hypervisor Call",
99
- [EXCP_HYP_TRAP] = "Hypervisor Trap",
100
- [EXCP_SMC] = "Secure Monitor Call",
101
- [EXCP_VIRQ] = "Virtual IRQ",
102
- [EXCP_VFIQ] = "Virtual FIQ",
103
- [EXCP_SEMIHOST] = "Semihosting call",
104
- [EXCP_NOCP] = "v7M NOCP UsageFault",
105
- [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
106
- [EXCP_STKOF] = "v8M STKOF UsageFault",
107
- [EXCP_LAZYFP] = "v7M exception during lazy FP stacking",
108
- [EXCP_LSERR] = "v8M LSERR UsageFault",
109
- [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
110
- };
111
-
112
- if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
113
- exc = excnames[idx];
114
- }
115
- if (!exc) {
116
- exc = "unknown";
117
- }
118
- qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
119
- }
120
-}
121
-
122
static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
123
uint32_t addr, uint16_t *insn)
124
{
125
--
229
--
126
2.20.1
230
2.20.1
127
231
128
232
diff view generated by jsdifflib
[Qemu-devel] [PULL 35/46] target/arm: Fix coding style issues
[PULL 22/24] target/arm: Implement MVE long shifts by register
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Implement the MVE long shifts by register, which perform shifts on a
2
2
pair of general-purpose registers treated as a 64-bit quantity, with
3
Since we'll move this code around, fix its style first.
3
the shift count in another general-purpose register, which might be
4
4
either positive or negative.
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Like the long-shifts-by-immediate, these encodings sit in the space
7
Message-id: 20190701132516.26392-9-philmd@redhat.com
7
that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
8
Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
9
also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
10
we have to move the CSEL pattern into the same decodetree group.
11
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
9
---
15
---
10
target/arm/translate.c | 11 ++++++-----
16
target/arm/helper-mve.h | 6 +++
11
target/arm/vfp_helper.c | 36 ++++++++++++++++++++++++------------
17
target/arm/translate.h | 1 +
12
2 files changed, 30 insertions(+), 17 deletions(-)
18
target/arm/t32.decode | 16 +++++--
13
19
target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
20
target/arm/translate.c | 69 ++++++++++++++++++++++++++++++
21
5 files changed, 182 insertions(+), 3 deletions(-)
22
23
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/helper-mve.h
26
+++ b/target/arm/helper-mve.h
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
29
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
30
31
+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
32
+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
33
DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
34
DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
35
+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
36
+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
37
+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
38
+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
39
diff --git a/target/arm/translate.h b/target/arm/translate.h
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/translate.h
42
+++ b/target/arm/translate.h
43
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
44
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
45
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
46
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
47
+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
48
49
/**
50
* arm_tbflags_from_tb:
51
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/t32.decode
54
+++ b/target/arm/t32.decode
55
@@ -XXX,XX +XXX,XX @@
56
&mcrr !extern cp opc1 crm rt rt2
57
58
&mve_shl_ri rdalo rdahi shim
59
+&mve_shl_rr rdalo rdahi rm
60
61
# rdahi: bits [3:1] from insn, bit 0 is 1
62
# rdalo: bits [3:1] from insn, bit 0 is 0
63
@@ -XXX,XX +XXX,XX @@
64
65
@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
66
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
67
+@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
68
+ &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
69
70
{
71
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
72
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
73
URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
74
SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
75
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
76
+
77
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
78
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
79
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
80
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
81
+ UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
82
+ SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
83
]
84
85
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
86
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
87
+
88
+ # v8.1M CSEL and friends
89
+ CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
90
}
91
{
92
MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi
93
@@ -XXX,XX +XXX,XX @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi
94
}
95
RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi
96
97
-# v8.1M CSEL and friends
98
-CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
99
-
100
# Data-processing (register-shifted register)
101
102
MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
103
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/target/arm/mve_helper.c
106
+++ b/target/arm/mve_helper.c
107
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
108
return rdm;
109
}
110
111
+uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
112
+{
113
+ return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
114
+}
115
+
116
+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
117
+{
118
+ return do_uqrshl_d(n, (int8_t)shift, false, NULL);
119
+}
120
+
121
uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
122
{
123
return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
124
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
125
{
126
return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
}
128
+
129
+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
130
+{
131
+ return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
132
+}
133
+
134
+uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
135
+{
136
+ return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
137
+}
138
+
139
+/* Operate on 64-bit values, but saturate at 48 bits */
140
+static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
141
+ bool round, uint32_t *sat)
142
+{
143
+ if (shift <= -48) {
144
+ /* Rounding the sign bit always produces 0. */
145
+ if (round) {
146
+ return 0;
147
+ }
148
+ return src >> 63;
149
+ } else if (shift < 0) {
150
+ if (round) {
151
+ src >>= -shift - 1;
152
+ return (src >> 1) + (src & 1);
153
+ }
154
+ return src >> -shift;
155
+ } else if (shift < 48) {
156
+ int64_t val = src << shift;
157
+ int64_t extval = sextract64(val, 0, 48);
158
+ if (!sat || val == extval) {
159
+ return extval;
160
+ }
161
+ } else if (!sat || src == 0) {
162
+ return 0;
163
+ }
164
+
165
+ *sat = 1;
166
+ return (1ULL << 47) - (src >= 0);
167
+}
168
+
169
+/* Operate on 64-bit values, but saturate at 48 bits */
170
+static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
171
+ bool round, uint32_t *sat)
172
+{
173
+ uint64_t val, extval;
174
+
175
+ if (shift <= -(48 + round)) {
176
+ return 0;
177
+ } else if (shift < 0) {
178
+ if (round) {
179
+ val = src >> (-shift - 1);
180
+ val = (val >> 1) + (val & 1);
181
+ } else {
182
+ val = src >> -shift;
183
+ }
184
+ extval = extract64(val, 0, 48);
185
+ if (!sat || val == extval) {
186
+ return extval;
187
+ }
188
+ } else if (shift < 48) {
189
+ uint64_t val = src << shift;
190
+ uint64_t extval = extract64(val, 0, 48);
191
+ if (!sat || val == extval) {
192
+ return extval;
193
+ }
194
+ } else if (!sat || src == 0) {
195
+ return 0;
196
+ }
197
+
198
+ *sat = 1;
199
+ return MAKE_64BIT_MASK(0, 48);
200
+}
201
+
202
+uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
203
+{
204
+ return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
205
+}
206
+
207
+uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
208
+{
209
+ return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
210
+}
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
211
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
index XXXXXXX..XXXXXXX 100644
212
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
213
--- a/target/arm/translate.c
17
+++ b/target/arm/translate.c
214
+++ b/target/arm/translate.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
215
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
19
loaded_base = 0;
216
return do_mve_shl_ri(s, a, gen_urshr64_i64);
20
loaded_var = NULL;
217
}
21
n = 0;
218
22
- for(i=0;i<16;i++) {
219
+static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
23
+ for (i = 0; i < 16; i++) {
220
+{
24
if (insn & (1 << i))
221
+ TCGv_i64 rda;
25
n++;
222
+ TCGv_i32 rdalo, rdahi;
26
}
223
+
27
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
224
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
28
}
225
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
29
}
226
+ return false;
30
j = 0;
227
+ }
31
- for(i=0;i<16;i++) {
228
+ if (a->rdahi == 15) {
32
+ for (i = 0; i < 16; i++) {
229
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
33
if (insn & (1 << i)) {
230
+ return false;
34
if (is_load) {
231
+ }
35
/* load */
232
+ if (!dc_isar_feature(aa32_mve, s) ||
36
@@ -XXX,XX +XXX,XX @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
233
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
37
return;
234
+ a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
38
}
235
+ a->rm == a->rdahi || a->rm == a->rdalo) {
39
236
+ /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
40
- for(i=0;i<16;i++) {
237
+ unallocated_encoding(s);
41
+ for (i = 0; i < 16; i++) {
238
+ return true;
42
qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
239
+ }
43
- if ((i % 4) == 3)
240
+
44
+ if ((i % 4) == 3) {
241
+ rda = tcg_temp_new_i64();
45
qemu_fprintf(f, "\n");
242
+ rdalo = load_reg(s, a->rdalo);
46
- else
243
+ rdahi = load_reg(s, a->rdahi);
47
+ } else {
244
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
48
qemu_fprintf(f, " ");
245
+
49
+ }
246
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
50
}
247
+ fn(rda, cpu_env, rda, cpu_R[a->rm]);
51
248
+
52
if (arm_feature(env, ARM_FEATURE_M)) {
249
+ tcg_gen_extrl_i64_i32(rdalo, rda);
53
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
250
+ tcg_gen_extrh_i64_i32(rdahi, rda);
54
index XXXXXXX..XXXXXXX 100644
251
+ store_reg(s, a->rdalo, rdalo);
55
--- a/target/arm/vfp_helper.c
252
+ store_reg(s, a->rdahi, rdahi);
56
+++ b/target/arm/vfp_helper.c
253
+ tcg_temp_free_i64(rda);
57
@@ -XXX,XX +XXX,XX @@ static inline int vfp_exceptbits_from_host(int host_bits)
254
+
58
{
255
+ return true;
59
int target_bits = 0;
256
+}
60
257
+
61
- if (host_bits & float_flag_invalid)
258
+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
62
+ if (host_bits & float_flag_invalid) {
259
+{
63
target_bits |= 1;
260
+ return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
64
- if (host_bits & float_flag_divbyzero)
261
+}
65
+ }
262
+
66
+ if (host_bits & float_flag_divbyzero) {
263
+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
67
target_bits |= 2;
264
+{
68
- if (host_bits & float_flag_overflow)
265
+ return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
69
+ }
266
+}
70
+ if (host_bits & float_flag_overflow) {
267
+
71
target_bits |= 4;
268
+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
72
- if (host_bits & (float_flag_underflow | float_flag_output_denormal))
269
+{
73
+ }
270
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
74
+ if (host_bits & (float_flag_underflow | float_flag_output_denormal)) {
271
+}
75
target_bits |= 8;
272
+
76
- if (host_bits & float_flag_inexact)
273
+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
77
+ }
274
+{
78
+ if (host_bits & float_flag_inexact) {
275
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
79
target_bits |= 0x10;
276
+}
80
- if (host_bits & float_flag_input_denormal)
277
+
81
+ }
278
+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
82
+ if (host_bits & float_flag_input_denormal) {
279
+{
83
target_bits |= 0x80;
280
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
84
+ }
281
+}
85
return target_bits;
282
+
86
}
283
+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
87
284
+{
88
@@ -XXX,XX +XXX,XX @@ static inline int vfp_exceptbits_to_host(int target_bits)
285
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
89
{
286
+}
90
int host_bits = 0;
287
+
91
288
/*
92
- if (target_bits & 1)
289
* Multiply and multiply accumulate
93
+ if (target_bits & 1) {
290
*/
94
host_bits |= float_flag_invalid;
95
- if (target_bits & 2)
96
+ }
97
+ if (target_bits & 2) {
98
host_bits |= float_flag_divbyzero;
99
- if (target_bits & 4)
100
+ }
101
+ if (target_bits & 4) {
102
host_bits |= float_flag_overflow;
103
- if (target_bits & 8)
104
+ }
105
+ if (target_bits & 8) {
106
host_bits |= float_flag_underflow;
107
- if (target_bits & 0x10)
108
+ }
109
+ if (target_bits & 0x10) {
110
host_bits |= float_flag_inexact;
111
- if (target_bits & 0x80)
112
+ }
113
+ if (target_bits & 0x80) {
114
host_bits |= float_flag_input_denormal;
115
+ }
116
return host_bits;
117
}
118
119
--
291
--
120
2.20.1
292
2.20.1
121
293
122
294
diff view generated by jsdifflib
[Qemu-devel] [PULL 25/46] aspeed: Link SCU to the watchdog
[PULL 23/24] target/arm: Implement MVE shifts by immediate
1
From: Joel Stanley <joel@jms.id.au>
1
Implement the MVE shifts by immediate, which perform shifts
2
2
on a single general-purpose register.
3
The ast2500 uses the watchdog to reset the SDRAM controller. This
3
4
operation is usually performed by u-boot's memory training procedure,
4
These patterns overlap with the long-shift-by-immediates,
5
and it is enabled by setting a bit in the SCU and then causing the
5
so we have to rearrange the grouping a little here.
6
watchdog to expire. Therefore, we need the watchdog to be able to
6
7
access the SCU's register space.
8
9
This causes the watchdog to not perform a system reset when the bit is
10
set. In the future it could perform a reset of the SDMC model.
11
12
Signed-off-by: Joel Stanley <joel@jms.id.au>
13
Signed-off-by: Cédric Le Goater <clg@kaod.org>
14
Reviewed-by: Cédric Le Goater <clg@kaod.org>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
16
Message-id: 20190621065242.32535-1-joel@jms.id.au
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
18
---
10
---
19
include/hw/watchdog/wdt_aspeed.h | 1 +
11
target/arm/helper-mve.h | 3 ++
20
hw/arm/aspeed_soc.c | 2 ++
12
target/arm/translate.h | 1 +
21
hw/watchdog/wdt_aspeed.c | 20 ++++++++++++++++++++
13
target/arm/t32.decode | 31 ++++++++++++++-----
22
3 files changed, 23 insertions(+)
14
target/arm/mve_helper.c | 10 ++++++
23
15
target/arm/translate.c | 68 +++++++++++++++++++++++++++++++++++++++--
24
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
16
5 files changed, 104 insertions(+), 9 deletions(-)
25
index XXXXXXX..XXXXXXX 100644
17
26
--- a/include/hw/watchdog/wdt_aspeed.h
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
27
+++ b/include/hw/watchdog/wdt_aspeed.h
19
index XXXXXXX..XXXXXXX 100644
28
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedWDTState {
20
--- a/target/arm/helper-mve.h
29
MemoryRegion iomem;
21
+++ b/target/arm/helper-mve.h
30
uint32_t regs[ASPEED_WDT_REGS_MAX];
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
31
23
DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
32
+ AspeedSCUState *scu;
24
DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
33
uint32_t pclk_freq;
25
DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
34
uint32_t silicon_rev;
26
+
35
uint32_t ext_pulse_width_mask;
27
+DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
36
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
28
+DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
37
index XXXXXXX..XXXXXXX 100644
29
diff --git a/target/arm/translate.h b/target/arm/translate.h
38
--- a/hw/arm/aspeed_soc.c
30
index XXXXXXX..XXXXXXX 100644
39
+++ b/hw/arm/aspeed_soc.c
31
--- a/target/arm/translate.h
40
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
32
+++ b/target/arm/translate.h
41
sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
33
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
42
qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev",
34
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
43
sc->info->silicon_rev);
35
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
44
+ object_property_add_const_link(OBJECT(&s->wdt[i]), "scu",
36
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
45
+ OBJECT(&s->scu), &error_abort);
37
+typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
46
}
38
47
39
/**
48
for (i = 0; i < ASPEED_MACS_NUM; i++) {
40
* arm_tbflags_from_tb:
49
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
41
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
50
index XXXXXXX..XXXXXXX 100644
42
index XXXXXXX..XXXXXXX 100644
51
--- a/hw/watchdog/wdt_aspeed.c
43
--- a/target/arm/t32.decode
52
+++ b/hw/watchdog/wdt_aspeed.c
44
+++ b/target/arm/t32.decode
53
@@ -XXX,XX +XXX,XX @@
45
@@ -XXX,XX +XXX,XX @@
54
46
55
#define WDT_RESTART_MAGIC 0x4755
47
&mve_shl_ri rdalo rdahi shim
56
48
&mve_shl_rr rdalo rdahi rm
57
+#define SCU_RESET_CONTROL1 (0x04 / 4)
49
+&mve_sh_ri rda shim
58
+#define SCU_RESET_SDRAM BIT(0)
50
59
+
51
# rdahi: bits [3:1] from insn, bit 0 is 1
60
static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)
52
# rdalo: bits [3:1] from insn, bit 0 is 0
61
{
53
@@ -XXX,XX +XXX,XX @@
62
return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE;
54
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
63
@@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_timer_expired(void *dev)
55
@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
64
{
56
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
65
AspeedWDTState *s = ASPEED_WDT(dev);
57
+@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
66
58
+ &mve_sh_ri shim=%imm5_12_6
67
+ /* Do not reset on SDRAM controller reset */
59
68
+ if (s->scu->regs[SCU_RESET_CONTROL1] & SCU_RESET_SDRAM) {
60
{
69
+ timer_del(s->timer);
61
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
70
+ s->regs[WDT_CTRL] = 0;
62
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
63
# the rest fall through (where ORR_rrri and MOV_rxri will end up
64
# handling them as r13 and r15 accesses with the same semantics as A32).
65
[
66
- LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
67
- LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
68
- ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
69
+ {
70
+ UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri
71
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
72
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
73
+ }
74
75
- UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
76
- URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
77
- SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
78
- SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
79
+ {
80
+ URSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 01 1111 @mve_sh_ri
81
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
82
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
83
+ }
84
+
85
+ {
86
+ SRSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 10 1111 @mve_sh_ri
87
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
88
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
89
+ }
90
+
91
+ {
92
+ SQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 11 1111 @mve_sh_ri
93
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
94
+ }
95
96
LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
97
ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
98
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/mve_helper.c
101
+++ b/target/arm/mve_helper.c
102
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
103
{
104
return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
105
}
106
+
107
+uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
108
+{
109
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
110
+}
111
+
112
+uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
113
+{
114
+ return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
115
+}
116
diff --git a/target/arm/translate.c b/target/arm/translate.c
117
index XXXXXXX..XXXXXXX 100644
118
--- a/target/arm/translate.c
119
+++ b/target/arm/translate.c
120
@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
121
122
static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
123
{
124
- TCGv_i32 t = tcg_temp_new_i32();
125
+ TCGv_i32 t;
126
127
+ /* Handle shift by the input size for the benefit of trans_SRSHR_ri */
128
+ if (sh == 32) {
129
+ tcg_gen_movi_i32(d, 0);
71
+ return;
130
+ return;
72
+ }
131
+ }
73
+
132
+ t = tcg_temp_new_i32();
74
qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n");
133
tcg_gen_extract_i32(t, a, sh - 1, 1);
75
watchdog_perform_action();
134
tcg_gen_sari_i32(d, a, sh);
76
timer_del(s->timer);
135
tcg_gen_add_i32(d, d, t);
77
@@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
136
@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
78
{
137
79
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
138
static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
80
AspeedWDTState *s = ASPEED_WDT(dev);
139
{
81
+ Error *err = NULL;
140
- TCGv_i32 t = tcg_temp_new_i32();
82
+ Object *obj;
141
+ TCGv_i32 t;
83
+
142
84
+ obj = object_property_get_link(OBJECT(dev), "scu", &err);
143
+ /* Handle shift by the input size for the benefit of trans_URSHR_ri */
85
+ if (!obj) {
144
+ if (sh == 32) {
86
+ error_propagate(errp, err);
145
+ tcg_gen_extract_i32(d, a, sh - 1, 1);
87
+ error_prepend(errp, "required link 'scu' not found: ");
88
+ return;
146
+ return;
89
+ }
147
+ }
90
+ s->scu = ASPEED_SCU(obj);
148
+ t = tcg_temp_new_i32();
91
149
tcg_gen_extract_i32(t, a, sh - 1, 1);
92
if (!is_supported_silicon_rev(s->silicon_rev)) {
150
tcg_gen_shri_i32(d, a, sh);
93
error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
151
tcg_gen_add_i32(d, d, t);
152
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
153
return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
154
}
155
156
+static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)
157
+{
158
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
159
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
160
+ return false;
161
+ }
162
+ if (!dc_isar_feature(aa32_mve, s) ||
163
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
164
+ a->rda == 13 || a->rda == 15) {
165
+ /* These rda cases are UNPREDICTABLE; we choose to UNDEF */
166
+ unallocated_encoding(s);
167
+ return true;
168
+ }
169
+
170
+ if (a->shim == 0) {
171
+ a->shim = 32;
172
+ }
173
+ fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);
174
+
175
+ return true;
176
+}
177
+
178
+static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
179
+{
180
+ return do_mve_sh_ri(s, a, gen_urshr32_i32);
181
+}
182
+
183
+static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
184
+{
185
+ return do_mve_sh_ri(s, a, gen_srshr32_i32);
186
+}
187
+
188
+static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
189
+{
190
+ gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));
191
+}
192
+
193
+static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
194
+{
195
+ return do_mve_sh_ri(s, a, gen_mve_sqshl);
196
+}
197
+
198
+static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
199
+{
200
+ gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));
201
+}
202
+
203
+static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
204
+{
205
+ return do_mve_sh_ri(s, a, gen_mve_uqshl);
206
+}
207
+
208
/*
209
* Multiply and multiply accumulate
210
*/
94
--
211
--
95
2.20.1
212
2.20.1
96
213
97
214
diff view generated by jsdifflib
[Qemu-devel] [PULL 26/46] hw/arm: Add arm SBSA reference machine, skeleton part
[PULL 24/24] target/arm: Implement MVE shifts by register
1
From: Hongbo Zhang <hongbo.zhang@linaro.org>
1
Implement the MVE shifts by register, which perform
2
shifts on a single general-purpose register.
2
3
3
For AArch64, the existing "virt" machine is primarily meant to
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
run on KVM and execute virtualization workloads, but we need an
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
environment as faithful as possible to physical hardware, for supporting
6
Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
6
firmware and OS development for physical Aarch64 machines.
7
---
8
target/arm/helper-mve.h | 2 ++
9
target/arm/translate.h | 1 +
10
target/arm/t32.decode | 18 ++++++++++++++----
11
target/arm/mve_helper.c | 10 ++++++++++
12
target/arm/translate.c | 30 ++++++++++++++++++++++++++++++
13
5 files changed, 57 insertions(+), 4 deletions(-)
7
14
8
This patch introduces new machine type 'sbsa-ref' with main features:
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
9
- Based on 'virt' machine type.
10
- A new memory map.
11
- CPU type cortex-a57.
12
- EL2 and EL3 are enabled.
13
- GIC version 3.
14
- System bus AHCI controller.
15
- System bus EHCI controller.
16
- CDROM and hard disc on AHCI bus.
17
- E1000E ethernet card on PCIE bus.
18
- VGA display adaptor on PCIE bus.
19
- No virtio devices.
20
- No fw_cfg device.
21
- No ACPI table supplied.
22
- Only minimal device tree nodes.
23
24
Arm Trusted Firmware and UEFI porting to this are done accordingly,
25
and the firmware should supply ACPI tables to the guest OS. The
26
minimal device tree nodes supplied by QEMU for this platform are only
27
to pass the dynamic info reflecting command line input to firmware,
28
not for loading the guest OS.
29
30
To make the review easier, this task is split into two patches, the
31
fundamental skeleton part and the peripheral devices part; this patch is
32
the first part.
33
34
Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org>
35
Message-id: 1561890034-15921-2-git-send-email-hongbo.zhang@linaro.org
36
[PMM: commit message tweaks; moved some bits between patch 1 and 2
37
to ensure patch 1 builds cleanly; removed unneeded lines from
38
Kconfig stanza; only provide board for qemu-system-aarch64, not
39
qemu-system-arm; added MAINTAINERS entry]
40
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
41
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
42
---
43
hw/arm/Makefile.objs | 1 +
44
hw/arm/sbsa-ref.c | 271 ++++++++++++++++++++++++++++
45
MAINTAINERS | 8 +
46
default-configs/aarch64-softmmu.mak | 1 +
47
hw/arm/Kconfig | 14 ++
48
5 files changed, 295 insertions(+)
49
create mode 100644 hw/arm/sbsa-ref.c
50
51
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
52
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/arm/Makefile.objs
17
--- a/target/arm/helper-mve.h
54
+++ b/hw/arm/Makefile.objs
18
+++ b/target/arm/helper-mve.h
55
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_SPITZ) += spitz.o
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
56
obj-$(CONFIG_TOSA) += tosa.o
20
57
obj-$(CONFIG_Z2) += z2.o
21
DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
58
obj-$(CONFIG_REALVIEW) += realview.o
22
DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
59
+obj-$(CONFIG_SBSA_REF) += sbsa-ref.o
23
+DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
60
obj-$(CONFIG_STELLARIS) += stellaris.o
24
+DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)
61
obj-$(CONFIG_COLLIE) += collie.o
25
diff --git a/target/arm/translate.h b/target/arm/translate.h
62
obj-$(CONFIG_VERSATILE) += versatilepb.o
26
index XXXXXXX..XXXXXXX 100644
63
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
27
--- a/target/arm/translate.h
64
new file mode 100644
28
+++ b/target/arm/translate.h
65
index XXXXXXX..XXXXXXX
29
@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
66
--- /dev/null
30
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
67
+++ b/hw/arm/sbsa-ref.c
31
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
32
typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
33
+typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
34
35
/**
36
* arm_tbflags_from_tb:
37
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/t32.decode
40
+++ b/target/arm/t32.decode
68
@@ -XXX,XX +XXX,XX @@
41
@@ -XXX,XX +XXX,XX @@
69
+/*
42
&mve_shl_ri rdalo rdahi shim
70
+ * ARM SBSA Reference Platform emulation
43
&mve_shl_rr rdalo rdahi rm
71
+ *
44
&mve_sh_ri rda shim
72
+ * Copyright (c) 2018 Linaro Limited
45
+&mve_sh_rr rda rm
73
+ * Written by Hongbo Zhang <hongbo.zhang@linaro.org>
46
74
+ *
47
# rdahi: bits [3:1] from insn, bit 0 is 1
75
+ * This program is free software; you can redistribute it and/or modify it
48
# rdalo: bits [3:1] from insn, bit 0 is 0
76
+ * under the terms and conditions of the GNU General Public License,
49
@@ -XXX,XX +XXX,XX @@
77
+ * version 2 or later, as published by the Free Software Foundation.
50
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
78
+ *
51
@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
79
+ * This program is distributed in the hope it will be useful, but WITHOUT
52
&mve_sh_ri shim=%imm5_12_6
80
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
53
+@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr
81
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
54
82
+ * more details.
55
{
83
+ *
56
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
84
+ * You should have received a copy of the GNU General Public License along with
57
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
85
+ * this program. If not, see <http://www.gnu.org/licenses/>.
58
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
86
+ */
59
}
87
+
60
88
+#include "qemu/osdep.h"
61
- LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
89
+#include "qapi/error.h"
62
- ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
90
+#include "qemu/error-report.h"
63
- UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
91
+#include "qemu/units.h"
64
- SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
92
+#include "sysemu/numa.h"
65
+ {
93
+#include "sysemu/sysemu.h"
66
+ UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr
94
+#include "exec/address-spaces.h"
67
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
95
+#include "exec/hwaddr.h"
68
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
96
+#include "kvm_arm.h"
97
+#include "hw/arm/boot.h"
98
+#include "hw/boards.h"
99
+#include "hw/intc/arm_gicv3_common.h"
100
+
101
+#define RAMLIMIT_GB 8192
102
+#define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
103
+
104
+enum {
105
+ SBSA_FLASH,
106
+ SBSA_MEM,
107
+ SBSA_CPUPERIPHS,
108
+ SBSA_GIC_DIST,
109
+ SBSA_GIC_REDIST,
110
+ SBSA_SMMU,
111
+ SBSA_UART,
112
+ SBSA_RTC,
113
+ SBSA_PCIE,
114
+ SBSA_PCIE_MMIO,
115
+ SBSA_PCIE_MMIO_HIGH,
116
+ SBSA_PCIE_PIO,
117
+ SBSA_PCIE_ECAM,
118
+ SBSA_GPIO,
119
+ SBSA_SECURE_UART,
120
+ SBSA_SECURE_UART_MM,
121
+ SBSA_SECURE_MEM,
122
+ SBSA_AHCI,
123
+ SBSA_EHCI,
124
+};
125
+
126
+typedef struct MemMapEntry {
127
+ hwaddr base;
128
+ hwaddr size;
129
+} MemMapEntry;
130
+
131
+typedef struct {
132
+ MachineState parent;
133
+ struct arm_boot_info bootinfo;
134
+ int smp_cpus;
135
+ void *fdt;
136
+ int fdt_size;
137
+ int psci_conduit;
138
+} SBSAMachineState;
139
+
140
+#define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref")
141
+#define SBSA_MACHINE(obj) \
142
+ OBJECT_CHECK(SBSAMachineState, (obj), TYPE_SBSA_MACHINE)
143
+
144
+static const MemMapEntry sbsa_ref_memmap[] = {
145
+ /* 512M boot ROM */
146
+ [SBSA_FLASH] = { 0, 0x20000000 },
147
+ /* 512M secure memory */
148
+ [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 },
149
+ /* Space reserved for CPU peripheral devices */
150
+ [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 },
151
+ [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 },
152
+ [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 },
153
+ [SBSA_UART] = { 0x60000000, 0x00001000 },
154
+ [SBSA_RTC] = { 0x60010000, 0x00001000 },
155
+ [SBSA_GPIO] = { 0x60020000, 0x00001000 },
156
+ [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 },
157
+ [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 },
158
+ [SBSA_SMMU] = { 0x60050000, 0x00020000 },
159
+ /* Space here reserved for more SMMUs */
160
+ [SBSA_AHCI] = { 0x60100000, 0x00010000 },
161
+ [SBSA_EHCI] = { 0x60110000, 0x00010000 },
162
+ /* Space here reserved for other devices */
163
+ [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 },
164
+ /* 32-bit address PCIE MMIO space */
165
+ [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 },
166
+ /* 256M PCIE ECAM space */
167
+ [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 },
168
+ /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */
169
+ [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL },
170
+ [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES },
171
+};
172
+
173
+static void sbsa_ref_init(MachineState *machine)
174
+{
175
+ SBSAMachineState *sms = SBSA_MACHINE(machine);
176
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
177
+ MemoryRegion *sysmem = get_system_memory();
178
+ MemoryRegion *secure_sysmem = NULL;
179
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
180
+ const CPUArchIdList *possible_cpus;
181
+ int n, sbsa_max_cpus;
182
+
183
+ if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) {
184
+ error_report("sbsa-ref: CPU type other than the built-in "
185
+ "cortex-a57 not supported");
186
+ exit(1);
187
+ }
69
+ }
188
+
70
+
189
+ if (kvm_enabled()) {
71
+ {
190
+ error_report("sbsa-ref: KVM is not supported for this machine");
72
+ SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr
191
+ exit(1);
73
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
74
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
192
+ }
75
+ }
193
+
76
+
194
+ /*
77
UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
195
+ * This machine has EL3 enabled, external firmware should supply PSCI
78
SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
196
+ * implementation, so the QEMU's internal PSCI is disabled.
79
]
197
+ */
80
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
198
+ sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/arm/mve_helper.c
83
+++ b/target/arm/mve_helper.c
84
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
85
{
86
return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
87
}
199
+
88
+
200
+ sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
89
+uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)
90
+{
91
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);
92
+}
201
+
93
+
202
+ if (max_cpus > sbsa_max_cpus) {
94
+uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)
203
+ error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
95
+{
204
+ "supported by machine 'sbsa-ref' (%d)",
96
+ return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);
205
+ max_cpus, sbsa_max_cpus);
97
+}
206
+ exit(1);
98
diff --git a/target/arm/translate.c b/target/arm/translate.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/translate.c
101
+++ b/target/arm/translate.c
102
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
103
return do_mve_sh_ri(s, a, gen_mve_uqshl);
104
}
105
106
+static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)
107
+{
108
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
109
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
110
+ return false;
111
+ }
112
+ if (!dc_isar_feature(aa32_mve, s) ||
113
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
114
+ a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||
115
+ a->rm == a->rda) {
116
+ /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */
117
+ unallocated_encoding(s);
118
+ return true;
207
+ }
119
+ }
208
+
120
+
209
+ sms->smp_cpus = smp_cpus;
121
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
210
+
122
+ fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);
211
+ if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) {
123
+ return true;
212
+ error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB);
213
+ exit(1);
214
+ }
215
+
216
+ possible_cpus = mc->possible_cpu_arch_ids(machine);
217
+ for (n = 0; n < possible_cpus->len; n++) {
218
+ Object *cpuobj;
219
+ CPUState *cs;
220
+
221
+ if (n >= smp_cpus) {
222
+ break;
223
+ }
224
+
225
+ cpuobj = object_new(possible_cpus->cpus[n].type);
226
+ object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,
227
+ "mp-affinity", NULL);
228
+
229
+ cs = CPU(cpuobj);
230
+ cs->cpu_index = n;
231
+
232
+ numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
233
+ &error_fatal);
234
+
235
+ if (object_property_find(cpuobj, "reset-cbar", NULL)) {
236
+ object_property_set_int(cpuobj,
237
+ sbsa_ref_memmap[SBSA_CPUPERIPHS].base,
238
+ "reset-cbar", &error_abort);
239
+ }
240
+
241
+ object_property_set_link(cpuobj, OBJECT(sysmem), "memory",
242
+ &error_abort);
243
+
244
+ object_property_set_link(cpuobj, OBJECT(secure_sysmem),
245
+ "secure-memory", &error_abort);
246
+
247
+ object_property_set_bool(cpuobj, true, "realized", &error_fatal);
248
+ object_unref(cpuobj);
249
+ }
250
+
251
+ memory_region_allocate_system_memory(ram, NULL, "sbsa-ref.ram",
252
+ machine->ram_size);
253
+ memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, ram);
254
+
255
+ sms->bootinfo.ram_size = machine->ram_size;
256
+ sms->bootinfo.kernel_filename = machine->kernel_filename;
257
+ sms->bootinfo.nb_cpus = smp_cpus;
258
+ sms->bootinfo.board_id = -1;
259
+ sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base;
260
+ arm_load_kernel(ARM_CPU(first_cpu), &sms->bootinfo);
261
+}
124
+}
262
+
125
+
263
+static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
126
+static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)
264
+{
127
+{
265
+ uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
128
+ return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);
266
+ return arm_cpu_mp_affinity(idx, clustersz);
267
+}
129
+}
268
+
130
+
269
+static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms)
131
+static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)
270
+{
132
+{
271
+ SBSAMachineState *sms = SBSA_MACHINE(ms);
133
+ return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);
272
+ int n;
273
+
274
+ if (ms->possible_cpus) {
275
+ assert(ms->possible_cpus->len == max_cpus);
276
+ return ms->possible_cpus;
277
+ }
278
+
279
+ ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
280
+ sizeof(CPUArchId) * max_cpus);
281
+ ms->possible_cpus->len = max_cpus;
282
+ for (n = 0; n < ms->possible_cpus->len; n++) {
283
+ ms->possible_cpus->cpus[n].type = ms->cpu_type;
284
+ ms->possible_cpus->cpus[n].arch_id =
285
+ sbsa_ref_cpu_mp_affinity(sms, n);
286
+ ms->possible_cpus->cpus[n].props.has_thread_id = true;
287
+ ms->possible_cpus->cpus[n].props.thread_id = n;
288
+ }
289
+ return ms->possible_cpus;
290
+}
134
+}
291
+
135
+
292
+static CpuInstanceProperties
136
/*
293
+sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
137
* Multiply and multiply accumulate
294
+{
138
*/
295
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
296
+ const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
297
+
298
+ assert(cpu_index < possible_cpus->len);
299
+ return possible_cpus->cpus[cpu_index].props;
300
+}
301
+
302
+static int64_t
303
+sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx)
304
+{
305
+ return idx % nb_numa_nodes;
306
+}
307
+
308
+static void sbsa_ref_class_init(ObjectClass *oc, void *data)
309
+{
310
+ MachineClass *mc = MACHINE_CLASS(oc);
311
+
312
+ mc->init = sbsa_ref_init;
313
+ mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine";
314
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57");
315
+ mc->max_cpus = 512;
316
+ mc->pci_allow_0_address = true;
317
+ mc->minimum_page_bits = 12;
318
+ mc->block_default_type = IF_IDE;
319
+ mc->no_cdrom = 1;
320
+ mc->default_ram_size = 1 * GiB;
321
+ mc->default_cpus = 4;
322
+ mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids;
323
+ mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props;
324
+ mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id;
325
+}
326
+
327
+static const TypeInfo sbsa_ref_info = {
328
+ .name = TYPE_SBSA_MACHINE,
329
+ .parent = TYPE_MACHINE,
330
+ .class_init = sbsa_ref_class_init,
331
+ .instance_size = sizeof(SBSAMachineState),
332
+};
333
+
334
+static void sbsa_ref_machine_init(void)
335
+{
336
+ type_register_static(&sbsa_ref_info);
337
+}
338
+
339
+type_init(sbsa_ref_machine_init);
340
diff --git a/MAINTAINERS b/MAINTAINERS
341
index XXXXXXX..XXXXXXX 100644
342
--- a/MAINTAINERS
343
+++ b/MAINTAINERS
344
@@ -XXX,XX +XXX,XX @@ F: include/hw/arm/fsl-imx6.h
345
F: include/hw/misc/imx6_*.h
346
F: include/hw/ssi/imx_spi.h
347
348
+SBSA-REF
349
+M: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
350
+M: Peter Maydell <peter.maydell@linaro.org>
351
+R: Leif Lindholm <leif.lindholm@linaro.org>
352
+L: qemu-arm@nongnu.org
353
+S: Maintained
354
+F: hw/arm/sbsa-ref.c
355
+
356
Sharp SL-5500 (Collie) PDA
357
M: Peter Maydell <peter.maydell@linaro.org>
358
L: qemu-arm@nongnu.org
359
diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-softmmu.mak
360
index XXXXXXX..XXXXXXX 100644
361
--- a/default-configs/aarch64-softmmu.mak
362
+++ b/default-configs/aarch64-softmmu.mak
363
@@ -XXX,XX +XXX,XX @@ include arm-softmmu.mak
364
365
CONFIG_XLNX_ZYNQMP_ARM=y
366
CONFIG_XLNX_VERSAL=y
367
+CONFIG_SBSA_REF=y
368
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
369
index XXXXXXX..XXXXXXX 100644
370
--- a/hw/arm/Kconfig
371
+++ b/hw/arm/Kconfig
372
@@ -XXX,XX +XXX,XX @@ config REALVIEW
373
select DS1338 # I2C RTC+NVRAM
374
select USB_OHCI
375
376
+config SBSA_REF
377
+ bool
378
+ imply PCI_DEVICES
379
+ select AHCI
380
+ select ARM_SMMUV3
381
+ select GPIO_KEY
382
+ select PCI_EXPRESS
383
+ select PCI_EXPRESS_GENERIC_BRIDGE
384
+ select PFLASH_CFI01
385
+ select PL011 # UART
386
+ select PL031 # RTC
387
+ select PL061 # GPIO
388
+ select USB_EHCI_SYSBUS
389
+
390
config SABRELITE
391
bool
392
select FSL_IMX6
393
--
139
--
394
2.20.1
140
2.20.1
395
141
396
142
diff view generated by jsdifflib
[Qemu-devel] [PULL 29/46] target/arm: Makefile cleanup (ARM)
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
Group ARM objects together, TCG related ones at the bottom.
4
This will help when restricting TCG-only objects.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20190701132516.26392-3-philmd@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/Makefile.objs | 10 ++++++----
12
1 file changed, 6 insertions(+), 4 deletions(-)
13
14
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/Makefile.objs
17
+++ b/target/arm/Makefile.objs
18
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_KVM) += kvm.o
19
obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o
20
obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o
21
obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
22
-obj-y += translate.o op_helper.o helper.o cpu.o
23
-obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o vfp_helper.o
24
-obj-y += gdbstub.o
25
+obj-y += helper.o vfp_helper.o
26
+obj-y += cpu.o gdbstub.o
27
obj-$(TARGET_AARCH64) += cpu64.o gdbstub64.o
28
-obj-y += crypto_helper.o
29
obj-$(CONFIG_SOFTMMU) += arm-powerctl.o
30
31
DECODETREE = $(SRC_PATH)/scripts/decodetree.py
32
@@ -XXX,XX +XXX,XX @@ target/arm/translate-sve.o: target/arm/decode-sve.inc.c
33
target/arm/translate.o: target/arm/decode-vfp.inc.c
34
target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
35
36
+obj-y += translate.o op_helper.o
37
+obj-y += crypto_helper.o
38
+obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
39
+
40
obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o
41
obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o
42
obj-$(TARGET_AARCH64) += pauth_helper.o
43
--
44
2.20.1
45
46
diff view generated by jsdifflib
[Qemu-devel] [PULL 30/46] target/arm: Makefile cleanup (KVM)
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
Group KVM rules together.
4
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-id: 20190701132516.26392-4-philmd@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/Makefile.objs | 9 +++++----
11
1 file changed, 5 insertions(+), 4 deletions(-)
12
13
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/Makefile.objs
16
+++ b/target/arm/Makefile.objs
17
@@ -XXX,XX +XXX,XX @@
18
obj-y += arm-semi.o
19
obj-$(CONFIG_SOFTMMU) += machine.o psci.o arch_dump.o monitor.o
20
-obj-$(CONFIG_KVM) += kvm.o
21
-obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o
22
-obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o
23
-obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
24
obj-y += helper.o vfp_helper.o
25
obj-y += cpu.o gdbstub.o
26
obj-$(TARGET_AARCH64) += cpu64.o gdbstub64.o
27
obj-$(CONFIG_SOFTMMU) += arm-powerctl.o
28
29
+obj-$(CONFIG_KVM) += kvm.o
30
+obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o
31
+obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o
32
+obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
33
+
34
DECODETREE = $(SRC_PATH)/scripts/decodetree.py
35
36
target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE)
37
--
38
2.20.1
39
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 31/46] target/arm: Makefile cleanup (softmmu)
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
Group SOFTMMU objects together.
4
Since PSCI is TCG specific, keep it separate.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20190701132516.26392-5-philmd@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/Makefile.objs | 5 ++++-
12
1 file changed, 4 insertions(+), 1 deletion(-)
13
14
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/Makefile.objs
17
+++ b/target/arm/Makefile.objs
18
@@ -XXX,XX +XXX,XX @@
19
obj-y += arm-semi.o
20
-obj-$(CONFIG_SOFTMMU) += machine.o psci.o arch_dump.o monitor.o
21
obj-y += helper.o vfp_helper.o
22
obj-y += cpu.o gdbstub.o
23
obj-$(TARGET_AARCH64) += cpu64.o gdbstub64.o
24
+
25
+obj-$(CONFIG_SOFTMMU) += machine.o arch_dump.o monitor.o
26
obj-$(CONFIG_SOFTMMU) += arm-powerctl.o
27
28
obj-$(CONFIG_KVM) += kvm.o
29
@@ -XXX,XX +XXX,XX @@ obj-y += translate.o op_helper.o
30
obj-y += crypto_helper.o
31
obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
32
33
+obj-$(CONFIG_SOFTMMU) += psci.o
34
+
35
obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o
36
obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o
37
obj-$(TARGET_AARCH64) += pauth_helper.o
38
--
39
2.20.1
40
41
diff view generated by jsdifflib
[Qemu-devel] [PULL 32/46] target/arm: Add copyright boilerplate
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
Reviewed-by: Robert Bradford <robert.bradford@intel.com>
4
Reviewed-by: Samuel Ortiz <sameo@linux.intel.com>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-id: 20190701132516.26392-6-philmd@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/helper.c | 7 +++++++
11
1 file changed, 7 insertions(+)
12
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
16
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@
18
+/*
19
+ * ARM generic helpers.
20
+ *
21
+ * This code is licensed under the GNU GPL v2 or later.
22
+ *
23
+ * SPDX-License-Identifier: GPL-2.0-or-later
24
+ */
25
#include "qemu/osdep.h"
26
#include "qemu/units.h"
27
#include "target/arm/idau.h"
28
--
29
2.20.1
30
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 33/46] target/arm/helper: Remove unused include
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
4
Message-id: 20190701132516.26392-7-philmd@redhat.com
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/helper.c | 2 --
9
1 file changed, 2 deletions(-)
10
11
diff --git a/target/arm/helper.c b/target/arm/helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/helper.c
14
+++ b/target/arm/helper.c
15
@@ -XXX,XX +XXX,XX @@
16
#include "exec/gdbstub.h"
17
#include "exec/helper-proto.h"
18
#include "qemu/host-utils.h"
19
-#include "sysemu/arch_init.h"
20
#include "sysemu/sysemu.h"
21
#include "qemu/bitops.h"
22
#include "qemu/crc32c.h"
23
@@ -XXX,XX +XXX,XX @@
24
#include "hw/semihosting/semihost.h"
25
#include "sysemu/cpus.h"
26
#include "sysemu/kvm.h"
27
-#include "fpu/softfloat.h"
28
#include "qemu/range.h"
29
#include "qapi/qapi-commands-target.h"
30
#include "qapi/error.h"
31
--
32
2.20.1
33
34
diff view generated by jsdifflib
[Qemu-devel] [PULL 38/46] target/arm: Declare get_phys_addr() function publicly
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
1
3
In the next commit we will split the TLB related routines of
4
this file, and this function will also be called in the new
5
file. Declare it in the "internals.h" header.
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20190701132516.26392-12-philmd@redhat.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/internals.h | 16 ++++++++++++++++
13
target/arm/helper.c | 21 +++++----------------
14
2 files changed, 21 insertions(+), 16 deletions(-)
15
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/internals.h
19
+++ b/target/arm/internals.h
20
@@ -XXX,XX +XXX,XX @@ static inline int exception_target_el(CPUARMState *env)
21
return target_el;
22
}
23
24
+#ifndef CONFIG_USER_ONLY
25
+
26
+/* Cacheability and shareability attributes for a memory access */
27
+typedef struct ARMCacheAttrs {
28
+ unsigned int attrs:8; /* as in the MAIR register encoding */
29
+ unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */
30
+} ARMCacheAttrs;
31
+
32
+bool get_phys_addr(CPUARMState *env, target_ulong address,
33
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
34
+ hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
35
+ target_ulong *page_size,
36
+ ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
37
+
38
+#endif /* !CONFIG_USER_ONLY */
39
+
40
#endif
41
diff --git a/target/arm/helper.c b/target/arm/helper.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/helper.c
44
+++ b/target/arm/helper.c
45
@@ -XXX,XX +XXX,XX @@
46
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
47
48
#ifndef CONFIG_USER_ONLY
49
-/* Cacheability and shareability attributes for a memory access */
50
-typedef struct ARMCacheAttrs {
51
- unsigned int attrs:8; /* as in the MAIR register encoding */
52
- unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */
53
-} ARMCacheAttrs;
54
-
55
-static bool get_phys_addr(CPUARMState *env, target_ulong address,
56
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
57
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
58
- target_ulong *page_size,
59
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
60
61
static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
62
MMUAccessType access_type, ARMMMUIdx mmu_idx,
63
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2)
64
* @fi: set to fault info if the translation fails
65
* @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
66
*/
67
-static bool get_phys_addr(CPUARMState *env, target_ulong address,
68
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
69
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
70
- target_ulong *page_size,
71
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
72
+bool get_phys_addr(CPUARMState *env, target_ulong address,
73
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
74
+ hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
75
+ target_ulong *page_size,
76
+ ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
77
{
78
if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
79
/* Call ourselves recursively to do the stage 1 and then stage 2
80
--
81
2.20.1
82
83
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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