Latest arm queue, half minor code cleanups and half minor
bug fixes.
-- PMM
The following changes since commit 5d0e5694470d2952b4f257bc985cac8c89b4fd92:
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2019-06-17 11:55:14 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190617
for you to fetch changes up to 1120827fa182f0e76226df7ffe7a86598d1df54f:
target/arm: Only implement doubles if the FPU supports them (2019-06-17 15:15:06 +0100)
----------------------------------------------------------------
target-arm queue:
* support large kernel images in bootloader (by avoiding
putting the initrd over the top of them)
* correctly disable FPU/DSP in the CPU for the mps2-an521, musca-a boards
* arm_gicv3: Fix decoding of ID register range
* arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1
* some code cleanups following on from the VFP decodetree conversion
* Only implement doubles if the FPU supports them
(so we now correctly model Cortex-M4, -M33 as single precision only)
----------------------------------------------------------------
Peter Maydell (24):
hw/arm/boot: Don't assume RAM starts at address zero
hw/arm/boot: Diagnose layouts that put initrd or DTB off the end of RAM
hw/arm/boot: Avoid placing the initrd on top of the kernel
hw/arm/boot: Honour image size field in AArch64 Image format kernels
target/arm: Allow VFP and Neon to be disabled via a CPU property
target/arm: Allow M-profile CPUs to disable the DSP extension via CPU property
hw/arm/armv7m: Forward "vfp" and "dsp" properties to CPU
hw/arm: Correctly disable FPU/DSP for some ARMSSE-based boards
hw/intc/arm_gicv3: Fix decoding of ID register range
hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1
target/arm: Move vfp_expand_imm() to translate.[ch]
target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm
target/arm: Stop using cpu_F0s for NEON_2RM_VABS_F
target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_F
target/arm: Stop using cpu_F0s for NEON_2RM_VRINT*
target/arm: Stop using cpu_F0s for NEON_2RM_VCVT[ANPM][US]
target/arm: Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_F
target/arm: Stop using cpu_F0s for Neon f32/s32 VCVT
target/arm: Stop using cpu_F0s in Neon VCVT fixed-point ops
target/arm: stop using deprecated functions in NEON_2RM_VCVT_F16_F32
target/arm: Stop using deprecated functions in NEON_2RM_VCVT_F32_F16
target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d
target/arm: Fix typos in trans function prototypes
target/arm: Only implement doubles if the FPU supports them
include/hw/arm/armsse.h | 7 ++
include/hw/arm/armv7m.h | 4 +
target/arm/cpu.h | 12 +++
target/arm/translate-a64.h | 1 -
target/arm/translate.h | 7 ++
hw/arm/armsse.c | 58 +++++++---
hw/arm/armv7m.c | 18 ++++
hw/arm/boot.c | 83 ++++++++++----
hw/arm/musca.c | 8 ++
hw/intc/arm_gicv3_dist.c | 12 ++-
hw/intc/arm_gicv3_redist.c | 4 +-
target/arm/cpu.c | 179 ++++++++++++++++++++++++++++--
target/arm/translate-a64.c | 32 ------
target/arm/translate-vfp.inc.c | 173 ++++++++++++++++++++++-------
target/arm/translate.c | 240 ++++++++++++++---------------------------
target/arm/vfp.decode | 10 +-
16 files changed, 572 insertions(+), 276 deletions(-)