Patchew URL: https://patchew.org/QEMU/20190613121433.5246-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PULL 00/48] target-arm queue
Type: series
Message-id: 20190613121433.5246-1-peter.maydell@linaro.org
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
From https://github.com/patchew-project/qemu
fe18911af7..785a602eae master -> master
From https://github.com/patchew-project/qemu
* [new tag] patchew/20190613121433.5246-1-peter.maydell@linaro.org -> patchew/20190613121433.5246-1-peter.maydell@linaro.org
Switched to a new branch 'test'
926e630776 target/arm: Fix short-vector increment behaviour
ce22853077 target/arm: Convert float-to-integer VCVT insns to decodetree
c37ca2f3bf target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree
3b5f235346 target/arm: Convert VJCVT to decodetree
1bff1b42c5 target/arm: Convert integer-to-float insns to decodetree
555806532f target/arm: Convert double-single precision conversion insns to decodetree
2caa8efb18 target/arm: Convert VFP round insns to decodetree
f0a5e74211 target/arm: Convert the VCVT-to-f16 insns to decodetree
0c24088443 target/arm: Convert the VCVT-from-f16 insns to decodetree
117f5724d6 target/arm: Convert VFP comparison insns to decodetree
95c0d1a203 target/arm: Convert VMOV (register) to decodetree
89a58d122d target/arm: Convert VSQRT to decodetree
6d4705c930 target/arm: Convert VNEG to decodetree
b861d4f6fa target/arm: Convert VABS to decodetree
627584699a target/arm: Convert VMOV (imm) to decodetree
3b6c2fdb70 target/arm: Convert VFP fused multiply-add insns to decodetree
e6d14a1389 target/arm: Convert VDIV to decodetree
24c3a8aa7e target/arm: Convert VSUB to decodetree
cc1ee821b1 target/arm: Convert VADD to decodetree
4419e515ca target/arm: Convert VNMUL to decodetree
1f1b4d995f target/arm: Convert VMUL to decodetree
a400969852 target/arm: Convert VFP VNMLA to decodetree
c483f534cd target/arm: Convert VFP VNMLS to decodetree
2794fd01a6 target/arm: Convert VFP VMLS to decodetree
dbf9c663be target/arm: Convert VFP VMLA to decodetree
0235e3c319 target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d
39361dd565 target/arm: Convert the VFP load/store multiple insns to decodetree
f29a32d0ff target/arm: Convert VFP VLDR and VSTR to decodetree
e0068ce950 target/arm: Convert VFP two-register transfer insns to decodetree
e36f8bc0c1 target/arm: Convert "single-precision" register moves to decodetree
8064bfe1d5 target/arm: Convert "double-precision" register moves to decodetree
5334529e6d target/arm: Add helpers for VFP register loads and stores
41f67d30da target/arm: Move the VFP trans_* functions to translate-vfp.inc.c
52c347ae77 target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree
03a59cd74b target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree
ccb4d7b954 target/arm: Convert VMINNM, VMAXNM to decodetree
6ed963d6b4 target/arm: Convert the VSEL instructions to decodetree
37477468c5 target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max
3379f8474d target/arm: Fix Cortex-R5F MVFR values
3c4abd68dd target/arm: Factor out VFP access checking code
50869d532f target/arm: Add stubs for AArch32 VFP decodetree
7b75e12528 decodetree: Fix comparison of Field
0c2b3af838 target/arm: Fix output of PAuth Auth
f950fd07e1 hw/core/bus.c: Only the main system bus can have no parent
60c713650a hw/arm/smmuv3: Fix decoding of ID register range
b0666f9be8 target/arm: Implement NSACR gating of floating point
55e6145e4d target/arm: Use tcg_gen_gvec_bitsel
94b9d10fda target/arm: Vectorize USHL and SSHL
=== OUTPUT BEGIN ===
1/48 Checking commit 94b9d10fdafd (target/arm: Vectorize USHL and SSHL)
ERROR: trailing statements should be on next line
#163: FILE: target/arm/translate.c:5377:
+ case 2: gen_ushl_i32(var, var, shift); break;
ERROR: trailing statements should be on next line
#170: FILE: target/arm/translate.c:5383:
+ case 2: gen_sshl_i32(var, var, shift); break;
total: 2 errors, 0 warnings, 570 lines checked
Patch 1/48 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/48 Checking commit 55e6145e4da3 (target/arm: Use tcg_gen_gvec_bitsel)
3/48 Checking commit b0666f9be840 (target/arm: Implement NSACR gating of floating point)
4/48 Checking commit 60c713650a47 (hw/arm/smmuv3: Fix decoding of ID register range)
5/48 Checking commit f950fd07e1a6 (hw/core/bus.c: Only the main system bus can have no parent)
6/48 Checking commit 0c2b3af8381e (target/arm: Fix output of PAuth Auth)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#49:
new file mode 100644
total: 0 errors, 1 warnings, 80 lines checked
Patch 6/48 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
7/48 Checking commit 7b75e12528ba (decodetree: Fix comparison of Field)
8/48 Checking commit 50869d532f3f (target/arm: Add stubs for AArch32 VFP decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 136 lines checked
Patch 8/48 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/48 Checking commit 3c4abd68ddd5 (target/arm: Factor out VFP access checking code)
10/48 Checking commit 3379f8474d1b (target/arm: Fix Cortex-R5F MVFR values)
11/48 Checking commit 37477468c5db (target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max)
12/48 Checking commit 6ed963d6b4c9 (target/arm: Convert the VSEL instructions to decodetree)
13/48 Checking commit ccb4d7b95483 (target/arm: Convert VMINNM, VMAXNM to decodetree)
14/48 Checking commit 03a59cd74b1c (target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree)
15/48 Checking commit 52c347ae77aa (target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree)
16/48 Checking commit 41f67d30da15 (target/arm: Move the VFP trans_* functions to translate-vfp.inc.c)
17/48 Checking commit 5334529e6da8 (target/arm: Add helpers for VFP register loads and stores)
18/48 Checking commit 8064bfe1d5b6 (target/arm: Convert "double-precision" register moves to decodetree)
19/48 Checking commit e36f8bc0c13a (target/arm: Convert "single-precision" register moves to decodetree)
20/48 Checking commit e0068ce9501a (target/arm: Convert VFP two-register transfer insns to decodetree)
21/48 Checking commit f29a32d0ff3f (target/arm: Convert VFP VLDR and VSTR to decodetree)
22/48 Checking commit 39361dd5653d (target/arm: Convert the VFP load/store multiple insns to decodetree)
23/48 Checking commit 0235e3c3193c (target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d)
24/48 Checking commit dbf9c663be74 (target/arm: Convert VFP VMLA to decodetree)
25/48 Checking commit 2794fd01a68a (target/arm: Convert VFP VMLS to decodetree)
26/48 Checking commit c483f534cdd3 (target/arm: Convert VFP VNMLS to decodetree)
27/48 Checking commit a4009698528f (target/arm: Convert VFP VNMLA to decodetree)
28/48 Checking commit 1f1b4d995ff5 (target/arm: Convert VMUL to decodetree)
29/48 Checking commit 4419e515ca91 (target/arm: Convert VNMUL to decodetree)
30/48 Checking commit cc1ee821b1e0 (target/arm: Convert VADD to decodetree)
31/48 Checking commit 24c3a8aa7e3f (target/arm: Convert VSUB to decodetree)
32/48 Checking commit e6d14a1389af (target/arm: Convert VDIV to decodetree)
33/48 Checking commit 3b6c2fdb7026 (target/arm: Convert VFP fused multiply-add insns to decodetree)
34/48 Checking commit 627584699a47 (target/arm: Convert VMOV (imm) to decodetree)
35/48 Checking commit b861d4f6fa52 (target/arm: Convert VABS to decodetree)
36/48 Checking commit 6d4705c930fc (target/arm: Convert VNEG to decodetree)
37/48 Checking commit 89a58d122d68 (target/arm: Convert VSQRT to decodetree)
38/48 Checking commit 95c0d1a203d0 (target/arm: Convert VMOV (register) to decodetree)
39/48 Checking commit 117f5724d63e (target/arm: Convert VFP comparison insns to decodetree)
40/48 Checking commit 0c2408844380 (target/arm: Convert the VCVT-from-f16 insns to decodetree)
41/48 Checking commit f0a5e7421125 (target/arm: Convert the VCVT-to-f16 insns to decodetree)
42/48 Checking commit 2caa8efb184d (target/arm: Convert VFP round insns to decodetree)
43/48 Checking commit 555806532f88 (target/arm: Convert double-single precision conversion insns to decodetree)
44/48 Checking commit 1bff1b42c552 (target/arm: Convert integer-to-float insns to decodetree)
45/48 Checking commit 3b5f235346b4 (target/arm: Convert VJCVT to decodetree)
46/48 Checking commit c37ca2f3bfbc (target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree)
47/48 Checking commit ce2285307780 (target/arm: Convert float-to-integer VCVT insns to decodetree)
48/48 Checking commit 926e630776ee (target/arm: Fix short-vector increment behaviour)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190613121433.5246-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
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